[RFC 0/5] support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching

[RFC 0/5] support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching

[Gavin Li]

Previously, VXLAN-GPE in DPDK only supports VNI and next protocol header
fields. This patch series add support for flags and reserved field 0 and
1.

Below is the VXLAN-GPE header defined in the lasted draft.
    0                   1                   2                   3
    0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
   |R|R|Ver|I|P|B|O|       Reserved                |Next Protocol  |
   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
   |                VXLAN Network Identifier (VNI) |   Reserved    |
   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

Gavin Li (5):
  net/mlx5: support VXLAN-GPE flags matching
  app/testpmd: support VXLAN-GPE flags
  net/mlx5: support VXLAN-GPE reserved fields matching
  app/testpmd: support VXLAN-GPE reserved fields
  net/mlx5/hws: support VXLAN-GPE matching

 app/test-pmd/cmdline_flow.c                 |  30 +++++
 doc/guides/nics/mlx5.rst                    |   5 +
 doc/guides/rel_notes/release_24_03.rst      |   6 +
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   3 +
 drivers/net/mlx5/hws/mlx5dr_definer.c       | 117 ++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h       |  13 +++
 drivers/net/mlx5/mlx5_flow.c                |   6 +
 drivers/net/mlx5/mlx5_flow_dv.c             |  32 +++++-
 drivers/net/mlx5/mlx5_flow_hw.c             |   1 +
 9 files changed, 207 insertions(+), 6 deletions(-)

-- 
2.39.1

[RFC 1/5] net/mlx5: support VXLAN-GPE flags matching

[Gavin Li]

This commit adds support for matching on the flags field of VXLAN-GPE
header (the first 8-bits).

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Reviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 85e8c77c81..ffa183dc1b 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -3292,6 +3292,7 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 	struct rte_flow_item_vxlan_gpe nic_mask = {
 		.vni = "\xff\xff\xff",
 		.protocol = 0xff,
+		.flags = 0xff,
 	};
 
 	if (!priv->sh->config.l3_vxlan_en)
-- 
2.39.1

[RFC 2/5] app/testpmd: support VXLAN-GPE flags

[Gavin Li]

Add support for VXLAN-GPE flags field in flow rule pattern to testpmd.

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Reviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 app/test-pmd/cmdline_flow.c                 | 10 ++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  1 +
 2 files changed, 11 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index ce71818705..deb2d80301 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -401,6 +401,7 @@ enum index {
 	ITEM_VXLAN_GPE,
 	ITEM_VXLAN_GPE_VNI,
 	ITEM_VXLAN_GPE_PROTO,
+	ITEM_VXLAN_GPE_FLAGS,
 	ITEM_ARP_ETH_IPV4,
 	ITEM_ARP_ETH_IPV4_SHA,
 	ITEM_ARP_ETH_IPV4_SPA,
@@ -1789,6 +1790,7 @@ static const enum index item_geneve[] = {
 static const enum index item_vxlan_gpe[] = {
 	ITEM_VXLAN_GPE_VNI,
 	ITEM_VXLAN_GPE_PROTO,
+	ITEM_VXLAN_GPE_FLAGS,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -4936,6 +4938,14 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan_gpe,
 					     protocol)),
 	},
+	[ITEM_VXLAN_GPE_FLAGS] = {
+		.name = "flags",
+		.help = "VXLAN-GPE flags",
+		.next = NEXT(item_vxlan_gpe, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan_gpe,
+					     flags)),
+	},
 	[ITEM_ARP_ETH_IPV4] = {
 		.name = "arp_eth_ipv4",
 		.help = "match ARP header for Ethernet/IPv4",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 447e28e694..9c6b04442f 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3703,6 +3703,7 @@ This section lists supported pattern items and their attributes, if any.
 - ``vxlan-gpe``: match VXLAN-GPE header.
 
   - ``vni {unsigned}``: VXLAN-GPE identifier.
+  - ``flags {unsigned}``: VXLAN-GPE flags.
 
 - ``arp_eth_ipv4``: match ARP header for Ethernet/IPv4.
 
-- 
2.39.1

[RFC 3/5] net/mlx5: support VXLAN-GPE reserved fields matching

[Gavin Li]

This adds matching on the reserved fields of VXLAN-GPE header (the 16-bits
before Next Protocol and the last 8-bits).

To support all the header fields, tunnel_header_0_1 should be supported by
FW and misc5_cap is set.

If one of the reserved fields is matched on, misc5 is used for matching.
Otherwise, keep using misc3

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Reviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/mlx5.rst        |  5 +++++
 drivers/net/mlx5/mlx5_flow.c    |  5 +++++
 drivers/net/mlx5/mlx5_flow_dv.c | 32 ++++++++++++++++++++++++++------
 3 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 7bfd6c6aeb..27384d5a86 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -311,6 +311,11 @@ Limitations
   Group zero's behavior may differ which depends on FW.
   Matching value equals 0 (value & mask) is not supported.
 
+- Matching on VXLAN-GPE header fields:
+
+     - ``rsvd0``/``rsvd1`` matching support depends on FW version when using DV flow
+       engine (``dv_flow_en`` = 1).
+
 - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
 
 - MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2).
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index ffa183dc1b..9b6f483d3f 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -3316,6 +3316,11 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  "no outer UDP layer found");
 	if (!mask)
 		mask = &rte_flow_item_vxlan_gpe_mask;
+	if (priv->sh->misc5_cap && priv->sh->tunnel_header_0_1) {
+		nic_mask.rsvd0[0] = 0xff;
+		nic_mask.rsvd0[1] = 0xff;
+		nic_mask.rsvd1 = 0xff;
+	}
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
 		 (const uint8_t *)&nic_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 97f55003c3..f3589da654 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9813,14 +9813,10 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,
 		vxlan_v = vxlan_m;
 	else if (key_type == MLX5_SET_MATCHER_HS_V)
 		vxlan_m = vxlan_v;
-	for (i = 0; i < size; ++i)
-		vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];
 	if (vxlan_m->hdr.flags) {
 		flags_m = vxlan_m->hdr.flags;
 		flags_v = vxlan_v->hdr.flags;
 	}
-	MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,
-		 flags_m & flags_v);
 	m_protocol = vxlan_m->hdr.protocol;
 	v_protocol = vxlan_v->hdr.protocol;
 	if (!m_protocol) {
@@ -9839,8 +9835,32 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,
 		if (key_type & MLX5_SET_MATCHER_M)
 			v_protocol = m_protocol;
 	}
-	MLX5_SET(fte_match_set_misc3, misc_v,
-		 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
+	/*
+	 * If only match flags/protocol/vni field, keep using misc3 for matching.
+	 * If need to match rsvd0 or rsvd1, using misc5 and do not need using misc3.
+	 */
+	if (!(vxlan_m->hdr.rsvd0[0] || vxlan_m->hdr.rsvd0[1] || vxlan_m->hdr.rsvd1)) {
+		for (i = 0; i < size; ++i)
+			vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];
+		MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,
+			 flags_m & flags_v);
+		MLX5_SET(fte_match_set_misc3, misc_v,
+			 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
+	} else {
+		uint32_t tunnel_v;
+		void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+
+		tunnel_v = (flags_m & flags_v) << 24 |
+			   (vxlan_v->hdr.rsvd0[0] & vxlan_m->hdr.rsvd0[0]) << 16 |
+			   (vxlan_v->hdr.rsvd0[1] & vxlan_m->hdr.rsvd0[1]) << 8 |
+			   (m_protocol & v_protocol);
+		MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0, tunnel_v);
+		tunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) << 24 |
+			   (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 16 |
+			   (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 8 |
+			   (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1);
+		MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, tunnel_v);
+	}
 }
 
 /**
-- 
2.39.1

[RFC 4/5] app/testpmd: support VXLAN-GPE reserved fields

[Gavin Li]

Add support for VXLAN-GPE rsvd0 and rsvd1 fields in flow rule pattern to
testpmd

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Reviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 app/test-pmd/cmdline_flow.c                 | 20 ++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index deb2d80301..1d726835e7 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -402,6 +402,8 @@ enum index {
 	ITEM_VXLAN_GPE_VNI,
 	ITEM_VXLAN_GPE_PROTO,
 	ITEM_VXLAN_GPE_FLAGS,
+	ITEM_VXLAN_GPE_RSVD0,
+	ITEM_VXLAN_GPE_RSVD1,
 	ITEM_ARP_ETH_IPV4,
 	ITEM_ARP_ETH_IPV4_SHA,
 	ITEM_ARP_ETH_IPV4_SPA,
@@ -1791,6 +1793,8 @@ static const enum index item_vxlan_gpe[] = {
 	ITEM_VXLAN_GPE_VNI,
 	ITEM_VXLAN_GPE_PROTO,
 	ITEM_VXLAN_GPE_FLAGS,
+	ITEM_VXLAN_GPE_RSVD0,
+	ITEM_VXLAN_GPE_RSVD1,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -4946,6 +4950,22 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan_gpe,
 					     flags)),
 	},
+	[ITEM_VXLAN_GPE_RSVD0] = {
+		.name = "rsvd0",
+		.help = "VXLAN-GPE rsvd0",
+		.next = NEXT(item_vxlan_gpe, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan_gpe,
+					     rsvd0)),
+	},
+	[ITEM_VXLAN_GPE_RSVD1] = {
+		.name = "rsvd1",
+		.help = "VXLAN-GPE rsvd1",
+		.next = NEXT(item_vxlan_gpe, NEXT_ENTRY(COMMON_UNSIGNED),
+			     item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan_gpe,
+					     rsvd1)),
+	},
 	[ITEM_ARP_ETH_IPV4] = {
 		.name = "arp_eth_ipv4",
 		.help = "match ARP header for Ethernet/IPv4",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 9c6b04442f..50fad11fce 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3704,6 +3704,8 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``vni {unsigned}``: VXLAN-GPE identifier.
   - ``flags {unsigned}``: VXLAN-GPE flags.
+  - ``rsvd0 {unsigned}``: VXLAN-GPE reserved field 0.
+  - ``rsvd1 {unsigned}``: VXLAN-GPE reserved field 1.
 
 - ``arp_eth_ipv4``: match ARP header for Ethernet/IPv4.
 
-- 
2.39.1

[RFC 5/5] net/mlx5/hws: support VXLAN-GPE matching

[Gavin Li]

Add support for matching VXLAN-GPE tunnel header.

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Reviewed-by: Itamar Gozlan <igozlan@nvidia.com>
Reviewed-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/rel_notes/release_24_03.rst |   6 ++
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 117 +++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  13 +++
 drivers/net/mlx5/mlx5_flow_hw.c        |   1 +
 4 files changed, 137 insertions(+)

diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 2c0e2930cc..d5e1b1ad37 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -59,6 +59,12 @@ New Features
 
   * Added support for accumulating from src field to dst field.
 
+  * Added support for VXLAN-GPE flags/rsvd0/rsvd fields matching in DV flow
+    engine (``dv_flow_en`` = 1).
+
+  * Added support for VXLAN-GPE matching in HW Steering flow engine
+    (``dv_flow_en`` = 2).
+
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 0b60479406..8958049c8f 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -9,6 +9,7 @@
 #define ETH_TYPE_IPV4_VXLAN	0x0800
 #define ETH_TYPE_IPV6_VXLAN	0x86DD
 #define ETH_VXLAN_DEFAULT_PORT	4789
+#define ETH_VXLAN_GPE_DEFAULT_PORT	4790
 #define IP_UDP_PORT_MPLS	6635
 #define UDP_ROCEV2_PORT	4791
 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)
@@ -167,6 +168,10 @@ struct mlx5dr_definer_conv_data {
 	X(SET,		gtp_ext_hdr_qfi,	v->hdr.qfi,		rte_flow_item_gtp_psc) \
 	X(SET,		vxlan_flags,		v->flags,		rte_flow_item_vxlan) \
 	X(SET,		vxlan_udp_port,		ETH_VXLAN_DEFAULT_PORT,	rte_flow_item_vxlan) \
+	X(SET,		vxlan_gpe_udp_port,	ETH_VXLAN_GPE_DEFAULT_PORT,	rte_flow_item_vxlan_gpe) \
+	X(SET,		vxlan_gpe_flags,	v->flags,		rte_flow_item_vxlan_gpe) \
+	X(SET,		vxlan_gpe_protocol,	v->protocol,		rte_flow_item_vxlan_gpe) \
+	X(SET,		vxlan_gpe_rsvd1,	v->rsvd1,		rte_flow_item_vxlan_gpe) \
 	X(SET,		mpls_udp_port,		IP_UDP_PORT_MPLS,	rte_flow_item_mpls) \
 	X(SET,		source_qp,		v->queue,		mlx5_rte_flow_item_sq) \
 	X(SET,		tag,			v->data,		rte_flow_item_tag) \
@@ -691,6 +696,28 @@ mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,
 	memcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));
 }
 
+static void
+mlx5dr_definer_vxlan_gpe_vni_set(struct mlx5dr_definer_fc *fc,
+				 const void *item_spec,
+				 uint8_t *tag)
+{
+	const struct rte_flow_item_vxlan_gpe *v = item_spec;
+
+	memcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));
+}
+
+static void
+mlx5dr_definer_vxlan_gpe_rsvd0_set(struct mlx5dr_definer_fc *fc,
+				   const void *item_spec,
+				   uint8_t *tag)
+{
+	const struct rte_flow_item_vxlan_gpe *v = item_spec;
+	uint16_t rsvd0;
+
+	rsvd0 = (v->rsvd0[0] << 8 | v->rsvd0[1]);
+	DR_SET(tag, rsvd0, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
 static int
 mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,
 			     struct rte_flow_item *item,
@@ -2385,6 +2412,92 @@ mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd,
+				   struct rte_flow_item *item,
+				   int item_idx)
+{
+	const struct rte_flow_item_vxlan_gpe *m = item->mask;
+	struct mlx5dr_definer_fc *fc;
+	bool inner = cd->tunnel;
+
+	if (inner) {
+		DR_LOG(ERR, "Inner VXLAN GPE item not supported");
+		rte_errno = ENOTSUP;
+		return rte_errno;
+	}
+
+	/* In order to match on VXLAN GPE we must match on ip_protocol and l4_dport */
+	if (!cd->relaxed) {
+		fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];
+		if (!fc->tag_set) {
+			fc->item_idx = item_idx;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			fc->tag_set = &mlx5dr_definer_udp_protocol_set;
+			DR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);
+		}
+
+		fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];
+		if (!fc->tag_set) {
+			fc->item_idx = item_idx;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			fc->tag_set = &mlx5dr_definer_vxlan_gpe_udp_port_set;
+			DR_CALC_SET(fc, eth_l4, destination_port, inner);
+		}
+	}
+
+	if (!m)
+		return 0;
+
+	if (m->flags) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_vxlan_gpe_flags_set;
+		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);
+		fc->bit_mask = __mlx5_mask(header_vxlan_gpe, flags);
+		fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, flags);
+	}
+
+	if (!is_mem_zero(m->rsvd0, 2)) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd0_set;
+		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);
+		fc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd0);
+		fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd0);
+	}
+
+	if (m->protocol) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_vxlan_gpe_protocol_set;
+		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);
+		fc->byte_off += MLX5_BYTE_OFF(header_vxlan_gpe, protocol);
+		fc->bit_mask = __mlx5_mask(header_vxlan_gpe, protocol);
+		fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, protocol);
+	}
+
+	if (!is_mem_zero(m->vni, 3)) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_vxlan_gpe_vni_set;
+		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);
+		fc->bit_mask = __mlx5_mask(header_vxlan_gpe, vni);
+		fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, vni);
+	}
+
+	if (m->rsvd1) {
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1];
+		fc->item_idx = item_idx;
+		fc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd1_set;
+		DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);
+		fc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd1);
+		fc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd1);
+	}
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 				struct mlx5dr_match_template *mt,
@@ -2537,6 +2650,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
+			ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i);
+			item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6f1c99e37a..3dc5f4438d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -91,6 +91,11 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_VPORT_REG_C_0,
 	MLX5DR_DEFINER_FNAME_VXLAN_FLAGS,
 	MLX5DR_DEFINER_FNAME_VXLAN_VNI,
+	MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS,
+	MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0,
+	MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO,
+	MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI,
+	MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1,
 	MLX5DR_DEFINER_FNAME_SOURCE_QP,
 	MLX5DR_DEFINER_FNAME_REG_0,
 	MLX5DR_DEFINER_FNAME_REG_1,
@@ -593,6 +598,14 @@ struct mlx5_ifc_header_vxlan_bits {
 	u8 reserved2[0x8];
 };
 
+struct mlx5_ifc_header_vxlan_gpe_bits {
+	u8 flags[0x8];
+	u8 rsvd0[0x10];
+	u8 protocol[0x8];
+	u8 vni[0x18];
+	u8 rsvd1[0x8];
+};
+
 struct mlx5_ifc_header_gre_bits {
 	union {
 		u8 c_rsvd0_ver[0x10];
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index c4a90a3690..6d8f4f8f8b 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6827,6 +6827,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_GTP:
 		case RTE_FLOW_ITEM_TYPE_GTP_PSC:
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
+		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 		case RTE_FLOW_ITEM_TYPE_MPLS:
 		case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
 		case RTE_FLOW_ITEM_TYPE_GRE:
-- 
2.39.1