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From: Raslan Darawsheh <rasland@mellanox.com>
To: Slava Ovsiienko <viacheslavo@mellanox.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: Matan Azrad <matan@mellanox.com>, Ori Kam <orika@mellanox.com>
Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix Tx doorbell write memory barrier
Date: Mon, 18 Nov 2019 16:25:11 +0000	[thread overview]
Message-ID: <DB3PR0502MB39640C8DB485B18DEDD22B84C24D0@DB3PR0502MB3964.eurprd05.prod.outlook.com> (raw)
In-Reply-To: <1573817706-19322-1-git-send-email-viacheslavo@mellanox.com>

Hi,

> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Sent: Friday, November 15, 2019 1:35 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@mellanox.com>; Raslan Darawsheh
> <rasland@mellanox.com>; Ori Kam <orika@mellanox.com>
> Subject: [PATCH] net/mlx5: fix Tx doorbell write memory barrier
> 
> As the result of testing it was found that some hosts have
> the performance penalty imposed by required write memory barrier
> after doorbell writing. Before 19.08 release there was some
> heuristics to decide whether write memory barrier should be
> performed. For the bursts of recommended size (or multiple)
> it was supposed there were some extra ongoing packets in the
> next burst and write memory barrier may be skipped (supposed
> to be performed in the next burst, at least after descriptor
> writing).
> 
> This patch restores that behaviour, the devargs tx_db_nc=2
> must be specified to engage this performance tuning feature.
> 
> Fixes: 8409a28573d3 ("net/mlx5: control transmit doorbell register mapping")
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

      reply	other threads:[~2019-11-18 16:25 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 11:35 Viacheslav Ovsiienko
2019-11-18 16:25 ` Raslan Darawsheh [this message]

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