DPDK patches and discussions
 help / color / mirror / Atom feed
From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: "Phil Yang (Arm Technology China)" <Phil.Yang@arm.com>,
	"jerinj@marvell.com" <jerinj@marvell.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: "thomas@monjalon.net" <thomas@monjalon.net>,
	"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
	"Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>,
	Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
	nd <nd@arm.com>, "gage.eads@intel.com" <gage.eads@intel.com>,
	nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange
Date: Mon, 24 Jun 2019 16:12:47 +0000	[thread overview]
Message-ID: <VE1PR08MB51498692ECAC3E1081F61D3D98E00@VE1PR08MB5149.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <VE1PR08MB46407A25F7A91A56BC88E757E9E00@VE1PR08MB4640.eurprd08.prod.outlook.com>

<snip>

> > >
> > > Add 128-bit atomic compare exchange on aarch64.
> > >
> > > Signed-off-by: Phil Yang <phil.yang@arm.com>
> > > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > Tested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > ---
> > > This patch depends on 'eal/stack: fix 'pointer-sign' warning'
> > > http://patchwork.dpdk.org/patch/54840/
> > >
> > > +
> > > +#ifdef __ARM_FEATURE_ATOMICS
> > > +static inline rte_int128_t
> > > +__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t
> > > +updated, int mo) {
> >
> > Better to change to "const int mo".
> >
> > > +
> > > +	/* caspX instructions register pair must start from even-numbered
> > > +	 * register at operand 1.
> > > +	 * So, specify registers for local variables here.
> > > +	 */
> > > +	register uint64_t x0 __asm("x0") = (uint64_t)old.val[0];
> > > +	register uint64_t x1 __asm("x1") = (uint64_t)old.val[1];
> > > +	register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];
> > > +	register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];
> > > +
> > > +	if (mo ==  __ATOMIC_RELAXED) {
> > > +		asm volatile(
> > > +				"casp %[old0], %[old1], %[upd0], %[upd1],
> > > [%[dst]]"
> > > +				: [old0] "+r" (x0),
> > > +				  [old1] "+r" (x1)
> > > +				: [upd0] "r" (x2),
> > > +				  [upd1] "r" (x3),
> > > +				  [dst] "r" (dst)
> > > +				: "memory");
> > > +	} else if (mo == __ATOMIC_ACQUIRE) {
> > > +		asm volatile(
> > > +				"caspa %[old0], %[old1], %[upd0], %[upd1],
> > > [%[dst]]"
> > > +				: [old0] "+r" (x0),
> > > +				  [old1] "+r" (x1)
> > > +				: [upd0] "r" (x2),
> > > +				  [upd1] "r" (x3),
> > > +				  [dst] "r" (dst)
> > > +				: "memory");
> > > +	} else if (mo == __ATOMIC_ACQ_REL) {
> > > +		asm volatile(
> > > +				"caspal %[old0], %[old1], %[upd0], %[upd1],
> > > [%[dst]]"
> > > +				: [old0] "+r" (x0),
> > > +				  [old1] "+r" (x1)
> > > +				: [upd0] "r" (x2),
> > > +				  [upd1] "r" (x3),
> > > +				  [dst] "r" (dst)
> > > +				: "memory");
> > > +	} else if (mo == __ATOMIC_RELEASE) {
> > > +		asm volatile(
> > > +				"caspl %[old0], %[old1], %[upd0], %[upd1],
> > > [%[dst]]"
> > > +				: [old0] "+r" (x0),
> > > +				  [old1] "+r" (x1)
> > > +				: [upd0] "r" (x2),
> > > +				  [upd1] "r" (x3),
> > > +				  [dst] "r" (dst)
> > > +				: "memory");
> >
> > I think, This duplication code can be avoid with macro and
> > casp/capsa/casal/caspl as argument.
> >
> > > +	} else {
> > > +		rte_panic("Invalid memory order\n");
> >
> >
> > rte_panic should be removed from library. In this case, I think,
> > invalid mo can go for strongest barrier.
It is added here to capture programming errors. Memory order can be passed during compilation or during run time. 'rte_panic' supports both of these.
Adding code with strongest memory order will mask the programming error.

> >
> > > +	}
> > > +
> > > +	old.val[0] = x0;
> > > +	old.val[1] = x1;
> > > +
> > > +	return old;
> > > +}
> > > +#else

<snip>


  reply	other threads:[~2019-06-24 16:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-24  6:41 Jerin Jacob Kollanukkaran
2019-06-24 15:43 ` Phil Yang (Arm Technology China)
2019-06-24 16:12   ` Honnappa Nagarahalli [this message]
2019-06-24 16:25     ` Thomas Monjalon
2019-06-24 17:41       ` Honnappa Nagarahalli
2019-06-25  6:15         ` Jerin Jacob Kollanukkaran
2019-06-26 10:10           ` Phil Yang (Arm Technology China)
  -- strict thread matches above, loose matches on Subject: below --
2019-06-23  2:41 [dpdk-dev] [PATCH v1 " Phil Yang
2019-06-23  3:15 ` [dpdk-dev] [PATCH v2 " Phil Yang
2019-06-24 14:46   ` Eads, Gage
2019-06-24 15:35     ` Phil Yang (Arm Technology China)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=VE1PR08MB51498692ECAC3E1081F61D3D98E00@VE1PR08MB5149.eurprd08.prod.outlook.com \
    --to=honnappa.nagarahalli@arm.com \
    --cc=Gavin.Hu@arm.com \
    --cc=Phil.Yang@arm.com \
    --cc=dev@dpdk.org \
    --cc=gage.eads@intel.com \
    --cc=hemant.agrawal@nxp.com \
    --cc=jerinj@marvell.com \
    --cc=nd@arm.com \
    --cc=thomas@monjalon.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).