From: David Christensen <drc@linux.vnet.ibm.com>
To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: Olivier Matz <olivier.matz@6wind.com>,
Andrew Rybchenko <arybchenko@solarflare.com>,
"bruce.richardson@intel.com" <bruce.richardson@intel.com>,
"konstantin.ananyev@intel.com" <konstantin.ananyev@intel.com>,
"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
Shahaf Shuler <shahafs@mellanox.com>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
Gavin Hu <gavin.hu@arm.com>,
"viktorin@rehivetech.com" <viktorin@rehivetech.com>,
"anatoly.burakov@intel.com" <anatoly.burakov@intel.com>
Subject: Re: [dpdk-dev] Mbuf memory alignment constraints for (micro)architectures
Date: Wed, 13 Nov 2019 15:08:15 -0800 [thread overview]
Message-ID: <c2b3987a-e66a-d74c-7c5b-4b7c3a12df8c@linux.vnet.ibm.com> (raw)
In-Reply-To: <BYAPR18MB24249DB7169305B7BE0C73F2C8600@BYAPR18MB2424.namprd18.prod.outlook.com>
> # Is PPC and other ARM SoC has formula (B) to compute DRAM channel distribution ? or
> Is it specific to x86? That would define where the hooks needs to added to have proper fix.
The Power 9 chip has eight memory channels, each with a dedicated memory
controller unit (MCU). The MCUs can be configured into one or more
address interleave groups (with 1, 2, 3, 4, 6, or 8 MCUs), with a
programmable interleave granularity of 128B to 32KB. Trying to find
more info on how to access this configuration data and expose it to the
DPDK.
Dave
prev parent reply other threads:[~2019-11-13 23:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-30 18:02 Jerin Jacob Kollanukkaran
2019-11-11 14:01 ` Gavin Hu (Arm Technology China)
2019-11-12 2:36 ` Gavin Hu (Arm Technology China)
2019-11-13 23:08 ` David Christensen [this message]
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