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* [dpdk-stable] [dpdk-dev][PATCH v1 1/1] driver/net/ice sleep in dev_init
@ 2020-09-03 22:25 yanx.fu
  0 siblings, 0 replies; only message in thread
From: yanx.fu @ 2020-09-03 22:25 UTC (permalink / raw)
  To: qi.z.zhang; +Cc: dev, stable, FuYanX

From: FuYanX <yanx.fu@intel.com>

Fix a hardware issue at C0 4 port NIC via fiber.

When ice_driver send resetHW cmd, there is need to wait 100ms,
then the HW functions will be completed. Otherwise, the function
of the port link status will be unstable.

Solution just follow datasheet requirement.
The operating system sets the FLR bit in the Device Control register of the PF.
The operating system is required by PCIe specification to wait 100 ms
before it can assume that the FLR sequence is completed by hardware.

Signed-off-by: FuYanX <yanx.fu@intel.com>
---
 drivers/net/ice/base/ice_common.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 6168fb4f0..f5ea94ece 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -705,6 +705,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
 	if (status)
 		return status;
 
+	/* The driver e.g. vfio-pci may triggle a FLR reset.
+	 * The operating system sets the FLR bit in the Device Control register of the PF.
+	 * The operating system is required by PCIe specification to wait 100 ms
+	 * before it can assume that the FLR sequence is completed by hardware.
+	 */
+	rte_delay_ms(100);
 	hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
 			 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
 		PF_FUNC_RID_FUNCTION_NUMBER_S;
-- 
2.25.1


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2020-09-03 22:25 [dpdk-stable] [dpdk-dev][PATCH v1 1/1] driver/net/ice sleep in dev_init yanx.fu

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