From: Kevin Liu <kevinx.liu@intel.com>
To: dev@dpdk.org
Cc: qiming.yang@intel.com, qi.z.zhang@intel.com,
stevex.yang@intel.com, Kevin Liu <kevinx.liu@intel.com>,
stable@dpdk.org
Subject: [PATCH v2] net/ice: fix Tx Checksum offload
Date: Sun, 12 Dec 2021 14:35:20 +0000 [thread overview]
Message-ID: <20211212143520.2356157-1-kevinx.liu@intel.com> (raw)
In-Reply-To: <20211208095626.85026-1-kevinx.liu@intel.com>
The tunnel packets is missing some information after Tx forwarding.
In ice_txd_enable_offload, when set tunnel packet Tx checksum
offload enable, td_offset should be set with outer l2/l3 len instead
of inner l2/l3 len.
In ice_txd_enable_checksum, td_offset should also be set with outer
l3 len.
This patch fix the bug that the checksum engine can forward Ipv4/Ipv6
tunnel packets.
Fixes: 28f9002ab67f ("net/ice: add Tx AVX512 offload path")
Fixes: 17c7d0f9d6a4 ("net/ice: support basic Rx/Tx")
Cc: stable@dpdk.org
Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
---
v2:
- Refine the title and fix code in ice_txd_enable_checksum.
---
drivers/net/ice/ice_rxtx.c | 41 ++++++++++++++-------
drivers/net/ice/ice_rxtx_vec_common.h | 52 +++++++++++++++++++--------
2 files changed, 66 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index f6d8564ab8..d50acf5391 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -2490,18 +2490,35 @@ ice_txd_enable_checksum(uint64_t ol_flags,
<< ICE_TX_DESC_LEN_MACLEN_S;
/* Enable L3 checksum offloads */
- if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
- *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
- *td_offset |= (tx_offload.l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
- } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
- *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
- *td_offset |= (tx_offload.l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
- } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
- *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
- *td_offset |= (tx_offload.l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
+ /*Tunnel package usage outer len enable L3 checksum offload*/
+ if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
+ if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
+ *td_offset |= (tx_offload.outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
+ *td_offset |= (tx_offload.outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
+ *td_offset |= (tx_offload.outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ }
+ } else {
+ if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
+ *td_offset |= (tx_offload.l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
+ *td_offset |= (tx_offload.l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
+ *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
+ *td_offset |= (tx_offload.l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ }
}
if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
diff --git a/drivers/net/ice/ice_rxtx_vec_common.h b/drivers/net/ice/ice_rxtx_vec_common.h
index dfe60c81d9..8ff01046e1 100644
--- a/drivers/net/ice/ice_rxtx_vec_common.h
+++ b/drivers/net/ice/ice_rxtx_vec_common.h
@@ -364,23 +364,45 @@ ice_txd_enable_offload(struct rte_mbuf *tx_pkt,
uint32_t td_offset = 0;
/* Tx Checksum Offload */
- /* SET MACLEN */
- td_offset |= (tx_pkt->l2_len >> 1) <<
+ /*Tunnel package usage outer len enable L2/L3 checksum offload*/
+ if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
+ /* SET MACLEN */
+ td_offset |= (tx_pkt->outer_l2_len >> 1) <<
ICE_TX_DESC_LEN_MACLEN_S;
- /* Enable L3 checksum offload */
- if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
- td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
- td_offset |= (tx_pkt->l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
- } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
- td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
- td_offset |= (tx_pkt->l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
- } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
- td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
- td_offset |= (tx_pkt->l3_len >> 2) <<
- ICE_TX_DESC_LEN_IPLEN_S;
+ /* Enable L3 checksum offload */
+ if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
+ td_offset |= (tx_pkt->outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
+ td_offset |= (tx_pkt->outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
+ td_offset |= (tx_pkt->outer_l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ }
+ } else {
+ /* SET MACLEN */
+ td_offset |= (tx_pkt->l2_len >> 1) <<
+ ICE_TX_DESC_LEN_MACLEN_S;
+
+ /* Enable L3 checksum offload */
+ if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
+ td_offset |= (tx_pkt->l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
+ td_offset |= (tx_pkt->l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
+ td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
+ td_offset |= (tx_pkt->l3_len >> 2) <<
+ ICE_TX_DESC_LEN_IPLEN_S;
+ }
}
/* Enable L4 checksum offloads */
--
2.33.1
next parent reply other threads:[~2022-01-04 8:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20211208095626.85026-1-kevinx.liu@intel.com>
2021-12-12 14:35 ` Kevin Liu [this message]
2022-01-10 9:36 ` Zhang, Qi Z
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