patch 'net/mlx5: fix Windows build with MinGW GCC 12' has been queued to stable release 21.11.4

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to stable release 21.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/20/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/44bd8ea719ba866395947f99f4aa94cfed7353b1

Thanks.

Kevin

---
From 44bd8ea719ba866395947f99f4aa94cfed7353b1 Mon Sep 17 00:00:00 2001
From: Thomas Monjalon <thomas@monjalon.net>
Date: Thu, 2 Mar 2023 14:21:50 +0100
Subject: [PATCH] net/mlx5: fix Windows build with MinGW GCC 12

[ upstream commit 8ce24f0c8398b1129b64af83d49bf6fa8567c472 ]

With recent changes in Meson and MinGW toolchain,
the driver mlx5 was not able to compile on Linux for Windows.

There were errors due to system detection, non-typed constants,
constant going over int range forbidden in pedantic mode,
and minimum-comparison of different types.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Tal Shnaiderman <talshn@nvidia.com>
---
 drivers/common/mlx5/meson.build             |   9 +-
 drivers/common/mlx5/windows/mlx5_win_defs.h | 100 +++++++++++---------
 2 files changed, 63 insertions(+), 46 deletions(-)

diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build
index 6ddbde7e8f..d969b2a31a 100644
--- a/drivers/common/mlx5/meson.build
+++ b/drivers/common/mlx5/meson.build
@@ -2,7 +2,12 @@
 # Copyright 2019 Mellanox Technologies, Ltd
 
-if not (is_linux or (is_windows and is_ms_linker))
+if not (is_linux or is_windows)
     build = false
-    reason = 'only supported on Linux and Windows build with clang'
+    reason = 'only supported on Linux and Windows'
+    subdir_done()
+endif
+if is_windows and not is_ms_linker and not meson.is_cross_build()
+    build = false
+    reason = 'MinGW is supported only for cross-compilation test'
     subdir_done()
 endif
diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h
index 9f709ff30d..0c09325444 100644
--- a/drivers/common/mlx5/windows/mlx5_win_defs.h
+++ b/drivers/common/mlx5/windows/mlx5_win_defs.h
@@ -3,6 +3,8 @@
  */
 
-#ifndef __MLX5_WIN_DEFS_H__
-#define __MLX5_WIN_DEFS_H__
+#ifndef MLX5_WIN_DEFS_H
+#define MLX5_WIN_DEFS_H
+
+#include <rte_bitops.h>
 
 #ifdef __cplusplus
@@ -45,27 +47,27 @@ enum {
 
 enum mlx5dv_cq_init_attr_mask {
-	MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE	= 1 << 0,
-	MLX5DV_CQ_INIT_ATTR_MASK_FLAGS		= 1 << 1,
-	MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2,
+	MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = RTE_BIT32(0),
+	MLX5DV_CQ_INIT_ATTR_MASK_FLAG           = RTE_BIT32(1),
+	MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE       = RTE_BIT32(2),
 };
 
 enum mlx5dv_cqe_comp_res_format {
-	MLX5DV_CQE_RES_FORMAT_HASH		= 1 << 0,
-	MLX5DV_CQE_RES_FORMAT_CSUM		= 1 << 1,
-	MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX	= 1 << 2,
+	MLX5DV_CQE_RES_FORMAT_HASH        = RTE_BIT32(0),
+	MLX5DV_CQE_RES_FORMAT_CSUM        = RTE_BIT32(1),
+	MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = RTE_BIT32(2),
 };
 
 enum ibv_access_flags {
-	IBV_ACCESS_LOCAL_WRITE		= 1,
-	IBV_ACCESS_REMOTE_WRITE		= 1 << 1,
-	IBV_ACCESS_REMOTE_READ		= 1 << 2,
-	IBV_ACCESS_REMOTE_ATOMIC	= 1 << 3,
-	IBV_ACCESS_MW_BIND		= 1 << 4,
-	IBV_ACCESS_ZERO_BASED		= 1 << 5,
-	IBV_ACCESS_ON_DEMAND		= 1 << 6,
+	IBV_ACCESS_LOCAL_WRITE   = RTE_BIT32(0),
+	IBV_ACCESS_REMOTE_WRITE  = RTE_BIT32(1),
+	IBV_ACCESS_REMOTE_READ   = RTE_BIT32(2),
+	IBV_ACCESS_REMOTE_ATOMIC = RTE_BIT32(3),
+	IBV_ACCESS_MW_BIND       = RTE_BIT32(4),
+	IBV_ACCESS_ZERO_BASED    = RTE_BIT32(5),
+	IBV_ACCESS_ON_DEMAND     = RTE_BIT32(6),
 };
 
 enum mlx5_ib_uapi_devx_create_event_channel_flags {
-	MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,
+	MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = RTE_BIT32(0),
 };
 
@@ -90,13 +92,13 @@ enum {
 
 enum {
-	MLX5_ETH_WQE_L3_CSUM = (1 << 6),
-	MLX5_ETH_WQE_L4_CSUM = (1 << 7),
+	MLX5_ETH_WQE_L3_CSUM = RTE_BIT32(6),
+	MLX5_ETH_WQE_L4_CSUM = RTE_BIT32(7),
 };
 
 enum {
-	MLX5_WQE_CTRL_CQ_UPDATE	= 2 << 2,
-	MLX5_WQE_CTRL_SOLICITED	= 1 << 1,
-	MLX5_WQE_CTRL_FENCE	= 4 << 5,
-	MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5,
+	MLX5_WQE_CTRL_SOLICITED             = RTE_BIT32(1),
+	MLX5_WQE_CTRL_CQ_UPDATE             = RTE_BIT32(3),
+	MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = RTE_BIT32(5),
+	MLX5_WQE_CTRL_FENCE                 = RTE_BIT32(7),
 };
 
@@ -106,4 +108,9 @@ enum {
 };
 
+/* Verbs headers do not support -pedantic. */
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
 /*
  * RX Hash fields enable to set which incoming packet's field should
@@ -115,16 +122,20 @@ enum {
  */
 enum ibv_rx_hash_fields {
-	IBV_RX_HASH_SRC_IPV4	= 1 << 0,
-	IBV_RX_HASH_DST_IPV4	= 1 << 1,
-	IBV_RX_HASH_SRC_IPV6	= 1 << 2,
-	IBV_RX_HASH_DST_IPV6	= 1 << 3,
-	IBV_RX_HASH_SRC_PORT_TCP	= 1 << 4,
-	IBV_RX_HASH_DST_PORT_TCP	= 1 << 5,
-	IBV_RX_HASH_SRC_PORT_UDP	= 1 << 6,
-	IBV_RX_HASH_DST_PORT_UDP	= 1 << 7,
-	IBV_RX_HASH_IPSEC_SPI		= 1 << 8,
-	IBV_RX_HASH_INNER		= (1 << 31),
+	IBV_RX_HASH_SRC_IPV4     = RTE_BIT32(0),
+	IBV_RX_HASH_DST_IPV4     = RTE_BIT32(1),
+	IBV_RX_HASH_SRC_IPV6     = RTE_BIT32(2),
+	IBV_RX_HASH_DST_IPV6     = RTE_BIT32(3),
+	IBV_RX_HASH_SRC_PORT_TCP = RTE_BIT32(4),
+	IBV_RX_HASH_DST_PORT_TCP = RTE_BIT32(5),
+	IBV_RX_HASH_SRC_PORT_UDP = RTE_BIT32(6),
+	IBV_RX_HASH_DST_PORT_UDP = RTE_BIT32(7),
+	IBV_RX_HASH_IPSEC_SPI    = RTE_BIT32(8),
+	IBV_RX_HASH_INNER        = RTE_BIT32(31),
 };
 
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
 enum {
 	MLX5_RCV_DBR	= 0,
@@ -146,7 +157,7 @@ enum {
 
 enum ibv_flow_flags {
-	IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = 1 << 0,
-	IBV_FLOW_ATTR_FLAGS_DONT_TRAP = 1 << 1,
-	IBV_FLOW_ATTR_FLAGS_EGRESS = 1 << 2,
+	IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = RTE_BIT32(0),
+	IBV_FLOW_ATTR_FLAGS_DONT_TRAP = RTE_BIT32(1),
+	IBV_FLOW_ATTR_FLAGS_EGRESS = RTE_BIT32(2),
 };
 
@@ -245,9 +256,9 @@ struct mlx5_wqe_data_seg {
 };
 
-#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP	(1 << 4)
-#define IBV_DEVICE_RAW_IP_CSUM			(1 << 26)
-#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING	(1 << 0)
-#define IBV_RAW_PACKET_CAP_SCATTER_FCS		(1 << 1)
-#define IBV_QPT_RAW_PACKET			8
+#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP   RTE_BIT32(4)
+#define IBV_DEVICE_RAW_IP_CSUM               RTE_BIT32(26)
+#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING   RTE_BIT32(0)
+#define IBV_RAW_PACKET_CAP_SCATTER_FCS       RTE_BIT32(1)
+#define IBV_QPT_RAW_PACKET                   8
 
 enum {
@@ -259,7 +270,8 @@ enum {
 
 enum {
-	MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
-	MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
-	MLX5_MATCH_INNER_HEADERS        = 1 << 2,
+	MLX5_MATCH_OUTER_HEADERS        = RTE_BIT32(0),
+	MLX5_MATCH_MISC_PARAMETERS      = RTE_BIT32(1),
+	MLX5_MATCH_INNER_HEADERS        = RTE_BIT32(2),
 };
-#endif /* __MLX5_WIN_DEFS_H__ */
+
+#endif /* MLX5_WIN_DEFS_H */
-- 
2.39.2

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-03-15 14:30:21.653459810 +0000
+++ 0044-net-mlx5-fix-Windows-build-with-MinGW-GCC-12.patch	2023-03-15 14:30:20.617123811 +0000
@@ -1 +1 @@
-From 8ce24f0c8398b1129b64af83d49bf6fa8567c472 Mon Sep 17 00:00:00 2001
+From 44bd8ea719ba866395947f99f4aa94cfed7353b1 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 8ce24f0c8398b1129b64af83d49bf6fa8567c472 ]
+
@@ -13,2 +14,0 @@
-Cc: stable@dpdk.org
-
@@ -21,2 +21 @@
- drivers/net/mlx5/windows/mlx5_os.c          |   4 +-
- 3 files changed, 65 insertions(+), 48 deletions(-)
+ 2 files changed, 63 insertions(+), 46 deletions(-)
@@ -25 +24 @@
-index 60ccd95cbc..9dc809f192 100644
+index 6ddbde7e8f..d969b2a31a 100644
@@ -44 +43 @@
-index 3554e4a7ff..65da820c5e 100644
+index 9f709ff30d..0c09325444 100644
@@ -57,2 +56,2 @@
- enum {
-@@ -41,27 +43,27 @@ enum {
+ #ifdef __cplusplus
+@@ -45,27 +47,27 @@ enum {
@@ -100 +99 @@
-@@ -86,13 +88,13 @@ enum {
+@@ -90,13 +92,13 @@ enum {
@@ -120 +119 @@
-@@ -102,4 +104,9 @@ enum {
+@@ -106,4 +108,9 @@ enum {
@@ -130 +129 @@
-@@ -111,16 +118,20 @@ enum {
+@@ -115,16 +122,20 @@ enum {
@@ -161 +160 @@
-@@ -142,7 +153,7 @@ enum {
+@@ -146,7 +157,7 @@ enum {
@@ -172 +171 @@
-@@ -241,9 +252,9 @@ struct mlx5_wqe_data_seg {
+@@ -245,9 +256,9 @@ struct mlx5_wqe_data_seg {
@@ -187 +186 @@
-@@ -255,7 +266,8 @@ enum {
+@@ -259,7 +270,8 @@ enum {
@@ -200,13 +198,0 @@
-diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
-index 77f04cc931..f401264b61 100644
---- a/drivers/net/mlx5/windows/mlx5_os.c
-+++ b/drivers/net/mlx5/windows/mlx5_os.c
-@@ -194,6 +194,6 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
- 		 */
- 		sh->dev_cap.ind_table_max_size =
--			RTE_MIN(1 << hca_attr->rss_ind_tbl_cap,
--				(unsigned int)RTE_ETH_RSS_RETA_SIZE_512);
-+			RTE_MIN((uint32_t)1 << hca_attr->rss_ind_tbl_cap,
-+				(uint32_t)RTE_ETH_RSS_RETA_SIZE_512);
- 		DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u",
- 			sh->dev_cap.ind_table_max_size);