From: Christian Ehrhardt <christian.ehrhardt@canonical.com>
To: Ke Zhang <ke1x.zhang@intel.com>
Cc: stable@dpdk.org
Subject: Re: [PATCH 19.11] net/iavf: fix Rx queue interrupt setting
Date: Wed, 3 Aug 2022 11:58:23 +0200 [thread overview]
Message-ID: <CAATJJ0J+U7kaf_qFAFmjgUZz8yVGRDweM0fCkRh0wEevu4mnZg@mail.gmail.com> (raw)
In-Reply-To: <20220720051926.272674-1-ke1x.zhang@intel.com>
On Wed, Jul 20, 2022 at 7:28 AM Ke Zhang <ke1x.zhang@intel.com> wrote:
>
> [ upstream commit a08f9cb698c3d4687765860e328dca727f7a516b ]
Thank you,
your patch was too late in regard to my original deadline and I was
then unavailable for a while.
In the meantime more patches came in and I do not want to waste any of
them just because they were late.
Your patch is applied to the WIP branch now, but currently testing of
-rc1 is going on which I do not want to disrupt.
If we need an -rc2 anyway or generally have the time to do an -rc2
without too much disruption it will be in 19.11.13, otherwise it is
already queued for 19.11.14
> For Rx-Queue Interrupt Setting, when vf rx interrupt
> disable(INTENA=0), there are two ways to write back
> descriptor to host memory:
>
> 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
> Completed descriptors are posted to host memory according to
> the internal descriptor cache policy (in other words when a
> full cache line is available for write-back).
>
> A internal descriptor size is 16 bytes or 32 bytes, a cache
> line size is 64 bytes or 128 bytes from datasheet :
> PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO)
> so the full cache line could contains 4 packets, it means
> Network card will send 4 packets to host when a full cache line
> is available.
>
> 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
> Completed descriptors also trigger the ITR. Following ITR
> expiration, all leftover completed descriptors are posted to
> host memory.
>
> Network card will send packet to host even if only one
> descriptor is completed.
>
> Changing 1) to 2) to make sure VF send the packet to host even
> if there is only one rx packet is ready in hardware.
>
> Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
> Cc: stable@dpdk.org
>
> Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
> ---
> drivers/net/iavf/iavf_ethdev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
> index 3cb02bd1f..00a47bf13 100644
> --- a/drivers/net/iavf/iavf_ethdev.c
> +++ b/drivers/net/iavf/iavf_ethdev.c
> @@ -1209,7 +1209,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
>
> IAVF_WRITE_REG(hw,
> IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
> - 0);
> + IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
>
> IAVF_WRITE_FLUSH(hw);
> return 0;
> --
> 2.25.1
>
--
Christian Ehrhardt
Senior Staff Engineer, Ubuntu Server
Canonical Ltd
next prev parent reply other threads:[~2022-08-03 9:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-20 5:19 Ke Zhang
2022-08-03 9:58 ` Christian Ehrhardt [this message]
2022-08-03 11:40 ` Ali Alnubani
2022-08-03 12:15 ` Christian Ehrhardt
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