From: Shreyansh Jain <shreyansh.jain@nxp.com>
To: <dev@dpdk.org>
Cc: <ferruh.yigit@intel.com>, <hemant.agrawal@nxp.com>
Subject: [dpdk-dev] [PATCH v5 10/40] bus/dpaa: add QMAN interface driver
Date: Thu, 28 Sep 2017 17:03:14 +0530 [thread overview]
Message-ID: <20170928113344.12248-11-shreyansh.jain@nxp.com> (raw)
In-Reply-To: <20170928113344.12248-1-shreyansh.jain@nxp.com>
The Queue Manager (QMan) is a hardware queue management block that
allows software and accelerators on the datapath to enqueue and dequeue
frames in order to communicate.
This part of QBMAN DPAA Block.
Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
---
drivers/bus/dpaa/Makefile | 1 +
drivers/bus/dpaa/base/qbman/qman_driver.c | 271 +++++++
drivers/bus/dpaa/base/qbman/qman_priv.h | 303 +++++++
drivers/bus/dpaa/include/fsl_qman.h | 1254 +++++++++++++++++++++++++++++
drivers/bus/dpaa/include/fsl_usd.h | 13 +
5 files changed, 1842 insertions(+)
create mode 100644 drivers/bus/dpaa/base/qbman/qman_driver.c
create mode 100644 drivers/bus/dpaa/base/qbman/qman_priv.h
create mode 100644 drivers/bus/dpaa/include/fsl_qman.h
diff --git a/drivers/bus/dpaa/Makefile b/drivers/bus/dpaa/Makefile
index 5b76a4b..c9c15f8 100644
--- a/drivers/bus/dpaa/Makefile
+++ b/drivers/bus/dpaa/Makefile
@@ -63,6 +63,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \
base/fman/of.c \
base/fman/netcfg_layer.c \
base/qbman/process.c \
+ base/qbman/qman_driver.c \
base/qbman/dpaa_sys.c
# Link Pthread
diff --git a/drivers/bus/dpaa/base/qbman/qman_driver.c b/drivers/bus/dpaa/base/qbman/qman_driver.c
new file mode 100644
index 0000000..80dde20
--- /dev/null
+++ b/drivers/bus/dpaa/base/qbman/qman_driver.c
@@ -0,0 +1,271 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2008-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <fsl_usd.h>
+#include <process.h>
+#include "qman_priv.h"
+#include <sys/ioctl.h>
+#include <rte_branch_prediction.h>
+
+/* Global variable containing revision id (even on non-control plane systems
+ * where CCSR isn't available).
+ */
+u16 qman_ip_rev;
+u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
+u16 qm_channel_caam = QMAN_CHANNEL_CAAM;
+u16 qm_channel_pme = QMAN_CHANNEL_PME;
+
+/* Ccsr map address to access ccsrbased register */
+void *qman_ccsr_map;
+/* The qman clock frequency */
+u32 qman_clk;
+
+static __thread int fd = -1;
+static __thread struct qm_portal_config pcfg;
+static __thread struct dpaa_ioctl_portal_map map = {
+ .type = dpaa_portal_qman
+};
+
+static int fsl_qman_portal_init(uint32_t index, int is_shared)
+{
+ cpu_set_t cpuset;
+ int loop, ret;
+ struct dpaa_ioctl_irq_map irq_map;
+
+ /* Verify the thread's cpu-affinity */
+ ret = pthread_getaffinity_np(pthread_self(), sizeof(cpu_set_t),
+ &cpuset);
+ if (ret) {
+ error(0, ret, "pthread_getaffinity_np()");
+ return ret;
+ }
+ pcfg.cpu = -1;
+ for (loop = 0; loop < CPU_SETSIZE; loop++)
+ if (CPU_ISSET(loop, &cpuset)) {
+ if (pcfg.cpu != -1) {
+ pr_err("Thread is not affine to 1 cpu\n");
+ return -EINVAL;
+ }
+ pcfg.cpu = loop;
+ }
+ if (pcfg.cpu == -1) {
+ pr_err("Bug in getaffinity handling!\n");
+ return -EINVAL;
+ }
+
+ /* Allocate and map a qman portal */
+ map.index = index;
+ ret = process_portal_map(&map);
+ if (ret) {
+ error(0, ret, "process_portal_map()");
+ return ret;
+ }
+ pcfg.channel = map.channel;
+ pcfg.pools = map.pools;
+ pcfg.index = map.index;
+
+ /* Make the portal's cache-[enabled|inhibited] regions */
+ pcfg.addr_virt[DPAA_PORTAL_CE] = map.addr.cena;
+ pcfg.addr_virt[DPAA_PORTAL_CI] = map.addr.cinh;
+
+ fd = open(QMAN_PORTAL_IRQ_PATH, O_RDONLY);
+ if (fd == -1) {
+ pr_err("QMan irq init failed\n");
+ process_portal_unmap(&map.addr);
+ return -EBUSY;
+ }
+
+ pcfg.is_shared = is_shared;
+ pcfg.node = NULL;
+ pcfg.irq = fd;
+
+ irq_map.type = dpaa_portal_qman;
+ irq_map.portal_cinh = map.addr.cinh;
+ process_portal_irq_map(fd, &irq_map);
+ return 0;
+}
+
+static int fsl_qman_portal_finish(void)
+{
+ int ret;
+
+ process_portal_irq_unmap(fd);
+
+ ret = process_portal_unmap(&map.addr);
+ if (ret)
+ error(0, ret, "process_portal_unmap()");
+ return ret;
+}
+
+int qman_thread_init(void)
+{
+ /* Convert from contiguous/virtual cpu numbering to real cpu when
+ * calling into the code that is dependent on the device naming.
+ */
+ return fsl_qman_portal_init(QBMAN_ANY_PORTAL_IDX, 0);
+}
+
+int qman_thread_finish(void)
+{
+ return fsl_qman_portal_finish();
+}
+
+void qman_thread_irq(void)
+{
+ qbman_invoke_irq(pcfg.irq);
+
+ /* Now we need to uninhibit interrupts. This is the only code outside
+ * the regular portal driver that manipulates any portal register, so
+ * rather than breaking that encapsulation I am simply hard-coding the
+ * offset to the inhibit register here.
+ */
+ out_be32(pcfg.addr_virt[DPAA_PORTAL_CI] + 0xe0c, 0);
+}
+
+int qman_global_init(void)
+{
+ const struct device_node *dt_node;
+ int ret = 0;
+ size_t lenp;
+ const u32 *chanid;
+ static int ccsr_map_fd;
+ const uint32_t *qman_addr;
+ uint64_t phys_addr;
+ uint64_t regs_size;
+ const u32 *clk;
+
+ static int done;
+
+ if (done)
+ return -EBUSY;
+
+ /* Use the device-tree to determine IP revision until something better
+ * is devised.
+ */
+ dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman-portal");
+ if (!dt_node) {
+ pr_err("No qman portals available for any CPU\n");
+ return -ENODEV;
+ }
+ if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.0") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-1.0.0"))
+ pr_err("QMan rev1.0 on P4080 rev1 is not supported!\n");
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.1") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-1.1.0"))
+ qman_ip_rev = QMAN_REV11;
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-1.2") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-1.2.0"))
+ qman_ip_rev = QMAN_REV12;
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-2.0") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-2.0.0"))
+ qman_ip_rev = QMAN_REV20;
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.0") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-3.0.1"))
+ qman_ip_rev = QMAN_REV30;
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.0") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.1") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.2") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-3.1.3"))
+ qman_ip_rev = QMAN_REV31;
+ else if (of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.0") ||
+ of_device_is_compatible(dt_node, "fsl,qman-portal-3.2.1"))
+ qman_ip_rev = QMAN_REV32;
+ else
+ qman_ip_rev = QMAN_REV11;
+
+ if (!qman_ip_rev) {
+ pr_err("Unknown qman portal version\n");
+ return -ENODEV;
+ }
+ if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) {
+ qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
+ qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
+ qm_channel_pme = QMAN_CHANNEL_PME_REV3;
+ }
+
+ dt_node = of_find_compatible_node(NULL, NULL, "fsl,pool-channel-range");
+ if (!dt_node) {
+ pr_err("No qman pool channel range available\n");
+ return -ENODEV;
+ }
+ chanid = of_get_property(dt_node, "fsl,pool-channel-range", &lenp);
+ if (!chanid) {
+ pr_err("Can not get pool-channel-range property\n");
+ return -EINVAL;
+ }
+
+ /* get ccsr base */
+ dt_node = of_find_compatible_node(NULL, NULL, "fsl,qman");
+ if (!dt_node) {
+ pr_err("No qman device node available\n");
+ return -ENODEV;
+ }
+ qman_addr = of_get_address(dt_node, 0, ®s_size, NULL);
+ if (!qman_addr) {
+ pr_err("of_get_address cannot return qman address\n");
+ return -EINVAL;
+ }
+ phys_addr = of_translate_address(dt_node, qman_addr);
+ if (!phys_addr) {
+ pr_err("of_translate_address failed\n");
+ return -EINVAL;
+ }
+
+ ccsr_map_fd = open("/dev/mem", O_RDWR);
+ if (unlikely(ccsr_map_fd < 0)) {
+ pr_err("Can not open /dev/mem for qman ccsr map\n");
+ return ccsr_map_fd;
+ }
+
+ qman_ccsr_map = mmap(NULL, regs_size, PROT_READ | PROT_WRITE,
+ MAP_SHARED, ccsr_map_fd, phys_addr);
+ if (qman_ccsr_map == MAP_FAILED) {
+ pr_err("Can not map qman ccsr base\n");
+ return -EINVAL;
+ }
+
+ clk = of_get_property(dt_node, "clock-frequency", NULL);
+ if (!clk)
+ pr_warn("Can't find Qman clock frequency\n");
+ else
+ qman_clk = be32_to_cpu(*clk);
+
+ return ret;
+}
diff --git a/drivers/bus/dpaa/base/qbman/qman_priv.h b/drivers/bus/dpaa/base/qbman/qman_priv.h
new file mode 100644
index 0000000..4a11e40
--- /dev/null
+++ b/drivers/bus/dpaa/base/qbman/qman_priv.h
@@ -0,0 +1,303 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2008-2016 Freescale Semiconductor Inc.
+ * Copyright 2017 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __QMAN_PRIV_H
+#define __QMAN_PRIV_H
+
+#include "dpaa_sys.h"
+#include <fsl_qman.h>
+
+/* Congestion Groups */
+/*
+ * This wrapper represents a bit-array for the state of the 256 QMan congestion
+ * groups. Is also used as a *mask* for congestion groups, eg. so we ignore
+ * those that don't concern us. We harness the structure and accessor details
+ * already used in the management command to query congestion groups.
+ */
+struct qman_cgrs {
+ struct __qm_mcr_querycongestion q;
+};
+
+static inline void qman_cgrs_init(struct qman_cgrs *c)
+{
+ memset(c, 0, sizeof(*c));
+}
+
+static inline void qman_cgrs_fill(struct qman_cgrs *c)
+{
+ memset(c, 0xff, sizeof(*c));
+}
+
+static inline int qman_cgrs_get(struct qman_cgrs *c, int num)
+{
+ return QM_MCR_QUERYCONGESTION(&c->q, num);
+}
+
+static inline void qman_cgrs_set(struct qman_cgrs *c, int num)
+{
+ c->q.state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num));
+}
+
+static inline void qman_cgrs_unset(struct qman_cgrs *c, int num)
+{
+ c->q.state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num));
+}
+
+static inline int qman_cgrs_next(struct qman_cgrs *c, int num)
+{
+ while ((++num < (int)__CGR_NUM) && !qman_cgrs_get(c, num))
+ ;
+ return num;
+}
+
+static inline void qman_cgrs_cp(struct qman_cgrs *dest,
+ const struct qman_cgrs *src)
+{
+ memcpy(dest, src, sizeof(*dest));
+}
+
+static inline void qman_cgrs_and(struct qman_cgrs *dest,
+ const struct qman_cgrs *a,
+ const struct qman_cgrs *b)
+{
+ int ret;
+ u32 *_d = dest->q.state;
+ const u32 *_a = a->q.state;
+ const u32 *_b = b->q.state;
+
+ for (ret = 0; ret < 8; ret++)
+ *(_d++) = *(_a++) & *(_b++);
+}
+
+static inline void qman_cgrs_xor(struct qman_cgrs *dest,
+ const struct qman_cgrs *a,
+ const struct qman_cgrs *b)
+{
+ int ret;
+ u32 *_d = dest->q.state;
+ const u32 *_a = a->q.state;
+ const u32 *_b = b->q.state;
+
+ for (ret = 0; ret < 8; ret++)
+ *(_d++) = *(_a++) ^ *(_b++);
+}
+
+/* used by CCSR and portal interrupt code */
+enum qm_isr_reg {
+ qm_isr_status = 0,
+ qm_isr_enable = 1,
+ qm_isr_disable = 2,
+ qm_isr_inhibit = 3
+};
+
+struct qm_portal_config {
+ /*
+ * Corenet portal addresses;
+ * [0]==cache-enabled, [1]==cache-inhibited.
+ */
+ void __iomem *addr_virt[2];
+ struct device_node *node;
+ /* Allow these to be joined in lists */
+ struct list_head list;
+ /* User-visible portal configuration settings */
+ /* If the caller enables DQRR stashing (and thus wishes to operate the
+ * portal from only one cpu), this is the logical CPU that the portal
+ * will stash to. Whether stashing is enabled or not, this setting is
+ * also used for any "core-affine" portals, ie. default portals
+ * associated to the corresponding cpu. -1 implies that there is no
+ * core affinity configured.
+ */
+ int cpu;
+ /* portal interrupt line */
+ int irq;
+ /* the unique index of this portal */
+ u32 index;
+ /* Is this portal shared? (If so, it has coarser locking and demuxes
+ * processing on behalf of other CPUs.).
+ */
+ int is_shared;
+ /* The portal's dedicated channel id, use this value for initialising
+ * frame queues to target this portal when scheduled.
+ */
+ u16 channel;
+ /* A mask of which pool channels this portal has dequeue access to
+ * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask).
+ */
+ u32 pools;
+
+};
+
+/* Revision info (for errata and feature handling) */
+#define QMAN_REV11 0x0101
+#define QMAN_REV12 0x0102
+#define QMAN_REV20 0x0200
+#define QMAN_REV30 0x0300
+#define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
+extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
+extern u32 qman_clk;
+
+int qm_set_wpm(int wpm);
+int qm_get_wpm(int *wpm);
+
+struct qman_portal *qman_create_affine_portal(
+ const struct qm_portal_config *config,
+ const struct qman_cgrs *cgrs);
+const struct qm_portal_config *qman_destroy_affine_portal(void);
+
+struct qm_portal_config *qm_get_unused_portal(void);
+struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx);
+
+void qm_put_unused_portal(struct qm_portal_config *pcfg);
+void qm_set_liodns(struct qm_portal_config *pcfg);
+
+/* This CGR feature is supported by h/w and required by unit-tests and the
+ * debugfs hooks, so is implemented in the driver. However it allows an explicit
+ * corruption of h/w fields by s/w that are usually incorruptible (because the
+ * counters are usually maintained entirely within h/w). As such, we declare
+ * this API internally.
+ */
+int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
+ struct qm_mcr_cgrtestwrite *result);
+
+/* QMan s/w corenet portal, low-level i/face */
+
+/*
+ * For Choose one SOURCE. Choose one COUNT. Choose one
+ * dequeue TYPE. Choose TOKEN (8-bit).
+ * If SOURCE == CHANNELS,
+ * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
+ * You can choose DEDICATED_PRECEDENCE if the portal channel should have
+ * priority.
+ * If SOURCE == SPECIFICWQ,
+ * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
+ * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
+ * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
+ * same value.
+ */
+#define QM_SDQCR_SOURCE_CHANNELS 0x0
+#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
+#define QM_SDQCR_COUNT_EXACT1 0x0
+#define QM_SDQCR_COUNT_UPTO3 0x20000000
+#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
+#define QM_SDQCR_TYPE_MASK 0x03000000
+#define QM_SDQCR_TYPE_NULL 0x0
+#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
+#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
+#define QM_SDQCR_TYPE_ACTIVE 0x03000000
+#define QM_SDQCR_TOKEN_MASK 0x00ff0000
+#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
+#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
+#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
+#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
+#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
+#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
+#define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
+
+#define QM_VDQCR_FQID_MASK 0x00ffffff
+#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
+
+#define QM_EQCR_VERB_VBIT 0x80
+#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
+#define QM_EQCR_VERB_CMD_ENQUEUE 0x01
+#define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */
+#define QM_EQCR_VERB_COLOUR_GREEN 0x00
+#define QM_EQCR_VERB_COLOUR_YELLOW 0x08
+#define QM_EQCR_VERB_COLOUR_RED 0x10
+#define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18
+#define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */
+#define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */
+#define QM_EQCR_DCA_ENABLE 0x80
+#define QM_EQCR_DCA_PARK 0x40
+#define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */
+#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
+#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
+#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
+#define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */
+
+#define QM_MCC_VERB_VBIT 0x80
+#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
+#define QM_MCC_VERB_INITFQ_PARKED 0x40
+#define QM_MCC_VERB_INITFQ_SCHED 0x41
+#define QM_MCC_VERB_QUERYFQ 0x44
+#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
+#define QM_MCC_VERB_QUERYWQ 0x46
+#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
+#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
+#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
+#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
+#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
+#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
+#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
+#define QM_MCC_VERB_INITCGR 0x50
+#define QM_MCC_VERB_MODIFYCGR 0x51
+#define QM_MCC_VERB_CGRTESTWRITE 0x52
+#define QM_MCC_VERB_QUERYCGR 0x58
+#define QM_MCC_VERB_QUERYCONGESTION 0x59
+
+/*
+ * Used by all portal interrupt registers except 'inhibit'
+ * Channels with frame availability
+ */
+#define QM_PIRQ_DQAVAIL 0x0000ffff
+
+/* The DQAVAIL interrupt fields break down into these bits; */
+#define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
+#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
+#define QM_DQAVAIL_MASK 0xffff
+/* This mask contains all the "irqsource" bits visible to API users */
+#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
+
+/* These are qm_<reg>_<verb>(). So for example, qm_disable_write() means "write
+ * the disable register" rather than "disable the ability to write".
+ */
+#define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status)
+#define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m)
+#define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable)
+#define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v)
+#define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable)
+#define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v)
+/* TODO: unfortunate name-clash here, reword? */
+#define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1)
+#define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0)
+
+#define QMAN_PORTAL_IRQ_PATH "/dev/fsl-usdpaa-irq"
+
+#endif /* _QMAN_PRIV_H */
diff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h
new file mode 100644
index 0000000..784fe60
--- /dev/null
+++ b/drivers/bus/dpaa/include/fsl_qman.h
@@ -0,0 +1,1254 @@
+/*-
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * BSD LICENSE
+ *
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_QMAN_H
+#define __FSL_QMAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <dpaa_rbtree.h>
+
+/* Last updated for v00.800 of the BG */
+
+/* Hardware constants */
+#define QM_CHANNEL_SWPORTAL0 0
+#define QMAN_CHANNEL_POOL1 0x21
+#define QMAN_CHANNEL_CAAM 0x80
+#define QMAN_CHANNEL_PME 0xa0
+#define QMAN_CHANNEL_POOL1_REV3 0x401
+#define QMAN_CHANNEL_CAAM_REV3 0x840
+#define QMAN_CHANNEL_PME_REV3 0x860
+extern u16 qm_channel_pool1;
+extern u16 qm_channel_caam;
+extern u16 qm_channel_pme;
+enum qm_dc_portal {
+ qm_dc_portal_fman0 = 0,
+ qm_dc_portal_fman1 = 1,
+ qm_dc_portal_caam = 2,
+ qm_dc_portal_pme = 3
+};
+
+/* Portal processing (interrupt) sources */
+#define QM_PIRQ_CCSCI 0x00200000 /* CEETM Congestion State Change */
+#define QM_PIRQ_CSCI 0x00100000 /* Congestion State Change */
+#define QM_PIRQ_EQCI 0x00080000 /* Enqueue Command Committed */
+#define QM_PIRQ_EQRI 0x00040000 /* EQCR Ring (below threshold) */
+#define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */
+#define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */
+/*
+ * This mask contains all the interrupt sources that need handling except DQRI,
+ * ie. that if present should trigger slow-path processing.
+ */
+#define QM_PIRQ_SLOW (QM_PIRQ_CSCI | QM_PIRQ_EQCI | QM_PIRQ_EQRI | \
+ QM_PIRQ_MRI | QM_PIRQ_CCSCI)
+
+/* For qman_static_dequeue_*** APIs */
+#define QM_SDQCR_CHANNELS_POOL_MASK 0x00007fff
+/* for n in [1,15] */
+#define QM_SDQCR_CHANNELS_POOL(n) (0x00008000 >> (n))
+/* for conversion from n of qm_channel */
+static inline u32 QM_SDQCR_CHANNELS_POOL_CONV(u16 channel)
+{
+ return QM_SDQCR_CHANNELS_POOL(channel + 1 - qm_channel_pool1);
+}
+
+/* For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
+ * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
+ * FQID(n) to fill in the frame queue ID.
+ */
+#define QM_VDQCR_PRECEDENCE_VDQCR 0x0
+#define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000
+#define QM_VDQCR_EXACT 0x40000000
+#define QM_VDQCR_NUMFRAMES_MASK 0x3f000000
+#define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24)
+#define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f)
+#define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0)
+
+/* --- QMan data structures (and associated constants) --- */
+
+/* Represents s/w corenet portal mapped data structures */
+struct qm_eqcr_entry; /* EQCR (EnQueue Command Ring) entries */
+struct qm_dqrr_entry; /* DQRR (DeQueue Response Ring) entries */
+struct qm_mr_entry; /* MR (Message Ring) entries */
+struct qm_mc_command; /* MC (Management Command) command */
+struct qm_mc_result; /* MC result */
+
+#define QM_FD_FORMAT_SG 0x4
+#define QM_FD_FORMAT_LONG 0x2
+#define QM_FD_FORMAT_COMPOUND 0x1
+enum qm_fd_format {
+ /*
+ * 'contig' implies a contiguous buffer, whereas 'sg' implies a
+ * scatter-gather table. 'big' implies a 29-bit length with no offset
+ * field, otherwise length is 20-bit and offset is 9-bit. 'compound'
+ * implies a s/g-like table, where each entry itself represents a frame
+ * (contiguous or scatter-gather) and the 29-bit "length" is
+ * interpreted purely for congestion calculations, ie. a "congestion
+ * weight".
+ */
+ qm_fd_contig = 0,
+ qm_fd_contig_big = QM_FD_FORMAT_LONG,
+ qm_fd_sg = QM_FD_FORMAT_SG,
+ qm_fd_sg_big = QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG,
+ qm_fd_compound = QM_FD_FORMAT_COMPOUND
+};
+
+/* Capitalised versions are un-typed but can be used in static expressions */
+#define QM_FD_CONTIG 0
+#define QM_FD_CONTIG_BIG QM_FD_FORMAT_LONG
+#define QM_FD_SG QM_FD_FORMAT_SG
+#define QM_FD_SG_BIG (QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG)
+#define QM_FD_COMPOUND QM_FD_FORMAT_COMPOUND
+
+/* "Frame Descriptor (FD)" */
+struct qm_fd {
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 dd:2; /* dynamic debug */
+ u8 liodn_offset:6;
+ u8 bpid:8; /* Buffer Pool ID */
+ u8 eliodn_offset:4;
+ u8 __reserved:4;
+ u8 addr_hi; /* high 8-bits of 40-bit address */
+ u32 addr_lo; /* low 32-bits of 40-bit address */
+#else
+ u8 liodn_offset:6;
+ u8 dd:2; /* dynamic debug */
+ u8 bpid:8; /* Buffer Pool ID */
+ u8 __reserved:4;
+ u8 eliodn_offset:4;
+ u8 addr_hi; /* high 8-bits of 40-bit address */
+ u32 addr_lo; /* low 32-bits of 40-bit address */
+#endif
+ };
+ struct {
+ u64 __notaddress:24;
+ /* More efficient address accessor */
+ u64 addr:40;
+ };
+ u64 opaque_addr;
+ };
+ /* The 'format' field indicates the interpretation of the remaining 29
+ * bits of the 32-bit word. For packing reasons, it is duplicated in the
+ * other union elements. Note, union'd structs are difficult to use with
+ * static initialisation under gcc, in which case use the "opaque" form
+ * with one of the macros.
+ */
+ union {
+ /* For easier/faster copying of this part of the fd (eg. from a
+ * DQRR entry to an EQCR entry) copy 'opaque'
+ */
+ u32 opaque;
+ /* If 'format' is _contig or _sg, 20b length and 9b offset */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ enum qm_fd_format format:3;
+ u16 offset:9;
+ u32 length20:20;
+#else
+ u32 length20:20;
+ u16 offset:9;
+ enum qm_fd_format format:3;
+#endif
+ };
+ /* If 'format' is _contig_big or _sg_big, 29b length */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ enum qm_fd_format _format1:3;
+ u32 length29:29;
+#else
+ u32 length29:29;
+ enum qm_fd_format _format1:3;
+#endif
+ };
+ /* If 'format' is _compound, 29b "congestion weight" */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ enum qm_fd_format _format2:3;
+ u32 cong_weight:29;
+#else
+ u32 cong_weight:29;
+ enum qm_fd_format _format2:3;
+#endif
+ };
+ };
+ union {
+ u32 cmd;
+ u32 status;
+ };
+} __attribute__((aligned(8)));
+#define QM_FD_DD_NULL 0x00
+#define QM_FD_PID_MASK 0x3f
+static inline u64 qm_fd_addr_get64(const struct qm_fd *fd)
+{
+ return fd->addr;
+}
+
+static inline dma_addr_t qm_fd_addr(const struct qm_fd *fd)
+{
+ return (dma_addr_t)fd->addr;
+}
+
+/* Macro, so we compile better if 'v' isn't always 64-bit */
+#define qm_fd_addr_set64(fd, v) \
+ do { \
+ struct qm_fd *__fd931 = (fd); \
+ __fd931->addr = v; \
+ } while (0)
+
+/* Scatter/Gather table entry */
+struct qm_sg_entry {
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 __reserved1[3];
+ u8 addr_hi; /* high 8-bits of 40-bit address */
+ u32 addr_lo; /* low 32-bits of 40-bit address */
+#else
+ u32 addr_lo; /* low 32-bits of 40-bit address */
+ u8 addr_hi; /* high 8-bits of 40-bit address */
+ u8 __reserved1[3];
+#endif
+ };
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u64 __notaddress:24;
+ u64 addr:40;
+#else
+ u64 addr:40;
+ u64 __notaddress:24;
+#endif
+ };
+ u64 opaque;
+ };
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u32 extension:1; /* Extension bit */
+ u32 final:1; /* Final bit */
+ u32 length:30;
+#else
+ u32 length:30;
+ u32 final:1; /* Final bit */
+ u32 extension:1; /* Extension bit */
+#endif
+ };
+ u32 val;
+ };
+ u8 __reserved2;
+ u8 bpid;
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 __reserved3:3;
+ u16 offset:13;
+#else
+ u16 offset:13;
+ u16 __reserved3:3;
+#endif
+ };
+ u16 val_off;
+ };
+} __packed;
+static inline u64 qm_sg_entry_get64(const struct qm_sg_entry *sg)
+{
+ return sg->addr;
+}
+
+static inline dma_addr_t qm_sg_addr(const struct qm_sg_entry *sg)
+{
+ return (dma_addr_t)sg->addr;
+}
+
+/* Macro, so we compile better if 'v' isn't always 64-bit */
+#define qm_sg_entry_set64(sg, v) \
+ do { \
+ struct qm_sg_entry *__sg931 = (sg); \
+ __sg931->addr = v; \
+ } while (0)
+
+/* See 1.5.8.1: "Enqueue Command" */
+struct qm_eqcr_entry {
+ u8 __dont_write_directly__verb;
+ u8 dca;
+ u16 seqnum;
+ u32 orp; /* 24-bit */
+ u32 fqid; /* 24-bit */
+ u32 tag;
+ struct qm_fd fd;
+ u8 __reserved3[32];
+} __packed;
+
+
+/* "Frame Dequeue Response" */
+struct qm_dqrr_entry {
+ u8 verb;
+ u8 stat;
+ u16 seqnum; /* 15-bit */
+ u8 tok;
+ u8 __reserved2[3];
+ u32 fqid; /* 24-bit */
+ u32 contextB;
+ struct qm_fd fd;
+ u8 __reserved4[32];
+};
+
+#define QM_DQRR_VERB_VBIT 0x80
+#define QM_DQRR_VERB_MASK 0x7f /* where the verb contains; */
+#define QM_DQRR_VERB_FRAME_DEQUEUE 0x60 /* "this format" */
+#define QM_DQRR_STAT_FQ_EMPTY 0x80 /* FQ empty */
+#define QM_DQRR_STAT_FQ_HELDACTIVE 0x40 /* FQ held active */
+#define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */
+#define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */
+#define QM_DQRR_STAT_UNSCHEDULED 0x02 /* Unscheduled dequeue */
+#define QM_DQRR_STAT_DQCR_EXPIRED 0x01 /* VDQCR or PDQCR expired*/
+
+
+/* "ERN Message Response" */
+/* "FQ State Change Notification" */
+struct qm_mr_entry {
+ u8 verb;
+ union {
+ struct {
+ u8 dca;
+ u16 seqnum;
+ u8 rc; /* Rejection Code */
+ u32 orp:24;
+ u32 fqid; /* 24-bit */
+ u32 tag;
+ struct qm_fd fd;
+ } __packed ern;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 colour:2; /* See QM_MR_DCERN_COLOUR_* */
+ u8 __reserved1:4;
+ enum qm_dc_portal portal:2;
+#else
+ enum qm_dc_portal portal:3;
+ u8 __reserved1:3;
+ u8 colour:2; /* See QM_MR_DCERN_COLOUR_* */
+#endif
+ u16 __reserved2;
+ u8 rc; /* Rejection Code */
+ u32 __reserved3:24;
+ u32 fqid; /* 24-bit */
+ u32 tag;
+ struct qm_fd fd;
+ } __packed dcern;
+ struct {
+ u8 fqs; /* Frame Queue Status */
+ u8 __reserved1[6];
+ u32 fqid; /* 24-bit */
+ u32 contextB;
+ u8 __reserved2[16];
+ } __packed fq; /* FQRN/FQRNI/FQRL/FQPN */
+ };
+ u8 __reserved2[32];
+} __packed;
+#define QM_MR_VERB_VBIT 0x80
+/*
+ * ERNs originating from direct-connect portals ("dcern") use 0x20 as a verb
+ * which would be invalid as a s/w enqueue verb. A s/w ERN can be distinguished
+ * from the other MR types by noting if the 0x20 bit is unset.
+ */
+#define QM_MR_VERB_TYPE_MASK 0x27
+#define QM_MR_VERB_DC_ERN 0x20
+#define QM_MR_VERB_FQRN 0x21
+#define QM_MR_VERB_FQRNI 0x22
+#define QM_MR_VERB_FQRL 0x23
+#define QM_MR_VERB_FQPN 0x24
+#define QM_MR_RC_MASK 0xf0 /* contains one of; */
+#define QM_MR_RC_CGR_TAILDROP 0x00
+#define QM_MR_RC_WRED 0x10
+#define QM_MR_RC_ERROR 0x20
+#define QM_MR_RC_ORPWINDOW_EARLY 0x30
+#define QM_MR_RC_ORPWINDOW_LATE 0x40
+#define QM_MR_RC_FQ_TAILDROP 0x50
+#define QM_MR_RC_ORPWINDOW_RETIRED 0x60
+#define QM_MR_RC_ORP_ZERO 0x70
+#define QM_MR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
+#define QM_MR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
+#define QM_MR_DCERN_COLOUR_GREEN 0x00
+#define QM_MR_DCERN_COLOUR_YELLOW 0x01
+#define QM_MR_DCERN_COLOUR_RED 0x02
+#define QM_MR_DCERN_COLOUR_OVERRIDE 0x03
+/*
+ * An identical structure of FQD fields is present in the "Init FQ" command and
+ * the "Query FQ" result, it's suctioned out into the "struct qm_fqd" type.
+ * Within that, the 'stashing' and 'taildrop' pieces are also factored out, the
+ * latter has two inlines to assist with converting to/from the mant+exp
+ * representation.
+ */
+struct qm_fqd_stashing {
+ /* See QM_STASHING_EXCL_<...> */
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 exclusive;
+ u8 __reserved1:2;
+ /* Numbers of cachelines */
+ u8 annotation_cl:2;
+ u8 data_cl:2;
+ u8 context_cl:2;
+#else
+ u8 context_cl:2;
+ u8 data_cl:2;
+ u8 annotation_cl:2;
+ u8 __reserved1:2;
+ u8 exclusive;
+#endif
+} __packed;
+struct qm_fqd_taildrop {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 __reserved1:3;
+ u16 mant:8;
+ u16 exp:5;
+#else
+ u16 exp:5;
+ u16 mant:8;
+ u16 __reserved1:3;
+#endif
+} __packed;
+struct qm_fqd_oac {
+ /* "Overhead Accounting Control", see QM_OAC_<...> */
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 oac:2; /* "Overhead Accounting Control" */
+ u8 __reserved1:6;
+#else
+ u8 __reserved1:6;
+ u8 oac:2; /* "Overhead Accounting Control" */
+#endif
+ /* Two's-complement value (-128 to +127) */
+ signed char oal; /* "Overhead Accounting Length" */
+} __packed;
+struct qm_fqd {
+ union {
+ u8 orpc;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 __reserved1:2;
+ u8 orprws:3;
+ u8 oa:1;
+ u8 olws:2;
+#else
+ u8 olws:2;
+ u8 oa:1;
+ u8 orprws:3;
+ u8 __reserved1:2;
+#endif
+ } __packed;
+ };
+ u8 cgid;
+ u16 fq_ctrl; /* See QM_FQCTRL_<...> */
+ union {
+ u16 dest_wq;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 channel:13; /* qm_channel */
+ u16 wq:3;
+#else
+ u16 wq:3;
+ u16 channel:13; /* qm_channel */
+#endif
+ } __packed dest;
+ };
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 __reserved2:1;
+ u16 ics_cred:15;
+#else
+ u16 __reserved2:1;
+ u16 ics_cred:15;
+#endif
+ /*
+ * For "Initialize Frame Queue" commands, the write-enable mask
+ * determines whether 'td' or 'oac_init' is observed. For query
+ * commands, this field is always 'td', and 'oac_query' (below) reflects
+ * the Overhead ACcounting values.
+ */
+ union {
+ uint16_t opaque_td;
+ struct qm_fqd_taildrop td;
+ struct qm_fqd_oac oac_init;
+ };
+ u32 context_b;
+ union {
+ /* Treat it as 64-bit opaque */
+ u64 opaque;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u32 hi;
+ u32 lo;
+#else
+ u32 lo;
+ u32 hi;
+#endif
+ };
+ /* Treat it as s/w portal stashing config */
+ /* see "FQD Context_A field used for [...]" */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ struct qm_fqd_stashing stashing;
+ /*
+ * 48-bit address of FQ context to
+ * stash, must be cacheline-aligned
+ */
+ u16 context_hi;
+ u32 context_lo;
+#else
+ u32 context_lo;
+ u16 context_hi;
+ struct qm_fqd_stashing stashing;
+#endif
+ } __packed;
+ } context_a;
+ struct qm_fqd_oac oac_query;
+} __packed;
+/* 64-bit converters for context_hi/lo */
+static inline u64 qm_fqd_stashing_get64(const struct qm_fqd *fqd)
+{
+ return ((u64)fqd->context_a.context_hi << 32) |
+ (u64)fqd->context_a.context_lo;
+}
+
+static inline dma_addr_t qm_fqd_stashing_addr(const struct qm_fqd *fqd)
+{
+ return (dma_addr_t)qm_fqd_stashing_get64(fqd);
+}
+
+static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd)
+{
+ return ((u64)fqd->context_a.hi << 32) |
+ (u64)fqd->context_a.lo;
+}
+
+static inline void qm_fqd_stashing_set64(struct qm_fqd *fqd, u64 addr)
+{
+ fqd->context_a.context_hi = upper_32_bits(addr);
+ fqd->context_a.context_lo = lower_32_bits(addr);
+}
+
+static inline void qm_fqd_context_a_set64(struct qm_fqd *fqd, u64 addr)
+{
+ fqd->context_a.hi = upper_32_bits(addr);
+ fqd->context_a.lo = lower_32_bits(addr);
+}
+
+/* convert a threshold value into mant+exp representation */
+static inline int qm_fqd_taildrop_set(struct qm_fqd_taildrop *td, u32 val,
+ int roundup)
+{
+ u32 e = 0;
+ int oddbit = 0;
+
+ if (val > 0xe0000000)
+ return -ERANGE;
+ while (val > 0xff) {
+ oddbit = val & 1;
+ val >>= 1;
+ e++;
+ if (roundup && oddbit)
+ val++;
+ }
+ td->exp = e;
+ td->mant = val;
+ return 0;
+}
+
+/* and the other direction */
+static inline u32 qm_fqd_taildrop_get(const struct qm_fqd_taildrop *td)
+{
+ return (u32)td->mant << td->exp;
+}
+
+
+/* See "Frame Queue Descriptor (FQD)" */
+/* Frame Queue Descriptor (FQD) field 'fq_ctrl' uses these constants */
+#define QM_FQCTRL_MASK 0x07ff /* 'fq_ctrl' flags; */
+#define QM_FQCTRL_CGE 0x0400 /* Congestion Group Enable */
+#define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */
+#define QM_FQCTRL_ORP 0x0100 /* ORP Enable */
+#define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */
+#define QM_FQCTRL_CPCSTASH 0x0040 /* CPC Stash Enable */
+#define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */
+#define QM_FQCTRL_AVOIDBLOCK 0x0004 /* Don't block active */
+#define QM_FQCTRL_HOLDACTIVE 0x0002 /* Hold active in portal */
+#define QM_FQCTRL_PREFERINCACHE 0x0001 /* Aggressively cache FQD */
+#define QM_FQCTRL_LOCKINCACHE QM_FQCTRL_PREFERINCACHE /* older naming */
+
+/* See "FQD Context_A field used for [...] */
+/* Frame Queue Descriptor (FQD) field 'CONTEXT_A' uses these constants */
+#define QM_STASHING_EXCL_ANNOTATION 0x04
+#define QM_STASHING_EXCL_DATA 0x02
+#define QM_STASHING_EXCL_CTX 0x01
+
+/* See "Intra Class Scheduling" */
+/* FQD field 'OAC' (Overhead ACcounting) uses these constants */
+#define QM_OAC_ICS 0x2 /* Accounting for Intra-Class Scheduling */
+#define QM_OAC_CG 0x1 /* Accounting for Congestion Groups */
+
+/*
+ * This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields
+ * and associated commands/responses. The WRED parameters are calculated from
+ * these fields as follows;
+ * MaxTH = MA * (2 ^ Mn)
+ * Slope = SA / (2 ^ Sn)
+ * MaxP = 4 * (Pn + 1)
+ */
+struct qm_cgr_wr_parm {
+ union {
+ u32 word;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u32 MA:8;
+ u32 Mn:5;
+ u32 SA:7; /* must be between 64-127 */
+ u32 Sn:6;
+ u32 Pn:6;
+#else
+ u32 Pn:6;
+ u32 Sn:6;
+ u32 SA:7; /* must be between 64-127 */
+ u32 Mn:5;
+ u32 MA:8;
+#endif
+ } __packed;
+ };
+} __packed;
+/*
+ * This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding
+ * management commands, this is padded to a 16-bit structure field, so that's
+ * how we represent it here. The congestion state threshold is calculated from
+ * these fields as follows;
+ * CS threshold = TA * (2 ^ Tn)
+ */
+struct qm_cgr_cs_thres {
+ union {
+ u16 hword;
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 __reserved:3;
+ u16 TA:8;
+ u16 Tn:5;
+#else
+ u16 Tn:5;
+ u16 TA:8;
+ u16 __reserved:3;
+#endif
+ } __packed;
+ };
+} __packed;
+/*
+ * This identical structure of CGR fields is present in the "Init/Modify CGR"
+ * commands and the "Query CGR" result. It's suctioned out here into its own
+ * struct.
+ */
+struct __qm_mc_cgr {
+ struct qm_cgr_wr_parm wr_parm_g;
+ struct qm_cgr_wr_parm wr_parm_y;
+ struct qm_cgr_wr_parm wr_parm_r;
+ u8 wr_en_g; /* boolean, use QM_CGR_EN */
+ u8 wr_en_y; /* boolean, use QM_CGR_EN */
+ u8 wr_en_r; /* boolean, use QM_CGR_EN */
+ u8 cscn_en; /* boolean, use QM_CGR_EN */
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 cscn_targ_upd_ctrl; /* use QM_CSCN_TARG_UDP_ */
+ u16 cscn_targ_dcp_low; /* CSCN_TARG_DCP low-16bits */
+#else
+ u16 cscn_targ_dcp_low; /* CSCN_TARG_DCP low-16bits */
+ u16 cscn_targ_upd_ctrl; /* use QM_CSCN_TARG_UDP_ */
+#endif
+ };
+ u32 cscn_targ; /* use QM_CGR_TARG_* */
+ };
+ u8 cstd_en; /* boolean, use QM_CGR_EN */
+ u8 cs; /* boolean, only used in query response */
+ union {
+ struct qm_cgr_cs_thres cs_thres;
+ /* use qm_cgr_cs_thres_set64() */
+ u16 __cs_thres;
+ };
+ u8 mode; /* QMAN_CGR_MODE_FRAME not supported in rev1.0 */
+} __packed;
+#define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en */
+#define QM_CGR_TARG_UDP_CTRL_WRITE_BIT 0x8000 /* value written to portal bit*/
+#define QM_CGR_TARG_UDP_CTRL_DCP 0x4000 /* 0: SWP, 1: DCP */
+#define QM_CGR_TARG_PORTAL(n) (0x80000000 >> (n)) /* s/w portal, 0-9 */
+#define QM_CGR_TARG_FMAN0 0x00200000 /* direct-connect portal: fman0 */
+#define QM_CGR_TARG_FMAN1 0x00100000 /* : fman1 */
+/* Convert CGR thresholds to/from "cs_thres" format */
+static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th)
+{
+ return (u64)th->TA << th->Tn;
+}
+
+static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val,
+ int roundup)
+{
+ u32 e = 0;
+ int oddbit = 0;
+
+ while (val > 0xff) {
+ oddbit = val & 1;
+ val >>= 1;
+ e++;
+ if (roundup && oddbit)
+ val++;
+ }
+ th->Tn = e;
+ th->TA = val;
+ return 0;
+}
+
+/* See 1.5.8.5.1: "Initialize FQ" */
+/* See 1.5.8.5.2: "Query FQ" */
+/* See 1.5.8.5.3: "Query FQ Non-Programmable Fields" */
+/* See 1.5.8.5.4: "Alter FQ State Commands " */
+/* See 1.5.8.6.1: "Initialize/Modify CGR" */
+/* See 1.5.8.6.2: "CGR Test Write" */
+/* See 1.5.8.6.3: "Query CGR" */
+/* See 1.5.8.6.4: "Query Congestion Group State" */
+struct qm_mcc_initfq {
+ u8 __reserved1;
+ u16 we_mask; /* Write Enable Mask */
+ u32 fqid; /* 24-bit */
+ u16 count; /* Initialises 'count+1' FQDs */
+ struct qm_fqd fqd; /* the FQD fields go here */
+ u8 __reserved3[30];
+} __packed;
+struct qm_mcc_queryfq {
+ u8 __reserved1[3];
+ u32 fqid; /* 24-bit */
+ u8 __reserved2[56];
+} __packed;
+struct qm_mcc_queryfq_np {
+ u8 __reserved1[3];
+ u32 fqid; /* 24-bit */
+ u8 __reserved2[56];
+} __packed;
+struct qm_mcc_alterfq {
+ u8 __reserved1[3];
+ u32 fqid; /* 24-bit */
+ u8 __reserved2;
+ u8 count; /* number of consecutive FQID */
+ u8 __reserved3[10];
+ u32 context_b; /* frame queue context b */
+ u8 __reserved4[40];
+} __packed;
+struct qm_mcc_initcgr {
+ u8 __reserved1;
+ u16 we_mask; /* Write Enable Mask */
+ struct __qm_mc_cgr cgr; /* CGR fields */
+ u8 __reserved2[2];
+ u8 cgid;
+ u8 __reserved4[32];
+} __packed;
+struct qm_mcc_cgrtestwrite {
+ u8 __reserved1[2];
+ u8 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */
+ u8 __reserved2[23];
+ u8 cgid;
+ u8 __reserved3[32];
+} __packed;
+struct qm_mcc_querycgr {
+ u8 __reserved1[30];
+ u8 cgid;
+ u8 __reserved2[32];
+} __packed;
+struct qm_mcc_querycongestion {
+ u8 __reserved[63];
+} __packed;
+struct qm_mcc_querywq {
+ u8 __reserved;
+ /* select channel if verb != QUERYWQ_DEDICATED */
+ union {
+ u16 channel_wq; /* ignores wq (3 lsbits) */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 id:13; /* qm_channel */
+ u16 __reserved1:3;
+#else
+ u16 __reserved1:3;
+ u16 id:13; /* qm_channel */
+#endif
+ } __packed channel;
+ };
+ u8 __reserved2[60];
+} __packed;
+
+struct qm_mc_command {
+ u8 __dont_write_directly__verb;
+ union {
+ struct qm_mcc_initfq initfq;
+ struct qm_mcc_queryfq queryfq;
+ struct qm_mcc_queryfq_np queryfq_np;
+ struct qm_mcc_alterfq alterfq;
+ struct qm_mcc_initcgr initcgr;
+ struct qm_mcc_cgrtestwrite cgrtestwrite;
+ struct qm_mcc_querycgr querycgr;
+ struct qm_mcc_querycongestion querycongestion;
+ struct qm_mcc_querywq querywq;
+ };
+} __packed;
+
+/* INITFQ-specific flags */
+#define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */
+#define QM_INITFQ_WE_OAC 0x0100
+#define QM_INITFQ_WE_ORPC 0x0080
+#define QM_INITFQ_WE_CGID 0x0040
+#define QM_INITFQ_WE_FQCTRL 0x0020
+#define QM_INITFQ_WE_DESTWQ 0x0010
+#define QM_INITFQ_WE_ICSCRED 0x0008
+#define QM_INITFQ_WE_TDTHRESH 0x0004
+#define QM_INITFQ_WE_CONTEXTB 0x0002
+#define QM_INITFQ_WE_CONTEXTA 0x0001
+/* INITCGR/MODIFYCGR-specific flags */
+#define QM_CGR_WE_MASK 0x07ff /* 'Write Enable Mask'; */
+#define QM_CGR_WE_WR_PARM_G 0x0400
+#define QM_CGR_WE_WR_PARM_Y 0x0200
+#define QM_CGR_WE_WR_PARM_R 0x0100
+#define QM_CGR_WE_WR_EN_G 0x0080
+#define QM_CGR_WE_WR_EN_Y 0x0040
+#define QM_CGR_WE_WR_EN_R 0x0020
+#define QM_CGR_WE_CSCN_EN 0x0010
+#define QM_CGR_WE_CSCN_TARG 0x0008
+#define QM_CGR_WE_CSTD_EN 0x0004
+#define QM_CGR_WE_CS_THRES 0x0002
+#define QM_CGR_WE_MODE 0x0001
+
+struct qm_mcr_initfq {
+ u8 __reserved1[62];
+} __packed;
+struct qm_mcr_queryfq {
+ u8 __reserved1[8];
+ struct qm_fqd fqd; /* the FQD fields are here */
+ u8 __reserved2[30];
+} __packed;
+struct qm_mcr_queryfq_np {
+ u8 __reserved1;
+ u8 state; /* QM_MCR_NP_STATE_*** */
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u8 __reserved2;
+ u32 fqd_link:24;
+ u16 __reserved3:2;
+ u16 odp_seq:14;
+ u16 __reserved4:2;
+ u16 orp_nesn:14;
+ u16 __reserved5:1;
+ u16 orp_ea_hseq:15;
+ u16 __reserved6:1;
+ u16 orp_ea_tseq:15;
+ u8 __reserved7;
+ u32 orp_ea_hptr:24;
+ u8 __reserved8;
+ u32 orp_ea_tptr:24;
+ u8 __reserved9;
+ u32 pfdr_hptr:24;
+ u8 __reserved10;
+ u32 pfdr_tptr:24;
+ u8 __reserved11[5];
+ u8 __reserved12:7;
+ u8 is:1;
+ u16 ics_surp;
+ u32 byte_cnt;
+ u8 __reserved13;
+ u32 frm_cnt:24;
+ u32 __reserved14;
+ u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
+ u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
+ u16 __reserved15;
+ u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
+ u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
+ u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
+#else
+ u8 __reserved2;
+ u32 fqd_link:24;
+
+ u16 odp_seq:14;
+ u16 __reserved3:2;
+
+ u16 orp_nesn:14;
+ u16 __reserved4:2;
+
+ u16 orp_ea_hseq:15;
+ u16 __reserved5:1;
+
+ u16 orp_ea_tseq:15;
+ u16 __reserved6:1;
+
+ u8 __reserved7;
+ u32 orp_ea_hptr:24;
+
+ u8 __reserved8;
+ u32 orp_ea_tptr:24;
+
+ u8 __reserved9;
+ u32 pfdr_hptr:24;
+
+ u8 __reserved10;
+ u32 pfdr_tptr:24;
+
+ u8 __reserved11[5];
+ u8 is:1;
+ u8 __reserved12:7;
+ u16 ics_surp;
+ u32 byte_cnt;
+ u8 __reserved13;
+ u32 frm_cnt:24;
+ u32 __reserved14;
+ u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
+ u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
+ u16 __reserved15;
+ u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
+ u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
+ u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
+#endif
+} __packed;
+
+struct qm_mcr_alterfq {
+ u8 fqs; /* Frame Queue Status */
+ u8 __reserved1[61];
+} __packed;
+struct qm_mcr_initcgr {
+ u8 __reserved1[62];
+} __packed;
+struct qm_mcr_cgrtestwrite {
+ u16 __reserved1;
+ struct __qm_mc_cgr cgr; /* CGR fields */
+ u8 __reserved2[3];
+ u32 __reserved3:24;
+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */
+ u32 __reserved4:24;
+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */
+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */
+ u16 lgt; /* Last Group Tick */
+ u16 wr_prob_g;
+ u16 wr_prob_y;
+ u16 wr_prob_r;
+ u8 __reserved5[8];
+} __packed;
+struct qm_mcr_querycgr {
+ u16 __reserved1;
+ struct __qm_mc_cgr cgr; /* CGR fields */
+ u8 __reserved2[3];
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u32 __reserved3:24;
+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */
+#else
+ u32 i_bcnt_lo; /* low 32-bits of 40-bit */
+ u32 i_bcnt_hi:8;/* high 8-bits of 40-bit "Instant" */
+ u32 __reserved3:24;
+#endif
+ };
+ u64 i_bcnt;
+ };
+ union {
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u32 __reserved4:24;
+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */
+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */
+#else
+ u32 a_bcnt_lo; /* low 32-bits of 40-bit */
+ u32 a_bcnt_hi:8;/* high 8-bits of 40-bit "Average" */
+ u32 __reserved4:24;
+#endif
+ };
+ u64 a_bcnt;
+ };
+ union {
+ u32 cscn_targ_swp[4];
+ u8 __reserved5[16];
+ };
+} __packed;
+
+struct __qm_mcr_querycongestion {
+ u32 state[8];
+};
+
+struct qm_mcr_querycongestion {
+ u8 __reserved[30];
+ /* Access this struct using QM_MCR_QUERYCONGESTION() */
+ struct __qm_mcr_querycongestion state;
+} __packed;
+struct qm_mcr_querywq {
+ union {
+ u16 channel_wq; /* ignores wq (3 lsbits) */
+ struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ u16 id:13; /* qm_channel */
+ u16 __reserved:3;
+#else
+ u16 __reserved:3;
+ u16 id:13; /* qm_channel */
+#endif
+ } __packed channel;
+ };
+ u8 __reserved[28];
+ u32 wq_len[8];
+} __packed;
+
+struct qm_mc_result {
+ u8 verb;
+ u8 result;
+ union {
+ struct qm_mcr_initfq initfq;
+ struct qm_mcr_queryfq queryfq;
+ struct qm_mcr_queryfq_np queryfq_np;
+ struct qm_mcr_alterfq alterfq;
+ struct qm_mcr_initcgr initcgr;
+ struct qm_mcr_cgrtestwrite cgrtestwrite;
+ struct qm_mcr_querycgr querycgr;
+ struct qm_mcr_querycongestion querycongestion;
+ struct qm_mcr_querywq querywq;
+ };
+} __packed;
+
+#define QM_MCR_VERB_RRID 0x80
+#define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
+#define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
+#define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
+#define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
+#define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
+#define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
+#define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
+#define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
+#define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
+#define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
+#define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
+#define QM_MCR_RESULT_NULL 0x00
+#define QM_MCR_RESULT_OK 0xf0
+#define QM_MCR_RESULT_ERR_FQID 0xf1
+#define QM_MCR_RESULT_ERR_FQSTATE 0xf2
+#define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
+#define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
+#define QM_MCR_RESULT_PENDING 0xf8
+#define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
+#define QM_MCR_NP_STATE_FE 0x10
+#define QM_MCR_NP_STATE_R 0x08
+#define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
+#define QM_MCR_NP_STATE_OOS 0x00
+#define QM_MCR_NP_STATE_RETIRED 0x01
+#define QM_MCR_NP_STATE_TEN_SCHED 0x02
+#define QM_MCR_NP_STATE_TRU_SCHED 0x03
+#define QM_MCR_NP_STATE_PARKED 0x04
+#define QM_MCR_NP_STATE_ACTIVE 0x05
+#define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
+#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
+#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
+#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
+#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
+#define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
+#define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
+/* This extracts the state for congestion group 'n' from a query response.
+ * Eg.
+ * u8 cgr = [...];
+ * struct qm_mc_result *res = [...];
+ * printf("congestion group %d congestion state: %d\n", cgr,
+ * QM_MCR_QUERYCONGESTION(&res->querycongestion.state, cgr));
+ */
+#define __CGR_WORD(num) (num >> 5)
+#define __CGR_SHIFT(num) (num & 0x1f)
+#define __CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3)
+static inline int QM_MCR_QUERYCONGESTION(struct __qm_mcr_querycongestion *p,
+ u8 cgr)
+{
+ return p->state[__CGR_WORD(cgr)] & (0x80000000 >> __CGR_SHIFT(cgr));
+}
+
+ /* Portal and Frame Queues */
+/* Represents a managed portal */
+struct qman_portal;
+
+/*
+ * This object type represents QMan frame queue descriptors (FQD), it is
+ * cacheline-aligned, and initialised by qman_create_fq(). The structure is
+ * defined further down.
+ */
+struct qman_fq;
+
+/*
+ * This object type represents a QMan congestion group, it is defined further
+ * down.
+ */
+struct qman_cgr;
+
+/*
+ * This enum, and the callback type that returns it, are used when handling
+ * dequeued frames via DQRR. Note that for "null" callbacks registered with the
+ * portal object (for handling dequeues that do not demux because context_b is
+ * NULL), the return value *MUST* be qman_cb_dqrr_consume.
+ */
+enum qman_cb_dqrr_result {
+ /* DQRR entry can be consumed */
+ qman_cb_dqrr_consume,
+ /* Like _consume, but requests parking - FQ must be held-active */
+ qman_cb_dqrr_park,
+ /* Does not consume, for DCA mode only. This allows out-of-order
+ * consumes by explicit calls to qman_dca() and/or the use of implicit
+ * DCA via EQCR entries.
+ */
+ qman_cb_dqrr_defer,
+ /*
+ * Stop processing without consuming this ring entry. Exits the current
+ * qman_p_poll_dqrr() or interrupt-handling, as appropriate. If within
+ * an interrupt handler, the callback would typically call
+ * qman_irqsource_remove(QM_PIRQ_DQRI) before returning this value,
+ * otherwise the interrupt will reassert immediately.
+ */
+ qman_cb_dqrr_stop,
+ /* Like qman_cb_dqrr_stop, but consumes the current entry. */
+ qman_cb_dqrr_consume_stop
+};
+
+typedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(struct qman_portal *qm,
+ struct qman_fq *fq,
+ const struct qm_dqrr_entry *dqrr);
+
+/*
+ * This callback type is used when handling ERNs, FQRNs and FQRLs via MR. They
+ * are always consumed after the callback returns.
+ */
+typedef void (*qman_cb_mr)(struct qman_portal *qm, struct qman_fq *fq,
+ const struct qm_mr_entry *msg);
+
+/* This callback type is used when handling DCP ERNs */
+typedef void (*qman_cb_dc_ern)(struct qman_portal *qm,
+ const struct qm_mr_entry *msg);
+/*
+ * s/w-visible states. Ie. tentatively scheduled + truly scheduled + active +
+ * held-active + held-suspended are just "sched". Things like "retired" will not
+ * be assumed until it is complete (ie. QMAN_FQ_STATE_CHANGING is set until
+ * then, to indicate it's completing and to gate attempts to retry the retire
+ * command). Note, park commands do not set QMAN_FQ_STATE_CHANGING because it's
+ * technically impossible in the case of enqueue DCAs (which refer to DQRR ring
+ * index rather than the FQ that ring entry corresponds to), so repeated park
+ * commands are allowed (if you're silly enough to try) but won't change FQ
+ * state, and the resulting park notifications move FQs from "sched" to
+ * "parked".
+ */
+enum qman_fq_state {
+ qman_fq_state_oos,
+ qman_fq_state_parked,
+ qman_fq_state_sched,
+ qman_fq_state_retired
+};
+
+
+/*
+ * Frame queue objects (struct qman_fq) are stored within memory passed to
+ * qman_create_fq(), as this allows stashing of caller-provided demux callback
+ * pointers at no extra cost to stashing of (driver-internal) FQ state. If the
+ * caller wishes to add per-FQ state and have it benefit from dequeue-stashing,
+ * they should;
+ *
+ * (a) extend the qman_fq structure with their state; eg.
+ *
+ * // myfq is allocated and driver_fq callbacks filled in;
+ * struct my_fq {
+ * struct qman_fq base;
+ * int an_extra_field;
+ * [ ... add other fields to be associated with each FQ ...]
+ * } *myfq = some_my_fq_allocator();
+ * struct qman_fq *fq = qman_create_fq(fqid, flags, &myfq->base);
+ *
+ * // in a dequeue callback, access extra fields from 'fq' via a cast;
+ * struct my_fq *myfq = (struct my_fq *)fq;
+ * do_something_with(myfq->an_extra_field);
+ * [...]
+ *
+ * (b) when and if configuring the FQ for context stashing, specify how ever
+ * many cachelines are required to stash 'struct my_fq', to accelerate not
+ * only the QMan driver but the callback as well.
+ */
+
+struct qman_fq_cb {
+ qman_cb_dqrr dqrr; /* for dequeued frames */
+ qman_cb_mr ern; /* for s/w ERNs */
+ qman_cb_mr fqs; /* frame-queue state changes*/
+};
+
+struct qman_fq {
+ /* Caller of qman_create_fq() provides these demux callbacks */
+ struct qman_fq_cb cb;
+ /*
+ * These are internal to the driver, don't touch. In particular, they
+ * may change, be removed, or extended (so you shouldn't rely on
+ * sizeof(qman_fq) being a constant).
+ */
+ spinlock_t fqlock;
+ u32 fqid;
+ /* DPDK Interface */
+ void *dpaa_intf;
+
+ volatile unsigned long flags;
+ enum qman_fq_state state;
+ int cgr_groupid;
+ struct rb_node node;
+};
+
+/*
+ * This callback type is used when handling congestion group entry/exit.
+ * 'congested' is non-zero on congestion-entry, and zero on congestion-exit.
+ */
+typedef void (*qman_cb_cgr)(struct qman_portal *qm,
+ struct qman_cgr *cgr, int congested);
+
+struct qman_cgr {
+ /* Set these prior to qman_create_cgr() */
+ u32 cgrid; /* 0..255, but u32 to allow specials like -1, 256, etc.*/
+ qman_cb_cgr cb;
+ /* These are private to the driver */
+ u16 chan; /* portal channel this object is created on */
+ struct list_head node;
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FSL_QMAN_H */
diff --git a/drivers/bus/dpaa/include/fsl_usd.h b/drivers/bus/dpaa/include/fsl_usd.h
index 4ff48c6..b0d953f 100644
--- a/drivers/bus/dpaa/include/fsl_usd.h
+++ b/drivers/bus/dpaa/include/fsl_usd.h
@@ -47,6 +47,10 @@
extern "C" {
#endif
+/* Thread-entry/exit hooks; */
+int qman_thread_init(void);
+int qman_thread_finish(void);
+
#define QBMAN_ANY_PORTAL_IDX 0xffffffff
/* Obtain and free raw (unitialized) portals */
@@ -81,6 +85,15 @@ int qman_free_raw_portal(struct dpaa_raw_portal *portal);
int bman_allocate_raw_portal(struct dpaa_raw_portal *portal);
int bman_free_raw_portal(struct dpaa_raw_portal *portal);
+/* Post-process interrupts. NB, the kernel IRQ handler disables the interrupt
+ * line before notifying us, and this post-processing re-enables it once
+ * processing is complete. As such, it is essential to call this before going
+ * into another blocking read/select/poll.
+ */
+void qman_thread_irq(void);
+
+/* Global setup */
+int qman_global_init(void);
#ifdef __cplusplus
}
#endif
--
2.9.3
next prev parent reply other threads:[~2017-09-28 11:23 UTC|newest]
Thread overview: 367+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-16 5:40 [dpdk-dev] [PATCH 00/38] Introduce NXP DPAA Bus, Mempool and PMD Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 01/38] eal: add support for 24 40 and 48 bit operations Shreyansh Jain
2017-06-16 8:57 ` Bruce Richardson
2017-06-16 9:21 ` Shreyansh Jain
2017-06-16 9:42 ` Thomas Monjalon
2017-06-16 10:34 ` Adrien Mazarguil
2017-06-19 11:00 ` Shreyansh Jain
2017-06-19 13:52 ` Wiles, Keith
2017-06-20 10:43 ` Hemant Agrawal
2017-06-20 14:34 ` Wiles, Keith
2017-06-21 8:17 ` Hemant Agrawal
2017-06-21 8:32 ` Bruce Richardson
2017-06-21 9:02 ` Adrien Mazarguil
2017-10-02 10:16 ` Avi Kivity
2017-06-16 5:40 ` [dpdk-dev] [PATCH 02/38] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 03/38] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 04/38] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 05/38] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 06/38] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 07/38] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 08/38] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 09/38] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 10/38] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 11/38] bus/dpaa: add QMAN interface driver Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 12/38] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 13/38] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 14/38] bus/dpaa: add support for FMAN frame queue lookup Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 15/38] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 16/38] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 17/38] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 18/38] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-06-28 15:51 ` Ferruh Yigit
2017-06-29 14:17 ` Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 19/38] mempool/dpaa: add support for NXP DPAA Mempool Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 20/38] maintainers: claim ownership of DPAA Mempool driver Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 21/38] drivers: enable compilation " Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 22/38] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-06-28 15:41 ` Ferruh Yigit
2017-06-29 14:29 ` Shreyansh Jain
2017-07-02 6:47 ` Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 23/38] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 24/38] net/dpaa: add support for Tx and Rx queue setup Shreyansh Jain
2017-06-28 15:45 ` Ferruh Yigit
2017-06-29 14:55 ` Shreyansh Jain
2017-06-29 15:41 ` Ferruh Yigit
2017-06-30 11:48 ` Shreyansh Jain
2017-07-04 14:50 ` Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 25/38] net/dpaa: add support for MTU update Shreyansh Jain
2017-06-28 15:45 ` Ferruh Yigit
2017-06-29 14:56 ` Shreyansh Jain
2017-06-29 15:43 ` Ferruh Yigit
2017-06-16 5:40 ` [dpdk-dev] [PATCH 26/38] net/dpaa: add support for jumbo frames Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 27/38] net/dpaa: add support for link status update Shreyansh Jain
2017-06-28 15:46 ` Ferruh Yigit
2017-06-29 14:57 ` Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 28/38] net/dpaa: add support for device info Shreyansh Jain
2017-06-16 5:40 ` [dpdk-dev] [PATCH 29/38] net/dpaa: add support for promiscuous toggle Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 30/38] net/dpaa: add support for multicast toggle Shreyansh Jain
2017-06-28 15:47 ` Ferruh Yigit
2017-06-29 14:58 ` Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 31/38] net/dpaa: add support for basic stats Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 32/38] net/dpaa: add support for MAC address update Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 33/38] net/dpaa: add support for flow control Shreyansh Jain
2017-06-28 15:47 ` Ferruh Yigit
2017-06-30 9:37 ` Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 34/38] net/dpaa: add support for hashed RSS Shreyansh Jain
2017-06-28 15:48 ` Ferruh Yigit
2017-06-30 10:31 ` Shreyansh Jain
2017-06-30 11:39 ` Ferruh Yigit
2017-07-04 14:49 ` Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 35/38] net/dpaa: add support for packet type parsing Shreyansh Jain
2017-06-28 15:50 ` Ferruh Yigit
2017-06-30 11:40 ` Shreyansh Jain
2017-07-04 12:11 ` Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 36/38] net/dpaa: add support for checksum offload Shreyansh Jain
2017-06-28 15:50 ` Ferruh Yigit
2017-07-04 14:48 ` Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 37/38] net/dpaa: add support for Scattered Rx Shreyansh Jain
2017-06-16 5:41 ` [dpdk-dev] [PATCH 38/38] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-06-28 15:51 ` Ferruh Yigit
2017-06-30 11:47 ` Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 00/40] Introduce NXP DPAA Bus, Mempool and PMD Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 01/40] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 02/40] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 03/40] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 04/40] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 05/40] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 06/40] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 07/40] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-07-04 14:43 ` [dpdk-dev] [PATCH v2 08/40] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 09/40] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 10/40] bus/dpaa: add QMAN interface driver Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 11/40] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 12/40] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 13/40] bus/dpaa: add support for FMAN frame queue lookup Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 14/40] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 15/40] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 16/40] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 17/40] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 18/40] bus/dpaa: add DPAA mempool logging macros Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 19/40] mempool/dpaa: add support for NXP DPAA Mempool Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 20/40] drivers: enable compilation of DPAA Mempool driver Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 21/40] maintainers: claim ownership " Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 22/40] bus/dpaa: add DPAA PMD logging macros Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 23/40] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 24/40] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 25/40] net/dpaa: add support for Tx and Rx queue setup Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 26/40] net/dpaa: add support for MTU update Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 27/40] net/dpaa: add support for jumbo frames Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 28/40] net/dpaa: add support for link status update Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 29/40] net/dpaa: add support for device info and speed capability Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 30/40] net/dpaa: add support for promiscuous toggle Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 31/40] net/dpaa: add support for multicast toggle Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 32/40] net/dpaa: add support for MAC address update Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 33/40] net/dpaa: add support for basic stats Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 34/40] net/dpaa: add support for flow control Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 35/40] net/dpaa: add support for hashed RSS Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 36/40] net/dpaa: add support for packet type parsing Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 37/40] net/dpaa: add support for checksum offload Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 38/40] net/dpaa: add support for Scattered Rx Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 39/40] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-07-04 14:44 ` [dpdk-dev] [PATCH v2 40/40] net/dpaa: support for firmware version get API Shreyansh Jain
2017-07-05 0:13 ` [dpdk-dev] [PATCH v2 00/40] Introduce NXP DPAA Bus, Mempool and PMD Thomas Monjalon
2017-07-05 4:38 ` Shreyansh Jain
2017-07-05 6:28 ` Thomas Monjalon
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 " Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 01/40] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 02/40] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 03/40] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 04/40] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 05/40] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 06/40] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 07/40] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 08/40] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 09/40] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 10/40] bus/dpaa: add QMAN interface driver Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 11/40] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 12/40] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 13/40] bus/dpaa: add support for FMAN frame queue lookup Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 14/40] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 15/40] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 16/40] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 17/40] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 18/40] bus/dpaa: add DPAA mempool logging macros Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 19/40] mempool/dpaa: add support for NXP DPAA Mempool Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 20/40] drivers: enable compilation of DPAA Mempool driver Shreyansh Jain
2017-09-21 21:55 ` Thomas Monjalon
2017-09-22 6:35 ` Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 21/40] maintainers: claim ownership " Shreyansh Jain
2017-09-21 21:56 ` Thomas Monjalon
2017-09-22 6:47 ` Shreyansh Jain
2017-09-22 6:53 ` Thomas Monjalon
2017-09-22 7:37 ` Shreyansh Jain
2017-09-22 7:35 ` Thomas Monjalon
2017-09-27 8:30 ` Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 22/40] bus/dpaa: add DPAA PMD logging macros Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 23/40] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 24/40] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-09-21 22:03 ` Thomas Monjalon
2017-09-22 6:51 ` Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 25/40] net/dpaa: add support for Tx and Rx queue setup Shreyansh Jain
2017-08-23 14:11 ` [dpdk-dev] [PATCH v3 26/40] net/dpaa: add support for MTU update Shreyansh Jain
2017-09-21 22:07 ` Thomas Monjalon
2017-09-22 6:48 ` Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 27/40] net/dpaa: add support for jumbo frames Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 28/40] net/dpaa: add support for link status update Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 29/40] net/dpaa: add support for device info and speed capability Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 30/40] net/dpaa: add support for promiscuous toggle Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 31/40] net/dpaa: add support for multicast toggle Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 32/40] net/dpaa: add support for MAC address update Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 33/40] net/dpaa: add support for basic stats Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 34/40] net/dpaa: add support for flow control Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 35/40] net/dpaa: add support for hashed RSS Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 36/40] net/dpaa: add support for packet type parsing Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 37/40] net/dpaa: add support for checksum offload Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 38/40] net/dpaa: add support for Scattered Rx Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 39/40] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-08-23 14:12 ` [dpdk-dev] [PATCH v3 40/40] net/dpaa: support for firmware version get API Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 01/41] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 02/41] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-09-18 14:47 ` Ferruh Yigit
2017-09-19 13:14 ` Shreyansh Jain
2017-09-19 13:33 ` Ferruh Yigit
2017-09-25 14:32 ` Shreyansh Jain
2017-09-25 15:11 ` Ferruh Yigit
2017-09-26 11:26 ` Shreyansh Jain
2017-09-27 9:30 ` Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 03/41] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-09-18 14:49 ` Ferruh Yigit
2017-09-19 13:18 ` Shreyansh Jain
2017-09-19 13:40 ` Ferruh Yigit
2017-09-19 13:57 ` Shreyansh Jain
2017-09-26 12:43 ` Shreyansh Jain
2017-09-27 23:09 ` Ferruh Yigit
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 04/41] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-09-18 14:49 ` Ferruh Yigit
2017-09-19 13:37 ` Shreyansh Jain
2017-09-19 14:15 ` Ferruh Yigit
2017-09-19 20:01 ` Thomas Monjalon
2017-09-20 20:39 ` Jan Viktorin
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 05/41] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-09-18 14:50 ` Ferruh Yigit
2017-09-18 16:15 ` Thomas Monjalon
2017-09-18 17:12 ` Hemant Agrawal
2017-09-19 13:43 ` Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 06/41] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 07/41] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-09-18 14:51 ` Ferruh Yigit
2017-09-19 14:17 ` Shreyansh Jain
2017-09-09 11:20 ` [dpdk-dev] [PATCH v4 08/41] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 09/41] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 10/41] bus/dpaa: add QMAN interface driver Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 11/41] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-09-18 14:53 ` Ferruh Yigit
2017-09-19 14:18 ` Shreyansh Jain
2017-09-28 11:45 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 12/41] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 13/41] bus/dpaa: add support for FMAN frame queue lookup Shreyansh Jain
2017-09-18 14:51 ` Ferruh Yigit
2017-09-28 11:47 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 14/41] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 15/41] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 16/41] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 17/41] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-09-18 14:53 ` Ferruh Yigit
2017-09-19 14:25 ` Shreyansh Jain
2017-09-28 11:49 ` Shreyansh Jain
2017-09-18 18:33 ` Mcnamara, John
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 18/41] bus/dpaa: add DPAA mempool logging macros Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 19/41] mempool/dpaa: add support for NXP DPAA Mempool Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 20/41] drivers: enable compilation of DPAA Mempool driver Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 21/41] maintainers: claim ownership " Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 22/41] bus/dpaa: add DPAA PMD logging macros Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 23/41] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 24/41] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 25/41] net/dpaa: add support for Tx and Rx queue setup Shreyansh Jain
2017-09-18 14:55 ` Ferruh Yigit
2017-09-21 12:59 ` Shreyansh Jain
2017-09-28 11:51 ` Shreyansh Jain
2017-09-18 14:55 ` Ferruh Yigit
2017-09-21 13:00 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 26/41] net/dpaa: add support for MTU update Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 27/41] net/dpaa: add support for jumbo frames Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 28/41] net/dpaa: add support for link status update Shreyansh Jain
2017-09-18 14:56 ` Ferruh Yigit
2017-09-21 13:09 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 29/41] net/dpaa: add support for device info and speed capability Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 30/41] net/dpaa: add support for promiscuous toggle Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 31/41] net/dpaa: add support for multicast toggle Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 32/41] net/dpaa: add support for MAC address update Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 33/41] net/dpaa: add support for basic stats Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 34/41] net/dpaa: add support for flow control Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 35/41] net/dpaa: add support for hashed RSS Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 36/41] net/dpaa: add support for packet type parsing Shreyansh Jain
2017-09-18 14:56 ` Ferruh Yigit
2017-09-21 13:16 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 37/41] net/dpaa: add support for checksum offload Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 38/41] net/dpaa: add support for Scattered Rx Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 39/41] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 40/41] net/dpaa: support for firmware version get API Shreyansh Jain
2017-09-18 14:57 ` Ferruh Yigit
2017-09-21 13:18 ` Shreyansh Jain
2017-09-09 11:21 ` [dpdk-dev] [PATCH v4 41/41] net/dpaa: support for extended statistics Shreyansh Jain
2017-09-18 14:57 ` Ferruh Yigit
2017-09-21 13:26 ` Shreyansh Jain
2017-09-27 8:26 ` Shreyansh Jain
2017-09-27 23:37 ` Ferruh Yigit
2017-09-28 2:30 ` Shreyansh Jain
2017-09-28 2:52 ` Shreyansh Jain
2017-09-28 9:26 ` Ferruh Yigit
2017-09-21 22:09 ` [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD Thomas Monjalon
2017-09-21 22:10 ` Thomas Monjalon
2017-09-22 6:25 ` Shreyansh Jain
2017-09-22 6:33 ` Thomas Monjalon
2017-09-22 13:06 ` Shreyansh Jain
2017-09-22 13:13 ` Thomas Monjalon
2017-09-22 14:00 ` Shreyansh Jain
2017-09-22 14:19 ` Thomas Monjalon
2017-09-23 10:39 ` Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 00/40] " Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 01/40] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 02/40] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 03/40] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 04/40] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 05/40] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 06/40] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 07/40] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 08/40] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 09/40] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-09-28 11:33 ` Shreyansh Jain [this message]
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 11/40] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 12/40] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 13/40] bus/dpaa: support FMAN frame queue lookup Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 14/40] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 15/40] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 16/40] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 17/40] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 18/40] bus/dpaa: add DPAA mempool logging macros Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 19/40] mempool/dpaa: support NXP DPAA Mempool Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 20/40] config: enable compilation of DPAA Mempool driver Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 21/40] bus/dpaa: add DPAA PMD logging macros Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 22/40] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 23/40] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 24/40] net/dpaa: support Tx and Rx queue setup Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 25/40] net/dpaa: support MTU update Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 26/40] net/dpaa: support jumbo frames Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 27/40] net/dpaa: support link status update Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 28/40] net/dpaa: support device info and speed capability Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 29/40] net/dpaa: support promiscuous toggle Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 30/40] net/dpaa: support multicast toggle Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 31/40] net/dpaa: support MAC address update Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 32/40] net/dpaa: support basic stats Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 33/40] net/dpaa: support flow control Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 34/40] net/dpaa: support hashed RSS Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 35/40] net/dpaa: support packet type parsing Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 36/40] net/dpaa: support checksum offload Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 37/40] net/dpaa: support Scattered Rx Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 38/40] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 39/40] net/dpaa: support firmware version get API Shreyansh Jain
2017-09-28 11:33 ` [dpdk-dev] [PATCH v5 40/40] net/dpaa: support extended statistics Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 00/40] Introduce NXP DPAA Bus, Mempool and PMD Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 01/40] config: add NXP DPAA SoC build configuration Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 02/40] bus/dpaa: introduce NXP DPAA Bus driver skeleton Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 03/40] bus/dpaa: add compatibility and helper macros Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 04/40] bus/dpaa: add OF parser for device scanning Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 05/40] bus/dpaa: introducing FMan configurations Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 06/40] bus/dpaa: add FMan hardware operations Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 07/40] bus/dpaa: enable DPAA IOCTL portal driver Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 08/40] bus/dpaa: add layer for interrupt emulation using pthread Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 09/40] bus/dpaa: add routines for managing a RB tree Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 10/40] bus/dpaa: add QMAN interface driver Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 11/40] bus/dpaa: add QMan driver core routines Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 12/40] bus/dpaa: add BMAN driver core Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 13/40] bus/dpaa: support FMAN frame queue lookup Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 14/40] bus/dpaa: add BMan hardware interfaces Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 15/40] bus/dpaa: add fman flow control threshold setting Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 16/40] bus/dpaa: integrate DPAA Bus with hardware blocks Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 17/40] doc: add NXP DPAA PMD documentation Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 18/40] bus/dpaa: add DPAA mempool logging macros Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 19/40] mempool/dpaa: support NXP DPAA Mempool Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 20/40] config: enable compilation of DPAA Mempool driver Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 21/40] bus/dpaa: add DPAA PMD logging macros Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 22/40] net/dpaa: add NXP DPAA PMD driver skeleton Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 23/40] config: enable NXP DPAA PMD compilation Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 24/40] net/dpaa: support Tx and Rx queue setup Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 25/40] net/dpaa: support MTU update Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 26/40] net/dpaa: support jumbo frames Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 27/40] net/dpaa: support link status update Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 28/40] net/dpaa: support device info and speed capability Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 29/40] net/dpaa: support promiscuous toggle Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 30/40] net/dpaa: support multicast toggle Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 31/40] net/dpaa: support MAC address update Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 32/40] net/dpaa: support basic stats Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 33/40] net/dpaa: support flow control Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 34/40] net/dpaa: support hashed RSS Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 35/40] net/dpaa: support packet type parsing Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 36/40] net/dpaa: support checksum offload Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 37/40] net/dpaa: support Scattered Rx Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 38/40] net/dpaa: add packet dump for debugging Shreyansh Jain
2017-09-28 12:29 ` [dpdk-dev] [PATCH v6 39/40] net/dpaa: support firmware version get API Shreyansh Jain
2017-09-28 12:30 ` [dpdk-dev] [PATCH v6 40/40] net/dpaa: support extended statistics Shreyansh Jain
2017-09-28 14:10 ` [dpdk-dev] [PATCH 1/2] bus/dpaa: fix incorrect ccsr mem allocation Shreyansh Jain
2017-09-28 14:10 ` [dpdk-dev] [PATCH 2/2] config: fix DPAA PMD linking Shreyansh Jain
2017-09-28 14:12 ` [dpdk-dev] [PATCH 1/2] bus/dpaa: fix incorrect ccsr mem allocation Shreyansh Jain
2017-10-02 23:05 ` Ferruh Yigit
2017-10-02 23:05 ` [dpdk-dev] [PATCH v6 00/40] Introduce NXP DPAA Bus, Mempool and PMD Ferruh Yigit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170928113344.12248-11-shreyansh.jain@nxp.com \
--to=shreyansh.jain@nxp.com \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@intel.com \
--cc=hemant.agrawal@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).