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From: "Wu, Jingjing" <jingjing.wu@intel.com>
To: "Sexton, Rory" <rory.sexton@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	"Marjanovic, Nemanja" <nemanja.marjanovic@intel.com>,
	"Mcnamara, John" <john.mcnamara@intel.com>
Subject: Re: [dpdk-dev] [PATCH v1] net/i40e: set no drop for traffic class
Date: Mon, 26 Dec 2016 08:45:41 +0000	[thread overview]
Message-ID: <9BB6961774997848B5B42BEC655768F810CBEF56@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <EAC303C93824C94DB804849C22B752B30D2B20A0@IRSMSX104.ger.corp.intel.com>



> -----Original Message-----
> From: Sexton, Rory
> Sent: Friday, December 9, 2016 10:03 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Marjanovic, Nemanja <nemanja.marjanovic@intel.com>;
> Mcnamara, John <john.mcnamara@intel.com>
> Subject: RE: [PATCH v1] net/i40e: set no drop for traffic class
> 
> Hi Jingjing,
> 
> Yes PRTDCB_TC2PFC is used to control pfc for each TC however we have
> noticed other advantages of using the register.
> By setting the register explicitly by doing the "I40E_WRITE_REG(hw, 0x1c0980,
> 0xff);" it allows for packets to be temporarily stored on the NICs RX SRAM
> until there is space for them on SW descriptor ring versus dropping them
> when the SW ring becomes full. This also allows for larger burst handling. It
> also means SW doesn't have to be as quick to empty the DRAM based
> descriptor rings, allowing more processing on cores.
> 
> I have tested using the ETH_DCB_PFC_SUPPORT flag in
> rte_eth_conf.dcb_capability_en and rte_eth_dcb_rx_conf.nb_tcs.
> This results in the NIC's RX SRAM not being used and if there is no space on
> SW descriptor ring for packet it is dropped.

Besides ETH_DCB_PFC_SUPPORT, ETH_MQ_RX_DCB_FLAG is also required in
dev_conf.rxmode.mq_mode. After doing that, you will find register PRTDCB_TC2PFC
is also changed.
 
If you don't want to enable DCB, why not just implement that function "i40e_priority_flow_ctrl_set"?
You can change the register in this function without define a new API.


> The advantages of using the PRTDCB_TC2PFC explicitly is that there will be no
> packet loss and descriptor rings do not need to be modified (can be left at
> 128 for rx and 512 for tx as default settings for apps).  Enabling via this
> register allows Burst handling to be within the NIC Rx Buffer and SW rings
> combined.
> At the moment for tests the rx and tx descriptor rings have to be increased
> to 2048 to eliminate packet loss.
> 
> Ideally it would be an optional setting as using it may increase the max
> latency.
> 


Thanks for the clarification.

Thanks
Jingjing

  reply	other threads:[~2016-12-26  8:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-04 13:54 Rory Sexton
2016-12-05  8:44 ` Wu, Jingjing
2016-12-09 14:02   ` Sexton, Rory
2016-12-26  8:45     ` Wu, Jingjing [this message]
2017-01-16 15:52       ` [dpdk-dev] [PATCH v2] " rory.sexton
2017-01-17 15:09         ` Wu, Jingjing
2017-01-19 10:38           ` Sexton, Rory
2017-02-07 15:25             ` Wu, Jingjing
2017-02-09 15:34               ` Ferruh Yigit

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