From: "Hu, Jiayu" <jiayu.hu@intel.com>
To: Maxime Coquelin <maxime.coquelin@redhat.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>
Cc: "Wang, YuanX" <yuanx.wang@intel.com>,
"Xia, Chenbo" <chenbo.xia@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>,
"Jiang, Cheng1" <cheng1.jiang@intel.com>,
"Ma, WenwuX" <wenwux.ma@intel.com>,
"He, Xingguang" <xingguang.he@intel.com>,
Thomas Monjalon <thomas@monjalon.net>,
"Ilya Maximets" <imaximet@redhat.com>,
David Marchand <david.marchand@redhat.com>
Subject: RE: [PATCH v5] net/vhost: support asynchronous data path
Date: Wed, 26 Oct 2022 02:48:02 +0000 [thread overview]
Message-ID: <CY5PR11MB6487F089825D3DDE8547B54E92309@CY5PR11MB6487.namprd11.prod.outlook.com> (raw)
In-Reply-To: <e83bc805-1665-4879-76c9-bb24e70f81ba@redhat.com>
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Wednesday, October 26, 2022 12:05 AM
> To: Richardson, Bruce <bruce.richardson@intel.com>
> Cc: Hu, Jiayu <jiayu.hu@intel.com>; Wang, YuanX <yuanx.wang@intel.com>;
> Xia, Chenbo <chenbo.xia@intel.com>; dev@dpdk.org; Jiang, Cheng1
> <cheng1.jiang@intel.com>; Ma, WenwuX <wenwux.ma@intel.com>; He,
> Xingguang <xingguang.he@intel.com>; Thomas Monjalon
> <thomas@monjalon.net>; Ilya Maximets <imaximet@redhat.com>; David
> Marchand <david.marchand@redhat.com>
> Subject: Re: [PATCH v5] net/vhost: support asynchronous data path
>
>
>
> On 10/25/22 17:44, Bruce Richardson wrote:
> > On Tue, Oct 25, 2022 at 05:33:31PM +0200, Maxime Coquelin wrote:
> >>
> >>
> >> On 10/25/22 11:15, Hu, Jiayu wrote:
> >
> >>>> I think that for Vhost PMD, the Virtio completions should either be
> >>>> performed by DMA engine or by a dedicated thread.
> >>>
> >>> We cannot depend on DMA engine to do completion, as there is no
> >>> ordering guarantee on the HW. For example, given the DMA engine
> >>> issues two updates on the used ring's index, it is possible that the
> >>> second write completes before the first one.
> >>
> >> I'm not sure for Intel hardware, but other vendors may offer ordering
> >> guarantees, it should be exposed as a capability of the DMA device.
> >> If the DMA device offers this capability, it could be used for Vhost.
> >>
> >
> > While I haven't been following this discussion, this particular
> > comment caught my eye.
> >
> > For jobs submitted via a single dmadev device, the "FENCE" flag is
> > provided as part of the dmadev API[1]. Obviously, if the writes come
> > from different dmadevs, then things are rather more complicated.
>
The cost of "FENCE" is significant, as it requires the HW to stop pipeline and
wait until all previous jobs completed. If ask DMA to update used ring's index,
every updating on used ring's index requires "FENCE", which will make enqueue/
dequeue become sync operation finally. "FENCE" would slow down DMA and make
DMA become the bottleneck quickly. Also, stalling HW pipeline also means waste
DMA resource. The more efficient way to maintain the ordering is by SW. I don't
think it is acceptable from performance and resource utilization perspective.
Thanks,
Jiayu
> Thanks for the clarification Bruce.
>
> In the Vhost PMD case, there is a 1:1 mapping between the virtqueue and
> the DMA channel, so we should be fine.
>
> Regards,
> Maxime
>
> > /Bruce
> >
> >
> > [1]
> >
> https://doc.dpdk.org/api/rte__dmadev_8h.html#a3375e7b956b305505073c4
> ff
> > 035afe2f
> >
next prev parent reply other threads:[~2022-10-26 2:48 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-14 15:06 [PATCH] " Jiayu Hu
2022-08-18 2:05 ` [PATCH v2] " Jiayu Hu
2022-08-23 16:35 ` [PATCH v3] " Yuan Wang
2022-09-26 6:55 ` Xia, Chenbo
2022-09-27 7:34 ` Wang, YuanX
2022-09-28 8:13 ` Wang, YuanX
2022-10-10 5:17 ` Hu, Jiayu
2022-10-18 11:59 ` Xia, Chenbo
2022-09-29 19:47 ` [PATCH v4] " Yuan Wang
2022-10-19 14:10 ` Xia, Chenbo
2022-10-20 14:00 ` Wang, YuanX
2022-10-24 15:14 ` [PATCH v5] " Yuan Wang
2022-10-24 9:02 ` Xia, Chenbo
2022-10-24 9:25 ` Wang, YuanX
2022-10-24 9:08 ` Maxime Coquelin
2022-10-25 2:14 ` Hu, Jiayu
2022-10-25 7:52 ` Maxime Coquelin
2022-10-25 9:15 ` Hu, Jiayu
2022-10-25 15:33 ` Maxime Coquelin
2022-10-25 15:44 ` Bruce Richardson
2022-10-25 16:04 ` Maxime Coquelin
2022-10-26 2:48 ` Hu, Jiayu [this message]
2022-10-26 5:00 ` Maxime Coquelin
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