patches for DPDK stable branches
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From: "Tan, Jianfeng" <jianfeng.tan@intel.com>
To: 'Maxime Coquelin' <maxime.coquelin@redhat.com>,
	"dev@dpdk.org" <dev@dpdk.org>,
	"stable@dpdk.org" <stable@dpdk.org>,
	"santosh.shukla@caviumnetworks.com"
	<santosh.shukla@caviumnetworks.com>,
	"Burakov, Anatoly" <anatoly.burakov@intel.com>,
	"thomas@monjalon.net" <thomas@monjalon.net>,
	"stephen@networkplumber.org" <stephen@networkplumber.org>
Cc: "peterx@redhat.com" <peterx@redhat.com>,
	"Zhang, Qi Z" <qi.z.zhang@intel.com>
Subject: Re: [dpdk-stable] [PATCH v2] bus/pci: forbid VA as IOVA mode if IOMMU address width too small
Date: Fri, 12 Jan 2018 03:00:59 +0000	[thread overview]
Message-ID: <ED26CBA2FAD1BF48A8719AEF02201E36513B8177@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <20180109131801.26520-1-maxime.coquelin@redhat.com>



> -----Original Message-----
> From: Maxime Coquelin [mailto:maxime.coquelin@redhat.com]
> Sent: Tuesday, January 9, 2018 9:18 PM
> To: dev@dpdk.org; stable@dpdk.org; Tan, Jianfeng;
> santosh.shukla@caviumnetworks.com; Burakov, Anatoly;
> thomas@monjalon.net; stephen@networkplumber.org
> Cc: peterx@redhat.com; Maxime Coquelin
> Subject: [PATCH v2] bus/pci: forbid VA as IOVA mode if IOMMU address
> width too small
> 
> Intel VT-d supports different address widths for the IOVAs, from
> 39 bits to 56 bits.
> 
> While recent processors support at least 48 bits, VT-d emulation
> currently only supports 39 bits. It makes DMA mapping to fail in this
> case when using VA as IOVA mode, as user-space virtual addresses uses
> up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt).
> 
> This patch parses VT-d CAP register value available in sysfs, and
> forbid VA as IOVA mode if the GAW is 39 bits or unknown.
> 
> Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs")
> 
> Cc: stable@dpdk.org
> Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>

I don't have strong objection on this patch. Plus, this patch has been verified with --no-huge, and Intel low-end processors (with the help of Zhang Qi).

Tested-by: Jianfeng Tan <jianfeng.tan@intel.com>

> ---
> 
> Changes in v2:
> ==============
> - Rework pci_one_device_iommu_support_va #ifdefery (Stephen)
> - Don't inline introduced functions (Stephen)
> 
>  drivers/bus/pci/linux/pci.c | 108
> ++++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 99 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
> index 25f907e04..0a43c4b89 100644
> --- a/drivers/bus/pci/linux/pci.c
> +++ b/drivers/bus/pci/linux/pci.c
> @@ -547,6 +547,100 @@ pci_one_device_has_iova_va(void)
>  	return 0;
>  }
> 
> +#if defined(RTE_ARCH_X86)
> +static bool
> +pci_one_device_iommu_support_va(struct rte_pci_device *dev)
> +{
> +#define VTD_CAP_SAGAW_SHIFT         8
> +#define VTD_CAP_SAGAW_MASK          (0x1fULL <<
> VTD_CAP_SAGAW_SHIFT)
> +#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
> +	struct rte_pci_addr *addr = &dev->addr;
> +	char filename[PATH_MAX];
> +	FILE *fp;
> +	uint64_t sagaw, vtd_cap_reg = 0;
> +	int guest_addr_width = 0;
> +
> +	snprintf(filename, sizeof(filename),
> +		 "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
> +		 rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr-
> >devid,
> +		 addr->function);
> +	if (access(filename, F_OK) == -1) {
> +		/* We don't have an Intel IOMMU, assume VA supported*/

A nitpick: missed a space between "supported" and "*/"

Thanks,
Jianfeng

  parent reply	other threads:[~2018-01-12  3:01 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-09 13:18 Maxime Coquelin
2018-01-11 20:19 ` Maxime Coquelin
2018-01-12  1:15   ` Tan, Jianfeng
2018-01-12  3:00 ` Tan, Jianfeng [this message]
2018-01-12  3:28   ` Zhang, Qi Z
2018-01-12  3:56 ` [dpdk-stable] [dpdk-dev] " Zhang, Qi Z
2018-01-12  8:21   ` Maxime Coquelin

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