From: "Xu, Rosen" <rosen.xu@intel.com>
To: Shreyansh Jain <shreyansh.jain@nxp.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
"Doherty, Declan" <declan.doherty@intel.com>,
"Richardson, Bruce" <bruce.richardson@intel.com>,
"Yigit, Ferruh" <ferruh.yigit@intel.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Zhang, Tianfei" <tianfei.zhang@intel.com>,
"Wu, Hao" <hao.wu@intel.com>,
"gaetan.rivet@6wind.com" <gaetan.rivet@6wind.com>
Subject: Re: [dpdk-dev] [PATCH v4 1/3] Add Intel FPGA BUS Lib Code
Date: Wed, 4 Apr 2018 01:44:18 +0000 [thread overview]
Message-ID: <0E78D399C70DA940A335608C6ED296D739F33D54@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <b0930ad6-8da4-7e6f-656b-e37118d7b5e3@nxp.com>
Hello Shreyansh,
> -----Original Message-----
> From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com]
> Sent: Tuesday, April 03, 2018 17:25
> To: Xu, Rosen <rosen.xu@intel.com>
> Cc: dev@dpdk.org; Doherty, Declan <declan.doherty@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>; Yigit, Ferruh
> <ferruh.yigit@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; Zhang, Tianfei <tianfei.zhang@intel.com>;
> Wu, Hao <hao.wu@intel.com>; gaetan.rivet@6wind.com
> Subject: Re: [dpdk-dev] [PATCH v4 1/3] Add Intel FPGA BUS Lib Code
>
> Hello Rosen,
>
> On Saturday 31 March 2018 09:33 PM, Rosen Xu wrote:
> > Signed-off-by: Rosen Xu <rosen.xu@intel.com>
> > ---
> > config/common_base | 5 +
> > drivers/bus/Makefile | 1 +
> > drivers/bus/ifpga/Makefile | 33 ++
> > drivers/bus/ifpga/ifpga_bus.c | 517
> ++++++++++++++++++++++++++++
> > drivers/bus/ifpga/ifpga_common.c | 141 ++++++++
> > drivers/bus/ifpga/ifpga_common.h | 22 ++
> > drivers/bus/ifpga/ifpga_logs.h | 31 ++
> > drivers/bus/ifpga/rte_bus_ifpga.h | 175 ++++++++++
> > drivers/bus/ifpga/rte_bus_ifpga_version.map | 8 +
> > mk/rte.app.mk | 2 +
> > 10 files changed, 935 insertions(+)
> > create mode 100644 drivers/bus/ifpga/Makefile
> > create mode 100644 drivers/bus/ifpga/ifpga_bus.c
> > create mode 100644 drivers/bus/ifpga/ifpga_common.c
> > create mode 100644 drivers/bus/ifpga/ifpga_common.h
> > create mode 100644 drivers/bus/ifpga/ifpga_logs.h
> > create mode 100644 drivers/bus/ifpga/rte_bus_ifpga.h
> > create mode 100644 drivers/bus/ifpga/rte_bus_ifpga_version.map
> >
> > diff --git a/config/common_base b/config/common_base index
> > ad03cf4..49f6b09 100644
> > --- a/config/common_base
> > +++ b/config/common_base
> > @@ -134,6 +134,11 @@ CONFIG_RTE_LIBRTE_PCI_BUS=y
> > CONFIG_RTE_LIBRTE_VDEV_BUS=y
> >
> > #
> > +# Compile the Intel FPGA bus
> > +#
> > +CONFIG_RTE_LIBRTE_IFPGA_BUS=y
> > +
> > +#
> > # Compile ARK PMD
> > #
> > CONFIG_RTE_LIBRTE_ARK_PMD=y
> > diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index
> > 7ef2593..55d2dfe 100644
> > --- a/drivers/bus/Makefile
> > +++ b/drivers/bus/Makefile
> > @@ -7,5 +7,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += dpaa
> > DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc
> > DIRS-$(CONFIG_RTE_LIBRTE_PCI_BUS) += pci
> > DIRS-$(CONFIG_RTE_LIBRTE_VDEV_BUS) += vdev
> > +DIRS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga
>
> When I attempted to compile the above using SHARED_LIB=y, this is what I
> got:
>
> --->8---
> LD librte_bus_ifpga.so.1.1
> ifpga_bus.o: In function `rte_ifpga_parse':
> ifpga_bus.c:(.text+0x2eb): undefined reference to `rte_rawdevs'
> ifpga_bus.o: In function `rte_ifpga_scan':
> ifpga_bus.c:(.text+0x53e): undefined reference to `rte_kvargs_parse'
> ifpga_bus.c:(.text+0x55e): undefined reference to `rte_kvargs_count'
> ifpga_bus.c:(.text+0x580): undefined reference to `rte_kvargs_process'
> ifpga_bus.c:(.text+0x5e0): undefined reference to `rte_rawdevs'
> ifpga_bus.c:(.text+0x746): undefined reference to `rte_kvargs_free'
> ifpga_bus.c:(.text+0x7b8): undefined reference to `rte_pci_addr_cmp'
> ifpga_bus.c:(.text+0x858): undefined reference to `rte_kvargs_parse'
> ifpga_bus.c:(.text+0x878): undefined reference to `rte_kvargs_count'
> ifpga_bus.c:(.text+0x89c): undefined reference to `rte_kvargs_process'
> ifpga_bus.c:(.text+0x8b8): undefined reference to `rte_kvargs_count'
> ifpga_bus.c:(.text+0x8dc): undefined reference to `rte_kvargs_process'
> ifpga_bus.c:(.text+0x8f8): undefined reference to `rte_kvargs_count'
> ifpga_bus.c:(.text+0x91c): undefined reference to `rte_kvargs_process'
> ifpga_bus.c:(.text+0x981): undefined reference to `rte_kvargs_free'
> ifpga_common.o: In function `ifpga_pci_addr_cmp':
> ifpga_common.c:(.text+0x2c5): undefined reference to
> `rte_eal_compare_pci_addr'
> collect2: error: ld returned 1 exit status
> /home/shreyansh/build/DPDK/00_dpdk/mk/rte.lib.mk:98: recipe for target
> 'librte_bus_ifpga.so.1.1' failed
> make[6]: *** [librte_bus_ifpga.so.1.1] Error 1
> /home/shreyansh/build/DPDK/00_dpdk/mk/rte.subdir.mk:35: recipe for
> target 'ifpga' failed
> make[5]: *** [ifpga] Error 2
> --->8---
I have fixed it to modify Makefile in my PATCH v5.
> Essentially, you are dependent on librte_kvargs but you have not declared
> that in your Makefile. Same for lib_rawdev.
I have declared it in my PATCH v5.
> >
> > include $(RTE_SDK)/mk/rte.subdir.mk
> > diff --git a/drivers/bus/ifpga/Makefile b/drivers/bus/ifpga/Makefile
> > new file mode 100644 index 0000000..1b569af
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/Makefile
> > @@ -0,0 +1,33 @@
> > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel
> > +Corporation
> > +
> > +include $(RTE_SDK)/mk/rte.vars.mk
> > +
> > +#
> > +# library name
> > +#
> > +LIB = librte_bus_ifpga.a
> > +
> > +CFLAGS += -O3
> > +CFLAGS += $(WERROR_FLAGS)
> > +
> > +# versioning export map
> > +EXPORT_MAP := rte_bus_ifpga_version.map
> > +
> > +# library version
> > +LIBABIVER := 1
> > +
> > +VPATH += $(SRCDIR)/base
> > +
> > +SRCS-y += \
> > + ifpga_bus.c \
> > + ifpga_common.c
> > +
> > +LDLIBS += -lrte_eal
> > +
> > +#
> > +# Export include files
> > +#
> > +SYMLINK-y-include += rte_bus_ifpga.h
> > +
> > +include $(RTE_SDK)/mk/rte.lib.mk
> > diff --git a/drivers/bus/ifpga/ifpga_bus.c
> > b/drivers/bus/ifpga/ifpga_bus.c new file mode 100644 index
> > 0000000..eba2615
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/ifpga_bus.c
> > @@ -0,0 +1,517 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
>
> [...]
>
> > +
> > + if (rawdev->dev_ops &&
> > + rawdev->dev_ops->dev_start &&
> > + rawdev->dev_ops->dev_start(rawdev))
> > + goto free_dev;
> > + if (path) {
> > + strncpy(afu_pr_conf.bs_path, path, strlen(path));
>
> strncpy with demarcation based on source is not right. strlen(path) can be
> larger than afu_pr_conf.bs_path
I have changed to destination string in PATCH v5.
> I saw some comment from Gaetan in previous version, if I recall correctly.
>
> > + if (rawdev->dev_ops->firmware_load &&
> > + rawdev->dev_ops->firmware_load(rawdev,
> > + &afu_pr_conf)){
> > + printf("firmware load error %d\n", ret);
> > + goto free_dev;
> > + }
> > + afu_dev->id.uuid_low = afu_pr_conf.afu_id.uuid_low;
> > + afu_dev->id.uuid_high = afu_pr_conf.afu_id.uuid_high;
> > + }
> > +
> > + return afu_dev;
> > +
> > +free_dev:
> > + free(afu_dev);
> > +end:
> > + if (kvlist)
> > + rte_kvargs_free(kvlist);
> > + if (path)
> > + free(path);
> > +
> > + return NULL;
> > +}
> > +
> > +/*
> > + * Scan the content of the FPGA bus, and the devices in the devices
> > + * list
> > + */
> > +static int
> > +rte_ifpga_scan(void)
> > +{
>
> [...]
>
> > +
> > +static int
> > +ifpga_probe_all_drivers(struct rte_afu_device *afu_dev) {
> > + struct rte_afu_driver *drv = NULL;
> > + int rc;
> > +
> > + if (afu_dev == NULL)
> > + return -1;
> > +
> > + /* Check if a driver is already loaded */
> > + if (afu_dev->driver != NULL)
> > + return 0;
> > +
> > + TAILQ_FOREACH(drv, &rte_ifpga_bus.driver_list, next) {
> > + rc = ifpga_probe_one_driver(drv, afu_dev);
> > + if (rc < 0)
> > + /* negative value is an error */
> > + return -1;
> > + if (rc > 0)
> > + /* positive value means driver doesn't support it */
> > + continue;
> > + return 0;
> > + }
> > + return 1;
> > +}
> > +
> > +/*
> > + * Scan the content of the PCI bus, and call the probe() function for
>
> I think you are not moving on PCI bus elements. You are looping on
> rte_ifpga_bus.
I have modified all PCI bus elements to FPGA BUS in my PATCH v5.
> > + * all registered drivers that have a matching entry in its id_table
> > + * for discovered devices.
> > + */
> > +static int
> > +rte_ifpga_probe(void)
> > +{
> > + struct rte_ifpga_device *ifpga_dev;
> > + struct rte_afu_device *afu_dev = NULL;
> > + int ret = 0;
> > +
> > + TAILQ_FOREACH(ifpga_dev, &rte_ifpga_bus.ifpga_list, next) {
> > + TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) {
> > +
> > + if (afu_dev->device.driver)
> > + continue;
> > +
> > + ret = ifpga_probe_all_drivers(afu_dev);
> > + if (ret < 0)
> > + IFPGA_BUS_ERR("failed to initialize %s
> device\n",
> > + rte_ifpga_device_name(afu_dev));
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
>
> [...]
>
> > diff --git a/drivers/bus/ifpga/ifpga_common.c
> > b/drivers/bus/ifpga/ifpga_common.c
> > new file mode 100644
> > index 0000000..124ffd2
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/ifpga_common.c
> > @@ -0,0 +1,141 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
>
> [...]
>
> > +
> > +}
> > +int ifpga_get_bdf_arg(const char *key __rte_unused,
> > + const char *value, void *extra_args) { #define MAX_PATH_LEN 1024
>
> Is this max len of a file path or a max len of the value string (BDF).
> Can you rename this?
I will rename it to IFPGA_MAX_BDF_LEN in my PATCH v5.
> Just a trivial comment, though.
>
> [...]
>
> > diff --git a/drivers/bus/ifpga/ifpga_logs.h
> > b/drivers/bus/ifpga/ifpga_logs.h new file mode 100644 index
> > 0000000..873e0a4
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/ifpga_logs.h
> > @@ -0,0 +1,31 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
> > +#ifndef _IFPGA_LOGS_H_
> > +#define _IFPGA_LOGS_H_
> > +
> > +#include <rte_log.h>
> > +
> > +extern int ifpga_bus_logtype;
> > +
> > +#define IFPGA_LOG(level, fmt, args...) \
> > + rte_log(RTE_LOG_ ## level, ifpga_bus_logtype, "%s(): " fmt "\n", \
> > + __func__, ##args)
>
> I don't see macro above being used. Would you be using this in later patches?
> (But, i think they might have their own logging definitions).
Yes, they will be used in later patches.
For FPGA BUS is a common module, so we need to provide all macros will be used.
> > +
> > +#define IFPGA_BUS_LOG(level, fmt, args...) \
> > + rte_log(RTE_LOG_ ## level, ifpga_bus_logtype, "%s(): " fmt "\n", \
> > + __func__, ##args)
> > +
> > +#define IFPGA_BUS_FUNC_TRACE() IFPGA_BUS_LOG(DEBUG, ">>")
> > +
> > +#define IFPGA_BUS_DEBUG(fmt, args...) \
> > + IFPGA_BUS_LOG(DEBUG, fmt, ## args)
> > +#define IFPGA_BUS_INFO(fmt, args...) \
> > + IFPGA_BUS_LOG(INFO, fmt, ## args)
> > +#define IFPGA_BUS_ERR(fmt, args...) \
> > + IFPGA_BUS_LOG(ERR, fmt, ## args)
> > +#define IFPGA_BUS_WARN(fmt, args...) \
> > + IFPGA_BUS_LOG(WARNING, fmt, ## args)
> > +
> > +#endif /* _IFPGA_BUS_LOGS_H_ */
> > diff --git a/drivers/bus/ifpga/rte_bus_ifpga.h
> > b/drivers/bus/ifpga/rte_bus_ifpga.h
> > new file mode 100644
> > index 0000000..e22ab4e
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/rte_bus_ifpga.h
> > @@ -0,0 +1,175 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2010-2018 Intel Corporation */
> > +
> > +#ifndef _RTE_BUS_IFPGA_H_
> > +#define _RTE_BUS_IFPGA_H_
> > +
> > +/**
> > + * @file
> > + *
> > + * RTE PCI Bus Interface
>
> This is not a "RTE PCI Bus Interface" - It should be AFU/IFPA Bus interface file
I will modify it in PATCH v5.
> There are some comments which were given in early versions. Like this one.
> Please do respond to those individually if you are not fixing them.
> (Also, it is nice to get acknowledgment of those which are being fixed).
I have fix those comments and I also will reply it to those individually.
> > + */
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
> > +
> > +#include <rte_bus.h>
> > +#include <rte_pci.h>
> > +
> > +/** Name of Intel FPGA Bus */
> > +#define IFPGA_BUS_NAME ifpga
> > +
> > +/* Forward declarations */
> > +struct rte_ifpga_device;
> > +struct rte_afu_device;
> > +struct rte_afu_driver;
> > +
> > +/** List of Intel FPGA devices */
> > +TAILQ_HEAD(rte_ifpga_device_list, rte_ifpga_device);
> > +/** List of Intel AFU devices */
> > +TAILQ_HEAD(rte_afu_device_list, rte_afu_device);
> > +/** List of AFU drivers */
> > +TAILQ_HEAD(rte_afu_driver_list, rte_afu_driver);
> > +
> > +#define IFPGA_BUS_BITSTREAM_PATH_MAX_LEN 256
> > +
> > +struct rte_afu_uuid {
> > + uint64_t uuid_low;
> > + uint64_t uuid_high;
> > +} __attribute__ ((packed));
> > +
> > +#define IFPGA_BUS_DEV_PORT_MAX 4
> > +
> > +/**
> > + * A structure describing an ID for a AFU driver. Each driver
> > +provides a
> > + * table of these IDs for each device that it supports.
> > + */
> > +struct rte_afu_id {
> > + struct rte_pci_addr pci_addr;
> > + uint64_t uuid_low;
> > + uint64_t uuid_high;
> > + int port;
> > +} __attribute__ ((packed));
> > +
> > +/**
> > + * A structure pr configuration AFU driver.
> > + */
> > +
> > +struct rte_afu_pr_conf {
> > + struct rte_afu_id afu_id;
> > + int pr_enable;
> > + char bs_path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];
> ^^^^^^^^^^^
> Some stray indentation issue, it seems
Do you means to change it to:
char bs_path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];?
If so I have fixed it in my PATCH v5.
> > +};
> > +
> > +#define AFU_PRI_STR_SIZE (PCI_PRI_STR_SIZE + 8)
> > +
> > +/**
> > + * A structure describing a fpga device.
> > + */
> > +struct rte_ifpga_device {
> > + TAILQ_ENTRY(rte_ifpga_device) next; /**< Next in device list. */
> > + struct rte_pci_addr pci_addr;
> > + struct rte_rawdev *rdev;
> > + struct rte_afu_device_list afu_list; /**< List of AFU devices */ };
> > +
> > +/**
> > + * A structure describing a AFU device.
> > + */
> > +struct rte_afu_device {
> > + TAILQ_ENTRY(rte_afu_device) next; /**< Next in device list. */
> > + struct rte_device device; /**< Inherit core device */
> > + struct rte_rawdev *rawdev; /**< Point Rawdev */
> > + struct rte_ifpga_device *ifpga_dev; /**< Point ifpga device */
> > + struct rte_afu_id id; /**< AFU id within FPGA. */
> > + uint32_t num_region; /**< number of regions found */
> > + struct rte_mem_resource mem_resource[PCI_MAX_RESOURCE];
> > + /**< PCI Memory Resource
> */
> > + struct rte_intr_handle intr_handle; /**< Interrupt handle */
> > + struct rte_afu_driver *driver; /**< Associated driver */
> > + char path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN];
> > +} __attribute__ ((packed));
> > +
> > +/**
> > + * @internal
> > + * Helper macro for drivers that need to convert to struct rte_afu_device.
> > + */
> > +#define RTE_DEV_TO_AFU(ptr) \
> > + container_of(ptr, struct rte_afu_device, device)
> > +
> > +/**
> > + * Initialisation function for the driver called during PCI probing.
>
> PCI Probing would have already been done through the PCI bus. I think this is
> probing of the AFU devices (based on the PCI already probed).
rte_ifpga_plug()/rte_ifpga_unplug() will use this macro.
> > + */
> > +typedef int (afu_probe_t)(struct rte_afu_device *);
> > +
> > +/**
> > + * Uninitialisation function for the driver called during hotplugging.
> > + */
> > +typedef int (afu_remove_t)(struct rte_afu_device *);
> > +
> > +/**
> > + * A structure describing a PCI device.
> ^^^^
> Structure describing an AFU device.
Yes, it should be AFU device, and I have fixed it in my PATCH v5.
> > + */
> > +struct rte_afu_driver {
> > + TAILQ_ENTRY(rte_afu_driver) next; /**< Next afu driver. */
> > + struct rte_driver driver; /**< Inherit core driver. */
> > + afu_probe_t *probe; /**< Device Probe function. */
> > + afu_remove_t *remove; /**< Device Remove function. */
> > + const struct rte_afu_uuid *id_table; /**< AFU uuid within FPGA. */
> > + uint32_t drv_flags; /**< Flags contolling handling of device. */
> > +};
> > +
> > +/**
> > + * Structure describing the Intel FPGA bus */ struct rte_ifpga_bus {
> > + struct rte_bus bus; /**< Inherit the generic class */
> > + struct rte_ifpga_device_list ifpga_list; /**< List of FPGA devices */
> > + struct rte_afu_driver_list driver_list; /**< List of FPGA drivers
> > +*/ };
> > +
> > +static inline const char *
> > +rte_ifpga_device_name(const struct rte_afu_device *afu) {
> > + if (afu && afu->device.name)
> > + return afu->device.name;
> > + return NULL;
> > +}
> > +
> > +extern struct rte_ifpga_bus rte_ifpga_bus;
> > +
> > +/**
> > + * Register a ifpga afu device driver.
> > + *
> > + * @param driver
> > + * A pointer to a rte_afu_driver structure describing the driver
> > + * to be registered.
> > + */
> > +void rte_ifpga_driver_register(struct rte_afu_driver *driver);
> > +
> > +/**
> > + * Unregister a ifpga afu device driver.
> > + *
> > + * @param driver
> > + * A pointer to a rte_afu_driver structure describing the driver
> > + * to be unregistered.
> > + */
> > +void rte_ifpga_driver_unregister(struct rte_afu_driver *driver);
> > +
> > +#define RTE_PMD_REGISTER_AFU(nm, afudrv)\ RTE_INIT(afudrvinitfn_
> > +##afudrv);\ static const char *afudrvinit_ ## nm ## _alias;\ static
> > +void afudrvinitfn_ ##afudrv(void)\ {\
> > + (afudrv).driver.name = RTE_STR(nm);\
> > + (afudrv).driver.alias = afudrvinit_ ## nm ## _alias;\
> > + rte_ifpga_driver_register(&afudrv);\
> > +} \
> > +RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
> > +
> > +#define RTE_PMD_REGISTER_AFU_ALIAS(nm, alias)\ static const char
> > +*afudrvinit_ ## nm ## _alias = RTE_STR(alias)
> > +
> > +#endif /* _RTE_BUS_IFPGA_H_ */
> > diff --git a/drivers/bus/ifpga/rte_bus_ifpga_version.map
> > b/drivers/bus/ifpga/rte_bus_ifpga_version.map
> > new file mode 100644
> > index 0000000..4edc9c0
> > --- /dev/null
> > +++ b/drivers/bus/ifpga/rte_bus_ifpga_version.map
> > @@ -0,0 +1,8 @@
> > +DPDK_18.05 {
> > + global:
> > +
> > + rte_ifpga_driver_register;
> > + rte_ifpga_driver_unregister;
>
> Should be tab indented
Yes, I will fix them.
> > +
> > + local: *;
> > +};
>
> [...]
>
> One suggestion:
>
> I think a lot of comments were provided by Gaetan in the previous version. I
> see some that some of them are still not fixed in this version.
>
> I suggest you individually reply to his comments if you are not going to fix,
> with reason. He put quite an effort to go through your patches.
>
> That would help you track comments as well as not discount a reviewers
> effort.
OK, I will individually reply to Gaetan's comments.
> -
> Shreyansh
next prev parent reply other threads:[~2018-04-04 1:44 UTC|newest]
Thread overview: 149+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 13:45 [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-20 13:45 ` [dpdk-dev] [PATCH V1 5/5] Add Intel OPAE Share Code Rosen Xu
2018-03-20 14:58 ` [dpdk-dev] [PATCH V1 0/5] Introduce Intel FPGA BUS Gaëtan Rivet
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 0/6] " Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 1/6] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-28 13:26 ` Gaëtan Rivet
2018-03-31 16:25 ` Xu, Rosen
2018-04-04 1:58 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 2/6] config/common_base: Add Intel FPGA Build Configuration Macro Rosen Xu
2018-03-28 13:27 ` Gaëtan Rivet
2018-03-31 16:26 ` Xu, Rosen
2018-04-04 2:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 3/6] mk/rte.app.mk: Add Intel FPGA Bus Build Configuration Macro To App Script Rosen Xu
2018-03-28 13:28 ` Gaëtan Rivet
2018-03-31 16:27 ` Xu, Rosen
2018-04-04 2:02 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 4/6] drivers/bus: Add Intel FPGA Bus Lib Code Rosen Xu
2018-03-28 13:52 ` Gaëtan Rivet
2018-03-31 16:31 ` Xu, Rosen
2018-04-02 4:25 ` Xu, Rosen
2018-04-02 4:31 ` Xu, Rosen
2018-04-04 4:01 ` Xu, Rosen
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 5/6] drivers/raw/ifpga_rawdev: Add Intel FPGA Rawdev Driver Code Rosen Xu
2018-03-28 9:29 ` [dpdk-dev] [PATCH v3 6/6] drivers/raw/ifpga_rawdev: Add Intel FPGA OPAE Share Code Rosen Xu
2018-03-28 9:37 ` [dpdk-dev] [PATCH v3 0/6] Introduce Intel FPGA BUS Bruce Richardson
2018-03-28 13:17 ` Gaëtan Rivet
2018-03-28 16:15 ` Zhang, Tianfei
2018-04-04 1:57 ` Xu, Rosen
2018-03-31 16:02 ` [dpdk-dev] [PATCH v4 0/3] " Rosen Xu
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 1/3] Add Intel FPGA BUS Lib Code Rosen Xu
2018-04-03 9:25 ` Shreyansh Jain
2018-04-04 1:44 ` Xu, Rosen [this message]
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-03 9:34 ` Shreyansh Jain
2018-04-04 1:49 ` Xu, Rosen
2018-04-04 11:31 ` Shreyansh Jain
2018-04-26 10:47 ` Xu, Rosen
2018-03-31 16:03 ` [dpdk-dev] [PATCH v4 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 1/3] Add Intel FPGA BUS Library Rosen Xu
2018-04-04 9:55 ` Bruce Richardson
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 2/3] Add Intel FPGA BUS Rawdev Driver Rosen Xu
2018-04-04 6:51 ` [dpdk-dev] [PATCH v5 3/3] Add Intel FPGA OPAE Share Code Rosen Xu
2018-04-04 11:59 ` Hemant Agrawal
2018-04-26 10:45 ` Xu, Rosen
2018-04-04 10:14 ` [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS Shreyansh Jain
2018-04-04 10:38 ` Richardson, Bruce
2018-04-04 11:11 ` Shreyansh Jain
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 0/5] " Xu, Rosen
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 1/5] iFPGA: Add Intel FPGA BUS Library Xu, Rosen
2018-05-02 13:14 ` Shreyansh Jain
2018-05-02 13:33 ` Zhang, Tianfei
2018-05-03 3:58 ` Tan, Jianfeng
2018-05-03 8:12 ` Tan, Jianfeng
2018-05-03 8:35 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-04 9:14 ` Shreyansh Jain
2018-05-04 9:04 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 4/5] iFPGA: add meson build Xu, Rosen
2018-05-02 9:46 ` Shreyansh Jain
2018-05-02 13:36 ` Zhang, Tianfei
2018-05-03 9:13 ` Shreyansh Jain
2018-05-03 15:12 ` Zhang, Tianfei
2018-04-26 9:43 ` [dpdk-dev] [PATCH v6 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-04 14:10 ` [dpdk-dev] [PATCH v7 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-05 18:42 ` Shreyansh Jain
2018-05-06 0:28 ` Zhang, Tianfei
2018-05-05 19:09 ` Shreyansh Jain
2018-05-06 0:52 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 4/5] iFPGA: add meson build Xu, Rosen
2018-05-05 18:21 ` Shreyansh Jain
2018-05-06 0:27 ` Zhang, Tianfei
2018-05-04 14:11 ` [dpdk-dev] [PATCH v7 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-05 19:19 ` Shreyansh Jain
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 0/5] Introduce Intel FPGA BUS Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 1/5] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 2/5] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 4/5] iFPGA: add meson build Xu, Rosen
2018-05-06 8:40 ` [dpdk-dev] [PATCH v8 5/5] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-06 11:54 ` Shreyansh Jain
2018-05-06 14:24 ` Zhang, Tianfei
2018-05-08 14:18 ` [dpdk-dev] [PATCH v9 0/4] Introduce Intel FPGA BUS Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 1/4] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-08 14:42 ` Thomas Monjalon
2018-05-09 1:25 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 2/4] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-08 14:45 ` Thomas Monjalon
2018-05-09 1:24 ` Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 3/4] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-08 14:19 ` [dpdk-dev] [PATCH v9 4/4] iFPGA: add document for iFPGA driver Xu, Rosen
2018-05-08 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 8:43 ` Wu, Jingjing
2018-05-10 12:20 ` Xu, Rosen
2018-05-10 22:39 ` Wu, Jingjing
2018-05-11 3:18 ` Xu, Rosen
2018-05-10 12:26 ` Zhang, Qi Z
2018-05-10 13:29 ` Xu, Rosen
2018-05-10 13:48 ` Zhang, Qi Z
2018-05-10 13:58 ` Xu, Rosen
2018-05-10 14:11 ` Zhang, Qi Z
2018-05-10 13:51 ` Xu, Rosen
2018-05-10 13:58 ` Zhang, Qi Z
2018-05-10 14:49 ` Thomas Monjalon
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-09 7:43 ` [dpdk-dev] [PATCH v10 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-09 14:47 ` Thomas Monjalon
2018-05-09 15:33 ` Zhang, Tianfei
2018-05-09 15:37 ` Bruce Richardson
2018-05-09 15:57 ` Zhang, Tianfei
2018-05-10 13:31 ` Xu, Rosen
2018-05-10 9:21 ` Wu, Jingjing
2018-05-10 13:16 ` Xu, Rosen
2018-05-11 3:21 ` Xu, Rosen
2018-05-10 14:24 ` Zhang, Qi Z
2018-05-11 3:16 ` Xu, Rosen
2018-05-11 5:36 ` Zhang, Qi Z
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-10 14:00 ` [dpdk-dev] [PATCH v11 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 1/3] bus/ifpga: Add Intel FPGA BUS Library Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 2/3] iFPGA: Add Intel FPGA OPAE Share Code Xu, Rosen
2018-05-11 8:31 ` [dpdk-dev] [PATCH v12 3/3] iFPGA: Add Intel FPGA BUS Rawdev Driver Xu, Rosen
2018-05-11 12:11 ` [dpdk-dev] [PATCH v12 0/3] Introduce Intel FPGA BUS Zhang, Qi Z
2018-05-11 13:45 ` Xu, Rosen
2018-05-11 15:12 ` Thomas Monjalon
2018-05-14 9:58 ` [dpdk-dev] [PATCH] raw/ifpga/base: fix compile error on ia32 icc compiler Xu, Rosen
2018-05-14 10:20 ` De Lara Guarch, Pablo
2018-05-14 10:32 ` Thomas Monjalon
2018-05-16 13:48 ` [dpdk-dev] [PATCH] drivers/bus/ifpga/: fix Coverity issue Rosen Xu
2018-05-21 14:00 ` [dpdk-dev] [dpdk-stable] " Thomas Monjalon
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 1/3] bus/ifpga: fix error control flow issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 2/3] bus/ifpga: fix resource leaks issue Rosen Xu
2018-05-22 10:26 ` [dpdk-dev] [PATCH v2 3/3] bus/ifpga: fix null pointer dereferences issue Rosen Xu
2018-05-22 15:15 ` [dpdk-dev] [PATCH v2 0/3] Fix bus/ifpga coverity issue: 279455, 279459 and 279454 Thomas Monjalon
2018-05-23 0:26 ` Xu, Rosen
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