From: <xuelin.shi@freescale.com>
To: <thomas.monjalon@6wind.com>
Cc: dev@dpdk.org
Subject: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue
Date: Thu, 12 Feb 2015 09:19:50 +0800 [thread overview]
Message-ID: <1423703990-29031-1-git-send-email-xuelin.shi@freescale.com> (raw)
From: Xuelin Shi <xuelin.shi@freescale.com>
ixgbe is little endian, but cpu maybe not.
add necessary conversions.
rte_cpu_to_le_32(...) for PCI write
rte_le_to_cpu_32(...) for PCI read.
Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com>
---
lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
index 2d40bfd..f8bfb3f 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
@@ -119,11 +119,11 @@ typedef int bool;
static inline uint32_t ixgbe_read_addr(volatile void* addr)
{
- return IXGBE_PCI_REG(addr);
+ return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
}
#define IXGBE_PCI_REG_WRITE(reg, value) do { \
- IXGBE_PCI_REG((reg)) = (value); \
+ IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
} while(0)
#define IXGBE_PCI_REG_ADDR(hw, reg) \
--
1.9.1
next reply other threads:[~2015-02-12 2:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-12 1:19 xuelin.shi [this message]
2015-02-20 10:53 ` Thomas Monjalon
2015-03-25 6:33 ` Zhang, Helin
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