From: Ouyang Changchun <changchun.ouyang@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 31/36] ixgbe base codes: Bit-bang mode
Date: Thu, 12 Feb 2015 20:01:03 +0800 [thread overview]
Message-ID: <1423742468-30404-32-git-send-email-changchun.ouyang@intel.com> (raw)
In-Reply-To: <1423742468-30404-1-git-send-email-changchun.ouyang@intel.com>
Support the bit-bang mode on X550;
And negate I2C output enable;
Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
---
lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c | 66 +++++++++++++++++++++++++++++++--
lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 6 +++
2 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
index dc58f66..4a3463a 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
@@ -2103,6 +2103,7 @@ write_byte_out:
* @hw: pointer to hardware structure
*
* Sets I2C start condition (High -> Low on SDA while SCL is High)
+ * Set bit-bang mode on X550 hardware.
**/
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
{
@@ -2110,6 +2111,8 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_i2c_start");
+ i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
+
/* Start condition must begin with data and clock high */
ixgbe_set_i2c_data(hw, &i2cctl, 1);
ixgbe_raise_i2c_clk(hw, &i2cctl);
@@ -2134,10 +2137,15 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
* @hw: pointer to hardware structure
*
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
+ * Disables bit-bang mode and negates data output enable on X550
+ * hardware.
**/
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
+ u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
+ u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
DEBUGFUNC("ixgbe_i2c_stop");
@@ -2152,6 +2160,13 @@ STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
/* bus free time between stop and start (4.7us)*/
usec_delay(IXGBE_I2C_T_BUF);
+
+ if (bb_en_bit || data_oe_bit || clk_oe_bit) {
+ i2cctl &= ~bb_en_bit;
+ i2cctl |= data_oe_bit | clk_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ }
}
/**
@@ -2168,6 +2183,7 @@ STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
DEBUGFUNC("ixgbe_clock_in_i2c_byte");
+ *data = 0;
for (i = 7; i >= 0; i--) {
ixgbe_clock_in_i2c_bit(hw, &bit);
*data |= bit << i;
@@ -2203,6 +2219,7 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
/* Release SDA line (set high) */
i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
+ i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
IXGBE_WRITE_FLUSH(hw);
@@ -2217,6 +2234,7 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
**/
STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
s32 status = IXGBE_SUCCESS;
u32 i = 0;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
@@ -2225,9 +2243,14 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
DEBUGFUNC("ixgbe_get_i2c_ack");
+ if (data_oe_bit) {
+ i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
+ i2cctl |= data_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ }
ixgbe_raise_i2c_clk(hw, &i2cctl);
-
/* Minimum high period of clock is 4us */
usec_delay(IXGBE_I2C_T_HIGH);
@@ -2265,9 +2288,16 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
DEBUGFUNC("ixgbe_clock_in_i2c_bit");
+ if (data_oe_bit) {
+ i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
+ i2cctl |= data_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ }
ixgbe_raise_i2c_clk(hw, &i2cctl);
/* Minimum high period of clock is 4us */
@@ -2326,15 +2356,22 @@ STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
* @i2cctl: Current value of I2CCTL register
*
* Raises the I2C clock line '0'->'1'
+ * Negates the I2C clock output enable on X550 hardware.
**/
STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
+ u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
u32 i = 0;
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
u32 i2cctl_r = 0;
DEBUGFUNC("ixgbe_raise_i2c_clk");
+ if (clk_oe_bit) {
+ *i2cctl |= clk_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
+ }
+
for (i = 0; i < timeout; i++) {
*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
@@ -2355,13 +2392,14 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
* @i2cctl: Current value of I2CCTL register
*
* Lowers the I2C clock line '1'->'0'
+ * Asserts the I2C clock output enable on X550 hardware.
**/
STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
-
DEBUGFUNC("ixgbe_lower_i2c_clk");
*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
+ *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);
@@ -2377,9 +2415,11 @@ STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
* @data: I2C data value (0 or 1) to set
*
* Sets the I2C data bit
+ * Asserts the I2C data output enable on X550 hardware.
**/
STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
{
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
s32 status = IXGBE_SUCCESS;
DEBUGFUNC("ixgbe_set_i2c_data");
@@ -2388,6 +2428,7 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
else
*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
+ *i2cctl &= ~data_oe_bit;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);
@@ -2395,6 +2436,14 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
+ if (!data) /* Can't verify data in this case */
+ return IXGBE_SUCCESS;
+ if (data_oe_bit) {
+ *i2cctl |= data_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ }
+
/* Verify data was set correctly */
*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
@@ -2413,14 +2462,22 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
* @i2cctl: Current value of I2CCTL register
*
* Returns the I2C data bit value
+ * Negates the I2C data output enable on X550 hardware.
**/
STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
{
+ u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
bool data;
- UNREFERENCED_1PARAMETER(hw);
DEBUGFUNC("ixgbe_get_i2c_data");
+ if (data_oe_bit) {
+ *i2cctl |= data_oe_bit;
+ IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
+ IXGBE_WRITE_FLUSH(hw);
+ usec_delay(IXGBE_I2C_T_FALL);
+ }
+
if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
data = 1;
else
@@ -2438,12 +2495,13 @@ STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
**/
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
{
- u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+ u32 i2cctl;
u32 i;
DEBUGFUNC("ixgbe_i2c_bus_clear");
ixgbe_i2c_start(hw);
+ i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
ixgbe_set_i2c_data(hw, &i2cctl, 1);
diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index 94f4900..06b507a 100644
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -188,6 +188,12 @@ POSSIBILITY OF SUCH DAMAGE.
0x00001000 : 0x00000004)
#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
0x00000400 : 0x00000008)
+#define IXGBE_I2C_BB_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+ 0x00000100 : 0)
+#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+ 0x00000800 : 0)
+#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw) ((hw)->mac.type >= ixgbe_mac_X550 ? \
+ 0x00002000 : 0)
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
--
1.8.4.2
next prev parent reply other threads:[~2015-02-12 12:02 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-12 12:00 [dpdk-dev] [PATCH 00/36] Update IXGBE base codes Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 01/36] ixgbe base codes: Code cleanup and minor changes Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 02/36] ixgbe base codes: Debug output macro Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 03/36] ixgbe base codes: Fix bus type issue Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 04/36] ixgbe base codes: Fix link speed issue Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 05/36] ixgbe base codes: Fix early return Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 06/36] ixgbe base codes: Update the CS address Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 07/36] ixgbe base codes: Extract function for management capability Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 08/36] ixgbe base codes: Set phy power Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 09/36] ixgbe base codes: Use mng present function Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 10/36] ixgbe base codes: Get host interface command status Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 11/36] ixgbe base codes: Refine function for host interface command Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 12/36] ixgbe base codes: Refine struct for physical information Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 13/36] ixgbe base codes: Clear Tx pending Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 14/36] ixgbe base codes: Use IOMEM Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 15/36] ixgbe base codes: Update macros Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 16/36] ixgbe base codes: New phy ID Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 17/36] ixgbe base codes: Get bus info Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 18/36] ixgbe base codes: Restructure host interface command Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 19/36] ixgbe base codes: Fix mac type issue Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 20/36] ixgbe base codes: API for setup internal phy Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 21/36] ixgbe base codes: API for set phy power Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 22/36] ixgbe base codes: API for read i2c combined Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 23/36] ixgbe base codes: API for write " Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 24/36] ixgbe base codes: Support 5G link speed Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 25/36] ixgbe base codes: Refine branch statement Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 26/36] ixgbe base codes: SFP probe Ouyang Changchun
2015-02-12 12:00 ` [dpdk-dev] [PATCH 27/36] ixgbe base codes: Set LAN ID Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 28/36] ixgbe base codes: Calculate checksum Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 29/36] ixgbe base codes: Command for flow director Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 30/36] ixgbe base codes: Auto-negotiation Ouyang Changchun
2015-02-12 12:01 ` Ouyang Changchun [this message]
2015-02-12 12:01 ` [dpdk-dev] [PATCH 32/36] ixgbe base codes: Setup kx4 phy Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 33/36] ixgbe base codes: Read/write iosf sb stat Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 34/36] ixgbe base codes: New device id Ouyang Changchun
2015-02-12 12:01 ` [dpdk-dev] [PATCH 36/36] eal: Add 2 device ids for ixgbe Ouyang Changchun
2015-02-27 14:54 ` [dpdk-dev] [PATCH 00/36] Update IXGBE base codes Liu, Jijiang
2015-04-27 14:59 ` Thomas Monjalon
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