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From: Jingjing Wu <jingjing.wu@intel.com>
To: dev@dpdk.org
Subject: [dpdk-dev] [PATCH 18/52] i40e/base: Add parsing for CEE DCBX TLVs
Date: Sun,  6 Sep 2015 15:11:32 +0800	[thread overview]
Message-ID: <1441523526-26202-19-git-send-email-jingjing.wu@intel.com> (raw)
In-Reply-To: <1441523526-26202-1-git-send-email-jingjing.wu@intel.com>

This patch adds parsing for CEE DCBX TLVs from the LLDP MIB.

While the driver gets the DCB CEE operational configuration from Firmware
using the "Get CEE DCBX Oper Config" AQ command there is a need to get
the CEE DesiredCfg Tx by firmware and DCB configuration Rx from peer; for
debug and other application purposes.

Also gets rid of unused locals variables.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
---
 drivers/net/i40e/base/i40e_dcb.c  | 191 +++++++++++++++++++++++++++++++++++++-
 drivers/net/i40e/base/i40e_dcb.h  |  39 ++++++++
 drivers/net/i40e/base/i40e_type.h |   2 +
 3 files changed, 228 insertions(+), 4 deletions(-)

diff --git a/drivers/net/i40e/base/i40e_dcb.c b/drivers/net/i40e/base/i40e_dcb.c
index 033e52d..9c8e044 100644
--- a/drivers/net/i40e/base/i40e_dcb.c
+++ b/drivers/net/i40e/base/i40e_dcb.c
@@ -299,6 +299,188 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,
 }
 
 /**
+ * i40e_parse_cee_pgcfg_tlv
+ * @tlv: CEE DCBX PG CFG TLV
+ * @dcbcfg: Local store to update ETS CFG data
+ *
+ * Parses CEE DCBX PG CFG TLV
+ **/
+static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,
+				     struct i40e_dcbx_config *dcbcfg)
+{
+	struct i40e_dcb_ets_config *etscfg;
+	u8 *buf = tlv->tlvinfo;
+	u16 offset = 0;
+	u8 priority;
+	int i;
+
+	etscfg = &dcbcfg->etscfg;
+
+	if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
+		etscfg->willing = 1;
+
+	etscfg->cbs = 0;
+	/* Priority Group Table (4 octets)
+	 * Octets:|    1    |    2    |    3    |    4    |
+	 *        -----------------------------------------
+	 *        |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
+	 *        -----------------------------------------
+	 *   Bits:|7  4|3  0|7  4|3  0|7  4|3  0|7  4|3  0|
+	 *        -----------------------------------------
+	 */
+	for (i = 0; i < 4; i++) {
+		priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>
+				 I40E_CEE_PGID_PRIO_1_SHIFT);
+		etscfg->prioritytable[i * 2] =  priority;
+		priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>
+				 I40E_CEE_PGID_PRIO_0_SHIFT);
+		etscfg->prioritytable[i * 2 + 1] = priority;
+		offset++;
+	}
+
+	/* PG Percentage Table (8 octets)
+	 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
+	 *        ---------------------------------
+	 *        |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
+	 *        ---------------------------------
+	 */
+	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
+		etscfg->tcbwtable[i] = buf[offset++];
+
+	/* Number of TCs supported (1 octet) */
+	etscfg->maxtcs = buf[offset];
+}
+
+/**
+ * i40e_parse_cee_pfccfg_tlv
+ * @tlv: CEE DCBX PFC CFG TLV
+ * @dcbcfg: Local store to update PFC CFG data
+ *
+ * Parses CEE DCBX PFC CFG TLV
+ **/
+static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,
+				      struct i40e_dcbx_config *dcbcfg)
+{
+	u8 *buf = tlv->tlvinfo;
+
+	if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
+		dcbcfg->pfc.willing = 1;
+
+	/* ------------------------
+	 * | PFC Enable | PFC TCs |
+	 * ------------------------
+	 * | 1 octet    | 1 octet |
+	 */
+	dcbcfg->pfc.pfcenable = buf[0];
+	dcbcfg->pfc.pfccap = buf[1];
+}
+
+/**
+ * i40e_parse_cee_app_tlv
+ * @tlv: CEE DCBX APP TLV
+ * @dcbcfg: Local store to update APP PRIO data
+ *
+ * Parses CEE DCBX APP PRIO TLV
+ **/
+static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,
+				   struct i40e_dcbx_config *dcbcfg)
+{
+	u16 length, typelength, offset = 0;
+	struct i40e_cee_app_prio *app;
+	u8 i, up, selector;
+
+	typelength = I40E_NTOHS(tlv->hdr.typelen);
+	length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
+		       I40E_LLDP_TLV_LEN_SHIFT);
+
+	dcbcfg->numapps = length/sizeof(*app);
+	if (!dcbcfg->numapps)
+		return;
+
+	for (i = 0; i < dcbcfg->numapps; i++) {
+		app = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);
+		for (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {
+			if (app->prio_map & BIT(up))
+				break;
+		}
+		dcbcfg->app[i].priority = up;
+		/* Get Selector from lower 2 bits, and convert to IEEE */
+		selector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK);
+		if (selector == I40E_CEE_APP_SEL_ETHTYPE)
+			dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
+		else if (selector == I40E_CEE_APP_SEL_TCPIP)
+			dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
+		else
+			/* Keep selector as it is for unknown types */
+			dcbcfg->app[i].selector = selector;
+		dcbcfg->app[i].protocolid = I40E_NTOHS(app->protocol);
+		/* Move to next app */
+		offset += sizeof(*app);
+	}
+}
+
+/**
+ * i40e_parse_cee_tlv
+ * @tlv: CEE DCBX TLV
+ * @dcbcfg: Local store to update DCBX config data
+ *
+ * Get the TLV subtype and send it to parsing function
+ * based on the subtype value
+ **/
+static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,
+			       struct i40e_dcbx_config *dcbcfg)
+{
+	u16 len, tlvlen, sublen, typelength;
+	struct i40e_cee_feat_tlv *sub_tlv;
+	u8 subtype, feat_tlv_count = 0;
+	u32 ouisubtype;
+
+	ouisubtype = I40E_NTOHL(tlv->ouisubtype);
+	subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
+		       I40E_LLDP_TLV_SUBTYPE_SHIFT);
+	/* Return if not CEE DCBX */
+	if (subtype != I40E_CEE_DCBX_TYPE)
+		return;
+
+	typelength = I40E_NTOHS(tlv->typelength);
+	tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
+			I40E_LLDP_TLV_LEN_SHIFT);
+	len = sizeof(tlv->typelength) + sizeof(ouisubtype) +
+	      sizeof(struct i40e_cee_ctrl_tlv);
+	/* Return if no CEE DCBX Feature TLVs */
+	if (tlvlen <= len)
+		return;
+
+	sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);
+	while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {
+		typelength = I40E_NTOHS(sub_tlv->hdr.typelen);
+		sublen = (u16)((typelength &
+				I40E_LLDP_TLV_LEN_MASK) >>
+				I40E_LLDP_TLV_LEN_SHIFT);
+		subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
+				I40E_LLDP_TLV_TYPE_SHIFT);
+		switch (subtype) {
+		case I40E_CEE_SUBTYPE_PG_CFG:
+			i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);
+			break;
+		case I40E_CEE_SUBTYPE_PFC_CFG:
+			i40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);
+			break;
+		case I40E_CEE_SUBTYPE_APP_PRI:
+			i40e_parse_cee_app_tlv(sub_tlv, dcbcfg);
+			break;
+		default:
+			return; /* Invalid Sub-type return */
+		}
+		feat_tlv_count++;
+		/* Move to next sub TLV */
+		sub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +
+						sizeof(sub_tlv->hdr.typelen) +
+						sublen);
+	}
+}
+
+/**
  * i40e_parse_org_tlv
  * @tlv: Organization specific TLV
  * @dcbcfg: Local store to update ETS REC data
@@ -319,6 +501,9 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,
 	case I40E_IEEE_8021QAZ_OUI:
 		i40e_parse_ieee_tlv(tlv, dcbcfg);
 		break;
+	case I40E_CEE_DCBX_OUI:
+		i40e_parse_cee_tlv(tlv, dcbcfg);
+		break;
 	default:
 		break;
 	}
@@ -426,7 +611,7 @@ static void i40e_cee_to_dcb_v1_config(
 {
 	u16 status, tlv_status = LE16_TO_CPU(cee_cfg->tlv_status);
 	u16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);
-	u8 i, tc, err, sync, oper;
+	u8 i, tc, err;
 
 	/* CEE PG data to ETS config */
 	dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
@@ -466,9 +651,7 @@ static void i40e_cee_to_dcb_v1_config(
 	status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>
 		  I40E_AQC_CEE_APP_STATUS_SHIFT;
 	err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
-	sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
-	oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
-	/* Add APPs if Error is False and Oper/Sync is True */
+	/* Add APPs if Error is False */
 	if (!err) {
 		/* CEE operating configuration supports FCoE/iSCSI/FIP only */
 		dcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;
diff --git a/drivers/net/i40e/base/i40e_dcb.h b/drivers/net/i40e/base/i40e_dcb.h
index 841cfc3..3aa228b 100644
--- a/drivers/net/i40e/base/i40e_dcb.h
+++ b/drivers/net/i40e/base/i40e_dcb.h
@@ -54,6 +54,15 @@ POSSIBILITY OF SUCH DAMAGE.
 #define I40E_IEEE_SUBTYPE_PFC_CFG	11
 #define I40E_IEEE_SUBTYPE_APP_PRI	12
 
+#define I40E_CEE_DCBX_OUI		0x001b21
+#define I40E_CEE_DCBX_TYPE		2
+
+#define I40E_CEE_SUBTYPE_CTRL		1
+#define I40E_CEE_SUBTYPE_PG_CFG		2
+#define I40E_CEE_SUBTYPE_PFC_CFG	3
+#define I40E_CEE_SUBTYPE_APP_PRI	4
+
+#define I40E_CEE_MAX_FEAT_TYPE		3
 #define I40E_LLDP_ADMINSTATUS_DISABLED		0
 #define I40E_LLDP_ADMINSTATUS_ENABLED_RX	1
 #define I40E_LLDP_ADMINSTATUS_ENABLED_TX	2
@@ -136,6 +145,36 @@ struct i40e_lldp_org_tlv {
 	__be32 ouisubtype;
 	u8 tlvinfo[1];
 };
+
+struct i40e_cee_tlv_hdr {
+	__be16 typelen;
+	u8 operver;
+	u8 maxver;
+};
+
+struct i40e_cee_ctrl_tlv {
+	struct i40e_cee_tlv_hdr hdr;
+	__be32 seqno;
+	__be32 ackno;
+};
+
+struct i40e_cee_feat_tlv {
+	struct i40e_cee_tlv_hdr hdr;
+	u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
+#define I40E_CEE_FEAT_TLV_ENABLE_MASK	0x80
+#define I40E_CEE_FEAT_TLV_WILLING_MASK	0x40
+#define I40E_CEE_FEAT_TLV_ERR_MASK	0x20
+	u8 subtype;
+	u8 tlvinfo[1];
+};
+
+struct i40e_cee_app_prio {
+	__be16 protocol;
+	u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
+#define I40E_CEE_APP_SELECTOR_MASK	0x03
+	__be16 lower_oui;
+	u8 prio_map;
+};
 #pragma pack()
 
 /*
diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index ccd7992..eb87d54 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -483,6 +483,8 @@ struct i40e_fc_info {
 #define I40E_APP_PROTOID_FIP		0x8914
 #define I40E_APP_SEL_ETHTYPE		0x1
 #define I40E_APP_SEL_TCPIP		0x2
+#define I40E_CEE_APP_SEL_ETHTYPE	0x0
+#define I40E_CEE_APP_SEL_TCPIP		0x1
 
 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 struct i40e_dcb_ets_config {
-- 
2.4.0

  parent reply	other threads:[~2015-09-06  7:12 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-06  7:11 [dpdk-dev] [PATCH 00/52] update i40e base driver Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 01/52] i40e/base: split device ids into a separate file Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 02/52] i40e/base: Add new device id for 20Gb and Fort pond device Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 03/52] i40e/base: add error status value decoding Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 04/52] i40e/base: Replace sprintf with i40e_debug Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 05/52] i40e/base: Merge Fortville SW 4 admin Q command header Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 06/52] i40e/base: Add module_types and update_link_info Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 07/52] i40e/base: grab the AQ spinlocks before clearing registers Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 08/52] i40e/base: add handling of writeback descriptor Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 09/52] i40e/base: Add info to nvm info struct for OEM version data Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 10/52] i40e/base: add wait states to NVM state machine Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 11/52] i40e/base: add commands to nvmupdate utility Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 12/52] i40e/base: Add promiscuous on VLAN support Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 13/52] i40e/base: Add a workaround to drop all flow control frames Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 14/52] i40e/base: Add Debug Dump Internal Data AQ command Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 15/52] i40e/base: OEM Post Update AQ command implementation Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 16/52] i40e/base: add VF capabilities to virtual channel interface Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 17/52] i40e/base: create new BIT and BIT_ULL macros Jingjing Wu
2015-09-06  7:11 ` Jingjing Wu [this message]
2015-09-06  7:11 ` [dpdk-dev] [PATCH 19/52] i40e/base: Prepare the local LLDP MIB in IEEE TLV Format Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 20/52] i40e/base: Refactor PHY structure and add phy_capabilities enum Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 21/52] i40e/base: Store CEE DCBX cfg from firmware and Cache the CEE TLV status Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 22/52] i40e/base: Add some more stats for FD SB and ATR status Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 23/52] i40e/base: Update Flex-10 related device/function capabilities Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 24/52] i40e/base: Wrap the register definitions for PF and VF driver Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 25/52] i40e/base: fix up type clash in i40e_aq_rc_to_posix conversion Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 26/52] i40e/base: Add new link status defines Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 27/52] i40e/base: fixup padding issue in get_cee_dcb_cfg_v1_resp Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 28/52] i40e/base: Add Tx Scheduling related AQ commands Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 29/52] i40e/base: Additional checks for CEE APP priority validity Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 30/52] i40e/base: Add support for pre-allocated pages for pd Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 31/52] i40e/base: clean up unneeded gotos Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 32/52] i40e/base: Handle admin Q timeout when releasing NVM Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 33/52] i40e/base: Add definition of GLINT_CTL register Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 34/52] i40e/base: Add virtchnl op for additional solaris config Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 35/52] i40e/base: drop func from debug print Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 36/52] i40e/base: add new X722 device Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 37/52] i40e/base: Add AQ functions to handle RSS Key and LUT programming Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 38/52] i40e/base: add proxy config admin q functions Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 39/52] i40e/base: add wol config admin queue functions Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 40/52] i40e/base: add WR_CSR_PROT wol/proxy capability parsing Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 41/52] i40e/base: FortPark has additional PCTYPES supported for RSS Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 42/52] i40e/base: FortPark changes to Rx and Tx descriptor for Outer UDP checksum offloads Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 43/52] i40e/base: use INLINE macro for better cross-platform code management Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 44/52] i40e/base: ESS Support Jingjing Wu
2015-09-06  7:11 ` [dpdk-dev] [PATCH 45/52] i40e/base: print FCoE capability reported by the device function Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 46/52] i40e/base: remove useless assignments Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 47/52] i40e/base: Increase pf reset max loop limit Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 48/52] i40e/base: Add FortPark specific registers Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 49/52] i40e/base: Allow for per-device FW API version Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 50/52] i40e/base: Add ATR command bit definition for FortPark Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 51/52] i40e/base: Explicitly assign enum index for VSI type Jingjing Wu
2015-09-06  7:12 ` [dpdk-dev] [PATCH 52/52] eal/common: add new i40e device id Jingjing Wu
2015-09-09  1:53 ` [dpdk-dev] [PATCH 00/52] update i40e base driver Zhang, Helin
2015-10-01 23:38   ` Thomas Monjalon
2015-10-02  8:24     ` Mcnamara, John
2015-10-08  2:46       ` Wu, Jingjing
2015-09-16  7:45 ` Xu, HuilongX

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