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From: Sagi Grimberg <sagi@grimberg.me>
To: dev@dpdk.org
Cc: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>,
	Adrien Mazarguil <adrien.mazarguil@6wind.com>,
	Shahaf Shuler <shahafs@mellanox.com>
Subject: [dpdk-dev] [PATCH 2/2] net/mlx5: don't map doorbell register to write combining
Date: Mon, 21 Aug 2017 10:47:02 +0300	[thread overview]
Message-ID: <1503301622-14220-3-git-send-email-sagi@grimberg.me> (raw)
In-Reply-To: <1503301622-14220-1-git-send-email-sagi@grimberg.me>

From: Shahaf Shuler <shahafs@mellanox.com>

By default, Verbs maps the doorbell register to write combining.
Working with write combining is useful for drivers which use blue flame
for the doorbell write.

Since mlx5 PMD uses only doorbells and write combining mapping requires
an extra memory barrier to flush the doorbell after its write, setting
the mapping to un-cached by default.

Such change is reduces the max and average round trip
latency significantly.

Reported-by: Alexander Solganik <solganik@gmail.com>
Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Alexander Solganik <solganik@gmail.com>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
---
 drivers/net/mlx5/mlx5.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index b7e5046325c0..4c2a0b9652e3 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -920,6 +920,8 @@ rte_mlx5_pmd_init(void)
 	 * using this PMD, which is not supported in forked processes.
 	 */
 	setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
+	/* Don't map UAR to WC if BlueFlame is not used.*/
+	setenv("MLX5_SHUT_UP_BF", "1", 1);
 	ibv_fork_init();
 	rte_pci_register(&mlx5_driver);
 }
-- 
2.7.4

  parent reply	other threads:[~2017-08-21  7:47 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-21  7:47 [dpdk-dev] [PATCH 0/2] mlx5 high latency observed on send operations Sagi Grimberg
2017-08-21  7:47 ` [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type Sagi Grimberg
2017-08-23 11:39   ` Nélio Laranjeiro
2017-08-23 13:11     ` Bruce Richardson
2017-08-24  6:56       ` Shahaf Shuler
2017-08-24  9:27         ` Bruce Richardson
2017-08-21  7:47 ` Sagi Grimberg [this message]
2017-08-23 11:03   ` [dpdk-dev] [PATCH 2/2] net/mlx5: don't map doorbell register to write combining Ferruh Yigit
2017-08-23 12:06     ` Nélio Laranjeiro
2017-08-27  6:47 ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Shahaf Shuler
2017-08-27  6:47   ` [dpdk-dev] [PATCH v2 1/2] net/mlx5: replace memory barrier type Shahaf Shuler
2017-08-27  6:47   ` [dpdk-dev] [PATCH v2 2/2] net/mlx5: don't map doorbell register to write combining Shahaf Shuler
2017-08-29 16:53   ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Ferruh Yigit

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