* [dpdk-dev] [PATCH 1/2] crypto/octeontx2: discover capabilities
@ 2020-06-16 13:02 Anoob Joseph
2020-06-16 13:02 ` [dpdk-dev] [PATCH 2/2] crypto/octeontx2: add ChaCha20-Poly1305 support Anoob Joseph
0 siblings, 1 reply; 3+ messages in thread
From: Anoob Joseph @ 2020-06-16 13:02 UTC (permalink / raw)
To: Akhil Goyal, Radu Nicolau
Cc: Tejasree Kondoj, Narayana Prasad, Anoob Joseph, dev
From: Tejasree Kondoj <ktejasree@marvell.com>
Populate capabilities based on device features.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/octeontx2/otx2_mbox.h | 33 +
drivers/crypto/octeontx2/otx2_cryptodev.c | 7 +
drivers/crypto/octeontx2/otx2_cryptodev.h | 2 +
.../octeontx2/otx2_cryptodev_capabilities.c | 562 ++++++++++--------
.../octeontx2/otx2_cryptodev_capabilities.h | 12 +-
.../crypto/octeontx2/otx2_cryptodev_mbox.c | 21 +
.../crypto/octeontx2/otx2_cryptodev_mbox.h | 3 +
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 2 +-
drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 6 -
9 files changed, 390 insertions(+), 258 deletions(-)
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 7fa4276e9e..34b1d06632 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -198,6 +198,7 @@ M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
cpt_inline_ipsec_cfg_msg, msg_rsp) \
M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
cpt_rx_inline_lf_cfg_msg, msg_rsp) \
+M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
npc_mcam_alloc_entry_req, \
@@ -1258,6 +1259,38 @@ struct cpt_rx_inline_lf_cfg_msg {
uint16_t __otx2_io sso_pf_func;
};
+enum cpt_eng_type {
+ CPT_ENG_TYPE_AE = 1,
+ CPT_ENG_TYPE_SE = 2,
+ CPT_ENG_TYPE_IE = 3,
+ CPT_MAX_ENG_TYPES,
+};
+
+/* CPT HW capabilities */
+union cpt_eng_caps {
+ uint64_t __otx2_io u;
+ struct {
+ uint64_t __otx2_io reserved_0_4:5;
+ uint64_t __otx2_io mul:1;
+ uint64_t __otx2_io sha1_sha2:1;
+ uint64_t __otx2_io chacha20:1;
+ uint64_t __otx2_io zuc_snow3g:1;
+ uint64_t __otx2_io sha3:1;
+ uint64_t __otx2_io aes:1;
+ uint64_t __otx2_io kasumi:1;
+ uint64_t __otx2_io des:1;
+ uint64_t __otx2_io crc:1;
+ uint64_t __otx2_io reserved_14_63:50;
+ };
+};
+
+struct cpt_caps_rsp_msg {
+ struct mbox_msghdr hdr;
+ uint16_t __otx2_io cpt_pf_drv_version;
+ uint8_t __otx2_io cpt_revision;
+ union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
+};
+
/* NPC mbox message structs */
#define NPC_MCAM_ENTRY_INVALID 0xFFFF
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
index 6ffbc2eb7c..77aa315dc0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -14,6 +14,7 @@
#include "otx2_common.h"
#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_capabilities.h"
#include "otx2_cryptodev_mbox.h"
#include "otx2_cryptodev_ops.h"
#include "otx2_dev.h"
@@ -96,6 +97,12 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
+ ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);
+ if (ret) {
+ CPT_LOG_ERR("Could not determine hardware capabilities");
+ goto otx2_dev_fini;
+ }
+
dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED |
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
index c0aa661b3b..e7a1730b22 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -29,6 +29,8 @@ struct otx2_cpt_vf {
/**< MSI-X offsets */
uint8_t err_intr_registered:1;
/**< Are error interrupts registered? */
+ union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+ /**< CPT device capabilities */
};
#define CPT_LOGTYPE otx2_cpt_logtype
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 3eb3d8532c..9e18c4eee0 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -5,115 +5,87 @@
#include <rte_cryptodev.h>
#include "otx2_cryptodev_capabilities.h"
+#include "otx2_mbox.h"
-static const struct
-rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
- /* Symmetric capabilities */
- { /* NULL (AUTH) */
- .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- {.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_NULL,
- .block_size = 1,
- .key_size = {
- .min = 0,
- .max = 0,
- .increment = 0
- },
- .digest_size = {
- .min = 0,
- .max = 0,
- .increment = 0
- },
- }, },
- }, },
- },
- { /* AES GMAC (AUTH) */
- .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- {.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_AES_GMAC,
- .block_size = 16,
- .key_size = {
- .min = 16,
- .max = 32,
- .increment = 8
- },
- .digest_size = {
- .min = 8,
- .max = 16,
- .increment = 4
- },
- .iv_size = {
- .min = 12,
- .max = 12,
- .increment = 0
- }
- }, }
+#define CPT_EGRP_GET(hw_caps, name, egrp) do { \
+ if ((hw_caps[CPT_ENG_TYPE_SE].name) && \
+ (hw_caps[CPT_ENG_TYPE_IE].name)) \
+ *egrp = OTX2_CPT_EGRP_SE_IE; \
+ else if (hw_caps[CPT_ENG_TYPE_SE].name) \
+ *egrp = OTX2_CPT_EGRP_SE; \
+ else if (hw_caps[CPT_ENG_TYPE_AE].name) \
+ *egrp = OTX2_CPT_EGRP_AE; \
+ else \
+ *egrp = OTX2_CPT_EGRP_MAX; \
+} while (0)
+
+#define CPT_CAPS_ADD(hw_caps, name) do { \
+ enum otx2_cpt_egrp egrp; \
+ CPT_EGRP_GET(hw_caps, name, &egrp); \
+ if (egrp < OTX2_CPT_EGRP_MAX) \
+ cpt_caps_add(caps_##name, RTE_DIM(caps_##name)); \
+} while (0)
+
+#define OTX2_CPT_MAX_CAPS 34
+
+static struct rte_cryptodev_capabilities otx2_cpt_caps[OTX2_CPT_MAX_CAPS];
+
+static const struct rte_cryptodev_capabilities caps_mul[] = {
+ { /* RSA */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+ .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+ (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+ (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+ (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
}, }
},
- { /* KASUMI (F9) */
- .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- {.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
- .block_size = 8,
- .key_size = {
- .min = 16,
- .max = 16,
- .increment = 0
- },
- .digest_size = {
- .min = 4,
- .max = 4,
- .increment = 0
- },
- }, }
+ { /* MOD_EXP */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+ .op_types = 0,
+ {.modlen = {
+ .min = 17,
+ .max = 1024,
+ .increment = 1
+ }, }
+ }
}, }
},
- { /* MD5 */
- .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- {.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_MD5,
- .block_size = 64,
- .key_size = {
- .min = 0,
- .max = 0,
- .increment = 0
- },
- .digest_size = {
- .min = 16,
- .max = 16,
- .increment = 0
- },
- }, }
- }, }
+ { /* ECDSA */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,
+ .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+ (1 << RTE_CRYPTO_ASYM_OP_VERIFY)),
+ }
+ },
+ }
},
- { /* MD5 HMAC */
- .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
- {.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
- .block_size = 64,
- .key_size = {
- .min = 8,
- .max = 64,
- .increment = 8
- },
- .digest_size = {
- .min = 16,
- .max = 16,
- .increment = 0
- },
- }, }
- }, }
+ { /* ECPM */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ {.asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,
+ .op_types = 0
+ }
+ },
+ }
},
+};
+
+static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
{ /* SHA1 */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
@@ -147,9 +119,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
.increment = 1
},
.digest_size = {
- .min = 20,
+ .min = 12,
.max = 20,
- .increment = 0
+ .increment = 8
},
}, }
}, }
@@ -227,9 +199,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
.increment = 1
},
.digest_size = {
- .min = 32,
+ .min = 16,
.max = 32,
- .increment = 0
+ .increment = 16
},
}, }
}, }
@@ -267,9 +239,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
.increment = 1
},
.digest_size = {
- .min = 48,
+ .min = 24,
.max = 48,
- .increment = 0
+ .increment = 24
},
}, }
}, }
@@ -307,28 +279,66 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
.increment = 1
},
.digest_size = {
- .min = 64,
+ .min = 32,
.max = 64,
- .increment = 0
+ .increment = 32
},
}, }
}, }
},
- { /* SNOW 3G (UIA2) */
+ { /* MD5 */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
{.auth = {
- .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
- .block_size = 16,
+ .algo = RTE_CRYPTO_AUTH_MD5,
+ .block_size = 64,
.key_size = {
+ .min = 0,
+ .max = 0,
+ .increment = 0
+ },
+ .digest_size = {
.min = 16,
.max = 16,
.increment = 0
},
+ }, }
+ }, }
+ },
+ { /* MD5 HMAC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+ .block_size = 64,
+ .key_size = {
+ .min = 8,
+ .max = 64,
+ .increment = 8
+ },
.digest_size = {
- .min = 4,
- .max = 4,
+ .min = 12,
+ .max = 16,
+ .increment = 4
+ },
+ }, }
+ }, }
+ },
+};
+
+static const struct rte_cryptodev_capabilities caps_zuc_snow3g[] = {
+ { /* SNOW 3G (UEA2) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 16,
.increment = 0
},
.iv_size = {
@@ -339,23 +349,18 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
}, }
}, }
},
- { /* ZUC (EIA3) */
+ { /* ZUC (EEA3) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
- {.auth = {
- .algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
.block_size = 16,
.key_size = {
.min = 16,
.max = 16,
.increment = 0
},
- .digest_size = {
- .min = 4,
- .max = 4,
- .increment = 0
- },
.iv_size = {
.min = 16,
.max = 16,
@@ -364,61 +369,79 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
}, }
}, }
},
- { /* NULL (CIPHER) */
+ { /* SNOW 3G (UIA2) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- {.cipher = {
- .algo = RTE_CRYPTO_CIPHER_NULL,
- .block_size = 1,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+ .block_size = 16,
.key_size = {
- .min = 0,
- .max = 0,
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
.increment = 0
},
.iv_size = {
- .min = 0,
- .max = 0,
+ .min = 16,
+ .max = 16,
.increment = 0
}
- }, },
+ }, }
}, }
},
- { /* 3DES CBC */
+ { /* ZUC (EIA3) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- {.cipher = {
- .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
- .block_size = 8,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+ .block_size = 16,
.key_size = {
- .min = 24,
- .max = 24,
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 4,
.increment = 0
},
.iv_size = {
- .min = 8,
+ .min = 16,
.max = 16,
- .increment = 8
+ .increment = 0
}
}, }
}, }
},
- { /* 3DES ECB */
+};
+
+static const struct rte_cryptodev_capabilities caps_aes[] = {
+ { /* AES GMAC (AUTH) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- {.cipher = {
- .algo = RTE_CRYPTO_CIPHER_3DES_ECB,
- .block_size = 8,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_AES_GMAC,
+ .block_size = 16,
.key_size = {
- .min = 24,
- .max = 24,
- .increment = 0
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 8,
+ .max = 16,
+ .increment = 4
},
.iv_size = {
- .min = 0,
- .max = 0,
+ .min = 12,
+ .max = 12,
.increment = 0
}
}, }
@@ -484,26 +507,39 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
}, }
}, }
},
- { /* DES CBC */
+ { /* AES GCM */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- {.cipher = {
- .algo = RTE_CRYPTO_CIPHER_DES_CBC,
- .block_size = 8,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead = {
+ .algo = RTE_CRYPTO_AEAD_AES_GCM,
+ .block_size = 16,
.key_size = {
- .min = 8,
- .max = 8,
- .increment = 0
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .digest_size = {
+ .min = 4,
+ .max = 16,
+ .increment = 1
+ },
+ .aad_size = {
+ .min = 0,
+ .max = 1024,
+ .increment = 1
},
.iv_size = {
- .min = 8,
- .max = 8,
+ .min = 12,
+ .max = 12,
.increment = 0
}
}, }
}, }
},
+};
+
+static const struct rte_cryptodev_capabilities caps_kasumi[] = {
{ /* KASUMI (F8) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
@@ -524,137 +560,163 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
}, }
}, }
},
- { /* SNOW 3G (UEA2) */
+ { /* KASUMI (F9) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
- {.cipher = {
- .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
- .block_size = 16,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+ .block_size = 8,
.key_size = {
.min = 16,
.max = 16,
.increment = 0
},
+ .digest_size = {
+ .min = 4,
+ .max = 4,
+ .increment = 0
+ },
+ }, }
+ }, }
+ },
+};
+
+static const struct rte_cryptodev_capabilities caps_des[] = {
+ { /* 3DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
.iv_size = {
- .min = 16,
+ .min = 8,
.max = 16,
+ .increment = 8
+ }
+ }, }
+ }, }
+ },
+ { /* 3DES ECB */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_3DES_ECB,
+ .block_size = 8,
+ .key_size = {
+ .min = 24,
+ .max = 24,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 0,
+ .max = 0,
.increment = 0
}
}, }
}, }
},
- { /* ZUC (EEA3) */
+ { /* DES CBC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
{.cipher = {
- .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
- .block_size = 16,
+ .algo = RTE_CRYPTO_CIPHER_DES_CBC,
+ .block_size = 8,
.key_size = {
- .min = 16,
- .max = 16,
+ .min = 8,
+ .max = 8,
.increment = 0
},
.iv_size = {
- .min = 16,
- .max = 16,
+ .min = 8,
+ .max = 8,
.increment = 0
}
}, }
}, }
},
- { /* AES GCM */
+};
+
+static const struct rte_cryptodev_capabilities caps_null[] = {
+ { /* NULL (AUTH) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
- .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
- {.aead = {
- .algo = RTE_CRYPTO_AEAD_AES_GCM,
- .block_size = 16,
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth = {
+ .algo = RTE_CRYPTO_AUTH_NULL,
+ .block_size = 1,
.key_size = {
- .min = 16,
- .max = 32,
- .increment = 8
+ .min = 0,
+ .max = 0,
+ .increment = 0
},
.digest_size = {
- .min = 4,
- .max = 16,
- .increment = 1
+ .min = 0,
+ .max = 0,
+ .increment = 0
},
- .aad_size = {
+ }, },
+ }, },
+ },
+ { /* NULL (CIPHER) */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_NULL,
+ .block_size = 1,
+ .key_size = {
.min = 0,
- .max = 1024,
- .increment = 1
+ .max = 0,
+ .increment = 0
},
.iv_size = {
- .min = 12,
- .max = 12,
+ .min = 0,
+ .max = 0,
.increment = 0
}
- }, }
+ }, },
}, }
},
- /* End of symmetric capabilities */
+};
- /* Asymmetric capabilities */
- { /* RSA */
- .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
- {.asym = {
- .xform_capa = {
- .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
- .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
- (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
- (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
- (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
- {.modlen = {
- .min = 17,
- .max = 1024,
- .increment = 1
- }, }
- }
- }, }
- },
- { /* MOD_EXP */
- .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
- {.asym = {
- .xform_capa = {
- .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
- .op_types = 0,
- {.modlen = {
- .min = 17,
- .max = 1024,
- .increment = 1
- }, }
- }
- }, }
- },
- { /* ECDSA */
- .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
- {.asym = {
- .xform_capa = {
- .xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,
- .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
- (1 << RTE_CRYPTO_ASYM_OP_VERIFY)),
- }
- },
- }
- },
- { /* ECPM */
- .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
- {.asym = {
- .xform_capa = {
- .xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,
- .op_types = 0
- }
- },
- }
- },
- /* End of asymmetric capabilities */
+static const struct rte_cryptodev_capabilities caps_end[] = {
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
+static void
+cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)
+{
+ static int cur_pos;
+
+ if (cur_pos + nb_caps > OTX2_CPT_MAX_CAPS)
+ return;
+
+ memcpy(&otx2_cpt_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));
+ cur_pos += nb_caps;
+}
+
const struct rte_cryptodev_capabilities *
-otx2_cpt_capabilities_get(void)
+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps)
{
- return otx2_cpt_capabilities;
+
+ CPT_CAPS_ADD(hw_caps, mul);
+ CPT_CAPS_ADD(hw_caps, sha1_sha2);
+ CPT_CAPS_ADD(hw_caps, zuc_snow3g);
+ CPT_CAPS_ADD(hw_caps, aes);
+ CPT_CAPS_ADD(hw_caps, kasumi);
+ CPT_CAPS_ADD(hw_caps, des);
+
+ cpt_caps_add(caps_null, RTE_DIM(caps_null));
+ cpt_caps_add(caps_end, RTE_DIM(caps_end));
+
+ return otx2_cpt_caps;
}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
index f103c32eda..e07a2a8c92 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h
@@ -7,10 +7,20 @@
#include <rte_cryptodev.h>
+#include "otx2_mbox.h"
+
+enum otx2_cpt_egrp {
+ OTX2_CPT_EGRP_SE = 0,
+ OTX2_CPT_EGRP_SE_IE = 1,
+ OTX2_CPT_EGRP_AE = 2,
+ OTX2_CPT_EGRP_MAX,
+};
+
/*
* Get capabilities list for the device
*
*/
-const struct rte_cryptodev_capabilities *otx2_cpt_capabilities_get(void);
+const struct rte_cryptodev_capabilities *
+otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps);
#endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index 6bb8316ec9..6028439de3 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -14,6 +14,27 @@
#include "cpt_pmd_logs.h"
+int
+otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,
+ union cpt_eng_caps *hw_caps)
+{
+ struct otx2_cpt_vf *vf = dev->data->dev_private;
+ struct otx2_dev *otx2_dev = &vf->otx2_dev;
+ struct cpt_caps_rsp_msg *rsp;
+ int ret;
+
+ otx2_mbox_alloc_msg_cpt_caps_get(otx2_dev->mbox);
+
+ ret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);
+ if (ret)
+ return -EIO;
+
+ memcpy(hw_caps, rsp->eng_caps,
+ sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
+
+ return 0;
+}
+
int
otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index ae66b08461..4bc057774f 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -9,6 +9,9 @@
#include "otx2_cryptodev_hw_access.h"
+int otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,
+ union cpt_eng_caps *hw_caps);
+
int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
uint16_t *nb_queues);
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index ad292a08f7..132f599efd 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -1067,7 +1067,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
if (info != NULL) {
info->max_nb_queue_pairs = vf->max_queues;
info->feature_flags = dev->feature_flags;
- info->capabilities = otx2_cpt_capabilities_get();
+ info->capabilities = otx2_cpt_capabilities_get(vf->hw_caps);
info->sym.max_nb_sessions = 0;
info->driver_id = otx2_cryptodev_driver_id;
info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
index f83e36b486..1970187f88 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -10,12 +10,6 @@
#define OTX2_CPT_MIN_HEADROOM_REQ 24
#define OTX2_CPT_MIN_TAILROOM_REQ 8
-enum otx2_cpt_egrp {
- OTX2_CPT_EGRP_SE = 0,
- OTX2_CPT_EGRP_SE_IE = 1,
- OTX2_CPT_EGRP_AE = 2
-};
-
extern struct rte_cryptodev_ops otx2_cpt_ops;
#endif /* _OTX2_CRYPTODEV_OPS_H_ */
--
2.27.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* [dpdk-dev] [PATCH 2/2] crypto/octeontx2: add ChaCha20-Poly1305 support
2020-06-16 13:02 [dpdk-dev] [PATCH 1/2] crypto/octeontx2: discover capabilities Anoob Joseph
@ 2020-06-16 13:02 ` Anoob Joseph
2020-07-04 20:22 ` Akhil Goyal
0 siblings, 1 reply; 3+ messages in thread
From: Anoob Joseph @ 2020-06-16 13:02 UTC (permalink / raw)
To: Akhil Goyal, Radu Nicolau
Cc: Tejasree Kondoj, Narayana Prasad, Anoob Joseph, dev
From: Tejasree Kondoj <ktejasree@marvell.com>
Add ChaCha20-Poly1305 AEAD algorithm support in crypto_octeontx2 PMD
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
doc/guides/cryptodevs/features/octeontx2.ini | 7 ++--
doc/guides/cryptodevs/octeontx2.rst | 1 +
doc/guides/rel_notes/release_20_08.rst | 4 +++
drivers/common/cpt/cpt_mcode_defines.h | 5 ++-
drivers/common/cpt/cpt_ucode.h | 20 +++++++----
.../octeontx2/otx2_cryptodev_capabilities.c | 34 +++++++++++++++++++
drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 5 +--
7 files changed, 64 insertions(+), 12 deletions(-)
diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini
index cdcaf709de..25013f9966 100644
--- a/doc/guides/cryptodevs/features/octeontx2.ini
+++ b/doc/guides/cryptodevs/features/octeontx2.ini
@@ -61,9 +61,10 @@ ZUC EIA3 = Y
; Supported AEAD algorithms of 'octeontx2' crypto driver.
;
[AEAD]
-AES GCM (128) = Y
-AES GCM (192) = Y
-AES GCM (256) = Y
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
+CHACHA20-POLY1305 = Y
;
; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.
diff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst
index 8bdb83f490..085d669e49 100644
--- a/doc/guides/cryptodevs/octeontx2.rst
+++ b/doc/guides/cryptodevs/octeontx2.rst
@@ -55,6 +55,7 @@ Hash algorithms:
AEAD algorithms:
* ``RTE_CRYPTO_AEAD_AES_GCM``
+* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``
Asymmetric Crypto Algorithms
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst
index 39064afbe9..6debaca5d2 100644
--- a/doc/guides/rel_notes/release_20_08.rst
+++ b/doc/guides/rel_notes/release_20_08.rst
@@ -56,6 +56,10 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the OCTEON TX2 crypto PMD.**
+
+ Added Chacha20-Poly1305 AEAD algorithm support in OCTEON TX2 crypto PMD.
+
Removed Items
-------------
diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 69d831b5cc..fd306ab812 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -106,7 +106,7 @@ typedef enum {
SHA2_SHA384 = 5,
SHA2_SHA512 = 6,
GMAC_TYPE = 7,
- XCBC_TYPE = 8,
+ POLY1305 = 8,
SHA3_SHA224 = 10,
SHA3_SHA256 = 11,
SHA3_SHA384 = 12,
@@ -136,6 +136,7 @@ typedef enum {
AES_CTR = 0x6,
AES_GCM = 0x7,
AES_XTS = 0x8,
+ CHACHA20 = 0x9,
/* These are only for software use */
ZUC_EEA3 = 0x90,
@@ -241,6 +242,8 @@ struct cpt_sess_misc {
uint16_t aes_gcm:1;
/** Flag for AES CTR */
uint16_t aes_ctr:1;
+ /** Flag for CHACHA POLY */
+ uint16_t chacha_poly:1;
/** Flag for NULL cipher/auth */
uint16_t is_null:1;
/** Flag for GMAC */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 34ccd08a40..a42808cb8a 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -77,6 +77,9 @@ cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len)
return -1;
fc_type = FC_GEN;
break;
+ case CHACHA20:
+ fc_type = FC_GEN;
+ break;
case AES_XTS:
key_len = key_len / 2;
if (unlikely(key_len == CPT_BYTE_24)) {
@@ -229,6 +232,7 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
case AES_ECB:
case AES_CFB:
case AES_CTR:
+ case CHACHA20:
cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
break;
case AES_GCM:
@@ -2543,16 +2547,14 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform,
aead_form = &xform->aead;
void *ctx = SESS_PRIV(sess);
- if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
- aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+ if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
sess->cpt_op |= CPT_OP_AUTH_GENERATE;
- } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
- aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
+ } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT) {
sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
sess->cpt_op |= CPT_OP_AUTH_VERIFY;
} else {
- CPT_LOG_DP_ERR("Unknown cipher operation\n");
+ CPT_LOG_DP_ERR("Unknown aead operation\n");
return -1;
}
switch (aead_form->algo) {
@@ -2565,6 +2567,12 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform,
CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
aead_form->algo);
return -1;
+ case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
+ enc_type = CHACHA20;
+ auth_type = POLY1305;
+ cipher_key_len = 32;
+ sess->chacha_poly = 1;
+ break;
default:
CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
aead_form->algo);
@@ -3067,7 +3075,7 @@ fill_fc_params(struct rte_crypto_op *cop,
m_src = sym_op->m_src;
m_dst = sym_op->m_dst;
- if (sess_misc->aes_gcm) {
+ if (sess_misc->aes_gcm || sess_misc->chacha_poly) {
uint8_t *salt;
uint8_t *aad_data;
uint16_t aad_len;
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 9e18c4eee0..f6f4dee6cf 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -328,6 +328,39 @@ static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
},
};
+static const struct rte_cryptodev_capabilities caps_chacha20[] = {
+ { /* Chacha20-Poly1305 */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead = {
+ .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305,
+ .block_size = 64,
+ .key_size = {
+ .min = 32,
+ .max = 32,
+ .increment = 0
+ },
+ .digest_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ },
+ .aad_size = {
+ .min = 0,
+ .max = 1024,
+ .increment = 1
+ },
+ .iv_size = {
+ .min = 12,
+ .max = 12,
+ .increment = 0
+ },
+ }, }
+ }, }
+ }
+};
+
static const struct rte_cryptodev_capabilities caps_zuc_snow3g[] = {
{ /* SNOW 3G (UEA2) */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -710,6 +743,7 @@ otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps)
CPT_CAPS_ADD(hw_caps, mul);
CPT_CAPS_ADD(hw_caps, sha1_sha2);
+ CPT_CAPS_ADD(hw_caps, chacha20);
CPT_CAPS_ADD(hw_caps, zuc_snow3g);
CPT_CAPS_ADD(hw_caps, aes);
CPT_CAPS_ADD(hw_caps, kasumi);
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 132f599efd..08254062e9 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -395,9 +395,10 @@ sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
/*
* IE engines support IPsec operations
- * SE engines support IPsec operations and Air-Crypto operations
+ * SE engines support IPsec operations, Chacha-Poly and
+ * Air-Crypto operations
*/
- if (misc->zsk_flag)
+ if (misc->zsk_flag || misc->chacha_poly)
misc->egrp = OTX2_CPT_EGRP_SE;
else
misc->egrp = OTX2_CPT_EGRP_SE_IE;
--
2.27.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [dpdk-dev] [PATCH 2/2] crypto/octeontx2: add ChaCha20-Poly1305 support
2020-06-16 13:02 ` [dpdk-dev] [PATCH 2/2] crypto/octeontx2: add ChaCha20-Poly1305 support Anoob Joseph
@ 2020-07-04 20:22 ` Akhil Goyal
0 siblings, 0 replies; 3+ messages in thread
From: Akhil Goyal @ 2020-07-04 20:22 UTC (permalink / raw)
To: Anoob Joseph, Radu Nicolau; +Cc: Tejasree Kondoj, Narayana Prasad, dev
> From: Tejasree Kondoj <ktejasree@marvell.com>
>
> Add ChaCha20-Poly1305 AEAD algorithm support in crypto_octeontx2 PMD
>
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
> ---
Series Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-07-04 20:22 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-07-04 20:22 ` Akhil Goyal
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