* [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
@ 2019-03-28 13:36 ` Arek Kusztal
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 1/4] common/qat: add headers for asymmetric crypto Arek Kusztal
` (4 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:36 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This patchset adds Poll Mode Driver to use asymmetric cryptography
functions using Intel QuickAssist Techology devices.
Following functions are available with this patchset:
* Modular Exponentiation
* Modular Inverse
This patch depends on a QAT PF driver for device initialization. See
the file docs/guides/cryptodevs/qat.rst for configuration details.
Limitations:
* Maximum parameter size: 4096 bits
- For both modular exponentiaion and modular multiplicative inverse
v5:
- changed error checks order
v4:
- fixed yet more checkpatch issues
v3:
- fixed some checkpatch issues
v2:
- added Meson build
- fixed segfault on cookie
- fixed mod inverse problem
Arek Kusztal (4):
common/qat: add headers for asymmetric crypto
crypto/qat: add asymmetric cryptography PMD
crypto/qat: add modular exponentiation to qat asym pmd
crypto/qat: add modular inverse to qat asym pmd
config/common_base | 1 +
doc/guides/cryptodevs/qat.rst | 10 +
drivers/common/qat/Makefile | 8 +
drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h | 1538 ++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_fw_pke.h | 426 ++++++
.../qat/qat_adf/qat_pke_functionality_arrays.h | 52 +
drivers/common/qat/qat_device.h | 12 +-
drivers/common/qat/qat_qp.c | 8 +
drivers/crypto/qat/meson.build | 5 +-
drivers/crypto/qat/qat_asym.c | 420 ++++++
drivers/crypto/qat/qat_asym.h | 106 ++
drivers/crypto/qat/qat_asym_capabilities.h | 42 +
drivers/crypto/qat/qat_asym_pmd.c | 309 ++++
drivers/crypto/qat/qat_asym_pmd.h | 50 +
drivers/crypto/qat/qat_sym_pmd.c | 1 -
drivers/crypto/qat/qat_sym_pmd.h | 3 +-
mk/rte.app.mk | 1 +
17 files changed, 2987 insertions(+), 5 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_pke.h
create mode 100644 drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
create mode 100644 drivers/crypto/qat/qat_asym.c
create mode 100644 drivers/crypto/qat/qat_asym.h
create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* [dpdk-dev] [PATCH v5 1/4] common/qat: add headers for asymmetric crypto
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
2019-03-28 13:36 ` Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD Arek Kusztal
` (3 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds headers to be used in conjunction with asymmetric
cryptography operations using Intel QuickAssist Technology driver
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h | 1538 ++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_fw_pke.h | 426 ++++++
.../qat/qat_adf/qat_pke_functionality_arrays.h | 52 +
3 files changed, 2016 insertions(+)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_pke.h
create mode 100644 drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h b/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
new file mode 100644
index 0000000..d9a42dd
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
@@ -0,0 +1,1538 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_mmp_ids.h
+ * @ingroup icp_qat_fw_mmp
+ * @brief
+ * This file documents the external interfaces that the QAT FW running
+ * on the QAT Acceleration Engine provides to clients wanting to
+ * accelerate crypto assymetric applications
+ */
+
+#ifndef _ICP_QAT_FW_MMP_IDS_
+#define _ICP_QAT_FW_MMP_IDS_
+
+#define PKE_INIT 0x09061a09
+/**< Functionality ID for Initialisation sequence
+ * @li 1 input parameters : @link icp_qat_fw_mmp_init_input::z z @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_init_output::zz zz @endlink
+ */
+#define PKE_DH_G2_768 0x1c0b1a10
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ *768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_768_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_768_output::r r
+ * @endlink
+ */
+#define PKE_DH_768 0x210c1a1b
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 768-bit
+ *numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_768_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_768_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_768_output::r r @endlink
+ */
+#define PKE_DH_G2_1024 0x220b1a27
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1024_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1024_output::r r
+ * @endlink
+ */
+#define PKE_DH_1024 0x290c1a32
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1024-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1024_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1024_output::r r @endlink
+ */
+#define PKE_DH_G2_1536 0x2e0b1a3e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1536_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1536_output::r r
+ * @endlink
+ */
+#define PKE_DH_1536 0x390c1a49
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1536-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1536_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1536_output::r r @endlink
+ */
+#define PKE_DH_G2_2048 0x3e0b1a55
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_2048_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_2048_output::r r
+ * @endlink
+ */
+#define PKE_DH_2048 0x4d0c1a60
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 2048-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_2048_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_2048_output::r r @endlink
+ */
+#define PKE_DH_G2_3072 0x3a0b1a6c
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_3072_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_3072_output::r r
+ * @endlink
+ */
+#define PKE_DH_3072 0x510c1a77
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 3072-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_3072_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_3072_output::r r @endlink
+ */
+#define PKE_DH_G2_4096 0x4a0b1a83
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_4096_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_4096_output::r r
+ * @endlink
+ */
+#define PKE_DH_4096 0x690c1a8e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 4096-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_4096_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_4096_output::r r @endlink
+ */
+#define PKE_RSA_KP1_512 0x191d1a9a
+/**< Functionality ID for RSA 512 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_512_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_output::d d @endlink
+ */
+#define PKE_RSA_KP2_512 0x19401acc
+/**< Functionality ID for RSA 512 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_512 0x1c161b21
+/**< Functionality ID for RSA 512 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_512_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_512_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_512_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_512 0x1c161b3c
+/**< Functionality ID for RSA 512 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_512_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_512 0x1c131b57
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_512_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1024 0x36181b71
+/**< Functionality ID for RSA 1024 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1024_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1024 0x40451b9e
+/**< Functionality ID for RSA 1024 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1024 0x35111bf7
+/**< Functionality ID for RSA 1024 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1024_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1024_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1024 0x35111c12
+/**< Functionality ID for RSA 1024 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1024_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_1024 0x26131c2d
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1024_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1536 0x531d1c46
+/**< Functionality ID for RSA 1536 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1536_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1536 0x32391c78
+/**< Functionality ID for RSA 1536 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1536 0x4d111cdc
+/**< Functionality ID for RSA 1536 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1536_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1536_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1536 0x4d111cf7
+/**< Functionality ID for RSA 1536 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1536_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_output::m m
+ *@endlink
+ */
+#define PKE_RSA_DP2_1536 0x45111d12
+/**< Functionality ID for RSA 1536 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1536_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_2048 0x72181d2e
+/**< Functionality ID for RSA 2048 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_2048_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_output::d d @endlink
+ */
+#define PKE_RSA_KP2_2048 0x42341d5b
+/**< Functionality ID for RSA 2048 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_2048 0x6e111dba
+/**< Functionality ID for RSA 2048 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_2048_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_2048_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_2048 0x6e111dda
+/**< Functionality ID for RSA 2048 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_2048_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_2048 0x59121dfa
+/**< Functionality ID for RSA 2048 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_2048_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_3072 0x60191e16
+/**< Functionality ID for RSA 3072 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_3072_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_output::d d @endlink
+ */
+#define PKE_RSA_KP2_3072 0x68331e45
+/**< Functionality ID for RSA 3072 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_3072 0x7d111ea3
+/**< Functionality ID for RSA 3072 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_3072_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_3072_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_3072 0x7d111ebe
+/**< Functionality ID for RSA 3072 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_3072_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_3072 0x81121ed9
+/**< Functionality ID for RSA 3072 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_3072_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_4096 0x7d1f1ef6
+/**< Functionality ID for RSA 4096 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_4096_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_output::d d @endlink
+ */
+#define PKE_RSA_KP2_4096 0x91251f27
+/**< Functionality ID for RSA 4096 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_4096 0xa5101f7e
+/**< Functionality ID for RSA 4096 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_4096_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_4096_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_4096 0xa5101f98
+/**< Functionality ID for RSA 4096 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_4096_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_4096 0xb1111fb2
+/**< Functionality ID for RSA 4096 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_4096_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_output::m m
+ * @endlink
+ */
+#define PKE_GCD_PT_192 0x19201fcd
+/**< Functionality ID for GCD primality test for 192-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_192_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_256 0x19201ff7
+/**< Functionality ID for GCD primality test for 256-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_256_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_384 0x19202021
+/**< Functionality ID for GCD primality test for 384-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_384_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_512 0x1b1b204b
+/**< Functionality ID for GCD primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_768 0x170c2070
+/**< Functionality ID for GCD primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1024 0x130f2085
+/**< Functionality ID for GCD primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1536 0x1d0c2094
+/**< Functionality ID for GCD primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_2048 0x210c20a5
+/**< Functionality ID for GCD primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_3072 0x290c20b6
+/**< Functionality ID for GCD primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_4096 0x310c20c7
+/**< Functionality ID for GCD primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_160 0x0e1120d8
+/**< Functionality ID for Fermat primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_512 0x121120ee
+/**< Functionality ID for Fermat primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_L512 0x19162104
+/**< Functionality ID for Fermat primality test for <e; 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_768 0x19112124
+/**< Functionality ID for Fermat primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1024 0x1f11213a
+/**< Functionality ID for Fermat primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1536 0x2b112150
+/**< Functionality ID for Fermat primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_2048 0x3b112166
+/**< Functionality ID for Fermat primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_3072 0x3a11217c
+/**< Functionality ID for Fermat primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_4096 0x4a112192
+/**< Functionality ID for Fermat primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_160 0x0e1221a8
+/**< Functionality ID for Miller-Rabin primality test for 160-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_160_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_160_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_512 0x111221bf
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_768 0x1d0d21d6
+/**< Functionality ID for Miller-Rabin primality test for 768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_768_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_768_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1024 0x250d21ed
+/**< Functionality ID for Miller-Rabin primality test for 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1024_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1024_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1536 0x350d2204
+/**< Functionality ID for Miller-Rabin primality test for 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1536_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1536_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_2048 0x490d221b
+/**< Functionality ID for Miller-Rabin primality test for 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_2048_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_2048_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_3072 0x4d0d2232
+/**< Functionality ID for Miller-Rabin primality test for 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_3072_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_3072_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_4096 0x650d2249
+/**< Functionality ID for Miller-Rabin primality test for 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_4096_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_4096_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_L512 0x18182260
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_l512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_l512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_160 0x0e0c227e
+/**< Functionality ID for Lucas primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_512 0x110c228f
+/**< Functionality ID for Lucas primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_768 0x130c22a0
+/**< Functionality ID for Lucas primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1024 0x150c22b1
+/**< Functionality ID for Lucas primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1536 0x190c22c2
+/**< Functionality ID for Lucas primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_2048 0x1d0c22d3
+/**< Functionality ID for Lucas primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_3072 0x250c22e4
+/**< Functionality ID for Lucas primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_4096 0x661522f5
+/**< Functionality ID for Lucas primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_L512 0x1617230a
+/**< Functionality ID for Lucas primality test for L512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define MATHS_MODEXP_L512 0x150c2327
+/**< Functionality ID for Modular exponentiation for numbers less than 512-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l512_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l512_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l512_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l512_output::r r
+@endlink
+ */
+#define MATHS_MODEXP_L1024 0x2d0c233e
+/**< Functionality ID for Modular exponentiation for numbers less than 1024-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1024_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1024_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1024_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L1536 0x410c2355
+/**< Functionality ID for Modular exponentiation for numbers less than 1536-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1536_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1536_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1536_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2048 0x5e12236c
+/**< Functionality ID for Modular exponentiation for numbers less than 2048-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2048_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2048_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2048_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2560 0x60162388
+/**< Functionality ID for Modular exponentiation for numbers less than 2560-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2560_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2560_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2560_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2560_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3072 0x650c23a9
+/**< Functionality ID for Modular exponentiation for numbers less than 3072-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3072_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3072_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3072_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3584 0x801623c0
+/**< Functionality ID for Modular exponentiation for numbers less than 3584-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3584_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3584_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3584_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3584_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L4096 0x850c23e1
+/**< Functionality ID for Modular exponentiation for numbers less than 4096-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l4096_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l4096_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l4096_output::r r
+ * @endlink
+ */
+#define MATHS_MODINV_ODD_L128 0x090623f8
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l128_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l128_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l128_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L192 0x0a0623fe
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l192_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l192_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l192_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L256 0x0a062404
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l256_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l256_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l256_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L384 0x0b06240a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l384_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l384_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l384_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L512 0x0c062410
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l512_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l512_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l512_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L768 0x0e062416
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l768_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l768_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l768_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L1024 0x1006241c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L1536 0x18062422
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L2048 0x20062428
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L3072 0x3006242e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L4096 0x40062434
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l4096_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L128 0x0906243a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l128_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l128_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l128_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L192 0x0a062440
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l192_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l192_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l192_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L256 0x0a062446
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l256_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l256_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l256_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L384 0x0e0b244c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l384_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l384_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l384_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L512 0x110b2457
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l512_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l512_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l512_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L768 0x170b2462
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l768_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l768_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l768_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1024 0x1d0b246d
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1536 0x290b2478
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L2048 0x350b2483
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L3072 0x4d0b248e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L4096 0x650b2499
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l4096_output::c c @endlink
+ */
+#define PKE_DSA_GEN_P_1024_160 0x381824a4
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_1024_160_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_1024 0x261424d4
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_1024_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_1024 0x291224ed
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_1024_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_1024_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_1024_160 0x2c1c2504
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_160 0x12142526
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_1024_160 0x301e2540
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_1024_160 0x323a2570
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_1024_160_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_1024_160_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_224 0x341d25be
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_224_output::p p @endlink
+ */
+#define PKE_DSA_GEN_Y_2048 0x4d1225ea
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_2048_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_2048_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_224 0x511c2601
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_224 0x15142623
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_224 0x571e263d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_224 0x6930266d
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_224_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_224_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_256 0x431126b7
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_2048 0x4b1426ed
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_2048_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_output::g g
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_256 0x5b182706
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_256 0x15142733
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_256 0x5a2a274d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_256 0x723a2789
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_256_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_3072_256 0x4b1127e0
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_3072_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_3072 0x4f142816
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_3072_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_3072 0x5112282f
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_3072_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_3072_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_3072_256 0x59282846
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_R_S_3072_256 0x61292874
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_3072_256 0x7f4328ae
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_3072_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_3072_256_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L256 0x46512907
+/**< Functionality ID for ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L256 0x323a298f
+/**< Functionality ID for ECDSA Sign R for curves B/K-163 and B/K-233
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L256 0x2b2229e6
+/**< Functionality ID for ECDSA Sign S for curves with n < 2^256
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L256 0x337e2a27
+/**< Functionality ID for ECDSA Verify for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ *icp_qat_fw_mmp_ecdsa_verify_gf2_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L512 0x5e5f2ad7
+/**< Functionality ID for ECDSA Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L512 0x84312b6a
+/**< Functionality ID for ECDSA GF2 Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L512 0x26182bbe
+/**< Functionality ID for ECDSA GF2 Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L512 0x58892bea
+/**< Functionality ID for ECDSA GF2 Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_571 0x554a2c93
+/**< Functionality ID for ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_571 0x52332d09
+/**< Functionality ID for ECDSA GF2 Sign S for curves with deg(q) < 576
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_571 0x731a2d51
+/**< Functionality ID for ECDSA GF2 Sign R for degree 571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_output::r r @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_571 0x4f6c2d91
+/**< Functionality ID for ECDSA GF2 Verify for degree 571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_571_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L256 0x3b242e38
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L256 0x231a2e7c
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L512 0x722c2e96
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L512 0x25132ee2
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_571 0x44152ef5
+/**< Functionality ID for ECC GF2 Point Multiplication for curves B-571/K-571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_571 0x12072f1b
+/**< Functionality ID for ECC GF2 Point Verification for degree 571
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L256 0x515217d9
+/**< Functionality ID for KPT ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L512 0x4d811987
+/**< Functionality ID for KPT ECDSA Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_571 0x45731898
+/**< Functionality ID for KPT ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L256 0x431b2f22
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L256 0x2b252f6d
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L256 0x6a3c2fa6
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L256 0x325b3023
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gfp_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L512 0x4e2530b3
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L512 0x251830fa
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L512 0x5a2b3127
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L512 0x3553318a
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_521 0x772c31fe
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_521 0x52343251
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_521 0x494a329b
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_521 0x554c331f
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_521_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L256 0x432033a6
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L256 0x1f0c33fc
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L512 0x41253419
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L512 0x2612345c
+/**< Functionality ID for ECC GFP Partial Point
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_521 0x5511346e
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_521 0x0e0734be
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L256 0x1b6b182c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L512 0x7439179f
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_521 0x3b7a190c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+
+#define PKE_LIVENESS 0x00000001
+/**< Functionality ID for PKE_LIVENESS
+ * @li 0 input parameter(s)
+ * @li 1 output parameter(s) (8 qwords)
+ */
+#define PKE_INTERFACE_SIGNATURE 0x972ded54
+/**< Encoded signature of the interface specifications
+ */
+
+#define PKE_INVALID_FUNC_ID 0xffffffff
+
+#endif /* __ICP_QAT_FW_MMP_IDS__ */
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_pke.h b/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
new file mode 100644
index 0000000..1c1560a
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_pke.h
+ * @defgroup icp_qat_fw_pke ICP QAT FW PKE Processing Definitions
+ * @ingroup icp_qat_fw
+ * Revision: 0.1
+ * @brief
+ * This file documents the external interfaces that the QAT FW running
+ * on the QAT Acceleration Engine provides to clients wanting to
+ * accelerate crypto assymetric applications
+ */
+
+#ifndef _ICP_QAT_FW_PKE_H_
+#define _ICP_QAT_FW_PKE_H_
+
+/*
+ * Keep all dpdk-specific changes in this section
+ */
+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+/* End of DPDK-specific section
+ * Don't modify below this.
+ */
+
+/*
+ ****************************************************************************
+ * Include local header files
+ ****************************************************************************
+ */
+#include "icp_qat_fw.h"
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response status field structure contained
+ * within LW1, comprising the common error codes and
+ * the response flags.
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp_status {
+ u8 comn_err_code;
+ /**< 8 bit common error code */
+
+ u8 pke_resp_flags;
+ /**< 8-bit PKE response flags */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header pars field.
+ *
+ * @description
+ * PKE request message header pars structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_hdr_pke_cd_pars {
+ /**< LWs 2-3 */
+ u64 content_desc_addr;
+ /**< Content descriptor pointer */
+
+ /**< LW 4 */
+ u32 content_desc_resrvd;
+ /**< Content descriptor reserved field */
+
+ /**< LW 5 */
+ u32 func_id;
+ /**< MMP functionality Id */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header mid section.
+ *
+ * @description
+ * PKE request message header middle structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_mid {
+ /**< LWs 6-11 */
+ u64 opaque;
+ /**< Opaque data passed unmodified from the request to response messages
+ * by firmware (fw)
+ */
+
+ u64 src_data_addr;
+ /**< Generic definition of the source data supplied to the QAT AE. The
+ * common flags are used to further describe the attributes of this
+ * field
+ */
+
+ u64 dest_data_addr;
+ /**< Generic definition of the destination data supplied to the QAT AE.
+ * The common flags are used to further describe the attributes of this
+ * field
+ */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header.
+ *
+ * @description
+ * PKE request message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_hdr {
+ /**< LW0 */
+ u8 resrvd1;
+ /**< reserved field */
+
+ u8 resrvd2;
+ /**< reserved field */
+
+ u8 service_type;
+ /**< Service type */
+
+ u8 hdr_flags;
+ /**< This represents a flags field for the Service Request.
+ * The most significant bit is the 'valid' flag and the only
+ * one used. All remaining bit positions are unused and
+ * are therefore reserved and need to be set to 0.
+ */
+
+ /**< LW1 */
+ u16 comn_req_flags;
+ /**< Common Request flags must indicate flat buffer
+ * Common Request flags - PKE slice flags no longer used - slice
+ * allocated to a threadstrand.
+ */
+
+ u8 kpt_mask;
+ /** < KPT input parameters array mask, indicate which node in array is
+ *encrypted
+ */
+
+ u8 kpt_rn_mask;
+ /**< KPT random node(RN) mask - indicate which node is RN that QAT
+ * should generate itself.
+ */
+
+ /**< LWs 2-5 */
+ struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
+ /**< PKE request message header pars structure */
+};
+
+/**
+ ***************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE request message structure (64 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_request {
+ /**< LWs 0-5 */
+ struct icp_qat_fw_req_pke_hdr pke_hdr;
+ /**< Request header for PKE - CD Header/Param size must be zero */
+
+ /**< LWs 6-11 */
+ struct icp_qat_fw_req_pke_mid pke_mid;
+ /**< Request middle section for PKE */
+
+ /**< LW 12 */
+ u8 output_param_count;
+ /**< Number of output large integers for request */
+
+ u8 input_param_count;
+ /**< Number of input large integers for request */
+
+ u16 resrvd1;
+ /** Reserved **/
+
+ /**< LW 13 */
+ u32 resrvd2;
+ /**< Reserved */
+
+ /**< LWs 14-15 */
+ u64 next_req_adr;
+ /** < PKE - next request address */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_resp_pke_hdr {
+ /**< LW0 */
+ u8 resrvd1;
+ /**< Reserved */
+
+ u8 resrvd2;
+ /**< Reserved */
+
+ u8 response_type;
+ /**< Response type - copied from the request to the response message */
+
+ u8 hdr_flags;
+ /**< This represents a flags field for the Response.
+ * The most significant bit is the 'valid' flag and the only
+ * one used. All remaining bit positions are unused and
+ * are therefore reserved
+ */
+
+ /**< LW1 */
+ struct icp_qat_fw_pke_resp_status resp_status;
+
+ u16 resrvd4;
+ /**< Set to zero. */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response message structure (32 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
+ /**< Response header for PKE */
+
+ /**< LWs 2-3 */
+ u64 opaque;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-5 */
+ u64 src_data_addr;
+ /**< Generic definition of the source data supplied to the QAT AE. The
+ * common flags are used to further describe the attributes of this
+ * field
+ */
+
+ /**< LWs 6-7 */
+ u64 dest_data_addr;
+ /**< Generic definition of the destination data supplied to the QAT AE.
+ * The common flags are used to further describe the attributes of this
+ * field
+ */
+};
+
+/* ========================================================================= */
+/* MACRO DEFINITIONS */
+/* ========================================================================= */
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the 'valid' flag, within the
+ * hdr_flags field of LW0 (service request and response) of the PKE request
+ */
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK 0x1
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the PKE status flag, within the
+ * status field LW1 of a PKE response message
+ */
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+/**< @ingroup icp_qat_fw_pke
+ * Starting bit position indicating the PKE status flag within the PKE response
+ * pke_resp_flags byte.
+ */
+
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
+/**< @ingroup icp_qat_fw_pke
+ * One bit mask used to determine PKE status mask
+ */
+
+/*
+ * < @ingroup icp_qat_fw_pke
+ * *** PKE Response Status Field Definition ***
+ * The PKE response follows the CPM 1.5 message format. The status field is
+ * 16 bits wide, where the status flags are contained within the most
+ * significant byte of the icp_qat_fw_pke_resp_status structure.
+ * The lower 8 bits of this word now contain the common error codes,
+ * which are defined in the common header file(*).
+ */
+/* +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ * | Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | [7....0] |
+ * +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ * |Flags|Rsrvd|Pke |Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Common error codes(*)|
+ * +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ */
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Macro for extraction of the PKE bit from the 16-bit status field
+ * particular to a PKE response. The status flags are contained within
+ * the most significant byte of the word. The lower 8 bits of this status
+ * word now contain the common error codes, which are defined in the common
+ * header file. The appropriate macro definition to extract the PKE status
+ * lag from the PKE response assumes that a single byte i.e. pke_resp_flags
+ * is passed to the macro.
+ *
+ * @param status
+ * Status to extract the PKE status bit
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(flags) \
+ QAT_FIELD_GET((flags), QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Extract the valid flag from the PKE Request's header flags. Note that
+ * this invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr Structure passed to extract the valid bit
+ * from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Set the valid bit in the PKE Request's header flags. Note that
+ * this invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr Structure passed to set the valid bit.
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Extract the valid flag from the PKE Response's header flags. Note that
+ * invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr Structure to extract the valid bit
+ * from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Set the valid bit in the PKE Response's header flags. Note that
+ * this invokes the common macro which may be used by either the
+ * request or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr Structure to set the valid bit
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Common macro to extract the valid flag from the header flags field
+ * within the header structure (request or response).
+ *
+ * @param hdr Structure (request or response) to extract the
+ * valid bit from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(hdr) \
+ QAT_FIELD_GET(hdr.hdr_flags, ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Common macro to set the valid bit in the header flags field within
+ * the header structure (request or response).
+ *
+ * @param hdr Structure (request or response) containing the header
+ * flags field, to allow the valid bit to be set.
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr, val) \
+ QAT_FIELD_SET((hdr.hdr_flags), (val), \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+#endif /* _ICP_QAT_FW_PKE_H_ */
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
new file mode 100644
index 0000000..1fdb45a
--- /dev/null
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+#define _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+
+#include "icp_qat_fw_mmp_ids.h"
+
+/*
+ * Modular exponentiation functionality IDs
+ */
+static const uint32_t __rte_unused MOD_EXP_SIZE[][2] = {
+ { 512, MATHS_MODEXP_L512 },
+ { 1024, MATHS_MODEXP_L1024 },
+ { 1536, MATHS_MODEXP_L1536 },
+ { 2048, MATHS_MODEXP_L2048 },
+ { 2560, MATHS_MODEXP_L2560 },
+ { 3072, MATHS_MODEXP_L3072 },
+ { 3584, MATHS_MODEXP_L3584 },
+ { 4096, MATHS_MODEXP_L4096 }
+};
+
+static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
+ { 128, MATHS_MODINV_ODD_L128 },
+ { 192, MATHS_MODINV_ODD_L192 },
+ { 256, MATHS_MODINV_ODD_L256 },
+ { 384, MATHS_MODINV_ODD_L384 },
+ { 512, MATHS_MODINV_ODD_L512 },
+ { 768, MATHS_MODINV_ODD_L768 },
+ { 1024, MATHS_MODINV_ODD_L1024 },
+ { 1536, MATHS_MODINV_ODD_L1536 },
+ { 2048, MATHS_MODINV_ODD_L2048 },
+ { 3072, MATHS_MODINV_ODD_L3072 },
+ { 4096, MATHS_MODINV_ODD_L4096 },
+};
+
+static const uint32_t __rte_unused MOD_INV_IDS_EVEN[][2] = {
+ { 128, MATHS_MODINV_EVEN_L128 },
+ { 192, MATHS_MODINV_EVEN_L192 },
+ { 256, MATHS_MODINV_EVEN_L256 },
+ { 384, MATHS_MODINV_EVEN_L384 },
+ { 512, MATHS_MODINV_EVEN_L512 },
+ { 768, MATHS_MODINV_EVEN_L768 },
+ { 1024, MATHS_MODINV_EVEN_L1024 },
+ { 1536, MATHS_MODINV_EVEN_L1536 },
+ { 2048, MATHS_MODINV_EVEN_L2048 },
+ { 3072, MATHS_MODINV_EVEN_L3072 },
+ { 4096, MATHS_MODINV_EVEN_L4096 },
+};
+
+#endif
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* [dpdk-dev] [PATCH v5 1/4] common/qat: add headers for asymmetric crypto
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 1/4] common/qat: add headers for asymmetric crypto Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
0 siblings, 0 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds headers to be used in conjunction with asymmetric
cryptography operations using Intel QuickAssist Technology driver
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h | 1538 ++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_fw_pke.h | 426 ++++++
.../qat/qat_adf/qat_pke_functionality_arrays.h | 52 +
3 files changed, 2016 insertions(+)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_pke.h
create mode 100644 drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h b/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
new file mode 100644
index 0000000..d9a42dd
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
@@ -0,0 +1,1538 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_mmp_ids.h
+ * @ingroup icp_qat_fw_mmp
+ * @brief
+ * This file documents the external interfaces that the QAT FW running
+ * on the QAT Acceleration Engine provides to clients wanting to
+ * accelerate crypto assymetric applications
+ */
+
+#ifndef _ICP_QAT_FW_MMP_IDS_
+#define _ICP_QAT_FW_MMP_IDS_
+
+#define PKE_INIT 0x09061a09
+/**< Functionality ID for Initialisation sequence
+ * @li 1 input parameters : @link icp_qat_fw_mmp_init_input::z z @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_init_output::zz zz @endlink
+ */
+#define PKE_DH_G2_768 0x1c0b1a10
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ *768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_768_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_768_output::r r
+ * @endlink
+ */
+#define PKE_DH_768 0x210c1a1b
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 768-bit
+ *numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_768_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_768_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_768_output::r r @endlink
+ */
+#define PKE_DH_G2_1024 0x220b1a27
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1024_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1024_output::r r
+ * @endlink
+ */
+#define PKE_DH_1024 0x290c1a32
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1024-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1024_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1024_output::r r @endlink
+ */
+#define PKE_DH_G2_1536 0x2e0b1a3e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1536_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1536_output::r r
+ * @endlink
+ */
+#define PKE_DH_1536 0x390c1a49
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1536-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1536_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1536_output::r r @endlink
+ */
+#define PKE_DH_G2_2048 0x3e0b1a55
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_2048_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_2048_output::r r
+ * @endlink
+ */
+#define PKE_DH_2048 0x4d0c1a60
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 2048-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_2048_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_2048_output::r r @endlink
+ */
+#define PKE_DH_G2_3072 0x3a0b1a6c
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_3072_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_3072_output::r r
+ * @endlink
+ */
+#define PKE_DH_3072 0x510c1a77
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 3072-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_3072_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_3072_output::r r @endlink
+ */
+#define PKE_DH_G2_4096 0x4a0b1a83
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_4096_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_4096_output::r r
+ * @endlink
+ */
+#define PKE_DH_4096 0x690c1a8e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 4096-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_4096_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_4096_output::r r @endlink
+ */
+#define PKE_RSA_KP1_512 0x191d1a9a
+/**< Functionality ID for RSA 512 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_512_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_output::d d @endlink
+ */
+#define PKE_RSA_KP2_512 0x19401acc
+/**< Functionality ID for RSA 512 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_512 0x1c161b21
+/**< Functionality ID for RSA 512 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_512_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_512_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_512_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_512 0x1c161b3c
+/**< Functionality ID for RSA 512 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_512_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_512 0x1c131b57
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_512_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1024 0x36181b71
+/**< Functionality ID for RSA 1024 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1024_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1024 0x40451b9e
+/**< Functionality ID for RSA 1024 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1024 0x35111bf7
+/**< Functionality ID for RSA 1024 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1024_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1024_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1024 0x35111c12
+/**< Functionality ID for RSA 1024 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1024_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_1024 0x26131c2d
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1024_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1536 0x531d1c46
+/**< Functionality ID for RSA 1536 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1536_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1536 0x32391c78
+/**< Functionality ID for RSA 1536 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1536 0x4d111cdc
+/**< Functionality ID for RSA 1536 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1536_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1536_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1536 0x4d111cf7
+/**< Functionality ID for RSA 1536 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1536_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_output::m m
+ *@endlink
+ */
+#define PKE_RSA_DP2_1536 0x45111d12
+/**< Functionality ID for RSA 1536 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1536_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_2048 0x72181d2e
+/**< Functionality ID for RSA 2048 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_2048_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_output::d d @endlink
+ */
+#define PKE_RSA_KP2_2048 0x42341d5b
+/**< Functionality ID for RSA 2048 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_2048 0x6e111dba
+/**< Functionality ID for RSA 2048 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_2048_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_2048_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_2048 0x6e111dda
+/**< Functionality ID for RSA 2048 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_2048_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_2048 0x59121dfa
+/**< Functionality ID for RSA 2048 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_2048_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_3072 0x60191e16
+/**< Functionality ID for RSA 3072 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_3072_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_output::d d @endlink
+ */
+#define PKE_RSA_KP2_3072 0x68331e45
+/**< Functionality ID for RSA 3072 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_3072 0x7d111ea3
+/**< Functionality ID for RSA 3072 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_3072_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_3072_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_3072 0x7d111ebe
+/**< Functionality ID for RSA 3072 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_3072_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_3072 0x81121ed9
+/**< Functionality ID for RSA 3072 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_3072_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_4096 0x7d1f1ef6
+/**< Functionality ID for RSA 4096 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_4096_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_output::d d @endlink
+ */
+#define PKE_RSA_KP2_4096 0x91251f27
+/**< Functionality ID for RSA 4096 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_4096 0xa5101f7e
+/**< Functionality ID for RSA 4096 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_4096_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_4096_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_4096 0xa5101f98
+/**< Functionality ID for RSA 4096 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_4096_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_4096 0xb1111fb2
+/**< Functionality ID for RSA 4096 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_4096_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_output::m m
+ * @endlink
+ */
+#define PKE_GCD_PT_192 0x19201fcd
+/**< Functionality ID for GCD primality test for 192-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_192_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_256 0x19201ff7
+/**< Functionality ID for GCD primality test for 256-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_256_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_384 0x19202021
+/**< Functionality ID for GCD primality test for 384-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_384_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_512 0x1b1b204b
+/**< Functionality ID for GCD primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_768 0x170c2070
+/**< Functionality ID for GCD primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1024 0x130f2085
+/**< Functionality ID for GCD primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1536 0x1d0c2094
+/**< Functionality ID for GCD primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_2048 0x210c20a5
+/**< Functionality ID for GCD primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_3072 0x290c20b6
+/**< Functionality ID for GCD primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_4096 0x310c20c7
+/**< Functionality ID for GCD primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_160 0x0e1120d8
+/**< Functionality ID for Fermat primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_512 0x121120ee
+/**< Functionality ID for Fermat primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_L512 0x19162104
+/**< Functionality ID for Fermat primality test for <e; 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_768 0x19112124
+/**< Functionality ID for Fermat primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1024 0x1f11213a
+/**< Functionality ID for Fermat primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1536 0x2b112150
+/**< Functionality ID for Fermat primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_2048 0x3b112166
+/**< Functionality ID for Fermat primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_3072 0x3a11217c
+/**< Functionality ID for Fermat primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_4096 0x4a112192
+/**< Functionality ID for Fermat primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_160 0x0e1221a8
+/**< Functionality ID for Miller-Rabin primality test for 160-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_160_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_160_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_512 0x111221bf
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_768 0x1d0d21d6
+/**< Functionality ID for Miller-Rabin primality test for 768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_768_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_768_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1024 0x250d21ed
+/**< Functionality ID for Miller-Rabin primality test for 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1024_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1024_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1536 0x350d2204
+/**< Functionality ID for Miller-Rabin primality test for 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1536_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1536_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_2048 0x490d221b
+/**< Functionality ID for Miller-Rabin primality test for 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_2048_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_2048_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_3072 0x4d0d2232
+/**< Functionality ID for Miller-Rabin primality test for 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_3072_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_3072_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_4096 0x650d2249
+/**< Functionality ID for Miller-Rabin primality test for 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_4096_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_4096_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_L512 0x18182260
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_l512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_l512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_160 0x0e0c227e
+/**< Functionality ID for Lucas primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_512 0x110c228f
+/**< Functionality ID for Lucas primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_768 0x130c22a0
+/**< Functionality ID for Lucas primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1024 0x150c22b1
+/**< Functionality ID for Lucas primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1536 0x190c22c2
+/**< Functionality ID for Lucas primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_2048 0x1d0c22d3
+/**< Functionality ID for Lucas primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_3072 0x250c22e4
+/**< Functionality ID for Lucas primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_4096 0x661522f5
+/**< Functionality ID for Lucas primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_L512 0x1617230a
+/**< Functionality ID for Lucas primality test for L512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define MATHS_MODEXP_L512 0x150c2327
+/**< Functionality ID for Modular exponentiation for numbers less than 512-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l512_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l512_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l512_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l512_output::r r
+@endlink
+ */
+#define MATHS_MODEXP_L1024 0x2d0c233e
+/**< Functionality ID for Modular exponentiation for numbers less than 1024-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1024_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1024_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1024_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L1536 0x410c2355
+/**< Functionality ID for Modular exponentiation for numbers less than 1536-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1536_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1536_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1536_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2048 0x5e12236c
+/**< Functionality ID for Modular exponentiation for numbers less than 2048-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2048_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2048_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2048_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2560 0x60162388
+/**< Functionality ID for Modular exponentiation for numbers less than 2560-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2560_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2560_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2560_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2560_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3072 0x650c23a9
+/**< Functionality ID for Modular exponentiation for numbers less than 3072-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3072_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3072_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3072_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3584 0x801623c0
+/**< Functionality ID for Modular exponentiation for numbers less than 3584-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3584_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3584_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3584_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3584_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L4096 0x850c23e1
+/**< Functionality ID for Modular exponentiation for numbers less than 4096-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l4096_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l4096_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l4096_output::r r
+ * @endlink
+ */
+#define MATHS_MODINV_ODD_L128 0x090623f8
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l128_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l128_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l128_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L192 0x0a0623fe
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l192_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l192_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l192_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L256 0x0a062404
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l256_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l256_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l256_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L384 0x0b06240a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l384_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l384_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l384_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L512 0x0c062410
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l512_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l512_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l512_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L768 0x0e062416
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l768_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l768_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l768_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L1024 0x1006241c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L1536 0x18062422
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L2048 0x20062428
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L3072 0x3006242e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L4096 0x40062434
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l4096_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L128 0x0906243a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l128_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l128_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l128_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L192 0x0a062440
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l192_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l192_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l192_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L256 0x0a062446
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l256_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l256_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l256_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L384 0x0e0b244c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l384_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l384_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l384_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L512 0x110b2457
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l512_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l512_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l512_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L768 0x170b2462
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l768_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l768_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l768_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1024 0x1d0b246d
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1536 0x290b2478
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L2048 0x350b2483
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L3072 0x4d0b248e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L4096 0x650b2499
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l4096_output::c c @endlink
+ */
+#define PKE_DSA_GEN_P_1024_160 0x381824a4
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_1024_160_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_1024 0x261424d4
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_1024_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_1024 0x291224ed
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_1024_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_1024_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_1024_160 0x2c1c2504
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_160 0x12142526
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_1024_160 0x301e2540
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_1024_160 0x323a2570
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_1024_160_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_1024_160_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_224 0x341d25be
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_224_output::p p @endlink
+ */
+#define PKE_DSA_GEN_Y_2048 0x4d1225ea
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_2048_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_2048_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_224 0x511c2601
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_224 0x15142623
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_224 0x571e263d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_224 0x6930266d
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_224_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_224_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_256 0x431126b7
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_2048 0x4b1426ed
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_2048_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_output::g g
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_256 0x5b182706
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_256 0x15142733
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_256 0x5a2a274d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_256 0x723a2789
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_256_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_3072_256 0x4b1127e0
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_3072_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_3072 0x4f142816
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_3072_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_3072 0x5112282f
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_3072_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_3072_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_3072_256 0x59282846
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_R_S_3072_256 0x61292874
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_3072_256 0x7f4328ae
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_3072_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_3072_256_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L256 0x46512907
+/**< Functionality ID for ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L256 0x323a298f
+/**< Functionality ID for ECDSA Sign R for curves B/K-163 and B/K-233
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L256 0x2b2229e6
+/**< Functionality ID for ECDSA Sign S for curves with n < 2^256
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L256 0x337e2a27
+/**< Functionality ID for ECDSA Verify for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ *icp_qat_fw_mmp_ecdsa_verify_gf2_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L512 0x5e5f2ad7
+/**< Functionality ID for ECDSA Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L512 0x84312b6a
+/**< Functionality ID for ECDSA GF2 Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L512 0x26182bbe
+/**< Functionality ID for ECDSA GF2 Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L512 0x58892bea
+/**< Functionality ID for ECDSA GF2 Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_571 0x554a2c93
+/**< Functionality ID for ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_571 0x52332d09
+/**< Functionality ID for ECDSA GF2 Sign S for curves with deg(q) < 576
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_571 0x731a2d51
+/**< Functionality ID for ECDSA GF2 Sign R for degree 571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_output::r r @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_571 0x4f6c2d91
+/**< Functionality ID for ECDSA GF2 Verify for degree 571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_571_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L256 0x3b242e38
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L256 0x231a2e7c
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L512 0x722c2e96
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L512 0x25132ee2
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_571 0x44152ef5
+/**< Functionality ID for ECC GF2 Point Multiplication for curves B-571/K-571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_571 0x12072f1b
+/**< Functionality ID for ECC GF2 Point Verification for degree 571
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L256 0x515217d9
+/**< Functionality ID for KPT ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L512 0x4d811987
+/**< Functionality ID for KPT ECDSA Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_571 0x45731898
+/**< Functionality ID for KPT ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L256 0x431b2f22
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L256 0x2b252f6d
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L256 0x6a3c2fa6
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L256 0x325b3023
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gfp_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L512 0x4e2530b3
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L512 0x251830fa
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L512 0x5a2b3127
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L512 0x3553318a
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_521 0x772c31fe
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_521 0x52343251
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_521 0x494a329b
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_521 0x554c331f
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_521_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L256 0x432033a6
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L256 0x1f0c33fc
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L512 0x41253419
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L512 0x2612345c
+/**< Functionality ID for ECC GFP Partial Point
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_521 0x5511346e
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_521 0x0e0734be
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L256 0x1b6b182c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L512 0x7439179f
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_521 0x3b7a190c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+
+#define PKE_LIVENESS 0x00000001
+/**< Functionality ID for PKE_LIVENESS
+ * @li 0 input parameter(s)
+ * @li 1 output parameter(s) (8 qwords)
+ */
+#define PKE_INTERFACE_SIGNATURE 0x972ded54
+/**< Encoded signature of the interface specifications
+ */
+
+#define PKE_INVALID_FUNC_ID 0xffffffff
+
+#endif /* __ICP_QAT_FW_MMP_IDS__ */
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_pke.h b/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
new file mode 100644
index 0000000..1c1560a
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_pke.h
+ * @defgroup icp_qat_fw_pke ICP QAT FW PKE Processing Definitions
+ * @ingroup icp_qat_fw
+ * Revision: 0.1
+ * @brief
+ * This file documents the external interfaces that the QAT FW running
+ * on the QAT Acceleration Engine provides to clients wanting to
+ * accelerate crypto assymetric applications
+ */
+
+#ifndef _ICP_QAT_FW_PKE_H_
+#define _ICP_QAT_FW_PKE_H_
+
+/*
+ * Keep all dpdk-specific changes in this section
+ */
+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+/* End of DPDK-specific section
+ * Don't modify below this.
+ */
+
+/*
+ ****************************************************************************
+ * Include local header files
+ ****************************************************************************
+ */
+#include "icp_qat_fw.h"
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response status field structure contained
+ * within LW1, comprising the common error codes and
+ * the response flags.
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp_status {
+ u8 comn_err_code;
+ /**< 8 bit common error code */
+
+ u8 pke_resp_flags;
+ /**< 8-bit PKE response flags */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header pars field.
+ *
+ * @description
+ * PKE request message header pars structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_hdr_pke_cd_pars {
+ /**< LWs 2-3 */
+ u64 content_desc_addr;
+ /**< Content descriptor pointer */
+
+ /**< LW 4 */
+ u32 content_desc_resrvd;
+ /**< Content descriptor reserved field */
+
+ /**< LW 5 */
+ u32 func_id;
+ /**< MMP functionality Id */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header mid section.
+ *
+ * @description
+ * PKE request message header middle structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_mid {
+ /**< LWs 6-11 */
+ u64 opaque;
+ /**< Opaque data passed unmodified from the request to response messages
+ * by firmware (fw)
+ */
+
+ u64 src_data_addr;
+ /**< Generic definition of the source data supplied to the QAT AE. The
+ * common flags are used to further describe the attributes of this
+ * field
+ */
+
+ u64 dest_data_addr;
+ /**< Generic definition of the destination data supplied to the QAT AE.
+ * The common flags are used to further describe the attributes of this
+ * field
+ */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ * Definition of the QAT FW PKE request header.
+ *
+ * @description
+ * PKE request message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_hdr {
+ /**< LW0 */
+ u8 resrvd1;
+ /**< reserved field */
+
+ u8 resrvd2;
+ /**< reserved field */
+
+ u8 service_type;
+ /**< Service type */
+
+ u8 hdr_flags;
+ /**< This represents a flags field for the Service Request.
+ * The most significant bit is the 'valid' flag and the only
+ * one used. All remaining bit positions are unused and
+ * are therefore reserved and need to be set to 0.
+ */
+
+ /**< LW1 */
+ u16 comn_req_flags;
+ /**< Common Request flags must indicate flat buffer
+ * Common Request flags - PKE slice flags no longer used - slice
+ * allocated to a threadstrand.
+ */
+
+ u8 kpt_mask;
+ /** < KPT input parameters array mask, indicate which node in array is
+ *encrypted
+ */
+
+ u8 kpt_rn_mask;
+ /**< KPT random node(RN) mask - indicate which node is RN that QAT
+ * should generate itself.
+ */
+
+ /**< LWs 2-5 */
+ struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
+ /**< PKE request message header pars structure */
+};
+
+/**
+ ***************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE request message structure (64 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_request {
+ /**< LWs 0-5 */
+ struct icp_qat_fw_req_pke_hdr pke_hdr;
+ /**< Request header for PKE - CD Header/Param size must be zero */
+
+ /**< LWs 6-11 */
+ struct icp_qat_fw_req_pke_mid pke_mid;
+ /**< Request middle section for PKE */
+
+ /**< LW 12 */
+ u8 output_param_count;
+ /**< Number of output large integers for request */
+
+ u8 input_param_count;
+ /**< Number of input large integers for request */
+
+ u16 resrvd1;
+ /** Reserved **/
+
+ /**< LW 13 */
+ u32 resrvd2;
+ /**< Reserved */
+
+ /**< LWs 14-15 */
+ u64 next_req_adr;
+ /** < PKE - next request address */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_resp_pke_hdr {
+ /**< LW0 */
+ u8 resrvd1;
+ /**< Reserved */
+
+ u8 resrvd2;
+ /**< Reserved */
+
+ u8 response_type;
+ /**< Response type - copied from the request to the response message */
+
+ u8 hdr_flags;
+ /**< This represents a flags field for the Response.
+ * The most significant bit is the 'valid' flag and the only
+ * one used. All remaining bit positions are unused and
+ * are therefore reserved
+ */
+
+ /**< LW1 */
+ struct icp_qat_fw_pke_resp_status resp_status;
+
+ u16 resrvd4;
+ /**< Set to zero. */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ * PKE response message structure (32 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
+ /**< Response header for PKE */
+
+ /**< LWs 2-3 */
+ u64 opaque;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-5 */
+ u64 src_data_addr;
+ /**< Generic definition of the source data supplied to the QAT AE. The
+ * common flags are used to further describe the attributes of this
+ * field
+ */
+
+ /**< LWs 6-7 */
+ u64 dest_data_addr;
+ /**< Generic definition of the destination data supplied to the QAT AE.
+ * The common flags are used to further describe the attributes of this
+ * field
+ */
+};
+
+/* ========================================================================= */
+/* MACRO DEFINITIONS */
+/* ========================================================================= */
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the 'valid' flag, within the
+ * hdr_flags field of LW0 (service request and response) of the PKE request
+ */
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK 0x1
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the PKE status flag, within the
+ * status field LW1 of a PKE response message
+ */
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+/**< @ingroup icp_qat_fw_pke
+ * Starting bit position indicating the PKE status flag within the PKE response
+ * pke_resp_flags byte.
+ */
+
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
+/**< @ingroup icp_qat_fw_pke
+ * One bit mask used to determine PKE status mask
+ */
+
+/*
+ * < @ingroup icp_qat_fw_pke
+ * *** PKE Response Status Field Definition ***
+ * The PKE response follows the CPM 1.5 message format. The status field is
+ * 16 bits wide, where the status flags are contained within the most
+ * significant byte of the icp_qat_fw_pke_resp_status structure.
+ * The lower 8 bits of this word now contain the common error codes,
+ * which are defined in the common header file(*).
+ */
+/* +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ * | Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | [7....0] |
+ * +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ * |Flags|Rsrvd|Pke |Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Common error codes(*)|
+ * +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ */
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Macro for extraction of the PKE bit from the 16-bit status field
+ * particular to a PKE response. The status flags are contained within
+ * the most significant byte of the word. The lower 8 bits of this status
+ * word now contain the common error codes, which are defined in the common
+ * header file. The appropriate macro definition to extract the PKE status
+ * lag from the PKE response assumes that a single byte i.e. pke_resp_flags
+ * is passed to the macro.
+ *
+ * @param status
+ * Status to extract the PKE status bit
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(flags) \
+ QAT_FIELD_GET((flags), QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Extract the valid flag from the PKE Request's header flags. Note that
+ * this invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr Structure passed to extract the valid bit
+ * from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Set the valid bit in the PKE Request's header flags. Note that
+ * this invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr Structure passed to set the valid bit.
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Extract the valid flag from the PKE Response's header flags. Note that
+ * invokes the common macro which may be used by either the request
+ * or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr Structure to extract the valid bit
+ * from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Set the valid bit in the PKE Response's header flags. Note that
+ * this invokes the common macro which may be used by either the
+ * request or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr Structure to set the valid bit
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val) \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Common macro to extract the valid flag from the header flags field
+ * within the header structure (request or response).
+ *
+ * @param hdr Structure (request or response) to extract the
+ * valid bit from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(hdr) \
+ QAT_FIELD_GET(hdr.hdr_flags, ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ * Common macro to set the valid bit in the header flags field within
+ * the header structure (request or response).
+ *
+ * @param hdr Structure (request or response) containing the header
+ * flags field, to allow the valid bit to be set.
+ * @param val Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr, val) \
+ QAT_FIELD_SET((hdr.hdr_flags), (val), \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
+ ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+#endif /* _ICP_QAT_FW_PKE_H_ */
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
new file mode 100644
index 0000000..1fdb45a
--- /dev/null
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+#define _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+
+#include "icp_qat_fw_mmp_ids.h"
+
+/*
+ * Modular exponentiation functionality IDs
+ */
+static const uint32_t __rte_unused MOD_EXP_SIZE[][2] = {
+ { 512, MATHS_MODEXP_L512 },
+ { 1024, MATHS_MODEXP_L1024 },
+ { 1536, MATHS_MODEXP_L1536 },
+ { 2048, MATHS_MODEXP_L2048 },
+ { 2560, MATHS_MODEXP_L2560 },
+ { 3072, MATHS_MODEXP_L3072 },
+ { 3584, MATHS_MODEXP_L3584 },
+ { 4096, MATHS_MODEXP_L4096 }
+};
+
+static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
+ { 128, MATHS_MODINV_ODD_L128 },
+ { 192, MATHS_MODINV_ODD_L192 },
+ { 256, MATHS_MODINV_ODD_L256 },
+ { 384, MATHS_MODINV_ODD_L384 },
+ { 512, MATHS_MODINV_ODD_L512 },
+ { 768, MATHS_MODINV_ODD_L768 },
+ { 1024, MATHS_MODINV_ODD_L1024 },
+ { 1536, MATHS_MODINV_ODD_L1536 },
+ { 2048, MATHS_MODINV_ODD_L2048 },
+ { 3072, MATHS_MODINV_ODD_L3072 },
+ { 4096, MATHS_MODINV_ODD_L4096 },
+};
+
+static const uint32_t __rte_unused MOD_INV_IDS_EVEN[][2] = {
+ { 128, MATHS_MODINV_EVEN_L128 },
+ { 192, MATHS_MODINV_EVEN_L192 },
+ { 256, MATHS_MODINV_EVEN_L256 },
+ { 384, MATHS_MODINV_EVEN_L384 },
+ { 512, MATHS_MODINV_EVEN_L512 },
+ { 768, MATHS_MODINV_EVEN_L768 },
+ { 1024, MATHS_MODINV_EVEN_L1024 },
+ { 1536, MATHS_MODINV_EVEN_L1536 },
+ { 2048, MATHS_MODINV_EVEN_L2048 },
+ { 3072, MATHS_MODINV_EVEN_L3072 },
+ { 4096, MATHS_MODINV_EVEN_L4096 },
+};
+
+#endif
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
2019-03-28 13:36 ` Arek Kusztal
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 1/4] common/qat: add headers for asymmetric crypto Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` Arek Kusztal
2019-04-03 8:42 ` Akhil Goyal
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 3/4] crypto/qat: add modular exponentiation to qat asym pmd Arek Kusztal
` (2 subsequent siblings)
5 siblings, 2 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This patch adds Poll Mode Driver for asymmetric crypto
functions of Intel QuickAssist Technology hardware.
It contains plain driver with no functions implmented, specific
algorithms will be introduced in separate patches.
This patch depends on a QAT PF driver for device initialization. See
the file docs/guides/cryptodevs/qat.rst for configuration details.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
config/common_base | 1 +
doc/guides/cryptodevs/qat.rst | 7 +
drivers/common/qat/Makefile | 8 +
drivers/common/qat/qat_device.h | 12 +-
drivers/common/qat/qat_qp.c | 8 +
drivers/crypto/qat/meson.build | 5 +-
drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
drivers/crypto/qat/qat_asym.h | 97 +++++++++
drivers/crypto/qat/qat_asym_capabilities.h | 10 +
drivers/crypto/qat/qat_asym_pmd.c | 308 +++++++++++++++++++++++++++++
drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
drivers/crypto/qat/qat_sym_pmd.c | 1 -
drivers/crypto/qat/qat_sym_pmd.h | 3 +-
mk/rte.app.mk | 1 +
14 files changed, 742 insertions(+), 5 deletions(-)
create mode 100644 drivers/crypto/qat/qat_asym.c
create mode 100644 drivers/crypto/qat/qat_asym.h
create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
diff --git a/config/common_base b/config/common_base
index 0b09a93..d1dd66a 100644
--- a/config/common_base
+++ b/config/common_base
@@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
+CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index da9655c..53a8d61 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -101,7 +101,13 @@ of all the items described above, including the padding at the end.
Also, offset of data to authenticate "op.sym.auth.data.offset"
must be such that points at the start of the COUNT bytes.
+Asymmetric Crypto Service on QAT
+-------------------------------
+
+The QAT Asym PMD has support for:
+Limitations
+~~~~~~~~~~~
.. _building_qat:
@@ -112,6 +118,7 @@ A QAT device can host multiple acceleration services:
* symmetric cryptography
* data compression
+* asymmetric cryptography
These services are provided to DPDK applications via PMDs which register to
implement the corresponding cryptodev and compressdev APIs. The PMDs use
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index c68a032..792058d 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -25,6 +25,14 @@ endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM),y)
+ LDLIBS += -lrte_cryptodev
+ LDLIBS += -lcrypto
+ CFLAGS += -DBUILD_QAT_ASYM
+ SRCS-y += qat_asym.c
+ SRCS-y += qat_asym_pmd.c
+ build_qat = yes
+endif
ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index eb81c78..131375e 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -31,6 +31,7 @@ enum qat_comp_num_im_buffers {
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_asym_dev_private;
struct qat_comp_dev_private;
struct qat_pci_device {
@@ -57,7 +58,16 @@ struct qat_pci_device {
struct qat_sym_dev_private *sym_dev;
/**< link back to cryptodev private data */
struct rte_device sym_rte_dev;
- /**< This represents the crypto subset of this pci device.
+ /**< This represents the crypto sym subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a crypto-specific name
+ */
+
+ /* Data relating to asymmetric crypto service */
+ struct qat_asym_dev_private *asym_dev;
+ /**< link back to cryptodev private data */
+ struct rte_device asym_rte_dev;
+ /**< This represents the crypto asym subset of this pci device.
* Register with this rather than with the one in
* pci_dev so that its driver can have a crypto-specific name
*/
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 4e66c58..febc2ef 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_asym.h"
#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -273,6 +274,7 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,
QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
goto create_err;
}
+ memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
}
qp->qat_dev_gen = qat_dev->qat_dev_gen;
@@ -648,6 +650,12 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
qat_comp_process_response(ops, resp_msg,
&tmp_qp->stats.dequeue_err_count);
+ else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
+#ifdef BUILD_QAT_ASYM
+ qat_asym_process_response(ops, resp_msg,
+ tmp_qp->op_cookies[head / rx_queue->msg_size]);
+#endif
+ }
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 21f9697..710b081 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -11,7 +11,10 @@ if dep.found()
# Add our sources files to the list
qat_sources += files('qat_sym_pmd.c',
'qat_sym.c',
- 'qat_sym_session.c')
+ 'qat_sym_session.c',
+ 'qat_asym_pmd.c',
+ 'qat_asym.c')
qat_ext_deps += dep
qat_cflags += '-DBUILD_QAT_SYM'
+ qat_cflags += '-DBUILD_QAT_ASYM'
endif
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
new file mode 100644
index 0000000..708bafa
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym.c
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <stdarg.h>
+
+#include "qat_asym.h"
+#include "icp_qat_fw_pke.h"
+#include "icp_qat_fw.h"
+#include "qat_pke_functionality_arrays.h"
+
+#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
+
+static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
+ size_t arr_sz, size_t *size, uint32_t *func_id)
+{
+ size_t i;
+
+ for (i = 0; i < arr_sz; i++) {
+ if (*size <= arr[i][0]) {
+ *size = arr[i][0];
+ *func_id = arr[i][1];
+ return 0;
+ }
+ }
+ return -1;
+}
+
+static void qat_asym_build_req_tmpl(void *sess_private_data,
+ struct rte_crypto_asym_xform __rte_unused *xform)
+{
+
+ struct icp_qat_fw_pke_request *qat_req;
+ struct qat_asym_session *session = sess_private_data;
+
+ qat_req = &session->req_tmpl;
+ memset(qat_req, 0, sizeof(*qat_req));
+ qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
+
+ qat_req->pke_hdr.hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD
+ (ICP_QAT_FW_COMN_REQ_FLAG_SET);
+ qat_req->pke_hdr.comn_req_flags = 0;
+ qat_req->pke_hdr.resrvd1 = 0;
+ qat_req->pke_hdr.resrvd2 = 0;
+ qat_req->pke_hdr.kpt_mask = 0;
+ qat_req->pke_hdr.kpt_rn_mask = 0;
+ qat_req->pke_hdr.cd_pars.content_desc_addr = 0;
+ qat_req->pke_hdr.cd_pars.content_desc_resrvd = 0;
+ qat_req->resrvd1 = 0;
+ qat_req->resrvd2 = 0;
+ qat_req->next_req_adr = 0;
+}
+
+static size_t __rte_unused max_of(int n, ...)
+{
+ va_list args;
+ size_t len = 0, num;
+ int i;
+
+ va_start(args, n);
+ len = va_arg(args, size_t);
+
+ for (i = 0; i < n - 1; i++) {
+ num = va_arg(args, size_t);
+ if (num > len)
+ len = num;
+ }
+ va_end(args);
+
+ return len;
+}
+
+static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
+ int in_count, int out_count, int in_size, int out_size)
+{
+ int i;
+
+ for (i = 0; i < in_count; i++)
+ memset(cookie->input_array[i], 0x0, in_size);
+ for (i = 0; i < out_count; i++)
+ memset(cookie->output_array[i], 0x0, out_size);
+}
+
+static int __rte_unused qat_asym_check_nonzero(rte_crypto_param n)
+{
+ if (n.length < 8) {
+ /* Not a case for any cryptograpic function except for DH
+ * generator which very often can be of one byte length
+ */
+ size_t i;
+
+ if (n.data[n.length - 1] == 0x0) {
+ for (i = 0; i < n.length - 1; i++)
+ if (n.data[i] != 0x0)
+ break;
+ if (i == n.length - 1)
+ return QAT_ASYM_ERROR_INVALID_PARAM;
+ }
+ } else if (*(uint64_t *)&n.data[
+ n.length - 8] == 0) {
+ /* Very likely it is zeroed modulus */
+ size_t i;
+
+ for (i = 0; i < n.length - 8; i++)
+ if (n.data[i] != 0x0)
+ break;
+ if (i == n.length - 8)
+ return QAT_ASYM_ERROR_INVALID_PARAM;
+ }
+
+ return 0;
+}
+
+int
+qat_asym_build_request(void *in_op,
+ uint8_t *out_msg,
+ void *op_cookie,
+ __rte_unused enum qat_device_gen qat_dev_gen)
+{
+ struct qat_asym_session *ctx;
+ struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
+ struct rte_crypto_asym_op __rte_unused *asym_op = op->asym;
+ struct icp_qat_fw_pke_request *qat_req =
+ (struct icp_qat_fw_pke_request *)out_msg;
+ struct qat_asym_op_cookie *cookie =
+ (struct qat_asym_op_cookie *)op_cookie;
+
+ ctx = (struct qat_asym_session *)get_asym_session_private_data(
+ op->asym->session, cryptodev_qat_asym_driver_id);
+ rte_mov64((uint8_t *)qat_req, (const uint8_t *)&(ctx->req_tmpl));
+ qat_req->pke_mid.opaque = (uint64_t)(uintptr_t)op;
+
+ qat_req->pke_mid.src_data_addr = cookie->input_addr;
+ qat_req->pke_mid.dest_data_addr = cookie->output_addr;
+
+ goto error;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
+ sizeof(struct icp_qat_fw_pke_request));
+#endif
+ return 0;
+error:
+ qat_req->output_param_count = 0;
+ qat_req->input_param_count = 0;
+ qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+ cookie->error |= QAT_ASYM_ERROR_INVALID_PARAM;
+
+ return 0;
+}
+
+void
+qat_asym_process_response(void **op, uint8_t *resp,
+ void *op_cookie)
+{
+ struct icp_qat_fw_pke_resp *resp_msg =
+ (struct icp_qat_fw_pke_resp *)resp;
+ struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
+ (resp_msg->opaque);
+ struct qat_asym_op_cookie *cookie = op_cookie;
+
+ *op = rx_op;
+ rx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+
+ if (cookie->error) {
+ cookie->error = 0;
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Cookie status returned error");
+ } else {
+ if (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
+ resp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) {
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Asymmetric response status returned error");
+ }
+ if (resp_msg->pke_resp_hdr.resp_status.comn_err_code) {
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Asymmetric common status returned error");
+ }
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg,
+ sizeof(struct icp_qat_fw_pke_resp));
+#endif
+}
+
+int
+qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool)
+{
+ int err;
+ void *sess_private_data;
+
+ err = -EINVAL;
+ goto error;
+ if (rte_mempool_get(mempool, &sess_private_data)) {
+ QAT_LOG(ERR,
+ "Couldn't get object from session mempool");
+ return -ENOMEM;
+ }
+
+ qat_asym_build_req_tmpl(sess_private_data, xform);
+
+ set_asym_session_private_data(sess, dev->driver_id,
+ sess_private_data);
+
+ return 0;
+error:
+ return err;
+}
+
+unsigned int qat_asym_session_get_private_size(
+ struct rte_cryptodev *dev __rte_unused)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8);
+}
+
+void
+qat_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess)
+{
+ uint8_t index = dev->driver_id;
+ void *sess_priv = get_asym_session_private_data(sess, index);
+ struct qat_asym_session *s = (struct qat_asym_session *)sess_priv;
+
+ if (sess_priv) {
+ memset(s, 0, qat_asym_session_get_private_size(dev));
+ struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
+
+ set_asym_session_private_data(sess, index, NULL);
+ rte_mempool_put(sess_mp, sess_priv);
+ }
+}
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
new file mode 100644
index 0000000..7e5982d
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_ASYM_H_
+#define _QAT_ASYM_H_
+
+#include <rte_cryptodev_pmd.h>
+#include <rte_crypto_asym.h>
+#include "icp_qat_fw_pke.h"
+#include "qat_common.h"
+#include "qat_asym_pmd.h"
+#include "icp_qat_fw.h"
+
+typedef uint64_t large_int_ptr;
+#define MAX_PKE_PARAMS 8
+#define QAT_PKE_MAX_LN_SIZE 512
+#define _PKE_ALIGN_ __attribute__((__aligned__(8)))
+
+#define QAT_ASYM_ERROR_INVALID_PARAM 0x01
+
+struct qat_asym_op_cookie {
+ size_t alg_size;
+ uint64_t error;
+ rte_iova_t input_addr;
+ rte_iova_t output_addr;
+ large_int_ptr input_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;
+ large_int_ptr output_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;
+ union {
+ uint8_t input_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE];
+ uint8_t input_buffer[MAX_PKE_PARAMS * QAT_PKE_MAX_LN_SIZE];
+ } _PKE_ALIGN_;
+ uint8_t output_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE] _PKE_ALIGN_;
+} _PKE_ALIGN_;
+
+enum qat_asym_alg {
+ QAT_PKE_RSA,
+ QAT_PKE_DH,
+ QAT_PKE_DSA,
+ QAT_PKE_MODEXP,
+ QAT_PKE_MODINV,
+};
+
+struct qat_asym_session {
+ enum qat_asym_alg alg;
+ struct icp_qat_fw_pke_request req_tmpl;
+ uint64_t flags;
+};
+
+int
+qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool);
+
+unsigned int
+qat_asym_session_get_private_size(struct rte_cryptodev *dev);
+
+void
+qat_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess);
+
+/*
+ * Build PKE request to be sent to the fw, partially uses template
+ * request generated during session creation.
+ *
+ * @param in_op Pointer to the crypto operation, for every
+ * service it points to service specific struct.
+ * @param out_msg Message to be returned to enqueue function
+ * @param op_cookie Cookie pointer that holds private metadata
+ * @param qat_dev_gen Generation of QAT hardware
+ *
+ * @return
+ * This function always returns zero,
+ * it is because of backward compatibility.
+ * - 0: Always returned
+ *
+ */
+int
+qat_asym_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie, enum qat_device_gen qat_dev_gen);
+
+/*
+ * Process PKE response received from outgoing queue of QAT
+ *
+ * @param op a ptr to the rte_crypto_op referred to by
+ * the response message is returned in this param
+ * @param resp icp_qat_fw_pke_resp message received from
+ * outgoing fw message queue
+ * @param op_cookie Cookie pointer that holds private metadata
+ *
+ */
+void
+qat_asym_process_response(void __rte_unused **op, uint8_t *resp,
+ void *op_cookie);
+
+#endif /* _QAT_ASYM_H_ */
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
new file mode 100644
index 0000000..b50e061
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_ASYM_CAPABILITIES_H_
+#define _QAT_ASYM_CAPABILITIES_H_
+
+#define QAT_BASE_GEN1_ASYM_CAPABILITIES
+
+#endif /* _QAT_ASYM_CAPABILITIES_H_ */
diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c
new file mode 100644
index 0000000..254bc48
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <rte_cryptodev_pmd.h>
+
+#include "qat_logs.h"
+
+#include "qat_asym.h"
+#include "qat_asym_pmd.h"
+#include "qat_sym_capabilities.h"
+#include "qat_asym_capabilities.h"
+
+uint8_t cryptodev_qat_asym_driver_id;
+
+static const struct rte_cryptodev_capabilities qat_gen1_asym_capabilities[] = {
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+static int qat_asym_qp_release(struct rte_cryptodev *dev,
+ uint16_t queue_pair_id);
+
+static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused struct rte_cryptodev_config *config)
+{
+ return 0;
+}
+
+static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)
+{
+ return 0;
+}
+
+static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)
+{
+
+}
+
+static int qat_asym_dev_close(struct rte_cryptodev *dev)
+{
+ int i, ret;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_asym_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void qat_asym_dev_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *info)
+{
+ struct qat_asym_dev_private *internals = dev->data->dev_private;
+ const struct qat_qp_hw_data *asym_hw_qps =
+ qat_gen_config[internals->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_ASYMMETRIC];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs = qat_qps_per_service(asym_hw_qps,
+ QAT_SERVICE_ASYMMETRIC);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = internals->qat_dev_capabilities;
+ info->driver_id = cryptodev_qat_asym_driver_id;
+ /* No limit of number of sessions */
+ info->sym.max_nb_sessions = 0;
+ }
+}
+
+static void qat_asym_stats_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_asym_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_ASYMMETRIC);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+static void qat_asym_stats_reset(struct rte_cryptodev *dev)
+{
+ struct qat_asym_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid asymmetric cryptodev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_ASYMMETRIC);
+}
+
+static int qat_asym_qp_release(struct rte_cryptodev *dev,
+ uint16_t queue_pair_id)
+{
+ struct qat_asym_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release asym qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+static int qat_asym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *qp_conf,
+ int socket_id)
+{
+ struct qat_qp_config qat_qp_conf;
+ struct qat_qp *qp;
+ int ret = 0;
+ uint32_t i;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_asym_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *asym_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_ASYMMETRIC];
+ const struct qat_qp_hw_data *qp_hw_data = asym_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_asym_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(asym_hw_qps, QAT_SERVICE_ASYMMETRIC)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_asym_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_asym_op_cookie);
+ qat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "asym";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][qp_id]
+ = *qp_addr;
+
+ qp = (struct qat_qp *)*qp_addr;
+
+ for (i = 0; i < qp->nb_descriptors; i++) {
+ int j;
+
+ struct qat_asym_op_cookie __rte_unused *cookie =
+ qp->op_cookies[i];
+ cookie->input_addr = rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ input_params_ptrs);
+
+ cookie->output_addr = rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ output_params_ptrs);
+
+ for (j = 0; j < 8; j++) {
+ cookie->input_params_ptrs[j] =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ input_array[j]);
+ cookie->output_params_ptrs[j] =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ output_array[j]);
+ }
+ }
+
+ return ret;
+}
+
+struct rte_cryptodev_ops crypto_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_asym_dev_config,
+ .dev_start = qat_asym_dev_start,
+ .dev_stop = qat_asym_dev_stop,
+ .dev_close = qat_asym_dev_close,
+ .dev_infos_get = qat_asym_dev_info_get,
+
+ .stats_get = qat_asym_stats_get,
+ .stats_reset = qat_asym_stats_reset,
+ .queue_pair_setup = qat_asym_qp_setup,
+ .queue_pair_release = qat_asym_qp_release,
+ .queue_pair_count = NULL,
+
+ /* Crypto related operations */
+ .asym_session_get_size = qat_asym_session_get_private_size,
+ .asym_session_configure = qat_asym_session_configure,
+ .asym_session_clear = qat_asym_session_clear
+};
+
+uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+/* An rte_driver is needed in the registration of both the device and the driver
+ * with cryptodev.
+ * The actual qat pci's rte_driver can't be used as its name represents
+ * the whole pci device with all services. Think of this as a holder for a name
+ * for the crypto part of the pci device.
+ */
+static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);
+static const struct rte_driver cryptodev_qat_asym_driver = {
+ .name = qat_asym_drv_name,
+ .alias = qat_asym_drv_name
+};
+
+int
+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ struct rte_cryptodev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ .private_data_size = sizeof(struct qat_asym_dev_private)
+ };
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *cryptodev;
+ struct qat_asym_dev_private *internals;
+
+ snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "asym");
+ QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name);
+
+ /* Populate subset device to use in cryptodev device creation */
+ qat_pci_dev->asym_rte_dev.driver = &cryptodev_qat_asym_driver;
+ qat_pci_dev->asym_rte_dev.numa_node =
+ qat_pci_dev->pci_dev->device.numa_node;
+ qat_pci_dev->asym_rte_dev.devargs = NULL;
+
+ cryptodev = rte_cryptodev_pmd_create(name,
+ &(qat_pci_dev->asym_rte_dev), &init_params);
+
+ if (cryptodev == NULL)
+ return -ENODEV;
+
+ qat_pci_dev->asym_rte_dev.name = cryptodev->data->name;
+ cryptodev->driver_id = cryptodev_qat_asym_driver_id;
+ cryptodev->dev_ops = &crypto_qat_ops;
+
+ cryptodev->enqueue_burst = qat_asym_pmd_enqueue_op_burst;
+ cryptodev->dequeue_burst = qat_asym_pmd_dequeue_op_burst;
+
+ cryptodev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_HW_ACCELERATED;
+ internals = cryptodev->data->dev_private;
+ internals->qat_dev = qat_pci_dev;
+ qat_pci_dev->asym_dev = internals;
+
+ internals->asym_dev_id = cryptodev->data->dev_id;
+ internals->qat_dev_capabilities = qat_gen1_asym_capabilities;
+
+ QAT_LOG(DEBUG, "Created QAT ASYM device %s as cryptodev instance %d",
+ cryptodev->data->name, internals->asym_dev_id);
+ return 0;
+}
+
+int
+qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct rte_cryptodev *cryptodev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+ if (qat_pci_dev->asym_dev == NULL)
+ return 0;
+
+ /* free crypto device */
+ cryptodev = rte_cryptodev_pmd_get_dev(
+ qat_pci_dev->asym_dev->asym_dev_id);
+ rte_cryptodev_pmd_destroy(cryptodev);
+ qat_pci_dev->asym_rte_dev.name = NULL;
+ qat_pci_dev->asym_dev = NULL;
+
+ return 0;
+}
+
+static struct cryptodev_driver qat_crypto_drv;
+RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,
+ cryptodev_qat_asym_driver,
+ cryptodev_qat_asym_driver_id);
diff --git a/drivers/crypto/qat/qat_asym_pmd.h b/drivers/crypto/qat/qat_asym_pmd.h
new file mode 100644
index 0000000..895d0f6
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_pmd.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+
+#ifndef _QAT_ASYM_PMD_H_
+#define _QAT_ASYM_PMD_H_
+
+#include <rte_cryptodev.h>
+#include "qat_device.h"
+
+/** Intel(R) QAT Asymmetric Crypto PMD driver name */
+#define CRYPTODEV_NAME_QAT_ASYM_PMD crypto_qat_asym
+
+
+extern uint8_t cryptodev_qat_asym_driver_id;
+
+/** private data structure for a QAT device.
+ * This QAT device is a device offering only asymmetric crypto service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_asym_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ uint8_t asym_dev_id;
+ /**< Device instance for this rte_cryptodev */
+ const struct rte_cryptodev_capabilities *qat_dev_capabilities;
+ /* QAT device asymmetric crypto capabilities */
+};
+
+uint16_t
+qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops);
+
+int qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool);
+
+int
+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev);
+
+int
+qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev);
+
+#endif /* _QAT_ASYM_PMD_H_ */
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 31ccab3..af21270 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -325,7 +325,6 @@ qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev)
return 0;
}
-
static struct cryptodev_driver qat_crypto_drv;
RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,
cryptodev_qat_sym_driver,
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index 5563d5b..7ddaf45 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -19,8 +19,7 @@ extern uint8_t cryptodev_qat_driver_id;
/** private data structure for a QAT device.
* This QAT device is a device offering only symmetric crypto service,
- * there can be one of these on each qat_pci_device (VF),
- * in future there may also be private data structures for other services.
+ * there can be one of these on each qat_pci_device (VF).
*/
struct qat_sym_dev_private {
struct qat_pci_device *qat_dev;
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 262132f..e13f247 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -233,6 +233,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_SYM) += -lrte_pmd_qat -lcrypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM) += -lrte_pmd_qat -lcrypto
endif # CONFIG_RTE_LIBRTE_PMD_QAT
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -lrte_pmd_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -L$(LIBSSO_SNOW3G_PATH)/build -lsso_snow3g
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
2019-04-03 8:42 ` Akhil Goyal
1 sibling, 0 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This patch adds Poll Mode Driver for asymmetric crypto
functions of Intel QuickAssist Technology hardware.
It contains plain driver with no functions implmented, specific
algorithms will be introduced in separate patches.
This patch depends on a QAT PF driver for device initialization. See
the file docs/guides/cryptodevs/qat.rst for configuration details.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
config/common_base | 1 +
doc/guides/cryptodevs/qat.rst | 7 +
drivers/common/qat/Makefile | 8 +
drivers/common/qat/qat_device.h | 12 +-
drivers/common/qat/qat_qp.c | 8 +
drivers/crypto/qat/meson.build | 5 +-
drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
drivers/crypto/qat/qat_asym.h | 97 +++++++++
drivers/crypto/qat/qat_asym_capabilities.h | 10 +
drivers/crypto/qat/qat_asym_pmd.c | 308 +++++++++++++++++++++++++++++
drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
drivers/crypto/qat/qat_sym_pmd.c | 1 -
drivers/crypto/qat/qat_sym_pmd.h | 3 +-
mk/rte.app.mk | 1 +
14 files changed, 742 insertions(+), 5 deletions(-)
create mode 100644 drivers/crypto/qat/qat_asym.c
create mode 100644 drivers/crypto/qat/qat_asym.h
create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
diff --git a/config/common_base b/config/common_base
index 0b09a93..d1dd66a 100644
--- a/config/common_base
+++ b/config/common_base
@@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
+CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index da9655c..53a8d61 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -101,7 +101,13 @@ of all the items described above, including the padding at the end.
Also, offset of data to authenticate "op.sym.auth.data.offset"
must be such that points at the start of the COUNT bytes.
+Asymmetric Crypto Service on QAT
+-------------------------------
+
+The QAT Asym PMD has support for:
+Limitations
+~~~~~~~~~~~
.. _building_qat:
@@ -112,6 +118,7 @@ A QAT device can host multiple acceleration services:
* symmetric cryptography
* data compression
+* asymmetric cryptography
These services are provided to DPDK applications via PMDs which register to
implement the corresponding cryptodev and compressdev APIs. The PMDs use
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index c68a032..792058d 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -25,6 +25,14 @@ endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM),y)
+ LDLIBS += -lrte_cryptodev
+ LDLIBS += -lcrypto
+ CFLAGS += -DBUILD_QAT_ASYM
+ SRCS-y += qat_asym.c
+ SRCS-y += qat_asym_pmd.c
+ build_qat = yes
+endif
ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index eb81c78..131375e 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -31,6 +31,7 @@ enum qat_comp_num_im_buffers {
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_asym_dev_private;
struct qat_comp_dev_private;
struct qat_pci_device {
@@ -57,7 +58,16 @@ struct qat_pci_device {
struct qat_sym_dev_private *sym_dev;
/**< link back to cryptodev private data */
struct rte_device sym_rte_dev;
- /**< This represents the crypto subset of this pci device.
+ /**< This represents the crypto sym subset of this pci device.
+ * Register with this rather than with the one in
+ * pci_dev so that its driver can have a crypto-specific name
+ */
+
+ /* Data relating to asymmetric crypto service */
+ struct qat_asym_dev_private *asym_dev;
+ /**< link back to cryptodev private data */
+ struct rte_device asym_rte_dev;
+ /**< This represents the crypto asym subset of this pci device.
* Register with this rather than with the one in
* pci_dev so that its driver can have a crypto-specific name
*/
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 4e66c58..febc2ef 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_asym.h"
#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -273,6 +274,7 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,
QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
goto create_err;
}
+ memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
}
qp->qat_dev_gen = qat_dev->qat_dev_gen;
@@ -648,6 +650,12 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
qat_comp_process_response(ops, resp_msg,
&tmp_qp->stats.dequeue_err_count);
+ else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
+#ifdef BUILD_QAT_ASYM
+ qat_asym_process_response(ops, resp_msg,
+ tmp_qp->op_cookies[head / rx_queue->msg_size]);
+#endif
+ }
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 21f9697..710b081 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -11,7 +11,10 @@ if dep.found()
# Add our sources files to the list
qat_sources += files('qat_sym_pmd.c',
'qat_sym.c',
- 'qat_sym_session.c')
+ 'qat_sym_session.c',
+ 'qat_asym_pmd.c',
+ 'qat_asym.c')
qat_ext_deps += dep
qat_cflags += '-DBUILD_QAT_SYM'
+ qat_cflags += '-DBUILD_QAT_ASYM'
endif
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
new file mode 100644
index 0000000..708bafa
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym.c
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <stdarg.h>
+
+#include "qat_asym.h"
+#include "icp_qat_fw_pke.h"
+#include "icp_qat_fw.h"
+#include "qat_pke_functionality_arrays.h"
+
+#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
+
+static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
+ size_t arr_sz, size_t *size, uint32_t *func_id)
+{
+ size_t i;
+
+ for (i = 0; i < arr_sz; i++) {
+ if (*size <= arr[i][0]) {
+ *size = arr[i][0];
+ *func_id = arr[i][1];
+ return 0;
+ }
+ }
+ return -1;
+}
+
+static void qat_asym_build_req_tmpl(void *sess_private_data,
+ struct rte_crypto_asym_xform __rte_unused *xform)
+{
+
+ struct icp_qat_fw_pke_request *qat_req;
+ struct qat_asym_session *session = sess_private_data;
+
+ qat_req = &session->req_tmpl;
+ memset(qat_req, 0, sizeof(*qat_req));
+ qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
+
+ qat_req->pke_hdr.hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD
+ (ICP_QAT_FW_COMN_REQ_FLAG_SET);
+ qat_req->pke_hdr.comn_req_flags = 0;
+ qat_req->pke_hdr.resrvd1 = 0;
+ qat_req->pke_hdr.resrvd2 = 0;
+ qat_req->pke_hdr.kpt_mask = 0;
+ qat_req->pke_hdr.kpt_rn_mask = 0;
+ qat_req->pke_hdr.cd_pars.content_desc_addr = 0;
+ qat_req->pke_hdr.cd_pars.content_desc_resrvd = 0;
+ qat_req->resrvd1 = 0;
+ qat_req->resrvd2 = 0;
+ qat_req->next_req_adr = 0;
+}
+
+static size_t __rte_unused max_of(int n, ...)
+{
+ va_list args;
+ size_t len = 0, num;
+ int i;
+
+ va_start(args, n);
+ len = va_arg(args, size_t);
+
+ for (i = 0; i < n - 1; i++) {
+ num = va_arg(args, size_t);
+ if (num > len)
+ len = num;
+ }
+ va_end(args);
+
+ return len;
+}
+
+static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
+ int in_count, int out_count, int in_size, int out_size)
+{
+ int i;
+
+ for (i = 0; i < in_count; i++)
+ memset(cookie->input_array[i], 0x0, in_size);
+ for (i = 0; i < out_count; i++)
+ memset(cookie->output_array[i], 0x0, out_size);
+}
+
+static int __rte_unused qat_asym_check_nonzero(rte_crypto_param n)
+{
+ if (n.length < 8) {
+ /* Not a case for any cryptograpic function except for DH
+ * generator which very often can be of one byte length
+ */
+ size_t i;
+
+ if (n.data[n.length - 1] == 0x0) {
+ for (i = 0; i < n.length - 1; i++)
+ if (n.data[i] != 0x0)
+ break;
+ if (i == n.length - 1)
+ return QAT_ASYM_ERROR_INVALID_PARAM;
+ }
+ } else if (*(uint64_t *)&n.data[
+ n.length - 8] == 0) {
+ /* Very likely it is zeroed modulus */
+ size_t i;
+
+ for (i = 0; i < n.length - 8; i++)
+ if (n.data[i] != 0x0)
+ break;
+ if (i == n.length - 8)
+ return QAT_ASYM_ERROR_INVALID_PARAM;
+ }
+
+ return 0;
+}
+
+int
+qat_asym_build_request(void *in_op,
+ uint8_t *out_msg,
+ void *op_cookie,
+ __rte_unused enum qat_device_gen qat_dev_gen)
+{
+ struct qat_asym_session *ctx;
+ struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
+ struct rte_crypto_asym_op __rte_unused *asym_op = op->asym;
+ struct icp_qat_fw_pke_request *qat_req =
+ (struct icp_qat_fw_pke_request *)out_msg;
+ struct qat_asym_op_cookie *cookie =
+ (struct qat_asym_op_cookie *)op_cookie;
+
+ ctx = (struct qat_asym_session *)get_asym_session_private_data(
+ op->asym->session, cryptodev_qat_asym_driver_id);
+ rte_mov64((uint8_t *)qat_req, (const uint8_t *)&(ctx->req_tmpl));
+ qat_req->pke_mid.opaque = (uint64_t)(uintptr_t)op;
+
+ qat_req->pke_mid.src_data_addr = cookie->input_addr;
+ qat_req->pke_mid.dest_data_addr = cookie->output_addr;
+
+ goto error;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
+ sizeof(struct icp_qat_fw_pke_request));
+#endif
+ return 0;
+error:
+ qat_req->output_param_count = 0;
+ qat_req->input_param_count = 0;
+ qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+ cookie->error |= QAT_ASYM_ERROR_INVALID_PARAM;
+
+ return 0;
+}
+
+void
+qat_asym_process_response(void **op, uint8_t *resp,
+ void *op_cookie)
+{
+ struct icp_qat_fw_pke_resp *resp_msg =
+ (struct icp_qat_fw_pke_resp *)resp;
+ struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
+ (resp_msg->opaque);
+ struct qat_asym_op_cookie *cookie = op_cookie;
+
+ *op = rx_op;
+ rx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
+
+ if (cookie->error) {
+ cookie->error = 0;
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Cookie status returned error");
+ } else {
+ if (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
+ resp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) {
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Asymmetric response status returned error");
+ }
+ if (resp_msg->pke_resp_hdr.resp_status.comn_err_code) {
+ rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+ QAT_DP_LOG(ERR, "Asymmetric common status returned error");
+ }
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg,
+ sizeof(struct icp_qat_fw_pke_resp));
+#endif
+}
+
+int
+qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool)
+{
+ int err;
+ void *sess_private_data;
+
+ err = -EINVAL;
+ goto error;
+ if (rte_mempool_get(mempool, &sess_private_data)) {
+ QAT_LOG(ERR,
+ "Couldn't get object from session mempool");
+ return -ENOMEM;
+ }
+
+ qat_asym_build_req_tmpl(sess_private_data, xform);
+
+ set_asym_session_private_data(sess, dev->driver_id,
+ sess_private_data);
+
+ return 0;
+error:
+ return err;
+}
+
+unsigned int qat_asym_session_get_private_size(
+ struct rte_cryptodev *dev __rte_unused)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8);
+}
+
+void
+qat_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess)
+{
+ uint8_t index = dev->driver_id;
+ void *sess_priv = get_asym_session_private_data(sess, index);
+ struct qat_asym_session *s = (struct qat_asym_session *)sess_priv;
+
+ if (sess_priv) {
+ memset(s, 0, qat_asym_session_get_private_size(dev));
+ struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
+
+ set_asym_session_private_data(sess, index, NULL);
+ rte_mempool_put(sess_mp, sess_priv);
+ }
+}
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
new file mode 100644
index 0000000..7e5982d
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_ASYM_H_
+#define _QAT_ASYM_H_
+
+#include <rte_cryptodev_pmd.h>
+#include <rte_crypto_asym.h>
+#include "icp_qat_fw_pke.h"
+#include "qat_common.h"
+#include "qat_asym_pmd.h"
+#include "icp_qat_fw.h"
+
+typedef uint64_t large_int_ptr;
+#define MAX_PKE_PARAMS 8
+#define QAT_PKE_MAX_LN_SIZE 512
+#define _PKE_ALIGN_ __attribute__((__aligned__(8)))
+
+#define QAT_ASYM_ERROR_INVALID_PARAM 0x01
+
+struct qat_asym_op_cookie {
+ size_t alg_size;
+ uint64_t error;
+ rte_iova_t input_addr;
+ rte_iova_t output_addr;
+ large_int_ptr input_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;
+ large_int_ptr output_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;
+ union {
+ uint8_t input_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE];
+ uint8_t input_buffer[MAX_PKE_PARAMS * QAT_PKE_MAX_LN_SIZE];
+ } _PKE_ALIGN_;
+ uint8_t output_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE] _PKE_ALIGN_;
+} _PKE_ALIGN_;
+
+enum qat_asym_alg {
+ QAT_PKE_RSA,
+ QAT_PKE_DH,
+ QAT_PKE_DSA,
+ QAT_PKE_MODEXP,
+ QAT_PKE_MODINV,
+};
+
+struct qat_asym_session {
+ enum qat_asym_alg alg;
+ struct icp_qat_fw_pke_request req_tmpl;
+ uint64_t flags;
+};
+
+int
+qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool);
+
+unsigned int
+qat_asym_session_get_private_size(struct rte_cryptodev *dev);
+
+void
+qat_asym_session_clear(struct rte_cryptodev *dev,
+ struct rte_cryptodev_asym_session *sess);
+
+/*
+ * Build PKE request to be sent to the fw, partially uses template
+ * request generated during session creation.
+ *
+ * @param in_op Pointer to the crypto operation, for every
+ * service it points to service specific struct.
+ * @param out_msg Message to be returned to enqueue function
+ * @param op_cookie Cookie pointer that holds private metadata
+ * @param qat_dev_gen Generation of QAT hardware
+ *
+ * @return
+ * This function always returns zero,
+ * it is because of backward compatibility.
+ * - 0: Always returned
+ *
+ */
+int
+qat_asym_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie, enum qat_device_gen qat_dev_gen);
+
+/*
+ * Process PKE response received from outgoing queue of QAT
+ *
+ * @param op a ptr to the rte_crypto_op referred to by
+ * the response message is returned in this param
+ * @param resp icp_qat_fw_pke_resp message received from
+ * outgoing fw message queue
+ * @param op_cookie Cookie pointer that holds private metadata
+ *
+ */
+void
+qat_asym_process_response(void __rte_unused **op, uint8_t *resp,
+ void *op_cookie);
+
+#endif /* _QAT_ASYM_H_ */
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
new file mode 100644
index 0000000..b50e061
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_ASYM_CAPABILITIES_H_
+#define _QAT_ASYM_CAPABILITIES_H_
+
+#define QAT_BASE_GEN1_ASYM_CAPABILITIES
+
+#endif /* _QAT_ASYM_CAPABILITIES_H_ */
diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c
new file mode 100644
index 0000000..254bc48
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#include <rte_cryptodev_pmd.h>
+
+#include "qat_logs.h"
+
+#include "qat_asym.h"
+#include "qat_asym_pmd.h"
+#include "qat_sym_capabilities.h"
+#include "qat_asym_capabilities.h"
+
+uint8_t cryptodev_qat_asym_driver_id;
+
+static const struct rte_cryptodev_capabilities qat_gen1_asym_capabilities[] = {
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+static int qat_asym_qp_release(struct rte_cryptodev *dev,
+ uint16_t queue_pair_id);
+
+static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused struct rte_cryptodev_config *config)
+{
+ return 0;
+}
+
+static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)
+{
+ return 0;
+}
+
+static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)
+{
+
+}
+
+static int qat_asym_dev_close(struct rte_cryptodev *dev)
+{
+ int i, ret;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_asym_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void qat_asym_dev_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *info)
+{
+ struct qat_asym_dev_private *internals = dev->data->dev_private;
+ const struct qat_qp_hw_data *asym_hw_qps =
+ qat_gen_config[internals->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_ASYMMETRIC];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs = qat_qps_per_service(asym_hw_qps,
+ QAT_SERVICE_ASYMMETRIC);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = internals->qat_dev_capabilities;
+ info->driver_id = cryptodev_qat_asym_driver_id;
+ /* No limit of number of sessions */
+ info->sym.max_nb_sessions = 0;
+ }
+}
+
+static void qat_asym_stats_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_asym_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_ASYMMETRIC);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+static void qat_asym_stats_reset(struct rte_cryptodev *dev)
+{
+ struct qat_asym_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid asymmetric cryptodev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_ASYMMETRIC);
+}
+
+static int qat_asym_qp_release(struct rte_cryptodev *dev,
+ uint16_t queue_pair_id)
+{
+ struct qat_asym_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release asym qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+static int qat_asym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ const struct rte_cryptodev_qp_conf *qp_conf,
+ int socket_id)
+{
+ struct qat_qp_config qat_qp_conf;
+ struct qat_qp *qp;
+ int ret = 0;
+ uint32_t i;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_asym_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *asym_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_ASYMMETRIC];
+ const struct qat_qp_hw_data *qp_hw_data = asym_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_asym_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(asym_hw_qps, QAT_SERVICE_ASYMMETRIC)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_asym_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_asym_op_cookie);
+ qat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "asym";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_ASYMMETRIC][qp_id]
+ = *qp_addr;
+
+ qp = (struct qat_qp *)*qp_addr;
+
+ for (i = 0; i < qp->nb_descriptors; i++) {
+ int j;
+
+ struct qat_asym_op_cookie __rte_unused *cookie =
+ qp->op_cookies[i];
+ cookie->input_addr = rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ input_params_ptrs);
+
+ cookie->output_addr = rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ output_params_ptrs);
+
+ for (j = 0; j < 8; j++) {
+ cookie->input_params_ptrs[j] =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ input_array[j]);
+ cookie->output_params_ptrs[j] =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_asym_op_cookie,
+ output_array[j]);
+ }
+ }
+
+ return ret;
+}
+
+struct rte_cryptodev_ops crypto_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_asym_dev_config,
+ .dev_start = qat_asym_dev_start,
+ .dev_stop = qat_asym_dev_stop,
+ .dev_close = qat_asym_dev_close,
+ .dev_infos_get = qat_asym_dev_info_get,
+
+ .stats_get = qat_asym_stats_get,
+ .stats_reset = qat_asym_stats_reset,
+ .queue_pair_setup = qat_asym_qp_setup,
+ .queue_pair_release = qat_asym_qp_release,
+ .queue_pair_count = NULL,
+
+ /* Crypto related operations */
+ .asym_session_get_size = qat_asym_session_get_private_size,
+ .asym_session_configure = qat_asym_session_configure,
+ .asym_session_clear = qat_asym_session_clear
+};
+
+uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+/* An rte_driver is needed in the registration of both the device and the driver
+ * with cryptodev.
+ * The actual qat pci's rte_driver can't be used as its name represents
+ * the whole pci device with all services. Think of this as a holder for a name
+ * for the crypto part of the pci device.
+ */
+static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);
+static const struct rte_driver cryptodev_qat_asym_driver = {
+ .name = qat_asym_drv_name,
+ .alias = qat_asym_drv_name
+};
+
+int
+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ struct rte_cryptodev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ .private_data_size = sizeof(struct qat_asym_dev_private)
+ };
+ char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct rte_cryptodev *cryptodev;
+ struct qat_asym_dev_private *internals;
+
+ snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "asym");
+ QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name);
+
+ /* Populate subset device to use in cryptodev device creation */
+ qat_pci_dev->asym_rte_dev.driver = &cryptodev_qat_asym_driver;
+ qat_pci_dev->asym_rte_dev.numa_node =
+ qat_pci_dev->pci_dev->device.numa_node;
+ qat_pci_dev->asym_rte_dev.devargs = NULL;
+
+ cryptodev = rte_cryptodev_pmd_create(name,
+ &(qat_pci_dev->asym_rte_dev), &init_params);
+
+ if (cryptodev == NULL)
+ return -ENODEV;
+
+ qat_pci_dev->asym_rte_dev.name = cryptodev->data->name;
+ cryptodev->driver_id = cryptodev_qat_asym_driver_id;
+ cryptodev->dev_ops = &crypto_qat_ops;
+
+ cryptodev->enqueue_burst = qat_asym_pmd_enqueue_op_burst;
+ cryptodev->dequeue_burst = qat_asym_pmd_dequeue_op_burst;
+
+ cryptodev->feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+ RTE_CRYPTODEV_FF_HW_ACCELERATED;
+ internals = cryptodev->data->dev_private;
+ internals->qat_dev = qat_pci_dev;
+ qat_pci_dev->asym_dev = internals;
+
+ internals->asym_dev_id = cryptodev->data->dev_id;
+ internals->qat_dev_capabilities = qat_gen1_asym_capabilities;
+
+ QAT_LOG(DEBUG, "Created QAT ASYM device %s as cryptodev instance %d",
+ cryptodev->data->name, internals->asym_dev_id);
+ return 0;
+}
+
+int
+qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct rte_cryptodev *cryptodev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+ if (qat_pci_dev->asym_dev == NULL)
+ return 0;
+
+ /* free crypto device */
+ cryptodev = rte_cryptodev_pmd_get_dev(
+ qat_pci_dev->asym_dev->asym_dev_id);
+ rte_cryptodev_pmd_destroy(cryptodev);
+ qat_pci_dev->asym_rte_dev.name = NULL;
+ qat_pci_dev->asym_dev = NULL;
+
+ return 0;
+}
+
+static struct cryptodev_driver qat_crypto_drv;
+RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,
+ cryptodev_qat_asym_driver,
+ cryptodev_qat_asym_driver_id);
diff --git a/drivers/crypto/qat/qat_asym_pmd.h b/drivers/crypto/qat/qat_asym_pmd.h
new file mode 100644
index 0000000..895d0f6
--- /dev/null
+++ b/drivers/crypto/qat/qat_asym_pmd.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+
+#ifndef _QAT_ASYM_PMD_H_
+#define _QAT_ASYM_PMD_H_
+
+#include <rte_cryptodev.h>
+#include "qat_device.h"
+
+/** Intel(R) QAT Asymmetric Crypto PMD driver name */
+#define CRYPTODEV_NAME_QAT_ASYM_PMD crypto_qat_asym
+
+
+extern uint8_t cryptodev_qat_asym_driver_id;
+
+/** private data structure for a QAT device.
+ * This QAT device is a device offering only asymmetric crypto service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_asym_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ uint8_t asym_dev_id;
+ /**< Device instance for this rte_cryptodev */
+ const struct rte_cryptodev_capabilities *qat_dev_capabilities;
+ /* QAT device asymmetric crypto capabilities */
+};
+
+uint16_t
+qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+ uint16_t nb_ops);
+
+int qat_asym_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_asym_xform *xform,
+ struct rte_cryptodev_asym_session *sess,
+ struct rte_mempool *mempool);
+
+int
+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev);
+
+int
+qat_asym_dev_destroy(struct qat_pci_device *qat_pci_dev);
+
+#endif /* _QAT_ASYM_PMD_H_ */
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 31ccab3..af21270 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -325,7 +325,6 @@ qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev)
return 0;
}
-
static struct cryptodev_driver qat_crypto_drv;
RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,
cryptodev_qat_sym_driver,
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index 5563d5b..7ddaf45 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -19,8 +19,7 @@ extern uint8_t cryptodev_qat_driver_id;
/** private data structure for a QAT device.
* This QAT device is a device offering only symmetric crypto service,
- * there can be one of these on each qat_pci_device (VF),
- * in future there may also be private data structures for other services.
+ * there can be one of these on each qat_pci_device (VF).
*/
struct qat_sym_dev_private {
struct qat_pci_device *qat_dev;
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 262132f..e13f247 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -233,6 +233,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_SYM) += -lrte_pmd_qat -lcrypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM) += -lrte_pmd_qat -lcrypto
endif # CONFIG_RTE_LIBRTE_PMD_QAT
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -lrte_pmd_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -L$(LIBSSO_SNOW3G_PATH)/build -lsso_snow3g
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD Arek Kusztal
2019-03-28 13:37 ` Arek Kusztal
@ 2019-04-03 8:42 ` Akhil Goyal
2019-04-03 8:42 ` Akhil Goyal
2019-04-03 9:05 ` Kusztal, ArkadiuszX
1 sibling, 2 replies; 18+ messages in thread
From: Akhil Goyal @ 2019-04-03 8:42 UTC (permalink / raw)
To: Arek Kusztal, dev; +Cc: fiona.trahe
Hi Arek,
On 3/28/2019 7:07 PM, Arek Kusztal wrote:
> This patch adds Poll Mode Driver for asymmetric crypto
> functions of Intel QuickAssist Technology hardware.
>
> It contains plain driver with no functions implmented, specific
> algorithms will be introduced in separate patches.
>
> This patch depends on a QAT PF driver for device initialization. See
> the file docs/guides/cryptodevs/qat.rst for configuration details.
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> ---
> config/common_base | 1 +
> doc/guides/cryptodevs/qat.rst | 7 +
> drivers/common/qat/Makefile | 8 +
> drivers/common/qat/qat_device.h | 12 +-
> drivers/common/qat/qat_qp.c | 8 +
> drivers/crypto/qat/meson.build | 5 +-
> drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
> drivers/crypto/qat/qat_asym.h | 97 +++++++++
> drivers/crypto/qat/qat_asym_capabilities.h | 10 +
> drivers/crypto/qat/qat_asym_pmd.c | 308 +++++++++++++++++++++++++++++
> drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
> drivers/crypto/qat/qat_sym_pmd.c | 1 -
> drivers/crypto/qat/qat_sym_pmd.h | 3 +-
> mk/rte.app.mk | 1 +
> 14 files changed, 742 insertions(+), 5 deletions(-)
> create mode 100644 drivers/crypto/qat/qat_asym.c
> create mode 100644 drivers/crypto/qat/qat_asym.h
> create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
> create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
> create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
>
> diff --git a/config/common_base b/config/common_base
> index 0b09a93..d1dd66a 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
> #
> CONFIG_RTE_LIBRTE_PMD_QAT=y
> CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
> +CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
> #
> # Max. number of QuickAssist devices, which can be detected and attached
> #
> diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
> index da9655c..53a8d61 100644
> --- a/doc/guides/cryptodevs/qat.rst
> +++ b/doc/guides/cryptodevs/qat.rst
> @@ -101,7 +101,13 @@ of all the items described above, including the padding at the end.
> Also, offset of data to authenticate "op.sym.auth.data.offset"
> must be such that points at the start of the COUNT bytes.
>
> +Asymmetric Crypto Service on QAT
> +-------------------------------
doc/guides/cryptodevs/qat.rst:105: WARNING: Title underline too short.
here one '-' is less. I corrected this while applying the patch.
> +
> +The QAT Asym PMD has support for:
>
> +Limitations
> +~~~~~~~~~~~
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-04-03 8:42 ` Akhil Goyal
@ 2019-04-03 8:42 ` Akhil Goyal
2019-04-03 9:05 ` Kusztal, ArkadiuszX
1 sibling, 0 replies; 18+ messages in thread
From: Akhil Goyal @ 2019-04-03 8:42 UTC (permalink / raw)
To: Arek Kusztal, dev; +Cc: fiona.trahe
Hi Arek,
On 3/28/2019 7:07 PM, Arek Kusztal wrote:
> This patch adds Poll Mode Driver for asymmetric crypto
> functions of Intel QuickAssist Technology hardware.
>
> It contains plain driver with no functions implmented, specific
> algorithms will be introduced in separate patches.
>
> This patch depends on a QAT PF driver for device initialization. See
> the file docs/guides/cryptodevs/qat.rst for configuration details.
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> ---
> config/common_base | 1 +
> doc/guides/cryptodevs/qat.rst | 7 +
> drivers/common/qat/Makefile | 8 +
> drivers/common/qat/qat_device.h | 12 +-
> drivers/common/qat/qat_qp.c | 8 +
> drivers/crypto/qat/meson.build | 5 +-
> drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
> drivers/crypto/qat/qat_asym.h | 97 +++++++++
> drivers/crypto/qat/qat_asym_capabilities.h | 10 +
> drivers/crypto/qat/qat_asym_pmd.c | 308 +++++++++++++++++++++++++++++
> drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
> drivers/crypto/qat/qat_sym_pmd.c | 1 -
> drivers/crypto/qat/qat_sym_pmd.h | 3 +-
> mk/rte.app.mk | 1 +
> 14 files changed, 742 insertions(+), 5 deletions(-)
> create mode 100644 drivers/crypto/qat/qat_asym.c
> create mode 100644 drivers/crypto/qat/qat_asym.h
> create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
> create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
> create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
>
> diff --git a/config/common_base b/config/common_base
> index 0b09a93..d1dd66a 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
> #
> CONFIG_RTE_LIBRTE_PMD_QAT=y
> CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
> +CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
> #
> # Max. number of QuickAssist devices, which can be detected and attached
> #
> diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
> index da9655c..53a8d61 100644
> --- a/doc/guides/cryptodevs/qat.rst
> +++ b/doc/guides/cryptodevs/qat.rst
> @@ -101,7 +101,13 @@ of all the items described above, including the padding at the end.
> Also, offset of data to authenticate "op.sym.auth.data.offset"
> must be such that points at the start of the COUNT bytes.
>
> +Asymmetric Crypto Service on QAT
> +-------------------------------
doc/guides/cryptodevs/qat.rst:105: WARNING: Title underline too short.
here one '-' is less. I corrected this while applying the patch.
> +
> +The QAT Asym PMD has support for:
>
> +Limitations
> +~~~~~~~~~~~
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-04-03 8:42 ` Akhil Goyal
2019-04-03 8:42 ` Akhil Goyal
@ 2019-04-03 9:05 ` Kusztal, ArkadiuszX
2019-04-03 9:05 ` Kusztal, ArkadiuszX
1 sibling, 1 reply; 18+ messages in thread
From: Kusztal, ArkadiuszX @ 2019-04-03 9:05 UTC (permalink / raw)
To: Akhil Goyal, dev; +Cc: Trahe, Fiona
Hi Akhil,
Thanks a lot for that, let me know if anything else is needed.
> -----Original Message-----
> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
> Sent: Wednesday, April 3, 2019 10:42 AM
> To: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>; dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>
> Subject: Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric
> cryptography PMD
>
> Hi Arek,
>
> On 3/28/2019 7:07 PM, Arek Kusztal wrote:
> > This patch adds Poll Mode Driver for asymmetric crypto functions of
> > Intel QuickAssist Technology hardware.
> >
> > It contains plain driver with no functions implmented, specific
> > algorithms will be introduced in separate patches.
> >
> > This patch depends on a QAT PF driver for device initialization. See
> > the file docs/guides/cryptodevs/qat.rst for configuration details.
> >
> > Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> > ---
> > config/common_base | 1 +
> > doc/guides/cryptodevs/qat.rst | 7 +
> > drivers/common/qat/Makefile | 8 +
> > drivers/common/qat/qat_device.h | 12 +-
> > drivers/common/qat/qat_qp.c | 8 +
> > drivers/crypto/qat/meson.build | 5 +-
> > drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
> > drivers/crypto/qat/qat_asym.h | 97 +++++++++
> > drivers/crypto/qat/qat_asym_capabilities.h | 10 +
> > drivers/crypto/qat/qat_asym_pmd.c | 308
> +++++++++++++++++++++++++++++
> > drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
> > drivers/crypto/qat/qat_sym_pmd.c | 1 -
> > drivers/crypto/qat/qat_sym_pmd.h | 3 +-
> > mk/rte.app.mk | 1 +
> > 14 files changed, 742 insertions(+), 5 deletions(-)
> > create mode 100644 drivers/crypto/qat/qat_asym.c
> > create mode 100644 drivers/crypto/qat/qat_asym.h
> > create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
> > create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
> > create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
> >
> > diff --git a/config/common_base b/config/common_base index
> > 0b09a93..d1dd66a 100644
> > --- a/config/common_base
> > +++ b/config/common_base
> > @@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
> > #
> > CONFIG_RTE_LIBRTE_PMD_QAT=y
> > CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
> > +CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
> > #
> > # Max. number of QuickAssist devices, which can be detected and
> attached
> > #
> > diff --git a/doc/guides/cryptodevs/qat.rst
> > b/doc/guides/cryptodevs/qat.rst index da9655c..53a8d61 100644
> > --- a/doc/guides/cryptodevs/qat.rst
> > +++ b/doc/guides/cryptodevs/qat.rst
> > @@ -101,7 +101,13 @@ of all the items described above, including the
> padding at the end.
> > Also, offset of data to authenticate "op.sym.auth.data.offset"
> > must be such that points at the start of the COUNT bytes.
> >
> > +Asymmetric Crypto Service on QAT
> > +-------------------------------
>
> doc/guides/cryptodevs/qat.rst:105: WARNING: Title underline too short.
>
>
> here one '-' is less. I corrected this while applying the patch.
>
> > +
> > +The QAT Asym PMD has support for:
> >
> > +Limitations
> > +~~~~~~~~~~~
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD
2019-04-03 9:05 ` Kusztal, ArkadiuszX
@ 2019-04-03 9:05 ` Kusztal, ArkadiuszX
0 siblings, 0 replies; 18+ messages in thread
From: Kusztal, ArkadiuszX @ 2019-04-03 9:05 UTC (permalink / raw)
To: Akhil Goyal, dev; +Cc: Trahe, Fiona
Hi Akhil,
Thanks a lot for that, let me know if anything else is needed.
> -----Original Message-----
> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
> Sent: Wednesday, April 3, 2019 10:42 AM
> To: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>; dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>
> Subject: Re: [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric
> cryptography PMD
>
> Hi Arek,
>
> On 3/28/2019 7:07 PM, Arek Kusztal wrote:
> > This patch adds Poll Mode Driver for asymmetric crypto functions of
> > Intel QuickAssist Technology hardware.
> >
> > It contains plain driver with no functions implmented, specific
> > algorithms will be introduced in separate patches.
> >
> > This patch depends on a QAT PF driver for device initialization. See
> > the file docs/guides/cryptodevs/qat.rst for configuration details.
> >
> > Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
> > ---
> > config/common_base | 1 +
> > doc/guides/cryptodevs/qat.rst | 7 +
> > drivers/common/qat/Makefile | 8 +
> > drivers/common/qat/qat_device.h | 12 +-
> > drivers/common/qat/qat_qp.c | 8 +
> > drivers/crypto/qat/meson.build | 5 +-
> > drivers/crypto/qat/qat_asym.c | 236 ++++++++++++++++++++++
> > drivers/crypto/qat/qat_asym.h | 97 +++++++++
> > drivers/crypto/qat/qat_asym_capabilities.h | 10 +
> > drivers/crypto/qat/qat_asym_pmd.c | 308
> +++++++++++++++++++++++++++++
> > drivers/crypto/qat/qat_asym_pmd.h | 50 +++++
> > drivers/crypto/qat/qat_sym_pmd.c | 1 -
> > drivers/crypto/qat/qat_sym_pmd.h | 3 +-
> > mk/rte.app.mk | 1 +
> > 14 files changed, 742 insertions(+), 5 deletions(-)
> > create mode 100644 drivers/crypto/qat/qat_asym.c
> > create mode 100644 drivers/crypto/qat/qat_asym.h
> > create mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
> > create mode 100644 drivers/crypto/qat/qat_asym_pmd.c
> > create mode 100644 drivers/crypto/qat/qat_asym_pmd.h
> >
> > diff --git a/config/common_base b/config/common_base index
> > 0b09a93..d1dd66a 100644
> > --- a/config/common_base
> > +++ b/config/common_base
> > @@ -545,6 +545,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
> > #
> > CONFIG_RTE_LIBRTE_PMD_QAT=y
> > CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
> > +CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
> > #
> > # Max. number of QuickAssist devices, which can be detected and
> attached
> > #
> > diff --git a/doc/guides/cryptodevs/qat.rst
> > b/doc/guides/cryptodevs/qat.rst index da9655c..53a8d61 100644
> > --- a/doc/guides/cryptodevs/qat.rst
> > +++ b/doc/guides/cryptodevs/qat.rst
> > @@ -101,7 +101,13 @@ of all the items described above, including the
> padding at the end.
> > Also, offset of data to authenticate "op.sym.auth.data.offset"
> > must be such that points at the start of the COUNT bytes.
> >
> > +Asymmetric Crypto Service on QAT
> > +-------------------------------
>
> doc/guides/cryptodevs/qat.rst:105: WARNING: Title underline too short.
>
>
> here one '-' is less. I corrected this while applying the patch.
>
> > +
> > +The QAT Asym PMD has support for:
> >
> > +Limitations
> > +~~~~~~~~~~~
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* [dpdk-dev] [PATCH v5 3/4] crypto/qat: add modular exponentiation to qat asym pmd
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
` (2 preceding siblings ...)
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 2/4] crypto/qat: add asymmetric cryptography PMD Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 4/4] crypto/qat: add modular inverse " Arek Kusztal
2019-03-28 13:57 ` [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Trahe, Fiona
5 siblings, 1 reply; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds modular exponentiation to Intel QuickAssist
Technology driver. For capabilities or limitations please refer to
qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/qat.rst | 2 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 2 +-
drivers/crypto/qat/qat_asym.c | 125 +++++++++++++++++++--
drivers/crypto/qat/qat_asym.h | 6 +
drivers/crypto/qat/qat_asym_capabilities.h | 18 ++-
drivers/crypto/qat/qat_asym_pmd.c | 1 +
6 files changed, 140 insertions(+), 14 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 53a8d61..e09ae8b 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -106,6 +106,8 @@ Asymmetric Crypto Service on QAT
The QAT Asym PMD has support for:
+* ``Modular exponentiation``
+
Limitations
~~~~~~~~~~~
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index 1fdb45a..ffea27e 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -10,7 +10,7 @@
/*
* Modular exponentiation functionality IDs
*/
-static const uint32_t __rte_unused MOD_EXP_SIZE[][2] = {
+static const uint32_t MOD_EXP_SIZE[][2] = {
{ 512, MATHS_MODEXP_L512 },
{ 1024, MATHS_MODEXP_L1024 },
{ 1536, MATHS_MODEXP_L1536 },
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 708bafa..6cd6435 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -11,7 +11,7 @@
#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
-static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
+static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
size_t arr_sz, size_t *size, uint32_t *func_id)
{
size_t i;
@@ -27,7 +27,7 @@ static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
}
static void qat_asym_build_req_tmpl(void *sess_private_data,
- struct rte_crypto_asym_xform __rte_unused *xform)
+ struct rte_crypto_asym_xform *xform)
{
struct icp_qat_fw_pke_request *qat_req;
@@ -50,9 +50,14 @@ static void qat_asym_build_req_tmpl(void *sess_private_data,
qat_req->resrvd1 = 0;
qat_req->resrvd2 = 0;
qat_req->next_req_adr = 0;
+
+ if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
+ qat_req->output_param_count = 1;
+ qat_req->input_param_count = 3;
+ }
}
-static size_t __rte_unused max_of(int n, ...)
+static size_t max_of(int n, ...)
{
va_list args;
size_t len = 0, num;
@@ -71,7 +76,7 @@ static size_t __rte_unused max_of(int n, ...)
return len;
}
-static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
+static void qat_clear_arrays(struct qat_asym_op_cookie *cookie,
int in_count, int out_count, int in_size, int out_size)
{
int i;
@@ -82,7 +87,7 @@ static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
memset(cookie->output_array[i], 0x0, out_size);
}
-static int __rte_unused qat_asym_check_nonzero(rte_crypto_param n)
+static int qat_asym_check_nonzero(rte_crypto_param n)
{
if (n.length < 8) {
/* Not a case for any cryptograpic function except for DH
@@ -120,12 +125,17 @@ qat_asym_build_request(void *in_op,
{
struct qat_asym_session *ctx;
struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
- struct rte_crypto_asym_op __rte_unused *asym_op = op->asym;
+ struct rte_crypto_asym_op *asym_op = op->asym;
struct icp_qat_fw_pke_request *qat_req =
(struct icp_qat_fw_pke_request *)out_msg;
struct qat_asym_op_cookie *cookie =
(struct qat_asym_op_cookie *)op_cookie;
+ uint64_t err = 0;
+ size_t alg_size;
+ size_t alg_size_in_bytes;
+ uint32_t func_id;
+
ctx = (struct qat_asym_session *)get_asym_session_private_data(
op->asym->session, cryptodev_qat_asym_driver_id);
rte_mov64((uint8_t *)qat_req, (const uint8_t *)&(ctx->req_tmpl));
@@ -134,7 +144,52 @@ qat_asym_build_request(void *in_op,
qat_req->pke_mid.src_data_addr = cookie->input_addr;
qat_req->pke_mid.dest_data_addr = cookie->output_addr;
- goto error;
+ if (ctx->alg == QAT_PKE_MODEXP) {
+ err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_exp.n);
+ if (err) {
+ QAT_LOG(ERR, "Empty modulus, aborting this operation");
+ goto error;
+ }
+
+ alg_size_in_bytes = max_of(3, asym_op->modex.base.length,
+ ctx->sess_alg_params.mod_exp.e.length,
+ ctx->sess_alg_params.mod_exp.n.length);
+ alg_size = alg_size_in_bytes << 3;
+
+ if (qat_asym_get_sz_and_func_id(MOD_EXP_SIZE,
+ sizeof(MOD_EXP_SIZE)/sizeof(*MOD_EXP_SIZE),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+
+ alg_size_in_bytes = alg_size >> 3;
+ rte_memcpy(cookie->input_array[0] + alg_size_in_bytes -
+ asym_op->modex.base.length
+ , asym_op->modex.base.data,
+ asym_op->modex.base.length);
+ rte_memcpy(cookie->input_array[1] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_exp.e.length
+ , ctx->sess_alg_params.mod_exp.e.data,
+ ctx->sess_alg_params.mod_exp.e.length);
+ rte_memcpy(cookie->input_array[2] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_exp.n.length,
+ ctx->sess_alg_params.mod_exp.n.data,
+ ctx->sess_alg_params.mod_exp.n.length);
+ cookie->alg_size = alg_size;
+ qat_req->pke_hdr.cd_pars.func_id = func_id;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "base",
+ cookie->input_array[0],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "exponent",
+ cookie->input_array[1],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modulus",
+ cookie->input_array[2],
+ alg_size_in_bytes);
+#endif
+ }
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
@@ -145,7 +200,7 @@ qat_asym_build_request(void *in_op,
qat_req->output_param_count = 0;
qat_req->input_param_count = 0;
qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
- cookie->error |= QAT_ASYM_ERROR_INVALID_PARAM;
+ cookie->error |= err;
return 0;
}
@@ -154,11 +209,17 @@ void
qat_asym_process_response(void **op, uint8_t *resp,
void *op_cookie)
{
+ struct qat_asym_session *ctx;
struct icp_qat_fw_pke_resp *resp_msg =
(struct icp_qat_fw_pke_resp *)resp;
struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
(resp_msg->opaque);
+ struct rte_crypto_asym_op *asym_op = rx_op->asym;
struct qat_asym_op_cookie *cookie = op_cookie;
+ size_t alg_size, alg_size_in_bytes;
+
+ ctx = (struct qat_asym_session *)get_asym_session_private_data(
+ rx_op->asym->session, cryptodev_qat_asym_driver_id);
*op = rx_op;
rx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
@@ -179,6 +240,30 @@ qat_asym_process_response(void **op, uint8_t *resp,
}
}
+ if (ctx->alg == QAT_PKE_MODEXP) {
+ alg_size = cookie->alg_size;
+ alg_size_in_bytes = alg_size >> 3;
+ uint8_t *modexp_result = asym_op->modex.result.data;
+
+ if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {
+ rte_memcpy(modexp_result +
+ (asym_op->modex.result.length -
+ ctx->sess_alg_params.mod_exp.n.length),
+ cookie->output_array[0] + alg_size_in_bytes
+ - ctx->sess_alg_params.mod_exp.n.length,
+ ctx->sess_alg_params.mod_exp.n.length
+ );
+ rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modexp_result",
+ cookie->output_array[0],
+ alg_size_in_bytes);
+#endif
+ }
+ qat_clear_arrays(cookie, 3, 1, alg_size_in_bytes,
+ alg_size_in_bytes);
+ }
+
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg,
sizeof(struct icp_qat_fw_pke_resp));
@@ -191,24 +276,40 @@ qat_asym_session_configure(struct rte_cryptodev *dev,
struct rte_cryptodev_asym_session *sess,
struct rte_mempool *mempool)
{
- int err;
+ int err = 0;
void *sess_private_data;
+ struct qat_asym_session *session;
- err = -EINVAL;
- goto error;
if (rte_mempool_get(mempool, &sess_private_data)) {
QAT_LOG(ERR,
"Couldn't get object from session mempool");
return -ENOMEM;
}
+ session = sess_private_data;
+ if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
+ session->sess_alg_params.mod_exp.e = xform->modex.exponent;
+ session->sess_alg_params.mod_exp.n = xform->modex.modulus;
+ session->alg = QAT_PKE_MODEXP;
+
+ if (xform->modex.exponent.length == 0 ||
+ xform->modex.modulus.length == 0) {
+ QAT_LOG(ERR, "Invalid mod exp input parameter");
+ err = -EINVAL;
+ goto error;
+ }
+ } else {
+ QAT_LOG(ERR, "Invalid asymmetric crypto xform");
+ err = -EINVAL;
+ goto error;
+ }
qat_asym_build_req_tmpl(sess_private_data, xform);
-
set_asym_session_private_data(sess, dev->driver_id,
sess_private_data);
return 0;
error:
+ rte_mempool_put(mempool, sess_private_data);
return err;
}
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
index 7e5982d..228d2f7 100644
--- a/drivers/crypto/qat/qat_asym.h
+++ b/drivers/crypto/qat/qat_asym.h
@@ -45,6 +45,12 @@ struct qat_asym_session {
enum qat_asym_alg alg;
struct icp_qat_fw_pke_request req_tmpl;
uint64_t flags;
+ union {
+ struct {
+ rte_crypto_param n;
+ rte_crypto_param e;
+ } mod_exp;
+ } sess_alg_params;
};
int
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
index b50e061..1d6323f 100644
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -5,6 +5,22 @@
#ifndef _QAT_ASYM_CAPABILITIES_H_
#define _QAT_ASYM_CAPABILITIES_H_
-#define QAT_BASE_GEN1_ASYM_CAPABILITIES
+#define QAT_BASE_GEN1_ASYM_CAPABILITIES \
+ { /* modexp */ \
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, \
+ {.asym = { \
+ .xform_capa = { \
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, \
+ .op_types = 0, \
+ { \
+ .modlen = { \
+ .min = 1, \
+ .max = 512, \
+ .increment = 1 \
+ }, } \
+ } \
+ }, \
+ } \
+ } \
#endif /* _QAT_ASYM_CAPABILITIES_H_ */
diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c
index 254bc48..c999799 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -14,6 +14,7 @@
uint8_t cryptodev_qat_asym_driver_id;
static const struct rte_cryptodev_capabilities qat_gen1_asym_capabilities[] = {
+ QAT_BASE_GEN1_ASYM_CAPABILITIES,
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* [dpdk-dev] [PATCH v5 3/4] crypto/qat: add modular exponentiation to qat asym pmd
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 3/4] crypto/qat: add modular exponentiation to qat asym pmd Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
0 siblings, 0 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds modular exponentiation to Intel QuickAssist
Technology driver. For capabilities or limitations please refer to
qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/qat.rst | 2 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 2 +-
drivers/crypto/qat/qat_asym.c | 125 +++++++++++++++++++--
drivers/crypto/qat/qat_asym.h | 6 +
drivers/crypto/qat/qat_asym_capabilities.h | 18 ++-
drivers/crypto/qat/qat_asym_pmd.c | 1 +
6 files changed, 140 insertions(+), 14 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 53a8d61..e09ae8b 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -106,6 +106,8 @@ Asymmetric Crypto Service on QAT
The QAT Asym PMD has support for:
+* ``Modular exponentiation``
+
Limitations
~~~~~~~~~~~
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index 1fdb45a..ffea27e 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -10,7 +10,7 @@
/*
* Modular exponentiation functionality IDs
*/
-static const uint32_t __rte_unused MOD_EXP_SIZE[][2] = {
+static const uint32_t MOD_EXP_SIZE[][2] = {
{ 512, MATHS_MODEXP_L512 },
{ 1024, MATHS_MODEXP_L1024 },
{ 1536, MATHS_MODEXP_L1536 },
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 708bafa..6cd6435 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -11,7 +11,7 @@
#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
-static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
+static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
size_t arr_sz, size_t *size, uint32_t *func_id)
{
size_t i;
@@ -27,7 +27,7 @@ static int __rte_unused qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
}
static void qat_asym_build_req_tmpl(void *sess_private_data,
- struct rte_crypto_asym_xform __rte_unused *xform)
+ struct rte_crypto_asym_xform *xform)
{
struct icp_qat_fw_pke_request *qat_req;
@@ -50,9 +50,14 @@ static void qat_asym_build_req_tmpl(void *sess_private_data,
qat_req->resrvd1 = 0;
qat_req->resrvd2 = 0;
qat_req->next_req_adr = 0;
+
+ if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
+ qat_req->output_param_count = 1;
+ qat_req->input_param_count = 3;
+ }
}
-static size_t __rte_unused max_of(int n, ...)
+static size_t max_of(int n, ...)
{
va_list args;
size_t len = 0, num;
@@ -71,7 +76,7 @@ static size_t __rte_unused max_of(int n, ...)
return len;
}
-static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
+static void qat_clear_arrays(struct qat_asym_op_cookie *cookie,
int in_count, int out_count, int in_size, int out_size)
{
int i;
@@ -82,7 +87,7 @@ static void __rte_unused qat_clear_arrays(struct qat_asym_op_cookie *cookie,
memset(cookie->output_array[i], 0x0, out_size);
}
-static int __rte_unused qat_asym_check_nonzero(rte_crypto_param n)
+static int qat_asym_check_nonzero(rte_crypto_param n)
{
if (n.length < 8) {
/* Not a case for any cryptograpic function except for DH
@@ -120,12 +125,17 @@ qat_asym_build_request(void *in_op,
{
struct qat_asym_session *ctx;
struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
- struct rte_crypto_asym_op __rte_unused *asym_op = op->asym;
+ struct rte_crypto_asym_op *asym_op = op->asym;
struct icp_qat_fw_pke_request *qat_req =
(struct icp_qat_fw_pke_request *)out_msg;
struct qat_asym_op_cookie *cookie =
(struct qat_asym_op_cookie *)op_cookie;
+ uint64_t err = 0;
+ size_t alg_size;
+ size_t alg_size_in_bytes;
+ uint32_t func_id;
+
ctx = (struct qat_asym_session *)get_asym_session_private_data(
op->asym->session, cryptodev_qat_asym_driver_id);
rte_mov64((uint8_t *)qat_req, (const uint8_t *)&(ctx->req_tmpl));
@@ -134,7 +144,52 @@ qat_asym_build_request(void *in_op,
qat_req->pke_mid.src_data_addr = cookie->input_addr;
qat_req->pke_mid.dest_data_addr = cookie->output_addr;
- goto error;
+ if (ctx->alg == QAT_PKE_MODEXP) {
+ err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_exp.n);
+ if (err) {
+ QAT_LOG(ERR, "Empty modulus, aborting this operation");
+ goto error;
+ }
+
+ alg_size_in_bytes = max_of(3, asym_op->modex.base.length,
+ ctx->sess_alg_params.mod_exp.e.length,
+ ctx->sess_alg_params.mod_exp.n.length);
+ alg_size = alg_size_in_bytes << 3;
+
+ if (qat_asym_get_sz_and_func_id(MOD_EXP_SIZE,
+ sizeof(MOD_EXP_SIZE)/sizeof(*MOD_EXP_SIZE),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+
+ alg_size_in_bytes = alg_size >> 3;
+ rte_memcpy(cookie->input_array[0] + alg_size_in_bytes -
+ asym_op->modex.base.length
+ , asym_op->modex.base.data,
+ asym_op->modex.base.length);
+ rte_memcpy(cookie->input_array[1] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_exp.e.length
+ , ctx->sess_alg_params.mod_exp.e.data,
+ ctx->sess_alg_params.mod_exp.e.length);
+ rte_memcpy(cookie->input_array[2] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_exp.n.length,
+ ctx->sess_alg_params.mod_exp.n.data,
+ ctx->sess_alg_params.mod_exp.n.length);
+ cookie->alg_size = alg_size;
+ qat_req->pke_hdr.cd_pars.func_id = func_id;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "base",
+ cookie->input_array[0],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "exponent",
+ cookie->input_array[1],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modulus",
+ cookie->input_array[2],
+ alg_size_in_bytes);
+#endif
+ }
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
@@ -145,7 +200,7 @@ qat_asym_build_request(void *in_op,
qat_req->output_param_count = 0;
qat_req->input_param_count = 0;
qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
- cookie->error |= QAT_ASYM_ERROR_INVALID_PARAM;
+ cookie->error |= err;
return 0;
}
@@ -154,11 +209,17 @@ void
qat_asym_process_response(void **op, uint8_t *resp,
void *op_cookie)
{
+ struct qat_asym_session *ctx;
struct icp_qat_fw_pke_resp *resp_msg =
(struct icp_qat_fw_pke_resp *)resp;
struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
(resp_msg->opaque);
+ struct rte_crypto_asym_op *asym_op = rx_op->asym;
struct qat_asym_op_cookie *cookie = op_cookie;
+ size_t alg_size, alg_size_in_bytes;
+
+ ctx = (struct qat_asym_session *)get_asym_session_private_data(
+ rx_op->asym->session, cryptodev_qat_asym_driver_id);
*op = rx_op;
rx_op->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;
@@ -179,6 +240,30 @@ qat_asym_process_response(void **op, uint8_t *resp,
}
}
+ if (ctx->alg == QAT_PKE_MODEXP) {
+ alg_size = cookie->alg_size;
+ alg_size_in_bytes = alg_size >> 3;
+ uint8_t *modexp_result = asym_op->modex.result.data;
+
+ if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {
+ rte_memcpy(modexp_result +
+ (asym_op->modex.result.length -
+ ctx->sess_alg_params.mod_exp.n.length),
+ cookie->output_array[0] + alg_size_in_bytes
+ - ctx->sess_alg_params.mod_exp.n.length,
+ ctx->sess_alg_params.mod_exp.n.length
+ );
+ rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modexp_result",
+ cookie->output_array[0],
+ alg_size_in_bytes);
+#endif
+ }
+ qat_clear_arrays(cookie, 3, 1, alg_size_in_bytes,
+ alg_size_in_bytes);
+ }
+
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg,
sizeof(struct icp_qat_fw_pke_resp));
@@ -191,24 +276,40 @@ qat_asym_session_configure(struct rte_cryptodev *dev,
struct rte_cryptodev_asym_session *sess,
struct rte_mempool *mempool)
{
- int err;
+ int err = 0;
void *sess_private_data;
+ struct qat_asym_session *session;
- err = -EINVAL;
- goto error;
if (rte_mempool_get(mempool, &sess_private_data)) {
QAT_LOG(ERR,
"Couldn't get object from session mempool");
return -ENOMEM;
}
+ session = sess_private_data;
+ if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
+ session->sess_alg_params.mod_exp.e = xform->modex.exponent;
+ session->sess_alg_params.mod_exp.n = xform->modex.modulus;
+ session->alg = QAT_PKE_MODEXP;
+
+ if (xform->modex.exponent.length == 0 ||
+ xform->modex.modulus.length == 0) {
+ QAT_LOG(ERR, "Invalid mod exp input parameter");
+ err = -EINVAL;
+ goto error;
+ }
+ } else {
+ QAT_LOG(ERR, "Invalid asymmetric crypto xform");
+ err = -EINVAL;
+ goto error;
+ }
qat_asym_build_req_tmpl(sess_private_data, xform);
-
set_asym_session_private_data(sess, dev->driver_id,
sess_private_data);
return 0;
error:
+ rte_mempool_put(mempool, sess_private_data);
return err;
}
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
index 7e5982d..228d2f7 100644
--- a/drivers/crypto/qat/qat_asym.h
+++ b/drivers/crypto/qat/qat_asym.h
@@ -45,6 +45,12 @@ struct qat_asym_session {
enum qat_asym_alg alg;
struct icp_qat_fw_pke_request req_tmpl;
uint64_t flags;
+ union {
+ struct {
+ rte_crypto_param n;
+ rte_crypto_param e;
+ } mod_exp;
+ } sess_alg_params;
};
int
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
index b50e061..1d6323f 100644
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -5,6 +5,22 @@
#ifndef _QAT_ASYM_CAPABILITIES_H_
#define _QAT_ASYM_CAPABILITIES_H_
-#define QAT_BASE_GEN1_ASYM_CAPABILITIES
+#define QAT_BASE_GEN1_ASYM_CAPABILITIES \
+ { /* modexp */ \
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, \
+ {.asym = { \
+ .xform_capa = { \
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX, \
+ .op_types = 0, \
+ { \
+ .modlen = { \
+ .min = 1, \
+ .max = 512, \
+ .increment = 1 \
+ }, } \
+ } \
+ }, \
+ } \
+ } \
#endif /* _QAT_ASYM_CAPABILITIES_H_ */
diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c
index 254bc48..c999799 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -14,6 +14,7 @@
uint8_t cryptodev_qat_asym_driver_id;
static const struct rte_cryptodev_capabilities qat_gen1_asym_capabilities[] = {
+ QAT_BASE_GEN1_ASYM_CAPABILITIES,
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [dpdk-dev] [PATCH v5 4/4] crypto/qat: add modular inverse to qat asym pmd
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
` (3 preceding siblings ...)
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 3/4] crypto/qat: add modular exponentiation to qat asym pmd Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:37 ` Arek Kusztal
2019-03-28 13:57 ` [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Trahe, Fiona
5 siblings, 1 reply; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds modular multiplicative inverse to Intel
QuickAssist Technology driver. For capabilities or limitations
please refer to qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/qat.rst | 1 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 4 +-
drivers/crypto/qat/qat_asym.c | 85 +++++++++++++++++++++-
drivers/crypto/qat/qat_asym.h | 3 +
drivers/crypto/qat/qat_asym_capabilities.h | 16 ++++
5 files changed, 106 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index e09ae8b..3c2467d 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -107,6 +107,7 @@ Asymmetric Crypto Service on QAT
The QAT Asym PMD has support for:
* ``Modular exponentiation``
+* ``Modular multiplicative inverse``
Limitations
~~~~~~~~~~~
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index ffea27e..8adf209 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -21,7 +21,7 @@ static const uint32_t MOD_EXP_SIZE[][2] = {
{ 4096, MATHS_MODEXP_L4096 }
};
-static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
+static const uint32_t MOD_INV_IDS_ODD[][2] = {
{ 128, MATHS_MODINV_ODD_L128 },
{ 192, MATHS_MODINV_ODD_L192 },
{ 256, MATHS_MODINV_ODD_L256 },
@@ -35,7 +35,7 @@ static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
{ 4096, MATHS_MODINV_ODD_L4096 },
};
-static const uint32_t __rte_unused MOD_INV_IDS_EVEN[][2] = {
+static const uint32_t MOD_INV_IDS_EVEN[][2] = {
{ 128, MATHS_MODINV_EVEN_L128 },
{ 192, MATHS_MODINV_EVEN_L192 },
{ 256, MATHS_MODINV_EVEN_L256 },
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 6cd6435..4ddb0e5 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -54,6 +54,9 @@ static void qat_asym_build_req_tmpl(void *sess_private_data,
if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
qat_req->output_param_count = 1;
qat_req->input_param_count = 3;
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {
+ qat_req->output_param_count = 1;
+ qat_req->input_param_count = 2;
}
}
@@ -147,7 +150,8 @@ qat_asym_build_request(void *in_op,
if (ctx->alg == QAT_PKE_MODEXP) {
err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_exp.n);
if (err) {
- QAT_LOG(ERR, "Empty modulus, aborting this operation");
+ QAT_LOG(ERR, "Empty modulus in modular exponentiation,"
+ " aborting this operation");
goto error;
}
@@ -189,6 +193,56 @@ qat_asym_build_request(void *in_op,
cookie->input_array[2],
alg_size_in_bytes);
#endif
+ } else if (ctx->alg == QAT_PKE_MODINV) {
+ err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_inv.n);
+ if (err) {
+ QAT_LOG(ERR, "Empty modulus in modular multiplicative"
+ " inverse, aborting this operation");
+ goto error;
+ }
+
+ alg_size_in_bytes = max_of(2, asym_op->modinv.base.length,
+ ctx->sess_alg_params.mod_inv.n.length);
+ alg_size = alg_size_in_bytes << 3;
+
+ if (ctx->sess_alg_params.mod_inv.n.data[
+ ctx->sess_alg_params.mod_inv.n.length - 1] & 0x01) {
+ if (qat_asym_get_sz_and_func_id(MOD_INV_IDS_ODD,
+ sizeof(MOD_INV_IDS_ODD)/
+ sizeof(*MOD_INV_IDS_ODD),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+ } else {
+ if (qat_asym_get_sz_and_func_id(MOD_INV_IDS_EVEN,
+ sizeof(MOD_INV_IDS_EVEN)/
+ sizeof(*MOD_INV_IDS_EVEN),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+ }
+
+ alg_size_in_bytes = alg_size >> 3;
+ rte_memcpy(cookie->input_array[0] + alg_size_in_bytes -
+ asym_op->modinv.base.length
+ , asym_op->modinv.base.data,
+ asym_op->modinv.base.length);
+ rte_memcpy(cookie->input_array[1] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_inv.n.length
+ , ctx->sess_alg_params.mod_inv.n.data,
+ ctx->sess_alg_params.mod_inv.n.length);
+ cookie->alg_size = alg_size;
+ qat_req->pke_hdr.cd_pars.func_id = func_id;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "base",
+ cookie->input_array[0],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modulus",
+ cookie->input_array[1],
+ alg_size_in_bytes);
+#endif
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -262,6 +316,26 @@ qat_asym_process_response(void **op, uint8_t *resp,
}
qat_clear_arrays(cookie, 3, 1, alg_size_in_bytes,
alg_size_in_bytes);
+ } else if (ctx->alg == QAT_PKE_MODINV) {
+ alg_size = cookie->alg_size;
+ alg_size_in_bytes = alg_size >> 3;
+ uint8_t *modinv_result = asym_op->modinv.result.data;
+
+ if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {
+ rte_memcpy(modinv_result + (asym_op->modinv.result.length
+ - ctx->sess_alg_params.mod_inv.n.length),
+ cookie->output_array[0] + alg_size_in_bytes
+ - ctx->sess_alg_params.mod_inv.n.length,
+ ctx->sess_alg_params.mod_inv.n.length);
+ rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modinv_result",
+ cookie->output_array[0],
+ alg_size_in_bytes);
+#endif
+ }
+ qat_clear_arrays(cookie, 2, 1, alg_size_in_bytes,
+ alg_size_in_bytes);
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -298,6 +372,15 @@ qat_asym_session_configure(struct rte_cryptodev *dev,
err = -EINVAL;
goto error;
}
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {
+ session->sess_alg_params.mod_inv.n = xform->modinv.modulus;
+ session->alg = QAT_PKE_MODINV;
+
+ if (xform->modinv.modulus.length == 0) {
+ QAT_LOG(ERR, "Invalid mod inv input parameter");
+ err = -EINVAL;
+ goto error;
+ }
} else {
QAT_LOG(ERR, "Invalid asymmetric crypto xform");
err = -EINVAL;
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
index 228d2f7..ce4839b 100644
--- a/drivers/crypto/qat/qat_asym.h
+++ b/drivers/crypto/qat/qat_asym.h
@@ -50,6 +50,9 @@ struct qat_asym_session {
rte_crypto_param n;
rte_crypto_param e;
} mod_exp;
+ struct {
+ rte_crypto_param n;
+ } mod_inv;
} sess_alg_params;
};
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
index 1d6323f..f43c025 100644
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -21,6 +21,22 @@
} \
}, \
} \
+ }, \
+ { /* modinv */ \
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, \
+ {.asym = { \
+ .xform_capa = { \
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODINV, \
+ .op_types = 0, \
+ { \
+ .modlen = { \
+ .min = 1, \
+ .max = 512, \
+ .increment = 1 \
+ }, } \
+ } \
+ }, \
+ } \
} \
#endif /* _QAT_ASYM_CAPABILITIES_H_ */
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread* [dpdk-dev] [PATCH v5 4/4] crypto/qat: add modular inverse to qat asym pmd
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 4/4] crypto/qat: add modular inverse " Arek Kusztal
@ 2019-03-28 13:37 ` Arek Kusztal
0 siblings, 0 replies; 18+ messages in thread
From: Arek Kusztal @ 2019-03-28 13:37 UTC (permalink / raw)
To: dev; +Cc: akhil.goyal, fiona.trahe, Arek Kusztal
This commit adds modular multiplicative inverse to Intel
QuickAssist Technology driver. For capabilities or limitations
please refer to qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/qat.rst | 1 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 4 +-
drivers/crypto/qat/qat_asym.c | 85 +++++++++++++++++++++-
drivers/crypto/qat/qat_asym.h | 3 +
drivers/crypto/qat/qat_asym_capabilities.h | 16 ++++
5 files changed, 106 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index e09ae8b..3c2467d 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -107,6 +107,7 @@ Asymmetric Crypto Service on QAT
The QAT Asym PMD has support for:
* ``Modular exponentiation``
+* ``Modular multiplicative inverse``
Limitations
~~~~~~~~~~~
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index ffea27e..8adf209 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -21,7 +21,7 @@ static const uint32_t MOD_EXP_SIZE[][2] = {
{ 4096, MATHS_MODEXP_L4096 }
};
-static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
+static const uint32_t MOD_INV_IDS_ODD[][2] = {
{ 128, MATHS_MODINV_ODD_L128 },
{ 192, MATHS_MODINV_ODD_L192 },
{ 256, MATHS_MODINV_ODD_L256 },
@@ -35,7 +35,7 @@ static const uint32_t __rte_unused MOD_INV_IDS_ODD[][2] = {
{ 4096, MATHS_MODINV_ODD_L4096 },
};
-static const uint32_t __rte_unused MOD_INV_IDS_EVEN[][2] = {
+static const uint32_t MOD_INV_IDS_EVEN[][2] = {
{ 128, MATHS_MODINV_EVEN_L128 },
{ 192, MATHS_MODINV_EVEN_L192 },
{ 256, MATHS_MODINV_EVEN_L256 },
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 6cd6435..4ddb0e5 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -54,6 +54,9 @@ static void qat_asym_build_req_tmpl(void *sess_private_data,
if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
qat_req->output_param_count = 1;
qat_req->input_param_count = 3;
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {
+ qat_req->output_param_count = 1;
+ qat_req->input_param_count = 2;
}
}
@@ -147,7 +150,8 @@ qat_asym_build_request(void *in_op,
if (ctx->alg == QAT_PKE_MODEXP) {
err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_exp.n);
if (err) {
- QAT_LOG(ERR, "Empty modulus, aborting this operation");
+ QAT_LOG(ERR, "Empty modulus in modular exponentiation,"
+ " aborting this operation");
goto error;
}
@@ -189,6 +193,56 @@ qat_asym_build_request(void *in_op,
cookie->input_array[2],
alg_size_in_bytes);
#endif
+ } else if (ctx->alg == QAT_PKE_MODINV) {
+ err = qat_asym_check_nonzero(ctx->sess_alg_params.mod_inv.n);
+ if (err) {
+ QAT_LOG(ERR, "Empty modulus in modular multiplicative"
+ " inverse, aborting this operation");
+ goto error;
+ }
+
+ alg_size_in_bytes = max_of(2, asym_op->modinv.base.length,
+ ctx->sess_alg_params.mod_inv.n.length);
+ alg_size = alg_size_in_bytes << 3;
+
+ if (ctx->sess_alg_params.mod_inv.n.data[
+ ctx->sess_alg_params.mod_inv.n.length - 1] & 0x01) {
+ if (qat_asym_get_sz_and_func_id(MOD_INV_IDS_ODD,
+ sizeof(MOD_INV_IDS_ODD)/
+ sizeof(*MOD_INV_IDS_ODD),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+ } else {
+ if (qat_asym_get_sz_and_func_id(MOD_INV_IDS_EVEN,
+ sizeof(MOD_INV_IDS_EVEN)/
+ sizeof(*MOD_INV_IDS_EVEN),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ goto error;
+ }
+ }
+
+ alg_size_in_bytes = alg_size >> 3;
+ rte_memcpy(cookie->input_array[0] + alg_size_in_bytes -
+ asym_op->modinv.base.length
+ , asym_op->modinv.base.data,
+ asym_op->modinv.base.length);
+ rte_memcpy(cookie->input_array[1] + alg_size_in_bytes -
+ ctx->sess_alg_params.mod_inv.n.length
+ , ctx->sess_alg_params.mod_inv.n.data,
+ ctx->sess_alg_params.mod_inv.n.length);
+ cookie->alg_size = alg_size;
+ qat_req->pke_hdr.cd_pars.func_id = func_id;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "base",
+ cookie->input_array[0],
+ alg_size_in_bytes);
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modulus",
+ cookie->input_array[1],
+ alg_size_in_bytes);
+#endif
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -262,6 +316,26 @@ qat_asym_process_response(void **op, uint8_t *resp,
}
qat_clear_arrays(cookie, 3, 1, alg_size_in_bytes,
alg_size_in_bytes);
+ } else if (ctx->alg == QAT_PKE_MODINV) {
+ alg_size = cookie->alg_size;
+ alg_size_in_bytes = alg_size >> 3;
+ uint8_t *modinv_result = asym_op->modinv.result.data;
+
+ if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) {
+ rte_memcpy(modinv_result + (asym_op->modinv.result.length
+ - ctx->sess_alg_params.mod_inv.n.length),
+ cookie->output_array[0] + alg_size_in_bytes
+ - ctx->sess_alg_params.mod_inv.n.length,
+ ctx->sess_alg_params.mod_inv.n.length);
+ rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "modinv_result",
+ cookie->output_array[0],
+ alg_size_in_bytes);
+#endif
+ }
+ qat_clear_arrays(cookie, 2, 1, alg_size_in_bytes,
+ alg_size_in_bytes);
}
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
@@ -298,6 +372,15 @@ qat_asym_session_configure(struct rte_cryptodev *dev,
err = -EINVAL;
goto error;
}
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {
+ session->sess_alg_params.mod_inv.n = xform->modinv.modulus;
+ session->alg = QAT_PKE_MODINV;
+
+ if (xform->modinv.modulus.length == 0) {
+ QAT_LOG(ERR, "Invalid mod inv input parameter");
+ err = -EINVAL;
+ goto error;
+ }
} else {
QAT_LOG(ERR, "Invalid asymmetric crypto xform");
err = -EINVAL;
diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h
index 228d2f7..ce4839b 100644
--- a/drivers/crypto/qat/qat_asym.h
+++ b/drivers/crypto/qat/qat_asym.h
@@ -50,6 +50,9 @@ struct qat_asym_session {
rte_crypto_param n;
rte_crypto_param e;
} mod_exp;
+ struct {
+ rte_crypto_param n;
+ } mod_inv;
} sess_alg_params;
};
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h b/drivers/crypto/qat/qat_asym_capabilities.h
index 1d6323f..f43c025 100644
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ b/drivers/crypto/qat/qat_asym_capabilities.h
@@ -21,6 +21,22 @@
} \
}, \
} \
+ }, \
+ { /* modinv */ \
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, \
+ {.asym = { \
+ .xform_capa = { \
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_MODINV, \
+ .op_types = 0, \
+ { \
+ .modlen = { \
+ .min = 1, \
+ .max = 512, \
+ .increment = 1 \
+ }, } \
+ } \
+ }, \
+ } \
} \
#endif /* _QAT_ASYM_CAPABILITIES_H_ */
--
2.1.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices
2019-03-28 13:36 [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Arek Kusztal
` (4 preceding siblings ...)
2019-03-28 13:37 ` [dpdk-dev] [PATCH v5 4/4] crypto/qat: add modular inverse " Arek Kusztal
@ 2019-03-28 13:57 ` Trahe, Fiona
2019-03-28 13:57 ` Trahe, Fiona
2019-03-29 14:27 ` Akhil Goyal
5 siblings, 2 replies; 18+ messages in thread
From: Trahe, Fiona @ 2019-03-28 13:57 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev; +Cc: akhil.goyal, Trahe, Fiona
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Thursday, March 28, 2019 1:37 PM
> To: dev@dpdk.org
> Cc: akhil.goyal@nxp.com; Trahe, Fiona <fiona.trahe@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist
> Technology devices
>
> This patchset adds Poll Mode Driver to use asymmetric cryptography
> functions using Intel QuickAssist Techology devices.
>
> Following functions are available with this patchset:
> * Modular Exponentiation
> * Modular Inverse
>
> This patch depends on a QAT PF driver for device initialization. See
> the file docs/guides/cryptodevs/qat.rst for configuration details.
>
> Limitations:
> * Maximum parameter size: 4096 bits
> - For both modular exponentiaion and modular multiplicative inverse
>
> v5:
> - changed error checks order
>
> v4:
> - fixed yet more checkpatch issues
>
> v3:
> - fixed some checkpatch issues
>
> v2:
> - added Meson build
> - fixed segfault on cookie
> - fixed mod inverse problem
>
> Arek Kusztal (4):
> common/qat: add headers for asymmetric crypto
> crypto/qat: add asymmetric cryptography PMD
> crypto/qat: add modular exponentiation to qat asym pmd
> crypto/qat: add modular inverse to qat asym pmd
Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices
2019-03-28 13:57 ` [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Trahe, Fiona
@ 2019-03-28 13:57 ` Trahe, Fiona
2019-03-29 14:27 ` Akhil Goyal
1 sibling, 0 replies; 18+ messages in thread
From: Trahe, Fiona @ 2019-03-28 13:57 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev; +Cc: akhil.goyal, Trahe, Fiona
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Thursday, March 28, 2019 1:37 PM
> To: dev@dpdk.org
> Cc: akhil.goyal@nxp.com; Trahe, Fiona <fiona.trahe@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist
> Technology devices
>
> This patchset adds Poll Mode Driver to use asymmetric cryptography
> functions using Intel QuickAssist Techology devices.
>
> Following functions are available with this patchset:
> * Modular Exponentiation
> * Modular Inverse
>
> This patch depends on a QAT PF driver for device initialization. See
> the file docs/guides/cryptodevs/qat.rst for configuration details.
>
> Limitations:
> * Maximum parameter size: 4096 bits
> - For both modular exponentiaion and modular multiplicative inverse
>
> v5:
> - changed error checks order
>
> v4:
> - fixed yet more checkpatch issues
>
> v3:
> - fixed some checkpatch issues
>
> v2:
> - added Meson build
> - fixed segfault on cookie
> - fixed mod inverse problem
>
> Arek Kusztal (4):
> common/qat: add headers for asymmetric crypto
> crypto/qat: add asymmetric cryptography PMD
> crypto/qat: add modular exponentiation to qat asym pmd
> crypto/qat: add modular inverse to qat asym pmd
Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices
2019-03-28 13:57 ` [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices Trahe, Fiona
2019-03-28 13:57 ` Trahe, Fiona
@ 2019-03-29 14:27 ` Akhil Goyal
2019-03-29 14:27 ` Akhil Goyal
1 sibling, 1 reply; 18+ messages in thread
From: Akhil Goyal @ 2019-03-29 14:27 UTC (permalink / raw)
To: Trahe, Fiona, Kusztal, ArkadiuszX, dev
On 3/28/2019 7:27 PM, Trahe, Fiona wrote:
>
>> -----Original Message-----
>> From: Kusztal, ArkadiuszX
>> Sent: Thursday, March 28, 2019 1:37 PM
>> To: dev@dpdk.org
>> Cc: akhil.goyal@nxp.com; Trahe, Fiona <fiona.trahe@intel.com>; Kusztal, ArkadiuszX
>> <arkadiuszx.kusztal@intel.com>
>> Subject: [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist
>> Technology devices
>>
>> This patchset adds Poll Mode Driver to use asymmetric cryptography
>> functions using Intel QuickAssist Techology devices.
>>
>> Following functions are available with this patchset:
>> * Modular Exponentiation
>> * Modular Inverse
>>
>> This patch depends on a QAT PF driver for device initialization. See
>> the file docs/guides/cryptodevs/qat.rst for configuration details.
>>
>> Limitations:
>> * Maximum parameter size: 4096 bits
>> - For both modular exponentiaion and modular multiplicative inverse
>>
>> v5:
>> - changed error checks order
>>
>> v4:
>> - fixed yet more checkpatch issues
>>
>> v3:
>> - fixed some checkpatch issues
>>
>> v2:
>> - added Meson build
>> - fixed segfault on cookie
>> - fixed mod inverse problem
>>
>> Arek Kusztal (4):
>> common/qat: add headers for asymmetric crypto
>> crypto/qat: add asymmetric cryptography PMD
>> crypto/qat: add modular exponentiation to qat asym pmd
>> crypto/qat: add modular inverse to qat asym pmd
> Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [dpdk-dev] [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist Technology devices
2019-03-29 14:27 ` Akhil Goyal
@ 2019-03-29 14:27 ` Akhil Goyal
0 siblings, 0 replies; 18+ messages in thread
From: Akhil Goyal @ 2019-03-29 14:27 UTC (permalink / raw)
To: Trahe, Fiona, Kusztal, ArkadiuszX, dev
On 3/28/2019 7:27 PM, Trahe, Fiona wrote:
>
>> -----Original Message-----
>> From: Kusztal, ArkadiuszX
>> Sent: Thursday, March 28, 2019 1:37 PM
>> To: dev@dpdk.org
>> Cc: akhil.goyal@nxp.com; Trahe, Fiona <fiona.trahe@intel.com>; Kusztal, ArkadiuszX
>> <arkadiuszx.kusztal@intel.com>
>> Subject: [PATCH v5 0/4] Add PMD for asymmetric cryptography operations using Intel QuickAssist
>> Technology devices
>>
>> This patchset adds Poll Mode Driver to use asymmetric cryptography
>> functions using Intel QuickAssist Techology devices.
>>
>> Following functions are available with this patchset:
>> * Modular Exponentiation
>> * Modular Inverse
>>
>> This patch depends on a QAT PF driver for device initialization. See
>> the file docs/guides/cryptodevs/qat.rst for configuration details.
>>
>> Limitations:
>> * Maximum parameter size: 4096 bits
>> - For both modular exponentiaion and modular multiplicative inverse
>>
>> v5:
>> - changed error checks order
>>
>> v4:
>> - fixed yet more checkpatch issues
>>
>> v3:
>> - fixed some checkpatch issues
>>
>> v2:
>> - added Meson build
>> - fixed segfault on cookie
>> - fixed mod inverse problem
>>
>> Arek Kusztal (4):
>> common/qat: add headers for asymmetric crypto
>> crypto/qat: add asymmetric cryptography PMD
>> crypto/qat: add modular exponentiation to qat asym pmd
>> crypto/qat: add modular inverse to qat asym pmd
> Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply [flat|nested] 18+ messages in thread