From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
"Kiran Kumar K" <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>
Cc: <dev@dpdk.org>
Subject: [PATCH 02/20] common/cnxk: realloc inline device XAQ AURA
Date: Mon, 7 Feb 2022 12:59:14 +0530 [thread overview]
Message-ID: <20220207072932.22409-2-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20220207072932.22409-1-ndabilpuram@marvell.com>
Add support to realloc inline device XAQ AURA with more
buffers of new packet pool AURA.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
drivers/common/cnxk/roc_nix_inl.h | 1 +
drivers/common/cnxk/roc_nix_inl_dev.c | 110 +++++++++++++++++++++++++++++-
drivers/common/cnxk/roc_nix_inl_dev_irq.c | 2 +-
drivers/common/cnxk/roc_nix_inl_priv.h | 3 +
drivers/common/cnxk/roc_platform.h | 1 +
drivers/common/cnxk/version.map | 3 +-
6 files changed, 115 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index abbeac6..bbdcbc8 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -124,6 +124,7 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);
bool __roc_api roc_nix_inl_dev_is_probed(void);
void __roc_api roc_nix_inl_dev_lock(void);
void __roc_api roc_nix_inl_dev_unlock(void);
+int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
/* NIX Inline Inbound API */
int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index dd93765..1d14f04 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -219,7 +219,6 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
struct sso_lf_alloc_rsp *sso_rsp;
struct dev *dev = &inl_dev->dev;
uint16_t hwgrp[1] = {0};
- uint32_t xae_cnt;
int rc;
/* Alloc SSOW LF */
@@ -240,8 +239,8 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
inl_dev->xae_waes = sso_rsp->xaq_wq_entries;
inl_dev->iue = sso_rsp->in_unit_entries;
- xae_cnt = inl_dev->iue;
- rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, xae_cnt,
+ inl_dev->nb_xae = inl_dev->iue;
+ rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, inl_dev->nb_xae,
inl_dev->xae_waes, inl_dev->xaq_buf_size,
1);
if (rc) {
@@ -518,6 +517,111 @@ nix_inl_lf_detach(struct nix_inl_dev *inl_dev)
return mbox_process(dev->mbox);
}
+static int
+nix_inl_dev_wait_for_sso_empty(struct nix_inl_dev *inl_dev)
+{
+ uintptr_t sso_base = inl_dev->sso_base;
+ int wait_ms = 3000;
+
+ while (wait_ms > 0) {
+ /* Break when empty */
+ if (!plt_read64(sso_base + SSO_LF_GGRP_XAQ_CNT) &&
+ !plt_read64(sso_base + SSO_LF_GGRP_AQ_CNT))
+ return 0;
+
+ plt_delay_us(1000);
+ wait_ms -= 1;
+ }
+
+ return -ETIMEDOUT;
+}
+
+int
+roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)
+{
+ struct idev_cfg *idev = idev_get_cfg();
+ struct nix_inl_dev *inl_dev;
+ int rc, i;
+
+ if (idev == NULL)
+ return 0;
+
+ inl_dev = idev->nix_inl_dev;
+ /* Nothing to do if no inline device */
+ if (!inl_dev)
+ return 0;
+
+ if (!aura_handle) {
+ inl_dev->nb_xae = inl_dev->iue;
+ goto no_pool;
+ }
+
+ /* Check if aura is already considered */
+ for (i = 0; i < inl_dev->pkt_pools_cnt; i++) {
+ if (inl_dev->pkt_pools[i] == aura_handle)
+ return 0;
+ }
+
+no_pool:
+ /* Disable RQ if enabled */
+ if (inl_dev->rq_refs) {
+ rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, false);
+ if (rc) {
+ plt_err("Failed to disable inline dev RQ, rc=%d", rc);
+ return rc;
+ }
+ }
+
+ /* Wait for events to be removed */
+ rc = nix_inl_dev_wait_for_sso_empty(inl_dev);
+ if (rc) {
+ plt_err("Timeout waiting for inline device event cleanup");
+ goto exit;
+ }
+
+ /* Disable HWGRP */
+ plt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+ inl_dev->pkt_pools_cnt++;
+ inl_dev->pkt_pools =
+ plt_realloc(inl_dev->pkt_pools,
+ sizeof(uint64_t *) * inl_dev->pkt_pools_cnt, 0);
+ if (!inl_dev->pkt_pools)
+ inl_dev->pkt_pools_cnt = 0;
+ else
+ inl_dev->pkt_pools[inl_dev->pkt_pools_cnt - 1] = aura_handle;
+ inl_dev->nb_xae += roc_npa_aura_op_limit_get(aura_handle);
+
+ /* Realloc XAQ aura */
+ rc = sso_hwgrp_init_xaq_aura(&inl_dev->dev, &inl_dev->xaq,
+ inl_dev->nb_xae, inl_dev->xae_waes,
+ inl_dev->xaq_buf_size, 1);
+ if (rc) {
+ plt_err("Failed to reinitialize xaq aura, rc=%d", rc);
+ return rc;
+ }
+
+ /* Setup xaq for hwgrps */
+ rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1);
+ if (rc) {
+ plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc);
+ return rc;
+ }
+
+ /* Enable HWGRP */
+ plt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+exit:
+ /* Renable RQ */
+ if (inl_dev->rq_refs) {
+ rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, true);
+ if (rc)
+ plt_err("Failed to enable inline dev RQ, rc=%d", rc);
+ }
+
+ return rc;
+}
+
int
roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
{
diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index 848523b..d758e0c 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -72,7 +72,7 @@ nix_inl_sso_hwgrp_irq(void *param)
if (intr & BIT(1))
nix_inl_sso_work_cb(inl_dev);
- if (!(intr & BIT(1)))
+ if (intr & ~BIT(1))
plt_err("GGRP 0 GGRP_INT=0x%" PRIx64 "", intr);
/* Clear interrupt */
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 2cdab6dc..17df23f 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -27,9 +27,12 @@ struct nix_inl_dev {
uint32_t xaq_buf_size;
uint32_t xae_waes;
uint32_t iue;
+ uint32_t nb_xae;
struct roc_sso_xaq_data xaq;
roc_nix_inl_sso_work_cb_t work_cb;
void *cb_args;
+ uint64_t *pkt_pools;
+ uint16_t pkt_pools_cnt;
/* NIX data */
uint8_t lf_tx_stats;
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index c35a2b1..8eac24f 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -147,6 +147,7 @@
#define plt_intr_handle rte_intr_handle
#define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
+#define plt_realloc rte_realloc
#define plt_free rte_free
#define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 82b9fc1..617364f 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -132,11 +132,12 @@ INTERNAL {
roc_nix_inl_dev_init;
roc_nix_inl_dev_is_probed;
roc_nix_inl_dev_lock;
- roc_nix_inl_dev_unlock;
roc_nix_inl_dev_rq;
roc_nix_inl_dev_rq_get;
roc_nix_inl_dev_rq_put;
roc_nix_inl_dev_rq_limit_get;
+ roc_nix_inl_dev_unlock;
+ roc_nix_inl_dev_xaq_realloc;
roc_nix_inl_inb_is_enabled;
roc_nix_inl_inb_init;
roc_nix_inl_inb_sa_base_get;
--
2.8.4
next prev parent reply other threads:[~2022-02-07 7:30 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 7:29 [PATCH 01/20] common/cnxk: increase resource count for bitmap alloc Nithin Dabilpuram
2022-02-07 7:29 ` Nithin Dabilpuram [this message]
2022-02-07 7:29 ` [PATCH 03/20] common/cnxk: adjust shaper rates to lower boundaries Nithin Dabilpuram
2022-02-17 13:20 ` Jerin Jacob
2022-02-22 18:19 ` Nithin Kumar Dabilpuram
2022-02-22 18:21 ` Jerin Jacob
2022-02-07 7:29 ` [PATCH 04/20] common/cnxk: support inline device API without ROC NIX Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 05/20] common/cnxk: use common SA init API for default options Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 06/20] common/cnxk: enable l3hdr write back in SA Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 07/20] common/cnxk: support to enable aura tail drop for RQ Nithin Dabilpuram
2022-02-17 13:24 ` Jerin Jacob
2022-02-07 7:29 ` [PATCH 08/20] common/cnxk: use SSO time counter threshold for IRQ Nithin Dabilpuram
2022-02-17 13:25 ` Jerin Jacob
2022-02-07 7:29 ` [PATCH 09/20] common/cnxk: allow force use of SSO pffunc for outb inline Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 10/20] net/cnxk: added Rx metadata negotiate operation Nithin Dabilpuram
2022-02-17 13:33 ` Jerin Jacob
2022-02-22 18:31 ` Nithin Kumar Dabilpuram
2022-02-07 7:29 ` [PATCH 11/20] common/cnxk: removed tracking of mark actions Nithin Dabilpuram
2022-02-17 13:36 ` Jerin Jacob
2022-02-07 7:29 ` [PATCH 12/20] net/cnxk: fix inline device RQ tag mask Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 13/20] net/cnxk: register callback early to handle initial packets Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 14/20] net/cnxk: realloc inline dev XAQ for security Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 15/20] net/cnxk: use raw mbuf free on inline sec err Nithin Dabilpuram
2022-02-17 13:45 ` Jerin Jacob
2022-02-07 7:29 ` [PATCH 16/20] net/cnxk: use NPA batch burst free for meta buffers Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 17/20] net/cnxk: enable packet pool tail drop Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 18/20] net/cnxk: enable flow control by default on device configure Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 19/20] net/cnxk: add dev args for min-max spi Nithin Dabilpuram
2022-02-07 7:29 ` [PATCH 20/20] net/cnxk: add option to override outbound inline sa iv Nithin Dabilpuram
2022-02-17 13:54 ` Jerin Jacob
2022-02-17 13:11 ` [PATCH 01/20] common/cnxk: increase resource count for bitmap alloc Jerin Jacob
2022-02-17 13:13 ` Jerin Jacob
2022-02-22 19:34 ` [PATCH v2 01/21] common/cnxk: increase SMQ resource count Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 02/21] common/cnxk: realloc inline device XAQ AURA Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 03/21] common/cnxk: adjust shaper rates to lower boundaries Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 04/21] common/cnxk: support inline device API without ROC NIX Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 05/21] common/cnxk: use common SA init API for default options Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 06/21] common/cnxk: enable l3hdr write back in SA Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 07/21] common/cnxk: support to enable AURA tail drop for RQ Nithin Dabilpuram
2022-02-22 19:34 ` [PATCH v2 08/21] common/cnxk: use SSO time counter threshold for IRQ Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 09/21] common/cnxk: allow force use of SSO pffunc for outb inline Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 10/21] net/cnxk: added Rx metadata negotiate operation Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 11/21] common/cnxk: remove tracking of mark actions Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 12/21] net/cnxk: fix inline device RQ tag mask Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 13/21] net/cnxk: register callback early to handle initial packets Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 14/21] net/cnxk: realloc inline dev XAQ for security Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 15/21] net/cnxk: fix inline IPsec security error handling Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 16/21] net/cnxk: use NPA batch burst free for meta buffers Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 17/21] net/cnxk: enable packet pool tail drop Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 18/21] net/cnxk: enable flow control by default on device configure Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 19/21] net/cnxk: add dev args for min-max spi Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 20/21] net/cnxk: add option to override outbound inline SA IV Nithin Dabilpuram
2022-02-22 19:35 ` [PATCH v2 21/21] doc: add table for environment variables used by cnxk Nithin Dabilpuram
2022-02-26 9:22 ` Thomas Monjalon
2022-02-26 9:37 ` Jerin Jacob
2022-02-26 13:31 ` Thomas Monjalon
2022-02-23 16:45 ` [PATCH v2 01/21] common/cnxk: increase SMQ resource count Jerin Jacob
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