From: Min Zhou <zhoumin@loongson.cn>
To: thomas@monjalon.net, david.marchand@redhat.com,
bruce.richardson@intel.com, anatoly.burakov@intel.com,
qiming.yang@intel.com, Yuying.Zhang@intel.com,
jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru
Cc: dev@dpdk.org, maobibo@loongson.cn
Subject: [v1 19/24] lpm: add dummy vector implementation for LoongArch
Date: Sat, 28 May 2022 17:33:06 +0800 [thread overview]
Message-ID: <20220528093311.123946-20-zhoumin@loongson.cn> (raw)
In-Reply-To: <20220528093311.123946-1-zhoumin@loongson.cn>
The hardware instructions based vector implementation will come
in a future patch. This dummy implementation can also work.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
app/test/test_xmmt_ops.h | 17 ++++++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_lsx.h | 129 +++++++++++++++++++++++++++++++++++++++
4 files changed, 149 insertions(+)
create mode 100644 lib/lpm/rte_lpm_lsx.h
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 3a82d5ecac..7b2c3c37dd 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -49,6 +49,23 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
return data;
}
+#elif defined(RTE_ARCH_LOONGARCH)
+/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
+static __rte_always_inline xmm_t
+vect_loadu_sil128(void *p)
+{
+ xmm_t data;
+ data = *(const xmm_t *)p;
+ return data;
+}
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3} };
+ return data;
+}
#endif
#endif /* _TEST_XMMT_OPS_H_ */
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..66df44b9b4 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -16,6 +16,7 @@ indirect_headers += files(
'rte_lpm_neon.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
+ 'rte_lpm_lsx.h',
)
deps += ['hash']
deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..7e94821212 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,6 +405,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
+#elif defined(RTE_ARCH_LOONGARCH)
+#include "rte_lpm_lsx.h"
#else
#include "rte_lpm_sse.h"
#endif
diff --git a/lib/lpm/rte_lpm_lsx.h b/lib/lpm/rte_lpm_lsx.h
new file mode 100644
index 0000000000..07942571e7
--- /dev/null
+++ b/lib/lpm/rte_lpm_lsx.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_LPM_LSX_H_
+#define _RTE_LPM_LSX_H_
+
+#include <rte_branch_prediction.h>
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_vect.h>
+#include <rte_lpm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef RTE_ARCH_NO_VECTOR
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ xmm_t i24;
+ rte_xmm_t i8;
+ uint32_t tbl[4];
+ uint64_t idx, pt, pt2;
+ const uint32_t *ptbl;
+ int i;
+
+ const uint32_t mask = UINT8_MAX;
+ xmm_t mask8_tmp = (xmm_t){.u32 = {mask, mask, mask, mask} };
+
+ const xmm_t mask8 = mask8_tmp;
+
+ /*
+ * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
+ * as one 64-bit value (0x0300000003000000).
+ */
+ const uint64_t mask_xv =
+ ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
+ (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
+
+ /*
+ * RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
+ * as one 64-bit value (0x0100000001000000).
+ */
+ const uint64_t mask_v =
+ ((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
+ (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
+
+ /* get 4 indexes for tbl24[]. */
+ for (i = 0; i < 4; i++)
+ i24.u32[i] = ip.u32[i] >> CHAR_BIT;
+
+ /* extract values from tbl24[] */
+ idx = i24.i64[0];
+
+ ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx];
+ tbl[0] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32];
+ tbl[1] = *ptbl;
+
+ idx = i24.i64[1];
+
+ ptbl = (const uint32_t *)&lpm->tbl24[(uint32_t)idx];
+ tbl[2] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[idx >> 32];
+ tbl[3] = *ptbl;
+
+ /* get 4 indexes for tbl8[]. */
+ for (i = 0; i < 2; i++)
+ i8.x.u64[i] = ip.u64[i] & mask8.u64[i];
+
+ pt = (uint64_t)tbl[0] |
+ (uint64_t)tbl[1] << 32;
+ pt2 = (uint64_t)tbl[2] |
+ (uint64_t)tbl[3] << 32;
+
+ /* search successfully finished for all 4 IP addresses. */
+ if (likely((pt & mask_xv) == mask_v) &&
+ likely((pt2 & mask_xv) == mask_v)) {
+ *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
+ *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
+ return;
+ }
+
+ if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+ i8.u32[0] = i8.u32[0] +
+ (tbl[0] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+ ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]];
+ tbl[0] = *ptbl;
+ }
+ if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+ i8.u32[1] = i8.u32[1] +
+ (tbl[1] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+ ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]];
+ tbl[1] = *ptbl;
+ }
+ if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+ i8.u32[2] = i8.u32[2] +
+ (tbl[2] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+ ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]];
+ tbl[2] = *ptbl;
+ }
+ if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+ i8.u32[3] = i8.u32[3] +
+ (tbl[3] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+ ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]];
+ tbl[3] = *ptbl;
+ }
+
+ hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv;
+ hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv;
+ hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv;
+ hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv;
+}
+#else
+#error "The current version of LoongArch does not support vector!"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_LSX_H_ */
--
2.31.1
next prev parent reply other threads:[~2022-05-28 9:35 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-28 9:32 [v1 00/24] Support LoongArch architecture Min Zhou
2022-05-28 9:32 ` [v1 01/24] eal/loongarch: add atomic operations for LoongArch Min Zhou
2022-05-28 15:52 ` Stephen Hemminger
2022-05-30 1:00 ` zhoumin
2022-05-28 9:32 ` [v1 02/24] eal/loongarch: add byte order " Min Zhou
2022-05-28 9:32 ` [v1 03/24] eal/loongarch: add cpu cycle " Min Zhou
2022-05-28 9:32 ` [v1 04/24] eal/loongarch: add prefetch " Min Zhou
2022-05-28 9:32 ` [v1 05/24] eal/loongarch: add spinlock " Min Zhou
2022-05-28 15:54 ` Stephen Hemminger
2022-05-30 1:09 ` zhoumin
2022-05-28 9:32 ` [v1 06/24] eal/loongarch: add cpu flag checks " Min Zhou
2022-05-28 9:32 ` [v1 07/24] eal/loongarch: add dummy vector memcpy " Min Zhou
2022-05-28 9:32 ` [v1 08/24] eal/loongarch: add io operations " Min Zhou
2022-05-28 9:32 ` [v1 09/24] eal/loongarch: add mcslock " Min Zhou
2022-05-28 9:32 ` [v1 10/24] eal/loongarch: add pause " Min Zhou
2022-05-28 9:32 ` [v1 11/24] eal/loongarch: add pflock " Min Zhou
2022-05-28 9:32 ` [v1 12/24] eal/loongarch: add rwlock " Min Zhou
2022-05-28 9:33 ` [v1 13/24] eal/loongarch: add ticketlock " Min Zhou
2022-05-28 9:33 ` [v1 14/24] eal/loongarch: add power " Min Zhou
2022-05-28 9:33 ` [v1 15/24] eal/loongarch: add hypervisor " Min Zhou
2022-05-28 9:33 ` [v1 16/24] mem: add huge page size definition " Min Zhou
2022-05-28 9:33 ` [v1 17/24] eal/linux: set eal base address " Min Zhou
2022-05-28 9:33 ` [v1 18/24] meson: introduce LoongArch architecture Min Zhou
2022-05-28 9:33 ` Min Zhou [this message]
2022-05-28 9:33 ` [v1 20/24] ixgbe: add dummy vector implementation for LoongArch Min Zhou
2022-05-28 9:33 ` [v1 21/24] i40e: " Min Zhou
2022-05-28 9:33 ` [v1 22/24] tap: add system call number " Min Zhou
2022-05-28 9:33 ` [v1 23/24] memif: " Min Zhou
2022-05-28 9:33 ` [v1 24/24] maintainers: claim responsibility " Min Zhou
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