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From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
	Kiran Kumar K <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, <dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>
Subject: [PATCH 01/23] common/cnxk: fix part value for cn10k
Date: Wed, 10 Aug 2022 00:18:45 +0530	[thread overview]
Message-ID: <20220809184908.24030-1-ndabilpuram@marvell.com> (raw)

From: Harman Kalra <hkalra@marvell.com>

Updating the logic for getting part and pass value for cn10k family,
as device tree compatible logic does not work in VMs.
Scanning all the PCI device and detect first RVU device, subsystem
device file gives part no and revision file provide pass information.

Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API")

Signed-off-by: Harman Kalra <hkalra@marvell.com>
---

Depends-on: series-23650("[v2] event/cnxk: add eth port specific PTP enable")
Depends-on: series-24029("[1/4] cnxk/net: add fc check in vector event Tx path")

 drivers/common/cnxk/roc_model.c    | 152 +++++++++++++++++++++++++++----------
 drivers/common/cnxk/roc_platform.h |   3 +
 2 files changed, 113 insertions(+), 42 deletions(-)

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index a68baa6..791ffa6 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -2,6 +2,7 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include <dirent.h>
 #include <fcntl.h>
 #include <unistd.h>
 
@@ -40,6 +41,16 @@ struct roc_model *roc_model;
 #define MODEL_MINOR_SHIFT 0
 #define MODEL_MINOR_MASK  ((1 << MODEL_MINOR_BITS) - 1)
 
+#define MODEL_CN10K_PART_SHIFT	8
+#define MODEL_CN10K_PASS_BITS	4
+#define MODEL_CN10K_PASS_MASK	((1 << MODEL_CN10K_PASS_BITS) - 1)
+#define MODEL_CN10K_MAJOR_BITS	2
+#define MODEL_CN10K_MAJOR_SHIFT 2
+#define MODEL_CN10K_MAJOR_MASK	((1 << MODEL_CN10K_MAJOR_BITS) - 1)
+#define MODEL_CN10K_MINOR_BITS	2
+#define MODEL_CN10K_MINOR_SHIFT 0
+#define MODEL_CN10K_MINOR_MASK	((1 << MODEL_CN10K_MINOR_BITS) - 1)
+
 static const struct model_db {
 	uint32_t impl;
 	uint32_t part;
@@ -66,55 +77,101 @@ static const struct model_db {
 	{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
 	 "cnf95xxmm_a0"}};
 
-static uint32_t
-cn10k_part_get(void)
+/* Detect if RVU device */
+static bool
+is_rvu_device(unsigned long val)
 {
-	uint32_t soc = 0x0;
-	char buf[BUFSIZ];
-	char *ptr;
-	FILE *fd;
-
-	/* Read the CPU compatible variant */
-	fd = fopen("/proc/device-tree/compatible", "r");
-	if (!fd) {
-		plt_err("Failed to open /proc/device-tree/compatible");
-		goto err;
-	}
+	return (val == PCI_DEVID_CNXK_RVU_PF || val == PCI_DEVID_CNXK_RVU_VF ||
+		val == PCI_DEVID_CNXK_RVU_AF ||
+		val == PCI_DEVID_CNXK_RVU_AF_VF ||
+		val == PCI_DEVID_CNXK_RVU_NPA_PF ||
+		val == PCI_DEVID_CNXK_RVU_NPA_VF ||
+		val == PCI_DEVID_CNXK_RVU_SSO_TIM_PF ||
+		val == PCI_DEVID_CNXK_RVU_SSO_TIM_VF ||
+		val == PCI_DEVID_CN10K_RVU_CPT_PF ||
+		val == PCI_DEVID_CN10K_RVU_CPT_VF);
+}
 
-	if (fgets(buf, sizeof(buf), fd) == NULL) {
-		plt_err("Failed to read from /proc/device-tree/compatible");
-		goto fclose;
-	}
-	ptr = strchr(buf, ',');
-	if (!ptr) {
-		plt_err("Malformed 'CPU compatible': <%s>", buf);
-		goto fclose;
-	}
-	ptr++;
-	if (strcmp("cn10ka", ptr) == 0) {
-		soc = PART_106xx;
-	} else if (strcmp("cnf10ka", ptr) == 0) {
-		soc = PART_105xx;
-	} else if (strcmp("cnf10kb", ptr) == 0) {
-		soc = PART_105xxN;
-	} else if (strcmp("cn10kb", ptr) == 0) {
-		soc = PART_103xx;
-	} else {
-		plt_err("Unidentified 'CPU compatible': <%s>", ptr);
-		goto fclose;
+static int
+rvu_device_lookup(const char *dirname, uint32_t *part, uint32_t *pass)
+{
+	char filename[PATH_MAX];
+	unsigned long val;
+
+	/* Check if vendor id is cavium */
+	snprintf(filename, sizeof(filename), "%s/vendor", dirname);
+	if (plt_sysfs_value_parse(filename, &val) < 0)
+		goto error;
+
+	if (val != PCI_VENDOR_ID_CAVIUM)
+		goto error;
+
+	/* Get device id  */
+	snprintf(filename, sizeof(filename), "%s/device", dirname);
+	if (plt_sysfs_value_parse(filename, &val) < 0)
+		goto error;
+
+	/* Check if device ID belongs to any RVU device */
+	if (!is_rvu_device(val))
+		goto error;
+
+	/* Get subsystem_device id */
+	snprintf(filename, sizeof(filename), "%s/subsystem_device", dirname);
+	if (plt_sysfs_value_parse(filename, &val) < 0)
+		goto error;
+
+	*part = val >> MODEL_CN10K_PART_SHIFT;
+
+	/* Get revision for pass value*/
+	snprintf(filename, sizeof(filename), "%s/revision", dirname);
+	if (plt_sysfs_value_parse(filename, &val) < 0)
+		goto error;
+
+	*pass = val & MODEL_CN10K_PASS_MASK;
+
+	return 0;
+error:
+	return -EINVAL;
+}
+
+/* Scans through all PCI devices, detects RVU device and returns
+ * subsystem_device
+ */
+static int
+cn10k_part_pass_get(uint32_t *part, uint32_t *pass)
+{
+#define SYSFS_PCI_DEVICES "/sys/bus/pci/devices"
+	char dirname[PATH_MAX];
+	struct dirent *e;
+	DIR *dir;
+
+	dir = opendir(SYSFS_PCI_DEVICES);
+	if (dir == NULL) {
+		plt_err("%s(): opendir failed: %s\n", __func__,
+			strerror(errno));
+		return -errno;
 	}
 
-fclose:
-	fclose(fd);
+	while ((e = readdir(dir)) != NULL) {
+		if (e->d_name[0] == '.')
+			continue;
+
+		snprintf(dirname, sizeof(dirname), "%s/%s", SYSFS_PCI_DEVICES,
+			 e->d_name);
+
+		/* Lookup for rvu device and get part pass information */
+		if (!rvu_device_lookup(dirname, part, pass))
+			break;
+	}
 
-err:
-	return soc;
+	closedir(dir);
+	return 0;
 }
 
 static bool
 populate_model(struct roc_model *model, uint32_t midr)
 {
-	uint32_t impl, major, part, minor;
+	uint32_t impl, major, part, minor, pass;
 	bool found = false;
 	size_t i;
 
@@ -124,8 +181,19 @@ populate_model(struct roc_model *model, uint32_t midr)
 	minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK;
 
 	/* Update part number for cn10k from device-tree */
-	if (part == SOC_PART_CN10K)
-		part = cn10k_part_get();
+	if (part == SOC_PART_CN10K) {
+		if (cn10k_part_pass_get(&part, &pass))
+			goto not_found;
+		/*
+		 * Pass value format:
+		 * Bits 0..1: minor pass
+		 * Bits 3..2: major pass
+		 */
+		minor = (pass >> MODEL_CN10K_MINOR_SHIFT) &
+			MODEL_CN10K_MINOR_MASK;
+		major = (pass >> MODEL_CN10K_MAJOR_SHIFT) &
+			MODEL_CN10K_MAJOR_MASK;
+	}
 
 	for (i = 0; i < PLT_DIM(model_db); i++)
 		if (model_db[i].impl == impl && model_db[i].part == part &&
@@ -136,7 +204,7 @@ populate_model(struct roc_model *model, uint32_t midr)
 			found = true;
 			break;
 		}
-
+not_found:
 	if (!found) {
 		model->flag = 0;
 		strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 502f243..3e7adfc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -24,6 +24,8 @@
 #include <rte_tailq.h>
 #include <rte_telemetry.h>
 
+#include "eal_filesystem.h"
+
 #include "roc_bits.h"
 
 #if defined(__ARM_FEATURE_SVE)
@@ -94,6 +96,7 @@
 #define plt_pci_device		    rte_pci_device
 #define plt_pci_read_config	    rte_pci_read_config
 #define plt_pci_find_ext_capability rte_pci_find_ext_capability
+#define plt_sysfs_value_parse	    eal_parse_sysfs_value
 
 #define plt_log2_u32	 rte_log2_u32
 #define plt_cpu_to_be_16 rte_cpu_to_be_16
-- 
2.8.4


             reply	other threads:[~2022-08-09 18:49 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-09 18:48 Nithin Dabilpuram [this message]
2022-08-09 18:48 ` [PATCH 02/23] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 03/23] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 04/23] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 06/23] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 07/23] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 08/23] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 09/23] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 10/23] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 11/23] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 12/23] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 13/23] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 14/23] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-08-09 18:48 ` [PATCH 15/23] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 16/23] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 17/23] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 18/23] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 19/23] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 20/23] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 21/23] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 22/23] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-08-09 18:49 ` [PATCH 23/23] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-08-30  4:51 ` [PATCH 01/23] common/cnxk: fix part value for cn10k Jerin Jacob
2022-08-30  5:16   ` [EXT] " Nithin Kumar Dabilpuram
2022-09-05 13:31 ` [PATCH v2 01/31] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-05 13:31   ` [PATCH v2 02/31] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 03/31] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 04/31] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 05/31] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 06/31] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 07/31] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 08/31] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 09/31] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 10/31] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 11/31] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 12/31] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 13/31] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 14/31] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 16/31] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 17/31] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 18/31] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 19/31] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 20/31] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 21/31] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 22/31] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 23/31] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 24/31] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 25/31] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 26/31] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 27/31] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 28/31] net/cnxk: Add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 29/31] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 30/31] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-05 13:32   ` [PATCH v2 31/31] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-12 13:13 ` [PATCH v3 01/32] net/cnxk: add eth port specific PTP enable Nithin Dabilpuram
2022-09-12 13:13   ` [PATCH v3 02/32] cnxk/net: add fc check in vector event Tx path Nithin Dabilpuram
2022-09-12 13:13   ` [PATCH v3 03/32] common/cnxk: fix part value for cn10k Nithin Dabilpuram
2022-09-12 13:13   ` [PATCH v3 04/32] common/cnxk: add cn10ka A1 platform Nithin Dabilpuram
2022-09-12 13:13   ` [PATCH v3 05/32] common/cnxk: update inbound inline IPsec config mailbox Nithin Dabilpuram
2022-09-12 13:13   ` [PATCH v3 06/32] net/cnxk: fix missing fc wait for outbound path in vec mode Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 07/32] common/cnxk: limit meta aura workaround to CN10K A0 Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 08/32] common/cnxk: delay inline device RQ enable to dev start Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 09/32] common/cnxk: reserve aura zero on cn10ka NPA Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 10/32] common/cnxk: add support to set NPA buf type Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 11/32] common/cnxk: update attributes to pools used by NIX Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 12/32] common/cnxk: support zero aura for inline inbound meta Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 13/32] net/cnxk: support for zero aura for inline meta Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 14/32] common/cnxk: avoid the use of platform specific APIs Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 15/32] net/cnxk: use full context IPsec structures in fp Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 16/32] net/cnxk: add crypto capabilities for HMAC-SHA2 Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 17/32] common/cnxk: enable aging on CN10K platform Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 18/32] common/cnxk: updated shaper profile with red algorithm Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 19/32] common/cnxk: add 98xx A1 platform Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 20/32] net/cnxk: enable additional ciphers for inline Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 21/32] net/cnxk: enable 3des-cbc cipher capability Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 22/32] net/cnxk: skip PFC configuration on LBK Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 23/32] common/cnxk: add support for CPT second pass Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 24/32] common/cnxk: add CQ limit associated with SQ Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 25/32] common/cnxk: support Tx compl event via RQ to CQ mapping Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 26/32] event/cnxk: wait for CPT fc on wqe path Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 27/32] net/cnxk: limit port specific SA table size Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 28/32] net/cnxk: add support for crypto cipher DES-CBC Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 29/32] net/cnxk: add support for crypto auth alg MD5 Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 30/32] net/cnxk: enable esn and antireplay support Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 31/32] common/cnxk: dump device basic info to file Nithin Dabilpuram
2022-09-12 13:14   ` [PATCH v3 32/32] net/cnxk: dumps device private information Nithin Dabilpuram
2022-09-16 11:36     ` Jerin Jacob

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