From: Leo Xu <yongquanx@nvidia.com>
To: <dev@dpdk.org>
Cc: Shun Hao <shunh@nvidia.com>, Matan Azrad <matan@nvidia.com>,
Shahaf Shuler <shahafs@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Subject: [PATCH 3/3] net/mlx5/hws: add ICMPv6 id and sequence match support
Date: Mon, 12 Dec 2022 10:59:22 +0200 [thread overview]
Message-ID: <20221212085923.2314350-4-yongquanx@nvidia.com> (raw)
In-Reply-To: <20221212085923.2314350-1-yongquanx@nvidia.com>
This patch adds ICMPv6 id and sequence match support for HWS.
Since type and code of ICMPv6 echo is already specified by ITEM type:
RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST
RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY
mlx5 pmd will set appropriate type and code automatically:
Echo request: type(128), code(0)
Echo reply: type(129), code(0)
type and code provided by application will be ignored
This patch also fixes these issues in ICMP definer.
1. Parsing inner ICMP item gets and overwrites the outer IP_PROTOCOL
function, which will remove the outer L4 match incorrectly. Fix this
by getting correct inner function.
2. Member order of mlx5_ifc_header_icmp_bits doesn't follow ICMP format.
Reorder them to make it more consistent.
Signed-off-by: Leo Xu <yongquanx@nvidia.com>
Signed-off-by: Shun Hao <shunh@nvidia.com>
---
drivers/net/mlx5/steering/mlx5dr_definer.c | 110 ++++++++++++++++++---
drivers/net/mlx5/steering/mlx5dr_definer.h | 6 +-
2 files changed, 102 insertions(+), 14 deletions(-)
diff --git a/drivers/net/mlx5/steering/mlx5dr_definer.c b/drivers/net/mlx5/steering/mlx5dr_definer.c
index 9bb0f3b117..96da706ee2 100644
--- a/drivers/net/mlx5/steering/mlx5dr_definer.c
+++ b/drivers/net/mlx5/steering/mlx5dr_definer.c
@@ -316,9 +316,9 @@ mlx5dr_definer_icmp_dw1_set(struct mlx5dr_definer_fc *fc,
icmp_dw1 = (v->hdr.icmp_type << __mlx5_dw_bit_off(header_icmp, type)) |
(v->hdr.icmp_code << __mlx5_dw_bit_off(header_icmp, code)) |
- (v->hdr.icmp_cksum << __mlx5_dw_bit_off(header_icmp, cksum));
+ (rte_be_to_cpu_16(v->hdr.icmp_cksum) << __mlx5_dw_bit_off(header_icmp, cksum));
- DR_SET_BE32(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask);
+ DR_SET(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask);
}
static void
@@ -329,10 +329,10 @@ mlx5dr_definer_icmp_dw2_set(struct mlx5dr_definer_fc *fc,
const struct rte_flow_item_icmp *v = item_spec;
rte_be32_t icmp_dw2;
- icmp_dw2 = (v->hdr.icmp_ident << __mlx5_dw_bit_off(header_icmp, ident)) |
- (v->hdr.icmp_seq_nb << __mlx5_dw_bit_off(header_icmp, seq_nb));
+ icmp_dw2 = (rte_be_to_cpu_16(v->hdr.icmp_ident) << __mlx5_dw_bit_off(header_icmp, ident)) |
+ (rte_be_to_cpu_16(v->hdr.icmp_seq_nb) << __mlx5_dw_bit_off(header_icmp, seq_nb));
- DR_SET_BE32(tag, icmp_dw2, fc->byte_off, fc->bit_off, fc->bit_mask);
+ DR_SET(tag, icmp_dw2, fc->byte_off, fc->bit_off, fc->bit_mask);
}
static void
@@ -345,9 +345,50 @@ mlx5dr_definer_icmp6_dw1_set(struct mlx5dr_definer_fc *fc,
icmp_dw1 = (v->type << __mlx5_dw_bit_off(header_icmp, type)) |
(v->code << __mlx5_dw_bit_off(header_icmp, code)) |
- (v->checksum << __mlx5_dw_bit_off(header_icmp, cksum));
+ (rte_be_to_cpu_16(v->checksum) << __mlx5_dw_bit_off(header_icmp, cksum));
- DR_SET_BE32(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask);
+ DR_SET(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
+static void
+mlx5dr_definer_icmp6_echo_dw1_mask_set(struct mlx5dr_definer_fc *fc,
+ __rte_unused const void *item_spec,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_icmp6 spec = {0xFF, 0xFF, 0x0};
+ mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);
+}
+
+static void
+mlx5dr_definer_icmp6_echo_request_dw1_set(struct mlx5dr_definer_fc *fc,
+ __rte_unused const void *item_spec,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REQUEST, 0, 0};
+ mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);
+}
+
+static void
+mlx5dr_definer_icmp6_echo_reply_dw1_set(struct mlx5dr_definer_fc *fc,
+ __rte_unused const void *item_spec,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REPLY, 0, 0};
+ mlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);
+}
+
+static void
+mlx5dr_definer_icmp6_echo_dw2_set(struct mlx5dr_definer_fc *fc,
+ const void *item_spec,
+ uint8_t *tag)
+{
+ const struct rte_flow_item_icmp6_echo *v = item_spec;
+ rte_be32_t dw2;
+
+ dw2 = (rte_be_to_cpu_16(v->echo.identifier) << __mlx5_dw_bit_off(header_icmp, ident)) |
+ (rte_be_to_cpu_16(v->echo.sequence) << __mlx5_dw_bit_off(header_icmp, seq_nb));
+
+ DR_SET(tag, dw2, fc->byte_off, fc->bit_off, fc->bit_mask);
}
static void
@@ -1419,9 +1460,9 @@ mlx5dr_definer_conv_item_icmp(struct mlx5dr_definer_conv_data *cd,
struct mlx5dr_definer_fc *fc;
bool inner = cd->tunnel;
- /* Overwrite match on outer L4 type ICMP */
+ /* Overwrite match on L4 type ICMP */
if (!cd->relaxed) {
- fc = &cd->fc[MLX5DR_DEFINER_FNAME_IP_PROTOCOL_O];
+ fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];
fc->item_idx = item_idx;
fc->tag_set = &mlx5dr_definer_icmp_protocol_set;
fc->tag_mask_set = &mlx5dr_definer_ones_set;
@@ -1457,9 +1498,9 @@ mlx5dr_definer_conv_item_icmp6(struct mlx5dr_definer_conv_data *cd,
struct mlx5dr_definer_fc *fc;
bool inner = cd->tunnel;
- /* Overwrite match on outer L4 type ICMP6 */
+ /* Overwrite match on L4 type ICMP6 */
if (!cd->relaxed) {
- fc = &cd->fc[MLX5DR_DEFINER_FNAME_IP_PROTOCOL_O];
+ fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];
fc->item_idx = item_idx;
fc->tag_set = &mlx5dr_definer_icmp_protocol_set;
fc->tag_mask_set = &mlx5dr_definer_ones_set;
@@ -1479,6 +1520,48 @@ mlx5dr_definer_conv_item_icmp6(struct mlx5dr_definer_conv_data *cd,
return 0;
}
+static int
+mlx5dr_definer_conv_item_icmp6_echo(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_icmp6_echo *m = item->mask;
+ struct mlx5dr_definer_fc *fc;
+ bool inner = cd->tunnel;
+
+ if (!cd->relaxed) {
+ /* Overwrite match on L4 type ICMP6 */
+ fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_icmp_protocol_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, l4_type, inner);
+
+ /* Set fixed type and code for icmp6 echo request/reply */
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW1];
+ fc->item_idx = item_idx;
+ fc->tag_mask_set = &mlx5dr_definer_icmp6_echo_dw1_mask_set;
+ if (item->type == RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST)
+ fc->tag_set = &mlx5dr_definer_icmp6_echo_request_dw1_set;
+ else /* RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY */
+ fc->tag_set = &mlx5dr_definer_icmp6_echo_reply_dw1_set;
+ DR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw1);
+ }
+
+ if (!m)
+ return 0;
+
+ /* Set identifier & sequence into icmp_dw2 */
+ if (m->echo.identifier || m->echo.sequence) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW2];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_icmp6_echo_dw2_set;
+ DR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw2);
+ }
+
+ return 0;
+}
+
static int
mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,
struct rte_flow_item *item,
@@ -1615,6 +1698,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
ret = mlx5dr_definer_conv_item_icmp6(&cd, items, i);
item_flags |= MLX5_FLOW_LAYER_ICMP6;
break;
+ case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
+ case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
+ ret = mlx5dr_definer_conv_item_icmp6_echo(&cd, items, i);
+ item_flags |= MLX5_FLOW_LAYER_ICMP6;
+ break;
case RTE_FLOW_ITEM_TYPE_METER_COLOR:
ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
diff --git a/drivers/net/mlx5/steering/mlx5dr_definer.h b/drivers/net/mlx5/steering/mlx5dr_definer.h
index 9bf4bb3c13..b826b4468e 100644
--- a/drivers/net/mlx5/steering/mlx5dr_definer.h
+++ b/drivers/net/mlx5/steering/mlx5dr_definer.h
@@ -536,16 +536,16 @@ struct mlx5_ifc_header_icmp_bits {
union {
u8 icmp_dw1[0x20];
struct {
- u8 cksum[0x10];
- u8 code[0x8];
u8 type[0x8];
+ u8 code[0x8];
+ u8 cksum[0x10];
};
};
union {
u8 icmp_dw2[0x20];
struct {
- u8 seq_nb[0x10];
u8 ident[0x10];
+ u8 seq_nb[0x10];
};
};
};
--
2.27.0
next prev parent reply other threads:[~2022-12-12 9:01 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 8:59 [PATCH 0/3] support match icmpv6 id and sequence Leo Xu
2022-12-12 8:59 ` [PATCH 1/3] ethdev: add ICMPv6 " Leo Xu
2022-12-12 8:59 ` [PATCH 2/3] net/mlx5: add ICMPv6 id and sequence match support Leo Xu
2022-12-12 8:59 ` Leo Xu [this message]
2022-12-20 7:44 ` [PATCH v2 0/3] support match icmpv6 ID and sequence Leo Xu
2022-12-20 7:44 ` [PATCH v2 1/3] ethdev: add ICMPv6 " Leo Xu
2023-01-03 8:17 ` Ori Kam
2023-01-18 9:30 ` Thomas Monjalon
2023-01-31 6:53 ` Leo Xu (Networking SW)
2023-02-01 9:56 ` Thomas Monjalon
2023-02-02 18:33 ` Leo Xu (Networking SW)
2023-02-02 21:23 ` Thomas Monjalon
2023-02-03 2:56 ` Leo Xu (Networking SW)
2023-01-26 10:45 ` Ferruh Yigit
2023-01-31 3:58 ` Leo Xu (Networking SW)
2022-12-20 7:44 ` [PATCH v2 2/3] net/mlx5: add ICMPv6 ID and sequence match support Leo Xu
2023-01-18 8:55 ` Thomas Monjalon
2023-01-31 6:57 ` Leo Xu (Networking SW)
2022-12-20 7:44 ` [PATCH v2 3/3] net/mlx5/hws: " Leo Xu
2023-01-18 8:58 ` Thomas Monjalon
2023-01-31 6:56 ` Leo Xu (Networking SW)
2023-01-26 10:47 ` [PATCH v2 0/3] support match icmpv6 ID and sequence Ferruh Yigit
2023-01-31 3:54 ` Leo Xu (Networking SW)
2023-02-05 13:41 ` [PATCH v3 " Leo Xu
2023-02-05 13:41 ` [PATCH v3 1/3] ethdev: add ICMPv6 " Leo Xu
2023-02-05 13:41 ` [PATCH v3 2/3] net/mlx5: add ICMPv6 ID and sequence match support Leo Xu
2023-02-07 13:48 ` Slava Ovsiienko
2023-02-05 13:41 ` [PATCH v3 3/3] net/mlx5/hws: " Leo Xu
2023-02-07 13:05 ` Alex Vesker
2023-02-07 13:49 ` Slava Ovsiienko
2023-02-09 13:04 ` [PATCH v3 0/3] support match icmpv6 ID and sequence Ferruh Yigit
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