[PATCH 01/31] common/cnxk: add aura ref count mechanism

[PATCH 01/31] common/cnxk: add aura ref count mechanism

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Each RQ can be associated with lpb_aura and spb_aura.
lpb_aura or spb_aura is shared across multiple RQs then
cleanup via one RQ will reset the aura context.

To prevent, adding ref count mechanism.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix_fc.c   | 6 ++++++
 drivers/common/cnxk/roc_npa_priv.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index d8ca5f9996..1f5ef960da 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -537,6 +537,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 					plt_err("Enabling backpressue failed on aura 0x%" PRIx64,
 						pool_id);
 			} else {
+				lf->aura_attr[aura_id].ref_count++;
 				plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64,
 					 roc_nix->port_id, tc, pool_id);
 			}
@@ -552,6 +553,8 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	if (ena) {
 		if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))
 			plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id);
+		else
+			lf->aura_attr[aura_id].ref_count++;
 	} else {
 		bool found = !!force;
 
@@ -561,6 +564,9 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 				found = true;
 		if (!found)
 			return;
+		else if ((lf->aura_attr[aura_id].ref_count > 0) &&
+			 --lf->aura_attr[aura_id].ref_count)
+			return;
 
 		if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))
 			plt_err("Disabling backpressue failed on aura 0x%" PRIx64, pool_id);
diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h
index d2118cc4fb..704d93d5dc 100644
--- a/drivers/common/cnxk/roc_npa_priv.h
+++ b/drivers/common/cnxk/roc_npa_priv.h
@@ -49,6 +49,7 @@ struct npa_aura_lim {
 
 struct npa_aura_attr {
 	int buf_type[ROC_NPA_BUF_TYPE_END];
+	uint16_t ref_count;
 };
 
 struct dev;
-- 
2.25.1

[PATCH 02/31] common/cnxk: optimize time while configuring fc on VF

[Nithin Dabilpuram]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

PFC configuration function is taking 8 ms due
to mailbox communication to check whether sso is
connected to RQ and whether back pressure is enabled
on each aura. To optimize this time we are updating
aura attributes in nixlf and sso_ena parameter
in RQ during write configuration and the same updated
value is accessed while configuring flow control,
reducing time to 6 ms.

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/common/cnxk/roc_nix_fc.c   | 47 ++++++++----------------------
 drivers/common/cnxk/roc_npa.c      | 16 +++++++++-
 drivers/common/cnxk/roc_npa_priv.h |  6 ++++
 3 files changed, 33 insertions(+), 36 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index 1f5ef960da..d58b35268e 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -285,15 +285,11 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
 	struct roc_nix_fc_cfg tmp;
 	uint64_t pool_drop_pct;
 	struct roc_nix_rq *rq;
-	int sso_ena = 0, rc;
+	int rc;
 
 	rq = nix->rqs[fc_cfg->rq_cfg.rq];
-	/* Check whether RQ is connected to SSO or not */
-	sso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq);
-	if (sso_ena < 0)
-		return -EINVAL;
 
-	if (sso_ena) {
+	if (rq->sso_ena) {
 		pool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct;
 		/* Use default value for zero pct */
 		if (fc_cfg->rq_cfg.enable && !pool_drop_pct)
@@ -486,12 +482,10 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	uint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id);
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct npa_lf *lf = idev_npa_obj_get();
-	struct npa_aq_enq_req *req;
-	struct npa_aq_enq_rsp *rsp;
+	struct npa_aura_attr *aura_attr;
 	uint8_t bp_thresh, bp_intf;
-	struct mbox *mbox;
 	uint16_t bpid;
-	int rc, i;
+	int i;
 
 	if (roc_nix_is_sdp(roc_nix))
 		return;
@@ -499,30 +493,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	if (!lf)
 		return;
 
-	mbox = lf->mbox;
-	req = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox));
-	if (req == NULL) {
-		mbox_put(mbox);
-		return;
-	}
-
-	req->aura_id = aura_id;
-	req->ctype = NPA_AQ_CTYPE_AURA;
-	req->op = NPA_AQ_INSTOP_READ;
-
-	rc = mbox_process_msg(mbox, (void *)&rsp);
-	mbox_put(mbox);
-	if (rc) {
-		plt_nix_dbg("Failed to read context of aura 0x%" PRIx64, pool_id);
-		return;
-	}
+	aura_attr = &lf->aura_attr[aura_id];
 
 	bp_intf = 1 << nix->is_nix1;
-	bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift);
+	bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift);
 
-	bpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;
+	bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid;
 	/* BP is already enabled. */
-	if (rsp->aura.bp_ena && ena) {
+	if (aura_attr->bp_ena && ena) {
 		/* Disable BP if BPIDs don't match and couldn't add new BPID. */
 		if (bpid != nix->bpid[tc]) {
 			uint16_t bpid_new = NIX_BPID_INVALID;
@@ -537,7 +515,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 					plt_err("Enabling backpressue failed on aura 0x%" PRIx64,
 						pool_id);
 			} else {
-				lf->aura_attr[aura_id].ref_count++;
+				aura_attr->ref_count++;
 				plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64,
 					 roc_nix->port_id, tc, pool_id);
 			}
@@ -547,14 +525,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	}
 
 	/* BP was previously enabled but now disabled skip. */
-	if (rsp->aura.bp && ena)
+	if (aura_attr->bp && ena)
 		return;
 
 	if (ena) {
 		if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))
 			plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id);
 		else
-			lf->aura_attr[aura_id].ref_count++;
+			aura_attr->ref_count++;
 	} else {
 		bool found = !!force;
 
@@ -564,8 +542,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 				found = true;
 		if (!found)
 			return;
-		else if ((lf->aura_attr[aura_id].ref_count > 0) &&
-			 --lf->aura_attr[aura_id].ref_count)
+		else if ((aura_attr->ref_count > 0) && --(aura_attr->ref_count))
 			return;
 
 		if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 3b9a70028b..d5c3a53b9b 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -535,6 +535,8 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 	if (rc)
 		goto stack_mem_free;
 
+	lf->aura_attr[aura_id].shift = aura->shift;
+	lf->aura_attr[aura_id].limit = aura->limit;
 	*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);
 	/* Update aura count */
 	roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count);
@@ -657,6 +659,8 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id,
 	if (rc)
 		return rc;
 
+	lf->aura_attr[aura_id].shift = aura->shift;
+	lf->aura_attr[aura_id].limit = aura->limit;
 	*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);
 
 	return 0;
@@ -735,6 +739,9 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit)
 	aura_req->aura.limit = aura_limit;
 	aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
 	rc = mbox_process(mbox);
+	if (rc)
+		goto exit;
+	lf->aura_attr[aura_req->aura_id].limit = aura_req->aura.limit;
 exit:
 	mbox_put(mbox);
 	return rc;
@@ -931,7 +938,14 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf,
 	req->aura.bp_ena = bp_intf;
 	req->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);
 
-	mbox_process(mbox);
+	rc = mbox_process(mbox);
+	if (rc)
+		goto fail;
+
+	lf->aura_attr[aura_id].nix0_bpid = req->aura.nix0_bpid;
+	lf->aura_attr[aura_id].nix1_bpid = req->aura.nix1_bpid;
+	lf->aura_attr[aura_id].bp_ena = req->aura.bp_ena;
+	lf->aura_attr[aura_id].bp = req->aura.bp;
 fail:
 	mbox_put(mbox);
 	return rc;
diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h
index 704d93d5dc..060df9ab04 100644
--- a/drivers/common/cnxk/roc_npa_priv.h
+++ b/drivers/common/cnxk/roc_npa_priv.h
@@ -50,6 +50,12 @@ struct npa_aura_lim {
 struct npa_aura_attr {
 	int buf_type[ROC_NPA_BUF_TYPE_END];
 	uint16_t ref_count;
+	uint64_t nix0_bpid;
+	uint64_t nix1_bpid;
+	uint64_t shift;
+	uint64_t limit;
+	uint8_t bp_ena;
+	uint8_t bp;
 };
 
 struct dev;
-- 
2.25.1

[PATCH 03/31] common/cnxk: use only user sqb slack when provided

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

This patch preferred user provided argument while configuring slack.
If no platform argument given then by default MAX(24, 30% of SQ size)
was configured as slack. Currently even if user provided SQB slack,
we take max of internally calculated value and user given one

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix_queue.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 08e8bf7ea2..5e689d08be 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -7,6 +7,9 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+/* Default SQB slack per SQ */
+#define ROC_NIX_SQB_SLACK_DFLT 24
+
 static inline uint32_t
 nix_qsize_to_val(enum nix_q_size qsize)
 {
@@ -1012,7 +1015,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
 	sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);
 	sq->nb_sqb_bufs_adj = nb_sqb_bufs;
 
-	nb_sqb_bufs += PLT_MAX(thr, roc_nix->sqb_slack);
+	if (roc_nix->sqb_slack)
+		nb_sqb_bufs += roc_nix->sqb_slack;
+	else
+		nb_sqb_bufs += PLT_MAX((int)thr, (int)ROC_NIX_SQB_SLACK_DFLT);
 	/* Explicitly set nat_align alone as by default pool is with both
 	 * nat_align and buf_offset = 1 which we don't want for SQB.
 	 */
-- 
2.25.1

[PATCH 04/31] common/cnxk: add workaround for CPT ctx fetch issue

[Nithin Dabilpuram]

Add workaround for CPT context fetch issue in CN10KB
by setting CTX_ILEN to that of CTX_SIZE and enabling
FLR_FLUSH in CPT_LF_CTX_CTL.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c         | 23 ++++++++++++++++++++---
 drivers/common/cnxk/roc_cpt.h         |  2 ++
 drivers/common/cnxk/roc_cpt_priv.h    |  4 ++--
 drivers/common/cnxk/roc_errata.h      |  7 +++++++
 drivers/common/cnxk/roc_ie_ot.h       |  3 +++
 drivers/common/cnxk/roc_mbox.h        |  4 ++++
 drivers/common/cnxk/roc_nix_inl.c     | 14 +++++++++++++-
 drivers/common/cnxk/roc_nix_inl_dev.c | 10 +++++++++-
 8 files changed, 60 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index d235ff51ca..981e85a204 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -331,6 +331,8 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipse
 	req->param2 = cfg->param2;
 	req->opcode = cfg->opcode;
 	req->bpid = cfg->bpid;
+	req->ctx_ilen_valid = cfg->ctx_ilen_valid;
+	req->ctx_ilen = cfg->ctx_ilen;
 
 	rc = mbox_process(mbox);
 exit:
@@ -460,8 +462,8 @@ cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)
 }
 
 int
-cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,
-	      bool inl_dev_sso)
+cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, bool inl_dev_sso,
+	      bool ctx_ilen_valid, uint8_t ctx_ilen)
 {
 	struct cpt_lf_alloc_req_msg *req;
 	struct mbox *mbox = mbox_get(dev->mbox);
@@ -485,6 +487,8 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,
 		req->sso_pf_func = idev_sso_pffunc_get();
 	req->eng_grpmsk = eng_grpmsk;
 	req->blkaddr = blkaddr;
+	req->ctx_ilen_valid = ctx_ilen_valid;
+	req->ctx_ilen = ctx_ilen;
 
 	rc = mbox_process(mbox);
 exit:
@@ -587,6 +591,8 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
 	uint8_t blkaddr[ROC_CPT_MAX_BLKS];
 	struct msix_offset_rsp *rsp;
+	bool ctx_ilen_valid = false;
+	uint16_t ctx_ilen = 0;
 	uint8_t eng_grpmsk;
 	int blknum = 0;
 	int rc, i;
@@ -618,7 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
 		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
 
-	rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false);
+	if (roc_errata_cpt_has_ctx_fetch_issue()) {
+		ctx_ilen_valid = true;
+		/* Inbound SA size is max context size */
+		ctx_ilen = (PLT_ALIGN(ROC_OT_IPSEC_SA_SZ_MAX, ROC_ALIGN) / 128) - 1;
+	}
+
+	rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false, ctx_ilen_valid, ctx_ilen);
 	if (rc)
 		goto lfs_detach;
 
@@ -1108,6 +1120,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf)
 	lf_inprog.s.eena = 1;
 	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
 
+	if (roc_errata_cpt_has_ctx_fetch_issue()) {
+		/* Enable flush on FLR */
+		plt_write64(1, lf->rbase + CPT_LF_CTX_CTL);
+	}
+
 	cpt_lf_dump(lf);
 }
 
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 910bd37a0c..787bccb27d 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -161,6 +161,8 @@ struct roc_cpt_inline_ipsec_inb_cfg {
 	uint16_t bpid;
 	uint32_t credit_th;
 	uint8_t egrp;
+	uint8_t ctx_ilen_valid : 1;
+	uint8_t ctx_ilen : 7;
 };
 
 int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 61dec9a168..4ed87c857b 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -21,8 +21,8 @@ roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)
 int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify,
 		   uint16_t nb_lf);
 int cpt_lfs_detach(struct dev *dev);
-int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,
-		  bool inl_dev_sso);
+int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, bool inl_dev_sso,
+		  bool ctx_ilen_valid, uint8_t ctx_ilen);
 int cpt_lfs_free(struct dev *dev);
 int cpt_lf_init(struct roc_cpt_lf *lf);
 void cpt_lf_fini(struct roc_cpt_lf *lf);
diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h
index 22d2406e94..6f84e06603 100644
--- a/drivers/common/cnxk/roc_errata.h
+++ b/drivers/common/cnxk/roc_errata.h
@@ -82,6 +82,13 @@ roc_errata_cpt_hang_on_x2p_bp(void)
 	return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1();
 }
 
+/* Errata IPBUCPT-38756 */
+static inline bool
+roc_errata_cpt_has_ctx_fetch_issue(void)
+{
+	return roc_model_is_cn10kb();
+}
+
 /* IPBUNIXRX-40400 */
 static inline bool
 roc_errata_nix_no_meta_aura(void)
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index b7fcdf9ba7..af2691e0eb 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -570,6 +570,9 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==
 PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==
 		  31 * sizeof(uint64_t));
 
+#define ROC_OT_IPSEC_SA_SZ_MAX \
+	(PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct roc_ot_ipsec_outb_sa)))
+
 void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,
 					bool is_inline);
 void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 2f85b2f755..f038d3e02b 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2002,6 +2002,8 @@ struct cpt_lf_alloc_req_msg {
 	uint16_t __io sso_pf_func;
 	uint16_t __io eng_grpmsk;
 	uint8_t __io blkaddr;
+	uint8_t __io ctx_ilen_valid : 1;
+	uint8_t __io ctx_ilen : 7;
 };
 
 #define CPT_INLINE_INBOUND  0
@@ -2083,6 +2085,8 @@ struct cpt_rx_inline_lf_cfg_msg {
 	uint32_t __io credit_th;
 	uint16_t __io bpid;
 	uint32_t __io reserved;
+	uint8_t __io ctx_ilen_valid : 1;
+	uint8_t __io ctx_ilen : 7;
 };
 
 struct cpt_caps_rsp_msg {
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 16f858f561..5cb1f11f53 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -851,6 +851,11 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 			nix->cpt_nixbpid = bpids[0];
 			cfg.bpid = nix->cpt_nixbpid;
 		}
+
+		if (roc_errata_cpt_has_ctx_fetch_issue()) {
+			cfg.ctx_ilen_valid = true;
+			cfg.ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1;
+		}
 	}
 
 	/* Do onetime Inbound Inline config in CPTPF */
@@ -931,7 +936,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	struct dev *dev = &nix->dev;
 	struct msix_offset_rsp *rsp;
 	struct nix_inl_dev *inl_dev;
+	bool ctx_ilen_valid = false;
 	size_t sa_sz, ring_sz;
+	uint8_t ctx_ilen = 0;
 	uint16_t sso_pffunc;
 	uint8_t eng_grpmask;
 	uint64_t blkaddr, i;
@@ -967,12 +974,17 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 		return rc;
 	}
 
+	if (!roc_model_is_cn9k() && roc_errata_cpt_has_ctx_fetch_issue()) {
+		ctx_ilen = (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ / 128) - 1;
+		ctx_ilen_valid = true;
+	}
+
 	/* Alloc CPT LF */
 	eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
 	rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
-			   !roc_nix->ipsec_out_sso_pffunc);
+			   !roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid, ctx_ilen);
 	if (rc) {
 		plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
 		goto lf_detach;
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index d76158e30d..2863d5da51 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -176,7 +176,9 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso)
 {
 	struct roc_cpt_lf *lf = &inl_dev->cpt_lf;
 	struct dev *dev = &inl_dev->dev;
+	bool ctx_ilen_valid = false;
 	uint8_t eng_grpmask;
+	uint8_t ctx_ilen = 0;
 	int rc;
 
 	if (!inl_dev->attach_cptlf)
@@ -186,7 +188,13 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso)
 	eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
-	rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso);
+	if (roc_errata_cpt_has_ctx_fetch_issue()) {
+		ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1;
+		ctx_ilen_valid = true;
+	}
+
+	rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso, ctx_ilen_valid,
+			   ctx_ilen);
 	if (rc) {
 		plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
 		return rc;
-- 
2.25.1

[PATCH 05/31] common/cnxk: support rate limit on PFC TM tree

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

New SQ rate limit API to support SQ rate limit on PFC tree.
In PFC tree each SQ had its one to one mapped TL3, this patch
configures shaper rate on TL3. Also configures the TL2 with
link rate.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix.h        |  9 ++-
 drivers/common/cnxk/roc_nix_tm_ops.c | 98 ++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map      |  1 +
 3 files changed, 106 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 9c2ba9a685..1d84f4de9d 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -707,8 +707,13 @@ int __roc_api roc_nix_tm_node_stats_get(struct roc_nix *roc_nix,
 /*
  * TM ratelimit tree API.
  */
-int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid,
-				   uint64_t rate);
+int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate);
+
+/*
+ * TM PFC tree ratelimit API.
+ */
+int __roc_api roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate);
+
 /*
  * TM hierarchy enable/disable API.
  */
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index 4e88ad1beb..e1cef7a670 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -1032,6 +1032,104 @@ roc_nix_tm_init(struct roc_nix *roc_nix)
 	return rc;
 }
 
+int
+roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct nix_tm_shaper_profile profile;
+	struct mbox *mbox = (&nix->dev)->mbox;
+	struct nix_tm_node *node, *parent;
+	struct roc_nix_link_info link_info;
+
+	volatile uint64_t *reg, *regval;
+	struct nix_txschq_config *req;
+	uint64_t tl2_rate = 0;
+	uint16_t flags;
+	uint8_t k = 0;
+	int rc;
+
+	if ((nix->tm_tree != ROC_NIX_TM_PFC) || !(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
+		return NIX_ERR_TM_INVALID_TREE;
+
+	node = nix_tm_node_search(nix, qid, nix->tm_tree);
+
+	/* check if we found a valid leaf node */
+	if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||
+	    node->parent->hw_id == NIX_TM_HW_ID_INVALID) {
+		return NIX_ERR_TM_INVALID_NODE;
+	}
+
+	/* Get the link Speed */
+	if (roc_nix_mac_link_info_get(roc_nix, &link_info))
+		return -EINVAL;
+
+	if (link_info.status)
+		tl2_rate = link_info.speed * (uint64_t)1E6;
+
+	/* Configure TL3 of leaf node with requested rate */
+	parent = node->parent;	 /* SMQ/MDQ */
+	parent = parent->parent; /* TL4 */
+	parent = parent->parent; /* TL3 */
+	flags = parent->flags;
+
+	req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));
+	req->lvl = parent->hw_lvl;
+	reg = req->reg;
+	regval = req->regval;
+
+	if (rate == 0) {
+		k += nix_tm_sw_xoff_prep(parent, true, &reg[k], &regval[k]);
+		flags &= ~NIX_TM_NODE_ENABLED;
+		goto exit;
+	}
+
+	if (!(flags & NIX_TM_NODE_ENABLED)) {
+		k += nix_tm_sw_xoff_prep(parent, false, &reg[k], &regval[k]);
+		flags |= NIX_TM_NODE_ENABLED;
+	}
+
+	/* Use only PIR for rate limit */
+	memset(&profile, 0, sizeof(profile));
+	profile.peak.rate = rate;
+	/* Minimum burst of ~4us Bytes of Tx */
+	profile.peak.size =
+		PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), (4ul * rate) / ((uint64_t)1E6 * 8));
+	if (!nix->tm_rate_min || nix->tm_rate_min > rate)
+		nix->tm_rate_min = rate;
+
+	k += nix_tm_shaper_reg_prep(parent, &profile, &reg[k], &regval[k]);
+exit:
+	req->num_regs = k;
+	rc = mbox_process(mbox);
+	mbox_put(mbox);
+	if (rc)
+		return rc;
+
+	parent->flags = flags;
+
+	/* If link is up then configure TL2 with link speed */
+	if (tl2_rate && (flags & NIX_TM_NODE_ENABLED)) {
+		k = 0;
+		parent = parent->parent;
+		req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));
+		req->lvl = parent->hw_lvl;
+		reg = req->reg;
+		regval = req->regval;
+
+		/* Use only PIR for rate limit */
+		memset(&profile, 0, sizeof(profile));
+		profile.peak.rate = tl2_rate;
+		/* Minimum burst of ~4us Bytes of Tx */
+		profile.peak.size = PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix),
+					    (4ul * tl2_rate) / ((uint64_t)1E6 * 8));
+		k += nix_tm_shaper_reg_prep(parent, &profile, &reg[k], &regval[k]);
+		req->num_regs = k;
+		rc = mbox_process(mbox);
+		mbox_put(mbox);
+	}
+	return rc;
+}
+
 int
 roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)
 {
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8c71497df8..1436c90e12 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -379,6 +379,7 @@ INTERNAL {
 	roc_nix_tm_node_suspend_resume;
 	roc_nix_tm_prealloc_res;
 	roc_nix_tm_pfc_prepare_tree;
+	roc_nix_tm_pfc_rlimit_sq;
 	roc_nix_tm_prepare_rate_limited_tree;
 	roc_nix_tm_rlimit_sq;
 	roc_nix_tm_root_has_sp;
-- 
2.25.1

[PATCH 06/31] common/cnxk: fixes CGX promisc toggling

[Nithin Dabilpuram]

From: Rahul Bhansali <rbhansali@marvell.com>

This will allow CGX promisc toggling even when exact
match feature is enabled.
Also, In case of exact feature, CGX promisc enable/disable mbox
response returns failure code -1101 in case if no change in the state.
This failure code can be ignored and proceed further.

Fixes: a90649722b51 ("common/cnxk: skip CGX promisc mode with NPC exact match")

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_dev.c     | 13 ++++++++++++-
 drivers/common/cnxk/roc_mbox.h    | 15 +++++++++++++++
 drivers/common/cnxk/roc_nix_mac.c |  8 --------
 3 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 4b0ba218ed..128b9751e4 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -451,7 +451,6 @@ process_msgs(struct dev *dev, struct mbox *mbox)
 			 * while PFC already configured on other VFs. This is
 			 * not an error but a warning which can be ignored.
 			 */
-#define LMAC_AF_ERR_PERM_DENIED -1103
 			if (msg->rc) {
 				if (msg->rc == LMAC_AF_ERR_PERM_DENIED) {
 					plt_mbox_dbg(
@@ -464,6 +463,18 @@ process_msgs(struct dev *dev, struct mbox *mbox)
 				}
 			}
 			break;
+		case MBOX_MSG_CGX_PROMISC_DISABLE:
+		case MBOX_MSG_CGX_PROMISC_ENABLE:
+			if (msg->rc) {
+				if (msg->rc == LMAC_AF_ERR_INVALID_PARAM) {
+					plt_mbox_dbg("Already in same promisc state");
+					msg->rc = 0;
+				} else {
+					plt_err("Message (%s) response has err=%d",
+						mbox_id2name(msg->id), msg->rc);
+				}
+			}
+			break;
 
 		default:
 			if (msg->rc)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index f038d3e02b..2fd01cd710 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -540,6 +540,21 @@ struct lmtst_tbl_setup_req {
 };
 
 /* CGX mbox message formats */
+/* CGX mailbox error codes
+ * Range 1101 - 1200.
+ */
+enum cgx_af_status {
+	LMAC_AF_ERR_INVALID_PARAM = -1101,
+	LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
+	LMAC_AF_ERR_PERM_DENIED = -1103,
+	LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
+	LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
+	LMAC_AF_ERR_CMD_TIMEOUT = -1106,
+	LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
+	LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
+	LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
+	LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
+};
 
 struct cgx_stats_rsp {
 	struct mbox_msghdr hdr;
diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c
index 754d75ac73..ac30fb52d1 100644
--- a/drivers/common/cnxk/roc_nix_mac.c
+++ b/drivers/common/cnxk/roc_nix_mac.c
@@ -201,14 +201,6 @@ roc_nix_mac_promisc_mode_enable(struct roc_nix *roc_nix, int enable)
 		goto exit;
 	}
 
-	/* Skip CGX promisc toggling if NPC exact match is enabled as
-	 * CGX filtering is disabled permanently.
-	 */
-	if (nix->exact_match_ena) {
-		rc = 0;
-		goto exit;
-	}
-
 	if (enable)
 		mbox_alloc_msg_cgx_promisc_enable(mbox);
 	else
-- 
2.25.1

[PATCH 07/31] common/cnxk: fix xstats for different packet sizes

[Nithin Dabilpuram]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

xstats for transmitted packets with different sizes
are not updated as sizeof mbox response structure
are different in dpdk and kernel.This patch fixes the
same.

Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions")

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 2fd01cd710..169bbcb664 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -558,7 +558,7 @@ enum cgx_af_status {
 
 struct cgx_stats_rsp {
 	struct mbox_msghdr hdr;
-#define CGX_RX_STATS_COUNT 13
+#define CGX_RX_STATS_COUNT 9
 #define CGX_TX_STATS_COUNT 18
 	uint64_t __io rx_stats[CGX_RX_STATS_COUNT];
 	uint64_t __io tx_stats[CGX_TX_STATS_COUNT];
-- 
2.25.1

[PATCH 08/31] common/cnxk: disable BP on SDP link while closing SQ

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Host SDP port closes the SDP link on NIX causes crash when
BP enabled on SDP link. This patch disables BP on SDP link
when SQ flush fails due to link disabled at host.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix_tm.c | 73 ++++++++++++++++++++++++++++++--
 1 file changed, 70 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index c104611355..ce1e44ac4f 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -610,8 +610,6 @@ roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)
 
 	return 0;
 exit:
-	roc_nix_tm_dump(sq->roc_nix, NULL);
-	roc_nix_queues_ctx_dump(sq->roc_nix, NULL);
 	return -EFAULT;
 }
 
@@ -748,6 +746,70 @@ roc_nix_tm_sq_free_pending_sqe(struct nix *nix, int q)
 	return 0;
 }
 
+static inline int
+nix_tm_sdp_sq_drop_pkts(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct mbox *mbox = mbox_get((&nix->dev)->mbox);
+	struct nix_txschq_config *req = NULL, *rsp;
+	enum roc_nix_tm_tree tree = nix->tm_tree;
+	int rc = 0, qid = sq->qid;
+	struct nix_tm_node *node;
+	uint64_t regval;
+
+	/* Find the node for this SQ */
+	node = nix_tm_node_search(nix, qid, tree);
+	while (node) {
+		if (node->hw_lvl != NIX_TXSCH_LVL_TL4) {
+			node = node->parent;
+			continue;
+		}
+		break;
+	}
+	if (!node) {
+		plt_err("Invalid node/state for sq %u", qid);
+		return -EFAULT;
+	}
+
+	/* Get present link config */
+	req = mbox_alloc_msg_nix_txschq_cfg(mbox);
+	req->read = 1;
+	req->lvl = NIX_TXSCH_LVL_TL4;
+	req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id);
+	req->num_regs = 1;
+	rc = mbox_process_msg(mbox, (void **)&rsp);
+	if (rc || rsp->num_regs != 1)
+		goto err;
+	regval = rsp->regval[0];
+	/* Disable BP_ENA in SDP link config */
+	req = mbox_alloc_msg_nix_txschq_cfg(mbox);
+	req->lvl = NIX_TXSCH_LVL_TL4;
+	req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id);
+	req->regval[0] = 0x0ull;
+	req->regval_mask[0] = ~(BIT_ULL(13));
+	req->num_regs = 1;
+	rc = mbox_process(mbox);
+	if (rc)
+		goto err;
+	mbox_put(mbox);
+	/* Flush SQ to drop all packets */
+	rc = roc_nix_tm_sq_flush_spin(sq);
+	if (rc)
+		plt_nix_dbg("SQ flush failed with link reset config rc %d", rc);
+	mbox = mbox_get((&nix->dev)->mbox);
+	/* Restore link config */
+	req = mbox_alloc_msg_nix_txschq_cfg(mbox);
+	req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id);
+	req->lvl = NIX_TXSCH_LVL_TL4;
+	req->regval[0] = regval;
+	req->regval_mask[0] = ~(BIT_ULL(13) | BIT_ULL(12) | GENMASK_ULL(7, 0));
+	req->num_regs = 1;
+	rc = mbox_process(mbox);
+err:
+	mbox_put(mbox);
+	return rc;
+}
+
 /* Flush and disable tx queue and its parent SMQ */
 int
 nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
@@ -834,8 +896,13 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
 		/* Wait for sq entries to be flushed */
 		rc = roc_nix_tm_sq_flush_spin(sq);
 		if (rc) {
-			rc = roc_nix_tm_sq_free_pending_sqe(nix, sq->qid);
+			if (nix->sdp_link)
+				rc = nix_tm_sdp_sq_drop_pkts(roc_nix, sq);
+			else
+				rc = roc_nix_tm_sq_free_pending_sqe(nix, sq->qid);
 			if (rc) {
+				roc_nix_tm_dump(sq->roc_nix, NULL);
+				roc_nix_queues_ctx_dump(sq->roc_nix, NULL);
 				plt_err("Failed to drain sq %u, rc=%d\n", sq->qid, rc);
 				return rc;
 			}
-- 
2.25.1

[PATCH 09/31] common/cnxk: fix leak in error path

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

Fixed resource leak when pthread create fails in dev_init().

Fixes: 1c7a4d37e73d ("common/cnxk: fix mailbox timeout due to deadlock")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/roc_dev.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 128b9751e4..18d7981825 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -1472,7 +1472,7 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
 					    pf_vf_mbox_thread_main, dev);
 		if (rc != 0) {
 			plt_err("Failed to create thread for VF mbox handling\n");
-			goto iounmap;
+			goto thread_fail;
 		}
 	}
 
@@ -1500,9 +1500,10 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
 		dev->sync.start_thread = false;
 		pthread_cond_signal(&dev->sync.pfvf_msg_cond);
 		pthread_join(dev->sync.pfvf_msg_thread, NULL);
-		pthread_mutex_destroy(&dev->sync.mutex);
-		pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
 	}
+thread_fail:
+	pthread_mutex_destroy(&dev->sync.mutex);
+	pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
 iounmap:
 	dev_vf_mbase_put(pci_dev, vf_mbase);
 mbox_unregister:
-- 
2.25.1

[PATCH 10/31] common/cnxk: fix different size bit operations

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

WORD_SIZE is made as unsigned long long so that
bit operations are done on same size of variables.

Fixes: 1ec23c7523b4 ("common/cnxk: support anti-replay check in SW for cn9k")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/cnxk_security_ar.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/cnxk_security_ar.h b/drivers/common/cnxk/cnxk_security_ar.h
index deb38db0d0..d0151a752c 100644
--- a/drivers/common/cnxk/cnxk_security_ar.h
+++ b/drivers/common/cnxk/cnxk_security_ar.h
@@ -17,7 +17,7 @@
 	 BITS_PER_LONG_LONG)
 
 #define WORD_SHIFT 6
-#define WORD_SIZE  (1 << WORD_SHIFT)
+#define WORD_SIZE  (1ULL << WORD_SHIFT)
 #define WORD_MASK  (WORD_SIZE - 1)
 
 #define IPSEC_ANTI_REPLAY_FAILED (-1)
-- 
2.25.1

[PATCH 11/31] common/cnxk: fix different size bit operations

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

Bitwise or is being done on relchan which is 32 bit,
but the result is 64 bit, hence typecast to uint64_t.

Fixes: 8f867a87b9c5 ("common/cnxk: enable SDP channel backpressure to TL4")
Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/roc_nix_tm_utils.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 3840d6d457..ce26ddff50 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -588,7 +588,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 			reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 			regval[k] = BIT_ULL(12);
 			regval[k] |= BIT_ULL(13);
-			regval[k] |= relchan;
+			regval[k] |= (uint64_t)relchan;
 			k++;
 		}
 		break;
@@ -606,7 +606,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 		if (!nix->sdp_link &&
 		    nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) {
 			reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
-			regval[k] = BIT_ULL(12) | relchan;
+			regval[k] = BIT_ULL(12) | (uint64_t)relchan;
 			k++;
 		}
 
@@ -625,7 +625,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 		if (!nix->sdp_link &&
 		    nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) {
 			reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
-			regval[k] = BIT_ULL(12) | relchan;
+			regval[k] = BIT_ULL(12) | (uint64_t)relchan;
 			k++;
 		}
 
-- 
2.25.1

[PATCH 12/31] common/cnxk: remove unnecessory ROC API calls

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

Removed the calls to roc_nix_num_rx[tx]_xstats which
does a model check again for cn9k/cn10k.
The model check is already done before the call in the
same leg, hence not needed to call these APIs.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/roc_nix_stats.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c
index 1e93191a07..7a9619b39d 100644
--- a/drivers/common/cnxk/roc_nix_stats.c
+++ b/drivers/common/cnxk/roc_nix_stats.c
@@ -400,14 +400,14 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,
 		if (rc)
 			goto exit;
 
-		for (i = 0; i < roc_nix_num_rx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) {
 			xstats[count].value =
 				cgx_resp->rx_stats[nix_rx_xstats_cgx[i].offset];
 			xstats[count].id = count;
 			count++;
 		}
 
-		for (i = 0; i < roc_nix_num_tx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) {
 			xstats[count].value =
 				cgx_resp->tx_stats[nix_tx_xstats_cgx[i].offset];
 			xstats[count].id = count;
@@ -426,14 +426,14 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,
 		if (rc)
 			goto exit;
 
-		for (i = 0; i < roc_nix_num_rx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) {
 			xstats[count].value =
 				rpm_resp->rx_stats[nix_rx_xstats_rpm[i].offset];
 			xstats[count].id = count;
 			count++;
 		}
 
-		for (i = 0; i < roc_nix_num_tx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) {
 			xstats[count].value =
 				rpm_resp->tx_stats[nix_tx_xstats_rpm[i].offset];
 			xstats[count].id = count;
@@ -504,26 +504,26 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix,
 		return count;
 
 	if (roc_model_is_cn9k()) {
-		for (i = 0; i < roc_nix_num_rx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) {
 			NIX_XSTATS_NAME_PRINT(xstats_names, count,
 					      nix_rx_xstats_cgx, i);
 			count++;
 		}
 
-		for (i = 0; i < roc_nix_num_tx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) {
 			NIX_XSTATS_NAME_PRINT(xstats_names, count,
 					      nix_tx_xstats_cgx, i);
 			count++;
 		}
 
 	} else {
-		for (i = 0; i < roc_nix_num_rx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) {
 			NIX_XSTATS_NAME_PRINT(xstats_names, count,
 					      nix_rx_xstats_rpm, i);
 			count++;
 		}
 
-		for (i = 0; i < roc_nix_num_tx_xstats(); i++) {
+		for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) {
 			NIX_XSTATS_NAME_PRINT(xstats_names, count,
 					      nix_tx_xstats_rpm, i);
 			count++;
-- 
2.25.1

[PATCH 13/31] common/cnxk: sync MAC addr set mailbox structure

[Nithin Dabilpuram]

From: Srujana Challa <schalla@marvell.com>

Sync MAC address set mailbox format with kernel. And
send match table index to the kernel to add the
mac address. This fixes the issues on cn10kb, where
traffic was not received when promisc is disabled
and two ports are used.

Signed-off-by: Srujana Challa <schalla@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h     | 1 +
 drivers/common/cnxk/roc_nix.c      | 1 +
 drivers/common/cnxk/roc_nix_mac.c  | 8 ++++++--
 drivers/common/cnxk/roc_nix_priv.h | 1 +
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 169bbcb664..04fc56465e 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -584,6 +584,7 @@ struct cgx_fec_stats_rsp {
 struct cgx_mac_addr_set_or_get {
 	struct mbox_msghdr hdr;
 	uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];
+	uint32_t index;
 };
 
 /* Structure for requesting the operation to
diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c
index 152ef7269e..498328d6ed 100644
--- a/drivers/common/cnxk/roc_nix.c
+++ b/drivers/common/cnxk/roc_nix.c
@@ -475,6 +475,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix)
 	nix->pci_dev = pci_dev;
 	nix->reta_sz = reta_sz;
 	nix->mtu = ROC_NIX_DEFAULT_HW_FRS;
+	nix->dmac_flt_idx = -1;
 
 	/* Register error and ras interrupts */
 	rc = nix_register_irqs(nix);
diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c
index ac30fb52d1..e2e87be525 100644
--- a/drivers/common/cnxk/roc_nix_mac.c
+++ b/drivers/common/cnxk/roc_nix_mac.c
@@ -81,9 +81,9 @@ int
 roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[])
 {
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct cgx_mac_addr_set_or_get *req, *rsp;
 	struct dev *dev = &nix->dev;
 	struct mbox *mbox = mbox_get(dev->mbox);
-	struct cgx_mac_addr_set_or_get *req;
 	int rc;
 
 	if (roc_nix_is_vf_or_sdp(roc_nix)) {
@@ -97,9 +97,13 @@ roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[])
 	}
 
 	req = mbox_alloc_msg_cgx_mac_addr_set(mbox);
+	req->index = nix->dmac_flt_idx;
 	mbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN);
 
-	rc = mbox_process(mbox);
+	rc = mbox_process_msg(mbox, (void *)&rsp);
+	if (rc)
+		goto exit;
+	nix->dmac_flt_idx = rsp->index;
 exit:
 	mbox_put(mbox);
 	return rc;
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index ea4211dfed..f82e411b70 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -153,6 +153,7 @@ struct nix {
 	uint8_t sdp_links;
 	uint8_t tx_link;
 	uint16_t sqb_size;
+	uint32_t dmac_flt_idx;
 	/* Without FCS, with L2 overhead */
 	uint16_t mtu;
 	uint16_t chan_cnt;
-- 
2.25.1

[PATCH 14/31] common/cnxk: add API to get Rx chan count from NIX

[Nithin Dabilpuram]

From: Rahul Bhansali <rbhansali@marvell.com>

For SDP, provide an API to get Rx chan count from NIX as
all channels are always active.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_nix.c   | 8 ++++++++
 drivers/common/cnxk/roc_nix.h   | 1 +
 drivers/common/cnxk/version.map | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c
index 498328d6ed..f64933a1d9 100644
--- a/drivers/common/cnxk/roc_nix.c
+++ b/drivers/common/cnxk/roc_nix.c
@@ -21,6 +21,14 @@ roc_nix_get_base_chan(struct roc_nix *roc_nix)
 	return nix->rx_chan_base;
 }
 
+uint8_t
+roc_nix_get_rx_chan_cnt(struct roc_nix *roc_nix)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+
+	return nix->rx_chan_cnt;
+}
+
 uint16_t
 roc_nix_get_vwqe_interval(struct roc_nix *roc_nix)
 {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 1d84f4de9d..377b9604ea 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -527,6 +527,7 @@ bool __roc_api roc_nix_is_sdp(struct roc_nix *roc_nix);
 bool __roc_api roc_nix_is_pf(struct roc_nix *roc_nix);
 bool __roc_api roc_nix_is_vf_or_sdp(struct roc_nix *roc_nix);
 int __roc_api roc_nix_get_base_chan(struct roc_nix *roc_nix);
+uint8_t __roc_api roc_nix_get_rx_chan_cnt(struct roc_nix *roc_nix);
 int __roc_api roc_nix_get_pf(struct roc_nix *roc_nix);
 int __roc_api roc_nix_get_vf(struct roc_nix *roc_nix);
 uint16_t __roc_api roc_nix_get_pf_func(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 1436c90e12..f2df099ad4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -214,6 +214,7 @@ INTERNAL {
 	roc_nix_get_base_chan;
 	roc_nix_get_pf;
 	roc_nix_get_pf_func;
+	roc_nix_get_rx_chan_cnt;
 	roc_nix_get_vf;
 	roc_nix_get_vwqe_interval;
 	roc_nix_inl_cb_register;
-- 
2.25.1

[PATCH 15/31] common/cnxk: fix BP threshold calculation

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Current macro to calculate BP threshold were evaluating incorrect
threshold because aura_limit is first shifted by shift then percentage
is calculated.

While first percentage should be calculated and the resultant should be
shifted by shift.

So formula is updated accordingly.

Fixes: cb4bfd6e7bdf ("event/cnxk: support Rx adapter")

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix_fc.c   | 2 +-
 drivers/common/cnxk/roc_nix_priv.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index d58b35268e..0f9b5cbbc0 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -496,7 +496,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	aura_attr = &lf->aura_attr[aura_id];
 
 	bp_intf = 1 << nix->is_nix1;
-	bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift);
+	bp_thresh = NIX_RQ_AURA_BP_THRESH(drop_percent, aura_attr->limit, aura_attr->shift);
 
 	bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid;
 	/* BP is already enabled. */
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index f82e411b70..a582b9df33 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -20,7 +20,7 @@
 /* Apply LBP at 75% of actual BP */
 #define NIX_CQ_LPB_THRESH_FRAC	(75 * 16 / 100)
 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
-#define NIX_RQ_AURA_THRESH(percent, val) (((val) * (percent)) / 100)
+#define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift))
 
 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
 #define CQ_CQE_THRESH_DEFAULT	0x1ULL
-- 
2.25.1

[PATCH 16/31] common/cnxk: allow same TC on multiple RQs

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

To achieve actual PFC behavior, user needs to configure
different TC on different aura so that PFC can be generated
for specific TC but same TC can also configured on multiple
RQs which has same configured aura.

In this patch, aura with same BP configuration is allowed
on multiple RQs.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix_fc.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index 0f9b5cbbc0..2a58567751 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -501,7 +501,6 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 	bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid;
 	/* BP is already enabled. */
 	if (aura_attr->bp_ena && ena) {
-		/* Disable BP if BPIDs don't match and couldn't add new BPID. */
 		if (bpid != nix->bpid[tc]) {
 			uint16_t bpid_new = NIX_BPID_INVALID;
 
@@ -519,15 +518,13 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
 				plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64,
 					 roc_nix->port_id, tc, pool_id);
 			}
+		} else {
+			aura_attr->ref_count++;
 		}
 
 		return;
 	}
 
-	/* BP was previously enabled but now disabled skip. */
-	if (aura_attr->bp && ena)
-		return;
-
 	if (ena) {
 		if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))
 			plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id);
-- 
2.25.1

[PATCH 17/31] common/cnxk: expose different params for bp config

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Currently same bp percentage is applied on SPB and
LPB pool but both pools can be configured with different
bp level.

Added one more parameter so that separate threshold parameters
can be passed for SPB and LPB pools.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix.h    |  3 ++-
 drivers/common/cnxk/roc_nix_fc.c | 14 +++++++++-----
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 377b9604ea..bb55fbe971 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -196,10 +196,11 @@ struct roc_nix_fc_cfg {
 			uint32_t rq;
 			uint16_t tc;
 			uint16_t cq_drop;
-			bool enable;
 			uint64_t pool;
 			uint64_t spb_pool;
 			uint64_t pool_drop_pct;
+			uint64_t spb_pool_drop_pct;
+			bool enable;
 		} rq_cfg;
 
 		struct {
diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index 2a58567751..12bfb9816b 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -282,8 +282,8 @@ static int
 nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
 {
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	uint64_t pool_drop_pct, spb_pool_drop_pct;
 	struct roc_nix_fc_cfg tmp;
-	uint64_t pool_drop_pct;
 	struct roc_nix_rq *rq;
 	int rc;
 
@@ -295,14 +295,18 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
 		if (fc_cfg->rq_cfg.enable && !pool_drop_pct)
 			pool_drop_pct = ROC_NIX_AURA_THRESH;
 
-		roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool,
-				      fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,
-				      fc_cfg->rq_cfg.tc, pool_drop_pct);
+		roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, fc_cfg->rq_cfg.enable,
+				      roc_nix->force_rx_aura_bp, fc_cfg->rq_cfg.tc, pool_drop_pct);
 
 		if (rq->spb_ena) {
+			spb_pool_drop_pct = fc_cfg->rq_cfg.spb_pool_drop_pct;
+			/* Use default value for zero pct */
+			if (!spb_pool_drop_pct)
+				spb_pool_drop_pct = ROC_NIX_AURA_THRESH;
+
 			roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool,
 					      fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,
-					      fc_cfg->rq_cfg.tc, pool_drop_pct);
+					      fc_cfg->rq_cfg.tc, spb_pool_drop_pct);
 		}
 
 		if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)
-- 
2.25.1

[PATCH 18/31] common/cnxk: enable CQ stashing

[Nithin Dabilpuram]

From: Kommula Shiva Shankar <kshankar@marvell.com>

This patch enables CQ stashing for better CQE
processing performance

Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>
---
 drivers/common/cnxk/roc_features.h  | 6 ++++++
 drivers/common/cnxk/roc_nix.h       | 1 +
 drivers/common/cnxk/roc_nix_queue.c | 7 +++++++
 3 files changed, 14 insertions(+)

diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h
index 815f800e7a..a461ca46c5 100644
--- a/drivers/common/cnxk/roc_features.h
+++ b/drivers/common/cnxk/roc_features.h
@@ -46,6 +46,12 @@ roc_feature_nix_has_reass(void)
 	return roc_model_is_cn10ka();
 }
 
+static inline bool
+roc_feature_nix_has_cqe_stash(void)
+{
+	return roc_model_is_cn10ka_b0();
+}
+
 static inline bool
 roc_feature_nix_has_rxchan_multi_bpid(void)
 {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index bb55fbe971..5892de6b24 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -368,6 +368,7 @@ struct roc_nix_cq {
 	/* Input parameters */
 	uint16_t qid;
 	uint32_t nb_desc;
+	uint8_t stash_thresh;
 	/* End of Input parameters */
 	uint16_t drop_thresh;
 	struct roc_nix *roc_nix;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 5e689d08be..f96d5c3a96 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -908,6 +908,13 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
 	}
 	cq_ctx->bp = cq->drop_thresh;
 
+	if (roc_feature_nix_has_cqe_stash()) {
+		if (cq_ctx->caching) {
+			cq_ctx->stashing = 1;
+			cq_ctx->stash_thresh = cq->stash_thresh;
+		}
+	}
+
 	rc = mbox_process(mbox);
 	mbox_put(mbox);
 	if (rc)
-- 
2.25.1

[PATCH 19/31] common/cnxk: fix incorrect aura ID

[Nithin Dabilpuram]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

The function `sso_hwgrp_alloc_xaq` expects aura ID, fix incorrectly
passing aura handle to it.

Fixes: 7e9a94909eea ("common/cnxk: realloc inline device XAQ AURA")

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl_dev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 2863d5da51..de3498a4f7 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -678,7 +678,8 @@ roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)
 	}
 
 	/* Setup xaq for hwgrps */
-	rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1);
+	rc = sso_hwgrp_alloc_xaq(&inl_dev->dev,
+				 roc_npa_aura_handle_to_aura(inl_dev->xaq.aura_handle), 1);
 	if (rc) {
 		plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc);
 		return rc;
-- 
2.25.1

[PATCH 20/31] net/cnxk: fix CQ allocation

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Allocate number of CQs sufficient to handle completions of both
RQs and SQs.

Fixes: dd9446991212 ("net/cnxk: add transmit completion handler")
Cc: rkudurumalla@marvell.com

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 4b98faa729..46450088eb 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1197,8 +1197,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 	char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
 	struct roc_nix_fc_cfg fc_cfg = {0};
 	struct roc_nix *nix = &dev->nix;
+	uint16_t nb_rxq, nb_txq, nb_cq;
 	struct rte_ether_addr *ea;
-	uint16_t nb_rxq, nb_txq;
 	uint64_t rx_cfg;
 	void *qs;
 	int rc;
@@ -1309,6 +1309,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 
 	nb_rxq = data->nb_rx_queues;
 	nb_txq = data->nb_tx_queues;
+	nb_cq = nb_rxq;
+	if (nix->tx_compl_ena)
+		nb_cq += nb_txq;
 	rc = -ENOMEM;
 	if (nb_rxq) {
 		/* Allocate memory for roc rq's and cq's */
@@ -1318,13 +1321,6 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 			goto free_nix_lf;
 		}
 		dev->rqs = qs;
-
-		qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0);
-		if (!qs) {
-			plt_err("Failed to alloc cqs");
-			goto free_nix_lf;
-		}
-		dev->cqs = qs;
 	}
 
 	if (nb_txq) {
@@ -1335,15 +1331,15 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 			goto free_nix_lf;
 		}
 		dev->sqs = qs;
+	}
 
-		if (nix->tx_compl_ena) {
-			qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_txq, 0);
-			if (!qs) {
-				plt_err("Failed to alloc cqs");
-				goto free_nix_lf;
-			}
-			dev->cqs = qs;
+	if (nb_cq) {
+		qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_cq, 0);
+		if (!qs) {
+			plt_err("Failed to alloc cqs");
+			goto free_nix_lf;
 		}
+		dev->cqs = qs;
 	}
 
 	/* Re-enable NIX LF error interrupts */
-- 
2.25.1

[PATCH 21/31] net/cnxk: fix issue with GCC 4.8

[Nithin Dabilpuram]

Fix issue with GCC 4.8 cross compilation of ARM64 for
flexible vector conversions.

Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets")

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 8148866e44..0dc0b0595c 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -164,9 +164,9 @@ nix_sec_reass_frags_get(const struct cpt_parse_hdr_s *hdr, struct rte_mbuf **nex
 	next_mbufs[1] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 0) - 1);
 	next_mbufs[2] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 1) - 1);
 
-	fsz_w1 = vdup_n_u64(finfo->w1.u64);
+	fsz_w1 = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64));
 	fsz_w1 = vrev16_u8(fsz_w1);
-	return vget_lane_u64(fsz_w1, 0);
+	return vget_lane_u64(vreinterpret_u64_u16(fsz_w1), 0);
 }
 
 static __rte_always_inline void
@@ -174,7 +174,7 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const uint8_t *m_ipptr,
 				uint64_t fsz, uint64_t cq_w1, uint16_t *ihl)
 {
 	union nix_rx_parse_u *rx = (union nix_rx_parse_u *)((uintptr_t)(head + 1) + 8);
-	uint16_t fragx_sum = vaddv_u16(vdup_n_u64(fsz));
+	uint16_t fragx_sum = vaddv_u16(vreinterpret_u16_u64(vdup_n_u64(fsz)));
 	uint8_t lcptr = rx->lcptr;
 	uint16_t tot_len;
 	uint32_t cksum;
-- 
2.25.1

[PATCH 22/31] net/cnxk: add mapping of DMAC address indexes

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Add support to map DMAC address indexes during
mac address add and remove operation.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c     | 11 +++++++++++
 drivers/net/cnxk/cnxk_ethdev.h     |  1 +
 drivers/net/cnxk/cnxk_ethdev_ops.c |  4 +++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 46450088eb..bd161ad375 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1921,6 +1921,13 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 		goto dev_fini;
 	}
 
+	dev->dmac_idx_map = rte_zmalloc("dmac_idx_map", max_entries * sizeof(int), 0);
+	if (dev->dmac_idx_map == NULL) {
+		plt_err("Failed to allocate memory for dmac idx map");
+		rc = -ENOMEM;
+		goto free_mac_addrs;
+	}
+
 	dev->max_mac_entries = max_entries;
 	dev->dmac_filter_count = 1;
 
@@ -1978,6 +1985,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 
 free_mac_addrs:
 	rte_free(eth_dev->data->mac_addrs);
+	rte_free(dev->dmac_idx_map);
 dev_fini:
 	roc_nix_dev_fini(nix);
 error:
@@ -2095,6 +2103,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
 	if (rc)
 		plt_err("Failed to free nix lf, rc=%d", rc);
 
+	rte_free(dev->dmac_idx_map);
+	dev->dmac_idx_map = NULL;
+
 	rte_free(eth_dev->data->mac_addrs);
 	eth_dev->data->mac_addrs = NULL;
 
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ed531fb277..8649f9e6f0 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -329,6 +329,7 @@ struct cnxk_eth_dev {
 	uint8_t dmac_filter_count;
 	uint8_t max_mac_entries;
 	bool dmac_filter_enable;
+	int *dmac_idx_map;
 
 	uint16_t flags;
 	uint8_t ptype_disable;
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 3ade8eed36..5de2919047 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -474,6 +474,8 @@ cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr,
 		return rc;
 	}
 
+	dev->dmac_idx_map[index] = rc;
+
 	/* Enable promiscuous mode at NIX level */
 	roc_nix_npc_promisc_ena_dis(nix, true);
 	dev->dmac_filter_enable = true;
@@ -490,7 +492,7 @@ cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index)
 	struct roc_nix *nix = &dev->nix;
 	int rc;
 
-	rc = roc_nix_mac_addr_del(nix, index);
+	rc = roc_nix_mac_addr_del(nix, dev->dmac_idx_map[index]);
 	if (rc)
 		plt_err("Failed to delete mac address, rc=%d", rc);
 
-- 
2.25.1

[PATCH 23/31] net/cnxk: support rate limit in PFC TM tree

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

SQ rate limit was different in PFC tree compared to regular rate
limit tree.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cnxk_tm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c
index 9d8cd3f0a9..c799193cb8 100644
--- a/drivers/net/cnxk/cnxk_tm.c
+++ b/drivers/net/cnxk/cnxk_tm.c
@@ -765,6 +765,9 @@ cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
 	if (queue_idx >= eth_dev->data->nb_tx_queues)
 		goto exit;
 
+	if (roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_PFC)
+		return roc_nix_tm_pfc_rlimit_sq(nix, queue_idx, tx_rate);
+
 	if ((roc_nix_tm_tree_type_get(nix) != ROC_NIX_TM_RLIMIT) &&
 	    eth_dev->data->nb_tx_queues > 1) {
 		/*
-- 
2.25.1

[PATCH 24/31] net/cnxk: move MAC address set from init to configure

[Nithin Dabilpuram]

From: Srujana Challa <schalla@marvell.com>

Channel(rx_chan_base) is not available in the kernel at
the time of nix probe. Hence, move the mac address set
call from nix_device_init() to nix_device_configure().
This fixes the issue on cn10kb, where traffic was not
getting received when promisc is disabled.

Signed-off-by: Srujana Challa <schalla@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index bd161ad375..3b2ad5ff7d 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1301,6 +1301,15 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_configure;
 	}
 
+	if (!roc_nix_is_vf_or_sdp(nix)) {
+		/* Sync same MAC address to CGX/RPM table */
+		rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
+		if (rc) {
+			plt_err("Failed to set mac addr, rc=%d", rc);
+			goto fail_configure;
+		}
+	}
+
 	/* Check if ptp is enable in PF owning this VF*/
 	if (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix)))
 		dev->ptp_en = roc_nix_ptp_is_enable(nix);
@@ -1941,15 +1950,6 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 	/* Update the mac address */
 	memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
 
-	if (!roc_nix_is_vf_or_sdp(nix)) {
-		/* Sync same MAC address to CGX/RPM table */
-		rc = roc_nix_mac_addr_set(nix, dev->mac_addr);
-		if (rc) {
-			plt_err("Failed to set mac addr, rc=%d", rc);
-			goto free_mac_addrs;
-		}
-	}
-
 	/* Union of all capabilities supported by CNXK.
 	 * Platform specific capabilities will be
 	 * updated later.
-- 
2.25.1

[PATCH 25/31] net/cnxk: update different size bit operations

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

Certain bitwise operations are done with different
sized operands which causes warnings in static code
analysis. The necessary operands are typecast to remove
the warning.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev.c |  2 +-
 drivers/net/cnxk/cn10k_rx.h     | 10 +++++-----
 drivers/net/cnxk/cn10k_tx.h     | 12 ++++++------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 4c4acc7cf0..40437d2d73 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -262,7 +262,7 @@ cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 
 		txq->cpt_desc = inl_lf->nb_desc * 0.7;
 		txq->sa_base = (uint64_t)dev->outb.sa_base;
-		txq->sa_base |= eth_dev->data->port_id;
+		txq->sa_base |= (uint64_t)eth_dev->data->port_id;
 		PLT_STATIC_ASSERT(ROC_NIX_INL_SA_BASE_ALIGN == BIT_ULL(16));
 	}
 
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 0dc0b0595c..a696427091 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -795,7 +795,7 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
 	/* Skip rx ol flags extraction for Security packets */
 	if ((!(flag & NIX_RX_SEC_REASSEMBLY_F) || !(w1 & BIT(11))) &&
 			flag & NIX_RX_OFFLOAD_CHECKSUM_F)
-		ol_flags |= nix_rx_olflags_get(lookup_mem, w1);
+		ol_flags |= (uint64_t)nix_rx_olflags_get(lookup_mem, w1);
 
 	if (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) {
 		if (rx->vtag0_gone) {
@@ -1334,10 +1334,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 		}
 
 		if (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {
-			ol_flags0 |= nix_rx_olflags_get(lookup_mem, cq0_w1);
-			ol_flags1 |= nix_rx_olflags_get(lookup_mem, cq1_w1);
-			ol_flags2 |= nix_rx_olflags_get(lookup_mem, cq2_w1);
-			ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);
+			ol_flags0 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq0_w1);
+			ol_flags1 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq1_w1);
+			ol_flags2 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq2_w1);
+			ol_flags3 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq3_w1);
 		}
 
 		/* Translate meta to mbuf */
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 298d243aac..04d02317b1 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -484,7 +484,7 @@ cn10k_nix_sec_steorl(uintptr_t io_addr, uint32_t lmt_id, uint8_t lnum,
 	data &= ~(0x7ULL << 16);
 	/* Update lines - 1 that contain valid data */
 	data |= ((uint64_t)(lnum + loff - 1)) << 12;
-	data |= lmt_id;
+	data |= (uint64_t)lmt_id;
 
 	/* STEOR */
 	roc_lmt_submit_steorl(data, pa);
@@ -577,7 +577,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,
 		nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);
 		nixtx += 16;
 
-		w0 |= cn10k_nix_tx_ext_subs(flags) + 1;
+		w0 |= cn10k_nix_tx_ext_subs(flags) + 1ULL;
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		*cmd1 = vsetq_lane_u16(pkt_len + dlen_adj, *cmd1, 0);
@@ -718,7 +718,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr,
 		nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1);
 		nixtx += 16;
 
-		w0 |= cn10k_nix_tx_ext_subs(flags) + 1;
+		w0 |= cn10k_nix_tx_ext_subs(flags) + 1ULL;
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		sg->seg1_size = pkt_len + dlen_adj;
@@ -1421,7 +1421,7 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts,
 		pa = io_addr | (data & 0x7) << 4;
 		data &= ~0x7ULL;
 		data |= ((uint64_t)(burst - 1)) << 12;
-		data |= lmt_id;
+		data |= (uint64_t)lmt_id;
 
 		if (flags & NIX_TX_VWQE_F)
 			cn10k_nix_vwqe_wait_fc(txq, burst);
@@ -1583,7 +1583,7 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws,
 		data0 &= ~0x7ULL;
 		/* Move lmtst1..15 sz to bits 63:19 */
 		data0 <<= 16;
-		data0 |= ((burst - 1) << 12);
+		data0 |= ((burst - 1ULL) << 12);
 		data0 |= (uint64_t)lmt_id;
 
 		if (flags & NIX_TX_VWQE_F)
@@ -3193,7 +3193,7 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
 			wd.data[0] <<= 16;
 
 		wd.data[0] |= ((uint64_t)(lnum - 1)) << 12;
-		wd.data[0] |= lmt_id;
+		wd.data[0] |= (uint64_t)lmt_id;
 
 		if (flags & NIX_TX_VWQE_F)
 			cn10k_nix_vwqe_wait_fc(txq, burst);
-- 
2.25.1

[PATCH 26/31] net/cnxk: fix uninitialized variable

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

sa_base may be uninitialized in some remote case.
It is better to initialize it.

Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index a696427091..55ccf2023c 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -909,8 +909,8 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,
 	struct nix_cqe_hdr_s *cq;
 	struct rte_mbuf *mbuf;
 	uint64_t aura_handle;
+	uint64_t sa_base = 0;
 	uintptr_t cpth = 0;
-	uint64_t sa_base;
 	uint16_t lmt_id;
 	uint64_t laddr;
 
@@ -1050,9 +1050,9 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 	uint8x16_t f0, f1, f2, f3;
 	uint16_t lmt_id, d_off;
 	uint64_t lbase, laddr;
+	uintptr_t sa_base = 0;
 	uint16_t packets = 0;
 	uint16_t pkts_left;
-	uintptr_t sa_base;
 	uint32_t head;
 	uintptr_t cq0;
 
-- 
2.25.1

[PATCH 27/31] net/cnxk: fix usage of mbuf rearm data

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

mbuf->rearm_data is a zero length array and it is being
used to set data from that location. This shows an error
in static code analysis.
Hence it is typecast to a pointer which can be used to
set values accordingly.

Fixes: c062f5726f61 ("net/cnxk: support IP reassembly")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 55ccf2023c..982fd26045 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -510,6 +510,7 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa,
 		(const struct cpt_parse_hdr_s *)cpth;
 	uint64_t mbuf_init = vgetq_lane_u64(*rearm, 0);
 	struct cn10k_inb_priv_data *inb_priv;
+	uintptr_t p;
 
 	/* Clear checksum flags */
 	*ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK |
@@ -530,7 +531,8 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa,
 			/* First frag len */
 			inner->pkt_len = vgetq_lane_u16(*rx_desc_field1, 2);
 			inner->data_len = vgetq_lane_u16(*rx_desc_field1, 4);
-			*(uint64_t *)(&inner->rearm_data) = mbuf_init;
+			p = (uintptr_t)&inner->rearm_data;
+			*(uint64_t *)p = mbuf_init;
 
 			/* Reassembly success */
 			nix_sec_reassemble_frags(hdr, inner, cq_w1, cq_w5, mbuf_init);
@@ -545,7 +547,7 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa,
 							 *rx_desc_field1, 4);
 
 			/* Data offset might be updated */
-			mbuf_init = *(uint64_t *)(&inner->rearm_data);
+			mbuf_init = *(uint64_t *)p;
 			*rearm = vsetq_lane_u64(mbuf_init, *rearm, 0);
 		} else {
 			/* Reassembly failure */
@@ -628,6 +630,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,
 	uint64_t cq_w1;
 	int64_t len;
 	uint64_t sg;
+	uintptr_t p;
 
 	cq_w1 = *(const uint64_t *)rx;
 	if (flags & NIX_RX_REAS_F)
@@ -703,7 +706,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,
 
 		mbuf->data_len = sg_len;
 		sg = sg >> 16;
-		*(uint64_t *)(&mbuf->rearm_data) = rearm & ~0xFFFF;
+		p = (uintptr_t)&mbuf->rearm_data;
+		*(uint64_t *)p = rearm & ~0xFFFF;
 		nb_segs--;
 		iova_list++;
 
@@ -753,7 +757,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,
 			head->nb_segs = nb_segs;
 		}
 		mbuf = next_frag;
-		*(uint64_t *)(&mbuf->rearm_data) = rearm + ldptr;
+		p = (uintptr_t)&mbuf->rearm_data;
+		*(uint64_t *)p = rearm + ldptr;
 		mbuf->data_len = (sg & 0xFFFF) - ldptr -
 				 (flags & NIX_RX_OFFLOAD_TSTAMP_F ?
 				  CNXK_NIX_TIMESYNC_RX_OFFSET : 0);
@@ -781,6 +786,7 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
 	const uint64_t w1 = *(const uint64_t *)rx;
 	uint16_t len = rx->pkt_lenm1 + 1;
 	uint64_t ol_flags = 0;
+	uintptr_t p;
 
 	if (flag & NIX_RX_OFFLOAD_PTYPE_F)
 		mbuf->packet_type = nix_ptype_get(lookup_mem, w1);
@@ -818,7 +824,8 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
 		mbuf->ol_flags = ol_flags;
 		mbuf->pkt_len = len;
 		mbuf->data_len = len;
-		*(uint64_t *)(&mbuf->rearm_data) = val;
+		p = (uintptr_t)&mbuf->rearm_data;
+		*(uint64_t *)p = val;
 	}
 
 	if (flag & NIX_RX_MULTI_SEG_F)
-- 
2.25.1

[PATCH 28/31] net/cnxk: fix uninitialized variable

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

shift may be uninitialized in certain case.
It is better to initialize.
Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_tx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 04d02317b1..464cd9b401 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1999,6 +1999,7 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
 	uint64x2_t xmask01_w0, xmask23_w0;
 	uint64x2_t xmask01_w1, xmask23_w1;
 	rte_iova_t io_addr = txq->io_addr;
+	uint8_t lnum, shift = 0, loff = 0;
 	uintptr_t laddr = txq->lmt_base;
 	uint8_t c_lnum, c_shft, c_loff;
 	struct nix_send_hdr_s send_hdr;
@@ -2006,7 +2007,6 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
 	uint64x2_t xtmp128, ytmp128;
 	uint64x2_t xmask01, xmask23;
 	uintptr_t c_laddr = laddr;
-	uint8_t lnum, shift, loff = 0;
 	rte_iova_t c_io_addr;
 	uint64_t sa_base;
 	union wdata {
-- 
2.25.1

[PATCH 29/31] net/cnxk: check returned value for null

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

nix_mtr_find may return NULL in case mtr is not found.
Hence checking the return value before using it.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev_mtr.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev_mtr.c b/drivers/net/cnxk/cnxk_ethdev_mtr.c
index 27a6e4ef3d..edeca6dcc3 100644
--- a/drivers/net/cnxk/cnxk_ethdev_mtr.c
+++ b/drivers/net/cnxk/cnxk_ethdev_mtr.c
@@ -613,6 +613,11 @@ cnxk_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id,
 		while ((mtr->prev_cnt) + 1) {
 			mid_mtr =
 				nix_mtr_find(dev, mtr->prev_id[mtr->prev_cnt]);
+			if (mid_mtr == NULL) {
+				return -rte_mtr_error_set(error, ENOENT,
+					  RTE_MTR_ERROR_TYPE_MTR_ID, &mtr->prev_id[mtr->prev_cnt],
+					  "Mid meter id is invalid.");
+			}
 			rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_LEAF,
 						 mid_mtr->bpf_id,
 						 ROC_NIX_BPF_ID_INVALID);
@@ -628,6 +633,11 @@ cnxk_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id,
 		while (mtr->prev_cnt) {
 			top_mtr =
 				nix_mtr_find(dev, mtr->prev_id[mtr->prev_cnt]);
+			if (top_mtr == NULL) {
+				return -rte_mtr_error_set(error, ENOENT,
+					  RTE_MTR_ERROR_TYPE_MTR_ID, &mtr->prev_id[mtr->prev_cnt],
+					  "Top meter id is invalid.");
+			}
 			rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_MID,
 						 top_mtr->bpf_id,
 						 ROC_NIX_BPF_ID_INVALID);
@@ -1590,6 +1600,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 		switch (*tree_level) {
 		case 0:
 			mtr = nix_get_mtr(eth_dev, cur_mtr_id);
+			if (mtr == NULL)
+				return -EINVAL;
 			if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) {
 				nix_mtr_level_update(eth_dev, cur_mtr_id, 0);
 				nix_mtr_chain_update(eth_dev, cur_mtr_id, -1,
@@ -1605,6 +1617,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 			break;
 		case 1:
 			mtr = nix_get_mtr(eth_dev, cur_mtr_id);
+			if (mtr == NULL)
+				return -EINVAL;
 			if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) {
 				nix_mtr_level_update(eth_dev, cur_mtr_id, 1);
 				prev_mtr_id = id;
@@ -1635,6 +1649,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 		switch (*tree_level) {
 		case 0:
 			mtr = nix_get_mtr(eth_dev, cur_mtr_id);
+			if (mtr == NULL)
+				return -EINVAL;
 			if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) {
 				nix_mtr_level_update(eth_dev, cur_mtr_id, 0);
 			} else {
@@ -1646,6 +1662,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 			break;
 		case 1:
 			mtr = nix_get_mtr(eth_dev, cur_mtr_id);
+			if (mtr == NULL)
+				return -EINVAL;
 			if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) {
 				nix_mtr_level_update(eth_dev, cur_mtr_id, 1);
 				prev_mtr_id = id;
@@ -1666,6 +1684,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,
 			break;
 		case 2:
 			mtr = nix_get_mtr(eth_dev, cur_mtr_id);
+			if (mtr == NULL)
+				return -EINVAL;
 			if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) {
 				nix_mtr_level_update(eth_dev, cur_mtr_id, 2);
 				prev_mtr_id = *prev_id;
-- 
2.25.1

[PATCH 30/31] net/cnxk: add flag check for extension header when used

[Nithin Dabilpuram]

From: Akhil Goyal <gakhil@marvell.com>

send_hdr_ext is being used, but it may be null when
the flag check for NIX_TX_NEED_EXT_HDR is not done.
Hence added a check here to avoid null pointer dereference.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/net/cnxk/cn10k_tx.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 464cd9b401..fff7ae7fc9 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1011,7 +1011,8 @@ cn10k_nix_xmit_prepare(struct cn10k_eth_txq *txq,
 		send_hdr_ext->w0.markptr = markptr;
 	}
 
-	if (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
+	if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
+	    (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
 		uint16_t lso_sb;
 		uint64_t mask;
 
-- 
2.25.1

[PATCH 31/31] net/cnxk: fixes for IPv6 header in reassembly

[Nithin Dabilpuram]

From: Rahul Bhansali <rbhansali@marvell.com>

In reassembly path, next header field in IPv6 header is not
updated correctly, hence reassembled packet is corrupted.
This fix will consider IPv6 fragment header presence at start/mid/end in
extension list and update the next header field accordingly.

Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets")

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 982fd26045..41d11349fd 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -205,26 +205,36 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const uint8_t *m_ipptr,
 		struct rte_ipv6_hdr *hdr = (struct rte_ipv6_hdr *)ipptr;
 		size_t ext_len = sizeof(struct rte_ipv6_hdr);
 		uint8_t *nxt_hdr = (uint8_t *)hdr;
+		uint8_t *nxt_proto = &hdr->proto;
 		int nh = hdr->proto;
 
 		*ihl = 0;
+		tot_len = 0;
 		while (nh != -EINVAL) {
 			nxt_hdr += ext_len;
 			*ihl += ext_len;
+			if (nh == IPPROTO_FRAGMENT) {
+				*nxt_proto = *nxt_hdr;
+				tot_len = *ihl;
+			}
 			nh = rte_ipv6_get_next_ext(nxt_hdr, nh, &ext_len);
+			nxt_proto = nxt_hdr;
 		}
 
 		/* Remove the frag header by moving header 8 bytes forward */
 		hdr->payload_len = rte_cpu_to_be_16(fragx_sum + *ihl -
 					8 - sizeof(struct rte_ipv6_hdr));
 
+		/* tot_len is sum of all IP header's length before fragment header */
 		rte_memcpy(rte_pktmbuf_mtod_offset(head, void *, 8),
 			   rte_pktmbuf_mtod(head, void *),
-			   lcptr + sizeof(struct rte_ipv6_hdr));
+			   lcptr + tot_len);
 
 		head->data_len -= 8;
 		head->data_off += 8;
 		head->pkt_len = lcptr + *ihl - 8 + fragx_sum;
+		/* ihl l3hdr size value should be up to fragment header for next frags */
+		*ihl = tot_len + 8;
 	}
 }
 
-- 
2.25.1

Re: [PATCH 31/31] net/cnxk: fixes for IPv6 header in reassembly

[Jerin Jacob]

On Fri, Aug 11, 2023 at 2:31 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Rahul Bhansali <rbhansali@marvell.com>
>
> In reassembly path, next header field in IPv6 header is not
> updated correctly, hence reassembled packet is corrupted.
> This fix will consider IPv6 fragment header presence at start/mid/end in
> extension list and update the next header field accordingly.
>
> Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets")
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

Adding following changeset with cc: stable@dpdk.org

Is it candidate for Cc: stable@dpdk.org backport?
        common/cnxk: fixes CGX promisc toggling
        common/cnxk: fix xstats for different packet sizes
        common/cnxk: fix leak in error path
        common/cnxk: fix different size bit operations
        common/cnxk: fix different size bit operations
        common/cnxk: fix BP threshold calculation
        common/cnxk: fix incorrect aura ID
        net/cnxk: fix CQ allocation
        net/cnxk: fix issue with GCC 4.8
        net/cnxk: fix uninitialized variable
        net/cnxk: fix usage of mbuf rearm data
        net/cnxk: fix uninitialized variable
        net/cnxk: fixes for IPv6 header in reassembly


Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks

commit 2c71d37506009777af406615d43fc421fd1412cc
Author: Rahul Bhansali <rbhansali@marvell.com>
Date:   Fri Aug 11 14:28:05 2023 +0530

    net/cnxk: fix IPv6 header reassembly

    In reassembly path, next header field in IPv6 header is not
    updated correctly, hence reassembled packet is corrupted.
    This fix will consider IPv6 fragment header presence at start/mid/end in
    extension list and update the next header field accordingly.

    Fixes: ec28231ed260 ("net/cnxk: support reassembly of
multi-segment packets")
    Cc: stable@dpdk.org

    Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

commit d2c7aa15b84246740beec23d68aa1351e5517a17
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:28:04 2023 +0530

    net/cnxk: add flag check for extension header when used

    send_hdr_ext is being used, but it may be null when
    the flag check for NIX_TX_NEED_EXT_HDR is not done.
    Hence added a check here to avoid null pointer dereference.

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit 0e6b7f09b3e11f487828c475b9d8286f970a74f1
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:28:03 2023 +0530

    net/cnxk: check returned value for null

    nix_mtr_find may return NULL in case MTR is not found.
    Hence checking the return value before using it.

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit 15f6a30bbfb4d884fceb15d42f7cca579067ddca
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:28:02 2023 +0530

    net/cnxk: fix uninitialized variable

    Shift may be uninitialized in certain case, initialize it.

    Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k")
    Cc: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit 031272db4a44e0f398a91bd36e605f3e1e675a9f
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:28:01 2023 +0530

    net/cnxk: fix usage of mbuf rearm data

    mbuf->rearm_data is a zero length array and it is being
    used to set data from that location.
    This shows an error in static code analysis.
    Hence it is typecast to a pointer which can be used to
    set values accordingly.

    Fixes: c062f5726f61 ("net/cnxk: support IP reassembly")
    Cc: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit db0e6258355d047575ede320fcf839ad7d4cc6ba
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:28:00 2023 +0530

    net/cnxk: fix uninitialized variable

    sa_base may be uninitialized in for cases. Initialize it.

    Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k")
    Cc: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit c4c50edebc3c2cd5f5d35810cfba5d913ad5df68
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:27:59 2023 +0530

    net/cnxk: update different size bit operations

    Certain bitwise operations are done with different
    sized operands which causes warnings in static code
    analysis. The necessary operands are typecast to remove
    the warning.

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit c950b013afeca04d17d9eb8206acac783376eae1
Author: Srujana Challa <schalla@marvell.com>
Date:   Fri Aug 11 14:27:58 2023 +0530

    net/cnxk: move MAC address set from init to configure

    Channel(rx_chan_base) is not available in the kernel at
    the time of nix probe. Hence, move the mac address set
    call from nix_device_init() to nix_device_configure().
    This fixes the issue on cn10kb, where traffic was not
    getting received when promiscuous is disabled.

    Signed-off-by: Srujana Challa <schalla@marvell.com>

commit 07f39d45590eed229696993760c937243a91206a
Author: Satha Rao <skoteshwar@marvell.com>
Date:   Fri Aug 11 14:27:57 2023 +0530

    net/cnxk: support rate limit in PFC TM tree

    SQ rate limit was different in PFC tree compared to regular rate
    limit tree.

    Signed-off-by: Satha Rao <skoteshwar@marvell.com>

commit dfeceb66ade867d212c70a18524aca33f94bd5d6
Author: Sunil Kumar Kori <skori@marvell.com>
Date:   Fri Aug 11 14:27:56 2023 +0530

    net/cnxk: add mapping of DMAC address indexes

    Add support to map DMAC address indexes during
    mac address add and remove operation.

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>

commit df58fc9ed25ddc3efb1be37f0765215a245bbef0
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date:   Fri Aug 11 14:27:55 2023 +0530

    net/cnxk: fix issue with GCC 4.8

    Fix issue with GCC 4.8 cross compilation of ARM64 for
    flexible vector conversions.

    Fixes: ec28231ed260 ("net/cnxk: support reassembly of
multi-segment packets")
    Cc: stable@dpdk.org

    Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

commit ad06e4384ef706638f872521656cd81fbcf8519a
Author: Satha Rao <skoteshwar@marvell.com>
Date:   Fri Aug 11 14:27:54 2023 +0530

    net/cnxk: fix CQ allocation

    Allocate number of CQs sufficient to handle completions of both
    RQs and SQs.

    Fixes: dd9446991212 ("net/cnxk: add transmit completion handler")
    Cc: stable@dpdk.org

    Signed-off-by: Satha Rao <skoteshwar@marvell.com>

commit 69194137a3e2649ffcafc0ea5760cda5dde758cf
Author: Pavan Nikhilesh <pbhagavatula@marvell.com>
Date:   Fri Aug 11 14:27:53 2023 +0530

    common/cnxk: fix incorrect aura ID

    The function `sso_hwgrp_alloc_xaq` expects aura ID, fix incorrectly
    passing aura handle to it.

    Fixes: 7e9a94909eea ("common/cnxk: realloc inline device XAQ AURA")
    Cc: stable@dpdk.org

    Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>

commit 2b2d3faa8d5c4a7d91e72feb9c750bb0baab43fc
Author: Kommula Shiva Shankar <kshankar@marvell.com>
Date:   Fri Aug 11 14:27:52 2023 +0530

    common/cnxk: enable CQ stashing

    This patch enables CQ stashing for better CQE
    processing performance

    Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>

commit ce99eb272ca6e958c6f4022f754c8df7ed165844
Author: Sunil Kumar Kori <skori@marvell.com>
Date:   Fri Aug 11 14:27:51 2023 +0530

    common/cnxk: expose different params for BP config

    Currently same bp percentage is applied on SPB and
    LPB pool but both pools can be configured with different
    BP level.

    Added one more parameter so that separate threshold parameters
    can be passed for SPB and LPB pools.

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>

commit 042d4df880469031412d43c037a769c577b22953
Author: Sunil Kumar Kori <skori@marvell.com>
Date:   Fri Aug 11 14:27:50 2023 +0530

    common/cnxk: allow same TC on multiple RQs

    To achieve actual PFC behavior, user needs to configure
    different TC on different aura so that PFC can be generated
    for specific TC but same TC can also configured on multiple
    RQs which has same configured aura.

    In this patch, aura with same BP configuration is allowed
    on multiple RQs.

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>

commit 2a14586dd1dd22c76393a1c7070a781b79b3b5a8
Author: Sunil Kumar Kori <skori@marvell.com>
Date:   Fri Aug 11 14:27:49 2023 +0530

    common/cnxk: fix BP threshold calculation

    Current macro to calculate BP threshold were evaluating incorrect
    threshold because aura_limit is first shifted by shift then
    percentage is calculated.

    While first percentage should be calculated and the resultant should be
    shifted by shift. So formula is updated accordingly.

    Fixes: cb4bfd6e7bdf ("event/cnxk: support Rx adapter")
    Cc: stable@dpdk.org

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>

commit c6f86d4d378a502e43ce876e09dc849d95a7bfb8
Author: Rahul Bhansali <rbhansali@marvell.com>
Date:   Fri Aug 11 14:27:48 2023 +0530

    common/cnxk: add API to get Rx chan count from NIX

    For SDP, provide an API to get Rx chan count from NIX as
    all channels are always active.

    Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

commit 8a9e44c11e8ac61a84bf5c1cb089ab29383e5936
Author: Srujana Challa <schalla@marvell.com>
Date:   Fri Aug 11 14:27:47 2023 +0530

    common/cnxk: sync MAC addr set mailbox structure

    Sync MAC address set mailbox format with kernel. And
    send match table index to the kernel to add the
    mac address. This fixes the issues on cn10kb, where
    traffic was not received when promiscuous is disabled
    and two ports are used.

    Signed-off-by: Srujana Challa <schalla@marvell.com>

commit ef88cbdf31cab8c0f384e8b46cd6f1630b4bbe9a
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:27:46 2023 +0530

    common/cnxk: remove unnecessary ROC API calls

    Removed the calls to roc_nix_num_rx[tx]_xstats which
    does a model check again for cn9k/cn10k.
    The model check is already done before the call in the
    same leg, hence not needed to call these APIs.

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit bdda357d9fc106ec5fba1e527d5abc9903ab295f
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:27:45 2023 +0530

    common/cnxk: fix different size bit operations

    Bitwise or is being done on relchan which is 32 bit,
    but the result is 64 bit, hence typecast to uint64_t.

    Fixes: 8f867a87b9c5 ("common/cnxk: enable SDP channel backpressure to TL4")
    Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")
    CC: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit b28fbdb946c6c8dfeca3a3ee1122397726036c64
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:27:44 2023 +0530

    common/cnxk: fix different size bit operations

    WORD_SIZE is made as unsigned long long so that
    bit operations are done on same size of variables.

    Fixes: 1ec23c7523b4 ("common/cnxk: support anti-replay check in SW
for cn9k")
    CC: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit fe2f65a00d573cb38bb729777bb54ada5d0113cf
Author: Akhil Goyal <gakhil@marvell.com>
Date:   Fri Aug 11 14:27:43 2023 +0530

    common/cnxk: fix leak in error path

    Fixed resource leak when pthread create fails in dev_init().

    Fixes: 1c7a4d37e73d ("common/cnxk: fix mailbox timeout due to deadlock")
    CC: stable@dpdk.org

    Signed-off-by: Akhil Goyal <gakhil@marvell.com>

commit 2b82385bab1142036b61169be1d5c07c29bb8d81
Author: Satha Rao <skoteshwar@marvell.com>
Date:   Fri Aug 11 14:27:42 2023 +0530

    common/cnxk: disable BP on SDP link while closing SQ

    Host SDP port closes the SDP link on NIX causes crash when
    BP enabled on SDP link. This patch disables BP on SDP link
    when SQ flush fails due to link disabled at host.

    Signed-off-by: Satha Rao <skoteshwar@marvell.com>

commit 5307971ae312eeaa7bd062205e5f5a954f437f29
Author: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Date:   Fri Aug 11 14:27:41 2023 +0530

    common/cnxk: fix xstats for different packet sizes

    xstats for transmitted packets with different sizes
    are not updated as sizeof mailbox response structure
    are different in DPDK and kernel. This patch fixes the
    same.

    Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response
definitions")
    CC: stable@dpdk.org

    Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>

commit 72aeb217bf6ee71e53755bc6d3f2c123a3d70826
Author: Rahul Bhansali <rbhansali@marvell.com>
Date:   Fri Aug 11 14:27:40 2023 +0530

    common/cnxk: fix CGX promiscuous toggling

    Allow CGX promiscuous toggling even when exact match feature is enabled.
    Also, In case of exact feature, CGX promiscuous enable/disable mailbox
    response returns failure code -1101 in case if no change in the state.
    This failure code can be ignored and proceed further.

    Fixes: a90649722b51 ("common/cnxk: skip CGX promisc mode with NPC
exact match")
    CC: stable@dpdk.org

    Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

commit f12b398c331ff011a8f51937338832f8f30d8e47
Author: Satha Rao <skoteshwar@marvell.com>
Date:   Fri Aug 11 14:27:39 2023 +0530

    common/cnxk: support rate limit on PFC TM tree

    New SQ rate limit API to support SQ rate limit on PFC tree.
    In PFC tree each SQ had its one to one mapped TL3, this patch
    configures shaper rate on TL3. Also configures the TL2 with
    link rate.

    Signed-off-by: Satha Rao <skoteshwar@marvell.com>

commit dc82880872e17950c118d61b6055fd4d02caf8bd
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date:   Fri Aug 11 14:27:38 2023 +0530

    common/cnxk: add workaround for CPT ctx fetch issue

    Add workaround for CPT context fetch issue in CN10KB
    by setting CTX_ILEN to that of CTX_SIZE and enabling
    FLR_FLUSH in CPT_LF_CTX_CTL.

    Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

commit fcb9f3e796c5481ff63464d2c039925337c89de6
Author: Satha Rao <skoteshwar@marvell.com>
Date:   Fri Aug 11 14:27:37 2023 +0530

    common/cnxk: use only user SQB slack when provided

    This patch preferred user provided argument while configuring slack.
    If no platform argument given then by default MAX(24, 30% of SQ size)
    was configured as slack. Currently even if user provided SQB slack,
    it take max of internally calculated value and user given one.

    Signed-off-by: Satha Rao <skoteshwar@marvell.com>

commit 01949e68299f1bc1fea53704cf1bdcdea7c7d478
Author: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Date:   Fri Aug 11 14:27:36 2023 +0530

    common/cnxk: optimize FC configure time on VF

    PFC configuration function is taking 8 ms due
    to mailbox communication to check whether SSO is
    connected to RQ and whether back pressure is enabled
    on each AURA. To optimize this time, updating AURA
    attributes in nixlf and sso_ena parameter in RQ during
    write configuration and the same updated value is
    accessed while configuring flow control, reducing time to 6 ms.

    Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>

commit c010ea427d1d1566784066750b27821bafc6b9fe
Author: Sunil Kumar Kori <skori@marvell.com>
Date:   Fri Aug 11 14:27:35 2023 +0530

    common/cnxk: add aura reference count mechanism

    Each RQ can be associated with lpb_aura and spb_aura.
    lpb_aura or spb_aura is shared across multiple RQs then
    cleanup via one RQ will reset the aura context.

    To prevent, adding reference count mechanism.

    Signed-off-by: Sunil Kumar Kori <skori@marvell.com>