From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Cyril Chemparathy <cchemparathy@ezchip.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on element alignment
Date: Tue, 23 Jun 2015 00:31:06 +0000 [thread overview]
Message-ID: <2601191342CEEE43887BDE71AB97725836A1CDB8@irsmsx105.ger.corp.intel.com> (raw)
In-Reply-To: <1434999524-26528-9-git-send-email-cchemparathy@ezchip.com>
Hi Cyril,
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Cyril Chemparathy
> Sent: Monday, June 22, 2015 7:59 PM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on element alignment
>
> On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware
> buffer manager require a 128-byte alignment. With this change, we
> allow configuration based override of the element alignment, and
> default to RTE_CACHE_LINE_SIZE if left unspecified.
>
> Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7
> Signed-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>
> ---
> lib/librte_mempool/rte_mempool.c | 16 +++++++++-------
> lib/librte_mempool/rte_mempool.h | 6 ++++++
> 2 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c
> index 002d3a8..7656b0f 100644
> --- a/lib/librte_mempool/rte_mempool.c
> +++ b/lib/librte_mempool/rte_mempool.c
> @@ -120,10 +120,10 @@ static unsigned optimize_object_size(unsigned obj_size)
> nrank = 1;
>
> /* process new object size */
> - new_obj_size = (obj_size + RTE_CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE;
> + new_obj_size = (obj_size + RTE_MEMPOOL_ALIGN_MASK) / RTE_MEMPOOL_ALIGN;
> while (get_gcd(new_obj_size, nrank * nchan) != 1)
> new_obj_size++;
> - return new_obj_size * RTE_CACHE_LINE_SIZE;
> + return new_obj_size * RTE_MEMPOOL_ALIGN;
> }
>
> static void
> @@ -267,7 +267,7 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,
> #endif
> if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0)
> sz->header_size = RTE_ALIGN_CEIL(sz->header_size,
> - RTE_CACHE_LINE_SIZE);
> + RTE_MEMPOOL_ALIGN);
>
> /* trailer contains the cookie in debug mode */
> sz->trailer_size = 0;
> @@ -281,9 +281,9 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,
> if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) {
> sz->total_size = sz->header_size + sz->elt_size +
> sz->trailer_size;
> - sz->trailer_size += ((RTE_CACHE_LINE_SIZE -
> - (sz->total_size & RTE_CACHE_LINE_MASK)) &
> - RTE_CACHE_LINE_MASK);
> + sz->trailer_size += ((RTE_MEMPOOL_ALIGN -
> + (sz->total_size & RTE_MEMPOOL_ALIGN_MASK)) &
> + RTE_MEMPOOL_ALIGN_MASK);
> }
>
> /*
> @@ -498,7 +498,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
> * cache-aligned
> */
> private_data_size = (private_data_size +
> - RTE_CACHE_LINE_MASK) & (~RTE_CACHE_LINE_MASK);
> + RTE_MEMPOOL_ALIGN_MASK) & (~RTE_MEMPOOL_ALIGN_MASK);
>
> if (! rte_eal_has_hugepages()) {
> /*
> @@ -525,6 +525,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
> * enough to hold mempool header and metadata plus mempool objects.
> */
> mempool_size = MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size;
> + mempool_size = RTE_ALIGN_CEIL(mempool_size, RTE_MEMPOOL_ALIGN);
> if (vaddr == NULL)
> mempool_size += (size_t)objsz.total_size * n;
>
> @@ -580,6 +581,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,
> /* calculate address of the first element for continuous mempool. */
> obj = (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) +
> private_data_size;
> + obj = RTE_PTR_ALIGN_CEIL(obj, RTE_MEMPOOL_ALIGN);
>
> /* populate address translation fields. */
> mp->pg_num = pg_num;
> diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h
> index 380d60b..9321b86 100644
> --- a/lib/librte_mempool/rte_mempool.h
> +++ b/lib/librte_mempool/rte_mempool.h
> @@ -142,6 +142,12 @@ struct rte_mempool_objsz {
> /** Mempool over one chunk of physically continuous memory */
> #define MEMPOOL_PG_NUM_DEFAULT 1
>
> +#ifndef RTE_MEMPOOL_ALIGN
> +#define RTE_MEMPOOL_ALIGN RTE_CACHE_LINE_SIZE
> +#endif
> +
> +#define RTE_MEMPOOL_ALIGN_MASK (RTE_MEMPOOL_ALIGN - 1)
I am probably a bit late with my comments, but why not make it a runtime decision then?
I know we can't add a new parameter to mempool_xmem_create() without ABI breakage,
but we can make some global variable for now, that could be setup at init time or something similar.
> +
> /**
> * Mempool object header structure
> *
> --
> 2.1.2
next prev parent reply other threads:[~2015-06-23 0:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1434999524-26528-1-git-send-email-cchemparathy@ezchip.com>
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 01/12] test: limit x86 cpuflags checks to x86 builds Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 02/12] hash: fix compilation on non-X86 platforms Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 03/12] hash: check SSE flags only on x86 builds Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 04/12] eal: allow empty compile time flags Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 05/12] config: remove RTE_LIBNAME definition Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 06/12] memzone: refactor rte_memzone_reserve() variants Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 07/12] memzone: allow multiple pagesizes to be requested Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 08/12] mempool: allow config override on element alignment Cyril Chemparathy
2015-06-23 0:31 ` Ananyev, Konstantin [this message]
2015-06-23 20:43 ` Cyril Chemparathy
2015-06-23 21:21 ` Ananyev, Konstantin
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 09/12] tile: add page sizes for TILE-Gx/Mx platforms Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 10/12] tile: initial TILE-Gx support Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 11/12] tile: Add TILE-Gx mPIPE poll mode driver Cyril Chemparathy
2015-06-22 18:58 ` [dpdk-dev] [PATCH v2 12/12] maintainers: claim responsibility for TILE-Gx platform Cyril Chemparathy
2015-06-24 16:42 ` [dpdk-dev] [PATCH v2 00/12] Introducing the " Cyril Chemparathy
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