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* [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3
@ 2021-04-28 14:41 Adam Dybkowski
  2021-04-28 14:41 ` [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on " Adam Dybkowski
  2021-04-28 15:08 ` [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for " Zhang, Roy Fan
  0 siblings, 2 replies; 5+ messages in thread
From: Adam Dybkowski @ 2021-04-28 14:41 UTC (permalink / raw)
  To: dev, roy.fan.zhang, arkadiuszx.kusztal, gakhil; +Cc: Adam Dybkowski

This patch increases the intermediate buffer size used for the
compression on QAT GEN3 to accommodate new hardware versions.

Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index e6337c688d..9c6a3ca4e6 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -29,7 +29,7 @@ struct qat_dev_cmd_param {
 enum qat_comp_num_im_buffers {
 	QAT_NUM_INTERM_BUFS_GEN1 = 12,
 	QAT_NUM_INTERM_BUFS_GEN2 = 20,
-	QAT_NUM_INTERM_BUFS_GEN3 = 20
+	QAT_NUM_INTERM_BUFS_GEN3 = 64
 };
 
 struct qat_device_info {
-- 
2.25.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on QAT GEN3
  2021-04-28 14:41 [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3 Adam Dybkowski
@ 2021-04-28 14:41 ` Adam Dybkowski
  2021-04-28 15:10   ` Zhang, Roy Fan
  2021-04-28 15:08 ` [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for " Zhang, Roy Fan
  1 sibling, 1 reply; 5+ messages in thread
From: Adam Dybkowski @ 2021-04-28 14:41 UTC (permalink / raw)
  To: dev, roy.fan.zhang, arkadiuszx.kusztal, gakhil; +Cc: Adam Dybkowski

This patch enables the compression on QAT GEN3 (on hardware
versions that support it) and changes the error message shown
on older hardware versions that don't support the compression.

It also fixes the crash that happened on IM buffer allocation
failure (not enough memory) during the PMD cleaning phase.

Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
Fixes: 352332744c3a ("compress/qat: add dynamic SGL allocation")

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/compress/qat/qat_comp.c     |   7 +-
 drivers/compress/qat/qat_comp_pmd.c | 111 +++++++++++++++++++---------
 2 files changed, 79 insertions(+), 39 deletions(-)

diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index 3a064ec3b2..7ac25a3b4c 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -191,8 +191,8 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,
 					ICP_QAT_FW_COMP_EOP
 				      : ICP_QAT_FW_COMP_NOT_EOP,
 				ICP_QAT_FW_COMP_NOT_BFINAL,
-				ICP_QAT_FW_COMP_NO_CNV,
-				ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+				ICP_QAT_FW_COMP_CNV,
+				ICP_QAT_FW_COMP_CNV_RECOVERY);
 	}
 
 	/* common for sgl and flat buffers */
@@ -603,7 +603,8 @@ qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie,
 			rx_op->status = RTE_COMP_OP_STATUS_ERROR;
 			rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
 			*op = (void *)rx_op;
-			QAT_DP_LOG(ERR, "QAT has wrong firmware");
+			QAT_DP_LOG(ERR,
+					"This QAT hardware doesn't support compression operation");
 			++(*dequeue_err_count);
 			return 1;
 		}
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 18ecb34ba7..8de41f6b6e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -82,13 +82,13 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
 	qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
 						= NULL;
 
-	for (i = 0; i < qp->nb_descriptors; i++) {
-
-		struct qat_comp_op_cookie *cookie = qp->op_cookies[i];
+	if (qp != NULL)
+		for (i = 0; i < qp->nb_descriptors; i++) {
+			struct qat_comp_op_cookie *cookie = qp->op_cookies[i];
 
-		rte_free(cookie->qat_sgl_src_d);
-		rte_free(cookie->qat_sgl_dst_d);
-	}
+			rte_free(cookie->qat_sgl_src_d);
+			rte_free(cookie->qat_sgl_dst_d);
+		}
 
 	return qat_qp_release((struct qat_qp **)
 			&(dev->data->queue_pairs[queue_pair_id]));
@@ -198,7 +198,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
 	struct array_of_ptrs *array_of_pointers;
 	int size_of_ptr_array;
 	uint32_t full_size;
-	uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+	uint32_t offset_of_flat_buffs;
 	int i;
 	int num_im_sgls = qat_gen_config[
 		comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
@@ -213,31 +213,31 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
 		return memzone;
 	}
 
-	/* Create a memzone to hold intermediate buffers and associated
-	 * meta-data needed by the firmware. The memzone contains 3 parts:
+	/* Create multiple memzones to hold intermediate buffers and associated
+	 * meta-data needed by the firmware.
+	 * The first memzone contains:
 	 *  - a list of num_im_sgls physical pointers to sgls
-	 *  - the num_im_sgl sgl structures, each pointing to
-	 *    QAT_NUM_BUFS_IN_IM_SGL flat buffers
-	 *  - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL
-	 *    buffers, each of buff_size
+	 * All other memzones contain:
+	 *  - the sgl structure, pointing to QAT_NUM_BUFS_IN_IM_SGL flat buffers
+	 *  - the flat buffers: QAT_NUM_BUFS_IN_IM_SGL buffers,
+	 *    each of buff_size
 	 * num_im_sgls depends on the hardware generation of the device
 	 * buff_size comes from the user via the config file
 	 */
 
 	size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
-	offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
-			& QAT_64_BYTE_ALIGN_MASK;
-	offset_of_flat_buffs =
-	    offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+	offset_of_flat_buffs = sizeof(struct qat_inter_sgl);
 	full_size = offset_of_flat_buffs +
-			num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+			buff_size * QAT_NUM_BUFS_IN_IM_SGL;
 
-	memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+	memzone = rte_memzone_reserve_aligned(inter_buff_mz_name,
+			size_of_ptr_array,
 			comp_dev->compressdev->data->socket_id,
 			RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN);
 	if (memzone == NULL) {
-		QAT_LOG(ERR, "Can't allocate intermediate buffers"
-				" for device %s", comp_dev->qat_dev->name);
+		QAT_LOG(ERR,
+				"Can't allocate intermediate buffers for device %s",
+				comp_dev->qat_dev->name);
 		return NULL;
 	}
 
@@ -246,17 +246,50 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
 	QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
 			", size required %d, size created %zu",
 			inter_buff_mz_name, mz_start, mz_start_phys,
-			full_size, memzone->len);
+			size_of_ptr_array, memzone->len);
 
 	array_of_pointers = (struct array_of_ptrs *)mz_start;
 	for (i = 0; i < num_im_sgls; i++) {
-		uint32_t curr_sgl_offset =
-		    offset_of_sgls + i * sizeof(struct qat_inter_sgl);
-		struct qat_inter_sgl *sgl =
-		    (struct qat_inter_sgl *)(mz_start +	curr_sgl_offset);
+		const struct rte_memzone *mz;
+		struct qat_inter_sgl *sgl;
 		int lb;
-		array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
 
+		snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+				"%s_inter_buff_%d", comp_dev->qat_dev->name, i);
+		mz = rte_memzone_lookup(inter_buff_mz_name);
+		if (mz == NULL) {
+			mz = rte_memzone_reserve_aligned(inter_buff_mz_name,
+					full_size,
+					comp_dev->compressdev->data->socket_id,
+					RTE_MEMZONE_IOVA_CONTIG,
+					QAT_64_BYTE_ALIGN);
+			if (mz == NULL) {
+				QAT_LOG(ERR,
+						"Can't allocate intermediate buffers for device %s",
+						comp_dev->qat_dev->name);
+				while (--i >= 0) {
+					snprintf(inter_buff_mz_name,
+							RTE_MEMZONE_NAMESIZE,
+							"%s_inter_buff_%d",
+							comp_dev->qat_dev->name,
+							i);
+					rte_memzone_free(
+							rte_memzone_lookup(
+							inter_buff_mz_name));
+				}
+				rte_memzone_free(memzone);
+				return NULL;
+			}
+		}
+
+		QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64
+				", size required %d, size created %zu",
+				inter_buff_mz_name, mz->addr, mz->iova,
+				full_size, mz->len);
+
+		array_of_pointers->pointer[i] = mz->iova;
+
+		sgl = (struct qat_inter_sgl *) mz->addr;
 		sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
 		sgl->num_mapped_bufs = 0;
 		sgl->resrvd = 0;
@@ -268,8 +301,8 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
 #endif
 		for (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) {
 			sgl->buffers[lb].addr =
-			  mz_start_phys + offset_of_flat_buffs +
-			  (((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size);
+					mz->iova + offset_of_flat_buffs +
+					lb * buff_size;
 			sgl->buffers[lb].len = buff_size;
 			sgl->buffers[lb].resrvd = 0;
 #if QAT_IM_BUFFER_DEBUG
@@ -281,7 +314,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
 	}
 #if QAT_IM_BUFFER_DEBUG
 	QAT_DP_HEXDUMP_LOG(DEBUG,  "IM buffer memzone start:",
-			mz_start, offset_of_flat_buffs + 32);
+			memzone->addr, size_of_ptr_array);
 #endif
 	return memzone;
 }
@@ -444,6 +477,16 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
 {
 	/* Free intermediate buffers */
 	if (comp_dev->interm_buff_mz) {
+		char mz_name[RTE_MEMZONE_NAMESIZE];
+		int i = qat_gen_config[
+		      comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;
+
+		while (--i >= 0) {
+			snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
+					"%s_inter_buff_%d",
+					comp_dev->qat_dev->name, i);
+			rte_memzone_free(rte_memzone_lookup(mz_name));
+		}
 		rte_memzone_free(comp_dev->interm_buff_mz);
 		comp_dev->interm_buff_mz = NULL;
 	}
@@ -607,7 +650,8 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,
 
 			tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
 					&compress_qat_dummy_ops;
-			QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+			QAT_LOG(ERR,
+					"This QAT hardware doesn't support compression operation");
 
 		} else {
 			tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
@@ -656,11 +700,6 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,
 	int i = 0;
 	struct qat_device_info *qat_dev_instance =
 			&qat_pci_devs[qat_pci_dev->qat_dev_id];
-	if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
-		QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
-		return 0;
-	}
-
 	struct rte_compressdev_pmd_init_params init_params = {
 		.name = "",
 		.socket_id = qat_dev_instance->pci_dev->device.numa_node,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3
  2021-04-28 14:41 [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3 Adam Dybkowski
  2021-04-28 14:41 ` [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on " Adam Dybkowski
@ 2021-04-28 15:08 ` Zhang, Roy Fan
  2021-05-05 14:48   ` Akhil Goyal
  1 sibling, 1 reply; 5+ messages in thread
From: Zhang, Roy Fan @ 2021-04-28 15:08 UTC (permalink / raw)
  To: Dybkowski, AdamX, dev, Kusztal, ArkadiuszX, gakhil

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Wednesday, April 28, 2021 3:42 PM
> To: dev@dpdk.org; Zhang, Roy Fan <roy.fan.zhang@intel.com>; Kusztal,
> ArkadiuszX <arkadiuszx.kusztal@intel.com>; gakhil@marvell.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3
> 
> This patch increases the intermediate buffer size used for the
> compression on QAT GEN3 to accommodate new hardware versions.
> 
> Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> ---
>  drivers/common/qat/qat_device.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/common/qat/qat_device.h
> b/drivers/common/qat/qat_device.h
> index e6337c688d..9c6a3ca4e6 100644
> --- a/drivers/common/qat/qat_device.h
> +++ b/drivers/common/qat/qat_device.h
> @@ -29,7 +29,7 @@ struct qat_dev_cmd_param {
>  enum qat_comp_num_im_buffers {
>  	QAT_NUM_INTERM_BUFS_GEN1 = 12,
>  	QAT_NUM_INTERM_BUFS_GEN2 = 20,
> -	QAT_NUM_INTERM_BUFS_GEN3 = 20
> +	QAT_NUM_INTERM_BUFS_GEN3 = 64
>  };
> 
>  struct qat_device_info {
> --
> 2.25.1

Acked-by: Fan Zhang <roy.fan.zhang@intel.com>


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on QAT GEN3
  2021-04-28 14:41 ` [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on " Adam Dybkowski
@ 2021-04-28 15:10   ` Zhang, Roy Fan
  0 siblings, 0 replies; 5+ messages in thread
From: Zhang, Roy Fan @ 2021-04-28 15:10 UTC (permalink / raw)
  To: Dybkowski, AdamX, dev, Kusztal, ArkadiuszX, gakhil

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Wednesday, April 28, 2021 3:42 PM
> To: dev@dpdk.org; Zhang, Roy Fan <roy.fan.zhang@intel.com>; Kusztal,
> ArkadiuszX <arkadiuszx.kusztal@intel.com>; gakhil@marvell.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH 2/2] compress/qat: enable compression on QAT GEN3
> 
> This patch enables the compression on QAT GEN3 (on hardware
> versions that support it) and changes the error message shown
> on older hardware versions that don't support the compression.
> 
> It also fixes the crash that happened on IM buffer allocation
> failure (not enough memory) during the PMD cleaning phase.
> 
> Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
> Fixes: 352332744c3a ("compress/qat: add dynamic SGL allocation")
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> ---

Acked-by: Fan Zhang <roy.fan.zhang@intel.com>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3
  2021-04-28 15:08 ` [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for " Zhang, Roy Fan
@ 2021-05-05 14:48   ` Akhil Goyal
  0 siblings, 0 replies; 5+ messages in thread
From: Akhil Goyal @ 2021-05-05 14:48 UTC (permalink / raw)
  To: Zhang, Roy Fan, Dybkowski, AdamX, dev, Kusztal, ArkadiuszX; +Cc: stable

> > Subject: [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3
> >
> > This patch increases the intermediate buffer size used for the
> > compression on QAT GEN3 to accommodate new hardware versions.
> >
> > Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
> >
> > Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> > ---
Series applied to dpdk-next-crypto

Cc: stable@dpdk.org for both patches.

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-05-05 14:48 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-28 14:41 [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for QAT GEN3 Adam Dybkowski
2021-04-28 14:41 ` [dpdk-dev] [PATCH 2/2] compress/qat: enable compression on " Adam Dybkowski
2021-04-28 15:10   ` Zhang, Roy Fan
2021-04-28 15:08 ` [dpdk-dev] [PATCH 1/2] common/qat: increase IM buffer size for " Zhang, Roy Fan
2021-05-05 14:48   ` Akhil Goyal

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