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From: Shahaf Shuler <shahafs@mellanox.com>
To: nelio.laranjeiro@6wind.com, adrien.mazarguil@6wind.com
Cc: dev@dpdk.org, Yongseok Koh <yskoh@mellanox.com>,
	Alexander Solganik <solganik@gmail.com>,
	Sagi Grimberg <sagi@grimberg.me>
Subject: [dpdk-dev] [PATCH v2 1/2] net/mlx5: replace memory barrier type
Date: Sun, 27 Aug 2017 09:47:08 +0300	[thread overview]
Message-ID: <ad6f6fa1d198e00e071e0847d35aac74f15abbe6.1503816096.git.shahafs@mellanox.com> (raw)
In-Reply-To: <cover.1503816096.git.shahafs@mellanox.com>

The reason for the requirement of a barrier between the txq writes
and the doorbell record writes is to avoid a case where the device
reads the doorbell record's new value before the txq writes are flushed
to memory.

The current use of rte_wmb is not necessary, and can be replaced by
rte_io_wmb which is more relaxed.

Replacing the rte_wmb is also expected to improve the throughput.

on v2:
 * replace compiler barrier with rte_io_wmb.

Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Alexander Solganik <solganik@gmail.com>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
---
 drivers/net/mlx5/mlx5_rxtx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index b3b161da5..e9895a9c0 100644
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -591,7 +591,7 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 	uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 	volatile uint64_t *src = ((volatile uint64_t *)wqe);
 
-	rte_wmb();
+	rte_io_wmb();
 	*txq->qp_db = htonl(txq->wqe_ci);
 	/* Ensure ordering between DB record and BF copy. */
 	rte_wmb();
-- 
2.12.0

  reply	other threads:[~2017-08-27  6:47 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-21  7:47 [dpdk-dev] [PATCH 0/2] mlx5 high latency observed on send operations Sagi Grimberg
2017-08-21  7:47 ` [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type Sagi Grimberg
2017-08-23 11:39   ` Nélio Laranjeiro
2017-08-23 13:11     ` Bruce Richardson
2017-08-24  6:56       ` Shahaf Shuler
2017-08-24  9:27         ` Bruce Richardson
2017-08-21  7:47 ` [dpdk-dev] [PATCH 2/2] net/mlx5: don't map doorbell register to write combining Sagi Grimberg
2017-08-23 11:03   ` Ferruh Yigit
2017-08-23 12:06     ` Nélio Laranjeiro
2017-08-27  6:47 ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Shahaf Shuler
2017-08-27  6:47   ` Shahaf Shuler [this message]
2017-08-27  6:47   ` [dpdk-dev] [PATCH v2 2/2] net/mlx5: don't map doorbell register to write combining Shahaf Shuler
2017-08-29 16:53   ` [dpdk-dev] [PATCH v2 0/2] mlx5 high latency observed on send operations Ferruh Yigit

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