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From: Viacheslav Ovsiienko <>
Subject: [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion
Date: Tue, 24 Dec 2019 14:20:35 +0000
Message-ID: <> (raw)

The metadata register c0 field in the matcher might be split
into two independent fields - the source vport index and META
item value. These fields have no permanent assigned bits, the
configuration is queried from the kernel drivers.

It means the metadata item field might be less than 32 bits.
Also, the metadata are engaged in datapath and there are no
any metadata endianness conversions in datapath to provide the
better performance, all conversions are implemented in rte_flow
engine. If there are less than 32 bits of metadata the extra
right shift is needed after endianness conversion for little-
endian hosts.

Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")

Signed-off-by: Viacheslav Ovsiienko <>
 drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index f8e153c..cb416ca 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5903,8 +5903,12 @@ struct field_modify_info modify_tcp[] = {
 			struct mlx5_priv *priv = dev->data->dev_private;
 			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
 			uint32_t shl_c0 = rte_bsf32(msk_c0);
+			uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
-			msk_c0 = rte_cpu_to_be_32(msk_c0);
+			value >>= shr_c0;
+			mask >>= shr_c0;
 			value <<= shl_c0;
 			mask <<= shl_c0;

             reply	other threads:[~2019-12-24 14:20 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-24 14:20 Viacheslav Ovsiienko [this message]
2020-01-06 14:44 ` Matan Azrad
2020-01-08  9:03 ` Raslan Darawsheh
2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
2020-01-17 17:19   ` Ferruh Yigit

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