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* [dpdk-stable] [PATCH 1/2] test/hash: fix multiwriter with non consecutive cores
@ 2018-07-17 13:31 Pablo de Lara
  2018-07-17 13:31 ` [dpdk-stable] [PATCH 2/2] test/hash: fix potential memory leak Pablo de Lara
  2018-07-26 19:55 ` [dpdk-stable] [PATCH 1/2] test/hash: fix multiwriter with non consecutive cores Thomas Monjalon
  0 siblings, 2 replies; 3+ messages in thread
From: Pablo de Lara @ 2018-07-17 13:31 UTC (permalink / raw)
  To: bruce.richardson; +Cc: dev, Pablo de Lara, stable

When non consecutive cores are passed into the test application,
the distribution of the keys that each thread needs to insert
is not correct, since it assumes that there are no cores skipped
between the master core and the worker core.

Fixes: be856325cba3 ("hash: add scalable multi-writer insertion with Intel TSX")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
---
 test/test/test_hash_multiwriter.c | 41 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/test/test/test_hash_multiwriter.c b/test/test/test_hash_multiwriter.c
index f182f4052..acd6a91ca 100644
--- a/test/test/test_hash_multiwriter.c
+++ b/test/test/test_hash_multiwriter.c
@@ -48,18 +48,29 @@ static rte_atomic64_t ginsertions;
 static int use_htm;
 
 static int
-test_hash_multiwriter_worker(__attribute__((unused)) void *arg)
+test_hash_multiwriter_worker(void *arg)
 {
 	uint64_t i, offset;
+	uint16_t pos_core;
 	uint32_t lcore_id = rte_lcore_id();
 	uint64_t begin, cycles;
+	uint16_t *enabled_core_ids = (uint16_t *)arg;
 
-	offset = (lcore_id - rte_get_master_lcore())
-		* tbl_multiwriter_test_params.nb_tsx_insertion;
+	for (pos_core = 0; pos_core < rte_lcore_count(); pos_core++) {
+		if (enabled_core_ids[pos_core] == lcore_id)
+			break;
+	}
+
+	/*
+	 * Calculate offset for entries based on the position of the
+	 * logical core, from the master core (not counting not enabled cores)
+	 */
+	offset = pos_core * tbl_multiwriter_test_params.nb_tsx_insertion;
 
 	printf("Core #%d inserting %d: %'"PRId64" - %'"PRId64"\n",
 	       lcore_id, tbl_multiwriter_test_params.nb_tsx_insertion,
-	       offset, offset + tbl_multiwriter_test_params.nb_tsx_insertion);
+	       offset,
+	       offset + tbl_multiwriter_test_params.nb_tsx_insertion - 1);
 
 	begin = rte_rdtsc_precise();
 
@@ -88,6 +99,8 @@ test_hash_multiwriter(void)
 {
 	unsigned int i, rounded_nb_total_tsx_insertion;
 	static unsigned calledCount = 1;
+	uint16_t enabled_core_ids[RTE_MAX_LCORE];
+	uint16_t core_id;
 
 	uint32_t *keys;
 	uint32_t *found;
@@ -159,9 +172,27 @@ test_hash_multiwriter(void)
 	rte_atomic64_init(&ginsertions);
 	rte_atomic64_clear(&ginsertions);
 
+	/* Get list of enabled cores */
+	i = 0;
+	for (core_id = 0; core_id < RTE_MAX_LCORE; core_id++) {
+		if (i == rte_lcore_count())
+			break;
+
+		if (rte_lcore_is_enabled(core_id)) {
+			enabled_core_ids[i] = core_id;
+			i++;
+		}
+	}
+
+	if (i != rte_lcore_count()) {
+		printf("Number of enabled cores in list is different from "
+				"number given by rte_lcore_count()\n");
+		goto err3;
+	}
+
 	/* Fire all threads. */
 	rte_eal_mp_remote_launch(test_hash_multiwriter_worker,
-				 NULL, CALL_MASTER);
+				 enabled_core_ids, CALL_MASTER);
 	rte_eal_mp_wait_lcore();
 
 	count = rte_hash_count(handle);
-- 
2.14.4

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2018-07-26 19:55 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-17 13:31 [dpdk-stable] [PATCH 1/2] test/hash: fix multiwriter with non consecutive cores Pablo de Lara
2018-07-17 13:31 ` [dpdk-stable] [PATCH 2/2] test/hash: fix potential memory leak Pablo de Lara
2018-07-26 19:55 ` [dpdk-stable] [PATCH 1/2] test/hash: fix multiwriter with non consecutive cores Thomas Monjalon

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