[dpdk-stable] patch 'net/e1000: fix i219 hang on reset/close' has been queued to LTS release 18.11.6

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to LTS release 18.11.6

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/29/19. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable-queue

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable-queue/commit/0c97c2c11cb9408f35cebbb6aaf94ed45671ccbc

Thanks.

Kevin.

---
From 0c97c2c11cb9408f35cebbb6aaf94ed45671ccbc Mon Sep 17 00:00:00 2001
From: Xiao Zhang <xiao.zhang@intel.com>
Date: Mon, 22 Jul 2019 23:11:52 +0800
Subject: [PATCH] net/e1000: fix i219 hang on reset/close

[ upstream commit 1fc9701238edcf0541289b9ae15565b6d9d7ab30]
[ upstream commit 675f65dc660805eff1953e3dfb6242ec076a9444]

Squashing these commits because an issue was identified with
the first commit after it was applied on master but before
backported to stable. The second commit fixes the issue
introduced in the first commit.

commit 1fc9701238edcf0541289b9ae15565b6d9d7ab30
Author: Xiao Zhang <xiao.zhang@intel.com>
Date:   Mon Jul 22 23:11:52 2019 +0800

    net/e1000: fix i219 hang on reset/close

    Unit hang may occur if multiple descriptors are available in the rings
    during reset or close. This state can be detected by configure status
    by bit 8 in register. If the bit is set and there are pending
    descriptors in one of the rings, we must flush them before reset or
    close.

    Fixes: 805803445a02 ("e1000: support EM devices (also known as e1000/e1000e)")

    Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
    Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>

commit 675f65dc660805eff1953e3dfb6242ec076a9444
Author: Xiao Zhang <xiao.zhang@intel.com>
Date:   Wed Sep 11 01:40:55 2019 +0800

    net/e1000: fix MAC type checking

    The mac types of i219 are e1000_pch_spt and e1000_pch_cnp, correct the
    checking code of mac type when flushing i219 descriptor rings.

    Fixes: 1fc9701238ed ("net/e1000: fix i219 hang on reset/close")

    Reported-by: Kevin Traynor <ktraynor@redhat.com>
    Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
    Acked-by: Kevin Traynor <ktraynor@redhat.com>
    Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>

Signed-off-by: Kevin Traynor <ktraynor@redhat.com>
---
 drivers/net/e1000/e1000_ethdev.h |   4 ++
 drivers/net/e1000/em_ethdev.c    |   5 ++
 drivers/net/e1000/em_rxtx.c      | 111 +++++++++++++++++++++++++++++++
 3 files changed, 120 insertions(+)

diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h
index 94edff08e..78fb61e41 100644
--- a/drivers/net/e1000/e1000_ethdev.h
+++ b/drivers/net/e1000/e1000_ethdev.h
@@ -36,4 +36,7 @@
 #define IGB_MAX_RX_QUEUE_NUM_82576     16
 
+#define E1000_I219_MAX_RX_QUEUE_NUM		2
+#define E1000_I219_MAX_TX_QUEUE_NUM		2
+
 #define E1000_SYN_FILTER_ENABLE        0x00000001 /* syn filter enable field */
 #define E1000_SYN_FILTER_QUEUE         0x0000000E /* syn filter queue field */
@@ -516,4 +519,5 @@ int igb_config_rss_filter(struct rte_eth_dev *dev,
 			struct igb_rte_flow_rss_conf *conf,
 			bool add);
+void em_flush_desc_rings(struct rte_eth_dev *dev);
 
 #endif /* _E1000_ETHDEV_H_ */
diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
index 8230824e7..123c73053 100644
--- a/drivers/net/e1000/em_ethdev.c
+++ b/drivers/net/e1000/em_ethdev.c
@@ -738,4 +738,9 @@ eth_em_stop(struct rte_eth_dev *dev)
 
 	e1000_reset_hw(hw);
+
+	/* Flush desc rings for i219 */
+	if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
+		em_flush_desc_rings(dev);
+
 	if (hw->mac.type >= e1000_82544)
 		E1000_WRITE_REG(hw, E1000_WUC, 0);
diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c
index 67c7ec701..951d1642c 100644
--- a/drivers/net/e1000/em_rxtx.c
+++ b/drivers/net/e1000/em_rxtx.c
@@ -19,4 +19,5 @@
 #include <rte_debug.h>
 #include <rte_pci.h>
+#include <rte_bus_pci.h>
 #include <rte_memory.h>
 #include <rte_memcpy.h>
@@ -60,4 +61,9 @@
 		(PKT_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)
 
+/* PCI offset for querying configuration status register */
+#define PCI_CFG_STATUS_REG                 0x06
+#define FLUSH_DESC_REQUIRED               0x100
+
+
 /**
  * Structure associated with each descriptor of the RX ring of a RX queue.
@@ -2017,2 +2023,107 @@ em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 	qinfo->conf.offloads = txq->offloads;
 }
+
+static void
+e1000_flush_tx_ring(struct rte_eth_dev *dev)
+{
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	volatile struct e1000_data_desc *tx_desc;
+	volatile uint32_t *tdt_reg_addr;
+	uint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
+	uint16_t size = 512;
+	struct em_tx_queue *txq;
+	int i;
+
+	if (dev->data->tx_queues == NULL)
+		return;
+	tctl = E1000_READ_REG(hw, E1000_TCTL);
+	E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
+	for (i = 0; i < dev->data->nb_tx_queues &&
+		i < E1000_I219_MAX_TX_QUEUE_NUM; i++) {
+		txq = dev->data->tx_queues[i];
+		tdt = E1000_READ_REG(hw, E1000_TDT(i));
+		if (tdt != txq->tx_tail)
+			return;
+		tx_desc = &txq->tx_ring[txq->tx_tail];
+		tx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);
+		tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
+		tx_desc->upper.data = 0;
+
+		rte_wmb();
+		txq->tx_tail++;
+		if (txq->tx_tail == txq->nb_tx_desc)
+			txq->tx_tail = 0;
+		rte_io_wmb();
+		tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
+		E1000_PCI_REG_WRITE_RELAXED(tdt_reg_addr, txq->tx_tail);
+		usec_delay(250);
+	}
+}
+
+static void
+e1000_flush_rx_ring(struct rte_eth_dev *dev)
+{
+	uint32_t rctl, rxdctl;
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	int i;
+
+	rctl = E1000_READ_REG(hw, E1000_RCTL);
+	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
+	E1000_WRITE_FLUSH(hw);
+	usec_delay(150);
+
+	for (i = 0; i < dev->data->nb_rx_queues &&
+		i < E1000_I219_MAX_RX_QUEUE_NUM; i++) {
+		rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
+		/* zero the lower 14 bits (prefetch and host thresholds) */
+		rxdctl &= 0xffffc000;
+
+		/* update thresholds: prefetch threshold to 31,
+		 * host threshold to 1 and make sure the granularity
+		 * is "descriptors" and not "cache lines"
+		 */
+		rxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
+
+		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
+	}
+	/* momentarily enable the RX ring for the changes to take effect */
+	E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
+	E1000_WRITE_FLUSH(hw);
+	usec_delay(150);
+	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
+}
+
+/**
+ * em_flush_desc_rings - remove all descriptors from the descriptor rings
+ *
+ * In i219, the descriptor rings must be emptied before resetting/closing the
+ * HW. Failure to do this will cause the HW to enter a unit hang state which
+ * can only be released by PCI reset on the device
+ *
+ */
+
+void
+em_flush_desc_rings(struct rte_eth_dev *dev)
+{
+	uint32_t fextnvm11, tdlen;
+	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+	uint16_t pci_cfg_status = 0;
+
+	fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
+	E1000_WRITE_REG(hw, E1000_FEXTNVM11,
+			fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
+	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
+	rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
+				PCI_CFG_STATUS_REG);
+
+	/* do nothing if we're not in faulty state, or if the queue is empty */
+	if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
+		/* flush desc ring */
+		e1000_flush_tx_ring(dev);
+		rte_pci_read_config(pci_dev, &pci_cfg_status,
+				sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+		if (pci_cfg_status & FLUSH_DESC_REQUIRED)
+			e1000_flush_rx_ring(dev);
+	}
+}
-- 
2.21.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2019-11-22 14:36:57.543482433 +0000
+++ 0044-net-e1000-fix-i219-hang-on-reset-close.patch	2019-11-22 14:36:55.231148560 +0000
@@ -0,0 +1,216 @@
+From 0c97c2c11cb9408f35cebbb6aaf94ed45671ccbc Mon Sep 17 00:00:00 2001
+From: Xiao Zhang <xiao.zhang@intel.com>
+Date: Mon, 22 Jul 2019 23:11:52 +0800
+Subject: [PATCH] net/e1000: fix i219 hang on reset/close
+
+[ upstream commit 1fc9701238edcf0541289b9ae15565b6d9d7ab30]
+[ upstream commit 675f65dc660805eff1953e3dfb6242ec076a9444]
+
+Squashing these commits because an issue was identified with
+the first commit after it was applied on master but before
+backported to stable. The second commit fixes the issue
+introduced in the first commit.
+
+commit 1fc9701238edcf0541289b9ae15565b6d9d7ab30
+Author: Xiao Zhang <xiao.zhang@intel.com>
+Date:   Mon Jul 22 23:11:52 2019 +0800
+
+    net/e1000: fix i219 hang on reset/close
+
+    Unit hang may occur if multiple descriptors are available in the rings
+    during reset or close. This state can be detected by configure status
+    by bit 8 in register. If the bit is set and there are pending
+    descriptors in one of the rings, we must flush them before reset or
+    close.
+
+    Fixes: 805803445a02 ("e1000: support EM devices (also known as e1000/e1000e)")
+
+    Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
+    Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
+
+commit 675f65dc660805eff1953e3dfb6242ec076a9444
+Author: Xiao Zhang <xiao.zhang@intel.com>
+Date:   Wed Sep 11 01:40:55 2019 +0800
+
+    net/e1000: fix MAC type checking
+
+    The mac types of i219 are e1000_pch_spt and e1000_pch_cnp, correct the
+    checking code of mac type when flushing i219 descriptor rings.
+
+    Fixes: 1fc9701238ed ("net/e1000: fix i219 hang on reset/close")
+
+    Reported-by: Kevin Traynor <ktraynor@redhat.com>
+    Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
+    Acked-by: Kevin Traynor <ktraynor@redhat.com>
+    Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
+
+Signed-off-by: Kevin Traynor <ktraynor@redhat.com>
+---
+ drivers/net/e1000/e1000_ethdev.h |   4 ++
+ drivers/net/e1000/em_ethdev.c    |   5 ++
+ drivers/net/e1000/em_rxtx.c      | 111 +++++++++++++++++++++++++++++++
+ 3 files changed, 120 insertions(+)
+
+diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h
+index 94edff08e..78fb61e41 100644
+--- a/drivers/net/e1000/e1000_ethdev.h
++++ b/drivers/net/e1000/e1000_ethdev.h
+@@ -36,4 +36,7 @@
+ #define IGB_MAX_RX_QUEUE_NUM_82576     16
+ 
++#define E1000_I219_MAX_RX_QUEUE_NUM		2
++#define E1000_I219_MAX_TX_QUEUE_NUM		2
++
+ #define E1000_SYN_FILTER_ENABLE        0x00000001 /* syn filter enable field */
+ #define E1000_SYN_FILTER_QUEUE         0x0000000E /* syn filter queue field */
+@@ -516,4 +519,5 @@ int igb_config_rss_filter(struct rte_eth_dev *dev,
+ 			struct igb_rte_flow_rss_conf *conf,
+ 			bool add);
++void em_flush_desc_rings(struct rte_eth_dev *dev);
+ 
+ #endif /* _E1000_ETHDEV_H_ */
+diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
+index 8230824e7..123c73053 100644
+--- a/drivers/net/e1000/em_ethdev.c
++++ b/drivers/net/e1000/em_ethdev.c
+@@ -738,4 +738,9 @@ eth_em_stop(struct rte_eth_dev *dev)
+ 
+ 	e1000_reset_hw(hw);
++
++	/* Flush desc rings for i219 */
++	if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
++		em_flush_desc_rings(dev);
++
+ 	if (hw->mac.type >= e1000_82544)
+ 		E1000_WRITE_REG(hw, E1000_WUC, 0);
+diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c
+index 67c7ec701..951d1642c 100644
+--- a/drivers/net/e1000/em_rxtx.c
++++ b/drivers/net/e1000/em_rxtx.c
+@@ -19,4 +19,5 @@
+ #include <rte_debug.h>
+ #include <rte_pci.h>
++#include <rte_bus_pci.h>
+ #include <rte_memory.h>
+ #include <rte_memcpy.h>
+@@ -60,4 +61,9 @@
+ 		(PKT_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)
+ 
++/* PCI offset for querying configuration status register */
++#define PCI_CFG_STATUS_REG                 0x06
++#define FLUSH_DESC_REQUIRED               0x100
++
++
+ /**
+  * Structure associated with each descriptor of the RX ring of a RX queue.
+@@ -2017,2 +2023,107 @@ em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
+ 	qinfo->conf.offloads = txq->offloads;
+ }
++
++static void
++e1000_flush_tx_ring(struct rte_eth_dev *dev)
++{
++	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
++	volatile struct e1000_data_desc *tx_desc;
++	volatile uint32_t *tdt_reg_addr;
++	uint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
++	uint16_t size = 512;
++	struct em_tx_queue *txq;
++	int i;
++
++	if (dev->data->tx_queues == NULL)
++		return;
++	tctl = E1000_READ_REG(hw, E1000_TCTL);
++	E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
++	for (i = 0; i < dev->data->nb_tx_queues &&
++		i < E1000_I219_MAX_TX_QUEUE_NUM; i++) {
++		txq = dev->data->tx_queues[i];
++		tdt = E1000_READ_REG(hw, E1000_TDT(i));
++		if (tdt != txq->tx_tail)
++			return;
++		tx_desc = &txq->tx_ring[txq->tx_tail];
++		tx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);
++		tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
++		tx_desc->upper.data = 0;
++
++		rte_wmb();
++		txq->tx_tail++;
++		if (txq->tx_tail == txq->nb_tx_desc)
++			txq->tx_tail = 0;
++		rte_io_wmb();
++		tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
++		E1000_PCI_REG_WRITE_RELAXED(tdt_reg_addr, txq->tx_tail);
++		usec_delay(250);
++	}
++}
++
++static void
++e1000_flush_rx_ring(struct rte_eth_dev *dev)
++{
++	uint32_t rctl, rxdctl;
++	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
++	int i;
++
++	rctl = E1000_READ_REG(hw, E1000_RCTL);
++	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
++	E1000_WRITE_FLUSH(hw);
++	usec_delay(150);
++
++	for (i = 0; i < dev->data->nb_rx_queues &&
++		i < E1000_I219_MAX_RX_QUEUE_NUM; i++) {
++		rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
++		/* zero the lower 14 bits (prefetch and host thresholds) */
++		rxdctl &= 0xffffc000;
++
++		/* update thresholds: prefetch threshold to 31,
++		 * host threshold to 1 and make sure the granularity
++		 * is "descriptors" and not "cache lines"
++		 */
++		rxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
++
++		E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
++	}
++	/* momentarily enable the RX ring for the changes to take effect */
++	E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
++	E1000_WRITE_FLUSH(hw);
++	usec_delay(150);
++	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
++}
++
++/**
++ * em_flush_desc_rings - remove all descriptors from the descriptor rings
++ *
++ * In i219, the descriptor rings must be emptied before resetting/closing the
++ * HW. Failure to do this will cause the HW to enter a unit hang state which
++ * can only be released by PCI reset on the device
++ *
++ */
++
++void
++em_flush_desc_rings(struct rte_eth_dev *dev)
++{
++	uint32_t fextnvm11, tdlen;
++	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
++	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
++	uint16_t pci_cfg_status = 0;
++
++	fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
++	E1000_WRITE_REG(hw, E1000_FEXTNVM11,
++			fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
++	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
++	rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
++				PCI_CFG_STATUS_REG);
++
++	/* do nothing if we're not in faulty state, or if the queue is empty */
++	if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
++		/* flush desc ring */
++		e1000_flush_tx_ring(dev);
++		rte_pci_read_config(pci_dev, &pci_cfg_status,
++				sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
++		if (pci_cfg_status & FLUSH_DESC_REQUIRED)
++			e1000_flush_rx_ring(dev);
++	}
++}
+-- 
+2.21.0
+