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* [dpdk-stable] [PATCH v1 1/2] raw/ifpga/base: fix spi transaction issue
@ 2020-07-09 16:35 Tianfei zhang
  2020-07-14 21:35 ` [dpdk-stable] [PATCH v3 " Tianfei zhang
  0 siblings, 1 reply; 6+ messages in thread
From: Tianfei zhang @ 2020-07-09 16:35 UTC (permalink / raw)
  To: dev, rosen.xu; +Cc: Tianfei Zhang, stable

From: Tianfei Zhang <tianfei.zhang@intel.com>

0x4a means idle status on physical layer. when encounter
0x4a on raw data, it need insert a ESCAPE character for
indication.

Fixes: 96ebfcf8 ("raw/ifpga/base: add SPI and MAX10 device driver")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
 drivers/raw/ifpga/base/opae_spi_transaction.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/raw/ifpga/base/opae_spi_transaction.c b/drivers/raw/ifpga/base/opae_spi_transaction.c
index 013efee3e..d13d2fbc8 100644
--- a/drivers/raw/ifpga/base/opae_spi_transaction.c
+++ b/drivers/raw/ifpga/base/opae_spi_transaction.c
@@ -166,7 +166,7 @@ static int byte_to_core_convert(struct spi_transaction_dev *dev,
 		current_byte = send_data[i];
 		switch (current_byte) {
 		case SPI_BYTE_IDLE:
-			*p++ = SPI_BYTE_IDLE;
+			*p++ = SPI_BYTE_ESC;
 			*p++ = xor_20(current_byte);
 			break;
 		case SPI_BYTE_ESC:
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-stable] [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue
  2020-07-09 16:35 [dpdk-stable] [PATCH v1 1/2] raw/ifpga/base: fix spi transaction issue Tianfei zhang
@ 2020-07-14 21:35 ` Tianfei zhang
  2020-07-14 21:35   ` [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial Tianfei zhang
  2020-07-15 11:21   ` [dpdk-stable] [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue Xu, Rosen
  0 siblings, 2 replies; 6+ messages in thread
From: Tianfei zhang @ 2020-07-14 21:35 UTC (permalink / raw)
  To: dev, rosen.xu; +Cc: Tianfei Zhang, stable

From: Tianfei Zhang <tianfei.zhang@intel.com>

0x4a means idle status on physical layer. when encounter
0x4a on raw data, it need insert a ESCAPE character for
indication.

Fixes: 96ebfcf8 ("raw/ifpga/base: add SPI and MAX10 device driver")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>

---
v3: resend with threaded option for git send-email
---
 drivers/raw/ifpga/base/opae_spi_transaction.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/raw/ifpga/base/opae_spi_transaction.c b/drivers/raw/ifpga/base/opae_spi_transaction.c
index 013efee3e..d13d2fbc8 100644
--- a/drivers/raw/ifpga/base/opae_spi_transaction.c
+++ b/drivers/raw/ifpga/base/opae_spi_transaction.c
@@ -166,7 +166,7 @@ static int byte_to_core_convert(struct spi_transaction_dev *dev,
 		current_byte = send_data[i];
 		switch (current_byte) {
 		case SPI_BYTE_IDLE:
-			*p++ = SPI_BYTE_IDLE;
+			*p++ = SPI_BYTE_ESC;
 			*p++ = xor_20(current_byte);
 			break;
 		case SPI_BYTE_ESC:
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial
  2020-07-14 21:35 ` [dpdk-stable] [PATCH v3 " Tianfei zhang
@ 2020-07-14 21:35   ` Tianfei zhang
  2020-07-15 11:21     ` Xu, Rosen
  2020-07-15 11:21   ` [dpdk-stable] [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue Xu, Rosen
  1 sibling, 1 reply; 6+ messages in thread
From: Tianfei zhang @ 2020-07-14 21:35 UTC (permalink / raw)
  To: dev, rosen.xu; +Cc: Tianfei Zhang, stable

From: Tianfei Zhang <tianfei.zhang@intel.com>

Add fecmode setting on NIOS SPI primary initialization.
this SPI is shared by NIOS core inside FPGA, NIOS will
use this SPI primary to do some one-time initialization
after power up, and then release the control to DPDK.

Fix the timeout initialization for polling the
NIOS_INIT_DONE.

Fixes: bc44402f ("raw/ifpga/base: configure FEC mode")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>

---
v3: resend the patch with threaded option for git send-email
v2: fix coding style issue
---
 drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++-------
 drivers/raw/ifpga/base/opae_spi.h  |  1 +
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c
index c31a94cf8..9057087b5 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = {
 static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 {
 	u32 val = 0;
-	unsigned long timeout = msecs_to_timer_cycles(10000);
+	unsigned long timeout = rte_get_timer_cycles() +
+			msecs_to_timer_cycles(10000);
 	unsigned long ticks;
 	int major_version;
+	int fecmode = FEC_MODE_NO;
 
 	if (spi_reg_read(dev, NIOS_VERSION, &val))
 		return -EIO;
 
-	major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
-		NIOS_VERSION_MAJOR;
-	dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+	major_version =
+		(val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;
+	dev_info(dev, "A10 NIOS FW version %d\n", major_version);
 
 	if (major_version >= 3) {
 		/* read NIOS_INIT to check if PKVL INIT done or not */
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
 
+		dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+
 		/* check if PKVLs are initialized already */
 		if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
 			goto nios_init_done;
 
 		/* start to config the default FEC mode */
-		val = NIOS_INIT_START;
+		val = fecmode | NIOS_INIT_START;
 
 		if (spi_reg_write(dev, NIOS_INIT, val))
 			return -EIO;
@@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 	do {
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
-		if (val)
+		if (val & NIOS_INIT_DONE)
 			break;
 
 		ticks = rte_get_timer_cycles();
 		if (time_after(ticks, timeout))
 			return -ETIMEDOUT;
 		msleep(100);
-	} while (!val);
+	} while (1);
+
+	/* get the fecmode */
+	if (spi_reg_read(dev, NIOS_INIT, &val))
+		return -EIO;
+	dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+	fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;
+	dev_info(dev, "fecmode: 0x%x, %s\n", fecmode,
+			(fecmode == FEC_MODE_KR) ? "kr" :
+			((fecmode == FEC_MODE_RS) ? "rs" : "no"));
 
 	return 0;
 }
diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h
index d20a4c3ed..73a227673 100644
--- a/drivers/raw/ifpga/base/opae_spi.h
+++ b/drivers/raw/ifpga/base/opae_spi.h
@@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
 
 #define NIOS_INIT		0x1000
 #define REQ_FEC_MODE		GENMASK(23, 8)
+#define REQ_FEC_MODE_SHIFT      8
 #define FEC_MODE_NO		0x0
 #define FEC_MODE_KR		0x5555
 #define FEC_MODE_RS		0xaaaa
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-stable] [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue
  2020-07-14 21:35 ` [dpdk-stable] [PATCH v3 " Tianfei zhang
  2020-07-14 21:35   ` [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial Tianfei zhang
@ 2020-07-15 11:21   ` Xu, Rosen
  1 sibling, 0 replies; 6+ messages in thread
From: Xu, Rosen @ 2020-07-15 11:21 UTC (permalink / raw)
  To: Zhang, Tianfei, dev; +Cc: stable



-----Original Message-----
From: Zhang, Tianfei <tianfei.zhang@intel.com> 
Sent: Wednesday, July 15, 2020 5:35 AM
To: dev@dpdk.org; Xu, Rosen <rosen.xu@intel.com>
Cc: Zhang, Tianfei <tianfei.zhang@intel.com>; stable@dpdk.org
Subject: [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue

From: Tianfei Zhang <tianfei.zhang@intel.com>

0x4a means idle status on physical layer. when encounter 0x4a on raw data, it need insert a ESCAPE character for indication.

Fixes: 96ebfcf8 ("raw/ifpga/base: add SPI and MAX10 device driver")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>

---
v3: resend with threaded option for git send-email
---
 drivers/raw/ifpga/base/opae_spi_transaction.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/raw/ifpga/base/opae_spi_transaction.c b/drivers/raw/ifpga/base/opae_spi_transaction.c
index 013efee3e..d13d2fbc8 100644
--- a/drivers/raw/ifpga/base/opae_spi_transaction.c
+++ b/drivers/raw/ifpga/base/opae_spi_transaction.c
@@ -166,7 +166,7 @@ static int byte_to_core_convert(struct spi_transaction_dev *dev,
 		current_byte = send_data[i];
 		switch (current_byte) {
 		case SPI_BYTE_IDLE:
-			*p++ = SPI_BYTE_IDLE;
+			*p++ = SPI_BYTE_ESC;
 			*p++ = xor_20(current_byte);
 			break;
 		case SPI_BYTE_ESC:
--
2.17.1

Acked-by: Rosen Xu <rosen.xu@intel.com>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial
  2020-07-14 21:35   ` [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial Tianfei zhang
@ 2020-07-15 11:21     ` Xu, Rosen
  2020-07-21 22:43       ` Thomas Monjalon
  0 siblings, 1 reply; 6+ messages in thread
From: Xu, Rosen @ 2020-07-15 11:21 UTC (permalink / raw)
  To: Zhang, Tianfei, dev; +Cc: stable



-----Original Message-----
From: Zhang, Tianfei <tianfei.zhang@intel.com> 
Sent: Wednesday, July 15, 2020 5:35 AM
To: dev@dpdk.org; Xu, Rosen <rosen.xu@intel.com>
Cc: Zhang, Tianfei <tianfei.zhang@intel.com>; stable@dpdk.org
Subject: [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial

From: Tianfei Zhang <tianfei.zhang@intel.com>

Add fecmode setting on NIOS SPI primary initialization.
this SPI is shared by NIOS core inside FPGA, NIOS will use this SPI primary to do some one-time initialization after power up, and then release the control to DPDK.

Fix the timeout initialization for polling the NIOS_INIT_DONE.

Fixes: bc44402f ("raw/ifpga/base: configure FEC mode")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>

---
v3: resend the patch with threaded option for git send-email
v2: fix coding style issue
---
 drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++-------  drivers/raw/ifpga/base/opae_spi.h  |  1 +
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c
index c31a94cf8..9057087b5 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = {  static int nios_spi_wait_init_done(struct altera_spi_device *dev)  {
 	u32 val = 0;
-	unsigned long timeout = msecs_to_timer_cycles(10000);
+	unsigned long timeout = rte_get_timer_cycles() +
+			msecs_to_timer_cycles(10000);
 	unsigned long ticks;
 	int major_version;
+	int fecmode = FEC_MODE_NO;
 
 	if (spi_reg_read(dev, NIOS_VERSION, &val))
 		return -EIO;
 
-	major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
-		NIOS_VERSION_MAJOR;
-	dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+	major_version =
+		(val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;
+	dev_info(dev, "A10 NIOS FW version %d\n", major_version);
 
 	if (major_version >= 3) {
 		/* read NIOS_INIT to check if PKVL INIT done or not */
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
 
+		dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+
 		/* check if PKVLs are initialized already */
 		if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
 			goto nios_init_done;
 
 		/* start to config the default FEC mode */
-		val = NIOS_INIT_START;
+		val = fecmode | NIOS_INIT_START;
 
 		if (spi_reg_write(dev, NIOS_INIT, val))
 			return -EIO;
@@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 	do {
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
-		if (val)
+		if (val & NIOS_INIT_DONE)
 			break;
 
 		ticks = rte_get_timer_cycles();
 		if (time_after(ticks, timeout))
 			return -ETIMEDOUT;
 		msleep(100);
-	} while (!val);
+	} while (1);
+
+	/* get the fecmode */
+	if (spi_reg_read(dev, NIOS_INIT, &val))
+		return -EIO;
+	dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+	fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;
+	dev_info(dev, "fecmode: 0x%x, %s\n", fecmode,
+			(fecmode == FEC_MODE_KR) ? "kr" :
+			((fecmode == FEC_MODE_RS) ? "rs" : "no"));
 
 	return 0;
 }
diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h
index d20a4c3ed..73a227673 100644
--- a/drivers/raw/ifpga/base/opae_spi.h
+++ b/drivers/raw/ifpga/base/opae_spi.h
@@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
 
 #define NIOS_INIT		0x1000
 #define REQ_FEC_MODE		GENMASK(23, 8)
+#define REQ_FEC_MODE_SHIFT      8
 #define FEC_MODE_NO		0x0
 #define FEC_MODE_KR		0x5555
 #define FEC_MODE_RS		0xaaaa
--
2.17.1

Acked-by: Rosen Xu <rosen.xu@intel.com>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial
  2020-07-15 11:21     ` Xu, Rosen
@ 2020-07-21 22:43       ` Thomas Monjalon
  0 siblings, 0 replies; 6+ messages in thread
From: Thomas Monjalon @ 2020-07-21 22:43 UTC (permalink / raw)
  To: Zhang, Tianfei; +Cc: dev, stable, Xu, Rosen

15/07/2020 13:21, Xu, Rosen:
> From: Tianfei Zhang <tianfei.zhang@intel.com>
> 
> Add fecmode setting on NIOS SPI primary initialization.
> this SPI is shared by NIOS core inside FPGA, NIOS will use this SPI primary to do some one-time initialization after power up, and then release the control to DPDK.
> 
> Fix the timeout initialization for polling the NIOS_INIT_DONE.
> 
> Fixes: bc44402f ("raw/ifpga/base: configure FEC mode")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> 
> Acked-by: Rosen Xu <rosen.xu@intel.com>

Series applied, thanks



^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-07-21 22:43 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 16:35 [dpdk-stable] [PATCH v1 1/2] raw/ifpga/base: fix spi transaction issue Tianfei zhang
2020-07-14 21:35 ` [dpdk-stable] [PATCH v3 " Tianfei zhang
2020-07-14 21:35   ` [dpdk-stable] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial Tianfei zhang
2020-07-15 11:21     ` Xu, Rosen
2020-07-21 22:43       ` Thomas Monjalon
2020-07-15 11:21   ` [dpdk-stable] [PATCH v3 1/2] raw/ifpga/base: fix spi transaction issue Xu, Rosen

patches for DPDK stable branches

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