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* [PATCH 1/4] net/mlx5: fix secondary process port close
       [not found] <20240416153054.3216706-1-michaelba@nvidia.com>
@ 2024-04-16 15:30 ` Michael Baum
  2024-04-16 15:30 ` [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask Michael Baum
  1 sibling, 0 replies; 2+ messages in thread
From: Michael Baum @ 2024-04-16 15:30 UTC (permalink / raw)
  To: dev
  Cc: Matan Azrad, Dariusz Sosnowski, Raslan Darawsheh,
	Viacheslav Ovsiienko, Ori Kam, Suanming Mou, michaelba, stable

The "mlx5_dev_close()" function is used for both primary and secondary
processes.

If secondary process use this function after primary process is closed,
the priv structure isn't valid anymore.
The function is accessing priv structure to get "sh" pointer in part
shared between processes causing a crash for secondary.

This patch avoids this access and print warning in this case.

Fixes: f5177bdc8b76 ("net/mlx5: add GENEVE TLV options parser API")
Cc: michaelba@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index d1a63822a5..585b4d5497 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -2295,11 +2295,13 @@ int
 mlx5_dev_close(struct rte_eth_dev *dev)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
-	struct mlx5_dev_ctx_shared *sh = priv->sh;
+	struct mlx5_dev_ctx_shared *sh;
 	unsigned int i;
 	int ret;
 
 	if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
+		if (!priv)
+			DRV_LOG(WARNING, "primary process is already closed");
 		/* Check if process_private released. */
 		if (!dev->process_private)
 			return 0;
@@ -2308,6 +2310,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 		rte_eth_dev_release_port(dev);
 		return 0;
 	}
+	sh = priv->sh;
 	if (!sh)
 		return 0;
 	if (priv->shared_refcnt) {
@@ -2326,9 +2329,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 	}
 #endif
 	DRV_LOG(DEBUG, "port %u closing device \"%s\"",
-		dev->data->port_id,
-		((priv->sh->cdev->ctx != NULL) ?
-		mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
+		dev->data->port_id, sh->ibdev_name);
 	/*
 	 * If default mreg copy action is removed at the stop stage,
 	 * the search will return none and nothing will be done anymore.
@@ -2402,7 +2403,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 		mlx5_free(priv->rss_conf.rss_key);
 	if (priv->reta_idx != NULL)
 		mlx5_free(priv->reta_idx);
-	if (priv->sh->dev_cap.vf)
+	if (sh->dev_cap.vf)
 		mlx5_os_mac_addr_flush(dev);
 	if (priv->nl_socket_route >= 0)
 		close(priv->nl_socket_route);
@@ -2445,7 +2446,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 	if (priv->hrxqs)
 		mlx5_list_destroy(priv->hrxqs);
 	mlx5_free(priv->ext_rxqs);
-	priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS;
+	sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS;
 	/*
 	 * The interrupt handler port id must be reset before priv is reset
 	 * since 'mlx5_dev_interrupt_nl_cb' uses priv.
@@ -2457,7 +2458,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 	 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
 	 * ifindex if Netlink fails.
 	 */
-	mlx5_free_shared_dev_ctx(priv->sh);
+	mlx5_free_shared_dev_ctx(sh);
 	if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 		unsigned int c = 0;
 		uint16_t port_id;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask
       [not found] <20240416153054.3216706-1-michaelba@nvidia.com>
  2024-04-16 15:30 ` [PATCH 1/4] net/mlx5: fix secondary process port close Michael Baum
@ 2024-04-16 15:30 ` Michael Baum
  1 sibling, 0 replies; 2+ messages in thread
From: Michael Baum @ 2024-04-16 15:30 UTC (permalink / raw)
  To: dev
  Cc: Matan Azrad, Dariusz Sosnowski, Raslan Darawsheh,
	Viacheslav Ovsiienko, Ori Kam, Suanming Mou, valex, stable

When GENEVE option parser is configured, the class field has 3 optional
modes:
1. ignored - ignore this field.
2. fixed - this field is part of option identifier along with type
	   field. In this mode, the exact value is provided in "spec"
	   field during pattern template creation and mask must be 0xffff.
3. matchable - class field isn't part of the identifier and only mask is
	       provided in pattern template creation. The mask can be
	       any value like all other fields.

In current implementation, when class mask isn't 0, pattern template
creation is failed for mask != 0xffff regardless to class mode.

This patch fixes this validation to be only when class mode is fixed.

Fixes: 8f8dad4289e0 ("net/mlx5/hws: support GENEVE options matching")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 35a2ed2048..f1f544deab 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -2500,11 +2500,6 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd,
 		goto out_not_supp;
 	}
 
-	if (m->option_class && m->option_class != RTE_BE16(UINT16_MAX)) {
-		DR_LOG(ERR, "Geneve option class has invalid mask");
-		goto out_not_supp;
-	}
-
 	ret = mlx5_get_geneve_hl_data(cd->ctx,
 				      v->option_type,
 				      v->option_class,
@@ -2517,6 +2512,11 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd,
 		goto out_not_supp;
 	}
 
+	if (ok_bit_on_class && m->option_class != RTE_BE16(UINT16_MAX)) {
+		DR_LOG(ERR, "Geneve option class has invalid mask");
+		goto out_not_supp;
+	}
+
 	if (!ok_bit_on_class && m->option_class) {
 		/* DW0 is used, we will match type, class */
 		if (!num_of_dws || hl_dws[0].dw_mask != UINT32_MAX) {
-- 
2.25.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

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     [not found] <20240416153054.3216706-1-michaelba@nvidia.com>
2024-04-16 15:30 ` [PATCH 1/4] net/mlx5: fix secondary process port close Michael Baum
2024-04-16 15:30 ` [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask Michael Baum

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