* |WARNING| pw118819 [v6 11/18] net/mlx5/hws: Add HWS definer layer
[not found] <20221020155749.16643-12-valex@nvidia.com>
@ 2022-10-20 16:04 ` checkpatch
0 siblings, 0 replies; only message in thread
From: checkpatch @ 2022-10-20 16:04 UTC (permalink / raw)
To: test-report; +Cc: Alex Vesker
Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/118819
_coding style issues_
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#192: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:23:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'byte_off' - possible side-effects?
#192: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:23:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit_off' - possible side-effects?
#192: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:23:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#192: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:23:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#204: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:35:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely((bit_off) < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, (bit_off), (mask)); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'v' - possible side-effects?
#204: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:35:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely((bit_off) < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, (bit_off), (mask)); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'byte_off' - possible side-effects?
#204: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:35:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely((bit_off) < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, (bit_off), (mask)); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit_off' - possible side-effects?
#204: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:35:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely((bit_off) < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, (bit_off), (mask)); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#204: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:35:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely((bit_off) < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, (bit_off), (mask)); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fc' - possible side-effects?
#237: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:68:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'hdr' - possible side-effects?
#237: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:68:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#237: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:68:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fc' - possible side-effects?
#245: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:76:
+#define DR_CALC_SET(fc, hdr, field, is_inner) \
+ do { \
+ if (is_inner) { \
+ DR_CALC_SET_HDR(fc, hdr##_inner, field); \
+ } else { \
+ DR_CALC_SET_HDR(fc, hdr##_outer, field); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#245: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:76:
+#define DR_CALC_SET(fc, hdr, field, is_inner) \
+ do { \
+ if (is_inner) { \
+ DR_CALC_SET_HDR(fc, hdr##_inner, field); \
+ } else { \
+ DR_CALC_SET_HDR(fc, hdr##_outer, field); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'typ' - possible side-effects?
#254: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:85:
+ #define DR_GET(typ, p, fld) \
+ ((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + \
+ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
+ __mlx5_mask(typ, fld))
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fld' - possible side-effects?
#254: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:85:
+ #define DR_GET(typ, p, fld) \
+ ((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + \
+ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
+ __mlx5_mask(typ, fld))
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#280: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:111:
+#define LIST_OF_FIELDS_INFO \
+ X(SET_BE16, eth_type, v->type, rte_flow_item_eth) \
+ X(SET_BE32P, eth_smac_47_16, &v->src.addr_bytes[0], rte_flow_item_eth) \
+ X(SET_BE16P, eth_smac_15_0, &v->src.addr_bytes[4], rte_flow_item_eth) \
+ X(SET_BE32P, eth_dmac_47_16, &v->dst.addr_bytes[0], rte_flow_item_eth) \
+ X(SET_BE16P, eth_dmac_15_0, &v->dst.addr_bytes[4], rte_flow_item_eth) \
+ X(SET_BE16, tci, v->tci, rte_flow_item_vlan) \
+ X(SET, ipv4_ihl, v->ihl, rte_ipv4_hdr) \
+ X(SET, ipv4_tos, v->type_of_service, rte_ipv4_hdr) \
+ X(SET, ipv4_time_to_live, v->time_to_live, rte_ipv4_hdr) \
+ X(SET_BE32, ipv4_dst_addr, v->dst_addr, rte_ipv4_hdr) \
+ X(SET_BE32, ipv4_src_addr, v->src_addr, rte_ipv4_hdr) \
+ X(SET, ipv4_next_proto, v->next_proto_id, rte_ipv4_hdr) \
+ X(SET, ipv4_version, STE_IPV4, rte_ipv4_hdr) \
+ X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \
+ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \
+ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \
+ X(SET, ipv6_hop_limits, v->hdr.hop_limits, rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_127_96, &v->hdr.src_addr[0], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_95_64, &v->hdr.src_addr[4], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_63_32, &v->hdr.src_addr[8], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_31_0, &v->hdr.src_addr[12], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_127_96, &v->hdr.dst_addr[0], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_95_64, &v->hdr.dst_addr[4], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_63_32, &v->hdr.dst_addr[8], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_31_0, &v->hdr.dst_addr[12], rte_flow_item_ipv6) \
+ X(SET, ipv6_version, STE_IPV6, rte_flow_item_ipv6) \
+ X(SET, ipv6_frag, v->has_frag_ext, rte_flow_item_ipv6) \
+ X(SET, icmp_protocol, STE_ICMP, rte_flow_item_icmp) \
+ X(SET, udp_protocol, STE_UDP, rte_flow_item_udp) \
+ X(SET_BE16, udp_src_port, v->hdr.src_port, rte_flow_item_udp) \
+ X(SET_BE16, udp_dst_port, v->hdr.dst_port, rte_flow_item_udp) \
+ X(SET, tcp_flags, v->hdr.tcp_flags, rte_flow_item_tcp) \
+ X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \
+ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \
+ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \
+ X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \
+ X(SET_BE32, gtp_teid, v->teid, rte_flow_item_gtp) \
+ X(SET, gtp_msg_type, v->msg_type, rte_flow_item_gtp) \
+ X(SET, gtp_ext_flag, !!v->v_pt_rsv_flags, rte_flow_item_gtp) \
+ X(SET, gtp_next_ext_hdr, GTP_PDU_SC, rte_flow_item_gtp_psc) \
+ X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \
+ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \
+ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \
+ X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \
+ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \
+ X(SET, tag, v->data, rte_flow_item_tag) \
+ X(SET, metadata, v->data, rte_flow_item_meta) \
+ X(SET_BE16, gre_c_ver, v->c_rsvd0_ver, rte_flow_item_gre) \
+ X(SET_BE16, gre_protocol_type, v->protocol, rte_flow_item_gre) \
+ X(SET, ipv4_protocol_gre, IPPROTO_GRE, rte_flow_item_gre) \
+ X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
+ X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
+ X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#333: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:164:
+ X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#334: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:165:
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'item_type' may be better as '(item_type)' to avoid precedence issues
#337: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:168:
+#define X(set_type, func_name, value, item_type) \
+static void mlx5dr_definer_##func_name##_set( \
+ struct mlx5dr_definer_fc *fc, \
+ const void *item_spec, \
+ uint8_t *tag) \
+{ \
+ __rte_unused const struct item_type *v = item_spec; \
+ DR_##set_type(tag, value, fc->byte_off, fc->bit_off, fc->bit_mask); \
+}
total: 1 errors, 2 warnings, 17 checks, 2567 lines checked
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2022-10-20 16:04 ` |WARNING| pw118819 [v6 11/18] net/mlx5/hws: Add HWS definer layer checkpatch
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