[dpdk-users] Do the two functions on 82599ES have independent registers?

[dpdk-users] Do the two functions on 82599ES have independent registers?

[Zhongming Qu]

Hi,


Thanks in advance (Orz)!

Could someone quickly confirm that the two functions on a 82599ES nic have
independent BAR0-based registers or not?

For example, when running two primary dpdk processes, one of which uses
port0 and the other of which uses port1, writing to RDBAL[0] simultaneously
is a race condition or not?

The BAR0-based registers are mapped to different physical memories, as in:

```
lwr@dev5:~$ lspci -s 02:00.0 -xx -n -v
02:00.0 0200: 8086:10fb (rev 01)
    ....
    Memory at fbd80000 (64-bit, prefetchable) [size=512K]
    ...

lwr@dev5:~$ lspci -s 02:00.1 -xx -n -v
02:00.1 0200: 8086:10fb (rev 01)
    ...
    Memory at fbd00000 (64-bit, prefetchable) [size=512K]
    ...
```

Could these two physical addresses be mapped to actually the same PCI
address?


The 82599 data sheet says that the two ports have independent BAR's. But it
does not explicitly say that the two ports share the same rx/tx queue
registers or not. It does not, either, say that the 128 rx/tx queues are
per-port or shared by the two ports.

It has been really difficult to find relevant information outside of this
group. Thanks in advance!



Best,
Zhongming