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From: Avi Cohen <acohen@ves.io>
To: "Van Haaren, Harry" <harry.van.haaren@intel.com>
Cc: Sara Gittlin <sara.gittlin@gmail.com>, users@dpdk.org
Subject: Re: [dpdk-users] HW cache utilisation w OVS-DPDK
Date: Tue, 30 Apr 2019 23:08:25 +0300	[thread overview]
Message-ID: <CAJGSrbNrLbaNV4gFiZdbOKudR16XU2jZW1OvfwhLg6CL7hYJ3w@mail.gmail.com> (raw)
In-Reply-To: <E923DB57A917B54B9182A2E928D00FA67582DE8B@IRSMSX102.ger.corp.intel.com>

Thank you Harry very much for your detailed answer.
I think that ovs with Data plane is a kernel module (i.e. not ovs dpdk) the
flow table is somehow always in the cache, hence there is an eviction
function in user space that is sending commands to the kernel to delete non
active flows in order to make place in this expensive cache memory. But i
dont know how it is w ovs-dpdk. I know that generaly caches mem are
transprant to sw, but w ovs kernel module the flow table is always stored
in cache.
Thanks again Harry
-Sara

בתאריך יום ג׳, 30 באפר׳ 2019, 21:33, מאת Van Haaren, Harry ‏<
harry.van.haaren@intel.com>:

> > -----Original Message-----
> > From: users [mailto:users-bounces@dpdk.org] On Behalf Of Sara Gittlin
> > Sent: Tuesday, April 30, 2019 6:15 PM
> > To: users@dpdk.org
> > Subject: [dpdk-users] HW cache utilisation w OVS-DPDK
> >
> > Hello  All
>
> Hi Sara,
>
> > It is a naive and maybe a stupid question , but do we use HW cache L1/L2
> > etc with OVS-DPDK?
>
> The hardware CPU caches (L1, L2 and LLC) are transparent to software.
>
> Another way to say that is that When writing code, the software doesn't
> have to explicitly use L1 or L2, the memory being used (from libc malloc()
> or stack memory)
> is cached by the CPU without any software involvement.
>
> In short, software uses L1/L2/etc without "knowing" it as such...
>
> However, just because we (as C software developers) cannot directly access
> cache,
> does not mean that we should ignore it! In particular designing
> cache-conscious
> data-structures can have a *huge* impact on runtime performance.
>
> I recommend some of the CPP Con talks on software performance, particularly
> the one titled "Efficiency with Algorithms, Performance with Data
> Structures".
>
>
> > for example  where the flow-table  is stored ? in  HW-cache or in RAM?
>
> This is a good question - and the answer is like so many engineering
> questions - it depends :)
>
> If the part of the flow-table has been recently accessed, it is likely to
> be in the HW-cache.
> If the flow-table has been initialized, but not used recently it is likely
> to be in ordinary RAM.
>
> From a performance point of view, this is quite interesting, as certain
> flow-table accesses
> are expected to be cheap (in cache) while others might take longer (RAM).
>
>
> > Thank you
> > -Sara
>
> Hope that helps! Regards, -Harry
>

  reply	other threads:[~2019-04-30 20:08 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-30 17:15 Sara Gittlin
2019-04-30 18:33 ` Van Haaren, Harry
2019-04-30 20:08   ` Avi Cohen [this message]
2019-05-01 10:35     ` Van Haaren, Harry

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