Re: [dpdk-users] HW cache utilisation w OVS-DPDK

["Van Haaren, Harry" <harry.van.haaren@intel.com>]

> -----Original Message-----
> From: users [mailto:users-bounces@dpdk.org] On Behalf Of Sara Gittlin
> Sent: Tuesday, April 30, 2019 6:15 PM
> To: users@dpdk.org
> Subject: [dpdk-users] HW cache utilisation w OVS-DPDK
> 
> Hello  All

Hi Sara,

> It is a naive and maybe a stupid question , but do we use HW cache L1/L2
> etc with OVS-DPDK?

The hardware CPU caches (L1, L2 and LLC) are transparent to software.

Another way to say that is that When writing code, the software doesn't
have to explicitly use L1 or L2, the memory being used (from libc malloc() or stack memory)
is cached by the CPU without any software involvement.

In short, software uses L1/L2/etc without "knowing" it as such...

However, just because we (as C software developers) cannot directly access cache,
does not mean that we should ignore it! In particular designing cache-conscious
data-structures can have a *huge* impact on runtime performance.

I recommend some of the CPP Con talks on software performance, particularly
the one titled "Efficiency with Algorithms, Performance with Data Structures".


> for example  where the flow-table  is stored ? in  HW-cache or in RAM?

This is a good question - and the answer is like so many engineering questions - it depends :)

If the part of the flow-table has been recently accessed, it is likely to be in the HW-cache.
If the flow-table has been initialized, but not used recently it is likely to be in ordinary RAM.

From a performance point of view, this is quite interesting, as certain flow-table accesses
are expected to be cheap (in cache) while others might take longer (RAM).


> Thank you
> -Sara

Hope that helps! Regards, -Harry