DPDK patches and discussions
 help / color / mirror / Atom feed
* [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API
@ 2020-03-03  8:19 asomalap
  2020-03-03  8:19 ` [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority " asomalap
  2020-03-16  3:53 ` [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " Kumar, Ravi1
  0 siblings, 2 replies; 6+ messages in thread
From: asomalap @ 2020-03-03  8:19 UTC (permalink / raw)
  To: dev; +Cc: Ravi1.Kumar

From: Amaranath Somalapuram <asomalap@amd.com>

Adding api for flow_ctrl_get and flow_ctrl_set.
By default axgbe driver flow control is disabled.
Adding dpdk flow control to set water high and low.

Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
---
 drivers/net/axgbe/axgbe_ethdev.c | 84 ++++++++++++++++++++++++++++++++
 drivers/net/axgbe/axgbe_ethdev.h | 11 +++++
 2 files changed, 95 insertions(+)

diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 00974e737..867c4744f 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -47,6 +47,10 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 static int  axgbe_dev_info_get(struct rte_eth_dev *dev,
 			       struct rte_eth_dev_info *dev_info);
+static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
+				struct rte_eth_fc_conf *fc_conf);
+static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
+				struct rte_eth_fc_conf *fc_conf);
 
 struct axgbe_xstats {
 	char name[RTE_ETH_XSTATS_NAME_SIZE];
@@ -174,6 +178,8 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
 	.rx_queue_release     = axgbe_dev_rx_queue_release,
 	.tx_queue_setup       = axgbe_dev_tx_queue_setup,
 	.tx_queue_release     = axgbe_dev_tx_queue_release,
+	.flow_ctrl_get        = axgbe_flow_ctrl_get,
+	.flow_ctrl_set        = axgbe_flow_ctrl_set,
 };
 
 static int axgbe_phy_reset(struct axgbe_port *pdata)
@@ -843,6 +849,84 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 	return 0;
 }
 
+static int
+axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
+{
+	struct axgbe_port *pdata = dev->data->dev_private;
+	struct xgbe_fc_info fc = pdata->fc;
+	unsigned int reg, reg_val = 0;
+
+	reg = MAC_Q0TFCR;
+	reg_val = AXGMAC_IOREAD(pdata, reg);
+	fc.low_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
+	fc.high_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
+	fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
+	fc.autoneg = pdata->pause_autoneg;
+
+	if (pdata->rx_pause && pdata->tx_pause)
+		fc.mode = RTE_FC_FULL;
+	else if (pdata->rx_pause)
+		fc.mode = RTE_FC_RX_PAUSE;
+	else if (pdata->tx_pause)
+		fc.mode = RTE_FC_TX_PAUSE;
+	else
+		fc.mode = RTE_FC_NONE;
+
+	fc_conf->high_water =  (1024 + (fc.low_water[0] << 9)) / 1024;
+	fc_conf->low_water =  (1024 + (fc.high_water[0] << 9)) / 1024;
+	fc_conf->pause_time = fc.pause_time[0];
+	fc_conf->send_xon = fc.send_xon;
+	fc_conf->mode = fc.mode;
+
+	return 0;
+}
+
+static int
+axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
+{
+	struct axgbe_port *pdata = dev->data->dev_private;
+	struct xgbe_fc_info fc = pdata->fc;
+	unsigned int reg, reg_val = 0;
+	reg = MAC_Q0TFCR;
+
+	pdata->pause_autoneg = fc_conf->autoneg;
+	pdata->phy.pause_autoneg = pdata->pause_autoneg;
+	fc.send_xon = fc_conf->send_xon;
+	AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
+			AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
+	AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
+			AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
+	AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
+	AXGMAC_IOWRITE(pdata, reg, reg_val);
+	fc.mode = fc_conf->mode;
+
+	if (fc.mode == RTE_FC_FULL) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 1;
+	} else if (fc.mode == RTE_FC_RX_PAUSE) {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 1;
+	} else if (fc.mode == RTE_FC_TX_PAUSE) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 0;
+	} else {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 0;
+	}
+
+	if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
+		pdata->hw_if.config_tx_flow_control(pdata);
+
+	if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
+		pdata->hw_if.config_rx_flow_control(pdata);
+
+	pdata->hw_if.config_flow_control(pdata);
+	pdata->phy.tx_pause = pdata->tx_pause;
+	pdata->phy.rx_pause = pdata->rx_pause;
+
+	return 0;
+}
+
 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
 {
 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index a1083b17b..436d780c9 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -485,6 +485,16 @@ struct axgbe_mmc_stats {
 	uint64_t rxwatchdogerror;
 };
 
+/* Flow control parameters */
+struct xgbe_fc_info {
+	uint32_t high_water[AXGBE_PRIORITY_QUEUES];
+	uint32_t low_water[AXGBE_PRIORITY_QUEUES];
+	uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
+	uint16_t send_xon;
+	enum rte_eth_fc_mode mode;
+	uint8_t autoneg;
+};
+
 /*
  * Structure to store private data for each port.
  */
@@ -625,6 +635,7 @@ struct axgbe_port {
 	uint32_t rx_csum_enable;
 
 	struct axgbe_mmc_stats mmc_stats;
+	struct xgbe_fc_info fc;
 };
 
 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority flow control API
  2020-03-03  8:19 [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API asomalap
@ 2020-03-03  8:19 ` asomalap
  2020-03-16  3:53 ` [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " Kumar, Ravi1
  1 sibling, 0 replies; 6+ messages in thread
From: asomalap @ 2020-03-03  8:19 UTC (permalink / raw)
  To: dev; +Cc: Ravi1.Kumar

From: Amaranath Somalapuram <asomalap@amd.com>

Adding API for  priority_flow_ctrl_set.
Priority flow control to set water high and low,
pause_time and priority.

Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
---
 drivers/net/axgbe/axgbe_common.h | 16 ++++++
 drivers/net/axgbe/axgbe_ethdev.c | 94 ++++++++++++++++++++++++++++++++
 drivers/net/axgbe/axgbe_ethdev.h |  1 +
 3 files changed, 111 insertions(+)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 2ac4d8946..bdd85a341 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -835,6 +835,22 @@
 #define MTL_TC_ETSCR_TSA_WIDTH		2
 #define MTL_TC_QWR_QW_INDEX		0
 #define MTL_TC_QWR_QW_WIDTH		21
+#define MTL_TCPM0R_PSTC0_INDEX		0
+#define MTL_TCPM0R_PSTC0_WIDTH		8
+#define MTL_TCPM0R_PSTC1_INDEX		8
+#define MTL_TCPM0R_PSTC1_WIDTH		8
+#define MTL_TCPM0R_PSTC2_INDEX		16
+#define MTL_TCPM0R_PSTC2_WIDTH		8
+#define MTL_TCPM0R_PSTC3_INDEX		24
+#define MTL_TCPM0R_PSTC3_WIDTH		8
+#define MTL_TCPM1R_PSTC4_INDEX		0
+#define MTL_TCPM1R_PSTC4_WIDTH		8
+#define MTL_TCPM1R_PSTC5_INDEX		8
+#define MTL_TCPM1R_PSTC5_WIDTH		8
+#define MTL_TCPM1R_PSTC6_INDEX		16
+#define MTL_TCPM1R_PSTC6_WIDTH		8
+#define MTL_TCPM1R_PSTC7_INDEX		24
+#define MTL_TCPM1R_PSTC7_WIDTH		8
 
 /* MTL traffic class register value */
 #define MTL_TSA_SP			0x00
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867c4744f..e7b731b2e 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -51,6 +51,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
+static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+				struct rte_eth_pfc_conf *pfc_conf);
 
 struct axgbe_xstats {
 	char name[RTE_ETH_XSTATS_NAME_SIZE];
@@ -180,6 +182,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
 	.tx_queue_release     = axgbe_dev_tx_queue_release,
 	.flow_ctrl_get        = axgbe_flow_ctrl_get,
 	.flow_ctrl_set        = axgbe_flow_ctrl_set,
+	.priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
 };
 
 static int axgbe_phy_reset(struct axgbe_port *pdata)
@@ -927,6 +930,97 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	return 0;
 }
 
+static int
+axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+		struct rte_eth_pfc_conf *pfc_conf)
+{
+	struct axgbe_port *pdata = dev->data->dev_private;
+	struct xgbe_fc_info fc = pdata->fc;
+	uint8_t tc_num;
+
+	tc_num = pdata->pfc_map[pfc_conf->priority];
+
+	if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
+		PMD_INIT_LOG(ERR, "Max supported  traffic class: %d\n",
+				pdata->hw_feat.tc_cnt);
+	return -EINVAL;
+	}
+
+	pdata->pause_autoneg = pfc_conf->fc.autoneg;
+	pdata->phy.pause_autoneg = pdata->pause_autoneg;
+	fc.send_xon = pfc_conf->fc.send_xon;
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
+
+	switch (tc_num) {
+	case 0:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC0, pfc_conf->fc.pause_time);
+		break;
+	case 1:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC1, pfc_conf->fc.pause_time);
+		break;
+	case 2:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC2, pfc_conf->fc.pause_time);
+		break;
+	case 3:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC3, pfc_conf->fc.pause_time);
+		break;
+	case 4:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC4, pfc_conf->fc.pause_time);
+		break;
+	case 5:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC5, pfc_conf->fc.pause_time);
+		break;
+	case 7:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC6, pfc_conf->fc.pause_time);
+		break;
+	case 6:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC7, pfc_conf->fc.pause_time);
+		break;
+	}
+
+	fc.mode = pfc_conf->fc.mode;
+
+	if (fc.mode == RTE_FC_FULL) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_RX_PAUSE) {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_TX_PAUSE) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	} else {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	}
+
+	if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
+		pdata->hw_if.config_tx_flow_control(pdata);
+
+	if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
+		pdata->hw_if.config_rx_flow_control(pdata);
+	pdata->hw_if.config_flow_control(pdata);
+	pdata->phy.tx_pause = pdata->tx_pause;
+	pdata->phy.rx_pause = pdata->rx_pause;
+
+	return 0;
+}
+
 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
 {
 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index 436d780c9..1d70559bf 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -586,6 +586,7 @@ struct axgbe_port {
 	unsigned int rx_rfa[AXGBE_MAX_QUEUES];
 	unsigned int rx_rfd[AXGBE_MAX_QUEUES];
 	unsigned int fifo;
+	unsigned int pfc_map[AXGBE_MAX_QUEUES];
 
 	/* Receive Side Scaling settings */
 	u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API
  2020-03-03  8:19 [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API asomalap
  2020-03-03  8:19 ` [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority " asomalap
@ 2020-03-16  3:53 ` Kumar, Ravi1
  2020-03-16 12:52   ` Ferruh Yigit
  1 sibling, 1 reply; 6+ messages in thread
From: Kumar, Ravi1 @ 2020-03-16  3:53 UTC (permalink / raw)
  To: Somalapuram, Amaranath, dev

[AMD Public Use]

For series,
Acked-by: Ravi Kumar <ravi1.kumar@amd.com> 


>From: Amaranath Somalapuram <asomalap@amd.com>
>
>Adding api for flow_ctrl_get and flow_ctrl_set.
>By default axgbe driver flow control is disabled.
>Adding dpdk flow control to set water high and low.
>
>Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
>---
> drivers/net/axgbe/axgbe_ethdev.c | 84 ++++++++++++++++++++++++++++++++  drivers/net/axgbe/axgbe_ethdev.h | 11 +++++
> 2 files changed, 95 insertions(+)
>
>diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
>index 00974e737..867c4744f 100644
>--- a/drivers/net/axgbe/axgbe_ethdev.c
>+++ b/drivers/net/axgbe/axgbe_ethdev.c
>@@ -47,6 +47,10 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,  static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);  static int  axgbe_dev_info_get(struct rte_eth_dev *dev,
> 			       struct rte_eth_dev_info *dev_info);
>+static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
>+				struct rte_eth_fc_conf *fc_conf);
>+static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
>+				struct rte_eth_fc_conf *fc_conf);
> 
> struct axgbe_xstats {
> 	char name[RTE_ETH_XSTATS_NAME_SIZE];
>@@ -174,6 +178,8 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
> 	.rx_queue_release     = axgbe_dev_rx_queue_release,
> 	.tx_queue_setup       = axgbe_dev_tx_queue_setup,
> 	.tx_queue_release     = axgbe_dev_tx_queue_release,
>+	.flow_ctrl_get        = axgbe_flow_ctrl_get,
>+	.flow_ctrl_set        = axgbe_flow_ctrl_set,
> };
> 
> static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -843,6 +849,84 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
> 	return 0;
> }
> 
>+static int
>+axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf 
>+*fc_conf) {
>+	struct axgbe_port *pdata = dev->data->dev_private;
>+	struct xgbe_fc_info fc = pdata->fc;
>+	unsigned int reg, reg_val = 0;
>+
>+	reg = MAC_Q0TFCR;
>+	reg_val = AXGMAC_IOREAD(pdata, reg);
>+	fc.low_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
>+	fc.high_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
>+	fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
>+	fc.autoneg = pdata->pause_autoneg;
>+
>+	if (pdata->rx_pause && pdata->tx_pause)
>+		fc.mode = RTE_FC_FULL;
>+	else if (pdata->rx_pause)
>+		fc.mode = RTE_FC_RX_PAUSE;
>+	else if (pdata->tx_pause)
>+		fc.mode = RTE_FC_TX_PAUSE;
>+	else
>+		fc.mode = RTE_FC_NONE;
>+
>+	fc_conf->high_water =  (1024 + (fc.low_water[0] << 9)) / 1024;
>+	fc_conf->low_water =  (1024 + (fc.high_water[0] << 9)) / 1024;
>+	fc_conf->pause_time = fc.pause_time[0];
>+	fc_conf->send_xon = fc.send_xon;
>+	fc_conf->mode = fc.mode;
>+
>+	return 0;
>+}
>+
>+static int
>+axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf 
>+*fc_conf) {
>+	struct axgbe_port *pdata = dev->data->dev_private;
>+	struct xgbe_fc_info fc = pdata->fc;
>+	unsigned int reg, reg_val = 0;
>+	reg = MAC_Q0TFCR;
>+
>+	pdata->pause_autoneg = fc_conf->autoneg;
>+	pdata->phy.pause_autoneg = pdata->pause_autoneg;
>+	fc.send_xon = fc_conf->send_xon;
>+	AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
>+			AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
>+	AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
>+			AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
>+	AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
>+	AXGMAC_IOWRITE(pdata, reg, reg_val);
>+	fc.mode = fc_conf->mode;
>+
>+	if (fc.mode == RTE_FC_FULL) {
>+		pdata->tx_pause = 1;
>+		pdata->rx_pause = 1;
>+	} else if (fc.mode == RTE_FC_RX_PAUSE) {
>+		pdata->tx_pause = 0;
>+		pdata->rx_pause = 1;
>+	} else if (fc.mode == RTE_FC_TX_PAUSE) {
>+		pdata->tx_pause = 1;
>+		pdata->rx_pause = 0;
>+	} else {
>+		pdata->tx_pause = 0;
>+		pdata->rx_pause = 0;
>+	}
>+
>+	if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
>+		pdata->hw_if.config_tx_flow_control(pdata);
>+
>+	if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
>+		pdata->hw_if.config_rx_flow_control(pdata);
>+
>+	pdata->hw_if.config_flow_control(pdata);
>+	pdata->phy.tx_pause = pdata->tx_pause;
>+	pdata->phy.rx_pause = pdata->rx_pause;
>+
>+	return 0;
>+}
>+
> static void axgbe_get_all_hw_features(struct axgbe_port *pdata)  {
> 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
>index a1083b17b..436d780c9 100644
>--- a/drivers/net/axgbe/axgbe_ethdev.h
>+++ b/drivers/net/axgbe/axgbe_ethdev.h
>@@ -485,6 +485,16 @@ struct axgbe_mmc_stats {
> 	uint64_t rxwatchdogerror;
> };
> 
>+/* Flow control parameters */
>+struct xgbe_fc_info {
>+	uint32_t high_water[AXGBE_PRIORITY_QUEUES];
>+	uint32_t low_water[AXGBE_PRIORITY_QUEUES];
>+	uint16_t pause_time[AXGBE_PRIORITY_QUEUES];
>+	uint16_t send_xon;
>+	enum rte_eth_fc_mode mode;
>+	uint8_t autoneg;
>+};
>+
> /*
>  * Structure to store private data for each port.
>  */
>@@ -625,6 +635,7 @@ struct axgbe_port {
> 	uint32_t rx_csum_enable;
> 
> 	struct axgbe_mmc_stats mmc_stats;
>+	struct xgbe_fc_info fc;
> };
> 
> void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
>--
>2.17.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API
  2020-03-16  3:53 ` [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " Kumar, Ravi1
@ 2020-03-16 12:52   ` Ferruh Yigit
  0 siblings, 0 replies; 6+ messages in thread
From: Ferruh Yigit @ 2020-03-16 12:52 UTC (permalink / raw)
  To: Kumar, Ravi1, Somalapuram, Amaranath, dev

On 3/16/2020 3:53 AM, Kumar, Ravi1 wrote:
<...>>> From: Amaranath Somalapuram <asomalap@amd.com>
>>
>> Adding api for flow_ctrl_get and flow_ctrl_set.
>> By default axgbe driver flow control is disabled.
>> Adding dpdk flow control to set water high and low.
>>
>> Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
>
> For series,
> Acked-by: Ravi Kumar <ravi1.kumar@amd.com>
>

Series applied to dpdk-next-net/master, thanks.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority flow control API
  2020-03-02  8:15 asomalap
@ 2020-03-02  8:15 ` asomalap
  0 siblings, 0 replies; 6+ messages in thread
From: asomalap @ 2020-03-02  8:15 UTC (permalink / raw)
  To: dev; +Cc: Ravi1.Kumar

From: Amaranath Somalapuram <asomalap@amd.com>

Adding API for  priority_flow_ctrl_set.
Priority flow control to set water high and low,
pause_time and priority.

Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
---
 drivers/net/axgbe/axgbe_ethdev.c | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867c4744f..e7b731b2e 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -51,6 +51,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
+static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+				struct rte_eth_pfc_conf *pfc_conf);
 
 struct axgbe_xstats {
 	char name[RTE_ETH_XSTATS_NAME_SIZE];
@@ -180,6 +182,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
 	.tx_queue_release     = axgbe_dev_tx_queue_release,
 	.flow_ctrl_get        = axgbe_flow_ctrl_get,
 	.flow_ctrl_set        = axgbe_flow_ctrl_set,
+	.priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
 };
 
 static int axgbe_phy_reset(struct axgbe_port *pdata)
@@ -927,6 +930,97 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	return 0;
 }
 
+static int
+axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+		struct rte_eth_pfc_conf *pfc_conf)
+{
+	struct axgbe_port *pdata = dev->data->dev_private;
+	struct xgbe_fc_info fc = pdata->fc;
+	uint8_t tc_num;
+
+	tc_num = pdata->pfc_map[pfc_conf->priority];
+
+	if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
+		PMD_INIT_LOG(ERR, "Max supported  traffic class: %d\n",
+				pdata->hw_feat.tc_cnt);
+	return -EINVAL;
+	}
+
+	pdata->pause_autoneg = pfc_conf->fc.autoneg;
+	pdata->phy.pause_autoneg = pdata->pause_autoneg;
+	fc.send_xon = pfc_conf->fc.send_xon;
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
+
+	switch (tc_num) {
+	case 0:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC0, pfc_conf->fc.pause_time);
+		break;
+	case 1:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC1, pfc_conf->fc.pause_time);
+		break;
+	case 2:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC2, pfc_conf->fc.pause_time);
+		break;
+	case 3:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC3, pfc_conf->fc.pause_time);
+		break;
+	case 4:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC4, pfc_conf->fc.pause_time);
+		break;
+	case 5:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC5, pfc_conf->fc.pause_time);
+		break;
+	case 7:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC6, pfc_conf->fc.pause_time);
+		break;
+	case 6:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC7, pfc_conf->fc.pause_time);
+		break;
+	}
+
+	fc.mode = pfc_conf->fc.mode;
+
+	if (fc.mode == RTE_FC_FULL) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_RX_PAUSE) {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_TX_PAUSE) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	} else {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	}
+
+	if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
+		pdata->hw_if.config_tx_flow_control(pdata);
+
+	if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
+		pdata->hw_if.config_rx_flow_control(pdata);
+	pdata->hw_if.config_flow_control(pdata);
+	pdata->phy.tx_pause = pdata->tx_pause;
+	pdata->phy.rx_pause = pdata->rx_pause;
+
+	return 0;
+}
+
 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
 {
 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority flow control API
  2020-03-02  7:46 [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " asomalap
@ 2020-03-02  7:46 ` asomalap
  0 siblings, 0 replies; 6+ messages in thread
From: asomalap @ 2020-03-02  7:46 UTC (permalink / raw)
  To: dev; +Cc: Ravi1.Kumar

From: Amaranath Somalapuram <asomalap@amd.com>

Adding API for  priority_flow_ctrl_set.
Priority flow control to set water high and low,
pause_time and priority.

Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
---
 drivers/net/axgbe/axgbe_ethdev.c | 94 ++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867c4744f..e7b731b2e 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -51,6 +51,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
+static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+				struct rte_eth_pfc_conf *pfc_conf);
 
 struct axgbe_xstats {
 	char name[RTE_ETH_XSTATS_NAME_SIZE];
@@ -180,6 +182,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
 	.tx_queue_release     = axgbe_dev_tx_queue_release,
 	.flow_ctrl_get        = axgbe_flow_ctrl_get,
 	.flow_ctrl_set        = axgbe_flow_ctrl_set,
+	.priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
 };
 
 static int axgbe_phy_reset(struct axgbe_port *pdata)
@@ -927,6 +930,97 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	return 0;
 }
 
+static int
+axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
+		struct rte_eth_pfc_conf *pfc_conf)
+{
+	struct axgbe_port *pdata = dev->data->dev_private;
+	struct xgbe_fc_info fc = pdata->fc;
+	uint8_t tc_num;
+
+	tc_num = pdata->pfc_map[pfc_conf->priority];
+
+	if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
+		PMD_INIT_LOG(ERR, "Max supported  traffic class: %d\n",
+				pdata->hw_feat.tc_cnt);
+	return -EINVAL;
+	}
+
+	pdata->pause_autoneg = pfc_conf->fc.autoneg;
+	pdata->phy.pause_autoneg = pdata->pause_autoneg;
+	fc.send_xon = pfc_conf->fc.send_xon;
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
+	AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
+		AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
+
+	switch (tc_num) {
+	case 0:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC0, pfc_conf->fc.pause_time);
+		break;
+	case 1:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC1, pfc_conf->fc.pause_time);
+		break;
+	case 2:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC2, pfc_conf->fc.pause_time);
+		break;
+	case 3:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
+				PSTC3, pfc_conf->fc.pause_time);
+		break;
+	case 4:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC4, pfc_conf->fc.pause_time);
+		break;
+	case 5:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC5, pfc_conf->fc.pause_time);
+		break;
+	case 7:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC6, pfc_conf->fc.pause_time);
+		break;
+	case 6:
+		AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
+				PSTC7, pfc_conf->fc.pause_time);
+		break;
+	}
+
+	fc.mode = pfc_conf->fc.mode;
+
+	if (fc.mode == RTE_FC_FULL) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_RX_PAUSE) {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 1;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
+	} else if (fc.mode == RTE_FC_TX_PAUSE) {
+		pdata->tx_pause = 1;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	} else {
+		pdata->tx_pause = 0;
+		pdata->rx_pause = 0;
+		AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
+	}
+
+	if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
+		pdata->hw_if.config_tx_flow_control(pdata);
+
+	if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
+		pdata->hw_if.config_rx_flow_control(pdata);
+	pdata->hw_if.config_flow_control(pdata);
+	pdata->phy.tx_pause = pdata->tx_pause;
+	pdata->phy.rx_pause = pdata->rx_pause;
+
+	return 0;
+}
+
 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
 {
 	unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2020-03-16 12:52 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-03  8:19 [dpdk-dev] [PATCH v4 1/2] net/axgbe: support flow control API asomalap
2020-03-03  8:19 ` [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority " asomalap
2020-03-16  3:53 ` [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " Kumar, Ravi1
2020-03-16 12:52   ` Ferruh Yigit
  -- strict thread matches above, loose matches on Subject: below --
2020-03-02  8:15 asomalap
2020-03-02  8:15 ` [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority " asomalap
2020-03-02  7:46 [dpdk-dev] [PATCH v4 1/2] net/axgbe: support " asomalap
2020-03-02  7:46 ` [dpdk-dev] [PATCH v4 2/2] net/axgbe: support priority " asomalap

DPDK patches and discussions

This inbox may be cloned and mirrored by anyone:

	git clone --mirror http://inbox.dpdk.org/dev/0 dev/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 dev dev/ http://inbox.dpdk.org/dev \
		dev@dpdk.org
	public-inbox-index dev

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.dpdk.org/inbox.dpdk.dev


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git