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* [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support
@ 2020-07-30 14:42 Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap Manish Chopra
                   ` (5 more replies)
  0 siblings, 6 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

Hi,

This series adds SR-IOV PF pmd driver support to have VF pmd
driver work over PF pmd driver instances in order to run the
adapter completely under DPDK environment for one of the use
cases like ovs-dpdk.

This is very initial bring-up with following testing covered -

* Enable/Disable SR-IOV VFs through igb_uio sysfs hook.
* Load VFs, run fastpath, teardown VFs in hypervisor and guest VM.
* VF FLR flow (in case of VF PCI passthrough to the guest VM)
* Bulletin mechanism tested to communicate link changes to the VFs.

Note that this series is intended for upcoming DPDK release (20.08)
Please consider applying this series to dpdk-next-net-mrvl.git

V4->V5:
=======

* drivers/raw/ifpga was escaped to compile, test-robot reported
  below build failure which is fixed within patch #1 in this series.

'drivers/drivers@@tmp_rte_rawdev_ifpga@sta/raw_ifpga_ifpga_rawdev.c.o' -c ../drivers/raw/ifpga/ifpga_rawdev.c
../drivers/raw/ifpga/ifpga_rawdev.c: In function ‘ifpga_pci_find_next_ext_capability’:
../drivers/raw/ifpga/ifpga_rawdev.c:166:34: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare]
   if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
                                  ^~
cc1: all warnings being treated as errors

V3->V4:
=======

* Fixed meson/ninja build failure for AMD arch.
* Incorporated cosmetic changes pointed by Gaetan.

V2->V3:
=======

* Instead of adding complete pci_regs.h file from linux, define handful
  PCI symbols (prefixed with RTE_) in dpdk which are required to implement
  generic rte_pci_find_next_ext_capability() API (patch #1) and to enable
  various other qede driver's OSAL_* defines (patch #2)
  (essentially, removed the patch #1 in v2)

* Fixed meson/ninja compilation issues reported

* Incorporated comments by Gaetan for rte_pci_find_next_ext_capability()

V1->V2: (Incorporated comments from Jerin Jacob)
================================================

* Added rte_pci_regs.h file (copy of linux/pci_regs.h) under
  lib/librte_pci to remove the dependency of dpdk on user headers

* Added generic API to find PCI extended capability and use
  that in the drivers, removed individual functions implemented
  by the drivers

Thanks,
Manish

Manish Chopra (6):
  drivers: add generic API to find PCI extended cap
  net/qede: define PCI config space specific osals
  net/qede: configure VFs on hardware
  net/qede: add infrastructure support for VF load
  net/qede: initialize VF MAC and link
  net/qede: add VF FLR support

 doc/guides/nics/features/qede.ini          |   1 +
 doc/guides/nics/qede.rst                   |   7 +-
 drivers/bus/pci/pci_common.c               |  43 ++++
 drivers/bus/pci/rte_bus_pci.h              |  20 ++
 drivers/bus/pci/rte_bus_pci_version.map    |   6 +
 drivers/net/ice/ice_ethdev.c               |  51 +----
 drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c |  48 +----
 drivers/net/qede/Makefile                  |   1 +
 drivers/net/qede/base/bcm_osal.c           |  31 +++
 drivers/net/qede/base/bcm_osal.h           |  29 ++-
 drivers/net/qede/base/ecore.h              |   7 +
 drivers/net/qede/base/ecore_dev.c          |   6 +-
 drivers/net/qede/base/ecore_iov_api.h      |   3 +
 drivers/net/qede/base/ecore_sriov.c        |  28 +--
 drivers/net/qede/base/meson.build          |   2 +-
 drivers/net/qede/meson.build               |   1 +
 drivers/net/qede/qede_ethdev.c             |  37 +++-
 drivers/net/qede/qede_ethdev.h             |   1 +
 drivers/net/qede/qede_if.h                 |   1 +
 drivers/net/qede/qede_main.c               |  13 +-
 drivers/net/qede/qede_sriov.c              | 219 +++++++++++++++++++++
 drivers/net/qede/qede_sriov.h              |  22 +++
 drivers/raw/ifpga/ifpga_rawdev.c           |  17 +-
 lib/librte_pci/rte_pci.h                   |  35 ++++
 24 files changed, 488 insertions(+), 141 deletions(-)
 create mode 100644 drivers/net/qede/qede_sriov.c
 create mode 100644 drivers/net/qede/qede_sriov.h

-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  2020-08-07 17:46   ` Nithin Dabilpuram
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 2/6] net/qede: define PCI config space specific osals Manish Chopra
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

By adding generic API, this patch removes individual
functions/defines implemented by drivers to find extended
PCI capabilities.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
---
 drivers/bus/pci/pci_common.c               | 43 ++++++++++++++++++
 drivers/bus/pci/rte_bus_pci.h              | 20 +++++++++
 drivers/bus/pci/rte_bus_pci_version.map    |  6 +++
 drivers/net/ice/ice_ethdev.c               | 51 +---------------------
 drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 +-------------------
 drivers/raw/ifpga/ifpga_rawdev.c           | 17 +++-----
 lib/librte_pci/rte_pci.h                   | 16 +++++++
 7 files changed, 95 insertions(+), 106 deletions(-)

diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
index a8e5fd52c..98c1f8155 100644
--- a/drivers/bus/pci/pci_common.c
+++ b/drivers/bus/pci/pci_common.c
@@ -665,6 +665,49 @@ rte_pci_get_iommu_class(void)
 	return iova_mode;
 }
 
+off_t
+rte_pci_find_next_ext_capability(struct rte_pci_device *dev, uint32_t cap)
+{
+	off_t offset = RTE_PCI_CFG_SPACE_SIZE;
+	uint32_t header;
+	int ttl;
+
+	/* minimum 8 bytes per capability */
+	ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
+
+	if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+		RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
+		return -1;
+	}
+
+	/*
+	 * If we have no capabilities, this is indicated by cap ID,
+	 * cap version and next pointer all being 0.
+	 */
+	if (header == 0)
+		return 0;
+
+	while (ttl != 0) {
+		if (RTE_PCI_EXT_CAP_ID(header) == cap)
+			return offset;
+
+		offset = RTE_PCI_EXT_CAP_NEXT(header);
+
+		if (offset < RTE_PCI_CFG_SPACE_SIZE)
+			break;
+
+		if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+			RTE_LOG(ERR, EAL,
+				"error in reading extended capabilities\n");
+			return -1;
+		}
+
+		ttl--;
+	}
+
+	return 0;
+}
+
 struct rte_pci_bus rte_pci_bus = {
 	.bus = {
 		.scan = rte_pci_scan,
diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
index 29bea6d70..f11af3762 100644
--- a/drivers/bus/pci/rte_bus_pci.h
+++ b/drivers/bus/pci/rte_bus_pci.h
@@ -224,6 +224,26 @@ void rte_pci_unmap_device(struct rte_pci_device *dev);
  */
 void rte_pci_dump(FILE *f);
 
+/**
+ * Find device's extended PCI capability.
+ *
+ *  @param dev
+ *    A pointer to rte_pci_device structure.
+ *
+ *  @param cap
+ *    Extended capability to be found, which can be any from
+ *    RTE_PCI_EXT_CAP_ID_*, defined in librte_pci.
+ *
+ *  @return
+ *  > 0: The offset of the next matching extended capability structure
+ *       within the device's PCI configuration space.
+ *  < 0: An error in PCI config space read.
+ *  = 0: Device does not support it.
+ */
+__rte_experimental
+off_t rte_pci_find_next_ext_capability(struct rte_pci_device *dev,
+				       uint32_t cap);
+
 /**
  * Register a PCI driver.
  *
diff --git a/drivers/bus/pci/rte_bus_pci_version.map b/drivers/bus/pci/rte_bus_pci_version.map
index 012d817e1..b5322660d 100644
--- a/drivers/bus/pci/rte_bus_pci_version.map
+++ b/drivers/bus/pci/rte_bus_pci_version.map
@@ -16,3 +16,9 @@ DPDK_20.0 {
 
 	local: *;
 };
+
+EXPERIMENTAL {
+	global:
+
+	rte_pci_find_next_ext_capability;
+};
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 7dd3fcd27..6c8cbea5c 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -1730,53 +1730,6 @@ ice_pf_setup(struct ice_pf *pf)
 	return 0;
 }
 
-/* PCIe configuration space setting */
-#define PCI_CFG_SPACE_SIZE          256
-#define PCI_CFG_SPACE_EXP_SIZE      4096
-#define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
-#define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
-#define PCI_EXT_CAP_ID_DSN          0x03
-
-static int
-ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
-{
-	uint32_t header;
-	int ttl;
-	int pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
-	if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
-		PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
-		return -1;
-	}
-
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
-			PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
 /*
  * Extract device serial number from PCIe Configuration Space and
  * determine the pkg file path according to the DSN.
@@ -1784,12 +1737,12 @@ ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
 static int
 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
 {
-	int pos;
+	off_t pos;
 	char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
 	uint32_t dsn_low, dsn_high;
 	memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
 
-	pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
+	pos = rte_pci_find_next_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
 
 	if (pos) {
 		rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
diff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
index 0b9db974e..dbab4f8cb 100644
--- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
+++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
@@ -746,59 +746,15 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)
 	return 0;
 }
 
-#define PCI_CFG_SPACE_SIZE	256
-#define PCI_CFG_SPACE_EXP_SIZE	4096
-#define PCI_EXT_CAP_ID(header)		(int)(header & 0x0000ffff)
-#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
-#define PCI_EXT_CAP_ID_DSN	0x03
-static int
-nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
-{
-	uint32_t header;
-	int ttl;
-	int pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
-	if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
-		printf("nfp error reading extended capabilities\n");
-		return -1;
-	}
-
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
-			printf("nfp error reading extended capabilities\n");
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
 static int
 nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)
 {
 	uint16_t tmp;
 	uint8_t serial[6];
 	int serial_len = 6;
-	int pos;
+	off_t pos;
 
-	pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
+	pos = rte_pci_find_next_ext_capability(dev, RTE_PCI_EXT_CAP_ID_DSN);
 	if (pos <= 0) {
 		printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n");
 		return -1;
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index cc25c662b..07aef4f6e 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -41,12 +41,6 @@
 #include "ifpga_rawdev.h"
 #include "ipn3ke_rawdev_api.h"
 
-#define RTE_PCI_EXT_CAP_ID_ERR           0x01	/* Advanced Error Reporting */
-#define RTE_PCI_CFG_SPACE_SIZE           256
-#define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
-#define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
-#define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
-
 #define PCI_VENDOR_ID_INTEL          0x8086
 /* PCI Device ID */
 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
@@ -86,8 +80,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
 static int set_surprise_link_check_aer(
 		struct ifpga_rawdev *ifpga_rdev, int force_disable);
 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
-		int start, int cap);
-static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
+					      int start, uint32_t cap);
+static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
 
 struct ifpga_rawdev *
 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
@@ -144,8 +138,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 	return dev;
 }
 
-static int ifpga_pci_find_next_ext_capability(unsigned int fd,
-int start, int cap)
+static int
+ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 {
 	uint32_t header;
 	int ttl;
@@ -183,7 +177,8 @@ int start, int cap)
 	return 0;
 }
 
-static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
+static int
+ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 {
 	return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 }
diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
index a03235da1..fec51e15a 100644
--- a/lib/librte_pci/rte_pci.h
+++ b/lib/librte_pci/rte_pci.h
@@ -22,6 +22,22 @@ extern "C" {
 #include <inttypes.h>
 #include <sys/types.h>
 
+
+/*
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
+ * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
+ * configuration space.
+ */
+#define RTE_PCI_CFG_SPACE_SIZE		256
+#define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
+
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+#define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
+#define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
+
+#define RTE_PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
+#define RTE_PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
+
 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 2/6] net/qede: define PCI config space specific osals
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 3/6] net/qede: configure VFs on hardware Manish Chopra
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

This patch defines various PCI config space access APIs
in order to read and find IOV specific PCI capabilities.

With these definitions implemented, it enables the base
driver to do SR-IOV specific initialization and HW specific
configuration required from PF-PMD driver instance.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 drivers/net/qede/base/bcm_osal.h    | 14 +++++++++-----
 drivers/net/qede/base/ecore.h       |  3 +++
 drivers/net/qede/base/ecore_dev.c   |  6 +++---
 drivers/net/qede/base/ecore_sriov.c | 28 +++++++++++++++-------------
 drivers/net/qede/base/meson.build   |  2 +-
 drivers/net/qede/qede_main.c        |  1 +
 lib/librte_pci/rte_pci.h            | 23 +++++++++++++++++++++--
 7 files changed, 53 insertions(+), 24 deletions(-)

diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index 5d4df5907..5f55cc2ee 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -21,6 +21,7 @@
 #include <rte_ether.h>
 #include <rte_io.h>
 #include <rte_version.h>
+#include <rte_bus_pci.h>
 
 /* Forward declaration */
 struct ecore_dev;
@@ -286,11 +287,14 @@ typedef struct osal_list_t {
 	OSAL_LIST_PUSH_HEAD(new_entry, list)
 
 /* PCI config space */
-
-#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing
-#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0
+#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 1, address)
+#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 2, address)
+#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \
+	rte_pci_read_config((dev)->pci_dev, dst, 4, address)
+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \
+	rte_pci_find_next_ext_capability((dev)->pci_dev, cap)
 #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0
 #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing
 #define OSAL_BAR_SIZE(dev, bar_id) 0
diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 63bd7466a..750e99a8f 100644
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -937,6 +937,9 @@ struct ecore_dev {
 	struct ecore_dbg_feature	dbg_features[DBG_FEATURE_NUM];
 	struct ecore_dbg_params		dbg_params;
 	osal_mutex_t			dbg_lock;
+
+	/* DPDK specific ecore field */
+	struct rte_pci_device		*pci_dev;
 };
 
 enum ecore_hsi_def_type {
diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 35a8394de..e895dee40 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -2787,7 +2787,7 @@ static enum _ecore_status_t ecore_hw_init_chip(struct ecore_dev *p_dev,
 		return ECORE_IO;
 	}
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);
 	wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
 	ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
 
@@ -5499,9 +5499,9 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
 	u32 tmp;
 
 	/* Read Vendor Id / Device Id */
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID,
 				  &p_dev->vendor_id);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID,
 				  &p_dev->device_id);
 
 	/* Determine type */
diff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c
index e60257e19..dac4cbee8 100644
--- a/drivers/net/qede/base/ecore_sriov.c
+++ b/drivers/net/qede/base/ecore_sriov.c
@@ -417,15 +417,16 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)
 	int pos = iov->pos;
 
 	DP_VERBOSE(p_dev, ECORE_MSG_IOV, "sriov ext pos %d\n", pos);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_CTRL, &iov->ctrl);
 
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_TOTAL_VF,
+				  &iov->total_vfs);
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
-	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_INITIAL_VF,
+				  pos + RTE_PCI_SRIOV_INITIAL_VF,
 				  &iov->initial_vfs);
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_NUM_VF,
+				  &iov->num_vfs);
 	if (iov->num_vfs) {
 		/* @@@TODO - in future we might want to add an OSAL here to
 		 * allow each OS to decide on its own how to act.
@@ -437,20 +438,21 @@ static enum _ecore_status_t ecore_iov_pci_cfg_info(struct ecore_dev *p_dev)
 	}
 
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
+				  pos + RTE_PCI_SRIOV_VF_OFFSET, &iov->offset);
 
 	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
+				  pos + RTE_PCI_SRIOV_VF_STRIDE, &iov->stride);
 
-	OSAL_PCI_READ_CONFIG_WORD(p_dev,
-				  pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
+	OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_SRIOV_VF_DID,
+				  &iov->vf_device_id);
 
 	OSAL_PCI_READ_CONFIG_DWORD(p_dev,
-				   pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
+				   pos + RTE_PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
 
-	OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + PCI_SRIOV_CAP, &iov->cap);
+	OSAL_PCI_READ_CONFIG_DWORD(p_dev, pos + RTE_PCI_SRIOV_CAP, &iov->cap);
 
-	OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
+	OSAL_PCI_READ_CONFIG_BYTE(p_dev, pos + RTE_PCI_SRIOV_FUNC_LINK,
+				  &iov->link);
 
 	DP_VERBOSE(p_dev, ECORE_MSG_IOV, "IOV info: nres %d, cap 0x%x,"
 		   "ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d,"
@@ -669,7 +671,7 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn)
 
 	/* Learn the PCI configuration */
 	pos = OSAL_PCI_FIND_EXT_CAPABILITY(p_hwfn->p_dev,
-					   PCI_EXT_CAP_ID_SRIOV);
+					   RTE_PCI_EXT_CAP_ID_SRIOV);
 	if (!pos) {
 		DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "No PCIe IOV support\n");
 		return ECORE_SUCCESS;
diff --git a/drivers/net/qede/base/meson.build b/drivers/net/qede/base/meson.build
index 59b41c895..03a6c44f5 100644
--- a/drivers/net/qede/base/meson.build
+++ b/drivers/net/qede/base/meson.build
@@ -52,6 +52,6 @@ foreach flag: error_cflags
 endforeach
 
 base_lib = static_library('qede_base', sources,
-	dependencies: static_rte_net,
+	dependencies: [static_rte_net, static_rte_bus_pci],
 	c_args: c_args)
 base_objs = base_lib.extract_all_objects()
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index 987a6f1e1..d919f9f11 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
 	edev->regview = pci_dev->mem_resource[0].addr;
 	edev->doorbells = pci_dev->mem_resource[2].addr;
 	edev->db_size = pci_dev->mem_resource[2].len;
+	edev->pci_dev = pci_dev;
 }
 
 static int
diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
index fec51e15a..a018a6e9a 100644
--- a/lib/librte_pci/rte_pci.h
+++ b/lib/librte_pci/rte_pci.h
@@ -31,12 +31,31 @@ extern "C" {
 #define RTE_PCI_CFG_SPACE_SIZE		256
 #define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
 
+#define RTE_PCI_VENDOR_ID	0x00	/* 16 bits */
+#define RTE_PCI_DEVICE_ID	0x02	/* 16 bits */
+
+/* PCI Express capability registers */
+#define RTE_PCI_EXP_DEVCTL	8	/* Device Control */
+
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
 #define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
 
-#define RTE_PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
-#define RTE_PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
+#define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
+#define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
+#define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
+
+/* Single Root I/O Virtualization */
+#define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
+#define RTE_PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
+#define RTE_PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */
+#define RTE_PCI_SRIOV_TOTAL_VF		0x0e	/* Total VFs */
+#define RTE_PCI_SRIOV_NUM_VF		0x10	/* Number of VFs */
+#define RTE_PCI_SRIOV_FUNC_LINK		0x12	/* Function Dependency Link */
+#define RTE_PCI_SRIOV_VF_OFFSET		0x14	/* First VF Offset */
+#define RTE_PCI_SRIOV_VF_STRIDE		0x16	/* Following VF Stride */
+#define RTE_PCI_SRIOV_VF_DID		0x1a	/* VF Device ID */
+#define RTE_PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
 
 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 3/6] net/qede: configure VFs on hardware
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 2/6] net/qede: define PCI config space specific osals Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 4/6] net/qede: add infrastructure support for VF load Manish Chopra
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

Based on number of VFs enabled at PCI, PF-PMD driver instance
enables/configures those VFs from hardware perspective, such
that in later patches they could get required HW access to
communicate with PFs for slowpath configuration and run the
fastpath themsleves.

This patch also add two new qede IOV files [qede_sriov(.c|.h)]
under qede directory to add non-base driver IOV APIs/contents there.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 drivers/net/qede/Makefile      |  1 +
 drivers/net/qede/meson.build   |  1 +
 drivers/net/qede/qede_ethdev.c |  1 +
 drivers/net/qede/qede_ethdev.h |  1 +
 drivers/net/qede/qede_if.h     |  1 +
 drivers/net/qede/qede_main.c   |  1 +
 drivers/net/qede/qede_sriov.c  | 85 ++++++++++++++++++++++++++++++++++
 drivers/net/qede/qede_sriov.h  |  9 ++++
 8 files changed, 100 insertions(+)
 create mode 100644 drivers/net/qede/qede_sriov.c
 create mode 100644 drivers/net/qede/qede_sriov.h

diff --git a/drivers/net/qede/Makefile b/drivers/net/qede/Makefile
index 0e8a67b0d..c57bef0e3 100644
--- a/drivers/net/qede/Makefile
+++ b/drivers/net/qede/Makefile
@@ -105,5 +105,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_rxtx.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_filter.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_debug.c
 SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_regs.c
+SRCS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede_sriov.c
 
 include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/qede/meson.build b/drivers/net/qede/meson.build
index 05c9bff73..ff0ac0b03 100644
--- a/drivers/net/qede/meson.build
+++ b/drivers/net/qede/meson.build
@@ -11,6 +11,7 @@ sources = files(
 	'qede_rxtx.c',
 	'qede_debug.c',
 	'qede_regs.c',
+	'qede_sriov.c',
 )
 
 if cc.has_argument('-Wno-format-nonliteral')
diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index 70d48e48e..0235c0798 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -2700,6 +2700,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
 		adapter->vxlan.enable = false;
 		adapter->geneve.enable = false;
 		adapter->ipgre.enable = false;
+		qed_ops->sriov_configure(edev, pci_dev->max_vfs);
 	}
 
 	DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h
index 76c5dae3b..4fb77b05c 100644
--- a/drivers/net/qede/qede_ethdev.h
+++ b/drivers/net/qede/qede_ethdev.h
@@ -34,6 +34,7 @@
 #include "base/ecore_l2.h"
 #include "base/ecore_vf.h"
 
+#include "qede_sriov.h"
 #include "qede_logs.h"
 #include "qede_if.h"
 #include "qede_rxtx.h"
diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h
index c5ae3fb2e..1693a243f 100644
--- a/drivers/net/qede/qede_if.h
+++ b/drivers/net/qede/qede_if.h
@@ -82,6 +82,7 @@ struct qed_eth_ops {
 	const struct qed_common_ops *common;
 	int (*fill_dev_info)(struct ecore_dev *edev,
 			     struct qed_dev_eth_info *info);
+	void (*sriov_configure)(struct ecore_dev *edev, int num_vfs);
 };
 
 struct qed_link_params {
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index d919f9f11..c37e8ebe0 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -822,6 +822,7 @@ const struct qed_common_ops qed_common_ops_pass = {
 const struct qed_eth_ops qed_eth_ops_pass = {
 	INIT_STRUCT_FIELD(common, &qed_common_ops_pass),
 	INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info),
+	INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure),
 };
 
 const struct qed_eth_ops *qed_get_eth_ops(void)
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
new file mode 100644
index 000000000..ba4384e90
--- /dev/null
+++ b/drivers/net/qede/qede_sriov.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2020 Marvell.
+ * All rights reserved.
+ * www.marvell.com
+ */
+
+#include "qede_sriov.h"
+
+static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn,
+					u16 vfid,
+					struct ecore_iov_vf_init_params *params)
+{
+	u16 num_pf_l2_queues, base, i;
+
+	/* Since we have an equal resource distribution per-VF, and we assume
+	 * PF has acquired its first queues, we start setting sequentially from
+	 * there.
+	 */
+	num_pf_l2_queues = (u16)FEAT_NUM(hwfn, ECORE_PF_L2_QUE);
+
+	base = num_pf_l2_queues + vfid * params->num_queues;
+	params->rel_vf_id = vfid;
+
+	for (i = 0; i < params->num_queues; i++) {
+		params->req_rx_queue[i] = base + i;
+		params->req_tx_queue[i] = base + i;
+	}
+
+	/* PF uses indices 0 for itself; Set vport/RSS afterwards */
+	params->vport_id = vfid + 1;
+	params->rss_eng_id = vfid + 1;
+}
+
+static void qed_sriov_enable(struct ecore_dev *edev, int num)
+{
+	struct ecore_iov_vf_init_params params;
+	struct ecore_hwfn *p_hwfn;
+	struct ecore_ptt *p_ptt;
+	int i, j, rc;
+
+	if ((u32)num >= RESC_NUM(&edev->hwfns[0], ECORE_VPORT)) {
+		DP_NOTICE(edev, false, "Can start at most %d VFs\n",
+			  RESC_NUM(&edev->hwfns[0], ECORE_VPORT) - 1);
+		return;
+	}
+
+	OSAL_MEMSET(&params, 0, sizeof(struct ecore_iov_vf_init_params));
+
+	for_each_hwfn(edev, j) {
+		int feat_num;
+
+		p_hwfn = &edev->hwfns[j];
+		p_ptt = ecore_ptt_acquire(p_hwfn);
+		feat_num = FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE) / num;
+
+		params.num_queues = OSAL_MIN_T(int, feat_num, 16);
+
+		for (i = 0; i < num; i++) {
+			if (!ecore_iov_is_valid_vfid(p_hwfn, i, false, true))
+				continue;
+
+			qed_sriov_enable_qid_config(p_hwfn, i, &params);
+
+			rc = ecore_iov_init_hw_for_vf(p_hwfn, p_ptt, &params);
+			if (rc) {
+				DP_ERR(edev, "Failed to enable VF[%d]\n", i);
+				ecore_ptt_release(p_hwfn, p_ptt);
+				return;
+			}
+		}
+
+		ecore_ptt_release(p_hwfn, p_ptt);
+	}
+}
+
+void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param)
+{
+	if (!IS_ECORE_SRIOV(edev)) {
+		DP_VERBOSE(edev, ECORE_MSG_IOV, "SR-IOV is not supported\n");
+		return;
+	}
+
+	if (num_vfs_param)
+		qed_sriov_enable(edev, num_vfs_param);
+}
diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h
new file mode 100644
index 000000000..6c85b1dd5
--- /dev/null
+++ b/drivers/net/qede/qede_sriov.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2020 Marvell.
+ * All rights reserved.
+ * www.marvell.com
+ */
+
+#include "qede_ethdev.h"
+
+void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 4/6] net/qede: add infrastructure support for VF load
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
                   ` (2 preceding siblings ...)
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 3/6] net/qede: configure VFs on hardware Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 5/6] net/qede: initialize VF MAC and link Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 6/6] net/qede: add VF FLR support Manish Chopra
  5 siblings, 0 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

This patch adds necessary infrastructure support (required to handle
messages from VF and sending ramrod on behalf of VF's configuration
request from alarm handler context) to start/load the VF-PMD driver
instance on top of PF-PMD driver instance.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 drivers/net/qede/base/bcm_osal.c      | 26 ++++++++++++
 drivers/net/qede/base/bcm_osal.h      | 11 +++--
 drivers/net/qede/base/ecore.h         |  4 ++
 drivers/net/qede/base/ecore_iov_api.h |  3 ++
 drivers/net/qede/qede_ethdev.c        |  2 +
 drivers/net/qede/qede_main.c          |  4 +-
 drivers/net/qede/qede_sriov.c         | 61 +++++++++++++++++++++++++++
 drivers/net/qede/qede_sriov.h         | 16 ++++++-
 8 files changed, 121 insertions(+), 6 deletions(-)

diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c
index 65837b53d..ef47339df 100644
--- a/drivers/net/qede/base/bcm_osal.c
+++ b/drivers/net/qede/base/bcm_osal.c
@@ -14,6 +14,32 @@
 #include "ecore_iov_api.h"
 #include "ecore_mcp_api.h"
 #include "ecore_l2_api.h"
+#include "../qede_sriov.h"
+
+int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn)
+{
+	int rc;
+
+	rc = qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG);
+	if (rc) {
+		DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
+			   "Failed to schedule alarm handler rc=%d\n", rc);
+	}
+
+	return rc;
+}
+
+void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie)
+{
+	struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
+
+	if (!p_hwfn)
+		return;
+
+	OSAL_SPIN_LOCK(&p_hwfn->spq_lock);
+	ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
+	OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);
+}
 
 /* Array of memzone pointers */
 static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index 5f55cc2ee..cf58db8bf 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -178,9 +178,12 @@ typedef pthread_mutex_t osal_mutex_t;
 
 /* DPC */
 
+void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie);
 #define OSAL_DPC_ALLOC(hwfn) OSAL_ALLOC(hwfn, GFP, sizeof(osal_dpc_t))
-#define OSAL_DPC_INIT(dpc, hwfn) nothing
-#define OSAL_POLL_MODE_DPC(hwfn) nothing
+#define OSAL_DPC_INIT(dpc, hwfn) \
+	OSAL_SPIN_LOCK_INIT(&(hwfn)->spq_lock)
+#define OSAL_POLL_MODE_DPC(hwfn) \
+	osal_poll_mode_dpc((osal_int_ptr_t)(p_hwfn))
 #define OSAL_DPC_SYNC(hwfn) nothing
 
 /* Lists */
@@ -345,10 +348,12 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length);
 
 /* SR-IOV channel */
 
+int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn);
 #define OSAL_VF_FLR_UPDATE(hwfn) nothing
 #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0
 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol)	(0)
-#define OSAL_PF_VF_MSG(hwfn, vfid) 0
+#define OSAL_PF_VF_MSG(hwfn, vfid) \
+	osal_pf_vf_msg(hwfn)
 #define OSAL_PF_VF_MALICIOUS(hwfn, vfid) nothing
 #define OSAL_IOV_CHK_UCAST(hwfn, vfid, params) 0
 #define OSAL_IOV_POST_START_VPORT(hwfn, vf, vport_id, opaque_fid) nothing
diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h
index 750e99a8f..6c8e6d407 100644
--- a/drivers/net/qede/base/ecore.h
+++ b/drivers/net/qede/base/ecore.h
@@ -714,6 +714,10 @@ struct ecore_hwfn {
 
 	/* @DPDK */
 	struct ecore_ptt		*p_arfs_ptt;
+
+	/* DPDK specific, not the part of vanilla ecore */
+	osal_spinlock_t spq_lock;
+	u32 iov_task_flags;
 };
 
 enum ecore_mf_mode {
diff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h
index 545001812..bd7c5703f 100644
--- a/drivers/net/qede/base/ecore_iov_api.h
+++ b/drivers/net/qede/base/ecore_iov_api.h
@@ -14,6 +14,9 @@
 #define ECORE_ETH_VF_NUM_VLAN_FILTERS 2
 #define ECORE_VF_ARRAY_LENGTH (3)
 
+#define ECORE_VF_ARRAY_GET_VFID(arr, vfid)	\
+	(((arr)[(vfid) / 64]) & (1ULL << ((vfid) % 64)))
+
 #define IS_VF(p_dev)		((p_dev)->b_is_vf)
 #define IS_PF(p_dev)		(!((p_dev)->b_is_vf))
 #ifdef CONFIG_ECORE_SRIOV
diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index 0235c0798..210a3b10f 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -281,7 +281,9 @@ qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 
 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 {
+	OSAL_SPIN_LOCK(&p_hwfn->spq_lock);
 	ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
+	OSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);
 }
 
 static void
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index c37e8ebe0..0afacc064 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -221,7 +221,9 @@ static void qed_stop_iov_task(struct ecore_dev *edev)
 
 	for_each_hwfn(edev, i) {
 		p_hwfn = &edev->hwfns[i];
-		if (!IS_PF(edev))
+		if (IS_PF(edev))
+			rte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn);
+		else
 			rte_eal_alarm_cancel(qede_vf_task, p_hwfn);
 	}
 }
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
index ba4384e90..6d620dde8 100644
--- a/drivers/net/qede/qede_sriov.c
+++ b/drivers/net/qede/qede_sriov.c
@@ -4,6 +4,14 @@
  * www.marvell.com
  */
 
+#include <rte_alarm.h>
+
+#include "base/bcm_osal.h"
+#include "base/ecore.h"
+#include "base/ecore_sriov.h"
+#include "base/ecore_mcp.h"
+#include "base/ecore_vf.h"
+
 #include "qede_sriov.h"
 
 static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn,
@@ -83,3 +91,56 @@ void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param)
 	if (num_vfs_param)
 		qed_sriov_enable(edev, num_vfs_param);
 }
+
+static void qed_handle_vf_msg(struct ecore_hwfn *hwfn)
+{
+	u64 events[ECORE_VF_ARRAY_LENGTH];
+	struct ecore_ptt *ptt;
+	int i;
+
+	ptt = ecore_ptt_acquire(hwfn);
+	if (!ptt) {
+		DP_NOTICE(hwfn, true, "PTT acquire failed\n");
+		qed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG);
+		return;
+	}
+
+	ecore_iov_pf_get_pending_events(hwfn, events);
+
+	ecore_for_each_vf(hwfn, i) {
+		/* Skip VFs with no pending messages */
+		if (!ECORE_VF_ARRAY_GET_VFID(events, i))
+			continue;
+
+		DP_VERBOSE(hwfn, ECORE_MSG_IOV,
+			   "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
+			   i, hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
+
+		/* Copy VF's message to PF's request buffer for that VF */
+		if (ecore_iov_copy_vf_msg(hwfn, ptt, i))
+			continue;
+
+		ecore_iov_process_mbx_req(hwfn, ptt, i);
+	}
+
+	ecore_ptt_release(hwfn, ptt);
+}
+
+void qed_iov_pf_task(void *arg)
+{
+	struct ecore_hwfn *p_hwfn = arg;
+
+	if (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) {
+		OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags);
+		qed_handle_vf_msg(p_hwfn);
+	}
+}
+
+int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)
+{
+	DP_VERBOSE(p_hwfn, ECORE_MSG_IOV, "Scheduling iov task [Flag: %d]\n",
+		   flag);
+
+	OSAL_SET_BIT(flag, &p_hwfn->iov_task_flags);
+	return rte_eal_alarm_set(1, qed_iov_pf_task, p_hwfn);
+}
diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h
index 6c85b1dd5..8b7fa7daa 100644
--- a/drivers/net/qede/qede_sriov.h
+++ b/drivers/net/qede/qede_sriov.h
@@ -4,6 +4,18 @@
  * www.marvell.com
  */
 
-#include "qede_ethdev.h"
-
 void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param);
+
+enum qed_iov_wq_flag {
+	QED_IOV_WQ_MSG_FLAG,
+	QED_IOV_WQ_SET_UNICAST_FILTER_FLAG,
+	QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
+	QED_IOV_WQ_STOP_WQ_FLAG,
+	QED_IOV_WQ_FLR_FLAG,
+	QED_IOV_WQ_TRUST_FLAG,
+	QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG,
+	QED_IOV_WQ_DB_REC_HANDLER,
+};
+
+int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag);
+void qed_iov_pf_task(void *arg);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 5/6] net/qede: initialize VF MAC and link
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
                   ` (3 preceding siblings ...)
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 4/6] net/qede: add infrastructure support for VF load Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 6/6] net/qede: add VF FLR support Manish Chopra
  5 siblings, 0 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

This patch configures VFs with random mac if no MAC is
provided by the PF/bulletin. This also adds required bulletin
APIs by PF-PMD driver to communicate LINK properties/changes to
the VFs through bulletin update mechanism.

With these changes, VF-PMD instance is able to run
fastpath over PF-PMD driver instance.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 drivers/net/qede/qede_ethdev.c | 34 ++++++++++++++++++++-
 drivers/net/qede/qede_main.c   |  7 ++++-
 drivers/net/qede/qede_sriov.c  | 55 ++++++++++++++++++++++++++++++++++
 drivers/net/qede/qede_sriov.h  |  1 +
 4 files changed, 95 insertions(+), 2 deletions(-)

diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index 210a3b10f..e785f3fb0 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -2479,6 +2479,24 @@ static void qede_update_pf_params(struct ecore_dev *edev)
 	qed_ops->common->update_pf_params(edev, &pf_params);
 }
 
+static void qede_generate_random_mac_addr(struct rte_ether_addr *mac_addr)
+{
+	uint64_t random;
+
+	/* Set Organizationally Unique Identifier (OUI) prefix. */
+	mac_addr->addr_bytes[0] = 0x00;
+	mac_addr->addr_bytes[1] = 0x09;
+	mac_addr->addr_bytes[2] = 0xC0;
+
+	/* Force indication of locally assigned MAC address. */
+	mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
+
+	/* Generate the last 3 bytes of the MAC address with a random number. */
+	random = rte_rand();
+
+	memcpy(&mac_addr->addr_bytes[3], &random, 3);
+}
+
 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
 {
 	struct rte_pci_device *pci_dev;
@@ -2491,7 +2509,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
 	uint8_t bulletin_change;
 	uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
 	uint8_t is_mac_forced;
-	bool is_mac_exist;
+	bool is_mac_exist = false;
 	/* Fix up ecore debug level */
 	uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
 	uint8_t dp_level = ECORE_LEVEL_VERBOSE;
@@ -2669,6 +2687,20 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
 				DP_ERR(edev, "No VF macaddr assigned\n");
 			}
 		}
+
+		/* If MAC doesn't exist from PF, generate random one */
+		if (!is_mac_exist) {
+			struct rte_ether_addr *mac_addr;
+
+			mac_addr = (struct rte_ether_addr *)&vf_mac;
+			qede_generate_random_mac_addr(mac_addr);
+
+			rte_ether_addr_copy(mac_addr,
+					    &eth_dev->data->mac_addrs[0]);
+
+			rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
+					    &adapter->primary_mac);
+		}
 	}
 
 	eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index 0afacc064..805a95e3c 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -651,10 +651,15 @@ void qed_link_update(struct ecore_hwfn *hwfn)
 	struct ecore_dev *edev = hwfn->p_dev;
 	struct qede_dev *qdev = (struct qede_dev *)edev;
 	struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
+	int rc;
+
+	rc = qede_link_update(dev, 0);
+	qed_inform_vf_link_state(hwfn);
 
-	if (!qede_link_update(dev, 0))
+	if (!rc) {
 		_rte_eth_dev_callback_process(dev,
 					      RTE_ETH_EVENT_INTR_LSC, NULL);
+	}
 }
 
 static int qed_drain(struct ecore_dev *edev)
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
index 6d620dde8..93f7a2a55 100644
--- a/drivers/net/qede/qede_sriov.c
+++ b/drivers/net/qede/qede_sriov.c
@@ -126,6 +126,28 @@ static void qed_handle_vf_msg(struct ecore_hwfn *hwfn)
 	ecore_ptt_release(hwfn, ptt);
 }
 
+static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn)
+{
+	struct ecore_ptt *ptt;
+	int i;
+
+	ptt = ecore_ptt_acquire(hwfn);
+	if (!ptt) {
+		DP_NOTICE(hwfn, true, "PTT acquire failed\n");
+		qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
+		return;
+	}
+
+	/* TODO - at the moment update bulletin board of all VFs.
+	 * if this proves to costly, we can mark VFs that need their
+	 * bulletins updated.
+	 */
+	ecore_for_each_vf(hwfn, i)
+		ecore_iov_post_vf_bulletin(hwfn, i, ptt);
+
+	ecore_ptt_release(hwfn, ptt);
+}
+
 void qed_iov_pf_task(void *arg)
 {
 	struct ecore_hwfn *p_hwfn = arg;
@@ -134,6 +156,13 @@ void qed_iov_pf_task(void *arg)
 		OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags);
 		qed_handle_vf_msg(p_hwfn);
 	}
+
+	if (OSAL_GET_BIT(QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
+			 &p_hwfn->iov_task_flags)) {
+		OSAL_CLEAR_BIT(QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
+			       &p_hwfn->iov_task_flags);
+		qed_handle_bulletin_post(p_hwfn);
+	}
 }
 
 int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)
@@ -144,3 +173,29 @@ int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)
 	OSAL_SET_BIT(flag, &p_hwfn->iov_task_flags);
 	return rte_eal_alarm_set(1, qed_iov_pf_task, p_hwfn);
 }
+
+void qed_inform_vf_link_state(struct ecore_hwfn *hwfn)
+{
+	struct ecore_hwfn *lead_hwfn = ECORE_LEADING_HWFN(hwfn->p_dev);
+	struct ecore_mcp_link_capabilities caps;
+	struct ecore_mcp_link_params params;
+	struct ecore_mcp_link_state link;
+	int i;
+
+	if (!hwfn->pf_iov_info)
+		return;
+
+	rte_memcpy(&params, ecore_mcp_get_link_params(lead_hwfn),
+		   sizeof(params));
+	rte_memcpy(&link, ecore_mcp_get_link_state(lead_hwfn), sizeof(link));
+	rte_memcpy(&caps, ecore_mcp_get_link_capabilities(lead_hwfn),
+		   sizeof(caps));
+
+	/* Update bulletin of all future possible VFs with link configuration */
+	for (i = 0; i < hwfn->p_dev->p_iov_info->total_vfs; i++) {
+		ecore_iov_set_link(hwfn, i,
+				   &params, &link, &caps);
+	}
+
+	qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
+}
diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h
index 8b7fa7daa..e58ecc2a5 100644
--- a/drivers/net/qede/qede_sriov.h
+++ b/drivers/net/qede/qede_sriov.h
@@ -17,5 +17,6 @@ enum qed_iov_wq_flag {
 	QED_IOV_WQ_DB_REC_HANDLER,
 };
 
+void qed_inform_vf_link_state(struct ecore_hwfn *hwfn);
 int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag);
 void qed_iov_pf_task(void *arg);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-dev] [PATCH v5 6/6] net/qede: add VF FLR support
  2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
                   ` (4 preceding siblings ...)
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 5/6] net/qede: initialize VF MAC and link Manish Chopra
@ 2020-07-30 14:42 ` Manish Chopra
  5 siblings, 0 replies; 8+ messages in thread
From: Manish Chopra @ 2020-07-30 14:42 UTC (permalink / raw)
  To: jerinjacobk, jerinj, ferruh.yigit, grive
  Cc: dev, irusskikh, rmody, GR-Everest-DPDK-Dev, rosen.xu,
	tianfei.zhang, heinrich.kuhn, qiming.yang, qi.z.zhang

This patch adds required bit to handle VF FLR
indication from Management FW (MFW) of the device

With that VFs were able to load in VM (VF attached as PCI
passthrough to the guest VM) followed by FLR successfully

Updated the docs/guides with the feature support

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 doc/guides/nics/features/qede.ini |  1 +
 doc/guides/nics/qede.rst          |  7 +------
 drivers/net/qede/base/bcm_osal.c  |  5 +++++
 drivers/net/qede/base/bcm_osal.h  |  4 +++-
 drivers/net/qede/qede_sriov.c     | 18 ++++++++++++++++++
 5 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/doc/guides/nics/features/qede.ini b/doc/guides/nics/features/qede.ini
index f8716523e..46fba8e6c 100644
--- a/doc/guides/nics/features/qede.ini
+++ b/doc/guides/nics/features/qede.ini
@@ -32,6 +32,7 @@ Basic stats          = Y
 Extended stats       = Y
 Stats per queue      = Y
 Registers dump       = Y
+SR-IOV               = Y
 Multiprocess aware   = Y
 Linux UIO            = Y
 Linux VFIO           = Y
diff --git a/doc/guides/nics/qede.rst b/doc/guides/nics/qede.rst
index 5b2f86895..e874915c2 100644
--- a/doc/guides/nics/qede.rst
+++ b/doc/guides/nics/qede.rst
@@ -34,18 +34,13 @@ Supported Features
 - VLAN offload - Filtering and stripping
 - N-tuple filter and flow director (limited support)
 - NPAR (NIC Partitioning)
-- SR-IOV VF
+- SR-IOV PF and VF
 - GRE Tunneling offload
 - GENEVE Tunneling offload
 - VXLAN Tunneling offload
 - MPLSoUDP Tx Tunneling offload
 - Generic flow API
 
-Non-supported Features
-----------------------
-
-- SR-IOV PF
-
 Co-existence considerations
 ---------------------------
 
diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c
index ef47339df..44a8692f5 100644
--- a/drivers/net/qede/base/bcm_osal.c
+++ b/drivers/net/qede/base/bcm_osal.c
@@ -29,6 +29,11 @@ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn)
 	return rc;
 }
 
+void osal_vf_flr_update(struct ecore_hwfn *p_hwfn)
+{
+	qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+}
+
 void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie)
 {
 	struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index cf58db8bf..c137004ba 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -349,7 +349,9 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length);
 /* SR-IOV channel */
 
 int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn);
-#define OSAL_VF_FLR_UPDATE(hwfn) nothing
+void osal_vf_flr_update(struct ecore_hwfn *p_hwfn);
+#define OSAL_VF_FLR_UPDATE(hwfn) \
+	osal_vf_flr_update(hwfn)
 #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0
 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol)	(0)
 #define OSAL_PF_VF_MSG(hwfn, vfid) \
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
index 93f7a2a55..0b99a8d6f 100644
--- a/drivers/net/qede/qede_sriov.c
+++ b/drivers/net/qede/qede_sriov.c
@@ -151,6 +151,7 @@ static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn)
 void qed_iov_pf_task(void *arg)
 {
 	struct ecore_hwfn *p_hwfn = arg;
+	int rc;
 
 	if (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) {
 		OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags);
@@ -163,6 +164,23 @@ void qed_iov_pf_task(void *arg)
 			       &p_hwfn->iov_task_flags);
 		qed_handle_bulletin_post(p_hwfn);
 	}
+
+	if (OSAL_GET_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags)) {
+		struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
+
+		OSAL_CLEAR_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags);
+
+		if (!p_ptt) {
+			qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+			return;
+		}
+
+		rc = ecore_iov_vf_flr_cleanup(p_hwfn, p_ptt);
+		if (rc)
+			qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+
+		ecore_ptt_release(p_hwfn, p_ptt);
+	}
 }
 
 int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap
  2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap Manish Chopra
@ 2020-08-07 17:46   ` Nithin Dabilpuram
  0 siblings, 0 replies; 8+ messages in thread
From: Nithin Dabilpuram @ 2020-08-07 17:46 UTC (permalink / raw)
  To: Manish Chopra
  Cc: jerinjacobk, jerinj, ferruh.yigit, grive, dev, irusskikh, rmody,
	GR-Everest-DPDK-Dev, rosen.xu, tianfei.zhang, heinrich.kuhn,
	qiming.yang, qi.z.zhang

On Thu, Jul 30, 2020 at 07:42:16AM -0700, Manish Chopra wrote:
> By adding generic API, this patch removes individual
> functions/defines implemented by drivers to find extended
> PCI capabilities.
> 
> Signed-off-by: Manish Chopra <manishc@marvell.com>
> Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
> ---
>  drivers/bus/pci/pci_common.c               | 43 ++++++++++++++++++
>  drivers/bus/pci/rte_bus_pci.h              | 20 +++++++++
>  drivers/bus/pci/rte_bus_pci_version.map    |  6 +++
>  drivers/net/ice/ice_ethdev.c               | 51 +---------------------
>  drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 +-------------------
>  drivers/raw/ifpga/ifpga_rawdev.c           | 17 +++-----
>  lib/librte_pci/rte_pci.h                   | 16 +++++++
>  7 files changed, 95 insertions(+), 106 deletions(-)
> 
> diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
> index a8e5fd52c..98c1f8155 100644
> --- a/drivers/bus/pci/pci_common.c
> +++ b/drivers/bus/pci/pci_common.c
> @@ -665,6 +665,49 @@ rte_pci_get_iommu_class(void)
>  	return iova_mode;
>  }
>  
> +off_t
> +rte_pci_find_next_ext_capability(struct rte_pci_device *dev, uint32_t cap)
> +{

Shouldn't it be named rte_pci_find_ext_capability() as it doesn't take start
position from where to search ?

> +	off_t offset = RTE_PCI_CFG_SPACE_SIZE;
> +	uint32_t header;
> +	int ttl;
> +
> +	/* minimum 8 bytes per capability */
> +	ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
> +
> +	if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
> +		RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
> +		return -1;
> +	}
> +
> +	/*
> +	 * If we have no capabilities, this is indicated by cap ID,
> +	 * cap version and next pointer all being 0.
> +	 */
> +	if (header == 0)
> +		return 0;
> +
> +	while (ttl != 0) {
> +		if (RTE_PCI_EXT_CAP_ID(header) == cap)
> +			return offset;
> +
> +		offset = RTE_PCI_EXT_CAP_NEXT(header);
> +
> +		if (offset < RTE_PCI_CFG_SPACE_SIZE)
> +			break;
> +
> +		if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
> +			RTE_LOG(ERR, EAL,
> +				"error in reading extended capabilities\n");
> +			return -1;
> +		}
> +
> +		ttl--;
> +	}
> +
> +	return 0;
> +}
> +
>  struct rte_pci_bus rte_pci_bus = {
>  	.bus = {
>  		.scan = rte_pci_scan,
> diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
> index 29bea6d70..f11af3762 100644
> --- a/drivers/bus/pci/rte_bus_pci.h
> +++ b/drivers/bus/pci/rte_bus_pci.h
> @@ -224,6 +224,26 @@ void rte_pci_unmap_device(struct rte_pci_device *dev);
>   */
>  void rte_pci_dump(FILE *f);
>  
> +/**
> + * Find device's extended PCI capability.
> + *
> + *  @param dev
> + *    A pointer to rte_pci_device structure.
> + *
> + *  @param cap
> + *    Extended capability to be found, which can be any from
> + *    RTE_PCI_EXT_CAP_ID_*, defined in librte_pci.
> + *
> + *  @return
> + *  > 0: The offset of the next matching extended capability structure
> + *       within the device's PCI configuration space.
> + *  < 0: An error in PCI config space read.
> + *  = 0: Device does not support it.
> + */
> +__rte_experimental
> +off_t rte_pci_find_next_ext_capability(struct rte_pci_device *dev,
> +				       uint32_t cap);
> +
>  /**
>   * Register a PCI driver.
>   *
> diff --git a/drivers/bus/pci/rte_bus_pci_version.map b/drivers/bus/pci/rte_bus_pci_version.map
> index 012d817e1..b5322660d 100644
> --- a/drivers/bus/pci/rte_bus_pci_version.map
> +++ b/drivers/bus/pci/rte_bus_pci_version.map
> @@ -16,3 +16,9 @@ DPDK_20.0 {
>  
>  	local: *;
>  };
> +
> +EXPERIMENTAL {
> +	global:
> +
> +	rte_pci_find_next_ext_capability;
> +};
> diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
> index 7dd3fcd27..6c8cbea5c 100644
> --- a/drivers/net/ice/ice_ethdev.c
> +++ b/drivers/net/ice/ice_ethdev.c
> @@ -1730,53 +1730,6 @@ ice_pf_setup(struct ice_pf *pf)
>  	return 0;
>  }
>  
> -/* PCIe configuration space setting */
> -#define PCI_CFG_SPACE_SIZE          256
> -#define PCI_CFG_SPACE_EXP_SIZE      4096
> -#define PCI_EXT_CAP_ID(header)      (int)((header) & 0x0000ffff)
> -#define PCI_EXT_CAP_NEXT(header)    (((header) >> 20) & 0xffc)
> -#define PCI_EXT_CAP_ID_DSN          0x03
> -
> -static int
> -ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
> -{
> -	uint32_t header;
> -	int ttl;
> -	int pos = PCI_CFG_SPACE_SIZE;
> -
> -	/* minimum 8 bytes per capability */
> -	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
> -
> -	if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
> -		PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
> -		return -1;
> -	}
> -
> -	/*
> -	 * If we have no capabilities, this is indicated by cap ID,
> -	 * cap version and next pointer all being 0.
> -	 */
> -	if (header == 0)
> -		return 0;
> -
> -	while (ttl-- > 0) {
> -		if (PCI_EXT_CAP_ID(header) == cap)
> -			return pos;
> -
> -		pos = PCI_EXT_CAP_NEXT(header);
> -
> -		if (pos < PCI_CFG_SPACE_SIZE)
> -			break;
> -
> -		if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
> -			PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
> -			return -1;
> -		}
> -	}
> -
> -	return 0;
> -}
> -
>  /*
>   * Extract device serial number from PCIe Configuration Space and
>   * determine the pkg file path according to the DSN.
> @@ -1784,12 +1737,12 @@ ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
>  static int
>  ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
>  {
> -	int pos;
> +	off_t pos;
>  	char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
>  	uint32_t dsn_low, dsn_high;
>  	memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
>  
> -	pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
> +	pos = rte_pci_find_next_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
>  
>  	if (pos) {
>  		rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
> diff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
> index 0b9db974e..dbab4f8cb 100644
> --- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
> +++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
> @@ -746,59 +746,15 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp)
>  	return 0;
>  }
>  
> -#define PCI_CFG_SPACE_SIZE	256
> -#define PCI_CFG_SPACE_EXP_SIZE	4096
> -#define PCI_EXT_CAP_ID(header)		(int)(header & 0x0000ffff)
> -#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
> -#define PCI_EXT_CAP_ID_DSN	0x03
> -static int
> -nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
> -{
> -	uint32_t header;
> -	int ttl;
> -	int pos = PCI_CFG_SPACE_SIZE;
> -
> -	/* minimum 8 bytes per capability */
> -	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
> -
> -	if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
> -		printf("nfp error reading extended capabilities\n");
> -		return -1;
> -	}
> -
> -	/*
> -	 * If we have no capabilities, this is indicated by cap ID,
> -	 * cap version and next pointer all being 0.
> -	 */
> -	if (header == 0)
> -		return 0;
> -
> -	while (ttl-- > 0) {
> -		if (PCI_EXT_CAP_ID(header) == cap)
> -			return pos;
> -
> -		pos = PCI_EXT_CAP_NEXT(header);
> -		if (pos < PCI_CFG_SPACE_SIZE)
> -			break;
> -
> -		if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
> -			printf("nfp error reading extended capabilities\n");
> -			return -1;
> -		}
> -	}
> -
> -	return 0;
> -}
> -
>  static int
>  nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp)
>  {
>  	uint16_t tmp;
>  	uint8_t serial[6];
>  	int serial_len = 6;
> -	int pos;
> +	off_t pos;
>  
> -	pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
> +	pos = rte_pci_find_next_ext_capability(dev, RTE_PCI_EXT_CAP_ID_DSN);
>  	if (pos <= 0) {
>  		printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n");
>  		return -1;
> diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
> index cc25c662b..07aef4f6e 100644
> --- a/drivers/raw/ifpga/ifpga_rawdev.c
> +++ b/drivers/raw/ifpga/ifpga_rawdev.c
> @@ -41,12 +41,6 @@
>  #include "ifpga_rawdev.h"
>  #include "ipn3ke_rawdev_api.h"
>  
> -#define RTE_PCI_EXT_CAP_ID_ERR           0x01	/* Advanced Error Reporting */
> -#define RTE_PCI_CFG_SPACE_SIZE           256
> -#define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
> -#define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
> -#define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
> -
>  #define PCI_VENDOR_ID_INTEL          0x8086
>  /* PCI Device ID */
>  #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
> @@ -86,8 +80,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
>  static int set_surprise_link_check_aer(
>  		struct ifpga_rawdev *ifpga_rdev, int force_disable);
>  static int ifpga_pci_find_next_ext_capability(unsigned int fd,
> -		int start, int cap);
> -static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
> +					      int start, uint32_t cap);
> +static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
>  
>  struct ifpga_rawdev *
>  ifpga_rawdev_get(const struct rte_rawdev *rawdev)
> @@ -144,8 +138,8 @@ ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
>  	return dev;
>  }
>  
> -static int ifpga_pci_find_next_ext_capability(unsigned int fd,
> -int start, int cap)
> +static int
> +ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
>  {
>  	uint32_t header;
>  	int ttl;
> @@ -183,7 +177,8 @@ int start, int cap)
>  	return 0;
>  }
>  
> -static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
> +static int
> +ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
>  {
>  	return ifpga_pci_find_next_ext_capability(fd, 0, cap);
>  }
> diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h
> index a03235da1..fec51e15a 100644
> --- a/lib/librte_pci/rte_pci.h
> +++ b/lib/librte_pci/rte_pci.h
> @@ -22,6 +22,22 @@ extern "C" {
>  #include <inttypes.h>
>  #include <sys/types.h>
>  
> +
> +/*
> + * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
> + * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
> + * configuration space.
> + */
> +#define RTE_PCI_CFG_SPACE_SIZE		256
> +#define RTE_PCI_CFG_SPACE_EXP_SIZE	4096
> +
> +/* Extended Capabilities (PCI-X 2.0 and Express) */
> +#define RTE_PCI_EXT_CAP_ID(header)	(header & 0x0000ffff)
> +#define RTE_PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
> +
> +#define RTE_PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
> +#define RTE_PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
> +
>  /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
>  #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
>  #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, back to index

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-30 14:42 [dpdk-dev] [PATCH v5 0/6] qede: SR-IOV PF driver support Manish Chopra
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 1/6] drivers: add generic API to find PCI extended cap Manish Chopra
2020-08-07 17:46   ` Nithin Dabilpuram
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 2/6] net/qede: define PCI config space specific osals Manish Chopra
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 3/6] net/qede: configure VFs on hardware Manish Chopra
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 4/6] net/qede: add infrastructure support for VF load Manish Chopra
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 5/6] net/qede: initialize VF MAC and link Manish Chopra
2020-07-30 14:42 ` [dpdk-dev] [PATCH v5 6/6] net/qede: add VF FLR support Manish Chopra

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