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* [PATCH 0/3] enic PMD patches
@ 2022-01-14  3:10 John Daley
  2022-01-14  3:10 ` [PATCH 1/3] net/enic: add support for eCPRI matching John Daley
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: John Daley @ 2022-01-14  3:10 UTC (permalink / raw)
  To: ferruh.yigit, arybchenko; +Cc: dev, John Daley

Here are a couple patches to the enic PMD that should apply on top of
the patch:
	'net/enic: support GENEVE flow item' by Hyong Youb Kim.

John Daley (3):
  net/enic: add support for eCPRI matching
  net/enic: update VIC firmware API
  net/enic: support max descriptors allowed by adapter

 doc/guides/rel_notes/release_22_03.rst |  1 +
 drivers/net/enic/base/cq_enet_desc.h   |  6 ++-
 drivers/net/enic/base/vnic_enet.h      | 22 +++++++++
 drivers/net/enic/enic_fm_flow.c        | 65 ++++++++++++++++++++++++++
 drivers/net/enic/enic_res.c            | 20 ++++++--
 drivers/net/enic/enic_res.h            |  6 ++-
 drivers/net/enic/enic_rxtx.c           | 33 +++++++++----
 7 files changed, 136 insertions(+), 17 deletions(-)

-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/3] net/enic: add support for eCPRI matching
  2022-01-14  3:10 [PATCH 0/3] enic PMD patches John Daley
@ 2022-01-14  3:10 ` John Daley
  2022-01-14  3:10 ` [PATCH 2/3] net/enic: update VIC firmware API John Daley
  2022-01-14  3:10 ` [PATCH 3/3] net/enic: support max descriptors allowed by adapter John Daley
  2 siblings, 0 replies; 4+ messages in thread
From: John Daley @ 2022-01-14  3:10 UTC (permalink / raw)
  To: ferruh.yigit, arybchenko; +Cc: dev, John Daley, Hyong Youb Kim

eCPRI message can be over Ethernet layer (.1Q supported also) or over
UDP layer. Message header formats are the same in these two variants.

Only up though the first packet header in the PDU can be matched.
RSS on the eCPRI header fields is not supported.

Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>
---
 doc/guides/rel_notes/release_22_03.rst |  1 +
 drivers/net/enic/enic_fm_flow.c        | 65 ++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
index b38dc54e62..52d1e32cf6 100644
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -58,6 +58,7 @@ New Features
 * **Updated Cisco enic driver.**
 
   * Added rte_flow support for matching GENEVE packets.
+  * Added rte_flow support for matching eCPRI packets.
 
 Removed Items
 -------------
diff --git a/drivers/net/enic/enic_fm_flow.c b/drivers/net/enic/enic_fm_flow.c
index 752ffeb5c5..589c9253e1 100644
--- a/drivers/net/enic/enic_fm_flow.c
+++ b/drivers/net/enic/enic_fm_flow.c
@@ -237,6 +237,7 @@ static enic_copy_item_fn enic_fm_copy_item_vxlan;
 static enic_copy_item_fn enic_fm_copy_item_gtp;
 static enic_copy_item_fn enic_fm_copy_item_geneve;
 static enic_copy_item_fn enic_fm_copy_item_geneve_opt;
+static enic_copy_item_fn enic_fm_copy_item_ecpri;
 
 /* Ingress actions */
 static const enum rte_flow_action_type enic_fm_supported_ig_actions[] = {
@@ -392,6 +393,15 @@ static const struct enic_fm_items enic_fm_items[] = {
 			       RTE_FLOW_ITEM_TYPE_END,
 		},
 	},
+	[RTE_FLOW_ITEM_TYPE_ECPRI] = {
+		.copy_item = enic_fm_copy_item_ecpri,
+		.valid_start_item = 1,
+		.prev_items = (const enum rte_flow_item_type[]) {
+			       RTE_FLOW_ITEM_TYPE_ETH,
+			       RTE_FLOW_ITEM_TYPE_UDP,
+			       RTE_FLOW_ITEM_TYPE_END,
+		},
+	},
 };
 
 static int
@@ -877,6 +887,61 @@ enic_fm_copy_item_geneve_opt(struct copy_item_args *arg)
 	return 0;
 }
 
+/* Match eCPRI combined message header */
+static int
+enic_fm_copy_item_ecpri(struct copy_item_args *arg)
+{
+	const struct rte_flow_item *item = arg->item;
+	const struct rte_flow_item_ecpri *spec = item->spec;
+	const struct rte_flow_item_ecpri *mask = item->mask;
+	struct fm_tcam_match_entry *entry = arg->fm_tcam_entry;
+	struct fm_header_set *fm_data, *fm_mask;
+	uint8_t *fm_data_to, *fm_mask_to;
+
+	ENICPMD_FUNC_TRACE();
+
+	/* Tunneling not supported- only matching on inner eCPRI fields. */
+	if (arg->header_level > 0)
+		return -EINVAL;
+
+	/* Need both spec and mask */
+	if (!spec || !mask)
+		return -EINVAL;
+
+	fm_data = &entry->ftm_data.fk_hdrset[0];
+	fm_mask = &entry->ftm_mask.fk_hdrset[0];
+
+	/* eCPRI can only follow L2/VLAN layer if ethernet type is 0xAEFE. */
+	if (!(fm_data->fk_metadata & FKM_UDP) &&
+	    (fm_mask->l2.eth.fk_ethtype != UINT16_MAX ||
+	    rte_cpu_to_be_16(fm_data->l2.eth.fk_ethtype) !=
+	    RTE_ETHER_TYPE_ECPRI))
+		return -EINVAL;
+
+	if (fm_data->fk_metadata & FKM_UDP) {
+		/* eCPRI on UDP */
+		fm_data->fk_header_select |= FKH_L4RAW;
+		fm_mask->fk_header_select |= FKH_L4RAW;
+		fm_data_to = &fm_data->l4.rawdata[sizeof(fm_data->l4.udp)];
+		fm_mask_to = &fm_mask->l4.rawdata[sizeof(fm_data->l4.udp)];
+	} else {
+		/* eCPRI directly after Etherent header */
+		fm_data->fk_header_select |= FKH_L3RAW;
+		fm_mask->fk_header_select |= FKH_L3RAW;
+		fm_data_to = &fm_data->l3.rawdata[0];
+		fm_mask_to = &fm_mask->l3.rawdata[0];
+	}
+
+	/*
+	 * Use the raw L3 or L4 buffer to match eCPRI since fm_header_set does
+	 * not have eCPRI header. Only 1st message header of PDU can be matched.
+	 * "C" * bit ignored.
+	 */
+	memcpy(fm_data_to, spec, sizeof(*spec));
+	memcpy(fm_mask_to, mask, sizeof(*mask));
+	return 0;
+}
+
 /*
  * Currently, raw pattern match is very limited. It is intended for matching
  * UDP tunnel header (e.g. vxlan or geneve).
-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/3] net/enic: update VIC firmware API
  2022-01-14  3:10 [PATCH 0/3] enic PMD patches John Daley
  2022-01-14  3:10 ` [PATCH 1/3] net/enic: add support for eCPRI matching John Daley
@ 2022-01-14  3:10 ` John Daley
  2022-01-14  3:10 ` [PATCH 3/3] net/enic: support max descriptors allowed by adapter John Daley
  2 siblings, 0 replies; 4+ messages in thread
From: John Daley @ 2022-01-14  3:10 UTC (permalink / raw)
  To: ferruh.yigit, arybchenko; +Cc: dev, John Daley, Hyong Youb Kim

Update the configuration structure used between the adapter and
driver. The structure is compatible with all Cisco VIC adapters.

Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>
---
 drivers/net/enic/base/vnic_enet.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/net/enic/base/vnic_enet.h b/drivers/net/enic/base/vnic_enet.h
index 2a97a33044..66261d9127 100644
--- a/drivers/net/enic/base/vnic_enet.h
+++ b/drivers/net/enic/base/vnic_enet.h
@@ -31,6 +31,28 @@ struct vnic_enet_config {
 	uint32_t rdma_mr_id;
 	uint32_t rdma_mr_count;
 	uint32_t max_pkt_size;
+	uint16_t vf_subvnic_count;
+	uint16_t mq_subvnic_count;
+	uint32_t mq_flags;
+
+	/* the following 3 fields are per-MQ-vnic counts */
+	uint32_t mq_rdma_mr_count;
+	uint16_t mq_rdma_qp_count;
+	uint16_t mq_rdma_resgrp;
+
+	uint16_t rdma_max_sq_ring_sz;
+	uint16_t rdma_max_rq_ring_sz;
+	uint32_t rdma_max_cq_ring_sz;
+	uint16_t rdma_max_wr_sge;
+	uint16_t rdma_max_mr_sge;
+	uint8_t rdma_max_rd_per_qp;
+	uint8_t unused;			/* available */
+	uint16_t mq_rdma_engine_count;
+	uint32_t intr_coal_tick_ns;	/* coalescing timer tick in nsec */
+	uint32_t max_rq_ring;		/* MAX RQ ring size */
+	uint32_t max_wq_ring;		/* MAX WQ ring size */
+	uint32_t max_cq_ring;		/* MAX CQ ring size */
+	uint32_t rdma_rsvd_lkey;	/* Reserved (privileged) LKey */
 };
 
 #define VENETF_TSO		0x1	/* TSO enabled */
-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 3/3] net/enic: support max descriptors allowed by adapter
  2022-01-14  3:10 [PATCH 0/3] enic PMD patches John Daley
  2022-01-14  3:10 ` [PATCH 1/3] net/enic: add support for eCPRI matching John Daley
  2022-01-14  3:10 ` [PATCH 2/3] net/enic: update VIC firmware API John Daley
@ 2022-01-14  3:10 ` John Daley
  2 siblings, 0 replies; 4+ messages in thread
From: John Daley @ 2022-01-14  3:10 UTC (permalink / raw)
  To: ferruh.yigit, arybchenko; +Cc: dev, John Daley, Hyong Youb Kim

Newer VIC adapters have the max number of supported RX and TX
descriptors in their configuration. Use these values as the
maximums.

Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>
---
 drivers/net/enic/base/cq_enet_desc.h |  6 ++++-
 drivers/net/enic/enic_res.c          | 20 +++++++++++++----
 drivers/net/enic/enic_res.h          |  6 +++--
 drivers/net/enic/enic_rxtx.c         | 33 +++++++++++++++++++---------
 4 files changed, 48 insertions(+), 17 deletions(-)

diff --git a/drivers/net/enic/base/cq_enet_desc.h b/drivers/net/enic/base/cq_enet_desc.h
index a34a4f5400..02db85b9a0 100644
--- a/drivers/net/enic/base/cq_enet_desc.h
+++ b/drivers/net/enic/base/cq_enet_desc.h
@@ -67,7 +67,8 @@ struct cq_enet_rq_desc_64 {
 	uint16_t vlan;
 	uint16_t checksum_fcoe;
 	uint8_t flags;
-	uint8_t unused[48];
+	uint8_t fetch_idx_flags;
+	uint8_t unused[47];
 	uint8_t type_color;
 };
 
@@ -92,6 +93,9 @@ struct cq_enet_rq_desc_64 {
 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS          14
 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \
 	((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)
+#define CQ_ENET_RQ_DESC_FETCH_IDX_BITS              2
+#define CQ_ENET_RQ_DESC_FETCH_IDX_MASK \
+	((1 << CQ_ENET_RQ_DESC_FETCH_IDX_BITS) - 1)
 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED             (0x1 << 14)
 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED         (0x1 << 15)
 
diff --git a/drivers/net/enic/enic_res.c b/drivers/net/enic/enic_res.c
index 9cfb857939..caf773bab2 100644
--- a/drivers/net/enic/enic_res.c
+++ b/drivers/net/enic/enic_res.c
@@ -26,6 +26,7 @@ int enic_get_vnic_config(struct enic *enic)
 	struct vnic_enet_config *c = &enic->config;
 	int err;
 	uint64_t sizes;
+	uint32_t max_rq_descs, max_wq_descs;
 
 	err = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);
 	if (err) {
@@ -57,6 +58,8 @@ int enic_get_vnic_config(struct enic *enic)
 	GET_CONFIG(loop_tag);
 	GET_CONFIG(num_arfs);
 	GET_CONFIG(max_pkt_size);
+	GET_CONFIG(max_rq_ring);
+	GET_CONFIG(max_wq_ring);
 
 	/* max packet size is only defined in newer VIC firmware
 	 * and will be 0 for legacy firmware and VICs
@@ -101,20 +104,29 @@ int enic_get_vnic_config(struct enic *enic)
 		((enic->filter_actions & FILTER_ACTION_COUNTER_FLAG) ?
 		 "count " : ""));
 
-	c->wq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_WQ_DESCS,
+	/* The max size of RQ and WQ rings are specified in 1500 series VICs and
+	 * beyond. If they are not specified by the VIC or if 64B CQ descriptors
+	 * are not being used, the max number of descriptors is 4096.
+	 */
+	max_wq_descs = (enic->cq64_request && c->max_wq_ring) ? c->max_wq_ring :
+		       ENIC_LEGACY_MAX_WQ_DESCS;
+	c->wq_desc_count = RTE_MIN(max_wq_descs,
 			RTE_MAX((uint32_t)ENIC_MIN_WQ_DESCS, c->wq_desc_count));
 	c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
-
-	c->rq_desc_count = RTE_MIN((uint32_t)ENIC_MAX_RQ_DESCS,
+	max_rq_descs = (enic->cq64_request && c->max_rq_ring) ? c->max_rq_ring
+		       : ENIC_LEGACY_MAX_WQ_DESCS;
+	c->rq_desc_count = RTE_MIN(max_rq_descs,
 			RTE_MAX((uint32_t)ENIC_MIN_RQ_DESCS, c->rq_desc_count));
 	c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
+	dev_debug(NULL, "Max supported VIC descriptors: WQ:%u, RQ:%u\n",
+		  max_wq_descs, max_rq_descs);
 
 	c->intr_timer_usec = RTE_MIN(c->intr_timer_usec,
 				  vnic_dev_get_intr_coal_timer_max(enic->vdev));
 
 	dev_info(enic_get_dev(enic),
 		"vNIC MAC addr " RTE_ETHER_ADDR_PRT_FMT
-		"wq/rq %d/%d mtu %d, max mtu:%d\n",
+		" wq/rq %d/%d mtu %d, max mtu:%d\n",
 		enic->mac_addr[0], enic->mac_addr[1], enic->mac_addr[2],
 		enic->mac_addr[3], enic->mac_addr[4], enic->mac_addr[5],
 		c->wq_desc_count, c->rq_desc_count,
diff --git a/drivers/net/enic/enic_res.h b/drivers/net/enic/enic_res.h
index 34f15d5a42..ae979d52be 100644
--- a/drivers/net/enic/enic_res.h
+++ b/drivers/net/enic/enic_res.h
@@ -12,9 +12,11 @@
 #include "vnic_rq.h"
 
 #define ENIC_MIN_WQ_DESCS		64
-#define ENIC_MAX_WQ_DESCS		4096
 #define ENIC_MIN_RQ_DESCS		64
-#define ENIC_MAX_RQ_DESCS		4096
+
+/* 1400 series VICs and prior all have 4K max, after that it's in the config */
+#define ENIC_LEGACY_MAX_WQ_DESCS        4096
+#define ENIC_LEGACY_MAX_RQ_DESCS        4096
 
 /* A descriptor ring has a multiple of 32 descriptors */
 #define ENIC_ALIGN_DESCS		32
diff --git a/drivers/net/enic/enic_rxtx.c b/drivers/net/enic/enic_rxtx.c
index c44715bfd0..4681ef6eca 100644
--- a/drivers/net/enic/enic_rxtx.c
+++ b/drivers/net/enic/enic_rxtx.c
@@ -84,6 +84,7 @@ enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,
 		uint8_t packet_error;
 		uint16_t ciflags;
 		uint8_t tc;
+		uint16_t rq_idx_msbs = 0;
 
 		max_rx--;
 
@@ -94,17 +95,24 @@ enic_recv_pkts_common(void *rx_queue, struct rte_mbuf **rx_pkts,
 
 		/* Get the cq descriptor and extract rq info from it */
 		cqd = *cqd_ptr;
+
 		/*
-		 * The first 16B of 64B descriptor is identical to the
-		 * 16B descriptor, except type_color. Copy type_color
-		 * from the 64B descriptor into the 16B descriptor's
-		 * field, so the code below can assume the 16B
-		 * descriptor format.
+		 * The first 16B of a 64B descriptor is identical to a 16B
+		 * descriptor except for the type_color and fetch index. Extract
+		 * fetch index and copy the type_color from the 64B to where it
+		 * would be in a 16B descriptor so sebwequent code can run
+		 * without further conditionals.
 		 */
-		if (use_64b_desc)
+		if (use_64b_desc) {
+			rq_idx_msbs = (((volatile struct cq_enet_rq_desc_64 *)
+				      cqd_ptr)->fetch_idx_flags
+				      & CQ_ENET_RQ_DESC_FETCH_IDX_MASK)
+				      << CQ_DESC_COMP_NDX_BITS;
 			cqd.type_color = tc;
+		}
 		rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
-		rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
+		rq_idx = rq_idx_msbs +
+			 (cqd.completed_index & CQ_DESC_COMP_NDX_MASK);
 
 		rq = &enic->rq[rq_num];
 		rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
@@ -362,14 +370,19 @@ static inline void enic_free_wq_bufs(struct vnic_wq *wq,
 				     uint16_t completed_index)
 {
 	struct rte_mbuf *buf;
-	struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
+	struct rte_mbuf *m, *free[ENIC_LEGACY_MAX_WQ_DESCS];
 	unsigned int nb_to_free, nb_free = 0, i;
 	struct rte_mempool *pool;
 	unsigned int tail_idx;
 	unsigned int desc_count = wq->ring.desc_count;
 
-	nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
-				   + 1;
+	/*
+	 * On 1500 Series VIC and beyond, greater than ENIC_LEGACY_MAX_WQ_DESCS
+	 * may be attempted to be freed. Cap it at ENIC_LEGACY_MAX_WQ_DESCS.
+	 */
+	nb_to_free = RTE_MIN(enic_ring_sub(desc_count, wq->tail_idx,
+			     completed_index) + 1,
+			     (uint32_t)ENIC_LEGACY_MAX_WQ_DESCS);
 	tail_idx = wq->tail_idx;
 	pool = wq->bufs[tail_idx]->pool;
 	for (i = 0; i < nb_to_free; i++) {
-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-01-14  3:11 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-14  3:10 [PATCH 0/3] enic PMD patches John Daley
2022-01-14  3:10 ` [PATCH 1/3] net/enic: add support for eCPRI matching John Daley
2022-01-14  3:10 ` [PATCH 2/3] net/enic: update VIC firmware API John Daley
2022-01-14  3:10 ` [PATCH 3/3] net/enic: support max descriptors allowed by adapter John Daley

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