* [PATCH v3 00/11] sync Truflow support with latest release
@ 2023-05-04 17:36 Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 01/11] net/bnxt: remove deprecated features Ajit Khaparde
` (11 more replies)
0 siblings, 12 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev
[-- Attachment #1: Type: text/plain, Size: 11816 bytes --]
Update Truflow support to latest release, deprecating code, updating
the copyright date and hsi structure, syncing the truflow core,
adding ULP shared session support, RSS action support, Queue
action support, rte meter support, and more.
Please apply.
v2->v3:
- update some commit messages
- removed some empty lines in the patches
- removed some dead and unnecessary code
- fixed some checkpatch errors
Version 2 fixes:
- misspellings
- whitespace issues
- signed off issues
Kishore Padmanabha (1):
net/bnxt: fix multi-root card support
Randy Schacher (8):
net/bnxt: remove deprecated features
net/bnxt: update bnxt hsi structure
net/bnxt: update copyright date and cleanup whitespace
net/bnxt: update Truflow core
net/bnxt: update ULP shared session support
net/bnxt: add RSS and Queue action in TruFLow
net/bnxt: add support for rte meter
net/bnxt: add support for eCPRI packet parsing
Shuanglin Wang (1):
net/bnxt: set RSS config based on RSS mode
Somnath Kotur (1):
net/bnxt: update PTP support on Thor
.mailmap | 1 +
doc/guides/nics/features/bnxt.ini | 3 +
drivers/net/bnxt/bnxt.h | 66 +-
drivers/net/bnxt/bnxt_cpr.c | 2 +-
drivers/net/bnxt/bnxt_cpr.h | 2 +-
drivers/net/bnxt/bnxt_ethdev.c | 209 +-
drivers/net/bnxt/bnxt_filter.c | 2 +-
drivers/net/bnxt/bnxt_filter.h | 6 +-
drivers/net/bnxt/bnxt_flow.c | 75 +-
drivers/net/bnxt/bnxt_hwrm.c | 272 +-
drivers/net/bnxt/bnxt_hwrm.h | 40 +-
drivers/net/bnxt/bnxt_irq.c | 2 +-
drivers/net/bnxt/bnxt_irq.h | 3 +-
drivers/net/bnxt/bnxt_nvm_defs.h | 3 +-
drivers/net/bnxt/bnxt_reps.c | 4 +-
drivers/net/bnxt/bnxt_reps.h | 2 +-
drivers/net/bnxt/bnxt_ring.c | 7 +-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 159 +-
drivers/net/bnxt/bnxt_rxq.h | 2 +-
drivers/net/bnxt/bnxt_rxr.c | 15 +-
drivers/net/bnxt/bnxt_rxr.h | 3 +-
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +-
drivers/net/bnxt/bnxt_stats.c | 2 +-
drivers/net/bnxt/bnxt_stats.h | 2 +-
drivers/net/bnxt/bnxt_txq.c | 3 +-
drivers/net/bnxt/bnxt_txq.h | 2 +-
drivers/net/bnxt/bnxt_txr.c | 55 +-
drivers/net/bnxt/bnxt_txr.h | 4 +-
drivers/net/bnxt/bnxt_util.c | 2 +-
drivers/net/bnxt/bnxt_util.h | 3 +-
drivers/net/bnxt/bnxt_vnic.c | 974 +-
drivers/net/bnxt/bnxt_vnic.h | 80 +-
drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 ++-
drivers/net/bnxt/meson.build | 5 +-
drivers/net/bnxt/rte_pmd_bnxt.c | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.h | 2 +-
drivers/net/bnxt/tf_core/bitalloc.c | 3 +-
drivers/net/bnxt/tf_core/bitalloc.h | 3 +-
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 +
.../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 +
drivers/net/bnxt/tf_core/dpool.c | 3 +-
drivers/net/bnxt/tf_core/dpool.h | 3 +-
drivers/net/bnxt/tf_core/ll.c | 2 +-
drivers/net/bnxt/tf_core/ll.h | 2 +-
drivers/net/bnxt/tf_core/lookup3.h | 1 -
drivers/net/bnxt/tf_core/meson.build | 38 +-
drivers/net/bnxt/tf_core/rand.c | 2 +-
drivers/net/bnxt/tf_core/rand.h | 3 +-
drivers/net/bnxt/tf_core/stack.c | 2 +-
drivers/net/bnxt/tf_core/stack.h | 3 +-
drivers/net/bnxt/tf_core/tf_common.h | 3 +-
drivers/net/bnxt/tf_core/tf_core.c | 56 +-
drivers/net/bnxt/tf_core/tf_core.h | 189 +-
drivers/net/bnxt/tf_core/tf_device.c | 53 +-
drivers/net/bnxt/tf_core/tf_device.h | 9 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 24 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 94 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +-
drivers/net/bnxt/tf_core/tf_em.h | 3 +-
drivers/net/bnxt/tf_core/tf_em_common.c | 10 +-
drivers/net/bnxt/tf_core/tf_em_common.h | 4 +-
.../net/bnxt/tf_core/tf_em_hash_internal.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_host.c | 3 +-
drivers/net/bnxt/tf_core/tf_em_internal.c | 13 +-
drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +-
drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +-
drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +-
drivers/net/bnxt/tf_core/tf_hash.c | 2 +-
drivers/net/bnxt/tf_core/tf_hash.h | 3 +-
drivers/net/bnxt/tf_core/tf_identifier.c | 111 +-
drivers/net/bnxt/tf_core/tf_identifier.h | 7 +-
drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +-
drivers/net/bnxt/tf_core/tf_if_tbl.h | 11 +-
drivers/net/bnxt/tf_core/tf_msg.c | 217 +-
drivers/net/bnxt/tf_core/tf_msg.h | 38 +-
drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +-
drivers/net/bnxt/tf_core/tf_project.h | 3 +-
drivers/net/bnxt/tf_core/tf_resources.h | 3 +-
drivers/net/bnxt/tf_core/tf_rm.c | 135 +-
drivers/net/bnxt/tf_core/tf_rm.h | 6 +-
drivers/net/bnxt/tf_core/tf_session.c | 121 +-
drivers/net/bnxt/tf_core/tf_session.h | 80 +-
.../net/bnxt/tf_core/tf_shadow_identifier.c | 190 -
.../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -
drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 -
drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 -
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 23 +-
drivers/net/bnxt/tf_core/tf_tbl.c | 8 +-
drivers/net/bnxt/tf_core/tf_tbl.h | 4 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +-
drivers/net/bnxt/tf_core/tf_tcam.c | 451 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 41 +-
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +-
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 4 +-
drivers/net/bnxt/tf_core/tf_util.c | 5 +-
drivers/net/bnxt/tf_core/tf_util.h | 3 +-
drivers/net/bnxt/tf_core/tfp.c | 2 +-
drivers/net/bnxt/tf_core/tfp.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 251 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 37 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 850 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 121 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 280 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 +
.../bnxt/tf_ulp/generic_templates/meson.build | 18 +-
.../generic_templates/ulp_template_db_act.c | 7000 +++-
.../generic_templates/ulp_template_db_class.c | 33556 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 4366 +-
.../generic_templates/ulp_template_db_field.h | 689 +-
.../generic_templates/ulp_template_db_tbl.c | 16055 ++++++--
.../ulp_template_db_thor_act.c | 8714 ++--
.../ulp_template_db_thor_class.c | 10746 +++--
.../ulp_template_db_wh_plus_act.c | 1157 +-
.../ulp_template_db_wh_plus_class.c | 288 +-
drivers/net/bnxt/tf_ulp/meson.build | 26 +-
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 26 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 37 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 5 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 131 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 726 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 64 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 35 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 30 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 504 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 46 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 25 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +-
163 files changed, 79517 insertions(+), 25424 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 01/11] net/bnxt: remove deprecated features
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
` (10 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Kishore Padmanabha, Peter Spreadborough
[-- Attachment #1: Type: text/plain, Size: 81234 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Deprecate shadow identifier
- Deprecate shadow TCAM
- Remove files which are not needed anymore.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 53 --
drivers/net/bnxt/bnxt_hwrm.h | 10 -
drivers/net/bnxt/tf_core/meson.build | 2 -
drivers/net/bnxt/tf_core/tf_core.c | 2 -
drivers/net/bnxt/tf_core/tf_core.h | 91 +-
drivers/net/bnxt/tf_core/tf_device.c | 35 -
drivers/net/bnxt/tf_core/tf_device.h | 6 -
drivers/net/bnxt/tf_core/tf_device_p4.c | 10 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 10 -
drivers/net/bnxt/tf_core/tf_identifier.c | 108 ---
drivers/net/bnxt/tf_core/tf_identifier.h | 4 -
drivers/net/bnxt/tf_core/tf_if_tbl.h | 8 -
drivers/net/bnxt/tf_core/tf_session.c | 9 +-
drivers/net/bnxt/tf_core/tf_session.h | 18 +-
.../net/bnxt/tf_core/tf_shadow_identifier.c | 190 ----
.../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -----
drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 ------------------
drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 ----
drivers/net/bnxt/tf_core/tf_tcam.c | 243 -----
drivers/net/bnxt/tf_core/tf_tcam.h | 38 +-
drivers/net/bnxt/tf_core/tf_util.c | 2 -
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 -
22 files changed, 8 insertions(+), 2095 deletions(-)
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index d86ac73293..3f273df6f3 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -407,59 +407,6 @@ int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
return rc;
}
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len)
-{
- int rc = 0;
- struct hwrm_cfa_tflib_input req = { .req_type = 0 };
- struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
- bool mailbox = BNXT_USE_CHIMP_MB;
-
- if (msg_len > sizeof(req.tf_req))
- return -ENOMEM;
-
- if (use_kong_mb)
- mailbox = BNXT_USE_KONG(bp);
-
- HWRM_PREP(&req, HWRM_TF, mailbox);
- /* Build request using the user supplied request payload.
- * TLV request size is checked at build time against HWRM
- * request max size, thus no checking required.
- */
- req.tf_type = tf_type;
- req.tf_subtype = tf_subtype;
- memcpy(req.tf_req, msg, msg_len);
-
- rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
- HWRM_CHECK_RESULT();
-
- /* Copy the resp to user provided response buffer */
- if (response != NULL)
- /* Post process response data. We need to copy only
- * the 'payload' as the HWRM data structure really is
- * HWRM header + msg header + payload and the TFLIB
- * only provided a payload place holder.
- */
- if (response_len != 0) {
- memcpy(response,
- resp->tf_resp,
- response_len);
- }
-
- /* Extract the internal tflib response code */
- *tf_response_code = resp->tf_resp_code;
- HWRM_UNLOCK();
-
- return rc;
-}
-
int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
int rc = 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index a82d9fb3ef..f9d9fe0ef2 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -79,16 +79,6 @@ struct hwrm_func_qstats_output;
bp->rx_cos_queue[x].profile = \
resp->queue_id##x##_service_profile
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len);
-
int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
bool use_kong_mb,
uint16_t msg_type,
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index 206935d18a..f812e471d1 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -30,9 +30,7 @@ sources += files(
'tf_identifier.c',
'tf_if_tbl.c',
'tf_session.c',
- 'tf_shadow_tcam.c',
'tf_tcam.c',
'tf_tcam_shared.c',
- 'tf_shadow_identifier.c',
'tf_hash.c',
'tf_device_p58.c')
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 90ff93946b..038e439101 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -917,7 +917,6 @@ tf_free_tcam_entry(struct tf *tfp,
return 0;
}
-#ifdef TF_TCAM_SHARED
int
tf_move_tcam_shared_entries(struct tf *tfp,
struct tf_move_tcam_shared_entries_parms *parms)
@@ -1019,7 +1018,6 @@ tf_clear_tcam_shared_entries(struct tf *tfp,
return 0;
}
-#endif /* TF_TCAM_SHARED */
int
tf_alloc_tbl_entry(struct tf *tfp,
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index f891d7a48f..814eff68da 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -337,41 +337,6 @@ enum tf_tbl_type {
TF_TBL_TYPE_MAX
};
-/** Enable Shared TCAM Management
- *
- * This feature allows for management of high and low pools within
- * the WC TCAM. These pools are only valid when this feature is enabled.
- *
- * For normal OVS-DPDK operation, this feature is not required and can
- * be disabled by commenting out TF_TCAM_SHARED in this header file.
- *
- * Operation:
- *
- * When a shared session is created with WC TCAM entries allocated during
- * tf_open_session(), the TF_TCAM_TBL_TYPE_WC_TCAM pool entries will be divided
- * into 2 equal pools - TF_TCAM_TBL_TYPE_WC_TCAM_HIGH and
- * TF_TCAM_TBL_TYPE_WC_TCAM_LOW.
- *
- * The user will allocate and free entries from either of these pools to obtain
- * WC_TCAM entry offsets. For the WC_TCAM_HI/LO management, alloc/free is done
- * using the tf_alloc_tcam_entry()/tf_free_tcam_entry() APIs for the shared
- * session.
- *
- * The use case for this feature is so that applications can have a shared
- * session and use the TF core to allocate/set/free entries within a given
- * region of the WC_TCAM within the shared session. Application A only writes
- * to the LOW region for example and Application B only writes to the HIGH
- * region during normal operation. After Application A goes down, Application
- * B may decide to overwrite the LOW region with the HIGH region's entries
- * and switch to the low region.
- *
- * For other TCAM types in the shared session, no alloc/free operations are
- * permitted. Only set should be used for other TCAM table types after getting
- * the range as provided by the tf_get_resource_info() API.
- *
- */
-#define TF_TCAM_SHARED 1
-
/**
* TCAM table type
*/
@@ -390,12 +355,10 @@ enum tf_tcam_tbl_type {
TF_TCAM_TBL_TYPE_CT_RULE_TCAM,
/** Virtual Edge Bridge TCAM */
TF_TCAM_TBL_TYPE_VEB_TCAM,
-#ifdef TF_TCAM_SHARED
/** Wildcard TCAM HI Priority */
TF_TCAM_TBL_TYPE_WC_TCAM_HIGH,
/** Wildcard TCAM Low Priority */
TF_TCAM_TBL_TYPE_WC_TCAM_LOW,
-#endif /* TF_TCAM_SHARED */
TF_TCAM_TBL_TYPE_MAX
};
@@ -626,20 +589,6 @@ struct tf_open_session_parms {
* 0000:02:00.0. The name for shared session is 0000:02:00.0-tf_shared.
*/
char ctrl_chan_name[TF_SESSION_NAME_MAX];
- /**
- * [in] shadow_copy
- *
- * Boolean controlling the use and availability of shadow
- * copy. Shadow copy will allow the TruFlow to keep track of
- * resource content on the firmware side without having to
- * query firmware. Additional private session core_data will
- * be allocated if this boolean is set to 'true', default
- * 'false'.
- *
- * Size of memory depends on the NVM Resource settings for the
- * control channel.
- */
- bool shadow_copy;
/**
* [in/out] session_id
*
@@ -1045,9 +994,6 @@ struct tf_search_identifier_parms {
* TruFlow core will allocate a free id from the per identifier resource type
* pool reserved for the session during tf_open(). No firmware is involved.
*
- * If shadow copy is enabled, the internal ref_cnt is set to 1 in the
- * shadow table for a newly allocated resource.
- *
* Returns success or failure code.
*/
int tf_alloc_identifier(struct tf *tfp,
@@ -1061,8 +1007,7 @@ int tf_alloc_identifier(struct tf *tfp,
* complete pool is returned to the firmware.
*
* additional operation (experimental)
- * Decrement reference count. Only release resource once refcnt goes to 0 if
- * shadow copy is enabled.
+ * Decrement reference count.
*
* Returns success or failure code.
*/
@@ -1072,19 +1017,6 @@ int tf_free_identifier(struct tf *tfp,
/**
* Search identifier resource (experimental)
*
- * If the shadow copy is enabled search_id is used to search for a matching
- * entry in the shadow table. The shadow table consists of an array of
- * reference counts indexed by identifier. If a matching entry is found hit is
- * set to TRUE, refcnt is increased by 1 and returned. Otherwise, hit is
- * set to false and refcnt is set to 0.
- *
- * TODO: we may need a per table internal shadow copy enable flag to stage
- * the shadow table implementation. We do not need the shadow table for other
- * tables at this time so we may only want to enable the identifier shadow.
- *
- * TODO: remove this pseudocode below added to show that if search fails
- * we shouldn't allocate a new entry but return.
- *
* identifier alloc (search_en=1)
* if (ident is allocated and ref_cnt >=1)
* return ident - hit is set, incr refcnt
@@ -1262,11 +1194,9 @@ int tf_free_tbl_scope(struct tf *tfp,
*
* @ref tf_free_tcam_entry
*
-#ifdef TF_TCAM_SHARED
* @ref tf_move_tcam_shared_entries
*
* @ref tf_clear_tcam_shared_entries
-#endif
*/
/**
@@ -1332,14 +1262,9 @@ struct tf_search_tcam_entry_parms {
*
* Search for a TCAM entry
*
- * This function searches the shadow copy of the TCAM table for a matching
- * entry. Key and mask must match for hit to be set. Only TruFlow core data
- * is accessed. If shadow_copy is not enabled, an error is returned.
- *
* Implementation:
*
- * A hash is performed on the key/mask data and mapped to a shadow copy entry
- * where the full key/mask is populated. If the full key/mask matches the
+ * If the full key/mask matches the
* entry, hit is set, ref_cnt is incremented, and search_status indicates what
* action the caller can take regarding setting the entry.
*
@@ -1416,8 +1341,7 @@ struct tf_alloc_tcam_entry_parms {
*
* This function allocates a TCAM table record. This function
* will attempt to allocate a TCAM table entry from the session
- * owned TCAM entries or search a shadow copy of the TCAM table for a
- * matching entry if search is enabled. Key, mask and result must match for
+ * owned TCAM entries. Key, mask and result must match for
* hit to be set. Only TruFlow core data is accessed.
* A hash table to entry mapping is maintained for search purposes. If
* search is not enabled, the first available free entry is returned based
@@ -1568,7 +1492,6 @@ struct tf_free_tcam_entry_parms {
int tf_free_tcam_entry(struct tf *tfp,
struct tf_free_tcam_entry_parms *parms);
-#ifdef TF_TCAM_SHARED
/**
* tf_move_tcam_shared_entries parameter definition
*/
@@ -1633,7 +1556,6 @@ struct tf_clear_tcam_shared_entries_parms {
int tf_clear_tcam_shared_entries(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-#endif /* TF_TCAM_SHARED */
/**
* @page table Table Access
*
@@ -1854,9 +1776,6 @@ struct tf_get_tbl_entry_parms {
*
* Used to retrieve a previous set index table entry.
*
- * Reads and compares with the shadow table copy (if enabled) (only
- * for internal objects).
- *
* Returns success or failure code. Failure will be returned if the
* provided data buffer is too small for the data type requested.
*/
@@ -2165,9 +2084,7 @@ int tf_delete_em_entry(struct tf *tfp,
* succeeds, a pointer to the matching entry and the result record associated
* with the matching entry will be provided.
*
- * If flow_handle is set, search shadow copy.
- *
- * Otherwise, query the fw with key to get result.
+ * Query the fw with key to get result.
*
* External:
*
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index a35d22841c..1c97218b5b 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -9,10 +9,8 @@
#include "tfp.h"
#include "tf_em.h"
#include "tf_rm.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
#include "tf_tbl_sram.h"
-#endif /* TF_TCAM_SHARED */
struct tf;
@@ -67,9 +65,6 @@ tf_dev_reservation_check(uint16_t count,
* [in] tfp
* Pointer to TF handle
*
- * [in] shadow_copy
- * Flag controlling shadow copy DB creation
- *
* [in] resources
* Pointer to resource allocation information
*
@@ -82,7 +77,6 @@ tf_dev_reservation_check(uint16_t count,
*/
static int
tf_dev_bind_p4(struct tf *tfp,
- bool shadow_copy,
struct tf_session_resources *resources,
struct tf_dev_info *dev_handle,
enum tf_wc_num_slice wc_num_slices)
@@ -115,7 +109,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
ident_cfg.num_elements = TF_IDENT_TYPE_MAX;
ident_cfg.cfg = tf_ident_p4;
- ident_cfg.shadow_copy = shadow_copy;
ident_cfg.resources = resources;
rc = tf_ident_bind(tfp, &ident_cfg);
if (rc) {
@@ -150,14 +143,9 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX;
tcam_cfg.cfg = tf_tcam_p4;
- tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
tcam_cfg.wc_num_slices = wc_num_slices;
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_bind(tfp, &tcam_cfg);
-#endif
if (rc) {
TFP_DRV_LOG(ERR,
"TCAM initialization failure\n");
@@ -223,7 +211,6 @@ tf_dev_bind_p4(struct tf *tfp,
*/
if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX;
if_tbl_cfg.cfg = tf_if_tbl_p4;
- if_tbl_cfg.shadow_copy = shadow_copy;
rc = tf_if_tbl_bind(tfp, &if_tbl_cfg);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -287,11 +274,7 @@ tf_dev_unbind_p4(struct tf *tfp)
* In case of residuals TCAMs are cleaned up first as to
* invalidate the pipeline in a clean manner.
*/
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_unbind(tfp);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_unbind(tfp);
-#endif /* TF_TCAM_SHARED */
if (rc) {
TFP_DRV_LOG(INFO,
"Device unbind failed, TCAM\n");
@@ -354,9 +337,6 @@ tf_dev_unbind_p4(struct tf *tfp)
* [in] tfp
* Pointer to TF handle
*
- * [in] shadow_copy
- * Flag controlling shadow copy DB creation
- *
* [in] resources
* Pointer to resource allocation information
*
@@ -369,7 +349,6 @@ tf_dev_unbind_p4(struct tf *tfp)
*/
static int
tf_dev_bind_p58(struct tf *tfp,
- bool shadow_copy,
struct tf_session_resources *resources,
struct tf_dev_info *dev_handle,
enum tf_wc_num_slice wc_num_slices)
@@ -400,7 +379,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
ident_cfg.num_elements = TF_IDENT_TYPE_MAX;
ident_cfg.cfg = tf_ident_p58;
- ident_cfg.shadow_copy = shadow_copy;
ident_cfg.resources = resources;
rc = tf_ident_bind(tfp, &ident_cfg);
if (rc) {
@@ -443,14 +421,9 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX;
tcam_cfg.cfg = tf_tcam_p58;
- tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
tcam_cfg.wc_num_slices = wc_num_slices;
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_bind(tfp, &tcam_cfg);
-#endif
if (rc) {
TFP_DRV_LOG(ERR,
"TCAM initialization failure\n");
@@ -495,7 +468,6 @@ tf_dev_bind_p58(struct tf *tfp,
*/
if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX;
if_tbl_cfg.cfg = tf_if_tbl_p58;
- if_tbl_cfg.shadow_copy = shadow_copy;
rc = tf_if_tbl_bind(tfp, &if_tbl_cfg);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -560,11 +532,7 @@ tf_dev_unbind_p58(struct tf *tfp)
* In case of residuals TCAMs are cleaned up first as to
* invalidate the pipeline in a clean manner.
*/
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_unbind(tfp);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_unbind(tfp);
-#endif /* TF_TCAM_SHARED */
if (rc) {
TFP_DRV_LOG(INFO,
"Device unbind failed, TCAM\n");
@@ -629,7 +597,6 @@ tf_dev_unbind_p58(struct tf *tfp)
int
tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
- bool shadow_copy,
struct tf_session_resources *resources,
uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
@@ -639,14 +606,12 @@ tf_dev_bind(struct tf *tfp __rte_unused,
case TF_DEVICE_TYPE_SR:
dev_handle->type = type;
return tf_dev_bind_p4(tfp,
- shadow_copy,
resources,
dev_handle,
wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
- shadow_copy,
resources,
dev_handle,
wc_num_slices);
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index bfb5de4370..bc6de60423 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -11,9 +11,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
@@ -86,7 +84,6 @@ struct tf_hcapi_resource_map {
*/
int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
- bool shadow_copy,
struct tf_session_resources *resources,
uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
@@ -705,7 +702,6 @@ struct tf_dev_ops {
int (*tf_dev_get_tcam)(struct tf *tfp,
struct tf_tcam_get_parms *parms);
-#ifdef TF_TCAM_SHARED
/**
* Move TCAM shared entries
*
@@ -738,8 +734,6 @@ struct tf_dev_ops {
int (*tf_dev_clear_tcam)(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-#endif /* TF_TCAM_SHARED */
-
/**
* Retrieves the tcam resource info.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index b8b3dcbb3f..72c6b1cde8 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -10,9 +10,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif /* TF_TCAM_SHARED */
#include "tf_em.h"
#include "tf_if_tbl.h"
#include "tfp.h"
@@ -540,20 +538,12 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
-#ifdef TF_TCAM_SHARED
.tf_dev_alloc_tcam = tf_tcam_shared_alloc,
.tf_dev_free_tcam = tf_tcam_shared_free,
.tf_dev_set_tcam = tf_tcam_shared_set,
.tf_dev_get_tcam = tf_tcam_shared_get,
.tf_dev_move_tcam = tf_tcam_shared_move_p4,
.tf_dev_clear_tcam = tf_tcam_shared_clear,
-#else /* !TF_TCAM_SHARED */
- .tf_dev_alloc_tcam = tf_tcam_alloc,
- .tf_dev_free_tcam = tf_tcam_free,
- .tf_dev_set_tcam = tf_tcam_set,
- .tf_dev_get_tcam = tf_tcam_get,
-#endif
- .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_delete_int_entry,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 8179287e46..f8b424ebc9 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -10,9 +10,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif /* TF_TCAM_SHARED */
#include "tf_em.h"
#include "tf_if_tbl.h"
#include "tfp.h"
@@ -848,20 +846,12 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
-#ifdef TF_TCAM_SHARED
.tf_dev_alloc_tcam = tf_tcam_shared_alloc,
.tf_dev_free_tcam = tf_tcam_shared_free,
.tf_dev_set_tcam = tf_tcam_shared_set,
.tf_dev_get_tcam = tf_tcam_shared_get,
.tf_dev_move_tcam = tf_tcam_shared_move_p58,
.tf_dev_clear_tcam = tf_tcam_shared_clear,
-#else /* !TF_TCAM_SHARED */
- .tf_dev_alloc_tcam = tf_tcam_alloc,
- .tf_dev_free_tcam = tf_tcam_free,
- .tf_dev_set_tcam = tf_tcam_set,
- .tf_dev_get_tcam = tf_tcam_get,
-#endif
- .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index c491f77a2b..8131d8754d 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -6,7 +6,6 @@
#include <rte_common.h>
#include "tf_identifier.h"
-#include "tf_shadow_identifier.h"
#include "tf_common.h"
#include "tf_rm.h"
#include "tf_util.h"
@@ -15,16 +14,6 @@
struct tf;
-/**
- * Identifier shadow DBs.
- */
-static void *ident_shadow_db[TF_DIR_MAX];
-
-/**
- * Shadow DB Init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
-
int
tf_ident_bind(struct tf *tfp,
struct tf_ident_cfg_parms *parms)
@@ -33,8 +22,6 @@ tf_ident_bind(struct tf *tfp,
int db_rc[TF_DIR_MAX] = { 0 };
int i;
struct tf_rm_create_db_parms db_cfg = { 0 };
- struct tf_shadow_ident_cfg_parms shadow_cfg = { 0 };
- struct tf_shadow_ident_create_db_parms shadow_cdb = { 0 };
struct ident_rm_db *ident_db;
struct tfp_calloc_parms cparms;
struct tf_session *tfs;
@@ -74,23 +61,6 @@ tf_ident_bind(struct tf *tfp,
db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg);
else
db_rc[i] = tf_rm_create_db(tfp, &db_cfg);
-
- if (parms->shadow_copy) {
- shadow_cfg.alloc_cnt =
- parms->resources->ident_cnt[i].cnt;
- shadow_cdb.num_elements = parms->num_elements;
- shadow_cdb.tf_shadow_ident_db = &ident_shadow_db[i];
- shadow_cdb.cfg = &shadow_cfg;
- rc = tf_shadow_ident_create_db(&shadow_cdb);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Ident shadow DB creation failed\n",
- tf_dir_2_str(i));
-
- return rc;
- }
- shadow_init = 1;
- }
}
/* No db created */
@@ -111,7 +81,6 @@ tf_ident_unbind(struct tf *tfp)
int rc = 0;
int i;
struct tf_rm_free_db_parms fparms = { 0 };
- struct tf_shadow_ident_free_db_parms sparms = { 0 };
struct ident_rm_db *ident_db;
void *ident_db_ptr = NULL;
@@ -132,22 +101,8 @@ tf_ident_unbind(struct tf *tfp)
TFP_DRV_LOG(ERR,
"rm free failed on unbind\n");
}
- if (shadow_init) {
- sparms.tf_shadow_ident_db = ident_shadow_db[i];
- rc = tf_shadow_ident_free_db(&sparms);
- if (rc) {
- /* TODO: If there are failures on unbind we
- * really just have to try until all DBs are
- * attempted to be cleared.
- */
- }
- ident_shadow_db[i] = NULL;
- }
ident_db->ident_db[i] = NULL;
}
-
- shadow_init = 0;
-
return 0;
}
@@ -159,7 +114,6 @@ tf_ident_alloc(struct tf *tfp __rte_unused,
uint32_t id;
uint32_t base_id;
struct tf_rm_allocate_parms aparms = { 0 };
- struct tf_shadow_ident_insert_parms iparms = { 0 };
struct ident_rm_db *ident_db;
void *ident_db_ptr = NULL;
@@ -187,23 +141,7 @@ tf_ident_alloc(struct tf *tfp __rte_unused,
return rc;
}
- if (shadow_init) {
- iparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- iparms.type = parms->type;
- iparms.id = base_id;
-
- rc = tf_shadow_ident_insert(&iparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed insert shadow DB, type:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
*parms->id = id;
-
return 0;
}
@@ -214,7 +152,6 @@ tf_ident_free(struct tf *tfp __rte_unused,
int rc;
struct tf_rm_is_allocated_parms aparms = { 0 };
struct tf_rm_free_parms fparms = { 0 };
- struct tf_shadow_ident_remove_parms rparms = { 0 };
int allocated = 0;
uint32_t base_id;
struct ident_rm_db *ident_db;
@@ -250,27 +187,6 @@ tf_ident_free(struct tf *tfp __rte_unused,
return -EINVAL;
}
- if (shadow_init) {
- rparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- rparms.type = parms->type;
- rparms.id = base_id;
- rparms.ref_cnt = parms->ref_cnt;
-
- rc = tf_shadow_ident_remove(&rparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: ref_cnt was 0 in shadow DB,"
- " type:%d, index:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->id);
- return rc;
- }
-
- if (*rparms.ref_cnt > 0)
- return 0;
- }
-
/* Free requested element */
fparms.rm_db = ident_db->ident_db[parms->dir];
fparms.subtype = parms->type;
@@ -294,7 +210,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
{
int rc;
struct tf_rm_is_allocated_parms aparms = { 0 };
- struct tf_shadow_ident_search_parms sparms = { 0 };
int allocated = 0;
uint32_t base_id;
struct ident_rm_db *ident_db;
@@ -302,13 +217,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
TF_CHECK_PARMS2(tfp, parms);
- if (!shadow_init) {
- TFP_DRV_LOG(ERR,
- "%s: Identifier Shadow copy is not enabled\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -336,22 +244,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
parms->search_id);
return -EINVAL;
}
-
- sparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- sparms.type = parms->type;
- sparms.search_id = base_id;
- sparms.hit = parms->hit;
- sparms.ref_cnt = parms->ref_cnt;
-
- rc = tf_shadow_ident_search(&sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed search shadow DB, type:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
-
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h
index 55c093802e..285ff11ce2 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.h
+++ b/drivers/net/bnxt/tf_core/tf_identifier.h
@@ -22,10 +22,6 @@ struct tf_ident_cfg_parms {
* [in] Identifier configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * [in] Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* [in] Session resource allocations
*/
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h
index 9f081c8196..bea2f07324 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h
@@ -84,14 +84,6 @@ struct tf_if_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_if_tbl_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_if_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index c30c0e7029..d0a0916c6a 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -141,8 +141,6 @@ tf_session_create(struct tf *tfp,
/* Return the allocated session id */
session_id->id = session->session_id.id;
- session->shadow_copy = parms->open_cfg->shadow_copy;
-
/* Init session client list */
ll_init(&session->client_ll);
@@ -200,7 +198,6 @@ tf_session_create(struct tf *tfp,
rc = tf_dev_bind(tfp,
parms->open_cfg->device_type,
- session->shadow_copy,
&parms->open_cfg->resources,
parms->open_cfg->wc_num_slices,
&session->dev);
@@ -360,7 +357,7 @@ tf_session_client_create(struct tf *tfp,
* - (-EINVAL) on failure.
* - (-ENOTFOUND) error, client not owned by the session.
* - (-ENOTSUPP) error, unable to destroy client as its the last
- * client. Please use the tf_session_close().
+ * client. Please use the tf_session_close().
*/
static int
tf_session_client_destroy(struct tf *tfp,
@@ -992,8 +989,6 @@ tf_session_set_db(struct tf *tfp,
return rc;
}
-#ifdef TF_TCAM_SHARED
-
int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle)
@@ -1070,8 +1065,6 @@ tf_session_set_sram_db(struct tf *tfp,
return rc;
}
-#endif /* TF_TCAM_SHARED */
-
int
tf_session_get_global_db(struct tf *tfp,
void **global_handle)
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index 19a96c28b1..a6716dfff4 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -48,8 +48,7 @@
*
* Shared memory containing private TruFlow session information.
* Through this structure the session can keep track of resource
- * allocations and (if so configured) any shadow copy of flow
- * information. It also holds info about Session Clients.
+ * allocations. It also holds info about Session Clients.
*
* Memory is assigned to the Truflow instance by way of
* tf_open_session. Memory is allocated and owned by i.e. ULP.
@@ -86,19 +85,6 @@ struct tf_session {
*/
bool shared_session_creator;
- /**
- * Boolean controlling the use and availability of shadow
- * copy. Shadow copy will allow the TruFlow Core to keep track
- * of resource content on the firmware side without having to
- * query firmware. Additional private session core_data will
- * be allocated if this boolean is set to 'true', default
- * 'false'.
- *
- * Size of memory depends on the NVM Resource settings for the
- * control channel.
- */
- bool shadow_copy;
-
/**
* Session Reference Count. To keep track of functions per
* session the ref_count is updated. There is also a
@@ -159,12 +145,10 @@ struct tf_session {
*/
void *em_pool[TF_DIR_MAX];
-#ifdef TF_TCAM_SHARED
/**
* tcam db reference for the session
*/
void *tcam_shared_db_handle;
-#endif /* TF_TCAM_SHARED */
/**
* SRAM db reference for the session
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c b/drivers/net/bnxt/tf_core/tf_shadow_identifier.c
deleted file mode 100644
index dc9606712c..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#include <rte_common.h>
-
-#include "tf_shadow_identifier.h"
-#include "tf_common.h"
-#include "tf_util.h"
-#include "tfp.h"
-
-/**
- * Shadow identifier DB element
- */
-struct tf_shadow_ident_element {
- /**
- * Identifier
- */
- uint32_t *id;
-
- /**
- * Reference count, array of number of identifier type entries
- */
- uint32_t *ref_count;
-};
-
-/**
- * Shadow identifier DB definition
- */
-struct tf_shadow_ident_db {
- /**
- * Number of elements in the DB
- */
- uint16_t num_entries;
-
- /**
- * The DB consists of an array of elements
- */
- struct tf_shadow_ident_element *db;
-};
-
-int
-tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms)
-{
- int rc;
- int i;
- struct tfp_calloc_parms cparms;
- struct tf_shadow_ident_db *shadow_db;
- struct tf_shadow_ident_element *db;
-
- TF_CHECK_PARMS1(parms);
-
- /* Build the shadow DB per the request */
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_ident_db);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db = (void *)cparms.mem_va;
-
- /* Build the DB within shadow DB */
- cparms.nitems = parms->num_elements;
- cparms.size = sizeof(struct tf_shadow_ident_element);
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db->db = (struct tf_shadow_ident_element *)cparms.mem_va;
- shadow_db->num_entries = parms->num_elements;
-
- db = shadow_db->db;
- for (i = 0; i < parms->num_elements; i++) {
- /* If the element didn't request an allocation no need
- * to create a pool nor verify if we got a reservation.
- */
- if (parms->cfg->alloc_cnt[i] == 0)
- continue;
-
- /* Create array */
- cparms.nitems = parms->cfg->alloc_cnt[i];
- cparms.size = sizeof(uint32_t);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Array alloc failed, type:%d\n",
- tf_dir_2_str(parms->dir),
- i);
- goto fail;
- }
- db[i].ref_count = (uint32_t *)cparms.mem_va;
- }
-
- *parms->tf_shadow_ident_db = (void *)shadow_db;
-
- return 0;
-fail:
- tfp_free((void *)db->ref_count);
- tfp_free((void *)db);
- tfp_free((void *)shadow_db);
- parms->tf_shadow_ident_db = NULL;
-
- return -EINVAL;
-}
-
-int
-tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms)
-{
- int i;
- struct tf_shadow_ident_db *shadow_db;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- for (i = 0; i < shadow_db->num_entries; i++)
- tfp_free((void *)shadow_db->db[i].ref_count);
-
- tfp_free((void *)shadow_db->db);
- tfp_free((void *)parms->tf_shadow_ident_db);
-
- return 0;
-}
-
-int
-tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
- uint32_t ref_cnt = 0;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- ref_cnt = shadow_db->db[parms->type].ref_count[parms->search_id];
- if (ref_cnt > 0) {
- *parms->hit = 1;
- *parms->ref_cnt = ++ref_cnt;
- shadow_db->db[parms->type].ref_count[parms->search_id] =
- ref_cnt;
- } else {
- *parms->hit = 0;
- *parms->ref_cnt = 0;
- }
-
-
- return 0;
-}
-
-#define ID_REF_CNT_MAX 0xffffffff
-int
-tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
-
- /* In case of overflow, ref count keeps the max value */
- if (shadow_db->db[parms->type].ref_count[parms->id] < ID_REF_CNT_MAX)
- shadow_db->db[parms->type].ref_count[parms->id]++;
- else
- TFP_DRV_LOG(ERR,
- "Identifier %d in type %d reaches the max ref_cnt\n",
- parms->type,
- parms->id);
-
- parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
-
- return 0;
-}
-
-int
-tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
- uint32_t ref_cnt = 0;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
- if (ref_cnt > 0)
- shadow_db->db[parms->type].ref_count[parms->id]--;
- else
- return -EINVAL;
-
- *parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
-
- return 0;
-}
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h b/drivers/net/bnxt/tf_core/tf_shadow_identifier.h
deleted file mode 100644
index ff41eaad9f..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#ifndef _TF_SHADOW_IDENTIFIER_H_
-#define _TF_SHADOW_IDENTIFIER_H_
-
-#include "tf_core.h"
-
-struct tf;
-
-/**
- * The Shadow Identifier module provides shadow DB handling for identifier based
- * TF types. A shadow DB provides the capability that allows for reuse
- * of TF resources.
- *
- * A Shadow identifier DB is intended to be used by the Identifier Type module
- * only.
- */
-
-/**
- * Shadow DB configuration information for a single identifier type.
- *
- * It is used in an array of identifier types. The array must be ordered
- * by the TF type is represents.
- */
-struct tf_shadow_ident_cfg_parms {
- /**
- * TF Identifier type
- */
- enum tf_identifier_type type;
-
- /**
- * Number of entries the Shadow DB needs to hold
- */
- int num_entries;
-
- /**
- * Resource allocation count array. This array content
- * originates from the tf_session_resources that is passed in
- * on session open.
- * Array size is num_elements.
- */
- uint16_t *alloc_cnt;
-};
-
-/**
- * Shadow identifier DB creation parameters
- */
-struct tf_shadow_ident_create_db_parms {
- /**
- * [in] Receive or transmit direction.
- */
- enum tf_dir dir;
- /**
- * [in] Configuration information for the shadow db
- */
- struct tf_shadow_ident_cfg_parms *cfg;
- /**
- * [in] Number of elements in the parms structure
- */
- uint16_t num_elements;
- /**
- * [out] Shadow identifier DB handle
- */
- void **tf_shadow_ident_db;
-};
-
-/**
- * Shadow identifier DB free parameters
- */
-struct tf_shadow_ident_free_db_parms {
- /**
- * Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
-};
-
-/**
- * Shadow identifier search parameters
- */
-struct tf_shadow_ident_search_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Identifier type
- */
- enum tf_identifier_type type;
- /**
- * [in] id to search
- */
- uint16_t search_id;
- /**
- * [out] Index of the found element returned if hit
- */
- bool *hit;
- /**
- * [out] Reference count incremented if hit
- */
- uint32_t *ref_cnt;
-};
-
-/**
- * Shadow identifier insert parameters
- */
-struct tf_shadow_ident_insert_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Tbl type
- */
- enum tf_identifier_type type;
- /**
- * [in] Entry to update
- */
- uint16_t id;
- /**
- * [out] Reference count after insert
- */
- uint32_t ref_cnt;
-};
-
-/**
- * Shadow identifier remove parameters
- */
-struct tf_shadow_ident_remove_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Tbl type
- */
- enum tf_identifier_type type;
- /**
- * [in] Entry to update
- */
- uint16_t id;
- /**
- * [out] Reference count after removal
- */
- uint32_t *ref_cnt;
-};
-
-/**
- * @page shadow_ident Shadow identifier DB
- *
- * @ref tf_shadow_ident_create_db
- *
- * @ref tf_shadow_ident_free_db
- *
- * @reg tf_shadow_ident_search
- *
- * @reg tf_shadow_ident_insert
- *
- * @reg tf_shadow_ident_remove
- */
-
-/**
- * Creates and fills a Shadow identifier DB. The DB is indexed per the
- * parms structure.
- *
- * [in] parms
- * Pointer to create db parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms);
-
-/**
- * Closes the Shadow identifier DB and frees all allocated
- * resources per the associated database.
- *
- * [in] parms
- * Pointer to the free DB parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms);
-
-/**
- * Search Shadow identifier db for matching result
- *
- * [in] parms
- * Pointer to the search parameters
- *
- * Returns
- * - (0) if successful, element was found.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms);
-
-/**
- * Inserts an element into the Shadow identifier DB. Ref_count after insert
- * will be incremented.
- *
- * [in] parms
- * Pointer to insert parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms);
-
-/**
- * Removes an element from the Shadow identifier DB. Will fail if the
- * elements ref_count is 0. Ref_count after removal will be
- * decremented.
- *
- * [in] parms
- * Pointer to remove parameter
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms);
-
-#endif /* _TF_SHADOW_IDENTIFIER_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c
deleted file mode 100644
index 5fcd1f9107..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#include "tf_common.h"
-#include "tf_util.h"
-#include "tfp.h"
-#include "tf_tcam.h"
-#include "tf_shadow_tcam.h"
-#include "tf_hash.h"
-
-/**
- * The implementation includes 3 tables per tcam table type.
- * - hash table
- * - sized so that a minimum of 4 slots per shadow entry are available to
- * minimize the likelihood of collisions.
- * - shadow key table
- * - sized to the number of entries requested and is directly indexed
- * - the index is zero based and is the tcam index - the base address
- * - the key and mask are stored in the key table.
- * - The stored key is the AND of the key/mask in order to eliminate the need
- * to compare both the key and mask.
- * - shadow result table
- * - the result table is stored separately since it only needs to be accessed
- * when the key matches.
- * - the result has a back pointer to the hash table via the hb handle. The
- * hb handle is a 32 bit representation of the hash with a valid bit, bucket
- * element index, and the hash index. It is necessary to store the hb handle
- * with the result since subsequent removes only provide the tcam index.
- *
- * - Max entries is limited in the current implementation since bit 15 is the
- * valid bit in the hash table.
- * - A 16bit hash is calculated and masked based on the number of entries
- * - 64b wide bucket is used and broken into 4x16bit elements.
- * This decision is based on quicker bucket scanning to determine if any
- * elements are in use.
- * - bit 15 of each bucket element is the valid, this is done to prevent having
- * to read the larger key/result data for determining VALID. It also aids
- * in the more efficient scanning of the bucket for slot usage.
- */
-
-/*
- * The maximum number of shadow entries supported. The value also doubles as
- * the maximum number of hash buckets. There are only 15 bits of data per
- * bucket to point to the shadow tables.
- */
-#define TF_SHADOW_TCAM_ENTRIES_MAX (1 << 15)
-
-/* The number of elements(BE) per hash bucket (HB) */
-#define TF_SHADOW_TCAM_HB_NUM_ELEM (4)
-#define TF_SHADOW_TCAM_BE_VALID (1 << 15)
-#define TF_SHADOW_TCAM_BE_IS_VALID(be) (((be) & TF_SHADOW_TCAM_BE_VALID) != 0)
-
-/**
- * The hash bucket handle is 32b
- * - bit 31, the Valid bit
- * - bit 29-30, the element
- * - bits 0-15, the hash idx (is masked based on the allocated size)
- */
-#define TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) != 0)
-#define TF_SHADOW_TCAM_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \
- ((be) << 29) | (idx))
-
-#define TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hdl) (((hdl) >> 29) & \
- (TF_SHADOW_TCAM_HB_NUM_ELEM - 1))
-
-#define TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hdl)((hdl) & \
- (ctxt)->hash_ctxt.hid_mask)
-
-/**
- * The idx provided by the caller is within a region, so currently the base is
- * either added or subtracted from the idx to ensure it can be used as a
- * compressed index
- */
-
-/* Convert the tcam index to a shadow index */
-#define TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, idx) ((idx) - \
- (ctxt)->shadow_ctxt.base_addr)
-
-/* Convert the shadow index to a tcam index */
-#define TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt, idx) ((idx) + \
- (ctxt)->shadow_ctxt.base_addr)
-
-/* Simple helper masks for clearing en element from the bucket */
-#define TF_SHADOW_TCAM_BE0_MASK_CLEAR(hb) ((hb) & 0xffffffffffff0000ull)
-#define TF_SHADOW_TCAM_BE1_MASK_CLEAR(hb) ((hb) & 0xffffffff0000ffffull)
-#define TF_SHADOW_TCAM_BE2_MASK_CLEAR(hb) ((hb) & 0xffff0000ffffffffull)
-#define TF_SHADOW_TCAM_BE3_MASK_CLEAR(hb) ((hb) & 0x0000ffffffffffffull)
-
-/**
- * This should be coming from external, but for now it is assumed that no key
- * is greater than 1K bits and no result is bigger than 128 bits. This makes
- * allocation of the hash table easier without having to allocate on the fly.
- */
-#define TF_SHADOW_TCAM_MAX_KEY_SZ 128
-#define TF_SHADOW_TCAM_MAX_RESULT_SZ 16
-
-/*
- * Local only defines for the internal data.
- */
-
-/**
- * tf_shadow_tcam_shadow_key_entry is the key/mask entry of the key table.
- * The key stored in the table is the masked version of the key. This is done
- * to eliminate the need of comparing both the key and mask.
- */
-struct tf_shadow_tcam_shadow_key_entry {
- uint8_t key[TF_SHADOW_TCAM_MAX_KEY_SZ];
- uint8_t mask[TF_SHADOW_TCAM_MAX_KEY_SZ];
-};
-
-/**
- * tf_shadow_tcam_shadow_result_entry is the result table entry.
- * The result table writes are broken into two phases:
- * - The search phase, which stores the hb_handle and key size and
- * - The set phase, which writes the result, refcnt, and result size
- */
-struct tf_shadow_tcam_shadow_result_entry {
- uint8_t result[TF_SHADOW_TCAM_MAX_RESULT_SZ];
- uint16_t result_size;
- uint16_t key_size;
- uint32_t refcnt;
- uint32_t hb_handle;
-};
-
-/**
- * tf_shadow_tcam_shadow_ctxt holds all information for accessing the key and
- * result tables.
- */
-struct tf_shadow_tcam_shadow_ctxt {
- struct tf_shadow_tcam_shadow_key_entry *sh_key_tbl;
- struct tf_shadow_tcam_shadow_result_entry *sh_res_tbl;
- uint32_t base_addr;
- uint16_t num_entries;
- uint16_t alloc_idx;
-};
-
-/**
- * tf_shadow_tcam_hash_ctxt holds all information related to accessing the hash
- * table.
- */
-struct tf_shadow_tcam_hash_ctxt {
- uint64_t *hashtbl;
- uint16_t hid_mask;
- uint16_t hash_entries;
-};
-
-/**
- * tf_shadow_tcam_ctxt holds the hash and shadow tables for the current shadow
- * tcam db. This structure is per tcam table type as each tcam table has it's
- * own shadow and hash table.
- */
-struct tf_shadow_tcam_ctxt {
- struct tf_shadow_tcam_shadow_ctxt shadow_ctxt;
- struct tf_shadow_tcam_hash_ctxt hash_ctxt;
-};
-
-/**
- * tf_shadow_tcam_db is the allocated db structure returned as an opaque
- * void * pointer to the caller during create db. It holds the pointers for
- * each tcam associated with the db.
- */
-struct tf_shadow_tcam_db {
- /* Each context holds the shadow and hash table information */
- struct tf_shadow_tcam_ctxt *ctxt[TF_TCAM_TBL_TYPE_MAX];
-};
-
-/**
- * Returns the number of entries in the contexts shadow table.
- */
-static inline uint16_t
-tf_shadow_tcam_sh_num_entries_get(struct tf_shadow_tcam_ctxt *ctxt)
-{
- return ctxt->shadow_ctxt.num_entries;
-}
-
-/**
- * Compare the give key with the key in the shadow table.
- *
- * Returns 0 if the keys match
- */
-static int
-tf_shadow_tcam_key_cmp(struct tf_shadow_tcam_ctxt *ctxt,
- uint8_t *key,
- uint8_t *mask,
- uint16_t sh_idx,
- uint16_t size)
-{
- if (size != ctxt->shadow_ctxt.sh_res_tbl[sh_idx].key_size ||
- sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !key || !mask)
- return -1;
-
- return memcmp(key, ctxt->shadow_ctxt.sh_key_tbl[sh_idx].key, size);
-}
-
-/**
- * Copies the shadow result to the result.
- *
- * Returns 0 on failure
- */
-static void *
-tf_shadow_tcam_res_cpy(struct tf_shadow_tcam_ctxt *ctxt,
- uint8_t *result,
- uint16_t sh_idx,
- uint16_t size)
-{
- if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !result)
- return 0;
-
- if (ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result_size != size)
- return 0;
-
- return memcpy(result,
- ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result,
- size);
-}
-
-/**
- * Using a software based CRC function for now, but will look into using hw
- * assisted in the future.
- */
-static uint32_t
-tf_shadow_tcam_crc32_calc(uint8_t *key, uint32_t len)
-{
- return tf_hash_calc_crc32(key, len);
-}
-
-/**
- * Free the memory associated with the context.
- */
-static void
-tf_shadow_tcam_ctxt_delete(struct tf_shadow_tcam_ctxt *ctxt)
-{
- if (!ctxt)
- return;
-
- tfp_free(ctxt->hash_ctxt.hashtbl);
- tfp_free(ctxt->shadow_ctxt.sh_key_tbl);
- tfp_free(ctxt->shadow_ctxt.sh_res_tbl);
-}
-
-/**
- * The TF Shadow TCAM context is per TCAM and holds all information relating to
- * managing the shadow and search capability. This routine allocated data that
- * needs to be deallocated by the tf_shadow_tcam_ctxt_delete prior when deleting
- * the shadow db.
- */
-static int
-tf_shadow_tcam_ctxt_create(struct tf_shadow_tcam_ctxt *ctxt,
- uint16_t num_entries,
- uint16_t base_addr)
-{
- struct tfp_calloc_parms cparms;
- uint16_t hash_size = 1;
- uint16_t hash_mask;
- int rc;
-
- /* Hash table is a power of two that holds the number of entries */
- if (num_entries > TF_SHADOW_TCAM_ENTRIES_MAX) {
- TFP_DRV_LOG(ERR, "Too many entries for shadow %d > %d\n",
- num_entries,
- TF_SHADOW_TCAM_ENTRIES_MAX);
- return -ENOMEM;
- }
-
- while (hash_size < num_entries)
- hash_size = hash_size << 1;
-
- hash_mask = hash_size - 1;
-
- /* Allocate the hash table */
- cparms.nitems = hash_size;
- cparms.size = sizeof(uint64_t);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->hash_ctxt.hashtbl = cparms.mem_va;
- ctxt->hash_ctxt.hid_mask = hash_mask;
- ctxt->hash_ctxt.hash_entries = hash_size;
-
- /* allocate the shadow tables */
- /* allocate the shadow key table */
- cparms.nitems = num_entries;
- cparms.size = sizeof(struct tf_shadow_tcam_shadow_key_entry);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->shadow_ctxt.sh_key_tbl = cparms.mem_va;
-
- /* allocate the shadow result table */
- cparms.nitems = num_entries;
- cparms.size = sizeof(struct tf_shadow_tcam_shadow_result_entry);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->shadow_ctxt.sh_res_tbl = cparms.mem_va;
-
- ctxt->shadow_ctxt.num_entries = num_entries;
- ctxt->shadow_ctxt.base_addr = base_addr;
-
- return 0;
-error:
- tf_shadow_tcam_ctxt_delete(ctxt);
-
- return -ENOMEM;
-}
-
-/**
- * Get a shadow TCAM context given the db and the TCAM type
- */
-static struct tf_shadow_tcam_ctxt *
-tf_shadow_tcam_ctxt_get(struct tf_shadow_tcam_db *shadow_db,
- enum tf_tcam_tbl_type type)
-{
- if (type >= TF_TCAM_TBL_TYPE_MAX ||
- !shadow_db ||
- !shadow_db->ctxt[type])
- return NULL;
-
- return shadow_db->ctxt[type];
-}
-
-/**
- * Sets the hash entry into the table given the TCAM context, hash bucket
- * handle, and shadow index.
- */
-static inline int
-tf_shadow_tcam_set_hash_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint32_t hb_handle,
- uint16_t sh_idx)
-{
- uint16_t hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle);
- uint16_t be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle);
- uint64_t entry = sh_idx | TF_SHADOW_TCAM_BE_VALID;
-
- if (hid >= ctxt->hash_ctxt.hash_entries)
- return -EINVAL;
-
- ctxt->hash_ctxt.hashtbl[hid] |= entry << (be * 16);
- return 0;
-}
-
-/**
- * Clears the hash entry given the TCAM context and hash bucket handle.
- */
-static inline void
-tf_shadow_tcam_clear_hash_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint32_t hb_handle)
-{
- uint16_t hid, be;
- uint64_t *bucket;
-
- if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hb_handle))
- return;
-
- hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle);
- be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle);
- bucket = &ctxt->hash_ctxt.hashtbl[hid];
-
- switch (be) {
- case 0:
- *bucket = TF_SHADOW_TCAM_BE0_MASK_CLEAR(*bucket);
- break;
- case 1:
- *bucket = TF_SHADOW_TCAM_BE1_MASK_CLEAR(*bucket);
- break;
- case 2:
- *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket);
- break;
- case 3:
- *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket);
- break;
- default:
- /*
- * Since the BE_GET masks non-inclusive bits, this will not
- * happen.
- */
- break;
- }
-}
-
-/**
- * Clears the shadow key and result entries given the TCAM context and
- * shadow index.
- */
-static void
-tf_shadow_tcam_clear_sh_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint16_t sh_idx)
-{
- struct tf_shadow_tcam_shadow_key_entry *sk_entry;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt))
- return;
-
- sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[sh_idx];
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[sh_idx];
-
- /*
- * memset key/result to zero for now, possibly leave the data alone
- * in the future and rely on the valid bit in the hash table.
- */
- memset(sk_entry, 0, sizeof(struct tf_shadow_tcam_shadow_key_entry));
- memset(sr_entry, 0, sizeof(struct tf_shadow_tcam_shadow_result_entry));
-}
-
-/**
- * Binds the allocated tcam index with the hash and shadow tables.
- * The entry will be incomplete until the set has happened with the result
- * data.
- */
-int
-tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms)
-{
- int rc;
- int i;
- uint16_t idx, klen;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_shadow_tcam_shadow_key_entry *sk_entry;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
- uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ];
-
- if (!parms || !TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(parms->hb_handle) ||
- !parms->key || !parms->mask) {
- TFP_DRV_LOG(ERR, "Invalid parms\n");
- return -EINVAL;
- }
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, parms->type);
- if (!ctxt) {
- TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n",
- tf_tcam_tbl_2_str(parms->type));
- return -EINVAL;
- }
-
- memset(tkey, 0, sizeof(tkey));
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, parms->idx);
- klen = parms->key_size;
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) ||
- klen > TF_SHADOW_TCAM_MAX_KEY_SZ) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid len (%d) > %d || oob idx %d\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- klen,
- TF_SHADOW_TCAM_MAX_KEY_SZ, idx);
-
- return -EINVAL;
- }
-
- rc = tf_shadow_tcam_set_hash_entry(ctxt, parms->hb_handle, idx);
- if (rc)
- return -EINVAL;
-
- sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[idx];
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
-
- /*
- * Write the masked key to the table for more efficient comparisons
- * later.
- */
- for (i = 0; i < klen; i++)
- tkey[i] = parms->key[i] & parms->mask[i];
-
- memcpy(sk_entry->key, tkey, klen);
- memcpy(sk_entry->mask, parms->mask, klen);
-
- /* Write the result table */
- sr_entry->key_size = parms->key_size;
- sr_entry->hb_handle = parms->hb_handle;
- sr_entry->refcnt = 1;
-
- return 0;
-}
-
-/**
- * Deletes hash/shadow information if no more references.
- *
- * Returns 0 - The caller should delete the tcam entry in hardware.
- * Returns non-zero - The number of references to the entry
- */
-int
-tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms)
-{
- uint16_t idx;
- uint32_t hb_handle;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_tcam_free_parms *fparms;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (!parms || !parms->fparms) {
- TFP_DRV_LOG(ERR, "Invalid parms\n");
- return -EINVAL;
- }
-
- fparms = parms->fparms;
-
- /*
- * Initialize the reference count to zero. It will only be changed if
- * non-zero.
- */
- fparms->ref_cnt = 0;
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, fparms->type);
- if (!ctxt) {
- TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n",
- tf_tcam_tbl_2_str(fparms->type));
- return 0;
- }
-
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, fparms->idx);
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) {
- TFP_DRV_LOG(DEBUG, "%s %d >= %d\n",
- tf_tcam_tbl_2_str(fparms->type),
- fparms->idx,
- tf_shadow_tcam_sh_num_entries_get(ctxt));
- return 0;
- }
-
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
- if (sr_entry->refcnt <= 1) {
- hb_handle = sr_entry->hb_handle;
- tf_shadow_tcam_clear_hash_entry(ctxt, hb_handle);
- tf_shadow_tcam_clear_sh_entry(ctxt, idx);
- } else {
- sr_entry->refcnt--;
- fparms->ref_cnt = sr_entry->refcnt;
- }
-
- return 0;
-}
-
-int
-tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms)
-{
- uint16_t len;
- uint8_t rcopy;
- uint64_t bucket;
- uint32_t i, hid32;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- uint16_t hid16, hb_idx, hid_mask, shtbl_idx, shtbl_key, be_valid;
- struct tf_tcam_alloc_search_parms *sparms;
- uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ];
- uint32_t be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM;
-
- if (!parms || !parms->sparms) {
- TFP_DRV_LOG(ERR, "tcam search with invalid parms\n");
- return -EINVAL;
- }
-
- memset(tkey, 0, sizeof(tkey));
- sparms = parms->sparms;
-
- /* Initialize return values to invalid */
- sparms->hit = 0;
- sparms->search_status = REJECT;
- parms->hb_handle = 0;
- sparms->ref_cnt = 0;
- /* see if caller wanted the result */
- rcopy = sparms->result && sparms->result_size;
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type);
- if (!ctxt) {
- TFP_DRV_LOG(ERR, "%s Unable to get tcam mgr context\n",
- tf_tcam_tbl_2_str(sparms->type));
- return -EINVAL;
- }
-
- hid_mask = ctxt->hash_ctxt.hid_mask;
-
- len = sparms->key_size;
-
- if (len > TF_SHADOW_TCAM_MAX_KEY_SZ ||
- !sparms->key || !sparms->mask || !len) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid parms %d : %p : %p\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- len,
- sparms->key,
- sparms->mask);
- return -EINVAL;
- }
-
- /* Combine the key and mask */
- for (i = 0; i < len; i++)
- tkey[i] = sparms->key[i] & sparms->mask[i];
-
- /*
- * Calculate the crc32
- * Fold it to create a 16b value
- * Reduce it to fit the table
- */
- hid32 = tf_shadow_tcam_crc32_calc(tkey, len);
- hid16 = (uint16_t)(((hid32 >> 16) & 0xffff) ^ (hid32 & 0xffff));
- hb_idx = hid16 & hid_mask;
-
- bucket = ctxt->hash_ctxt.hashtbl[hb_idx];
-
- if (!bucket) {
- /* empty bucket means a miss and available entry */
- sparms->search_status = MISS;
- parms->hb_handle = TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, 0);
- sparms->idx = 0;
- return 0;
- }
-
- /* Set the avail to max so we can detect when there is an avail entry */
- be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM;
- for (i = 0; i < TF_SHADOW_TCAM_HB_NUM_ELEM; i++) {
- shtbl_idx = (uint16_t)((bucket >> (i * 16)) & 0xffff);
- be_valid = TF_SHADOW_TCAM_BE_IS_VALID(shtbl_idx);
- if (!be_valid) {
- /* The element is avail, keep going */
- be_avail = i;
- continue;
- }
- /* There is a valid entry, compare it */
- shtbl_key = shtbl_idx & ~TF_SHADOW_TCAM_BE_VALID;
- if (!tf_shadow_tcam_key_cmp(ctxt,
- sparms->key,
- sparms->mask,
- shtbl_key,
- sparms->key_size)) {
- /*
- * It matches, increment the ref count if the caller
- * requested allocation and return the info
- */
- if (sparms->alloc)
- ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt++;
-
- sparms->hit = 1;
- sparms->search_status = HIT;
- parms->hb_handle =
- TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, i);
- sparms->idx = TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt,
- shtbl_key);
- sparms->ref_cnt =
- ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt;
-
- /* copy the result, if caller wanted it. */
- if (rcopy &&
- !tf_shadow_tcam_res_cpy(ctxt,
- sparms->result,
- shtbl_key,
- sparms->result_size)) {
- /*
- * Should never get here, possible memory
- * corruption or something unexpected.
- */
- TFP_DRV_LOG(ERR, "Error copying result\n");
- return -EINVAL;
- }
-
- return 0;
- }
- }
-
- /* No hits, return avail entry if exists */
- if (be_avail < TF_SHADOW_TCAM_HB_NUM_ELEM) {
- parms->hb_handle =
- TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, be_avail);
- sparms->search_status = MISS;
- sparms->hit = 0;
- sparms->idx = 0;
- } else {
- sparms->search_status = REJECT;
- }
-
- return 0;
-}
-
-int
-tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms)
-{
- uint16_t idx;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_tcam_set_parms *sparms;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (!parms || !parms->sparms) {
- TFP_DRV_LOG(ERR, "Null parms\n");
- return -EINVAL;
- }
-
- sparms = parms->sparms;
- if (!sparms->result || !sparms->result_size) {
- TFP_DRV_LOG(ERR, "%s:%s No result to set.\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type));
- return -EINVAL;
- }
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type);
- if (!ctxt) {
- /* We aren't tracking this table, so return success */
- TFP_DRV_LOG(DEBUG, "%s Unable to get tcam mgr context\n",
- tf_tcam_tbl_2_str(sparms->type));
- return 0;
- }
-
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, sparms->idx);
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid idx(0x%x)\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- sparms->idx);
- return -EINVAL;
- }
-
- /* Write the result table, the key/hash has been written already */
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
-
- /*
- * If the handle is not valid, the bind was never called. We aren't
- * tracking this entry.
- */
- if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(sr_entry->hb_handle))
- return 0;
-
- if (sparms->result_size > TF_SHADOW_TCAM_MAX_RESULT_SZ) {
- TFP_DRV_LOG(ERR, "%s:%s Result length %d > %d\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- sparms->result_size,
- TF_SHADOW_TCAM_MAX_RESULT_SZ);
- return -EINVAL;
- }
-
- memcpy(sr_entry->result, sparms->result, sparms->result_size);
- sr_entry->result_size = sparms->result_size;
-
- return 0;
-}
-
-int
-tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms)
-{
- struct tf_shadow_tcam_db *shadow_db;
- int i;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- if (!shadow_db) {
- TFP_DRV_LOG(DEBUG, "Shadow db is NULL cannot be freed\n");
- return -EINVAL;
- }
-
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- if (shadow_db->ctxt[i]) {
- tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]);
- tfp_free(shadow_db->ctxt[i]);
- }
- }
-
- tfp_free(shadow_db);
-
- return 0;
-}
-
-/**
- * Allocate the TCAM resources for search and allocate
- *
- */
-int tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms)
-{
- int rc;
- int i;
- uint16_t base;
- struct tfp_calloc_parms cparms;
- struct tf_shadow_tcam_db *shadow_db = NULL;
-
- TF_CHECK_PARMS1(parms);
-
- /* Build the shadow DB per the request */
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_tcam_db);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db = (void *)cparms.mem_va;
-
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- /* If the element didn't request an allocation no need
- * to create a pool nor verify if we got a reservation.
- */
- if (!parms->cfg->alloc_cnt[i]) {
- shadow_db->ctxt[i] = NULL;
- continue;
- }
-
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_tcam_ctxt);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
-
- shadow_db->ctxt[i] = cparms.mem_va;
- base = parms->cfg->base_addr[i];
- rc = tf_shadow_tcam_ctxt_create(shadow_db->ctxt[i],
- parms->cfg->alloc_cnt[i],
- base);
- if (rc)
- goto error;
- }
-
- *parms->shadow_db = (void *)shadow_db;
-
- TFP_DRV_LOG(INFO,
- "TF SHADOW TCAM - initialized\n");
-
- return 0;
-error:
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- if (shadow_db->ctxt[i]) {
- tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]);
- tfp_free(shadow_db->ctxt[i]);
- }
- }
-
- tfp_free(shadow_db);
-
- return -ENOMEM;
-}
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h b/drivers/net/bnxt/tf_core/tf_shadow_tcam.h
deleted file mode 100644
index d6506b219a..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#ifndef _TF_SHADOW_TCAM_H_
-#define _TF_SHADOW_TCAM_H_
-
-#include "tf_core.h"
-
-/**
- * Shadow DB configuration information
- *
- * The shadow configuration is for all tcam table types for a direction
- */
-struct tf_shadow_tcam_cfg_parms {
- /**
- * [in] The number of elements in the alloc_cnt and base_addr
- * For now, it should always be equal to TF_TCAM_TBL_TYPE_MAX
- */
- int num_entries;
- /**
- * [in] Resource allocation count array
- * This array content originates from the tf_session_resources
- * that is passed in on session open
- * Array size is TF_TCAM_TBL_TYPE_MAX
- */
- uint16_t *alloc_cnt;
- /**
- * [in] The base index for each tcam table
- */
- uint16_t base_addr[TF_TCAM_TBL_TYPE_MAX];
-};
-
-/**
- * Shadow TCAM DB creation parameters. The shadow db for this direction
- * is returned
- */
-struct tf_shadow_tcam_create_db_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Configuration information for the shadow db
- */
- struct tf_shadow_tcam_cfg_parms *cfg;
- /**
- * [out] Shadow tcam DB handle
- */
- void **shadow_db;
-};
-
-/**
- * Create the shadow db for a single direction
- *
- * The returned shadow db must be free using the free db API when no longer
- * needed
- */
-int
-tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms);
-
-/**
- * Shadow TCAM free parameters
- */
-struct tf_shadow_tcam_free_db_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
-};
-
-/**
- * Free all resources associated with the shadow db
- */
-int
-tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms);
-
-/**
- * Shadow TCAM bind index parameters
- */
-struct tf_shadow_tcam_bind_index_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in] receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] TCAM table type
- */
- enum tf_tcam_tbl_type type;
- /**
- * [in] index of the entry to program
- */
- uint16_t idx;
- /**
- * [in] struct containing key
- */
- uint8_t *key;
- /**
- * [in] struct containing mask fields
- */
- uint8_t *mask;
- /**
- * [in] key size in bits (if search)
- */
- uint16_t key_size;
- /**
- * [in] The hash bucket handled returned from the search
- */
- uint32_t hb_handle;
-};
-
-/**
- * Binds the allocated tcam index with the hash and shadow tables
- */
-int
-tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms);
-
-/**
- * Shadow TCAM insert parameters
- */
-struct tf_shadow_tcam_insert_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in] The set parms from tf core
- */
- struct tf_tcam_set_parms *sparms;
-};
-
-/**
- * Set the entry into the tcam manager hash and shadow tables
- *
- * The search must have been used prior to setting the entry so that the
- * hash has been calculated and duplicate entries will not be added
- */
-int
-tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms);
-
-/**
- * Shadow TCAM remove parameters
- */
-struct tf_shadow_tcam_remove_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in,out] The set parms from tf core
- */
- struct tf_tcam_free_parms *fparms;
-};
-
-/**
- * Remove the entry from the tcam hash and shadow tables
- *
- * The search must have been used prior to setting the entry so that the
- * hash has been calculated and duplicate entries will not be added
- */
-int
-tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms);
-
-/**
- * Shadow TCAM search parameters
- */
-struct tf_shadow_tcam_search_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in,out] The search parameters from tf core
- */
- struct tf_tcam_alloc_search_parms *sparms;
- /**
- * [out] The hash handle to use for the set
- */
- uint32_t hb_handle;
-};
-
-/**
- * Search for an entry in the tcam hash/shadow tables
- *
- * If there is a miss, but there is room for insertion, the hb_handle returned
- * is used for insertion during the bind index API
- */
-int
-tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms);
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 273f20858b..1c42a6adc7 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -14,20 +14,9 @@
#include "tfp.h"
#include "tf_session.h"
#include "tf_msg.h"
-#include "tf_shadow_tcam.h"
struct tf;
-/**
- * TCAM Shadow DBs
- */
-static void *shadow_tcam_db[TF_DIR_MAX];
-
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
-
int
tf_tcam_bind(struct tf *tfp,
struct tf_tcam_cfg_parms *parms)
@@ -40,9 +29,6 @@ tf_tcam_bind(struct tf *tfp,
struct tf_rm_create_db_parms db_cfg;
struct tf_tcam_resources *tcam_cnt;
struct tf_rm_get_alloc_info_parms ainfo;
- struct tf_shadow_tcam_free_db_parms fshadow;
- struct tf_shadow_tcam_cfg_parms shadow_cfg;
- struct tf_shadow_tcam_create_db_parms shadow_cdb;
uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
@@ -144,44 +130,6 @@ tf_tcam_bind(struct tf *tfp,
}
/* Initialize the TCAM manager. */
- if (parms->shadow_copy) {
- for (d = 0; d < TF_DIR_MAX; d++) {
- memset(&shadow_cfg, 0, sizeof(shadow_cfg));
- memset(&shadow_cdb, 0, sizeof(shadow_cdb));
- /* Get the base addresses of the tcams for tcam mgr */
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- memset(&info, 0, sizeof(info));
-
- if (!parms->resources->tcam_cnt[d].cnt[i])
- continue;
- ainfo.rm_db = tcam_db->tcam_db[d];
- ainfo.subtype = i;
- ainfo.info = &info;
- rc = tf_rm_get_info(&ainfo);
- if (rc)
- goto error;
-
- shadow_cfg.base_addr[i] = info.entry.start;
- }
-
- /* Create the shadow db */
- shadow_cfg.alloc_cnt =
- parms->resources->tcam_cnt[d].cnt;
- shadow_cfg.num_entries = parms->num_elements;
-
- shadow_cdb.shadow_db = &shadow_tcam_db[d];
- shadow_cdb.cfg = &shadow_cfg;
- rc = tf_shadow_tcam_create_db(&shadow_cdb);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "TCAM MGR DB creation failed "
- "rc=%d\n", rc);
- goto error;
- }
- }
- shadow_init = 1;
- }
-
TFP_DRV_LOG(INFO,
"TCAM - initialized\n");
@@ -193,19 +141,10 @@ tf_tcam_bind(struct tf *tfp,
fparms.rm_db = tcam_db->tcam_db[i];
/* Ignoring return here since we are in the error case */
(void)tf_rm_free_db(tfp, &fparms);
-
- if (parms->shadow_copy) {
- fshadow.shadow_db = shadow_tcam_db[i];
- tf_shadow_tcam_free_db(&fshadow);
- shadow_tcam_db[i] = NULL;
- }
-
tcam_db->tcam_db[i] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL);
}
- shadow_init = 0;
-
return rc;
}
@@ -217,7 +156,6 @@ tf_tcam_unbind(struct tf *tfp)
struct tf_rm_free_db_parms fparms;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
- struct tf_shadow_tcam_free_db_parms fshadow;
TF_CHECK_PARMS1(tfp);
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
@@ -237,18 +175,8 @@ tf_tcam_unbind(struct tf *tfp)
return rc;
tcam_db->tcam_db[i] = NULL;
-
- if (shadow_init) {
- memset(&fshadow, 0, sizeof(fshadow));
-
- fshadow.shadow_db = shadow_tcam_db[i];
- tf_shadow_tcam_free_db(&fshadow);
- shadow_tcam_db[i] = NULL;
- }
}
- shadow_init = 0;
-
return 0;
}
@@ -346,7 +274,6 @@ tf_tcam_free(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms;
uint16_t num_slices = 1;
int allocated = 0;
- struct tf_shadow_tcam_remove_parms shparms;
int i;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
@@ -416,35 +343,6 @@ tf_tcam_free(struct tf *tfp,
return -EINVAL;
}
- /*
- * The Shadow mgmt, if enabled, determines if the entry needs
- * to be deleted.
- */
- if (shadow_init) {
- shparms.shadow_db = shadow_tcam_db[parms->dir];
- shparms.fparms = parms;
- rc = tf_shadow_tcam_remove(&shparms);
- if (rc) {
- /*
- * Should not get here, log it and let the entry be
- * deleted.
- */
- TFP_DRV_LOG(ERR, "%s: Shadow free fail, "
- "type:%d index:%d deleting the entry.\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- } else {
- /*
- * If the entry still has references, just return the
- * ref count to the caller. No need to remove entry
- * from rm or hw
- */
- if (parms->ref_cnt >= 1)
- return rc;
- }
- }
-
for (i = 0; i < num_slices; i++) {
/* Free requested element */
memset(&fparms, 0, sizeof(fparms));
@@ -488,128 +386,6 @@ tf_tcam_free(struct tf *tfp,
return 0;
}
-int
-tf_tcam_alloc_search(struct tf *tfp,
- struct tf_tcam_alloc_search_parms *parms)
-{
- struct tf_shadow_tcam_search_parms sparms;
- struct tf_shadow_tcam_bind_index_parms bparms;
- struct tf_tcam_free_parms fparms;
- struct tf_tcam_alloc_parms aparms;
- uint16_t num_slice_per_row = 1;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int rc;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tcam_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: TCAM Shadow not initialized for %s\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type));
- return -EINVAL;
- }
-
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Need to retrieve row size etc */
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- parms->type,
- parms->key_size,
- &num_slice_per_row);
- if (rc)
- return rc;
-
- /*
- * Prep the shadow search, reusing the parms from original search
- * instead of copying them. Shadow will update output in there.
- */
- memset(&sparms, 0, sizeof(sparms));
- sparms.sparms = parms;
- sparms.shadow_db = shadow_tcam_db[parms->dir];
-
- rc = tf_shadow_tcam_search(&sparms);
- if (rc)
- return rc;
-
- /*
- * The app didn't request us to alloc the entry, so return now.
- * The hit should have been updated in the original search parm.
- */
- if (!parms->alloc || parms->search_status != MISS)
- return rc;
-
- /* Caller desires an allocate on miss */
- if (dev->ops->tf_dev_alloc_tcam == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
- memset(&aparms, 0, sizeof(aparms));
- aparms.dir = parms->dir;
- aparms.type = parms->type;
- aparms.key_size = parms->key_size;
- aparms.priority = parms->priority;
- rc = dev->ops->tf_dev_alloc_tcam(tfp, &aparms);
- if (rc)
- return rc;
-
- /* Successful allocation, attempt to add it to the shadow */
- memset(&bparms, 0, sizeof(bparms));
- bparms.dir = parms->dir;
- bparms.shadow_db = shadow_tcam_db[parms->dir];
- bparms.type = parms->type;
- bparms.key = parms->key;
- bparms.mask = parms->mask;
- bparms.key_size = parms->key_size;
- bparms.idx = aparms.idx;
- bparms.hb_handle = sparms.hb_handle;
- rc = tf_shadow_tcam_bind_index(&bparms);
- if (rc) {
- /* Error binding entry, need to free the allocated idx */
- if (dev->ops->tf_dev_free_tcam == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- fparms.dir = parms->dir;
- fparms.type = parms->type;
- fparms.idx = aparms.idx;
- rc = dev->ops->tf_dev_free_tcam(tfp, &fparms);
- if (rc)
- return rc;
- }
-
- /* Add the allocated index to output and done */
- parms->idx = aparms.idx;
-
- return 0;
-}
-
int
tf_tcam_set(struct tf *tfp __rte_unused,
struct tf_tcam_set_parms *parms __rte_unused)
@@ -619,7 +395,6 @@ tf_tcam_set(struct tf *tfp __rte_unused,
struct tf_dev_info *dev;
struct tf_rm_is_allocated_parms aparms;
struct tf_rm_get_hcapi_parms hparms;
- struct tf_shadow_tcam_insert_parms iparms;
uint16_t num_slice_per_row = 1;
int allocated = 0;
struct tcam_rm_db *tcam_db;
@@ -705,24 +480,6 @@ tf_tcam_set(struct tf *tfp __rte_unused,
strerror(-rc));
return rc;
}
-
- /* Successfully added to hw, now for shadow if enabled. */
- if (!shadow_init || !shadow_tcam_db[parms->dir])
- return 0;
-
- iparms.shadow_db = shadow_tcam_db[parms->dir];
- iparms.sparms = parms;
- rc = tf_shadow_tcam_insert(&iparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: %s: Entry %d set failed, rc:%s",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- return rc;
- }
-
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index b1e7a92b0b..0ed2250464 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -27,14 +27,6 @@ struct tf_tcam_cfg_parms {
* TCAM configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tcam_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -91,11 +83,6 @@ struct tf_tcam_free_parms {
* [in] Index to free
*/
uint16_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
@@ -322,10 +309,8 @@ int tf_tcam_alloc(struct tf *tfp,
struct tf_tcam_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Free's the requested table type and returns it to the DB.
+ * If refcount goes to 0 then its returned to the table type DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
@@ -340,25 +325,6 @@ int tf_tcam_alloc(struct tf *tfp,
int tf_tcam_free(struct tf *tfp,
struct tf_tcam_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tcam_alloc_search(struct tf *tfp,
- struct tf_tcam_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index c1b9be0755..7d9de7c764 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -59,12 +59,10 @@ tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type)
return "sp_tcam";
case TF_TCAM_TBL_TYPE_CT_RULE_TCAM:
return "ct_rule_tcam";
-#ifdef TF_TCAM_SHARED
case TF_TCAM_TBL_TYPE_WC_TCAM_HIGH:
return "wc_tcam_hi";
case TF_TCAM_TBL_TYPE_WC_TCAM_LOW:
return "wc_tcam_lo";
-#endif
default:
return "Invalid tcam table type";
}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 1ee21fceef..1bb38399e4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -461,7 +461,6 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
return rc;
}
- parms.shadow_copy = true;
parms.bp = bp;
if (app_id == 0)
parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
@@ -550,8 +549,6 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
}
- params.shadow_copy = true;
-
rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 02/11] net/bnxt: update bnxt hsi structure
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 01/11] net/bnxt: remove deprecated features Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
` (9 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Kishore Padmanabha
[-- Attachment #1: Type: text/plain, Size: 271515 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Sync hsi structure to latest revision.
New version is 1.10.2.138
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 +++++++++++++++++++++---
1 file changed, 5128 insertions(+), 595 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 380dec4d3e..9afdd056ce 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2022 Broadcom Inc.
+ * Copyright (c) 2014-2023 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -442,6 +442,8 @@ struct cmd_nums {
#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
#define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
#define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
+ #define HWRM_PORT_CFG UINT32_C(0xdc)
+ #define HWRM_PORT_QCFG UINT32_C(0xdd)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
@@ -480,9 +482,7 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
/* Experimental */
#define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
- /* Experimental */
#define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
- /* Experimental */
#define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
/* Experimental */
#define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
@@ -678,6 +678,17 @@ struct cmd_nums {
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
/* The is the new API to query backing store capabilities. */
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
+ /* To query doorbell pacing NQ id list configuration. */
+ #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)
+ /*
+ * To notify the firmware that recovery cycle has been
+ * completed by host function drivers.
+ */
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)
+ /* Configures SyncE configurations. */
+ #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)
+ /* Queries SyncE configurations. */
+ #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
@@ -747,6 +758,8 @@ struct cmd_nums {
* to run.
*/
#define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
+ /* Queries the generic stats */
+ #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)
/* Experimental */
#define HWRM_TF UINT32_C(0x2bc)
/* Experimental */
@@ -774,6 +787,10 @@ struct cmd_nums {
/* Experimental */
#define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
/* Experimental */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)
+ /* Experimental */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)
+ /* Experimental */
#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
/* Experimental */
#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
@@ -819,6 +836,54 @@ struct cmd_nums {
#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
/* Experimental */
#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
+ /* TruFlow command to check firmware table scope capabilities. */
+ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)
+ /* TruFlow command to allocate a table scope ID and create the pools. */
+ #define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)
+ /* TruFlow command to configure the table scope memory. */
+ #define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)
+ /* TruFlow command to deconfigure a table scope memory. */
+ #define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)
+ /* TruFlow command to add a FID to a table scope. */
+ #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)
+ /* TruFlow command to remove a FID from a table scope. */
+ #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)
+ /* TruFlow command to allocate a table scope pool. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)
+ /* TruFlow command to free a table scope pool. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)
+ /* Experimental */
+ #define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)
+ /* Experimental */
+ #define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)
+ /* TruFlow command to allocate an index table entry */
+ #define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)
+ /* TruFlow command to allocate and set an index table entry */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)
+ /* TruFlow command to set an index table entry */
+ #define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)
+ /* TruFlow command to get an index table entry */
+ #define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)
+ /* TruFlow command to free an index table entry */
+ #define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)
+ /* TruFlow command to allocate resources for a global id. */
+ #define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)
+ /* TruFlow command to set TCAM entry. */
+ #define HWRM_TFC_TCAM_SET UINT32_C(0x393)
+ /* TruFlow command to get TCAM entry. */
+ #define HWRM_TFC_TCAM_GET UINT32_C(0x394)
+ /* TruFlow command to allocate a TCAM entry. */
+ #define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)
+ /* TruFlow command allocate and set TCAM entry. */
+ #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)
+ /* TruFlow command to free a TCAM entry. */
+ #define HWRM_TFC_TCAM_FREE UINT32_C(0x397)
/* Experimental */
#define HWRM_SV UINT32_C(0x400)
/* Experimental */
@@ -1089,8 +1154,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 2
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 83
-#define HWRM_VERSION_STR "1.10.2.83"
+#define HWRM_VERSION_RSVD 138
+#define HWRM_VERSION_STR "1.10.2.138"
/****************
* hwrm_ver_get *
@@ -1345,6 +1410,7 @@ struct hwrm_ver_get_output {
* If set to 1, firmware is capable to support flow aging.
* If set to 0, firmware is not capable to support flow aging.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
@@ -1353,6 +1419,7 @@ struct hwrm_ver_get_output {
* Meter drop counters and EEM counters.
* If set to 0, firmware is not capable to support advanced flow counters.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
UINT32_C(0x400)
@@ -1362,6 +1429,7 @@ struct hwrm_ver_get_output {
* If set to 0, firmware is not capable to support the use of the
* CFA EEM feature.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
UINT32_C(0x800)
@@ -1996,7 +2064,7 @@ struct cfa_bds_event_collect_cmd_data_msg {
uint64_t host_address;
} __rte_packed;
-/* ce_bds_add_data_msg (size:512b/64B) */
+/* ce_bds_add_data_msg (size:576b/72B) */
struct ce_bds_add_data_msg {
uint32_t version_algorithm_kid_opcode;
/*
@@ -2050,26 +2118,14 @@ struct ce_bds_add_data_msg {
(UINT32_C(0x1) << 28)
#define CE_BDS_ADD_DATA_MSG__LAST \
CE_BDS_ADD_DATA_MSG__TLS1_3
- uint8_t cmd_type_ctx_kind;
- /*
- * Command Type in the TLS header. HW will provide registers that
- * converts the 3b encoded command type to 8b of actual command
- * type in the TLS Header. This field is initialized/updated by
- * this "KTLS crypto add" mid-path command.
- */
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
- /* Application */
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
- CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
+ uint8_t ctx_kind;
/* This field selects the context kind for the request. */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8)
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0
/* Crypto key transmit context */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)
/* Crypto key receive context */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \
CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX
uint8_t unused0[3];
@@ -2083,8 +2139,8 @@ struct ce_bds_add_data_msg {
* is zero padded to 12B and then xor'ed with the 4B of salt to generate
* the 12B of IV. This value is initialized by this mid-path command.
*/
- uint32_t salt;
- uint32_t unused1;
+ uint8_t salt[4];
+ uint8_t unused1[4];
/*
* This field keeps track of the TCP sequence number that is expected as
* the first byte in the next TCP packet. This field is calculated by HW
@@ -2111,16 +2167,21 @@ struct ce_bds_add_data_msg {
* the field after that for every record processed as it parses the TCP
* packet.
*/
- uint32_t record_seq_num[2];
+ uint64_t record_seq_num;
/*
* Key used for encrypting or decrypting TLS records. The Key is
* exchanged during the hand-shake protocol by the client-server and
* provided to HW through this mid-path BD.
*/
- uint32_t session_key[8];
+ uint8_t session_key[32];
+ /*
+ * Additional IV that is exchanged as part of sessions setup between
+ * the two end points. This field is used for TLS1.3 only.
+ */
+ uint8_t addl_iv[8];
} __rte_packed;
-/* ce_bds_delete_data_msg (size:64b/8B) */
+/* ce_bds_delete_data_msg (size:32b/4B) */
struct ce_bds_delete_data_msg {
uint32_t kid_opcode_ctx_kind;
/*
@@ -2160,7 +2221,6 @@ struct ce_bds_delete_data_msg {
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \
CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX
- uint32_t unused0;
} __rte_packed;
/* ce_bds_resync_resp_ack_msg (size:128b/16B) */
@@ -2213,7 +2273,7 @@ struct ce_bds_resync_resp_ack_msg {
* it has found since sending the resync request, update the context and
* resume decrypting records.
*/
- uint32_t resync_record_seq_num[2];
+ uint64_t resync_record_seq_num;
} __rte_packed;
/* ce_bds_resync_resp_nack_msg (size:64b/8B) */
@@ -2288,6 +2348,19 @@ struct crypto_presync_bd_cmd {
*/
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
UINT32_C(0x1)
+ /*
+ * When packet with an authentication TAG is lost in the network,
+ * During retransmission Device driver will post the entire record for
+ * the hardware to recalculate the TAG. Hardware is set to retransmit
+ * only portions of the record, it does so by looking at the Header
+ * TCP Sequence Number and Start TCP Sequence Number. However, there
+ * is a case where the header packet gets dropped in the stack for ex
+ * BPF packet filter and it is impossible for the Hardware to
+ * determine if this is a case of full replay for only the TAG
+ * generation.
+ */
+ #define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN \
+ UINT32_C(0x2)
uint8_t unused0;
uint16_t unused1;
/*
@@ -2331,7 +2404,7 @@ struct crypto_presync_bd_cmd {
* the first TLS header. When subsequent TLS Headers are detected, the
* value is extracted from packet.
*/
- uint32_t explicit_nonce[2];
+ uint8_t explicit_nonce[8];
/*
* This is sequence number for the TLS record in a particular session. In
* TLS1.2, record sequence number is part of the Associated Data (AD) in
@@ -2343,7 +2416,110 @@ struct crypto_presync_bd_cmd {
* delivering more retransmission instruction will also update this
* field.
*/
- uint32_t record_seq_num[2];
+ uint64_t record_seq_num;
+} __rte_packed;
+
+/* ce_bds_quic_add_data_msg (size:832b/104B) */
+struct ce_bds_quic_add_data_msg {
+ uint32_t ver_algo_kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0
+ /*
+ * This is the add command. Using this opcode, Host Driver can add
+ * information required for QUIC processing. The information is
+ * updated in the CFCK context.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated QUIC offloaded connection.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK \
+ UINT32_C(0xfffff0)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4
+ /* Algorithm used for encryption and decryption. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK \
+ UINT32_C(0xf000000)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24
+ /* AES_GCM_128 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
+ (UINT32_C(0x1) << 24)
+ /* AES_GCM_256 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
+ (UINT32_C(0x2) << 24)
+ /* Chacha20 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 \
+ (UINT32_C(0x3) << 24)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20
+ /* Version number of QUIC connection. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK \
+ UINT32_C(0xf0000000)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28
+ /* TLS1.2 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 \
+ (UINT32_C(0x0) << 28)
+ /* TLS1.3 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 \
+ (UINT32_C(0x1) << 28)
+ /* DTLS1.2 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 \
+ (UINT32_C(0x2) << 28)
+ /* DTLS1.2 for RoCE Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE \
+ (UINT32_C(0x3) << 28)
+ /* QUIC Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__QUIC \
+ (UINT32_C(0x4) << 28)
+ #define CE_BDS_QUIC_ADD_DATA_MSG__LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG__QUIC
+ uint32_t ctx_kind_dcid_width_key_phase;
+ /* Key phase. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)
+ /* Destination connection ID width. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1
+ /* This field selects the context kind for the request. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6
+ /* QUIC key transmit context */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX \
+ (UINT32_C(0x14) << 6)
+ /* QUIC key receive context */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX \
+ (UINT32_C(0x15) << 6)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX
+ uint32_t unused_0[2];
+ /*
+ * Least-significant 64 bits (of 96) of additional IV that is
+ * exchanged as part of sessions setup between the two end
+ * points for QUIC operations.
+ */
+ uint64_t quic_iv_lo;
+ /*
+ * Most-significant 32 bits (of 96) of additional IV that is
+ * exchanged as part of sessions setup between the two end
+ * points for QUIC operations.
+ */
+ uint32_t quic_iv_hi;
+ uint32_t unused_1;
+ /*
+ * Key used for encrypting or decrypting records. The Key is exchanged
+ * as part of sessions setup between the two end points through this
+ * mid-path BD.
+ */
+ uint32_t session_key[8];
+ /* Header protection key. */
+ uint32_t hp_key[8];
+ /* Packet number associated with the QUIC connection. */
+ uint64_t pkt_number;
} __rte_packed;
/* bd_base (size:64b/8B) */
@@ -3665,7 +3841,7 @@ struct cfa_dma128b_data_msg {
/* ce_cmpls_cmp_data_msg (size:128b/16B) */
struct ce_cmpls_cmp_data_msg {
- uint16_t status_subtype_type;
+ uint16_t client_subtype_type;
/*
* This field indicates the exact type of the completion. By
* convention, the LSB identifies the length of the record in 16B
@@ -3678,82 +3854,82 @@ struct ce_cmpls_cmp_data_msg {
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6
/*
* This value indicates the CE sub-type operation that is being
* completed.
*/
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8
/* Completion Response for a Solicited Command. */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)
/* Error Completion (Unsolicited). */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)
/* Re-Sync Completion (Unsolicited) */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12
+ /* TX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE \
+ (UINT32_C(0x0) << 12)
+ /* RX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE \
+ (UINT32_C(0x1) << 12)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
+ CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE
+ uint16_t status;
/* This value indicates the status for the command. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0
/* Completed without error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
- (UINT32_C(0x0) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)
/* CFCK load error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
- (UINT32_C(0x1) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)
/* FID check error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
- (UINT32_C(0x2) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)
/* Context kind / MP version mismatch error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \
- (UINT32_C(0x3) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)
/* Unsupported Destination Connection ID Length. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \
- (UINT32_C(0x4) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)
/*
* Invalid MP Command [anything other than ADD or DELETE
* triggers this for QUIC].
*/
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \
- (UINT32_C(0x5) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR
- uint8_t unused0;
- uint8_t mp_clients;
- #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
- #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
- /*
- * This field represents the Mid-Path client that generated the
- * completion.
- */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
- /* TX crypto engine block. */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
- /* RX crypto engine block. */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
- CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4
/*
* This is a copy of the opaque field from the mid path BD of this
* command.
*/
uint32_t opaque;
- /* */
- uint32_t kid_v;
+ uint32_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes will
* write 1. The odd passes will write 0.
*/
- #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1
+ uint32_t kid;
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
- #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
- #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
- uint32_t unused2;
+ #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)
+ #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20
} __rte_packed;
/* cmpl_base (size:128b/16B) */
@@ -3783,16 +3959,11 @@ struct cmpl_base {
* Completion of coalesced TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
- /*
- * TX L2 PTP completion:
- * Completion of PTP TX packet. Length = 32B
- */
- #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
/*
* TX L2 Packet Timestamp completion:
* Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
- #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4)
+ #define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
/*
* RX L2 TPA Start V2 Completion:
* Completion of and L2 RX packet. Length = 32B
@@ -4173,47 +4344,79 @@ struct tx_cmpl_coal {
#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
} __rte_packed;
-/* tx_cmpl_ptp (size:128b/16B) */
-struct tx_cmpl_ptp {
- uint16_t flags_type;
+/* tx_cmpl_packet_timestamp (size:128b/16B) */
+struct tx_cmpl_packet_timestamp {
+ uint16_t ts_sub_ns_flags_type;
/*
- * This field indicates the exact type of the completion.
- * By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
- * records.
+ * This field indicates the exact type of the completion. By
+ * convention, the LSB identifies the length of the record in 16B
+ * units. Even values indicate 16B records. Odd values indicate
+ * 32B records.
*/
- #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
- #define TX_CMPL_PTP_TYPE_SFT 0
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0
/*
- * TX L2 PTP completion:
- * Completion of TX packet. Length = 32B
+ * TX L2 Packet Timestamp completion:
+ * Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
- #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
- #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
- #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
- #define TX_CMPL_PTP_FLAGS_SFT 6
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6
/*
- * When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
- * error_flags.
+ * When this bit is '1', it indicates a packet that has an error
+ * of some type. Type of error is indicated in error_flags.
*/
- #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)
/*
- * When this bit is '1', it indicates that the packet completed
- * was transmitted using the push acceleration data provided
- * by the driver. When this bit is '0', it indicates that the
- * packet had not push acceleration data written or was executed
- * as a normal packet even though push data was provided.
+ * This field indicates the TX packet timestamp type that is
+ * represented by a TX Packet Timestamp Completion. Note that
+ * this field is invalid if the timestamp_invalid_error flag
+ * is set.
*/
- #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
- /* unused1 is 16 b */
- uint16_t unused_0;
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)
+ /* The packet timestamp came from PM. */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM \
+ (UINT32_C(0x0) << 7)
+ /* The packet timestamp came from PA. */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA \
+ (UINT32_C(0x1) << 7)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA
+ /*
+ * This flag indicates that the timestamp should have come from PM,
+ * but came instead from PA because all PM timestamp resources were
+ * in use. This can occur in the following circumstances:
+ * 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet
+ * but PA could not request a PM timestamp
+ * 2. The BD specified ts_2cmpl_pm, but PA could not request a PM
+ * timestamp
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)
+ /*
+ * For 2-step PTP timestamps, bits[3:0] of this field represent the
+ * sub-nanosecond portion of the packet timestamp, returned from PM
+ * for 2-step PTP timestamps. For PA timestamps, this field also
+ * represents the sub-nanosecond portion of the packet timestamp;
+ * however, due to synchronization uncertainties, the accuracy of
+ * PA timestamps is limited to approximately +/- 4 ns. Therefore
+ * this field is of dubious value for PA timestamps.
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)
+ #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12
+ /*
+ * This is bits [47:32] of the nanoseconds portion of the packet
+ * timestamp, returned from PM for 2-step PTP timestamps or from
+ * PA for PA timestamps. This field is in units of 2^32 ns.
+ */
+ uint16_t ts_ns_mid;
/*
* This is a copy of the opaque field from the first TX BD of this
- * transmitted packet. Note that, if the packet was described by a short
- * CSO or short CSO inline BD, then the 16-bit opaque field from the
- * short CSO BD will appear in the bottom 16 bits of this field.
+ * transmitted packet. Note that, if the packet was described by a
+ * short CSO or short CSO inline BD, then the 16-bit opaque field
+ * from the short CSO BD will appear in the bottom 16 bits of this
+ * field.
*/
uint32_t opaque;
uint16_t errors_v;
@@ -4222,95 +4425,103 @@ struct tx_cmpl_ptp {
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define TX_CMPL_PTP_V UINT32_C(0x1)
- #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
- #define TX_CMPL_PTP_ERRORS_SFT 1
+ #define TX_CMPL_PACKET_TIMESTAMP_V \
+ UINT32_C(0x1)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1
/*
- * This error indicates that there was some sort of problem
- * with the BDs for the packet.
+ * This field was previously used to indicate fatal errors, which
+ * now result in aborting and bringing down the ring. This field
+ * is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
- /* No error */
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK \
+ UINT32_C(0xe)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1
+ /* No error. */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR \
(UINT32_C(0x0) << 1)
- /*
- * Bad Format:
- * BDs were not formatted correctly.
- */
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
+ /* Deprecated. */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT \
(UINT32_C(0x2) << 1)
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
- TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT
/*
- * When this bit is '1', it indicates that the length of
- * the packet was zero. No packet was transmitted.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
- /*
- * When this bit is '1', it indicates that the packet
- * was longer than the programmed limit in TDI. No
- * packet was transmitted.
- */
- #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT \
+ UINT32_C(0x10)
/*
- * When this bit is '1', it indicates that one or more of the
- * BDs associated with this packet generated a PCI error.
- * This probably means the address was not valid.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH \
+ UINT32_C(0x20)
/*
- * When this bit is '1', it indicates that the packet was longer
- * than indicated by the hint. No packet was transmitted.
+ * When this bit is '1', it indicates that one or more of the BDs
+ * associated with this packet generated a PCI error when accessing
+ * header/payload data from host memory. It most likely indicates
+ * that the address was not valid. Note that this bit has no meaning
+ * for the timestamp completion and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR \
+ UINT32_C(0x40)
/*
- * When this bit is '1', it indicates that the packet was
- * dropped due to Poison TLP error on one or more of the
- * TLPs in the PXP completion.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT \
+ UINT32_C(0x80)
/*
- * When this bit is '1', it indicates that the packet was dropped due
- * to a transient internal error in TDC. The packet or LSO can be
- * retried and may transmit successfully on a subsequent attempt.
+ * When this bit is '1', it indicates that the packet was dropped
+ * due to Poison TLP error on one or more of the TLPs in one or more
+ * of the associated PXP completion(s) when accessing header/payload
+ * data from host memory. Note that this bit has no meaning for the
+ * timestamp completion, and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR \
+ UINT32_C(0x100)
/*
- * When this bit is '1', it was not possible to collect a a timestamp
- * for a PTP completion, in which case the timestamp_hi and
- * timestamp_lo fields are invalid. When this bit is '0' for a PTP
- * completion, the timestamp_hi and timestamp_lo fields are valid.
- * RJRN will copy the value of this bit into the field of the same
- * name in all TX completions, regardless of whether such
- * completions are PTP completions or other TX completions.
+ * When this bit is '1', it indicates that the packet was dropped
+ * due to a transient internal error in TDC. The packet or LSO can
+ * be retried and may transmit successfully on a subsequent attempt.
+ * Note that this bit has no meaning for the timestamp completion
+ * and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
- /* unused2 is 16 b */
- uint16_t unused_1;
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR \
+ UINT32_C(0x200)
/*
- * This is timestamp value (lower 32bits) read from PM for the PTP
- * timestamp enabled packet.
- */
- uint32_t timestamp_lo;
-} __rte_packed;
-
-/* tx_cmpl_ptp_hi (size:128b/16B) */
-struct tx_cmpl_ptp_hi {
+ * When this bit is '1', it was not possible to collect a timestamp
+ * for a timestamp completion, in which case the ts_ns and ts_sub_ns
+ * fields are invalid. When this bit is '0' in a timestamp
+ * completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields
+ * are valid. Note that this bit has meaning only for the timestamp
+ * completion. For types other than the timestamp completion, this
+ * bit will always be '0'.
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR \
+ UINT32_C(0x400)
/*
- * This is timestamp value (lower 32bits) read from PM for the PTP
- * timestamp enabled packet.
+ * When this bit is '1', it indicates that a Timed Transmit
+ * SO-TXTIME packet violated the max_ttx_overtime constraint i.e.,
+ * the time the packet was processed for transmission in TWE was
+ * later than the time given by (TimedTx_BD.tx_time +
+ * max_ttx_overtime) and as result, the packet was dropped.
+ * Note that max_ttx_overtime is a global configuration in TWE.
+ * Note that this bit has no meaning in a timestamp completion,
+ * and will always be '0'.
*/
- uint16_t timestamp_hi[3];
- uint16_t reserved16;
- uint64_t v2;
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR \
+ UINT32_C(0x800)
+ /* unused2 is 16 b */
+ uint16_t unused_2;
/*
- * This value is written by the NIC such that it will be different for
- * each pass through the completion queue.
- * The even passes will write 1.
- * The odd passes will write 0.
+ * This is bits [31:0] of the nanoseconds portion of the packet
+ * timestamp, returned from PM for 2-step PTP timestamp or from
+ * PA for PA timestamps. This field is in units of ns.
*/
- #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
+ uint32_t ts_ns_lo;
} __rte_packed;
/* rx_pkt_cmpl (size:128b/16B) */
@@ -9314,9 +9525,31 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \
UINT32_C(0x46)
+ /*
+ * An event from firmware indicating that the RSS capabilities have
+ * changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE \
+ UINT32_C(0x47)
+ /*
+ * An event from firmware indicating that list of nq ids used for
+ * doorbell pacing DBQ event notification has been updated. The driver
+ * needs to take appropriate action and retrieve the new list when this
+ * event is received from the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \
+ UINT32_C(0x48)
+ /*
+ * An event from firmware indicating that hardware ran into an error
+ * while trying to read the host based doorbell copy region. The driver
+ * needs to take the appropriate action and maintain the corresponding
+ * doorbell copy region.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \
+ UINT32_C(0x49)
/* Maximum Registrable event id. */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
- UINT32_C(0x47)
+ UINT32_C(0x4a)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -11828,6 +12061,195 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold {
uint32_t event_data1;
} __rte_packed;
+/* hwrm_async_event_cmpl_rss_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_rss_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that the RSS capabilities have changed. The driver will need
+ * to query hwrm_vnic_qcaps.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE \
+ UINT32_C(0x47)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */
+struct hwrm_async_event_cmpl_doorbell_pacing_nq_update {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * An event from firmware indicating that list of nq ids used for
+ * doorbell pacing DBQ event notification has been updated. The driver
+ * needs to take appropriate action and retrieve the new list when this
+ * event is received from the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \
+ UINT32_C(0x48)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that hardware ran into an error while trying to read the host
+ * based doorbell copy region. The driver will take the appropriate
+ * action to maintain the corresponding functions doorbell copy
+ * region in the correct format.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \
+ UINT32_C(0x49)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_SFT \
+ 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Indicates that there is an error while reading the doorbell copy
+ * regions.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK \
+ UINT32_C(0xf)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * SQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * RQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * SRQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * CQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \
+ UINT32_C(0x8)
+} __rte_packed;
+
/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
struct hwrm_async_event_cmpl_fw_trace_msg {
uint16_t type;
@@ -12385,6 +12807,14 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
+ /*
+ * The epoch value to be sent from firmware to the driver to track
+ * a doorbell recovery cycle.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK \
+ UINT32_C(0xffffff00)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \
+ 8
} __rte_packed;
/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */
@@ -12516,8 +12946,8 @@ struct metadata_base_msg {
#define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
/*
* This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * the state of the receive context, the meta-data will carry
+ * different information.
*/
#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
/*
@@ -12525,12 +12955,21 @@ struct metadata_base_msg {
* record that it is requesting a resync on in the meta data.
*/
#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
+ /* This setting is used for QUIC packets. */
+ #define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3)
+ /*
+ * This setting is used for crypto packets with an unsupported
+ * protocol.
+ */
+ #define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f)
#define METADATA_BASE_MSG_MD_TYPE_LAST \
- METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+ METADATA_BASE_MSG_MD_TYPE_ILLEGAL
/*
- * This field indicates where the next metadata block starts. It is
- * counted in 16B units. A value of zero indicates that there is no
- * metadata.
+ * This field indicates where the next metadata block starts, relative
+ * to the current metadata block. It is the offset to the next metadata
+ * header, counted in 16B units. A value of zero indicates that there is
+ * no additional metadata, and that the current metadata block is the
+ * last one.
*/
#define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
#define METADATA_BASE_MSG_LINK_SFT 5
@@ -12544,11 +12983,12 @@ struct tls_metadata_base_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT \
+ 0
/*
- * This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * This setting is used when packets are coming in-order. Depending
+ * on the state of the receive context, the meta-data will carry
+ * different information.
*/
#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
UINT32_C(0x1)
@@ -12567,11 +13007,13 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_BASE_MSG_LINK_SFT 5
+ #define TLS_METADATA_BASE_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_BASE_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_BASE_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12584,7 +13026,8 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12610,12 +13053,13 @@ struct tls_metadata_base_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
/*
* This enumeration states that there is at least one tag in the
@@ -12638,13 +13082,61 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_BASE_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_BASE_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -12661,11 +13153,12 @@ struct tls_metadata_insync_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT \
+ 0
/*
* This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * the state of the receive context, the meta-data will carry
+ * different information.
*/
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
UINT32_C(0x1)
@@ -12678,11 +13171,13 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
+ #define TLS_METADATA_INSYNC_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12695,7 +13190,8 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12721,12 +13217,13 @@ struct tls_metadata_insync_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
/*
* This enumeration states that there is at least one tag in the
@@ -12749,13 +13246,61 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -12764,14 +13309,14 @@ struct tls_metadata_insync_msg {
#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
/*
- * This field is only valid when md_type is set to tls_insync. This field
- * indicates the offset within the current TCP packet where the TLS header
- * starts. If there are multiple TLS headers in the packet, this provides
- * the offset of the last TLS header.
+ * This field is only valid when md_type is set to tls_insync. This
+ * field indicates the offset within the current TCP packet where the
+ * TLS header starts. If there are multiple TLS headers in the packet,
+ * this provides the offset of the last TLS header.
*
- * The field is calculated by subtracting TCP sequence number of the first
- * byte of the TCP payload of the packet from the TCP sequence number of
- * the last TLS header in the packet.
+ * The field is calculated by subtracting TCP sequence number of the
+ * first byte of the TCP payload of the packet from the TCP sequence
+ * number of the last TLS header in the packet.
*/
uint16_t tls_header_offset;
/*
@@ -12787,7 +13332,7 @@ struct tls_metadata_insync_msg {
* not decrypt every packet and authenticate the record. Partial GHASH is
* only sent out with packet having the TAG field.
*/
- uint64_t partial_ghash;
+ uint8_t partial_ghash[8];
} __rte_packed;
/* tls_metadata_resync_msg (size:256b/32B) */
@@ -12796,7 +13341,8 @@ struct tls_metadata_resync_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT \
+ 0
/*
* With this setting HW passes the TCP sequence number of the TLS
* record that it is requesting a resync on in the meta data.
@@ -12812,11 +13358,13 @@ struct tls_metadata_resync_msg {
*/
#define TLS_METADATA_RESYNC_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
+ #define TLS_METADATA_RESYNC_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12829,7 +13377,8 @@ struct tls_metadata_resync_msg {
*/
#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12841,28 +13390,77 @@ struct tls_metadata_resync_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
- TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
+ TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED
/*
* A value of 1 indicates that this packet contains a record that
* starts in the packet and extends beyond the packet.
*/
#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -13221,7 +13819,7 @@ struct hwrm_func_vf_free_output {
********************/
-/* hwrm_func_vf_cfg_input (size:448b/56B) */
+/* hwrm_func_vf_cfg_input (size:512b/64B) */
struct hwrm_func_vf_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13384,7 +13982,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of TX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
@@ -13393,7 +13991,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
@@ -13402,7 +14000,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of CMPL rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
@@ -13411,7 +14009,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RSS ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
@@ -13420,7 +14018,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of ring groups) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
@@ -13429,7 +14027,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of stat ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
@@ -13438,7 +14036,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of VNICs) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
@@ -13447,7 +14045,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of L2 ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
@@ -13486,9 +14084,10 @@ struct hwrm_func_vf_cfg_input {
/* The number of HW ring groups requested for the VF. */
uint16_t num_hw_ring_grps;
/* Number of Tx Key Contexts requested. */
- uint16_t num_tx_key_ctxs;
+ uint32_t num_tx_key_ctxs;
/* Number of Rx Key Contexts requested. */
- uint16_t num_rx_key_ctxs;
+ uint32_t num_rx_key_ctxs;
+ uint8_t unused[4];
} __rte_packed;
/* hwrm_func_vf_cfg_output (size:128b/16B) */
@@ -13558,7 +14157,7 @@ struct hwrm_func_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcaps_output (size:768b/96B) */
+/* hwrm_func_qcaps_output (size:896b/112B) */
struct hwrm_func_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -14176,6 +14775,74 @@ struct hwrm_func_qcaps_output {
/* When this bit is '1', it indicates that HW and FW support QUIC. */
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \
UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates that KDNet mode is
+ * supported on the port for this function. This bit is
+ * never set for a VF.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates the FW is capable of
+ * supporting Enhanced Doorbell Pacing.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates that FW is capable of
+ * supporting software based doorbell drop recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED \
+ UINT32_C(0x10)
+ /*
+ * When this bit is '1', it indicates the FW supports collection
+ * and query of the generic statistics.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', it indicates that the HW is capable of
+ * supporting UDP GSO on the function.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', it indicates that SyncE feature is
+ * supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', it indicates the FW is capable of
+ * supporting doorbell pacing version 0. As doorbell pacing
+ * notification from hardware for Thor2 is completely different
+ * from Thor1, this flag is used to differentiate the doorbell
+ * pacing notification between Thor1 and Thor2. Thor1 uses
+ * dbr_pacing_supported and dbr_pacing_ext_supported flags for
+ * doorbell pacing whereas Thor2 uses dbr_pacing_v0_supported flag.
+ * These flags will never be set at the same time for Thor2.
+ * Based on this flag, host drivers assume doorbell pacing is needed
+ * for Thor2.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', it indicates that the HW supports
+ * two-completion TX packet timestamp feature, a second completion
+ * carrying packet TX timestamp in addition to the standard
+ * completion returned for packets. Host driver should not use
+ * HWRM port timestamp query (HWRM_PORT_TS_QUERY) command for
+ * TX timestamp read when two-completion timestamp feature is
+ * supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', it indicates that the hardware based
+ * link aggregation group (L2 and RoCE) feature is supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \
+ UINT32_C(0x400)
uint16_t tunnel_disable_flag;
/*
* When this bit is '1', it indicates that the VXLAN parsing
@@ -14225,7 +14892,16 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \
UINT32_C(0x80)
- uint8_t unused_1;
+ uint8_t unused_1[2];
+ /*
+ * This value uniquely identifies the hardware NIC used by the
+ * function. The value returned will be the same for all functions.
+ * A value of 00-00-00-00-00-00-00-00 indicates no device serial number
+ * is currently configured. This is the same value that is returned by
+ * PCIe Capability Device Serial Number.
+ */
+ uint8_t device_serial_number[8];
+ uint8_t unused_2[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -14283,7 +14959,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcfg_output (size:896b/112B) */
+/* hwrm_func_qcfg_output (size:1024b/128B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -14787,7 +15463,36 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
UINT32_C(0x10)
- uint8_t unused_2[3];
+ /*
+ * Configured doorbell page size for this function.
+ * This field is valid for PF only.
+ */
+ uint8_t db_page_size;
+ /* DB page size is 4KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
+ /* DB page size is 8KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
+ /* DB page size is 16KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
+ /* DB page size is 32KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
+ /* DB page size is 64KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
+ /* DB page size is 128KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
+ /* DB page size is 256KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
+ /* DB page size is 512KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
+ /* DB page size is 1MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
+ /* DB page size is 2MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
+ /* DB page size is 4MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB
+ uint8_t unused_2[2];
/*
* Minimum guaranteed bandwidth for the network partition made up
* of the caller physical function and all its child virtual
@@ -14874,11 +15579,36 @@ struct hwrm_func_qcfg_output {
* value is used if ring MTU is not specified.
*/
uint16_t host_mtu;
+ uint8_t unused_3[2];
+ uint8_t unused_4[2];
+ /*
+ * KDNet mode for the port for this function. If a VF, KDNet
+ * mode is always disabled.
+ */
+ uint8_t port_kdnet_mode;
+ /* KDNet mode is not enabled on the port for this function. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
+ /* KDNet mode is enabled on the port for this function. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED
+ /*
+ * If KDNet mode is enabled, the PCI function number of the
+ * KDNet partition.
+ */
+ uint8_t kdnet_pcie_function;
+ /*
+ * Function ID of the KDNET function on this port. If the
+ * KDNET partition does not exist and the FW supports this
+ * feature, 0xffff will be returned.
+ */
+ uint16_t port_kdnet_fid;
+ uint8_t unused_5[2];
/* Number of Tx Key Contexts allocated. */
- uint16_t alloc_tx_key_ctxs;
+ uint32_t alloc_tx_key_ctxs;
/* Number of Rx Key Contexts allocated. */
- uint16_t alloc_rx_key_ctxs;
- uint8_t unused_3[5];
+ uint32_t alloc_rx_key_ctxs;
+ uint8_t unused_6[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -14894,7 +15624,7 @@ struct hwrm_func_qcfg_output {
*****************/
-/* hwrm_func_cfg_input (size:896b/112B) */
+/* hwrm_func_cfg_input (size:1024b/128B) */
struct hwrm_func_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -15002,7 +15732,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of TX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
@@ -15011,7 +15741,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
@@ -15020,7 +15750,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of CMPL rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
@@ -15029,7 +15759,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RSS ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
@@ -15038,7 +15768,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of ring groups) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
@@ -15047,7 +15777,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of stat ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
@@ -15056,7 +15786,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of VNICs) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
@@ -15065,7 +15795,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of L2 ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
@@ -15091,7 +15821,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of NQ rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
@@ -15158,6 +15888,15 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
UINT32_C(0x40000000)
+ /*
+ * If this bit is set to 1, the driver is requesting FW to see if
+ * all the assets requested in this command (i.e. number of KTLS/
+ * QUIC key contexts) are available. The firmware will return an
+ * error if the requested assets are not available. The firmware
+ * will NOT reserve the assets if they are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \
+ UINT32_C(0x80000000)
uint32_t enables;
/*
* This bit must be '1' for the admin_mtu field to be
@@ -15803,11 +16542,71 @@ struct hwrm_func_cfg_input {
* ring that is assigned to a function has a valid mtu.
*/
uint16_t host_mtu;
+ uint8_t unused_0[4];
+ uint32_t enables2;
+ /*
+ * This bit must be '1' for the kdnet_mode field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the db_page_size field to be
+ * configured. Legacy controller core FW may silently ignore
+ * the db_page_size programming request through this command.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)
+ /*
+ * KDNet mode for the port for this function. If NPAR is
+ * also configured on this port, it takes precedence. KDNet
+ * mode is ignored for a VF.
+ */
+ uint8_t port_kdnet_mode;
+ /* KDNet mode is not enabled. */
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
+ /* KDNet mode enabled. */
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_LAST \
+ HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED
+ /*
+ * This field can be used by the PF driver to configure the doorbell
+ * page size. L2 driver can use different pages to ring the doorbell
+ * for L2 push operation. The doorbell page size should be configured
+ * to match the native CPU page size for proper RoCE and L2 doorbell
+ * operations. This value supersedes the older method of configuring
+ * the doorbell page size by the RoCE driver using the command queue
+ * method. The default is 4K.
+ */
+ uint8_t db_page_size;
+ /* DB page size is 4KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
+ /* DB page size is 8KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
+ /* DB page size is 16KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
+ /* DB page size is 32KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
+ /* DB page size is 64KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
+ /* DB page size is 128KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
+ /* DB page size is 256KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
+ /* DB page size is 512KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
+ /* DB page size is 1MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
+ /* DB page size is 2MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
+ /* DB page size is 4MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \
+ HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB
+ uint8_t unused_1[2];
/* Number of Tx Key Contexts requested. */
- uint16_t num_tx_key_ctxs;
+ uint32_t num_tx_key_ctxs;
/* Number of Rx Key Contexts requested. */
- uint16_t num_rx_key_ctxs;
- uint8_t unused_0[4];
+ uint32_t num_rx_key_ctxs;
+ uint8_t unused_2[4];
} __rte_packed;
/* hwrm_func_cfg_output (size:128b/16B) */
@@ -15900,24 +16699,27 @@ struct hwrm_func_qstats_input {
* A privileged PF can query for other function's statistics.
*/
uint16_t fid;
- /* This flags indicates the type of statistics request. */
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * flags should be set to 1 when request is for only RoCE statistics.
- * This will be honored only if the caller_fid is a privileged PF.
- * In all other cases FID and caller_fid should be the same.
+ * This bit should be set to 1 when request is for only RoCE
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
*/
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
/*
- * flags should be set to 2 when request is for the counter mask,
+ * This bit should be set to 1 when request is for the counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
- HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
+ /*
+ * This bit should be set to 1 when request is for only L2
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
+ */
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4)
uint8_t unused_0[5];
} __rte_packed;
@@ -15992,7 +16794,18 @@ struct hwrm_func_qstats_output {
uint64_t rx_agg_events;
/* Number of aborted aggregations on the function. */
uint64_t rx_agg_aborts;
- uint8_t unused_0[7];
+ /*
+ * This field is the sequence of the statistics of a function being
+ * cleared. Firmware starts the sequence from zero. It increments
+ * the sequence number every time the statistics of the function
+ * are cleared, which can be triggered by a clear statistics request
+ * or by freeing all statistics contexts of the function. If a user
+ * is interested in knowing if the statistics have been cleared
+ * since the last query, it can keep track of this sequence number
+ * between queries.
+ */
+ uint8_t clear_seq;
+ uint8_t unused_0[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -16045,24 +16858,20 @@ struct hwrm_func_qstats_ext_input {
* A privileged PF can query for other function's statistics.
*/
uint16_t fid;
- /* This flags indicates the type of statistics request. */
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * flags should be set to 1 when request is for only RoCE statistics.
- * This will be honored only if the caller_fid is a privileged PF.
- * In all other cases FID and caller_fid should be the same.
+ * This bit should be set to 1 when request is for only RoCE
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
*/
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
+ #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
/*
- * flags should be set to 2 when request is for the counter mask
+ * This bit should be set to 1 when request is for the counter mask
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
- HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
uint8_t unused_0[1];
uint32_t enables;
/*
@@ -16418,6 +17227,14 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
UINT32_C(0x200)
+ /*
+ * When this bit is 1, the function's driver is indicating the
+ * support for asymmetric queue configuration, such that queue
+ * ids and service profiles on TX side are not the same as the
+ * corresponding queue configuration on the RX side
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \
+ UINT32_C(0x400)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -16979,7 +17796,7 @@ struct hwrm_func_resource_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_resource_qcaps_output (size:512b/64B) */
+/* hwrm_func_resource_qcaps_output (size:576b/72B) */
struct hwrm_func_resource_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -17054,15 +17871,16 @@ struct hwrm_func_resource_qcaps_output {
*/
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ uint8_t unused_0[2];
/* Minimum guaranteed number of Tx Key Contexts */
- uint16_t min_tx_key_ctxs;
+ uint32_t min_tx_key_ctxs;
/* Maximum non-guaranteed number of Tx Key Contexts */
- uint16_t max_tx_key_ctxs;
+ uint32_t max_tx_key_ctxs;
/* Minimum guaranteed number of Rx Key Contexts */
- uint16_t min_rx_key_ctxs;
+ uint32_t min_rx_key_ctxs;
/* Maximum non-guaranteed number of Rx Key Contexts */
- uint16_t max_rx_key_ctxs;
- uint8_t unused_0[5];
+ uint32_t max_rx_key_ctxs;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -17078,7 +17896,7 @@ struct hwrm_func_resource_qcaps_output {
*****************************/
-/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
+/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */
struct hwrm_func_vf_resource_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -17152,18 +17970,18 @@ struct hwrm_func_vf_resource_cfg_input {
*/
#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ uint8_t unused_0[2];
/* Minimum guaranteed number of Tx Key Contexts */
- uint16_t min_tx_key_ctxs;
+ uint32_t min_tx_key_ctxs;
/* Maximum non-guaranteed number of Tx Key Contexts */
- uint16_t max_tx_key_ctxs;
+ uint32_t max_tx_key_ctxs;
/* Minimum guaranteed number of Rx Key Contexts */
- uint16_t min_rx_key_ctxs;
+ uint32_t min_rx_key_ctxs;
/* Maximum non-guaranteed number of Rx Key Contexts */
- uint16_t max_rx_key_ctxs;
- uint8_t unused_0[2];
+ uint32_t max_rx_key_ctxs;
} __rte_packed;
-/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
+/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */
struct hwrm_func_vf_resource_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -17190,10 +18008,10 @@ struct hwrm_func_vf_resource_cfg_output {
/* Reserved number of ring groups */
uint16_t reserved_hw_ring_grps;
/* Actual number of Tx Key Contexts reserved */
- uint16_t reserved_tx_key_ctxs;
+ uint32_t reserved_tx_key_ctxs;
/* Actual number of Rx Key Contexts reserved */
- uint16_t reserved_rx_key_ctxs;
- uint8_t unused_0[3];
+ uint32_t reserved_rx_key_ctxs;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -17479,8 +18297,13 @@ struct hwrm_func_backing_store_qcaps_output {
* function.
*/
uint32_t rkc_max_entries;
+ /*
+ * Additional number of RoCE QP context entries required for this
+ * function to support fast QP destroy feature.
+ */
+ uint16_t fast_qpmd_qp_num_entries;
/* Reserved for future. */
- uint8_t rsvd1[7];
+ uint8_t rsvd1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20638,31 +21461,53 @@ struct hwrm_func_ptp_pin_qcfg_output {
/* Type of function for Pin #2. */
uint8_t pin2_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
/* Type of function for Pin #3. */
uint8_t pin3_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
@@ -20813,17 +21658,28 @@ struct hwrm_func_ptp_pin_cfg_input {
/* Configure function for TSIO pin#2. */
uint8_t pin2_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
/* Enable or disable functionality of Pin #3. */
uint8_t pin3_state;
/* Disabled */
@@ -20835,17 +21691,28 @@ struct hwrm_func_ptp_pin_cfg_input {
/* Configure function for TSIO pin#3. */
uint8_t pin3_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
uint8_t unused_0[4];
} __rte_packed;
@@ -21130,12 +21997,25 @@ struct hwrm_func_ptp_ts_query_output {
uint16_t resp_len;
/* Timestamp value of last PPS event latched. */
uint64_t pps_event_ts;
- /* PTM local timestamp value. */
- uint64_t ptm_res_local_ts;
- /* PTM Master timestamp value. */
- uint64_t ptm_pmstr_ts;
- /* PTM Master propagation delay */
- uint32_t ptm_mstr_prop_dly;
+ /*
+ * PHC timestamp value when PTM responseD request is received
+ * at downstream port (t4'). This is a 48 bit timestamp in nanoseconds.
+ */
+ uint64_t ptm_local_ts;
+ /*
+ * PTM System timestamp value corresponding to t4' at
+ * root complex (T4'). Together with ptm_local_ts, these
+ * two timestamps provide the cross-trigger timestamps.
+ * Driver can directly use these values for cross-trigger.
+ * This is a 48 bit timestamp in nanoseconds.
+ */
+ uint64_t ptm_system_ts;
+ /*
+ * PTM Link delay. This is the time taken at root complex (RC)
+ * between receiving PTM request and sending PTM response to
+ * downstream port. This is a 32 bit value in nanoseconds.
+ */
+ uint32_t ptm_link_delay;
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -21463,7 +22343,18 @@ struct hwrm_func_key_ctx_alloc_output {
uint16_t resp_len;
/* Actual number of Key Contexts allocated. */
uint16_t num_key_ctxs_allocated;
- uint8_t unused_0[5];
+ /* Control flags. */
+ uint8_t flags;
+ /*
+ * When set, it indicates that all key contexts allocated by this
+ * command are contiguous. As a result, the driver has to read the
+ * start context ID from the first entry of the DMA data buffer
+ * and figures out the end context ID by “start context ID +
+ * num_key_ctxs_allocated - 1”.
+ */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \
+ UINT32_C(0x1)
+ uint8_t unused_0[4];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21574,6 +22465,9 @@ struct hwrm_func_backing_store_cfg_v2_input {
* Instance of the backing store type. It is zero-based,
* which means "0" indicates the first instance. For backing
* stores with single instance only, leave this field to 0.
+ * 1. If the backing store type is MPC TQM ring, use the following
+ * instance value to MPC client mapping:
+ * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
*/
uint16_t instance;
/* Control flags. */
@@ -21586,6 +22480,31 @@ struct hwrm_func_backing_store_cfg_v2_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the driver indicates that the backing store type
+ * to be configured in this command is the last one to do for
+ * the associated PF. That means all backing store type
+ * configurations are done for the corresponding PF after this
+ * command. As a result, the firmware has to do the necessary
+ * post configurations.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE \
+ UINT32_C(0x2)
+ /*
+ * When set, the driver indicates extending the size of the specific
+ * backing store type instead of configuring the corresponding PBLs.
+ * The size specified in the command will be the new size to be
+ * configured. The operation is only valid when the specific backing
+ * store has been configured before. Otherwise, the firmware will
+ * return an error. The driver needs to zero out the “entry_size”,
+ * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the
+ * firmware will ignore these inputs. Further, the firmware expects
+ * the “num_entries” and any valid split entries to be no less than
+ * the initial value that has been configured. If not, it will
+ * return an error code.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND \
+ UINT32_C(0x4)
/* Page directory. */
uint64_t page_dir;
/* Number of entries */
@@ -21957,6 +22876,52 @@ struct hwrm_func_backing_store_qcfg_v2_output {
uint8_t valid;
} __rte_packed;
+/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* qpc_split_entries (size:128b/16B) */
+struct qpc_split_entries {
+ /* Number of L2 QP backing store entries. */
+ uint32_t qp_num_l2_entries;
+ /* Number of QP1 entries. */
+ uint32_t qp_num_qp1_entries;
+ uint32_t rsvd[2];
+} __rte_packed;
+
+/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* srq_split_entries (size:128b/16B) */
+struct srq_split_entries {
+ /* Number of L2 SRQ backing store entries. */
+ uint32_t srq_num_l2_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* cq_split_entries (size:128b/16B) */
+struct cq_split_entries {
+ /* Number of L2 CQ backing store entries. */
+ uint32_t cq_num_l2_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* vnic_split_entries (size:128b/16B) */
+struct vnic_split_entries {
+ /* Number of VNIC backing store entries. */
+ uint32_t vnic_num_vnic_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* mrav_split_entries (size:128b/16B) */
+struct mrav_split_entries {
+ /* Number of AV backing store entries. */
+ uint32_t mrav_num_av_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
/************************************
* hwrm_func_backing_store_qcaps_v2 *
************************************/
@@ -22150,6 +23115,9 @@ struct hwrm_func_backing_store_qcaps_v2_output {
/*
* Bit map of the valid instances associated with the
* backing store type.
+ * 1. If the backing store type is MPC TQM ring, use the following
+ * bit to MPC client mapping:
+ * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
*/
uint32_t instance_bit_map;
/*
@@ -22506,7 +23474,7 @@ struct hwrm_func_dbr_pacing_qcfg_output {
uint8_t unused_3[7];
/*
* Specifies primary function’s NQ ID.
- * A value of 0xFFFF indicates NQ ID is invalid.
+ * A value of 0xFFFF FFFF indicates NQ ID is invalid.
*/
uint32_t primary_nq_id;
/*
@@ -22585,13 +23553,13 @@ struct hwrm_func_dbr_pacing_broadcast_event_output {
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/*************************************
+ * hwrm_func_dbr_pacing_nqlist_query *
+ *************************************/
-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
-struct hwrm_func_vlan_qcfg_input {
+/* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */
+struct hwrm_func_dbr_pacing_nqlist_query_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -22620,18 +23588,10 @@ struct hwrm_func_vlan_qcfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
-struct hwrm_func_vlan_qcfg_output {
+/* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */
+struct hwrm_func_dbr_pacing_nqlist_query_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -22640,49 +23600,414 @@ struct hwrm_func_vlan_qcfg_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint64_t unused_0;
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id0;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id1;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id2;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id3;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id4;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id5;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id6;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id7;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id8;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id9;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id10;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id11;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id12;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id13;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id14;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id15;
+ /* Number of consecutive NQ ring IDs populated in the response. */
+ uint32_t num_nqs;
+ uint8_t unused_0[3];
/*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
+ uint8_t valid;
+} __rte_packed;
+
+/************************************
+ * hwrm_func_dbr_recovery_completed *
+ ************************************/
+
+
+/* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */
+struct hwrm_func_dbr_recovery_completed_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd2;
- /* Future use. */
- uint32_t rsvd3;
- uint8_t unused_3[3];
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Specifies the epoch value with the one that was specified by the
+ * firmware in the error_report_doorbell_drop_threshold async event
+ * corresponding to the specific recovery cycle.
+ */
+ uint32_t epoch;
+ /* The epoch value. */
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */
+struct hwrm_func_dbr_recovery_completed_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_func_vlan_cfg *
- **********************/
+/***********************
+ * hwrm_func_synce_cfg *
+ ***********************/
-/* hwrm_func_vlan_cfg_input (size:384b/48B) */
-struct hwrm_func_vlan_cfg_input {
+/* hwrm_func_synce_cfg_input (size:192b/24B) */
+struct hwrm_func_synce_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t enables;
+ /*
+ * This bit must be '1' for the freq_profile field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the primary_clock_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the secondary_clock_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK \
+ UINT32_C(0x4)
+ /* Frequency profile for SyncE recovered clock. */
+ uint8_t freq_profile;
+ /* Invalid frequency profile */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
+ /* 25MHz SyncE clock profile */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ
+ /*
+ * Enable or disable primary clock for PF/port, overriding previous
+ * primary clock setting.
+ */
+ uint8_t primary_clock_state;
+ /* Disable clock */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE \
+ UINT32_C(0x0)
+ /* Enable clock */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE \
+ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE
+ /*
+ * Enable or disable secondary clock for PF/port, overriding previous
+ * secondary clock setting.
+ */
+ uint8_t secondary_clock_state;
+ /* Clock disabled */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE \
+ UINT32_C(0x0)
+ /* Clock enabled */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE \
+ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_func_synce_cfg_output (size:128b/16B) */
+struct hwrm_func_synce_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_func_synce_qcfg *
+ ************************/
+
+
+/* hwrm_func_synce_qcfg_input (size:192b/24B) */
+struct hwrm_func_synce_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __rte_packed;
+
+/* hwrm_func_synce_qcfg_output (size:128b/16B) */
+struct hwrm_func_synce_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Frequency profile for SyncE recovered clock. */
+ uint8_t freq_profile;
+ /* Invalid frequency profile */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
+ /* 25MHz SyncE clock profile */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_LAST \
+ HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ
+ /* SyncE recovered clock state */
+ uint8_t state;
+ /*
+ * When this bit is '1', primary clock is enabled for this PF/port.
+ * When this bit is '0', primary clock is disabled for this PF/port.
+ */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', secondary clock is enabled for this
+ * PF/port.
+ * When this bit is '0', secondary clock is disabled for this
+ * PF/port.
+ */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED \
+ UINT32_C(0x2)
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
+
+
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
+ */
+ uint16_t fid;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
+struct hwrm_func_vlan_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint64_t unused_0;
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
+ /*
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
+ /*
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd2;
+ /* Future use. */
+ uint32_t rsvd3;
+ uint8_t unused_3[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_func_vlan_cfg *
+ **********************/
+
+
+/* hwrm_func_vlan_cfg_input (size:384b/48B) */
+struct hwrm_func_vlan_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24576,7 +25901,7 @@ struct hwrm_port_phy_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+/* hwrm_port_phy_qcfg_output (size:832b/104B) */
struct hwrm_port_phy_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25601,6 +26926,14 @@ struct hwrm_port_phy_qcfg_output {
/* 200Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
UINT32_C(0x4)
+ /*
+ * This field is used to indicate the reasons for link down.
+ * This field is set to 0, if the link down reason is unknown.
+ */
+ uint8_t link_down_reason;
+ /* Remote fault */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -26934,16 +28267,12 @@ struct hwrm_port_qstats_input {
/* Port ID of port that is being queried. */
uint16_t port_id;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for a counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0[5];
/*
* This is the host address where
@@ -27646,16 +28975,12 @@ struct hwrm_port_qstats_ext_input {
*/
uint16_t rx_stat_size;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for the counter mask,
* representing width of each of the stats counters, rather than
* counters themselves.
*/
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0;
/*
* This is the host address where
@@ -27903,16 +29228,12 @@ struct hwrm_port_ecn_qstats_input {
*/
uint16_t ecn_stat_buf_size;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for a counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
- HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0[3];
/*
* This is the host address where
@@ -28398,6 +29719,12 @@ struct hwrm_port_phy_qcaps_output {
*/
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \
UINT32_C(0x2)
+ /*
+ * If set to 1, then this field indicates that
+ * bank based addressing is supported in firmware.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \
+ UINT32_C(0x4)
/*
* Number of internal ports for this device. This field allows the FW
* to advertise how many internal ports are present. Manufacturing
@@ -29720,6 +31047,14 @@ struct hwrm_port_prbs_test_input {
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
/* PRBS58 */
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* PRBS49 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7)
+ /* PRBS10 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8)
+ /* PRBS20 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9)
+ /* PRBS13 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa)
/* Invalid */
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
@@ -29749,6 +31084,15 @@ struct hwrm_port_prbs_test_input {
*/
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
UINT32_C(0x4)
+ /* If set to 1, FEC stat t-code 0-7 registers are enabled. */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 \
+ UINT32_C(0x8)
+ /*
+ * If set to 1, FEC stat t-code 8-15 registers are enabled.
+ * If fec_stat_t0_t7 is set, fec_stat_t8_t15 field will be ignored.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 \
+ UINT32_C(0x10)
/* Duration in seconds to run the PRBS test. */
uint16_t timeout;
/*
@@ -29777,7 +31121,15 @@ struct hwrm_port_prbs_test_output {
uint16_t resp_len;
/* Total length of stored data. */
uint16_t total_data_len;
- uint16_t unused_0;
+ /* This field is used in Output records to indicate the output format */
+ uint8_t ber_format;
+ /* BER_FORMAT_PRBS */
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)
+ /* BER_FORMAT_FEC */
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1)
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_LAST \
+ HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC
+ uint8_t unused_0;
uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
@@ -30800,6 +32152,160 @@ struct hwrm_port_ep_tx_qcfg_output {
uint8_t valid;
} __rte_packed;
+/*****************
+ * hwrm_port_cfg *
+ *****************/
+
+
+/* hwrm_port_cfg_input (size:256b/32B) */
+struct hwrm_port_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tx_rate_limit field to
+ * be configured.
+ */
+ #define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1)
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
+ uint16_t unused_0;
+ /*
+ * Requested setting of TX rate limit in Mbps.
+ * tx_rate_limit = 0 will cancel the rate limit if any.
+ * This field is valid only when tx_rate_limit bit in 'enables'
+ * field is '1'.
+ */
+ uint32_t tx_rate_limit;
+} __rte_packed;
+
+/* hwrm_port_cfg_output (size:128b/16B) */
+struct hwrm_port_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************
+ * hwrm_port_qcfg *
+ ******************/
+
+
+/* hwrm_port_qcfg_input (size:192b/24B) */
+struct hwrm_port_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_port_qcfg_output (size:192b/24B) */
+struct hwrm_port_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t supported;
+ /*
+ * If set to '1', then this bit indicates that TX rate limit
+ * could be configured via hwrm_port_cfg command.
+ */
+ #define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1)
+ uint32_t enabled;
+ /*
+ * If set to '1', then this bit indicates that TX rate limit
+ * is enabled and could be found in tx_rate_limit field.
+ */
+ #define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1)
+ /*
+ * Current setting of TX rate limit in Mbps.
+ * This field is valid only when tx_rate_limit bit in 'enabled'
+ * field is '1'.
+ */
+ uint32_t tx_rate_limit;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -35688,29 +37194,19 @@ struct hwrm_vnic_update_input {
HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
/*
* The metadata format type used in all the RX packet completions
- * going through this VNIC.
+ * going through this VNIC. This value is product specific. Refer to
+ * the L2 HSI completion ring structures for the detailed
+ * descriptions. For Thor and Thor2, it corresponds to “meta_format”
+ * in “rx_pkt_cmpl_hi” and “rx_pkt_v3_cmpl_hi”, respectively.
*/
uint8_t metadata_format_type;
- /* No metadata information. */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
- UINT32_C(0x0)
- /*
- * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
- * vtag[19:0]).
- */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
- UINT32_C(0x1)
- /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
- UINT32_C(0x2)
- /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
- UINT32_C(0x3)
- /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
- UINT32_C(0x4)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
- HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
+ HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4
/*
* The maximum receive unit of the vnic.
* Each vnic is associated with a function.
@@ -35911,6 +37407,12 @@ struct hwrm_vnic_cfg_input {
*/
#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
UINT32_C(0x40)
+ /*
+ * When this bit is '1' it enables ring selection using the incoming
+ * spif and lcos for the packet.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the dflt_ring_grp field to be
@@ -36259,6 +37761,9 @@ struct hwrm_vnic_qcfg_output {
*/
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
UINT32_C(0x80)
+ /* When this bit is '1' it indicates port cos_mapping_mode enabled. */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x100)
/*
* When returned with a valid CoS Queue id, the CoS Queue/VNIC association
* is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
@@ -36315,7 +37820,30 @@ struct hwrm_vnic_qcfg_output {
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \
HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED
- uint8_t unused_1[3];
+ /*
+ * This field conveys the metadata format type that has been
+ * configured. This value is product specific. Refer to the L2 HSI
+ * completion ring structures for the detailed descriptions. For Thor
+ * and Thor2, it corresponds to “meta_format” in “rx_pkt_cmpl_hi” and
+ * “rx_pkt_v3_cmpl_hi”, respectively.
+ */
+ uint8_t metadata_format_type;
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST \
+ HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4
+ /* This field conveys the VNIC operation state. */
+ uint8_t vnic_state;
+ /* Normal operation state. */
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
+ /* Drop all packets. */
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1)
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST \
+ HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP
+ uint8_t unused_1;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -36557,6 +38085,53 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \
UINT32_C(0x100000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv4 IPSEC AH SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv4 IPSEC ESP SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP \
+ UINT32_C(0x400000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv6 IPSEC AH SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP \
+ UINT32_C(0x800000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv6 IPSEC ESP SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP \
+ UINT32_C(0x1000000)
+ /*
+ * When outermost_rss_cap is '1' and this bit is '1', the outermost
+ * RSS hash mode may be set on a PF or trusted VF.
+ * When outermost_rss_cap is '1' and this bit is '0', the outermost
+ * RSS hash mode may be set on a PF.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP \
+ UINT32_C(0x2000000)
+ /*
+ * When this bit is '1' it indicates HW is capable of enabling ring
+ * selection using the incoming spif and lcos for the packet.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x4000000)
+ /*
+ * When this bit is '1', it indicates controller enabled
+ * RSS profile TCAM mode.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED \
+ UINT32_C(0x8000000)
+ /* When this bit is '1' FW supports VNIC hash mode. */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \
+ UINT32_C(0x10000000)
/*
* This field advertises the maximum concurrent TPA aggregations
* supported by the VNIC on new devices that support TPA v2 or v3.
@@ -36869,6 +38444,38 @@ struct hwrm_vnic_rss_cfg_input {
*/
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \
UINT32_C(0x40)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv4 packets. Host drivers should set this bit based on
+ * rss_ipsec_ah_spi_ipv4_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv4 packets. Host drivers should set this bit based on
+ * rss_ipsec_esp_spi_ipv4_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv6 packets. Host drivers should set this bit based on
+ * rss_ipsec_ah_spi_ipv6_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv6 packets. Host drivers should set this bit based on
+ * rss_ipsec_esp_spi_ipv6_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 \
+ UINT32_C(0x400)
/* VNIC ID of VNIC associated with RSS table being configured. */
uint16_t vnic_id;
/*
@@ -36876,11 +38483,25 @@ struct hwrm_vnic_rss_cfg_input {
* Valid values range from 0 to 7.
*/
uint8_t ring_table_pair_index;
- /* Flags to specify different RSS hash modes. */
+ /*
+ * Flags to specify different RSS hash modes. Global RSS hash mode is
+ * indicated when vnic_id and rss_ctx_idx fields are set to value of
+ * 0xffff. Only PF can initiate global RSS hash mode setting changes.
+ * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx,
+ * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based
+ * on first come first serve order. Global RSS hash mode and VNIC RSS
+ * hash modes are mutually exclusive. FW returns invalid error
+ * if FW receives conflicting requests. To change the current hash
+ * mode, the mode associated drivers need to be unloaded and apply
+ * the new configuration.
+ */
uint8_t hash_mode_flags;
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,
+ * innermost_4 and innermost_2 hash modes are used to configure
+ * the tuple mode. When this bit is '1' and FW is not
+ * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash
+ * mode setting configured in the device otherwise.
*/
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
@@ -37063,9 +38684,17 @@ struct hwrm_vnic_rss_qcfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Index to the rss indirection table. */
+ /*
+ * Index to the rss indirection table. This field is used as a lookup
+ * for chips before Thor - i.e. Cumulus and Whitney.
+ */
uint16_t rss_ctx_idx;
- uint8_t unused_0[6];
+ /*
+ * VNIC ID of VNIC associated with RSS table being queried. This field
+ * is used as a lookup for Thor and later chips.
+ */
+ uint16_t vnic_id;
+ uint8_t unused_0[4];
} __rte_packed;
/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
@@ -37084,45 +38713,104 @@ struct hwrm_vnic_rss_qcfg_output {
* over source and destination IPv4 addresses of IPv4
* packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 \
+ UINT32_C(0x1)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv4 addresses and
* source/destination ports of TCP/IPv4 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 \
+ UINT32_C(0x2)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv4 addresses and
* source/destination ports of UDP/IPv4 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 \
+ UINT32_C(0x4)
/*
* When this bit is '1', the RSS hash shall be computed
* over source and destination IPv6 addresses of IPv6
* packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 \
+ UINT32_C(0x8)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv6 addresses and
* source/destination ports of TCP/IPv6 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 \
+ UINT32_C(0x10)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv6 addresses and
* source/destination ports of UDP/IPv6 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source, destination IPv6 addresses and flow label of IPv6
+ * packets. Hash type ipv6 and ipv6_flow_label are mutually
+ * exclusive. HW does not include the flow_label in hash
+ * calculation for the packets that are matching tcp_ipv6 and
+ * udp_ipv6 hash types. This bit will be '0' if
+ * rss_ipv6_flow_label_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap
+ * is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv4 packets. This bit will be '0' if
+ * rss_ipsec_esp_spi_ipv4_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv6 packets. This bit will be '0' if
+ * rss_ipsec_ah_spi_ipv6_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv6 packets. This bit will be '0' if
+ * rss_ipsec_esp_spi_ipv6_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 \
+ UINT32_C(0x400)
uint8_t unused_0[4];
/* This is the value of rss hash key */
uint32_t hash_key[10];
- /* Flags to specify different RSS hash modes. */
+ /*
+ * Flags to specify different RSS hash modes. Setting rss_ctx_idx to
+ * the value of 0xffff implies a global RSS configuration query.
+ * hash_mode_flags are only valid for global RSS configuration query.
+ * Only the PF can initiate a global RSS configuration query.
+ * The query request fails if any VNIC is configured with hash mode
+ * and rss_ctx_idx is 0xffff.
+ */
uint8_t hash_mode_flags;
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,
+ * it indicates VNIC's configured RSS hash mode.
+ * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable,
+ * It indicates using current RSS hash mode setting configured in the
+ * device.
*/
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
@@ -37832,6 +39520,27 @@ struct hwrm_ring_alloc_input {
*/
#define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \
UINT32_C(0x2)
+ /*
+ * Used with enhanced Doorbell Pacing feature, when set to '1'
+ * this flag indicates that the NQ id that's allocated should be
+ * used for DBR pacing notifications.
+ */
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING \
+ UINT32_C(0x4)
+ /*
+ * Host driver should set this flag bit to '1' to enable
+ * two-completion TX packet timestamp feature. By enabling this
+ * per QP flag and enabling stamp bit in TX BD lflags, host drivers
+ * expect two completions, one for regular TX completion and the
+ * other completion with timestamp. For a QP with both completion
+ * coalescing and timestamp completion features enabled, completion
+ * coalescing takes place on regular TX completions. The timestamp
+ * completions are not coalesced and a separate timestamp completion
+ * is generated for each packet with stamp bit set in the TX BD
+ * lflags.
+ */
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE \
+ UINT32_C(0x8)
/*
* This value is a pointer to the page table for the
* Ring.
@@ -38026,7 +39735,7 @@ struct hwrm_ring_alloc_input {
* completion rings are allowed.
*/
uint8_t int_mode;
- /* Legacy INTA */
+ /* Legacy INTA (deprecated) */
#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
/* Reserved */
#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
@@ -40371,6 +42080,9 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41239,6 +42951,9 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
*/
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41507,6 +43222,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41629,6 +43347,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41743,6 +43464,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41978,8 +43702,11 @@ struct hwrm_cfa_encap_record_alloc_input {
*/
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -42309,6 +44036,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* Applies to UDP and TCP traffic.
* 6 - TCP
* 17 - UDP
+ * 1 - ICMP
+ * 58 - ICMPV6
+ * 255 - RSVD
*/
uint8_t ip_protocol;
/* invalid */
@@ -42320,8 +44050,17 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* UDP */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
UINT32_C(0x11)
+ /* ICMP */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP \
+ UINT32_C(0x1)
+ /* ICMPV6 */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 \
+ UINT32_C(0x3a)
+ /* RSVD */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD \
+ UINT32_C(0xff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD
/*
* If set, this value shall represent the
* Logical VNIC ID of the destination VNIC for the RX
@@ -42388,6 +44127,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -42979,6 +44721,9 @@ struct hwrm_cfa_em_flow_alloc_input {
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -44444,6 +46189,9 @@ struct hwrm_cfa_decap_filter_alloc_input {
*/
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -44929,6 +46677,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -45182,8 +46933,11 @@ struct hwrm_cfa_flow_action_data {
* (IPV6oVXLANGPE)
*/
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
- HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE
uint8_t unused[7];
/* This value is encap data for the associated encap type. */
uint32_t encap_data[20];
@@ -45238,6 +46992,9 @@ struct hwrm_cfa_flow_tunnel_hdr_data {
*/
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -45377,19 +47134,35 @@ struct hwrm_cfa_flow_info_input {
/* Max flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
UINT32_C(0xfff)
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
/* CNP flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
UINT32_C(0x1000)
/* RoCEv1 flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
UINT32_C(0x2000)
+ /* NIC flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX \
+ UINT32_C(0x3000)
/* RoCEv2 flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
UINT32_C(0x4000)
/* Direction rx = 1 */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
UINT32_C(0x8000)
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX \
+ UINT32_C(0x9000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX \
+ UINT32_C(0xa000)
+ /* NIC flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX \
+ UINT32_C(0xb000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX \
+ UINT32_C(0xc000)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST \
+ HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX
uint8_t unused_0[6];
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
@@ -45629,27 +47402,67 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
+ /* Number of valid flows in this command. */
uint16_t num_flows;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_0 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_0;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_1 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_1;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_2 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_2;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_3 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_3;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_4 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_4;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_5 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_5;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_6 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_6;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_7 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_7;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_8 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_8;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_9 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_9;
uint8_t unused_0[2];
/* Flow ID of a flow. */
@@ -45724,7 +47537,16 @@ struct hwrm_cfa_flow_stats_output {
uint64_t byte_8;
/* byte_9 is 64 b */
uint64_t byte_9;
- uint8_t unused_0[7];
+ /*
+ * If a flow has been hit, the bit representing the flow will be 1.
+ * Likewise, if a flow has not, the bit representing the flow
+ * will be 0. Mapping will match flow numbers where bitX is for flowX
+ * (ex: bit 0 is flow0). This only applies for NIC flows. Upon
+ * reading of the flow, the bit will be cleared for the flow and only
+ * set again when traffic is received by the flow.
+ */
+ uint16_t flow_hits;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -46498,27 +48320,36 @@ struct hwrm_cfa_pair_alloc_input {
* 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
*/
uint16_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
UINT32_C(0x4)
- /* Modify existing rep2fn pair and move pair to new PF. */
+ /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
UINT32_C(0x5)
/*
* Modify existing rep2fn pairs paired with same PF and move pairs
- * to new PF.
+ * to new PF. (deprecated)
*/
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
UINT32_C(0x6)
@@ -46672,21 +48503,30 @@ struct hwrm_cfa_pair_free_input {
* 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
*/
uint16_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
- /* Modify existing rep2fn pair and move pair to new PF. */
+ /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
/*
* Modify existing rep2fn pairs paired with same PF and move pairs
- * to new PF.
+ * to new PF. (deprecated)
*/
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
/*
@@ -46808,15 +48648,24 @@ struct hwrm_cfa_pair_info_output {
uint16_t tx_cfa_action_b;
/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
uint8_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
@@ -47084,6 +48933,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
*/
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
UINT32_C(0x2000)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE \
+ UINT32_C(0x4000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -48272,7 +50124,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* Value of 1 to indicate firmware support flow batch delete
* operation through HWRM_CFA_FLOW_FLUSH command.
* Value of 0 to indicate that the firmware does not support flow
- * batch delete operation.
+ * batch delete operation. (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
UINT32_C(0x4)
@@ -48280,7 +50132,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* Value of 1 to indicate that the firmware support flow reset all
* operation through HWRM_CFA_FLOW_FLUSH command.
* Value of 0 indicates firmware does not support flow reset all
- * operation.
+ * operation. (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
@@ -48295,12 +50147,14 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
/*
* Value of 1 to indicate that firmware supports TX EEM flows.
* Value of 0 indicates firmware does not support TX EEM flows.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
/*
* Value of 1 to indicate that firmware supports RX EEM flows.
* Value of 0 indicates firmware does not support RX EEM flows.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
@@ -48309,6 +50163,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* allocation of an on-chip flow counter which can be used for EEM
* flows. Value of 0 indicates firmware does not support the dynamic
* allocation of an on-chip flow counter.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
UINT32_C(0x80)
@@ -48390,6 +50245,19 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \
UINT32_C(0x40000)
+ /*
+ * If set to 1, firmware is capable returning stats for nic flows
+ * in cfa_flow_stats command where flow_handle value 0xF000.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED \
+ UINT32_C(0x80000)
+ /*
+ * If set to 1, firmware is capable of supporting these additional
+ * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default,
+ * this flag should be 0 for older version of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \
+ UINT32_C(0x100000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -50172,7 +52040,7 @@ struct hwrm_tf_tbl_type_get_input {
uint32_t index;
} __rte_packed;
-/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
+/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */
struct hwrm_tf_tbl_type_get_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -50189,7 +52057,7 @@ struct hwrm_tf_tbl_type_get_output {
/* unused */
uint16_t unused0;
/* Response data. */
- uint8_t data[128];
+ uint8_t data[256];
/* unused */
uint8_t unused1[7];
/*
@@ -50250,6 +52118,8 @@ struct hwrm_tf_tbl_type_set_input {
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate table data is being sent via DMA. */
+ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
/* unused. */
uint8_t unused0[2];
/*
@@ -52298,133 +54168,2494 @@ struct hwrm_tf_if_tbl_set_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
- uint32_t fw_session_id;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Index of the type to set. */
+ uint32_t index;
+ /* Size of the data to set. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused1[6];
+ /* Data to be set. */
+ uint8_t data[88];
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
+struct hwrm_tf_if_tbl_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tf_tbl_type_bulk_get *
+ *****************************/
+
+
+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
+struct hwrm_tf_tbl_type_bulk_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * When set use the special access register access to clear
+ * the table entries on read.
+ */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Starting index of the type to retrieve. */
+ uint32_t start_index;
+ /* Number of entries to retrieve. */
+ uint32_t num_entries;
+ /* Number of entries to retrieve. */
+ uint32_t unused1;
+ /* Host memory where data will be stored. */
+ uint64_t host_addr;
+} __rte_packed;
+
+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
+struct hwrm_tf_tbl_type_bulk_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Response code. */
+ uint32_t resp_code;
+ /* Response size. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused0;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************************
+ * hwrm_tf_session_hotup_state_set *
+ ***********************************/
+
+
+/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */
+struct hwrm_tf_session_hotup_state_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Shared session state. */
+ uint16_t state;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX
+} __rte_packed;
+
+/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */
+struct hwrm_tf_session_hotup_state_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************************
+ * hwrm_tf_session_hotup_state_get *
+ ***********************************/
+
+
+/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */
+struct hwrm_tf_session_hotup_state_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX
+ /* unused. */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */
+struct hwrm_tf_session_hotup_state_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Shared session HA state. */
+ uint16_t state;
+ /* Shared session HA reference count. */
+ uint16_t ref_cnt;
+ /* unused. */
+ uint8_t unused0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_tbl_scope_qcaps *
+ ****************************/
+
+
+/*
+ * TruFlow command to check if firmware is capable of
+ * supporting table scopes.
+ */
+/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * The maximum number of lookup records that a table scope can support.
+ * This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint32_t max_lkup_rec_cnt;
+ /*
+ * The maximum number of action records that a table scope can support.
+ * This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint32_t max_act_rec_cnt;
+ /* Not zero if firmware capable of table scopes. */
+ uint8_t tbl_scope_capable;
+ /*
+ * log2 of the number of lookup static buckets that a table scope can
+ * support. This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint8_t max_lkup_static_buckets_exp;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_tfc_tbl_scope_id_alloc *
+ *******************************/
+
+
+/*
+ * TruFlow command to allocate a table scope ID and create the pools.
+ *
+ * There is no corresponding free command since a table scope
+ * ID will automatically be freed once the last FID is removed.
+ * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns
+ * a fid_cnt of 0 that also means that the table scope ID has
+ * been freed.
+ */
+/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The maximum number of pools for this table scope. */
+ uint16_t max_pools;
+ /* Non-zero if this table scope is shared. */
+ uint8_t shared;
+ /*
+ * The size of the lookup pools per direction expressed as
+ * log2(max_records/max_pools). That is, size=2^exp.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t lkup_pool_sz_exp[2];
+ /*
+ * The size of the action pools per direction expressed as
+ * log2(max_records/max_pools). That is, size=2^exp.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t act_pool_sz_exp[2];
+ /* unused. */
+ uint8_t unused0;
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The table scope ID that was allocated. */
+ uint8_t tsid;
+ /*
+ * Non-zero if this is the first FID associated with this table scope
+ * ID.
+ */
+ uint8_t first;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tfc_tbl_scope_config *
+ *****************************/
+
+
+/* TruFlow command to configure the table scope memory. */
+/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */
+struct hwrm_tfc_tbl_scope_config_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The base addresses for lookup memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint64_t lkup_base_addr[2];
+ /*
+ * The base addresses for action memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint64_t act_base_addr[2];
+ /*
+ * The number of minimum sized lkup records per direction.
+ * In this usage, records are the minimum lookup memory
+ * allocation unit in a table scope. This value is the total
+ * memory required for buckets and entries.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t lkup_rec_cnt[2];
+ /*
+ * The number of minimum sized action records per direction.
+ * Similar to the lkup_rec_cnt, records are the minimum
+ * action memory allocation unit in a table scope.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t act_rec_cnt[2];
+ /*
+ * The number of static lookup buckets in the table scope.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t lkup_static_bucket_cnt[2];
+ /* The page size of the table scope. */
+ uint32_t pbl_page_sz;
+ /*
+ * The PBL level for lookup memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t lkup_pbl_level[2];
+ /*
+ * The PBL level for action memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t act_pbl_level[2];
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_config_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_tfc_tbl_scope_deconfig *
+ *******************************/
+
+
+/* TruFlow command to deconfigure the table scope memory. */
+/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_deconfig_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_deconfig_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_tbl_scope_fid_add *
+ ******************************/
+
+
+/* TruFlow command to add a FID to a table scope. */
+/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_fid_add_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_fid_add_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs currently in the table scope ID. */
+ uint8_t fid_cnt;
+ /* unused. */
+ uint8_t unused0[6];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_tbl_scope_fid_rem *
+ ******************************/
+
+
+/* TruFlow command to remove a FID from a table scope. */
+/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_fid_rem_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_fid_rem_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs remaining in the table scope ID. */
+ uint16_t fid_cnt;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************************
+ * hwrm_tfc_tbl_scope_pool_alloc *
+ *********************************/
+
+
+/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_pool_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Table Scope ID */
+ uint8_t tsid;
+ /* Control flags. Direction and type. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX
+ /* Indicates the table type. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE \
+ UINT32_C(0x2)
+ /* Lookup table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP \
+ (UINT32_C(0x0) << 1)
+ /* Action table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION
+ /* Unused */
+ uint8_t unused[6];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_pool_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pool ID */
+ uint16_t pool_id;
+ /* Pool size exponent. An exponent of 0 indicates a failure. */
+ uint8_t pool_sz_exp;
+ /* unused. */
+ uint8_t unused1[4];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/********************************
+ * hwrm_tfc_tbl_scope_pool_free *
+ ********************************/
+
+
+/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_pool_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Table Scope ID */
+ uint8_t tsid;
+ /* Control flags. Direction and type. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX
+ /* Indicates the table type. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE \
+ UINT32_C(0x2)
+ /* Lookup table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP \
+ (UINT32_C(0x0) << 1)
+ /* Action table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION
+ /* Pool ID */
+ uint16_t pool_id;
+ /* Unused */
+ uint8_t unused[4];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_pool_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tfc_session_id_alloc *
+ *****************************/
+
+
+/*
+ * Allocate a TFC session. Requests the firmware to allocate a TFC
+ * session identifier and associate a forwarding function with the
+ * session. Though there's not an explicit matching free for a session
+ * id alloc, dis-associating the last fid from a session id (fid_cnt goes
+ * to 0), will result in this session id being freed automatically.
+ */
+/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */
+struct hwrm_tfc_session_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_session_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_session_fid_add *
+ ****************************/
+
+
+/*
+ * Associate a TFC session id with a forwarding function. The target_fid
+ * will be associated with the passed in sid.
+ */
+/* hwrm_tfc_session_fid_add_input (size:192b/24B) */
+struct hwrm_tfc_session_fid_add_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[6];
+} __rte_packed;
+
+/* hwrm_tfc_session_fid_add_output (size:128b/16B) */
+struct hwrm_tfc_session_fid_add_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs that share this session. */
+ uint16_t fid_cnt;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_session_fid_rem *
+ ****************************/
+
+
+/*
+ * Dis-associate a TFC session from the target_fid.
+ * Though there's not an explicit matching free for a
+ * session id alloc, dis-associating the last fid from a session id
+ * (fid_cnt goes to 0), will result in this session id being freed
+ * automatically.
+ */
+/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */
+struct hwrm_tfc_session_fid_rem_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[6];
+} __rte_packed;
+
+/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */
+struct hwrm_tfc_session_fid_rem_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs that share this session. */
+ uint16_t fid_cnt;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_ident_alloc *
+ ************************/
+
+
+/*
+ * Allocate a TFC identifier. Requests the firmware to
+ * allocate a TFC identifier. The session id and track_type are passed
+ * in. The tracking_id is either the sid or target_fid depends on the
+ * track_type. The resource subtype is passed in, an id corresponding
+ * to all these is allocated and returned in the HWRM response.
+ */
+/* hwrm_tfc_ident_alloc_input (size:192b/24B) */
+struct hwrm_tfc_ident_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware. Will be used to track this identifier.
+ */
+ uint16_t sid;
+ /* Control flags. Direction. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking tag to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused field */
+ uint8_t unused0[3];
+} __rte_packed;
+
+/* hwrm_tfc_ident_alloc_output (size:128b/16B) */
+struct hwrm_tfc_ident_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Resource identifier allocated by the firmware using
+ * parameters above.
+ */
+ uint16_t ident_id;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_tfc_ident_free *
+ ***********************/
+
+
+/*
+ * Requests the firmware to free a TFC resource identifier.
+ * A resource subtype and session id are passed in.
+ * An identifier (previously allocated) corresponding to all these is
+ * freed, only after various sanity checks are completed.
+ */
+/* hwrm_tfc_ident_free_input (size:192b/24B) */
+struct hwrm_tfc_ident_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware. Will be used to validate this request.
+ */
+ uint16_t sid;
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Control flags. Direction. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX
+ /* The resource identifier to be freed */
+ uint16_t ident_id;
+ /* Reserved */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_ident_free_output (size:128b/16B) */
+struct hwrm_tfc_ident_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Reserved */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_tfc_idx_tbl_alloc *
+ **************************/
+
+
+/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */
+struct hwrm_tfc_idx_tbl_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Reserved */
+ uint8_t unused0[3];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_idx_tbl_alloc_set *
+ ******************************/
+
+
+/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */
+struct hwrm_tfc_idx_tbl_alloc_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX
+ /*
+ * Indicate device data is being sent via DMA, the device
+ * data packing does not change.
+ */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Reserved */
+ uint8_t unused0;
+ /* The size of the index table entry in bytes. */
+ uint16_t data_size;
+ /* The location of the dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[104];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_alloc_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_idx_tbl_set *
+ ************************/
+
+
+/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */
+struct hwrm_tfc_idx_tbl_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX
+ /*
+ * Indicate device data is being sent via DMA, the device
+ * data packing does not change.
+ */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /*
+ * Index table index returned during alloc by the
+ * firmware.
+ */
+ uint16_t idx_tbl_id;
+ /* The size of the index table entry in bytes. */
+ uint16_t data_size;
+ /* The location of the dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[104];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_idx_tbl_get *
+ ************************/
+
+
+/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */
+struct hwrm_tfc_idx_tbl_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * When set use the special access register access to clear
+ * the table entry on read.
+ */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /*
+ * Index table index returned during alloc by the
+ * firmware.
+ */
+ uint16_t idx_tbl_id;
+ /* The size of the index table entry buffer in bytes. */
+ uint16_t buffer_size;
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of the index table buffer returned in device size bytes. */
+ uint16_t data_size;
+ /* unused */
+ uint8_t unused1[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_tfc_idx_tbl_free *
+ *************************/
+
+
+/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */
+struct hwrm_tfc_idx_tbl_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Index table id to be freed by the firmware. */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Reserved */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* TruFlow resources request for a global id. */
+/* tfc_global_id_hwrm_req (size:64b/8B) */
+struct tfc_global_id_hwrm_req {
+ /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */
+ uint16_t rtype;
+ /* Indicates the flow direction in type of cfa_dir. */
+ uint16_t dir;
+ /* Subtype of the resource type. */
+ uint16_t subtype;
+ /* Number of the type of resources. */
+ uint16_t cnt;
+} __rte_packed;
+
+/* The reserved resources for the global id. */
+/* tfc_global_id_hwrm_rsp (size:64b/8B) */
+struct tfc_global_id_hwrm_rsp {
+ /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */
+ uint16_t rtype;
+ /* Indicates the flow direction in type of cfa_dir. */
+ uint16_t dir;
+ /* Subtype of the resource type. */
+ uint16_t subtype;
+ /* The global id that the resources reserved for. */
+ uint16_t id;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_global_id_alloc *
+ ****************************/
+
+
+/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */
+struct hwrm_tfc_global_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint16_t sid;
+ /* Global domain id. */
+ uint16_t global_id;
+ /*
+ * Defines the array size of the provided req_addr and
+ * resv_addr array buffers. Should be set to the number of
+ * request entries.
+ */
+ uint16_t req_cnt;
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * This is the DMA address for the request input data array
+ * buffer. Array is of tfc_global_id_hwrm_req type. Size of the
+ * array buffer is provided by the 'req_cnt' field in this
+ * message.
+ */
+ uint64_t req_addr;
+ /*
+ * This is the DMA address for the resc output data array
+ * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array
+ * buffer is provided by the 'req_cnt' field in this
+ * message.
+ */
+ uint64_t resc_addr;
+} __rte_packed;
+
+/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_global_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Size of the returned hwrm_tfc_global_id_req data array. The value
+ * cannot exceed the req_cnt defined by the input msg. The data
+ * array is returned using the resv_addr specified DMA
+ * address also provided by the input msg.
+ */
+ uint16_t rsp_cnt;
+ /* Non-zero if this is the first allocation for the global ID. */
+ uint8_t first;
+ /* unused. */
+ uint8_t unused0[4];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_tfc_tcam_set *
+ *********************/
+
+
+/* hwrm_tfc_tcam_set_input (size:1088b/136B) */
+struct hwrm_tfc_tcam_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Number of bytes in the TCAM result. */
+ uint16_t result_size;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate device data is being sent via DMA. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* unused. */
+ uint8_t unused0[6];
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+ /*
+ * TCAM key located at offset 0, mask located at mask_offset
+ * and result at result_offset for the device.
+ */
+ uint8_t dev_data[96];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_set_output (size:128b/16B) */
+struct hwrm_tfc_tcam_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_tfc_tcam_get *
+ *********************/
+
+
+/* hwrm_tfc_tcam_get_input (size:192b/24B) */
+struct hwrm_tfc_tcam_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * Subtype of TCAM resource See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* unused. */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_get_output (size:2368b/296B) */
+struct hwrm_tfc_tcam_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Number of bytes in the TCAM result. */
+ uint16_t result_size;
+ /* unused. */
+ uint8_t unused0[4];
+ /*
+ * TCAM key located at offset 0, mask located at key_size
+ * and result at 2 * key_size for the device.
+ */
+ uint8_t dev_data[272];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_tfc_tcam_alloc *
+ ***********************/
+
+
+/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */
+struct hwrm_tfc_tcam_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Entry priority. */
+ uint16_t priority;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tcam_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_tfc_tcam_alloc_set *
+ ***************************/
+
+
+/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */
+struct hwrm_tfc_tcam_alloc_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate device data is being sent via DMA. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* The size of the TCAM table entry in bytes. */
+ uint16_t result_size;
+ /* Entry priority. */
+ uint16_t priority;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused */
+ uint8_t unused[5];
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[96];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */
+struct hwrm_tfc_tcam_alloc_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_tfc_tcam_free *
+ **********************/
+
+
+/* hwrm_tfc_tcam_free_input (size:192b/24B) */
+struct hwrm_tfc_tcam_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
/* Control flags. */
- uint16_t flags;
+ uint8_t flags;
/* Indicates the flow direction. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
/* If this bit is set to 1, then it indicates tx flow. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
- /* unused. */
- uint8_t unused0[2];
- /*
- * Type of the resource, defined globally in the
- * hwrm_tf_resc_type enum.
- */
- uint32_t type;
- /* Index of the type to set. */
- uint32_t index;
- /* Size of the data to set. */
- uint16_t size;
- /* unused */
- uint8_t unused1[6];
- /* Data to be set. */
- uint8_t data[88];
-} __rte_packed;
-
-/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
-struct hwrm_tf_if_tbl_set_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* unused. */
- uint8_t unused0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal
- * processor, the order of writes has to be such that this field
- * is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/*****************************
- * hwrm_tf_tbl_type_bulk_get *
- *****************************/
-
-
-/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
-struct hwrm_tf_tbl_type_bulk_get_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
*/
- uint16_t cmpl_ring;
+ uint8_t subtype;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
*/
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
- uint32_t fw_session_id;
- /* Control flags. */
- uint16_t flags;
- /* Indicates the flow direction. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
- UINT32_C(0x1)
- /* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
- UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates tx flow. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
- UINT32_C(0x1)
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
- /*
- * When set use the special access register access to clear
- * the table entries on read.
- */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
- UINT32_C(0x2)
- /* unused. */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Reserved */
uint8_t unused0[2];
- /*
- * Type of the resource, defined globally in the
- * hwrm_tf_resc_type enum.
- */
- uint32_t type;
- /* Starting index of the type to retrieve. */
- uint32_t start_index;
- /* Number of entries to retrieve. */
- uint32_t num_entries;
- /* Number of entries to retrieve. */
- uint32_t unused1;
- /* Host memory where data will be stored. */
- uint64_t host_addr;
} __rte_packed;
-/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
-struct hwrm_tf_tbl_type_bulk_get_output {
+/* hwrm_tfc_tcam_free_output (size:128b/16B) */
+struct hwrm_tfc_tcam_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -52433,12 +56664,8 @@ struct hwrm_tf_tbl_type_bulk_get_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Response code. */
- uint32_t resp_code;
- /* Response size. */
- uint16_t size;
- /* unused */
- uint8_t unused0;
+ /* Reserved */
+ uint8_t unused0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52505,8 +56732,20 @@ struct hwrm_tunnel_dst_port_query_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0[7];
} __rte_packed;
@@ -52538,7 +56777,38 @@ struct hwrm_tunnel_dst_port_query_output {
* configured.
*/
uint16_t tunnel_dst_port_val;
- uint8_t unused_0[3];
+ /*
+ * This field represents the UPAR usage status.
+ * Available UPARs on wh+ are UPAR0 and UPAR1
+ * Available UPARs on Thor are UPAR0 to UPAR3
+ * Available UPARs on Thor2 are UPAR0 to UPAR7
+ */
+ uint8_t upar_in_use;
+ /* This bit will be '1' when UPAR0 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 \
+ UINT32_C(0x1)
+ /* This bit will be '1' when UPAR1 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 \
+ UINT32_C(0x2)
+ /* This bit will be '1' when UPAR2 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 \
+ UINT32_C(0x4)
+ /* This bit will be '1' when UPAR3 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 \
+ UINT32_C(0x8)
+ /* This bit will be '1' when UPAR4 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 \
+ UINT32_C(0x10)
+ /* This bit will be '1' when UPAR5 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 \
+ UINT32_C(0x20)
+ /* This bit will be '1' when UPAR6 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 \
+ UINT32_C(0x40)
+ /* This bit will be '1' when UPAR7 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \
+ UINT32_C(0x80)
+ uint8_t unused_0[2];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52604,8 +56874,20 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -52636,7 +56918,51 @@ struct hwrm_tunnel_dst_port_alloc_output {
* types that has l4 destination port parameters.
*/
uint16_t tunnel_dst_port_id;
- uint8_t unused_0[5];
+ /* Error information */
+ uint8_t error_info;
+ /* No error */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS \
+ UINT32_C(0x0)
+ /* Tunnel port is already allocated */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED \
+ UINT32_C(0x1)
+ /* Out of resources error */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \
+ UINT32_C(0x2)
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \
+ HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE
+ /*
+ * This field represents the UPAR usage status.
+ * Available UPARs on wh+ are UPAR0 and UPAR1
+ * Available UPARs on Thor are UPAR0 to UPAR3
+ * Available UPARs on Thor2 are UPAR0 to UPAR7
+ */
+ uint8_t upar_in_use;
+ /* This bit will be '1' when UPAR0 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 \
+ UINT32_C(0x1)
+ /* This bit will be '1' when UPAR1 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 \
+ UINT32_C(0x2)
+ /* This bit will be '1' when UPAR2 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 \
+ UINT32_C(0x4)
+ /* This bit will be '1' when UPAR3 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 \
+ UINT32_C(0x8)
+ /* This bit will be '1' when UPAR4 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 \
+ UINT32_C(0x10)
+ /* This bit will be '1' when UPAR5 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 \
+ UINT32_C(0x20)
+ /* This bit will be '1' when UPAR6 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 \
+ UINT32_C(0x40)
+ /* This bit will be '1' when UPAR7 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 \
+ UINT32_C(0x80)
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52702,8 +57028,20 @@ struct hwrm_tunnel_dst_port_free_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -52723,7 +57061,20 @@ struct hwrm_tunnel_dst_port_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_1[7];
+ /* Error information */
+ uint8_t error_info;
+ /* No error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS \
+ UINT32_C(0x0)
+ /* Not owner error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER \
+ UINT32_C(0x1)
+ /* Not allocated error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED \
+ UINT32_C(0x2)
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST \
+ HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED
+ uint8_t unused_1[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -53534,6 +57885,185 @@ struct pcie_ctx_hw_stats {
uint64_t pcie_recovery_histogram;
} __rte_packed;
+/****************************
+ * hwrm_stat_generic_qstats *
+ ****************************/
+
+
+/* hwrm_stat_generic_qstats_input (size:256b/32B) */
+struct hwrm_stat_generic_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The size of the generic statistics buffer passed in the
+ * generic_stat_host_addr in bytes.
+ * Firmware will not exceed this size when it DMAs the
+ * statistics structure to the host. The actual DMA size
+ * will be returned in the response.
+ */
+ uint16_t generic_stat_size;
+ uint8_t flags;
+ /*
+ * The bit should be set to 1 when request is for the counter mask
+ * representing the width of each of the stats counters, rather
+ * than counters themselves.
+ */
+ #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK \
+ UINT32_C(0x1)
+ uint8_t unused_0[5];
+ /*
+ * This is the host address where
+ * generic statistics will be stored
+ */
+ uint64_t generic_stat_host_addr;
+} __rte_packed;
+
+/* hwrm_stat_generic_qstats_output (size:128b/16B) */
+struct hwrm_stat_generic_qstats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of Generic Statistics block in bytes. */
+ uint16_t generic_stat_size;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* Generic Statistic Format */
+/* generic_sw_hw_stats (size:1408b/176B) */
+struct generic_sw_hw_stats {
+ /*
+ * This is the number of TLP bytes that have been transmitted for
+ * the caller PF.
+ */
+ uint64_t pcie_statistics_tx_tlp;
+ /*
+ * This is the number of TLP bytes that have been received
+ * for the caller PF.
+ */
+ uint64_t pcie_statistics_rx_tlp;
+ /* Posted Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_posted;
+ /* Non-posted Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_nonposted;
+ /* Completion Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_cmpl;
+ /* Posted Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_posted;
+ /* Non-Posted Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_nonposted;
+ /* Completion Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_cmpl;
+ /*
+ * Available Non-posted credit for target flow control reads or
+ * config for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_nonposted;
+ /*
+ * Available posted data credit for target flow control writes
+ * for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_data_posted;
+ /*
+ * Available posted header credit for target flow control writes
+ * for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_hdr_posted;
+ /* Available completion flow control header credits for the caller PF. */
+ uint64_t pcie_credit_fc_cmpl_hdr_posted;
+ /* Available completion flow control data credits. */
+ uint64_t pcie_credit_fc_cmpl_data_posted;
+ /*
+ * Displays Time information of the longest completon time from any of
+ * the 4 tags for the caller PF. The unit of time recorded is in
+ * microseconds.
+ */
+ uint64_t pcie_cmpl_longest;
+ /*
+ * Displays Time information of the shortest completon time from any of
+ * the 4 tags for the caller PF. The unit of time recorded is in
+ * microseconds.
+ */
+ uint64_t pcie_cmpl_shortest;
+ /*
+ * This field contains the total number of CFCQ 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcq;
+ /*
+ * This field contains the total number of CFCS 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcs;
+ /*
+ * This field contains the total number of CFCC 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcc;
+ /*
+ * This field contains the total number of CFCM 'misses' observed
+ * for all the PF's.
+ */
+ uint64_t cache_miss_count_cfcm;
+ /*
+ * Total number of Doorbell messages dropped from the DB FIFO.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_dbs_dropped;
+ /*
+ * Total number of doorbell drops serviced.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_drops_serviced;
+ /*
+ * Total number of dropped doorbells recovered.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_dbs_recovered;
+} __rte_packed;
+
/**********************
* hwrm_exec_fwd_resp *
**********************/
@@ -55174,8 +59704,11 @@ struct hwrm_nvm_install_update_cmd_err {
/* Firmware update failed due to Anti-rollback. */
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
UINT32_C(0x3)
+ /* Firmware update does not support voltage regulators on the device. */
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT \
+ UINT32_C(0x4)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
- HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
+ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT
uint8_t unused_0[7];
} __rte_packed;
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 03/11] net/bnxt: update copyright date and cleanup whitespace
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 01/11] net/bnxt: remove deprecated features Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
` (8 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Kishore Padmanabha
[-- Attachment #1: Type: text/plain, Size: 46733 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Update the Copyright to 2023
Clean up extra blank lines
Clean up other whitespace issues
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_cpr.c | 2 +-
drivers/net/bnxt/bnxt_cpr.h | 2 +-
drivers/net/bnxt/bnxt_filter.c | 2 +-
drivers/net/bnxt/bnxt_irq.c | 2 +-
drivers/net/bnxt/bnxt_irq.h | 2 +-
drivers/net/bnxt/bnxt_nvm_defs.h | 2 +-
drivers/net/bnxt/bnxt_reps.h | 2 +-
drivers/net/bnxt/bnxt_ring.h | 2 +-
drivers/net/bnxt/bnxt_rxq.h | 2 +-
drivers/net/bnxt/bnxt_rxr.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +-
drivers/net/bnxt/bnxt_stats.c | 2 +-
drivers/net/bnxt/bnxt_stats.h | 2 +-
drivers/net/bnxt/bnxt_txq.h | 2 +-
drivers/net/bnxt/bnxt_util.c | 2 +-
drivers/net/bnxt/bnxt_util.h | 2 +-
drivers/net/bnxt/meson.build | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.c | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.h | 2 +-
drivers/net/bnxt/tf_core/bitalloc.c | 3 +--
drivers/net/bnxt/tf_core/bitalloc.h | 3 +--
drivers/net/bnxt/tf_core/cfa_resource_types.h | 3 +--
drivers/net/bnxt/tf_core/dpool.c | 3 ++-
drivers/net/bnxt/tf_core/dpool.h | 3 +--
drivers/net/bnxt/tf_core/ll.c | 2 +-
drivers/net/bnxt/tf_core/ll.h | 2 +-
drivers/net/bnxt/tf_core/lookup3.h | 1 -
drivers/net/bnxt/tf_core/rand.c | 2 +-
drivers/net/bnxt/tf_core/rand.h | 3 +--
drivers/net/bnxt/tf_core/stack.c | 2 +-
drivers/net/bnxt/tf_core/stack.h | 3 +--
drivers/net/bnxt/tf_core/tf_common.h | 3 +--
drivers/net/bnxt/tf_core/tf_core.h | 1 -
drivers/net/bnxt/tf_core/tf_device.h | 1 -
drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +--
drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +-
drivers/net/bnxt/tf_core/tf_em.h | 3 +--
drivers/net/bnxt/tf_core/tf_em_common.c | 8 +-------
drivers/net/bnxt/tf_core/tf_em_common.h | 4 +---
drivers/net/bnxt/tf_core/tf_em_hash_internal.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_host.c | 3 +--
drivers/net/bnxt/tf_core/tf_em_internal.c | 3 ++-
drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +---
drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +-
drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +--
drivers/net/bnxt/tf_core/tf_hash.c | 2 +-
drivers/net/bnxt/tf_core/tf_hash.h | 3 +--
drivers/net/bnxt/tf_core/tf_identifier.c | 2 +-
drivers/net/bnxt/tf_core/tf_identifier.h | 3 +--
drivers/net/bnxt/tf_core/tf_if_tbl.h | 3 +--
drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +--
drivers/net/bnxt/tf_core/tf_project.h | 3 +--
drivers/net/bnxt/tf_core/tf_resources.h | 3 +--
drivers/net/bnxt/tf_core/tf_rm.h | 6 +-----
drivers/net/bnxt/tf_core/tf_session.h | 1 -
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 1 -
drivers/net/bnxt/tf_core/tf_tbl.h | 4 +---
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +-----
drivers/net/bnxt/tf_core/tf_tcam.h | 3 +--
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 1 -
drivers/net/bnxt/tf_core/tf_util.c | 3 +--
drivers/net/bnxt/tf_core/tf_util.h | 3 +--
drivers/net/bnxt/tf_core/tfp.c | 2 +-
drivers/net/bnxt/tf_core/tfp.h | 4 +---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +--
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 -
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +--
87 files changed, 73 insertions(+), 135 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c
index 5bb376d4d5..0733cf4df2 100644
--- a/drivers/net/bnxt/bnxt_cpr.c
+++ b/drivers/net/bnxt/bnxt_cpr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index dab6bed2ae..2de154322d 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c
index b0c3bbd1b2..ff563f08bb 100644
--- a/drivers/net/bnxt/bnxt_filter.c
+++ b/drivers/net/bnxt/bnxt_filter.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_irq.c b/drivers/net/bnxt/bnxt_irq.c
index 508abfc844..71d1565e08 100644
--- a/drivers/net/bnxt/bnxt_irq.c
+++ b/drivers/net/bnxt/bnxt_irq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h
index 53d9198858..e498578968 100644
--- a/drivers/net/bnxt/bnxt_irq.h
+++ b/drivers/net/bnxt/bnxt_irq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h
index bb45d7e472..f5ac4e8c84 100644
--- a/drivers/net/bnxt/bnxt_nvm_defs.h
+++ b/drivers/net/bnxt/bnxt_nvm_defs.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h
index 01e57ee5b5..3f2db9d1ae 100644
--- a/drivers/net/bnxt/bnxt_reps.h
+++ b/drivers/net/bnxt/bnxt_reps.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index ef9586e64e..3d747aba54 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index a97037c6e0..b9908be5f4 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index a84f016609..e132166a18 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
index 34bd22edf0..d4e8e8eb87 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_common.h b/drivers/net/bnxt/bnxt_rxtx_vec_common.h
index 0627fd212d..2294f0aa3c 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_common.h
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2020-2021 Broadcom
+ * Copyright(c) 2020-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
index 6a4ece681b..aa1b1ab8bb 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
index ffd560166c..2ad8591b90 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c
index 72169e8b35..0e25207fc3 100644
--- a/drivers/net/bnxt/bnxt_stats.c
+++ b/drivers/net/bnxt/bnxt_stats.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_stats.h b/drivers/net/bnxt/bnxt_stats.h
index 1ca9b9c594..e46c05eed3 100644
--- a/drivers/net/bnxt/bnxt_stats.h
+++ b/drivers/net/bnxt/bnxt_stats.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txq.h b/drivers/net/bnxt/bnxt_txq.h
index f3a03812ad..3a483ad5c3 100644
--- a/drivers/net/bnxt/bnxt_txq.h
+++ b/drivers/net/bnxt/bnxt_txq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_util.c b/drivers/net/bnxt/bnxt_util.c
index 3167894789..47dd5fa6ff 100644
--- a/drivers/net/bnxt/bnxt_util.c
+++ b/drivers/net/bnxt/bnxt_util.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h
index b243c21ec2..3437dc75ae 100644
--- a/drivers/net/bnxt/bnxt_util.h
+++ b/drivers/net/bnxt/bnxt_util.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 96fa06a358..ead03a5ea3 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2020 Broadcom
+# Copyright(c) 2023 Broadcom
if is_windows
build = false
diff --git a/drivers/net/bnxt/rte_pmd_bnxt.c b/drivers/net/bnxt/rte_pmd_bnxt.c
index ffa1114046..964a5aeb05 100644
--- a/drivers/net/bnxt/rte_pmd_bnxt.c
+++ b/drivers/net/bnxt/rte_pmd_bnxt.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Broadcom
+ * Copyright(c) 2017-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/rte_pmd_bnxt.h b/drivers/net/bnxt/rte_pmd_bnxt.h
index 174c18a0f3..2077026903 100644
--- a/drivers/net/bnxt/rte_pmd_bnxt.h
+++ b/drivers/net/bnxt/rte_pmd_bnxt.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Broadcom
+ * Copyright(c) 2017-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/bitalloc.c b/drivers/net/bnxt/tf_core/bitalloc.c
index e253cfc3a6..136263b6a4 100644
--- a/drivers/net/bnxt/tf_core/bitalloc.c
+++ b/drivers/net/bnxt/tf_core/bitalloc.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -7,7 +7,6 @@
#define BITALLOC_MAX_LEVELS 6
-
/* Finds the last bit set plus 1, equivalent to gcc __builtin_fls */
static int
ba_fls(bitalloc_word_t v)
diff --git a/drivers/net/bnxt/tf_core/bitalloc.h b/drivers/net/bnxt/tf_core/bitalloc.h
index db8a09abdd..bf15cbc87b 100644
--- a/drivers/net/bnxt/tf_core/bitalloc.h
+++ b/drivers/net/bnxt/tf_core/bitalloc.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -121,5 +121,4 @@ int ba_free_count(struct bitalloc *pool);
* Returns the pool's in use count
*/
int ba_inuse_count(struct bitalloc *pool);
-
#endif /* _BITALLOC_H_ */
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 36a55d4e17..874d7b834f 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -256,5 +256,4 @@
/* Table Scope */
#define CFA_RESOURCE_TYPE_P4_TBL_SCOPE 0x22UL
#define CFA_RESOURCE_TYPE_P4_LAST CFA_RESOURCE_TYPE_P4_TBL_SCOPE
-
#endif /* _CFA_RESOURCE_TYPES_H_ */
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 5c03f775a5..f60c04e949 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <stdio.h>
@@ -55,6 +55,7 @@ static int dpool_move(struct dpool *dpool,
{
uint32_t size;
uint32_t i;
+
if (DP_IS_FREE(dpool->entry[dst_index].flags)) {
size = DP_FLAGS_SIZE(dpool->entry[src_index].flags);
diff --git a/drivers/net/bnxt/tf_core/dpool.h b/drivers/net/bnxt/tf_core/dpool.h
index fb79c7be4b..2e64916bf6 100644
--- a/drivers/net/bnxt/tf_core/dpool.h
+++ b/drivers/net/bnxt/tf_core/dpool.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -305,5 +305,4 @@ void dpool_dump(struct dpool *dpool);
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag);
-
#endif /* _DPOOL_H_ */
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index f2bdff6b9e..75b096aa08 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 9cf8f64ec2..89271b7243 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/lookup3.h b/drivers/net/bnxt/tf_core/lookup3.h
index 743c4d9c4f..a937de4a16 100644
--- a/drivers/net/bnxt/tf_core/lookup3.h
+++ b/drivers/net/bnxt/tf_core/lookup3.h
@@ -157,5 +157,4 @@ static inline uint32_t hashword(const uint32_t *k,
/*------------------------------------------------- report the result */
return c;
}
-
#endif /* _LOOKUP3_H_ */
diff --git a/drivers/net/bnxt/tf_core/rand.c b/drivers/net/bnxt/tf_core/rand.c
index d419d7257b..07d4aff750 100644
--- a/drivers/net/bnxt/tf_core/rand.c
+++ b/drivers/net/bnxt/tf_core/rand.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/rand.h b/drivers/net/bnxt/tf_core/rand.h
index 80b2ab3ecd..656bd58868 100644
--- a/drivers/net/bnxt/tf_core/rand.h
+++ b/drivers/net/bnxt/tf_core/rand.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -32,5 +32,4 @@ uint32_t rand32(void);
*
*/
void rand_init(void);
-
#endif /* __RAND_H__ */
diff --git a/drivers/net/bnxt/tf_core/stack.c b/drivers/net/bnxt/tf_core/stack.c
index db79461db9..d2e200b4f4 100644
--- a/drivers/net/bnxt/tf_core/stack.c
+++ b/drivers/net/bnxt/tf_core/stack.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/stack.h b/drivers/net/bnxt/tf_core/stack.h
index 358233279c..f9a748574c 100644
--- a/drivers/net/bnxt/tf_core/stack.h
+++ b/drivers/net/bnxt/tf_core/stack.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#ifndef _STACK_H_
@@ -113,5 +113,4 @@ int stack_pop(struct stack *st, uint32_t *x);
* none
*/
void stack_dump(struct stack *st);
-
#endif /* _STACK_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_common.h b/drivers/net/bnxt/tf_core/tf_common.h
index abdd390b4f..0bfb7f1f33 100644
--- a/drivers/net/bnxt/tf_core/tf_common.h
+++ b/drivers/net/bnxt/tf_core/tf_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2020-2021 Broadcom
+ * Copyright(c) 2020-2023 Broadcom
* All rights reserved.
*/
@@ -39,5 +39,4 @@
return -EINVAL; \
} \
} while (0)
-
#endif /* _TF_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 814eff68da..f5fe0a9098 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -2481,5 +2481,4 @@ struct tf_get_sram_policy_parms {
*/
int tf_get_sram_policy(struct tf *tfp,
struct tf_get_sram_policy_parms *parms);
-
#endif /* _TF_CORE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index bc6de60423..5a42180719 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -1142,5 +1142,4 @@ extern const struct tf_dev_ops tf_dev_ops_p58;
*/
extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1];
extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1];
-
#endif /* _TF_DEVICE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index 86de525995..20da2f97db 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -181,5 +181,4 @@ const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST
TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE
},
};
-
#endif /* _TF_DEVICE_P4_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 61c856b767..858d975f11 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 074c128651..97cdb48f14 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -8,7 +8,6 @@
#include "tf_core.h"
#include "tf_session.h"
-
#include "tf_em_common.h"
#include "hcapi_cfa_defs.h"
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 3bdfc14e05..b56b7cc188 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -9,7 +9,6 @@
#include <rte_common.h>
#include <rte_errno.h>
#include <rte_log.h>
-
#include "tf_core.h"
#include "tf_util.h"
#include "tf_common.h"
@@ -20,10 +19,8 @@
#include "tf_device.h"
#include "tf_ext_flow_handle.h"
#include "hcapi_cfa.h"
-
#include "bnxt.h"
-
/** Invalid table scope id */
#define TF_TBL_SCOPE_INVALID 0xffffffff
@@ -285,7 +282,6 @@ tf_em_create_key_entry(struct cfa_p4_eem_entry_hdr *result,
memcpy(key_entry->key, in_key, TF_P4_HW_EM_KEY_MAX_SIZE + 4);
}
-
/**
* Return the number of page table pages needed to
* reference the given number of next level pages.
@@ -908,7 +904,6 @@ tf_em_delete_ext_entry(struct tf *tfp,
return tf_delete_eem_entry(tbl_scope_cb, parms);
}
-
int
tf_em_ext_common_bind(struct tf *tfp,
struct tf_em_cfg_parms *parms)
@@ -1204,7 +1199,6 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp,
gcfg_parms.config_mask = (uint8_t *)mask;
gcfg_parms.config_sz_in_bytes = sizeof(uint64_t);
-
rc = tf_msg_set_global_cfg(tfp, &gcfg_parms);
if (rc) {
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h
index 7f215adef2..0ae95f260a 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.h
+++ b/drivers/net/bnxt/tf_core/tf_em_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -178,7 +178,6 @@ int tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb,
int tf_em_size_table(struct hcapi_cfa_em_table *tbl,
uint32_t page_size);
-
/**
* Look up table scope control block using tbl_scope_id from
* tf_session
@@ -196,5 +195,4 @@ int tf_em_size_table(struct hcapi_cfa_em_table *tbl,
struct tf_tbl_scope_cb *
tf_em_ext_common_tbl_scope_find(struct tf *tfp,
uint32_t tbl_scope_id);
-
#endif /* _TF_EM_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 60273a798c..d72ac83295 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index 869a78e904..9efffe4ee5 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -376,7 +376,6 @@ tf_em_ext_alloc(struct tf *tfp,
void *ext_ptr = NULL;
uint16_t pf;
-
rc = tf_session_get_session_internal(tfp, &tfs);
if (rc) {
TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n",
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 67ba011eae..8ea5d93672 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -15,6 +15,7 @@
#include "tf_msg.h"
#include "tfp.h"
#include "tf_ext_flow_handle.h"
+
#include "bnxt.h"
#define TF_EM_DB_EM_REC 0
diff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
index bf6dbcd238..8f967c5c85 100644
--- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
+++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -184,6 +184,4 @@ do { \
type = (((gfid) & TF_HASH_TYPE_GFID_MASK) >> \
TF_HASH_TYPE_GFID_SFT); \
} while (0)
-
-
#endif /* _TF_EXT_FLOW_HANDLE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.c b/drivers/net/bnxt/tf_core/tf_global_cfg.c
index d83e7db315..3a8030a2fb 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.c
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.h b/drivers/net/bnxt/tf_core/tf_global_cfg.h
index c14e5e9109..f57f3313da 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.h
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -146,5 +146,4 @@ int tf_global_cfg_set(struct tf *tfp,
*/
int tf_global_cfg_get(struct tf *tfp,
struct tf_global_cfg_parms *parms);
-
#endif /* TF_GLOBAL_CFG_H */
diff --git a/drivers/net/bnxt/tf_core/tf_hash.c b/drivers/net/bnxt/tf_core/tf_hash.c
index a722821f05..b402dc8a12 100644
--- a/drivers/net/bnxt/tf_core/tf_hash.c
+++ b/drivers/net/bnxt/tf_core/tf_hash.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_hash.h b/drivers/net/bnxt/tf_core/tf_hash.h
index d128269b54..0c082f5fd6 100644
--- a/drivers/net/bnxt/tf_core/tf_hash.h
+++ b/drivers/net/bnxt/tf_core/tf_hash.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -23,5 +23,4 @@ tf_hash_calc_crc32i(uint32_t init, uint8_t *buf, uint32_t len);
*/
uint32_t
tf_hash_calc_crc32(uint8_t *buf, uint32_t len);
-
#endif
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index 8131d8754d..1846675916 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h
index 285ff11ce2..48ca63a58d 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.h
+++ b/drivers/net/bnxt/tf_core/tf_identifier.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -212,5 +212,4 @@ int tf_ident_search(struct tf *tfp,
*/
int tf_ident_get_resc_info(struct tf *tfp,
struct tf_identifier_resource_info *parms);
-
#endif /* _TF_IDENTIFIER_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h
index bea2f07324..bb536c31d1 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -224,5 +224,4 @@ int tf_if_tbl_set(struct tf *tfp,
*/
int tf_if_tbl_get(struct tf *tfp,
struct tf_if_tbl_get_parms *parms);
-
#endif /* TF_IF_TBL_TYPE_H */
diff --git a/drivers/net/bnxt/tf_core/tf_msg_common.h b/drivers/net/bnxt/tf_core/tf_msg_common.h
index 49f334717d..949062a42f 100644
--- a/drivers/net/bnxt/tf_core/tf_msg_common.h
+++ b/drivers/net/bnxt/tf_core/tf_msg_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -40,5 +40,4 @@
parms.resp_size = 0; \
parms.resp_data = NULL; \
} while (0)
-
#endif /* _TF_MSG_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_project.h b/drivers/net/bnxt/tf_core/tf_project.h
index 57285508fb..6357760f16 100644
--- a/drivers/net/bnxt/tf_core/tf_project.h
+++ b/drivers/net/bnxt/tf_core/tf_project.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -20,5 +20,4 @@
#ifndef TF_SHARED
#define TF_SHARED 0
#endif
-
#endif /* _TF_PROJECT_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h
index 2c1d738755..8c28d3dc68 100644
--- a/drivers/net/bnxt/tf_core/tf_resources.h
+++ b/drivers/net/bnxt/tf_core/tf_resources.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -7,5 +7,4 @@
#define _TF_RESOURCES_H_
#define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */
-
#endif /* _TF_RESOURCES_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index da7d0c7211..a4187891f4 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -43,7 +43,6 @@ struct tf;
* support module, not called directly.
*/
-
/**
* RM Element configuration enumeration. Used by the Device to
* indicate how the RM elements the DB consists off, are to be
@@ -75,8 +74,6 @@ enum tf_rm_elem_cfg_type {
* HCAPI type. Child accesses the parent db.
*/
TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
-
-
TF_RM_TYPE_MAX
};
@@ -581,5 +578,4 @@ tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
*/
int
tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
-
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index a6716dfff4..5a94b941fa 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -716,5 +716,4 @@ tf_session_set_if_tbl_db(struct tf *tfp,
int
tf_session_get_if_tbl_db(struct tf *tfp,
void **if_tbl_handle);
-
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
index eb2156456a..fc78426130 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -303,5 +303,4 @@ const char
*/
const char
*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
-
#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 2483718e5d..dfa3bcaa14 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -15,7 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-
/**
* Table configuration parameters
*/
@@ -327,5 +326,4 @@ int tf_tbl_bulk_get(struct tf *tfp,
int
tf_tbl_get_resc_info(struct tf *tfp,
struct tf_tbl_resource_info *tbl);
-
#endif /* TF_TBL_TYPE_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
index 32001e34a9..c109210ce9 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -9,12 +9,10 @@
#include "tf_core.h"
#include "stack.h"
-
/**
* The SRAM Table module provides processing of managed SRAM types.
*/
-
/**
* @page tblsram SRAM Table
*
@@ -99,7 +97,6 @@ int tf_tbl_sram_alloc(struct tf *tfp,
int tf_tbl_sram_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
@@ -150,5 +147,4 @@ int tf_tbl_sram_get(struct tf *tfp,
*/
int tf_tbl_sram_bulk_get(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
-
#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index 0ed2250464..1807edd092 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -374,5 +374,4 @@ int tf_tcam_get(struct tf *tfp,
*/
int tf_tcam_get_resc_info(struct tf *tfp,
struct tf_tcam_resource_info *parms);
-
#endif /* _TF_TCAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
index 020763af6b..524631f262 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
@@ -179,5 +179,4 @@ int tf_tcam_shared_move_p58(struct tf *tfp,
*/
int tf_tcam_shared_clear(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-
#endif /* _TF_TCAM_SHARED_H */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index 7d9de7c764..8ce8238b4a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -1,10 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include "tf_util.h"
const char *
diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h
index 854c51931a..f46480868b 100644
--- a/drivers/net/bnxt/tf_core/tf_util.h
+++ b/drivers/net/bnxt/tf_core/tf_util.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -93,5 +93,4 @@ const char *tf_module_subtype_2_str(enum tf_module_type module,
* Pointer to a char string holding the string for the EM type
*/
const char *tf_module_2_str(enum tf_module_type module);
-
#endif /* _TF_UTIL_H_ */
diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c
index a967a9ccf2..604141b689 100644
--- a/drivers/net/bnxt/tf_core/tfp.c
+++ b/drivers/net/bnxt/tf_core/tfp.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
* see the individual elements.
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h
index 5a99c7a06e..92f76004da 100644
--- a/drivers/net/bnxt/tf_core/tfp.h
+++ b/drivers/net/bnxt/tf_core/tfp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -185,7 +185,6 @@ void tfp_spinlock_unlock(struct tfp_spinlock_parms *slock);
*/
int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
-
/*
* @ref tfp_cpu_to_le_16
* @ref tfp_le_to_cpu_16
@@ -232,5 +231,4 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
*
*/
int tfp_get_pf(struct tf *tfp, uint16_t *pf);
-
#endif /* _TFP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index d006464a75..cd4cd8ac74 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -68,5 +68,4 @@ bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx);
int32_t
bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mark_tbl *mark_tbl);
-
#endif /* _BNXT_TF_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index 229e21814b..d6d7a1f0af 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -25,5 +25,4 @@ uint16_t bnxt_pmd_get_phy_port_id(uint16_t port);
uint16_t bnxt_pmd_get_vport(uint16_t port);
enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port);
int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev);
-
#endif /* _BNXT_TF_PMD_ABSTRACT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 05a98b14e6..906d933af5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -317,5 +317,4 @@ bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
-
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 9825ed2a27..9df5ae51a3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -184,5 +184,4 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
uint32_t pc_idx);
-
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 2b02836a40..ada34c0e6c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -410,5 +410,4 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
-
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
index 84c83de35c..d746fbbd4e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
index 543ef79d30..d3f3840cbe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -162,5 +162,4 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl,
int32_t
ulp_gen_hash_tbl_list_del(struct ulp_gen_hash_tbl *hash_tbl,
struct ulp_gen_hash_entry_params *entry);
-
#endif /* _ULP_GEN_HASH_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
index f245825142..3060072967 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
@@ -167,5 +167,4 @@ int32_t
ulp_mapper_gen_tbl_hash_entry_add(struct ulp_mapper_gen_tbl_list *tbl_list,
struct ulp_gen_hash_entry_params *hash_entry,
struct ulp_mapper_gen_tbl_entry *gen_tbl_ent);
-
#endif /* _ULP_EN_TBL_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
index 793511564a..ded967a0af 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
@@ -63,5 +63,4 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx);
int32_t
ulp_ha_mgr_region_get(struct bnxt_ulp_context *ulp_ctx,
enum ulp_ha_mgr_region *region);
-
#endif /* _ULP_HA_MGR_H_*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 4d6ba0f73a..b7e6f3ada2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -133,5 +133,4 @@ ulp_mapper_get_shared_fid(struct bnxt_ulp_context *ulp,
uint32_t id,
uint16_t key,
uint32_t *fid);
-
#endif /* _ULP_MAPPER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 9dffaef73b..1cfb21782c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
index d9d82d4644..2a1f3ad615 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -112,5 +112,4 @@ int32_t
ulp_mark_db_mark_del(struct bnxt_ulp_context *ctxt,
uint32_t mark_flag,
uint32_t gfid);
-
#endif /* _ULP_MARK_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
index dc2487889c..47a9e8e0eb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -27,5 +27,4 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
int32_t
ulp_matcher_action_match(struct ulp_rte_parser_params *params,
uint32_t *act_id);
-
#endif /* ULP_MATCHER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index b112f1a216..f575a3c2e2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -326,5 +326,4 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
int32_t
ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint16_t *phy_port);
-
#endif /* _ULP_PORT_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index f59b10e88b..b0b2b4f33f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -259,5 +259,4 @@ ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
-
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 7d1bc06a3e..3dcc6dbc0c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -441,5 +441,4 @@ extern struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[];
* that could be reused by other templates.
*/
extern uint32_t ulp_glb_template_tbl[];
-
#endif /* _ULP_TEMPLATE_STRUCT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index 7ce6740633..3be3475a83 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 0fc2ac39d1..b60aa1efbe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -57,5 +57,4 @@ ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
int32_t
ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
-
#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index c60d81d14a..6fb2e3f2ad 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 68a537fa0a..e9ccee7bf4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -522,5 +522,4 @@ uint32_t ulp_bitmap_notzero(const uint8_t *bitmap, int32_t size);
/* returns 0 if input is power of 2 */
int32_t ulp_util_is_power_of_2(uint64_t x);
-
#endif /* _ULP_UTILS_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 04/11] net/bnxt: update Truflow core
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (2 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-06-10 18:32 ` Thomas Monjalon
2023-05-04 17:36 ` [PATCH v3 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
` (7 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Farah Smith, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 303760 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Update TruFlow core code to:
- Add shared session management
- Add SRAM session management
- Add dynamic TCAM management
- Add shared TCAM session management
- Add Hot Upgrade support
- Update copyright year
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 -
drivers/net/bnxt/bnxt_irq.h | 1 -
drivers/net/bnxt/bnxt_nvm_defs.h | 1 -
drivers/net/bnxt/bnxt_ring.h | 1 -
drivers/net/bnxt/bnxt_rxr.h | 1 -
drivers/net/bnxt/bnxt_txr.h | 1 -
drivers/net/bnxt/bnxt_util.h | 1 -
drivers/net/bnxt/tf_core/cfa_resource_types.h | 2 -
drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +++++++++++++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 ++++
.../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 ++
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 ++++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +++
.../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 +
drivers/net/bnxt/tf_core/meson.build | 36 +-
drivers/net/bnxt/tf_core/tf_core.c | 54 +-
drivers/net/bnxt/tf_core/tf_core.h | 97 +-
drivers/net/bnxt/tf_core/tf_device.c | 18 +-
drivers/net/bnxt/tf_core/tf_device.h | 2 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 14 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 84 +-
drivers/net/bnxt/tf_core/tf_em_common.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_internal.c | 10 +-
drivers/net/bnxt/tf_core/tf_identifier.c | 1 +
drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +-
drivers/net/bnxt/tf_core/tf_msg.c | 217 +-
drivers/net/bnxt/tf_core/tf_msg.h | 38 +-
drivers/net/bnxt/tf_core/tf_rm.c | 117 +-
drivers/net/bnxt/tf_core/tf_session.c | 112 +-
drivers/net/bnxt/tf_core/tf_session.h | 65 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 22 +-
drivers/net/bnxt/tf_core/tf_tbl.c | 8 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +-
drivers/net/bnxt/tf_core/tf_tcam.c | 226 +-
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +++
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +--------
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 +-
46 files changed, 6686 insertions(+), 1552 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 48bd8f2418..2bccdec7e0 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1044,5 +1044,4 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
-
#endif
diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h
index e498578968..e2d61bae7a 100644
--- a/drivers/net/bnxt/bnxt_irq.h
+++ b/drivers/net/bnxt/bnxt_irq.h
@@ -20,5 +20,4 @@ void bnxt_enable_int(struct bnxt *bp);
int bnxt_setup_int(struct bnxt *bp);
int bnxt_request_int(struct bnxt *bp);
void bnxt_int_handler(void *param);
-
#endif
diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h
index f5ac4e8c84..57ddefa7a1 100644
--- a/drivers/net/bnxt/bnxt_nvm_defs.h
+++ b/drivers/net/bnxt/bnxt_nvm_defs.h
@@ -66,5 +66,4 @@ enum bnxnvm_pkglog_field_index {
BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
};
-
#endif /* Don't add anything after this line */
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 3d747aba54..baa60b2627 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -142,5 +142,4 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr)
B_CP_DIS_DB(cpr, cp_raw_cons);
}
}
-
#endif
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index e132166a18..8e722b7bf0 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -386,5 +386,4 @@ bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
mbuf->packet_type = pkt_type;
}
-
#endif /* _BNXT_RXR_H_ */
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index e11343c082..75456df5bd 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -90,5 +90,4 @@ int bnxt_flush_tx_cmp(struct bnxt_cp_ring_info *cpr);
TX_BD_LONG_LFLAGS_IP_CHKSUM)
#define TX_BD_FLG_TIP_TCP_UDP_CHKSUM (TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM | \
TX_BD_LONG_LFLAGS_T_IP_CHKSUM)
-
#endif
diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h
index 3437dc75ae..7f5b4c160e 100644
--- a/drivers/net/bnxt/bnxt_util.h
+++ b/drivers/net/bnxt/bnxt_util.h
@@ -17,5 +17,4 @@
int bnxt_check_zero_bytes(const uint8_t *bytes, int len);
void bnxt_eth_hw_addr_random(uint8_t *mac_addr);
-
#endif /* _BNXT_UTIL_H_ */
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 874d7b834f..8431c778e4 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -63,7 +63,6 @@
#define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x18UL
#define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM
-
/* Meter */
#define CFA_RESOURCE_TYPE_P58_METER 0x0UL
/* SRAM_Bank_0 */
@@ -184,7 +183,6 @@
#define CFA_RESOURCE_TYPE_P45_TBL_SCOPE 0x23UL
#define CFA_RESOURCE_TYPE_P45_LAST CFA_RESOURCE_TYPE_P45_TBL_SCOPE
-
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P4_MCG 0x0UL
/* Encap 8 byte record */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
new file mode 100644
index 0000000000..f26d93e7a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
@@ -0,0 +1,2116 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <inttypes.h>
+#include <signal.h>
+
+#include "hcapi_cfa_defs.h"
+
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_util.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_hwop_msg.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_session.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+
+#define TF_TCAM_SLICE_INVALID (-1)
+
+/*
+ * The following macros are for setting the entry status in a row entry.
+ * row is (struct cfa_tcam_mgr_table_rows_0 *)
+ */
+#define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry)))
+#define ROW_ENTRY_SET(row, entry) ((row)->entry_inuse |= (1U << (entry)))
+#define ROW_ENTRY_CLEAR(row, entry) ((row)->entry_inuse &= ~(1U << (entry)))
+#define ROW_INUSE(row) ((row)->entry_inuse != 0)
+
+static struct cfa_tcam_mgr_entry_data *entry_data[TF_TCAM_MAX_SESSIONS];
+
+static int global_data_initialized[TF_TCAM_MAX_SESSIONS];
+int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+static int physical_table_types[CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS] =
+ TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS] =
+ TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_PROF_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_SP_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_CT_RULE_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_VEB_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM_HIGH,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM_LOW,
+};
+
+int
+cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type)
+{
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return physical_table_types[type];
+}
+
+const char *
+cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type)
+{
+ switch (tcam_type) {
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM:
+ return "l2_ctxt_tcam_high AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS:
+ return "l2_ctxt_tcam_high Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM:
+ return "l2_ctxt_tcam_low AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS:
+ return "l2_ctxt_tcam_low Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM:
+ return "prof_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS:
+ return "prof_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM:
+ return "wc_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS:
+ return "wc_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM:
+ return "veb_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS:
+ return "veb_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM:
+ return "sp_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS:
+ return "sp_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM:
+ return "ct_rule_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS:
+ return "ct_rule_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM:
+ return "wc_tcam_high AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS:
+ return "wc_tcam_high Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM:
+ return "wc_tcam_low AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS:
+ return "wc_tcam_low Apps";
+ default:
+ return "Invalid tcam table type";
+ }
+}
+
+/* key_size and slice_width are in bytes */
+static int
+cfa_tcam_mgr_get_num_slices(unsigned int key_size, unsigned int slice_width)
+{
+ int num_slices = 0;
+
+ if (key_size == 0)
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ num_slices = ((key_size - 1U) / slice_width) + 1U;
+ /* Round up to next highest power of 2 */
+ /* This is necessary since, for example, 3 slices is not a valid entry
+ * width.
+ */
+ num_slices--;
+ /* Repeat to maximum number of bits actually used */
+ /* This fills in all the bits. */
+ num_slices |= num_slices >> 1;
+ num_slices |= num_slices >> 2;
+ num_slices |= num_slices >> 4;
+ /*
+ * If the maximum number of slices that are supported by the HW
+ * increases, then additional shifts are needed.
+ */
+ num_slices++;
+ return num_slices;
+}
+
+static struct cfa_tcam_mgr_entry_data *
+cfa_tcam_mgr_entry_get(int sess_idx, uint16_t id)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return NULL;
+
+ return &entry_data[sess_idx][id];
+}
+
+/* Insert an entry into the entry table */
+static int
+cfa_tcam_mgr_entry_insert(int sess_idx, uint16_t id,
+ struct cfa_tcam_mgr_entry_data *entry)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ memcpy(&entry_data[sess_idx][id], entry,
+ sizeof(entry_data[sess_idx][id]));
+
+ return 0;
+}
+
+/* Delete an entry from the entry table */
+static int
+cfa_tcam_mgr_entry_delete(int sess_idx, uint16_t id)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ memset(&entry_data[sess_idx][id], 0, sizeof(entry_data[sess_idx][id]));
+
+ return 0;
+}
+
+/* Returns the size of the row structure taking into account how many slices a
+ * TCAM supports.
+ */
+static int
+cfa_tcam_mgr_row_size_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ return sizeof(struct cfa_tcam_mgr_table_rows_0) +
+ (cfa_tcam_mgr_tables[sess_idx][dir][type].max_slices *
+ sizeof(((struct cfa_tcam_mgr_table_rows_0 *)0)->entries[0]));
+}
+
+static void *
+cfa_tcam_mgr_row_ptr_get(void *base, int index, int row_size)
+{
+ return (uint8_t *)base + (index * row_size);
+}
+
+/*
+ * Searches a table to find the direction and type of an entry.
+ */
+static int
+cfa_tcam_mgr_entry_find_in_table(int sess_idx, int id, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ int max_slices, row_idx, row_size, slice;
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ if (table_data->max_entries > 0 &&
+ table_data->hcapi_type > 0) {
+ max_slices = table_data->max_slices;
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type);
+ for (row_idx = table_data->start_row;
+ row_idx <= table_data->end_row;
+ row_idx++) {
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows,
+ row_idx, row_size);
+ if (!ROW_INUSE(row))
+ continue;
+ for (slice = 0;
+ slice < (max_slices / row->entry_size);
+ slice++) {
+ if (!ROW_ENTRY_INUSE(row, slice))
+ continue;
+ if (row->entries[slice] == id)
+ return 0;
+ }
+ }
+ }
+
+ return -CFA_TCAM_MGR_ERR_CODE(NOENT);
+}
+
+/*
+ * Searches all the tables to find the direction and type of an entry.
+ */
+static int
+cfa_tcam_mgr_entry_find(int sess_idx, int id, enum tf_dir *tbl_dir,
+ enum cfa_tcam_mgr_tbl_type *tbl_type)
+{
+ enum tf_dir dir;
+ enum cfa_tcam_mgr_tbl_type type;
+ int rc = -CFA_TCAM_MGR_ERR_CODE(NOENT);
+
+ for (dir = TF_DIR_RX; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = CFA_TCAM_MGR_TBL_TYPE_START;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ rc = cfa_tcam_mgr_entry_find_in_table(sess_idx, id, dir, type);
+ if (rc == 0) {
+ *tbl_dir = dir;
+ *tbl_type = type;
+ return rc;
+ }
+ }
+ }
+
+ return rc;
+}
+
+static int
+cfa_tcam_mgr_row_is_entry_free(struct cfa_tcam_mgr_table_rows_0 *row,
+ int max_slices,
+ int key_slices)
+{
+ int j;
+
+ if (ROW_INUSE(row) &&
+ row->entry_size == key_slices) {
+ for (j = 0; j < (max_slices / row->entry_size); j++) {
+ if (!ROW_ENTRY_INUSE(row, j))
+ return j;
+ }
+ }
+ return -1;
+}
+
+static int
+cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ int entry_id,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dest_row_index, int dest_row_slice,
+ struct cfa_tcam_mgr_table_rows_0 *dest_row,
+ int source_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *source_row,
+ bool free_source_entry)
+{
+ struct cfa_tcam_mgr_get_parms gparms = { 0 };
+ struct cfa_tcam_mgr_set_parms sparms = { 0 };
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ struct cfa_tcam_mgr_entry_data *entry;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE];
+
+ int j, rc;
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id);
+ if (entry == NULL)
+ return -1;
+
+ gparms.dir = dir;
+ gparms.type = type;
+ gparms.hcapi_type = table_data->hcapi_type;
+ gparms.key = key;
+ gparms.mask = mask;
+ gparms.result = result;
+ gparms.id = source_row->entries[entry->slice];
+ gparms.key_size = sizeof(key);
+ gparms.result_size = sizeof(result);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms,
+ source_row_index,
+ entry->slice * source_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ sparms.dir = dir;
+ sparms.type = type;
+ sparms.hcapi_type = table_data->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = result;
+ sparms.id = gparms.id;
+ sparms.key_size = gparms.key_size;
+ sparms.result_size = gparms.result_size;
+
+ /* Slice in destination row not specified. Find first free slice. */
+ if (dest_row_slice < 0)
+ for (j = 0;
+ j < (table_data->max_slices / dest_row->entry_size);
+ j++) {
+ if (!ROW_ENTRY_INUSE(dest_row, j)) {
+ dest_row_slice = j;
+ break;
+ }
+ }
+
+ /* If no free slice found, return error. */
+ if (dest_row_slice < 0)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms,
+ dest_row_index,
+ dest_row_slice * dest_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ if (free_source_entry) {
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ source_row_index,
+ entry->slice *
+ dest_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ source_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR,
+ dir, type,
+ "Failed to free entry ID %d at"
+ " row %d, slice %d for sess_idx %d. rc: %d.\n",
+ gparms.id,
+ source_row_index,
+ entry->slice,
+ sess_idx,
+ -rc);
+ }
+ }
+
+ ROW_ENTRY_SET(dest_row, dest_row_slice);
+ dest_row->entries[dest_row_slice] = entry_id;
+ ROW_ENTRY_CLEAR(source_row, entry->slice);
+ entry->row = dest_row_index;
+ entry->slice = dest_row_slice;
+
+ return 0;
+}
+
+static int
+cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dest_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *dest_row,
+ int source_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *source_row)
+{
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ int j, rc;
+
+ dest_row->priority = source_row->priority;
+ dest_row->entry_size = source_row->entry_size;
+ dest_row->entry_inuse = 0;
+
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+
+ for (j = 0;
+ j < (table_data->max_slices / source_row->entry_size);
+ j++) {
+ if (ROW_ENTRY_INUSE(source_row, j)) {
+ cfa_tcam_mgr_entry_move(sess_idx, context, dir, type,
+ source_row->entries[j],
+ table_data,
+ dest_row_index, j, dest_row,
+ source_row_index, source_row,
+ true);
+ } else {
+ /* Slice not in use, write an empty slice. */
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ dest_row_index,
+ j *
+ dest_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ dest_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+/* Install entry into in-memory tables, not into TCAM (yet). */
+static void
+cfa_tcam_mgr_row_entry_install(int sess_idx,
+ struct cfa_tcam_mgr_table_rows_0 *row,
+ struct cfa_tcam_mgr_alloc_parms *parms,
+ struct cfa_tcam_mgr_entry_data *entry,
+ uint16_t id,
+ int key_slices,
+ int row_index, int slice)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return;
+ }
+
+ if (slice == TF_TCAM_SLICE_INVALID) {
+ slice = 0;
+ row->entry_size = key_slices;
+ row->priority = parms->priority;
+ }
+
+ ROW_ENTRY_SET(row, slice);
+ row->entries[slice] = id;
+ entry->row = row_index;
+ entry->slice = slice;
+}
+
+/* Finds an empty row that can be used and reserve for entry. If necessary,
+ * entries will be shuffled in order to make room.
+ */
+static struct cfa_tcam_mgr_table_rows_0 *
+cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms,
+ struct cfa_tcam_mgr_entry_data *entry,
+ uint16_t id,
+ int key_slices)
+{
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ struct cfa_tcam_mgr_table_rows_0 *from_row;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int i, max_slices, row_size;
+ int to_row_idx, from_row_idx, slice, start_row, end_row;
+ int empty_row = -1;
+ int target_row = -1;
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ max_slices = table_data->max_slices;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ /*
+ * First check for partially used entries, but only if the key needs
+ * fewer slices than there are in a row.
+ */
+ if (key_slices < max_slices) {
+ for (i = start_row; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ continue;
+ if (row->priority < parms->priority)
+ break;
+ if (row->priority > parms->priority)
+ continue;
+ slice = cfa_tcam_mgr_row_is_entry_free(row,
+ max_slices,
+ key_slices);
+ if (slice >= 0) {
+ cfa_tcam_mgr_row_entry_install(sess_idx, row, parms,
+ entry, id,
+ key_slices,
+ i, slice);
+ return row;
+ }
+ }
+ }
+
+ /* No partially used rows available. Find an empty row, if any. */
+
+ /*
+ * All max priority entries are placed in the beginning of the TCAM. It
+ * should not be necessary to shuffle any of these entries. All other
+ * priorities are placed from the end of the TCAM and may require
+ * shuffling.
+ */
+ if (parms->priority == TF_TCAM_PRIORITY_MAX) {
+ /* Handle max priority first. */
+ for (i = start_row; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row)) {
+ cfa_tcam_mgr_row_entry_install(sess_idx,
+ row, parms,
+ entry,
+ id, key_slices,
+ i,
+ TF_TCAM_SLICE_INVALID);
+ return row;
+ }
+ if (row->priority < parms->priority) {
+ /*
+ * No free entries before priority change, table
+ * is full.
+ */
+ return NULL;
+ }
+ }
+ /* No free entries found, table is full. */
+ return NULL;
+ }
+
+ /* Use the highest available entry */
+ for (i = end_row; i >= start_row; i--) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row)) {
+ empty_row = i;
+ break;
+ }
+
+ if (row->priority > parms->priority &&
+ target_row < 0)
+ target_row = i;
+ }
+
+ if (empty_row < 0) {
+ /* No free entries found, table is full. */
+ return NULL;
+ }
+
+ if (target_row < 0) {
+ /*
+ * Did not find a row with higher priority before unused row so
+ * just install new entry in empty_row.
+ */
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, empty_row, row_size);
+ cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, entry, id,
+ key_slices, empty_row,
+ TF_TCAM_SLICE_INVALID);
+ return row;
+ }
+
+ to_row_idx = empty_row;
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size);
+ while (to_row_idx < target_row) {
+ from_row_idx = to_row_idx + 1;
+ from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx,
+ row_size);
+ /*
+ * Find the highest row with the same priority as the initial
+ * source row (from_row). It's only necessary to copy one row
+ * of each priority.
+ */
+ for (i = from_row_idx + 1; i <= target_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (row->priority != from_row->priority)
+ break;
+ from_row_idx = i;
+ from_row = row;
+ }
+ cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type,
+ table_data, to_row_idx, to_row,
+ from_row_idx, from_row);
+ to_row = from_row;
+ to_row_idx = from_row_idx;
+ }
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, target_row, row_size);
+ memset(to_row, 0, row_size);
+ cfa_tcam_mgr_row_entry_install(sess_idx, to_row, parms, entry, id,
+ key_slices, target_row,
+ TF_TCAM_SLICE_INVALID);
+
+ return row;
+}
+
+/*
+ * This function will combine rows when possible to result in the fewest rows
+ * used necessary for the entries that are installed.
+ */
+static void
+cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int changed_row_index)
+{
+ struct cfa_tcam_mgr_table_rows_0 *from_row = NULL;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ int i, j, row_size;
+ int to_row_idx, from_row_idx, start_row, end_row, max_slices;
+ bool entry_moved = false;
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ max_slices = table_data->max_slices;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ from_row_idx = changed_row_index;
+ from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx, row_size);
+
+ if (ROW_INUSE(from_row)) {
+ /*
+ * Row is still in partial use. See if remaining entry(s) can
+ * be moved to free up a row.
+ */
+ for (i = 0; i < (max_slices / from_row->entry_size); i++) {
+ if (!ROW_ENTRY_INUSE(from_row, i))
+ continue;
+ for (to_row_idx = end_row;
+ to_row_idx >= start_row;
+ to_row_idx--) {
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows,
+ to_row_idx,
+ row_size);
+ if (!ROW_INUSE(to_row))
+ continue;
+ if (to_row->priority > from_row->priority)
+ break;
+ if (to_row->priority != from_row->priority)
+ continue;
+ if (to_row->entry_size != from_row->entry_size)
+ continue;
+ if (to_row_idx == changed_row_index)
+ continue;
+ for (j = 0;
+ j < (max_slices / to_row->entry_size);
+ j++) {
+ if (!ROW_ENTRY_INUSE(to_row, j)) {
+ cfa_tcam_mgr_entry_move
+ (sess_idx,
+ context,
+ parms->dir,
+ parms->type,
+ from_row->entries[i],
+ table_data,
+ to_row_idx,
+ -1, to_row,
+ from_row_idx,
+ from_row,
+ true);
+ entry_moved = true;
+ break;
+ }
+ }
+ if (entry_moved)
+ break;
+ }
+ if (ROW_INUSE(from_row))
+ entry_moved = false;
+ else
+ break;
+ }
+ }
+}
+
+/*
+ * This function will ensure that all rows, except those of the highest
+ * priority, at the end of the table. When this function is finished, all the
+ * empty rows should be between the highest priority rows at the beginning of
+ * the table and the rest of the rows with lower priorities.
+ */
+/*
+ * Will need to free the row left newly empty as a result of moving.
+ *
+ * Return row to free to caller. If new_row_to_free < 0, then no new row to
+ * free.
+ */
+static void
+cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int *new_row_to_free,
+ int changed_row_index)
+{
+ struct cfa_tcam_mgr_table_rows_0 *from_row = NULL;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ int i, row_size, priority;
+ int to_row_idx = 0, from_row_idx = 0, start_row = 0, end_row = 0;
+
+ *new_row_to_free = -1;
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ /*
+ * The row is no longer in use, so see if rows need to be moved in order
+ * to not leave any gaps.
+ */
+ to_row_idx = changed_row_index;
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size);
+
+ priority = to_row->priority;
+ if (priority == TF_TCAM_PRIORITY_MAX) {
+ if (changed_row_index == end_row)
+ /*
+ * Nothing to move - the last row in the TCAM is being
+ * deleted.
+ */
+ return;
+ for (i = changed_row_index + 1; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ break;
+
+ if (row->priority < priority)
+ break;
+
+ from_row = row;
+ from_row_idx = i;
+ }
+ } else {
+ if (changed_row_index == start_row)
+ /*
+ * Nothing to move - the first row in the TCAM is being
+ * deleted.
+ */
+ return;
+ for (i = changed_row_index - 1; i >= start_row; i--) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ break;
+
+ if (row->priority > priority) {
+ /* Don't move the highest priority rows. */
+ if (row->priority == TF_TCAM_PRIORITY_MAX)
+ break;
+ /*
+ * If from_row is NULL, that means that there
+ * were no rows of the deleted priority.
+ * Nothing to move yet.
+ *
+ * If from_row is not NULL, then it is the last
+ * row with the same priority and must be moved
+ * to fill the newly empty (by free or by move)
+ * row.
+ */
+ if (from_row != NULL) {
+ cfa_tcam_mgr_row_move(sess_idx, context,
+ parms->dir,
+ parms->type,
+ table_data,
+ to_row_idx, to_row,
+ from_row_idx,
+ from_row);
+ *new_row_to_free = from_row_idx;
+ to_row = from_row;
+ to_row_idx = from_row_idx;
+ }
+
+ priority = row->priority;
+ }
+ from_row = row;
+ from_row_idx = i;
+ }
+ }
+
+ if (from_row != NULL) {
+ cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type,
+ table_data,
+ to_row_idx, to_row,
+ from_row_idx, from_row);
+ *new_row_to_free = from_row_idx;
+ }
+}
+
+/*
+ * This function is to set table limits for the logical TCAM tables.
+ */
+static int
+cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ unsigned int dir, type;
+ int start, stride;
+
+ if (parms == NULL)
+ return 0;
+
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++)
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ /*
+ * If num_rows is zero, then TCAM Manager did not
+ * allocate any row storage for that table so cannot
+ * manage it.
+ */
+ if (table_data->num_rows == 0)
+ continue;
+ start = parms->resc[dir][type].start;
+ stride = parms->resc[dir][type].stride;
+ if (start % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Start of resources (%d) for table (%d) "
+ "does not begin on row boundary.\n",
+ start, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Start is %d, number of slices "
+ "is %d.\n",
+ start,
+ table_data->max_slices);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Stride of resources (%d) for table (%d)"
+ " does not end on row boundary.\n",
+ stride, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Stride is %d, number of "
+ "slices is %d.\n",
+ stride,
+ table_data->max_slices);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else {
+ table_data->start_row = start /
+ table_data->max_slices;
+ table_data->end_row = table_data->start_row +
+ (stride / table_data->max_slices) - 1;
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type,
+ struct cfa_tcam_mgr_init_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ unsigned int dir, tbl_type;
+ int rc;
+
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ rc = cfa_tcam_mgr_init_p4(sess_idx, &entry_data[sess_idx]);
+ break;
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ rc = cfa_tcam_mgr_init_p58(sess_idx, &entry_data[sess_idx]);
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d for sess_idx %d\n",
+ type, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+ if (rc < 0)
+ return rc;
+
+ rc = cfa_tcam_mgr_table_limits_set(sess_idx, parms);
+ if (rc < 0)
+ return rc;
+
+ /* Now calculate the max entries per table and global max entries based
+ * on the updated table limits.
+ */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++)
+ for (tbl_type = 0;
+ tbl_type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ tbl_type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type];
+ /*
+ * If num_rows is zero, then TCAM Manager did not
+ * allocate any row storage for that table so cannot
+ * manage it.
+ */
+ if (table_data->num_rows == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else if (table_data->end_row >=
+ table_data->num_rows) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(EMERG, dir, tbl_type,
+ "End row is out of "
+ "range (%d >= %d) for sess_idx %d\n",
+ table_data->end_row,
+ table_data->num_rows,
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(FAULT);
+ } else if (table_data->max_entries == 0 &&
+ table_data->start_row == 0 &&
+ table_data->end_row == 0) {
+ /* Nothing to do */
+ } else {
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ cfa_tcam_mgr_max_entries[sess_idx] += table_data->max_entries;
+ }
+
+ rc = cfa_tcam_mgr_hwops_init(type);
+ if (rc < 0)
+ return rc;
+
+ rc = cfa_tcam_mgr_session_init(sess_idx, type);
+ if (rc < 0)
+ return rc;
+
+ global_data_initialized[sess_idx] = 1;
+
+ if (parms != NULL)
+ parms->max_entries = cfa_tcam_mgr_max_entries[sess_idx];
+
+ CFA_TCAM_MGR_LOG(INFO, "Global TCAM table initialized for sess_idx %d.\n",
+ sess_idx);
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_qcaps_parms *parms)
+{
+ unsigned int type;
+ int rc, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ /*
+ * This code will indicate if TCAM Manager is managing a logical TCAM
+ * table or not. If not, then the physical TCAM will have to be
+ * accessed using the traditional methods.
+ */
+ parms->rx_tcam_supported = 0;
+ parms->tx_tcam_supported = 0;
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].max_entries > 0 &&
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].hcapi_type > 0)
+ parms->rx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type);
+ if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].max_entries > 0 &&
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].hcapi_type > 0)
+ parms->tx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type);
+ }
+
+ return 0;
+}
+
+/*
+ * Manipulate the tables to split the WC TCAM into HIGH and LOW ranges
+ * and also update the sizes in the tcam count array
+ */
+static int
+cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX])
+{
+ uint16_t start_row, end_row, max_entries, slices;
+ uint16_t num_pools = dual_ha_app ? 4 : 2;
+ enum tf_dir dir;
+ int rc;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ rc = cfa_tcam_mgr_tables_get(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ &start_row, &end_row, &max_entries, &slices);
+ if (rc)
+ return rc;
+ if (max_entries) {
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ start_row,
+ start_row +
+ ((max_entries / slices) / num_pools) - 1,
+ max_entries / num_pools);
+ if (rc)
+ return rc;
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ start_row +
+ ((max_entries / slices) / num_pools),
+ start_row +
+ (max_entries / slices) - 1,
+ max_entries / num_pools);
+ if (rc)
+ return rc;
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ 0, 0, 0);
+ if (rc)
+ return rc;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] =
+ max_entries / num_pools;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] =
+ max_entries / num_pools;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = 0;
+ }
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_cfg_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct tf_dev_info *dev;
+ unsigned int dir;
+ int rc, sess_idx;
+ uint32_t session_id;
+ struct tf_session *tfs;
+ unsigned int type;
+ int prev_max_entries;
+ int start, stride;
+ enum cfa_tcam_mgr_device_type device_type;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ switch (dev->type) {
+ case TF_DEVICE_TYPE_P4:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_P4;
+ break;
+ case TF_DEVICE_TYPE_SR:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_SR;
+ break;
+ case TF_DEVICE_TYPE_P5:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_P5;
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", dev->type);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_add(session_id);
+ if (sess_idx < 0)
+ return sess_idx;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ rc = cfa_tcam_mgr_init(sess_idx, device_type, NULL);
+ if (rc < 0)
+ return rc;
+ }
+
+ if (parms->num_elements != ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir])) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "Session element count (%d) differs "
+ "from table count (%zu) for sess_idx %d.\n",
+ parms->num_elements,
+ ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]),
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /*
+ * Only managing one session. resv_res contains the resources allocated
+ * to this session by the resource manager. Update the limits on TCAMs.
+ */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ prev_max_entries = table_data->max_entries;
+ /*
+ * In AFM logical tables, max_entries is initialized to
+ * zero. These logical tables are not used when TCAM
+ * Manager is in the core so skip.
+ */
+ if (prev_max_entries == 0)
+ continue;
+ start = parms->resv_res[dir][type].start;
+ stride = parms->resv_res[dir][type].stride;
+ if (start % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Start of resources (%d) for table(%d) "
+ "does not begin on row boundary.\n",
+ start, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Start is %d, number of slices "
+ "is %d.\n",
+ start,
+ table_data->max_slices);
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Stride of resources (%d) for table(%d) "
+ "does not end on row boundary.\n",
+ stride, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Stride is %d, number of "
+ "slices is %d.\n",
+ stride,
+ table_data->max_slices);
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else {
+ table_data->start_row = start /
+ table_data->max_slices;
+ table_data->end_row = table_data->start_row +
+ (stride / table_data->max_slices) - 1;
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ cfa_tcam_mgr_max_entries[sess_idx] += (table_data->max_entries -
+ prev_max_entries);
+ }
+ }
+
+ if (tf_session_is_shared_hotup_session(tfs)) {
+ rc = cfa_tcam_mgr_shared_wc_bind(sess_idx, false, parms->tcam_cnt);
+ if (rc) {
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return rc;
+ }
+ }
+
+ rc = cfa_tcam_mgr_session_cfg(session_id, parms->tcam_cnt);
+ if (rc < 0) {
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return rc;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context)
+{
+ int rc, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS1(context);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+
+ global_data_initialized[sess_idx] = 0;
+ return 0;
+}
+
+int
+cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int dir, tbl_type;
+ int key_slices, rc, sess_idx;
+ int new_entry_id;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ dir = parms->dir;
+ tbl_type = parms->type;
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Invalid direction: %d.\n", dir);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (tbl_type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Invalid table type: %d.\n",
+ tbl_type);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+#if TF_TCAM_PRIORITY_MAX < UINT16_MAX
+ if (parms->priority > TF_TCAM_PRIORITY_MAX) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Priority (%u) out of range (%u -%u).\n",
+ parms->priority,
+ TF_TCAM_PRIORITY_MIN,
+ TF_TCAM_PRIORITY_MAX);
+ }
+#endif
+
+ /* Check for session limits */
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type];
+
+ if (parms->key_size == 0 ||
+ parms->key_size > table_data->row_width) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Invalid key size:%d (range 1-%d) sess_idx %d.\n",
+ parms->key_size,
+ table_data->row_width,
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /* Check global limits */
+ if (table_data->used_entries >=
+ table_data->max_entries) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, tbl_type,
+ "Table full sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ /* There is room, now increment counts and allocate an entry. */
+ new_entry_id = cfa_tcam_mgr_session_entry_alloc(session_id,
+ parms->dir,
+ parms->type);
+ if (new_entry_id < 0)
+ return new_entry_id;
+
+ memset(&entry, 0, sizeof(entry));
+ entry.ref_cnt++;
+
+ key_slices = cfa_tcam_mgr_get_num_slices(parms->key_size,
+ (table_data->row_width /
+ table_data->max_slices));
+
+ row = cfa_tcam_mgr_empty_row_alloc(sess_idx, context, parms, &entry,
+ new_entry_id, key_slices);
+ if (row == NULL) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Table full (HW) sess_idx %d.\n",
+ sess_idx);
+ (void)cfa_tcam_mgr_session_entry_free(session_id, new_entry_id,
+ parms->dir, parms->type);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ memcpy(&entry_data[sess_idx][new_entry_id],
+ &entry,
+ sizeof(entry_data[sess_idx][new_entry_id]));
+ table_data->used_entries += 1;
+
+ cfa_tcam_mgr_entry_insert(sess_idx, new_entry_id, &entry);
+
+ parms->id = new_entry_id;
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int row_size, rc, sess_idx, new_row_to_free;
+ uint32_t session_id;
+ uint16_t id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ id = parms->id;
+ entry = cfa_tcam_mgr_entry_get(sess_idx, id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(INFO, "Entry %d not found for sess_idx %d.\n",
+ id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (entry->ref_cnt == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not in use for sess_idx %d.\n",
+ id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /*
+ * If the TCAM type is CFA_TCAM_MGR_TBL_TYPE_MAX, that implies that the
+ * caller does not know the table or direction of the entry and TCAM
+ * Manager must search the tables to find out which table has the entry
+ * installed.
+ *
+ * This would be the case if RM has informed TCAM Mgr that an entry must
+ * be freed. Clients (sessions, AFM) should always know the type and
+ * direction of the table where an entry is installed.
+ */
+ if (parms->type == CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Need to search for the entry in the tables */
+ rc = cfa_tcam_mgr_entry_find(sess_idx, id, &parms->dir, &parms->type);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not in tables for sess_idx %d.\n",
+ id, sess_idx);
+ return rc;
+ }
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ entry->ref_cnt--;
+
+ (void)cfa_tcam_mgr_session_entry_free(session_id, id,
+ parms->dir, parms->type);
+
+ if (entry->ref_cnt == 0) {
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ ROW_ENTRY_CLEAR(row, entry->slice);
+
+ new_row_to_free = entry->row;
+ cfa_tcam_mgr_rows_combine(sess_idx, context, parms, table_data,
+ new_row_to_free);
+
+ if (!ROW_INUSE(row)) {
+ cfa_tcam_mgr_rows_compact(sess_idx, context,
+ parms, table_data,
+ &new_row_to_free,
+ new_row_to_free);
+ if (new_row_to_free >= 0)
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms,
+ new_row_to_free, 0,
+ table_data->row_width,
+ table_data->result_size,
+ table_data->max_slices);
+ }
+
+ cfa_tcam_mgr_entry_delete(sess_idx, id);
+ table_data->used_entries -= 1;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int rc;
+ int row_size, sess_idx;
+ int entry_size_in_bytes;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not found for sess_idx %d.\n",
+ parms->id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ entry_size_in_bytes = table_data->row_width /
+ table_data->max_slices *
+ row->entry_size;
+ if (parms->key_size != entry_size_in_bytes) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "Key size(%d) is different from entry "
+ "size(%d).\n",
+ parms->key_size,
+ entry_size_in_bytes);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->max_slices);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Failed to set TCAM data.\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_get_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int rc;
+ int row_size, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not found.\n", parms->id);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->max_slices);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Failed to read from TCAM.\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_clear_parms *parms)
+{
+ int rc;
+ uint16_t row, slice = 0;
+ int sess_idx;
+ uint32_t session_id;
+ struct cfa_tcam_mgr_free_parms fparms;
+ struct cfa_tcam_mgr_table_data *table_data;
+ uint16_t start_row, end_row, max_entries, max_slices;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ fparms.dir = parms->dir;
+ fparms.type = parms->type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ fparms.id = 0;
+
+ rc = cfa_tcam_mgr_tables_get(sess_idx, parms->dir, parms->type,
+ &start_row, &end_row, &max_entries, &max_slices);
+ if (rc)
+ return rc;
+
+ for (row = start_row; row <= end_row; row++) {
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ row,
+ slice,
+ table_data->row_width,
+ table_data->result_size,
+ table_data->max_slices);
+ }
+ return rc;
+}
+
+static void
+cfa_tcam_mgr_mv_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ struct cfa_tcam_mgr_table_data *dst_table_data,
+ struct cfa_tcam_mgr_table_data *src_table_data)
+{
+ dst_table_data->used_entries++;
+ src_table_data->used_entries--;
+
+ cfa_tcam_mgr_mv_session_used_entries_cnt(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS);
+}
+
+/*
+ * Move HI WC TCAM entries to LOW TCAM region for HA
+ * This happens when secondary is becoming primary
+ */
+static int
+cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ int entry_id,
+ struct cfa_tcam_mgr_table_data *dst_table_data,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dst_row_index, int dst_row_slice,
+ struct cfa_tcam_mgr_table_rows_0 *dst_row,
+ int src_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *src_row)
+{
+ struct cfa_tcam_mgr_get_parms gparms = { 0 };
+ struct cfa_tcam_mgr_set_parms sparms = { 0 };
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ struct cfa_tcam_mgr_entry_data *entry;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE];
+
+ int rc;
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id);
+ if (entry == NULL)
+ return -1;
+
+ gparms.dir = dir;
+ gparms.type = type;
+ gparms.hcapi_type = table_data->hcapi_type;
+ gparms.key = key;
+ gparms.mask = mask;
+ gparms.result = result;
+ gparms.id = src_row->entries[entry->slice];
+ gparms.key_size = sizeof(key);
+ gparms.result_size = sizeof(result);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms,
+ src_row_index,
+ entry->slice * src_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ sparms.dir = dir;
+ sparms.type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS;
+ sparms.hcapi_type = table_data->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = result;
+ sparms.id = gparms.id;
+ sparms.key_size = gparms.key_size;
+ sparms.result_size = gparms.result_size;
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms,
+ dst_row_index,
+ dst_row_slice * dst_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ src_row_index,
+ entry->slice *
+ dst_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ src_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR,
+ dir, type,
+ "Failed to free entry ID %d at"
+ " row %d, slice %d for sess_idx %d. rc: %d.\n",
+ gparms.id,
+ src_row_index,
+ entry->slice,
+ sess_idx,
+ -rc);
+ }
+
+#ifdef CFA_TCAM_MGR_TRACING
+ CFA_TCAM_MGR_TRACE(INFO, "Moved entry %d from row %d, slice %d to "
+ "row %d, slice %d.\n",
+ entry_id, src_row_index, entry->slice,
+ dst_row_index, dst_row_slice);
+#endif
+
+ ROW_ENTRY_SET(dst_row, dst_row_slice);
+ dst_row->entries[dst_row_slice] = entry_id;
+ dst_row->entry_size = src_row->entry_size;
+ dst_row->priority = src_row->priority;
+ ROW_ENTRY_CLEAR(src_row, entry->slice);
+ entry->row = dst_row_index;
+ entry->slice = dst_row_slice;
+
+ cfa_tcam_mgr_mv_used_entries_cnt(sess_idx, dir, dst_table_data, table_data);
+
+#ifdef CFA_TCAM_MGR_TRACING
+ cfa_tcam_mgr_rows_dump(sess_idx, dir, type);
+ cfa_tcam_mgr_rows_dump(sess_idx, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS);
+#endif
+
+ return 0;
+}
+
+int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_move_parms *parms)
+{
+ int rc;
+ int sess_idx;
+ uint32_t session_id;
+ uint16_t src_row, dst_row, row_size, slice;
+ struct cfa_tcam_mgr_table_rows_0 *src_table_row;
+ struct cfa_tcam_mgr_table_rows_0 *dst_table_row;
+ struct cfa_tcam_mgr_table_data *src_table_data;
+ struct cfa_tcam_mgr_table_data *dst_table_data;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ src_table_data =
+ &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS];
+ dst_table_data =
+ &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS];
+
+ row_size =
+ cfa_tcam_mgr_row_size_get(sess_idx,
+ parms->dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS);
+
+ for (src_row = src_table_data->start_row,
+ dst_row = dst_table_data->start_row;
+ src_row <= src_table_data->end_row;
+ src_row++, dst_row++) {
+ src_table_row = cfa_tcam_mgr_row_ptr_get(src_table_data->tcam_rows,
+ src_row, row_size);
+ dst_table_row = cfa_tcam_mgr_row_ptr_get(dst_table_data->tcam_rows,
+ dst_row, row_size);
+ if (ROW_INUSE(src_table_row)) {
+ for (slice = 0;
+ slice < src_table_data->max_slices / src_table_row->entry_size;
+ slice++) {
+ if (ROW_ENTRY_INUSE(src_table_row, slice)) {
+#ifdef CFA_TCAM_MGR_TRACING
+ CFA_TCAM_MGR_TRACE(INFO, "Move entry id %d "
+ "from src_row %d, slice %d "
+ "to dst_row %d, slice %d.\n",
+ src_table_row->entries[slice],
+ src_row, slice,
+ dst_row, slice);
+#endif
+ rc = cfa_tcam_mgr_shared_entry_move(sess_idx,
+ context,
+ parms->dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ src_table_row->entries[slice],
+ dst_table_data,
+ src_table_data,
+ dst_row, slice,
+ dst_table_row,
+ src_row,
+ src_table_row);
+ }
+ }
+ }
+ }
+
+ return rc;
+}
+
+static void
+cfa_tcam_mgr_tbl_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ /* Get start, end and max for tcam type*/
+ *start_row = table_data->start_row;
+ *end_row = table_data->end_row;
+ *max_entries = table_data->max_entries;
+ *slices = table_data->max_slices;
+}
+
+int
+cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices)
+{
+ CFA_TCAM_MGR_CHECK_PARMS3(start_row, end_row, max_entries);
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n",
+ TF_DIR_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ cfa_tcam_mgr_tbl_get(sess_idx, dir,
+ type,
+ start_row,
+ end_row,
+ max_entries,
+ slices);
+ return 0;
+}
+
+static void
+cfa_tcam_mgr_tbl_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ /* Update start, end and max for tcam type*/
+ table_data->start_row = start_row;
+ table_data->end_row = end_row;
+ table_data->max_entries = max_entries;
+}
+
+int
+cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n",
+ TF_DIR_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ cfa_tcam_mgr_tbl_set(sess_idx, dir,
+ type,
+ start_row,
+ end_row,
+ max_entries);
+ return 0;
+}
+
+void
+cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_table_rows_0 *table_row;
+ int i, row, row_size;
+ bool row_found = false;
+ bool empty_row = false;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx);
+ return;
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ printf("Must specify a valid direction (0-%d).\n",
+ TF_DIR_MAX - 1);
+ return;
+ }
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ printf("Must specify a valid type (0-%d).\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1);
+ return;
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type);
+
+ printf("\nTCAM Rows:\n");
+ printf("Rows for direction %s, Logical table type %s\n",
+ tf_dir_2_str(dir), cfa_tcam_mgr_tbl_2_str(type));
+ printf("Managed rows %d-%d for sess_idx %d:\n",
+ table_data->start_row, table_data->end_row, sess_idx);
+
+ printf("Index Pri Size Entry IDs\n");
+ printf(" Sl 0");
+ for (i = 1; i < table_data->max_slices; i++)
+ printf(" Sl %d", i);
+ printf("\n");
+ for (row = table_data->start_row; row <= table_data->end_row; row++) {
+ table_row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, row,
+ row_size);
+ if (ROW_INUSE(table_row)) {
+ empty_row = false;
+ printf("%5u %5u %4u",
+ row,
+ TF_TCAM_PRIORITY_MAX - table_row->priority - 1,
+ table_row->entry_size);
+ for (i = 0;
+ i < table_data->max_slices / table_row->entry_size;
+ i++) {
+ if (ROW_ENTRY_INUSE(table_row, i))
+ printf(" %5u", table_row->entries[i]);
+ else
+ printf(" x");
+ }
+ printf("\n");
+ row_found = true;
+ } else if (!empty_row) {
+ empty_row = true;
+ printf("\n");
+ }
+ }
+
+ if (!row_found)
+ printf("No rows in use.\n");
+}
+
+static void
+cfa_tcam_mgr_table_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ printf("%3s %-22s %5u %5u %5u %5u %6u %7u %2u\n",
+ tf_dir_2_str(dir),
+ cfa_tcam_mgr_tbl_2_str(type),
+ table_data->row_width,
+ table_data->num_rows,
+ table_data->start_row,
+ table_data->end_row,
+ table_data->max_entries,
+ table_data->used_entries,
+ table_data->max_slices);
+}
+
+#define TABLE_DUMP_HEADER \
+ "Dir Table Width Rows Start End " \
+ "MaxEnt UsedEnt Slices\n"
+
+void
+cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx);
+ return;
+ }
+
+ printf("\nTCAM Table(s) for sess_idx %d:\n", sess_idx);
+ printf(TABLE_DUMP_HEADER);
+ if (dir >= TF_DIR_MAX) {
+ /* Iterate over all directions */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Iterate over all types */
+ for (type = 0;
+ type < CFA_TCAM_MGR_TBL_TYPE_MAX;
+ type++) {
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+ } else {
+ /* Display a specific type */
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+ }
+ } else if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Iterate over all types for a direction */
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++)
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ } else {
+ /* Display a specific direction and type */
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+}
+
+#define ENTRY_DUMP_HEADER "Entry RefCnt Row Slice\n"
+
+void
+cfa_tcam_mgr_entries_dump(int sess_idx)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ bool entry_found = false;
+ uint16_t id;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return;
+ }
+
+ printf("\nGlobal Maximum Entries: %d\n\n",
+ cfa_tcam_mgr_max_entries[sess_idx]);
+ printf("TCAM Entry Table:\n");
+ for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) {
+ if (entry_data[sess_idx][id].ref_cnt > 0) {
+ entry = &entry_data[sess_idx][id];
+ if (!entry_found)
+ printf(ENTRY_DUMP_HEADER);
+ printf("%5u %5u %5u %5u",
+ id, entry->ref_cnt,
+ entry->row, entry->slice);
+ printf("\n");
+ entry_found = true;
+ }
+ }
+
+ if (!entry_found)
+ printf("No entries found.\n");
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
new file mode 100644
index 0000000000..40bfe8e225
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
@@ -0,0 +1,523 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _CFA_TCAM_MGR_H_
+#define _CFA_TCAM_MGR_H_
+
+#include <errno.h>
+#include "rte_common.h"
+#include "hsi_struct_def_dpdk.h"
+#include "tf_core.h"
+
+#ifndef __rte_unused
+#define __rte_unused __attribute__((unused))
+#endif
+
+/**
+ * The TCAM module provides processing of Internal TCAM types.
+ */
+
+#ifndef TF_TCAM_MAX_SESSIONS
+#define TF_TCAM_MAX_SESSIONS 16
+#endif
+
+#define ENTRY_ID_INVALID UINT16_MAX
+
+#define TF_TCAM_PRIORITY_MIN 0
+#define TF_TCAM_PRIORITY_MAX UINT16_MAX
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_array) (sizeof(_array) / sizeof(_array[0]))
+#endif
+
+/* Use TFP_DRV_LOG definition in tfp.h */
+#define CFA_TCAM_MGR_LOG(level, fmt, args...) \
+ TFP_DRV_LOG(level, fmt, ## args)
+#define CFA_TCAM_MGR_LOG_DIR(level, dir, fmt, args...) \
+ TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir), ## args)
+#define CFA_TCAM_MGR_LOG_DIR_TYPE(level, dir, type, fmt, args...) \
+ TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \
+ cfa_tcam_mgr_tbl_2_str(type), ## args)
+
+#define CFA_TCAM_MGR_LOG_0(level, fmt) \
+ TFP_DRV_LOG(level, fmt)
+#define CFA_TCAM_MGR_LOG_DIR_0(level, dir, fmt) \
+ TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir))
+#define CFA_TCAM_MGR_LOG_DIR_TYPE_0(level, dir, type, fmt) \
+ TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \
+ cfa_tcam_mgr_tbl_2_str(type))
+
+#define CFA_TCAM_MGR_ERR_CODE(type) E ## type
+
+/**
+ * Checks 1 parameter against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS1(parms) do { \
+ if ((parms) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+/**
+ * Checks 2 parameters against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS2(parms1, parms2) do { \
+ if ((parms1) == NULL || (parms2) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+/**
+ * Checks 3 parameters against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS3(parms1, parms2, parms3) do { \
+ if ((parms1) == NULL || \
+ (parms2) == NULL || \
+ (parms3) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+enum cfa_tcam_mgr_tbl_type {
+ /* Logical TCAM tables */
+ CFA_TCAM_MGR_TBL_TYPE_START,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM =
+ CFA_TCAM_MGR_TBL_TYPE_START,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_MAX
+};
+
+enum cfa_tcam_mgr_device_type {
+ CFA_TCAM_MGR_DEVICE_TYPE_P4 = 0,
+ CFA_TCAM_MGR_DEVICE_TYPE_SR,
+ CFA_TCAM_MGR_DEVICE_TYPE_P5,
+ CFA_TCAM_MGR_DEVICE_TYPE_MAX
+};
+
+struct cfa_tcam_mgr_context {
+ struct tf *tfp;
+};
+
+/**
+ * TCAM Manager initialization parameters
+ */
+struct cfa_tcam_mgr_init_parms {
+ /**
+ * [in] TCAM resources reserved
+ * type element is not used.
+ */
+ struct tf_rm_resc_entry resc[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ /**
+ * [out] maximum number of entries available.
+ */
+ uint32_t max_entries;
+};
+
+/**
+ * TCAM Manager initialization parameters
+ */
+struct cfa_tcam_mgr_qcaps_parms {
+ /**
+ * [out] Bitmasks. Set if TCAM Manager is managing a logical TCAM.
+ * Each bitmask is indexed by logical TCAM table ID.
+ */
+ uint32_t rx_tcam_supported;
+ uint32_t tx_tcam_supported;
+};
+
+/**
+ * TCAM Manager configuration parameters
+ */
+struct cfa_tcam_mgr_cfg_parms {
+ /**
+ * [in] Number of tcam types in each of the configuration arrays
+ */
+ uint16_t num_elements;
+ /**
+ * [in] Session resource allocations
+ */
+ uint16_t tcam_cnt[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+ /**
+ * [in] TCAM Locations reserved
+ */
+ struct tf_rm_resc_entry (*resv_res)[CFA_TCAM_MGR_TBL_TYPE_MAX];
+};
+
+/**
+ * TCAM Manager allocation parameters
+ */
+struct cfa_tcam_mgr_alloc_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of the allocation
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [in] Priority of entry requested (definition TBD)
+ */
+ uint16_t priority;
+ /**
+ * [out] Id of allocated entry or found entry (if search_enable)
+ */
+ uint16_t id;
+};
+
+/**
+ * TCAM Manager free parameters
+ */
+struct cfa_tcam_mgr_free_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of the allocation
+ * If the type is not known, set the type to CFA_TCAM_MGR_TBL_TYPE_MAX.
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to free
+ */
+ uint16_t id;
+};
+
+/**
+ * TCAM Manager set parameters
+ */
+struct cfa_tcam_mgr_set_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of object to set
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to write to
+ */
+ uint16_t id;
+ /**
+ * [in] array containing key
+ */
+ uint8_t *key;
+ /**
+ * [in] array containing mask fields
+ */
+ uint8_t *mask;
+ /**
+ * [in] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [in] array containing result
+ */
+ uint8_t *result;
+ /**
+ * [in] result size (bytes)
+ */
+ uint16_t result_size;
+};
+
+/**
+ * TCAM Manager get parameters
+ */
+struct cfa_tcam_mgr_get_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of object to get
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to read
+ */
+ uint16_t id;
+ /**
+ * [out] array containing key
+ */
+ uint8_t *key;
+ /**
+ * [out] array containing mask fields
+ */
+ uint8_t *mask;
+ /**
+ * [out] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [out] array containing result
+ */
+ uint8_t *result;
+ /**
+ * [out] result size (bytes)
+ */
+ uint16_t result_size;
+};
+
+/**
+ * cfa_tcam_mgr_shared_clear_parms parameter definition
+ */
+struct cfa_tcam_mgr_shared_clear_parms {
+ /**
+ * [in] receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] TCAM table type
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+};
+
+/**
+ * cfa_tcam_mgr_shared_move_parms parameter definition
+ */
+struct cfa_tcam_mgr_shared_move_parms {
+ /**
+ * [in] receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] TCAM table type
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+};
+
+/**
+ * @page tcam TCAM Manager
+ *
+ * @ref cfa_tcam_mgr_init
+ *
+ * @ref cfa_tcam_mgr_get_phys_table_type
+ *
+ * @ref cfa_tcam_mgr_bind
+ *
+ * @ref cfa_tcam_mgr_unbind
+ *
+ * @ref cfa_tcam_mgr_alloc
+ *
+ * @ref cfa_tcam_mgr_free
+ *
+ * @ref cfa_tcam_mgr_set
+ *
+ * @ref cfa_tcam_mgr_get
+ *
+ */
+
+const char *
+cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type);
+
+/**
+ * Initializes the TCAM Manager
+ *
+ * [in] type
+ * Device type
+ *
+ * Returns
+ * - (0) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type,
+ struct cfa_tcam_mgr_init_parms *parms);
+
+/**
+ * Returns the physical TCAM table that a logical TCAM table uses.
+ *
+ * [in] type
+ * Logical table type
+ *
+ * Returns
+ * - (tf_tcam_tbl_type) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type);
+
+/**
+ * Queries the capabilities of TCAM Manager.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [out] parms
+ * Pointer to parameters to be returned
+ *
+ * Returns
+ * - (0) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_qcaps_parms *parms);
+
+/**
+ * Initializes the TCAM module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_cfg_parms *parms);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context);
+
+/**
+ * Allocates the requested tcam type from the internal RM DB.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB.
+ * If refcount goes to 0 then it is returned to the table type DB.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms);
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_get_parms *parms);
+
+int
+cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices);
+int
+cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries);
+
+int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_clear_parms *parms);
+
+int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_move_parms *parms);
+
+void cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type);
+void cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type);
+void cfa_tcam_mgr_entries_dump(int sess_idx);
+#endif /* _CFA_TCAM_MGR_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
new file mode 100644
index 0000000000..6ab9b5e118
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_DEVICE_H
+#define CFA_TCAM_MGR_DEVICE_H
+
+#include <inttypes.h>
+#include "cfa_tcam_mgr.h"
+
+/*
+ * This identifier is to be used for one-off variable sizes. Do not use it for
+ * sizing keys in an array.
+ */
+#define CFA_TCAM_MGR_MAX_KEY_SIZE 96
+
+/* Note that this macro's arguments are not macro expanded due to
+ * concatenation.
+ */
+#define TF_TCAM_TABLE_ROWS_DEF(_slices) \
+ struct cfa_tcam_mgr_table_rows_ ## _slices { \
+ uint16_t priority; \
+ uint8_t entry_size; /* Slices per entry */ \
+ uint8_t entry_inuse; /* bit[entry] set if in use */ \
+ uint16_t entries[_slices]; \
+ }
+
+/*
+ * Have to explicitly declare this struct since some compilers don't accept the
+ * GNU C extension of zero length arrays.
+ */
+struct cfa_tcam_mgr_table_rows_0 {
+ uint16_t priority;
+ uint8_t entry_size; /* Slices per entry */
+ uint8_t entry_inuse; /* bit[entry] set if in use */
+ uint16_t entries[];
+};
+
+TF_TCAM_TABLE_ROWS_DEF(1);
+TF_TCAM_TABLE_ROWS_DEF(2);
+TF_TCAM_TABLE_ROWS_DEF(4);
+TF_TCAM_TABLE_ROWS_DEF(8);
+
+#define TF_TCAM_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_ENTRIES + \
+ L2_CTXT_TCAM_TX_MAX_ENTRIES + \
+ PROF_TCAM_RX_MAX_ENTRIES + \
+ PROF_TCAM_TX_MAX_ENTRIES + \
+ WC_TCAM_RX_MAX_ENTRIES + \
+ WC_TCAM_TX_MAX_ENTRIES + \
+ SP_TCAM_RX_MAX_ENTRIES + \
+ SP_TCAM_TX_MAX_ENTRIES + \
+ CT_RULE_TCAM_RX_MAX_ENTRIES + \
+ CT_RULE_TCAM_TX_MAX_ENTRIES + \
+ VEB_TCAM_RX_MAX_ENTRIES + \
+ VEB_TCAM_TX_MAX_ENTRIES)
+
+struct cfa_tcam_mgr_entry_data {
+ uint16_t row;
+ uint8_t slice;
+ uint8_t ref_cnt;
+};
+
+struct cfa_tcam_mgr_table_data {
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ uint16_t hcapi_type;
+ uint16_t num_rows; /* Rows in physical TCAM */
+ uint16_t start_row; /* Where the logical TCAM starts */
+ uint16_t end_row; /* Where the logical TCAM ends */
+ uint16_t max_entries;
+ uint16_t used_entries;
+ uint8_t row_width; /* bytes */
+ uint8_t result_size; /* bytes */
+ uint8_t max_slices;
+};
+
+extern int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS];
+
+extern struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+/* HW OP definitions begin here */
+typedef int (*cfa_tcam_mgr_hwop_set_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_set_parms
+ *parms, int row, int slice,
+ int max_slices);
+typedef int (*cfa_tcam_mgr_hwop_get_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_get_parms
+ *parms, int row, int slice,
+ int max_slices);
+typedef int (*cfa_tcam_mgr_hwop_free_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_free_parms
+ *parms, int row, int slice,
+ int max_slices);
+
+struct cfa_tcam_mgr_hwops_funcs {
+ cfa_tcam_mgr_hwop_set_func_t set;
+ cfa_tcam_mgr_hwop_get_func_t get;
+ cfa_tcam_mgr_hwop_free_func_t free;
+};
+#endif /* CFA_TCAM_MGR_DEVICE_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
new file mode 100644
index 0000000000..0fb5563cc3
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+/*
+ * This file will "do the right thing" for each of the primitives set, get and
+ * free. The TCAM manager is running in the core, so the tables will be cached.
+ * Set and free messages will also be sent to the firmware. Instead of sending
+ * get messages, the entry will be read from the cached copy thus saving a
+ * firmware message.
+ */
+
+#include "tf_tcam.h"
+#include "hcapi_cfa_defs.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_hwop_msg.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+#include "tf_session.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_util.h"
+
+/*
+ * The free hwop will free more than a single slice so cannot be used.
+ */
+struct cfa_tcam_mgr_hwops_funcs hwop_funcs;
+
+int
+cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type)
+{
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ return cfa_tcam_mgr_hwops_get_funcs_p4(&hwop_funcs);
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ return cfa_tcam_mgr_hwops_get_funcs_p58(&hwop_funcs);
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+}
+
+/*
+ * This is the glue between the TCAM manager and the firmware HW operations. It
+ * is intended to abstract out the location of the TCAM manager so that the TCAM
+ * manager code will be the same whether or not it is actually using the
+ * firmware.
+ */
+
+int
+cfa_tcam_mgr_entry_set_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_set_parms *parms,
+ int row, int slice,
+ int max_slices __rte_unused)
+{
+ cfa_tcam_mgr_hwop_set_func_t set_func;
+
+ set_func = hwop_funcs.set;
+ if (set_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ struct tf_tcam_set_parms sparms;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ int rc;
+ enum tf_tcam_tbl_type type =
+ cfa_tcam_mgr_get_phys_table_type(parms->type);
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ memset(&sparms, 0, sizeof(sparms));
+ sparms.dir = parms->dir;
+ sparms.type = type;
+ sparms.hcapi_type = parms->hcapi_type;
+ sparms.idx = (row * max_slices) + slice;
+ sparms.key = parms->key;
+ sparms.mask = parms->mask;
+ sparms.key_size = parms->key_size;
+ sparms.result = parms->result;
+ sparms.result_size = parms->result_size;
+
+ rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms);
+ if (rc) {
+ /* Log error */
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d set failed, rc:%d\n",
+ parms->id, -rc);
+ return rc;
+ }
+
+ return set_func(sess_idx, parms, row, slice, max_slices);
+}
+
+int
+cfa_tcam_mgr_entry_get_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_get_parms *parms,
+ int row, int slice,
+ int max_slices __rte_unused)
+{
+ cfa_tcam_mgr_hwop_get_func_t get_func;
+
+ get_func = hwop_funcs.get;
+ if (get_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ return get_func(sess_idx, parms, row, slice, max_slices);
+}
+
+int
+cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice,
+ int key_size,
+ int result_size,
+ int max_slices)
+{
+ cfa_tcam_mgr_hwop_free_func_t free_func;
+
+ free_func = hwop_funcs.free;
+ if (free_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+ int rc;
+ enum tf_tcam_tbl_type type =
+ cfa_tcam_mgr_get_phys_table_type(parms->type);
+
+ /* Free will clear an entire row. */
+ /* Use set message to clear an individual entry */
+ struct tf_tcam_set_parms sparms;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 };
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 };
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ if (key_size > CFA_TCAM_MGR_MAX_KEY_SIZE) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d key size is %d greater than:%d\n",
+ parms->id, key_size,
+ CFA_TCAM_MGR_MAX_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ if (result_size > CFA_TCAM_MGR_MAX_KEY_SIZE) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d result size is %d greater than:%d\n",
+ parms->id, result_size,
+ CFA_TCAM_MGR_MAX_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ memset(&sparms, 0, sizeof(sparms));
+ memset(&key, 0, sizeof(key));
+ memset(&mask, 0xff, sizeof(mask));
+
+ sparms.dir = parms->dir;
+ sparms.type = type;
+ sparms.hcapi_type = parms->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = key;
+ sparms.idx = (row * max_slices) + slice;
+ sparms.key_size = key_size;
+ sparms.result_size = result_size;
+
+ rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms);
+ if (rc) {
+ /* Log error */
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Row %d, slice %d set failed, "
+ "rc:%d.\n",
+ row,
+ slice,
+ rc);
+ return rc;
+ }
+ return free_func(sess_idx, parms, row, slice, max_slices);
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
new file mode 100644
index 0000000000..f7ba625c07
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_HWOP_MSG_H
+#define CFA_TCAM_MGR_HWOP_MSG_H
+
+int
+cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type);
+
+int
+cfa_tcam_mgr_entry_set_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms,
+ int row, int slice, int max_slices);
+int
+cfa_tcam_mgr_entry_get_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_get_parms *parms,
+ int row, int slice, int max_slices);
+int
+cfa_tcam_mgr_entry_free_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int key_size,
+ int result_size, int max_slices);
+#endif /* CFA_TCAM_MGR_HWOP_MSG_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
new file mode 100644
index 0000000000..63c84c5938
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
@@ -0,0 +1,921 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include "hcapi_cfa_defs.h"
+
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_p4.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_resource_types.h"
+#include "tfp.h"
+#include "assert.h"
+#include "tf_util.h"
+
+/*
+ * Sizings of the TCAMs on P4
+ */
+
+#define MAX_ROW_WIDTH 48
+#define MAX_RESULT_SIZE 8
+
+#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#endif
+
+/*
+ * TCAM definitions
+ *
+ * These define the TCAMs in HW.
+ *
+ * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported
+ * by HW or not supported by TCAM Manager.
+ */
+
+/** L2 Context TCAM */
+#define L2_CTXT_TCAM_RX_MAX_SLICES 1
+#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(167)
+#define L2_CTXT_TCAM_RX_NUM_ROWS 1024
+#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \
+ L2_CTXT_TCAM_RX_NUM_ROWS)
+#define L2_CTXT_TCAM_RX_RESULT_SIZE 8
+
+#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES
+#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH
+#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS
+#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES
+#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE
+
+/** Profile TCAM */
+#define PROF_TCAM_RX_MAX_SLICES 1
+#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(81)
+#define PROF_TCAM_RX_NUM_ROWS 1024
+#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \
+ PROF_TCAM_RX_NUM_ROWS)
+#define PROF_TCAM_RX_RESULT_SIZE 8
+
+#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES
+#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH
+#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS
+#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES
+#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE
+
+/** Wildcard TCAM */
+#define WC_TCAM_RX_MAX_SLICES 4
+/* 82 bits per slice */
+#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_WORD_ALIGN(82) * \
+ WC_TCAM_RX_MAX_SLICES)
+#define WC_TCAM_RX_NUM_ROWS 256
+#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define WC_TCAM_RX_RESULT_SIZE 4
+
+#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES
+#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH
+#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS
+#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES
+#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE
+
+/** Source Properties TCAM */
+#define SP_TCAM_RX_MAX_SLICES 1
+#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(89)
+#define SP_TCAM_RX_NUM_ROWS 512
+#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define SP_TCAM_RX_RESULT_SIZE 8
+
+#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES
+#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH
+#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS
+#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES
+#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE
+
+/** Connection Tracking Rule TCAM */
+#define CT_RULE_TCAM_RX_MAX_SLICES 1
+#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(16)
+#define CT_RULE_TCAM_RX_NUM_ROWS 0
+#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \
+ CT_RULE_TCAM_RX_NUM_ROWS)
+#define CT_RULE_TCAM_RX_RESULT_SIZE 8
+
+#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES
+#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH
+#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS
+#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES
+#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE
+
+/** Virtual Edge Bridge TCAM */
+#define VEB_TCAM_RX_MAX_SLICES 1
+#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(78)
+/* Tx only */
+#define VEB_TCAM_RX_NUM_ROWS 0
+#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+#define VEB_TCAM_RX_RESULT_SIZE 8
+
+#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES
+#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH
+#define VEB_TCAM_TX_NUM_ROWS 1024
+#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE
+
+/* Declare the table rows for each table here. If new tables are added to the
+ * enum tf_tcam_tbl_type, then new declarations will be needed here.
+ *
+ * The numeric suffix of the structure type indicates how many slices a
+ * particular TCAM supports.
+ *
+ * Array sizes have 1 added to avoid zero length arrays.
+ */
+
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ { /* RX */
+ { /* High AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* High APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* Low AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* Low APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_RX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_RX_MAX_ENTRIES,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_RX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if VEB_TCAM_RX_NUM_ROWS > 0
+ .end_row = VEB_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = VEB_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = VEB_TCAM_RX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ },
+ { /* TX */
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_TX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_TX_MAX_ENTRIES,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_TX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = VEB_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = VEB_TCAM_TX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ },
+};
+
+static struct cfa_tcam_mgr_entry_data entry_data_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+static struct sbmp session_bmp_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+int
+cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp)
+{
+ *session_bmp = session_bmp_p4[sess_idx];
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data)
+{
+ int max_row_width = 0;
+ int max_result_size = 0;
+ int dir, type;
+
+ *global_entry_data = entry_data_p4[sess_idx];
+
+ memcpy(&cfa_tcam_mgr_tables[sess_idx],
+ &cfa_tcam_mgr_tables_p4,
+ sizeof(cfa_tcam_mgr_tables[sess_idx]));
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width >
+ max_row_width)
+ max_row_width =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].row_width;
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size >
+ max_result_size)
+ max_result_size =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].result_size;
+ }
+ }
+
+ if (max_row_width != MAX_ROW_WIDTH) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_ROW_WIDTH (%d) does not match actual "
+ "value (%d).\n",
+ MAX_ROW_WIDTH,
+ max_row_width);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (max_result_size != MAX_RESULT_SIZE) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_RESULT_SIZE (%d) does not match actual "
+ "value (%d).\n",
+ MAX_RESULT_SIZE,
+ max_result_size);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ return 0;
+}
+
+/* HW OP declarations begin here */
+struct cfa_tcam_mgr_TCAM_row_data {
+ int key_size;
+ int result_size;
+ uint8_t key[MAX_ROW_WIDTH];
+ uint8_t mask[MAX_ROW_WIDTH];
+ uint8_t result[MAX_RESULT_SIZE];
+};
+
+/* These macros are only needed to avoid exceeding 80 columns */
+#define L2_CTXT_RX_MAX_ROWS \
+ (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS)
+#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS)
+#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define CT_RULE_RX_MAX_ROWS \
+ (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS)
+#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+
+#define L2_CTXT_TX_MAX_ROWS \
+ (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS)
+#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS)
+#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS)
+#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS)
+#define CT_RULE_TX_MAX_ROWS \
+ (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS)
+#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+
+static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = {
+ L2_CTXT_RX_MAX_ROWS,
+ L2_CTXT_RX_MAX_ROWS,
+ PROF_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ SP_RX_MAX_ROWS,
+ CT_RULE_RX_MAX_ROWS,
+ VEB_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS
+};
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data *
+row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = {
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ },
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ }
+};
+
+static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type)
+{
+ if (type >= TF_TCAM_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return cfa_tcam_mgr_max_rows[type];
+}
+
+static int cfa_tcam_mgr_hwop_set(int sess_idx,
+ struct cfa_tcam_mgr_set_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ this_row->key_size = parms->key_size;
+ memcpy(&this_row->key, parms->key, parms->key_size);
+ memcpy(&this_row->mask, parms->mask, parms->key_size);
+ this_row->result_size = parms->result_size;
+ if (parms->result != ((void *)0))
+ memcpy(&this_row->result, parms->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_get(int sess_idx,
+ struct cfa_tcam_mgr_get_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ parms->key_size = this_row->key_size;
+ parms->result_size = this_row->result_size;
+ if (parms->key != ((void *)0))
+ memcpy(parms->key, &this_row->key, parms->key_size);
+ if (parms->mask != ((void *)0))
+ memcpy(parms->mask, &this_row->mask, parms->key_size);
+ if (parms->result != ((void *)0))
+ memcpy(parms->result, &this_row->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_free(int sess_idx,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ memset(&this_row->key, 0, sizeof(this_row->key));
+ memset(&this_row->mask, 0, sizeof(this_row->mask));
+ memset(&this_row->result, 0, sizeof(this_row->result));
+ this_row->key_size = 0;
+ this_row->result_size = 0;
+ return 0;
+};
+
+int cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs)
+{
+ hwop_funcs->set = cfa_tcam_mgr_hwop_set;
+ hwop_funcs->get = cfa_tcam_mgr_hwop_get;
+ hwop_funcs->free = cfa_tcam_mgr_hwop_free;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
new file mode 100644
index 0000000000..3ca59b2aeb
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_P4_H
+#define CFA_TCAM_MGR_P4_H
+
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_sbmp.h"
+
+int
+cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data);
+
+int
+cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp);
+
+int
+cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs);
+#endif /* CFA_TCAM_MGR_P4_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
new file mode 100644
index 0000000000..c9a04dc4e9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
@@ -0,0 +1,926 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include "hcapi_cfa_defs.h"
+
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_resource_types.h"
+#include "tfp.h"
+#include "assert.h"
+#include "tf_util.h"
+
+/*
+ * Sizings of the TCAMs on P5
+ */
+
+#define MAX_ROW_WIDTH 96
+#define MAX_RESULT_SIZE 8
+
+#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#endif
+
+/*
+ * TCAM definitions
+ *
+ * These define the TCAMs in HW.
+ *
+ * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported
+ * by HW or not supported by TCAM Manager.
+ */
+
+/** L2 Context TCAM */
+#define L2_CTXT_TCAM_RX_MAX_SLICES 1
+#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(214)
+#define L2_CTXT_TCAM_RX_NUM_ROWS 1024
+#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \
+ L2_CTXT_TCAM_RX_NUM_ROWS)
+#define L2_CTXT_TCAM_RX_RESULT_SIZE 8
+
+#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES
+#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH
+#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS
+#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES
+#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE
+
+/** Profile TCAM */
+#define PROF_TCAM_RX_MAX_SLICES 1
+#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(94)
+#define PROF_TCAM_RX_NUM_ROWS 256
+#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \
+ PROF_TCAM_RX_NUM_ROWS)
+#define PROF_TCAM_RX_RESULT_SIZE 8
+
+#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES
+#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH
+#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS
+#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES
+#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE
+
+/** Wildcard TCAM */
+#define WC_TCAM_RX_MAX_SLICES 4
+/* 162 bits per slice */
+#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_64B_WORD_ALIGN(162) * \
+ WC_TCAM_RX_MAX_SLICES)
+#define WC_TCAM_RX_NUM_ROWS 2048
+#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define WC_TCAM_RX_RESULT_SIZE 8
+
+#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES
+#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH
+#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS
+#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES
+#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE
+
+/** Source Properties TCAM */
+#define SP_TCAM_RX_MAX_SLICES 1
+#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(89)
+#define SP_TCAM_RX_NUM_ROWS 0
+#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define SP_TCAM_RX_RESULT_SIZE 8
+
+#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES
+#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH
+#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS
+#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES
+#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE
+
+/** Connection Tracking Rule TCAM */
+#define CT_RULE_TCAM_RX_MAX_SLICES 1
+#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(16)
+#define CT_RULE_TCAM_RX_NUM_ROWS 0
+#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \
+ CT_RULE_TCAM_RX_NUM_ROWS)
+#define CT_RULE_TCAM_RX_RESULT_SIZE 8
+
+#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES
+#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH
+#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS
+#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES
+#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE
+
+/** Virtual Edge Bridge TCAM */
+#define VEB_TCAM_RX_MAX_SLICES 1
+#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(79)
+/* Tx only */
+#define VEB_TCAM_RX_NUM_ROWS 0
+#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+#define VEB_TCAM_RX_RESULT_SIZE 8
+
+#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES
+#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH
+#define VEB_TCAM_TX_NUM_ROWS 1024
+#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE
+
+/* Declare the table rows for each table here. If new tables are added to the
+ * enum tf_tcam_tbl_type, then new declarations will be needed here.
+ *
+ * The numeric suffix of the structure type indicates how many slices a
+ * particular TCAM supports.
+ *
+ * Array sizes have 1 added to avoid zero length arrays.
+ */
+
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ { /* RX */
+ { /* High AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* High APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* Low AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* Low APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_RX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_RX_MAX_ENTRIES,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_RX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if VEB_TCAM_RX_NUM_ROWS > 0
+ .end_row = VEB_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = VEB_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = VEB_TCAM_RX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ },
+ { /* TX */
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_TX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_TX_MAX_ENTRIES,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_TX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = VEB_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = VEB_TCAM_TX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ },
+};
+
+static struct cfa_tcam_mgr_entry_data entry_data_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+static struct sbmp session_bmp_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+int
+cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp)
+{
+ *session_bmp = session_bmp_p58[sess_idx];
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data)
+{
+ int max_row_width = 0;
+ int max_result_size = 0;
+ int dir, type;
+
+ *global_entry_data = entry_data_p58[sess_idx];
+
+ memcpy(&cfa_tcam_mgr_tables[sess_idx],
+ &cfa_tcam_mgr_tables_p58,
+ sizeof(cfa_tcam_mgr_tables[sess_idx]));
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width >
+ max_row_width)
+ max_row_width =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].row_width;
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size >
+ max_result_size)
+ max_result_size =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].result_size;
+ }
+ }
+
+ if (max_row_width != MAX_ROW_WIDTH) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_ROW_WIDTH (%d) does not match actual "
+ "value (%d).\n",
+ MAX_ROW_WIDTH,
+ max_row_width);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (max_result_size != MAX_RESULT_SIZE) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_RESULT_SIZE (%d) does not match actual "
+ "value (%d).\n",
+ MAX_RESULT_SIZE,
+ max_result_size);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ return 0;
+}
+
+/* HW OP declarations begin here */
+
+struct cfa_tcam_mgr_TCAM_row_data {
+ int key_size;
+ int result_size;
+ uint8_t key[MAX_ROW_WIDTH];
+ uint8_t mask[MAX_ROW_WIDTH];
+ uint8_t result[MAX_RESULT_SIZE];
+};
+
+/* These macros are only needed to avoid exceeding 80 columns */
+#define L2_CTXT_RX_MAX_ROWS \
+ (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS)
+#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS)
+#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define CT_RULE_RX_MAX_ROWS \
+ (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS)
+#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+
+#define L2_CTXT_TX_MAX_ROWS \
+ (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS)
+#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS)
+#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS)
+#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS)
+#define CT_RULE_TX_MAX_ROWS \
+ (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS)
+#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+
+static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = {
+ L2_CTXT_RX_MAX_ROWS,
+ L2_CTXT_RX_MAX_ROWS,
+ PROF_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ SP_RX_MAX_ROWS,
+ CT_RULE_RX_MAX_ROWS,
+ VEB_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS
+};
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data *
+row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = {
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ },
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ }
+};
+
+static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type)
+{
+ if (type >= TF_TCAM_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return cfa_tcam_mgr_max_rows[type];
+}
+
+static int cfa_tcam_mgr_hwop_set(int sess_idx,
+ struct cfa_tcam_mgr_set_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ this_row->key_size = parms->key_size;
+ memcpy(&this_row->key, parms->key, parms->key_size);
+ memcpy(&this_row->mask, parms->mask, parms->key_size);
+ this_row->result_size = parms->result_size;
+ if (parms->result != ((void *)0))
+ memcpy(&this_row->result, parms->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_get(int sess_idx,
+ struct cfa_tcam_mgr_get_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ parms->key_size = this_row->key_size;
+ parms->result_size = this_row->result_size;
+ if (parms->key != ((void *)0))
+ memcpy(parms->key, &this_row->key, parms->key_size);
+ if (parms->mask != ((void *)0))
+ memcpy(parms->mask, &this_row->mask, parms->key_size);
+ if (parms->result != ((void *)0))
+ memcpy(parms->result, &this_row->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_free(int sess_idx,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ memset(&this_row->key, 0, sizeof(this_row->key));
+ memset(&this_row->mask, 0, sizeof(this_row->mask));
+ memset(&this_row->result, 0, sizeof(this_row->result));
+ this_row->key_size = 0;
+ this_row->result_size = 0;
+ return 0;
+};
+
+int cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs
+ *hwop_funcs)
+{
+ hwop_funcs->set = cfa_tcam_mgr_hwop_set;
+ hwop_funcs->get = cfa_tcam_mgr_hwop_get;
+ hwop_funcs->free = cfa_tcam_mgr_hwop_free;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
new file mode 100644
index 0000000000..7640f91911
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_P58_H
+#define CFA_TCAM_MGR_P58_H
+
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_sbmp.h"
+
+int
+cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data);
+
+int
+cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp);
+
+int
+cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs);
+#endif /* CFA_TCAM_MGR_P58_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
new file mode 100644
index 0000000000..6ad158abe8
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_SBMP_H
+#define CFA_TCAM_MGR_SBMP_H
+
+#include <inttypes.h>
+
+#include "cfa_tcam_mgr.h"
+
+#define SBMP_SESSION_MAX TF_TCAM_MAX_SESSIONS
+#if SBMP_SESSION_MAX <= 16
+#define SBMP_WORD_WIDTH 16
+#else
+#define SBMP_WORD_WIDTH 32
+#endif
+
+#define SBMP_WIDTH (((SBMP_SESSION_MAX + SBMP_WORD_WIDTH - 1) / \
+ SBMP_WORD_WIDTH) * SBMP_WORD_WIDTH)
+#define SBMP_WORD_MAX ((SBMP_WIDTH + SBMP_WORD_WIDTH - 1) / SBMP_WORD_WIDTH)
+
+struct sbmp {
+#if SBMP_WORD_WIDTH == 16
+ uint16_t bits[SBMP_WORD_MAX];
+#elif SBMP_WORD_WIDTH == 32
+ uint32_t bits[SBMP_WORD_MAX];
+#else
+ uint64_t bits[SBMP_WORD_MAX];
+#endif
+};
+
+#define SBMP_WORD_GET(bm, word) ((bm).bits[(word)])
+
+#if SBMP_WORD_MAX == 1
+#define SBMP_WENT(session) (0)
+#define SBMP_WBIT(session) (1U << (session))
+#define SBMP_CLEAR(bm) (SBMP_WORD_GET(bm, 0) = 0)
+#define SBMP_IS_NULL(bm) (SBMP_WORD_GET(bm, 0) == 0)
+#define SBMP_COUNT(bm, count) \
+ (count = __builtin_popcount(SBMP_WORD_GET(bm, 0)))
+#elif SBMP_WORD_MAX == 2
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = 0; \
+ } while (0)
+#define SBMP_IS_NULL(bm) \
+ (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0)
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 1))); \
+ } while (0)
+#elif SBMP_WORD_MAX == 3
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = \
+ SBMP_WORD_GET(*_bm, 2) = 0; \
+ } while (0)
+#define SBMP_IS_NULL(bm) \
+ (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0 && \
+ SBMP_WORD_GET(bm, 2) == 0)
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 1)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 2)); \
+ } while (0)
+#else /* SBMP_WORD_MAX > 3 */
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ int _w; \
+ for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \
+ SBMP_WORD_GET(*_bm, _w) = 0; \
+ } \
+ } while (0)
+#define SBMP_IS_NULL(bm) (sbmp_bmnull(&(bm)))
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ int _count, _w; \
+ _count = 0; \
+ for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \
+ _count += __builtin_popcount(SBMP_WORD_GET(*_bm, _w)); \
+ } \
+ count = _count; \
+ } while (0)
+
+/* Only needed if SBMP_WORD_MAX > 3 */
+static int
+sbmp_bmnull(struct ebmp *bmp)
+{
+ int i;
+
+ for (i = 0; i < SBMP_WORD_MAX; i++) {
+ if (SBMP_WORD_GET(*bmp, i) != 0)
+ return 0;
+ }
+ return 1;
+}
+#endif
+
+/* generics that use the previously defined helpers */
+#define SBMP_NOT_NULL(bm) (!SBMP_IS_NULL(bm))
+
+#define SBMP_ENTRY(bm, session) \
+ (SBMP_WORD_GET(bm, SBMP_WENT(session)))
+#define SBMP_MEMBER(bm, session) \
+ ((SBMP_ENTRY(bm, session) & SBMP_WBIT(session)) != 0)
+#define SBMP_SESSION_ADD(bm, session) \
+ (SBMP_ENTRY(bm, session) |= SBMP_WBIT(session))
+#define SBMP_SESSION_REMOVE(bm, session) \
+ (SBMP_ENTRY(bm, session) &= ~SBMP_WBIT(session))
+#endif /* CFA_TCAM_MGR_SBMP_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
new file mode 100644
index 0000000000..3d085bc69e
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
@@ -0,0 +1,377 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <inttypes.h>
+#include "hcapi_cfa_defs.h"
+#include "tf_util.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_session.h"
+#include "cfa_tcam_mgr_sbmp.h"
+#include "tfp.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+
+struct cfa_tcam_mgr_session_data {
+ uint32_t session_id;
+ /* The following are per-session values */
+ uint16_t max_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ uint16_t used_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+};
+
+static struct cfa_tcam_mgr_session_data session_data[TF_TCAM_MAX_SESSIONS];
+
+static uint16_t last_entry_id;
+
+static struct sbmp *session_bmp[TF_TCAM_MAX_SESSIONS];
+
+int
+cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type)
+{
+ int rc;
+
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ rc = cfa_tcam_mgr_sess_table_get_p4(sess_idx, &session_bmp[sess_idx]);
+ break;
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ rc = cfa_tcam_mgr_sess_table_get_p58(sess_idx, &session_bmp[sess_idx]);
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", type);
+ rc = -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ return rc;
+}
+
+int
+cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context,
+ uint32_t *session_id)
+{
+ if (context == NULL) {
+ CFA_TCAM_MGR_LOG_0(ERR, "context passed as NULL pointer.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ *session_id = context->tfp->session->session_id.id;
+ return 0;
+}
+
+int
+cfa_tcam_mgr_session_find(unsigned int session_id)
+{
+ unsigned int sess_idx;
+
+ for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) {
+ if (session_data[sess_idx].session_id == session_id)
+ return sess_idx;
+ }
+
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+}
+
+int
+cfa_tcam_mgr_session_add(unsigned int session_id)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx >= 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session is already bound.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(BUSY);
+ }
+
+ /* Session not found in table, find first empty entry. */
+ for (sess_idx = 0;
+ sess_idx < (signed int)ARRAY_SIZE(session_data);
+ sess_idx++) {
+ if (session_data[sess_idx].session_id == 0)
+ break;
+ }
+
+ if (sess_idx >= (signed int)ARRAY_SIZE(session_data)) {
+ /* No room in the session table */
+ CFA_TCAM_MGR_LOG_0(ERR, "Session table is full.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NOMEM);
+ }
+
+ session_data[sess_idx].session_id = session_id;
+
+ return sess_idx;
+}
+
+int
+cfa_tcam_mgr_session_free(unsigned int session_id,
+ struct cfa_tcam_mgr_context *context)
+{
+ struct cfa_tcam_mgr_free_parms free_parms;
+ int entry_id;
+ int sess_idx = cfa_tcam_mgr_session_find(session_id);
+
+ if (sess_idx < 0)
+ return sess_idx;
+
+ memset(&free_parms, 0, sizeof(free_parms));
+ /* Since we are freeing all pending TCAM entries (which is typically
+ * done during tcam_unbind), we don't know the type of each entry.
+ * So we set the type to MAX as a hint to cfa_tcam_mgr_free() to
+ * figure out the actual type. We need to set it through each
+ * iteration in the loop below; otherwise, the type determined for
+ * the first entry would be used for subsequent entries that may or
+ * may not be of the same type, resulting in errors.
+ */
+ for (entry_id = 0; entry_id < cfa_tcam_mgr_max_entries[sess_idx]; entry_id++) {
+ if (SBMP_MEMBER(session_bmp[sess_idx][entry_id], sess_idx)) {
+ SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx);
+
+ free_parms.id = entry_id;
+ free_parms.type = CFA_TCAM_MGR_TBL_TYPE_MAX;
+ cfa_tcam_mgr_free(context, &free_parms);
+ }
+ }
+
+ memset(&session_data[sess_idx], 0, sizeof(session_data[sess_idx]));
+ return 0;
+}
+
+int
+cfa_tcam_mgr_session_cfg(unsigned int session_id,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX])
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_session_data *session_entry;
+ unsigned int dir, type;
+ int sess_idx = cfa_tcam_mgr_session_find(session_id);
+ uint16_t requested_cnt;
+
+ if (sess_idx < 0)
+ return sess_idx;
+
+ session_entry = &session_data[sess_idx];
+
+ /* Validate session request */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ requested_cnt = tcam_cnt[dir][type];
+ /*
+ * Only check if table supported (max_entries > 0).
+ */
+ if (table_data->max_entries > 0 &&
+ requested_cnt > table_data->max_entries) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Requested %d, available %d.\n",
+ requested_cnt,
+ table_data->max_entries);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+ }
+ }
+
+ memcpy(session_entry->max_entries, tcam_cnt,
+ sizeof(session_entry->max_entries));
+ return 0;
+}
+
+void
+cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type dst_type,
+ enum cfa_tcam_mgr_tbl_type src_type)
+{
+ session_data[sess_idx].used_entries[dir][dst_type]++;
+ session_data[sess_idx].used_entries[dir][src_type]--;
+}
+
+int
+cfa_tcam_mgr_session_entry_alloc(unsigned int session_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ if (session_data[sess_idx].used_entries[dir][type] >=
+ session_data[sess_idx].max_entries[dir][type]) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Table full (session).\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ do {
+ last_entry_id++;
+ if (cfa_tcam_mgr_max_entries[sess_idx] <= last_entry_id)
+ last_entry_id = 0;
+ } while (!SBMP_IS_NULL(session_bmp[sess_idx][last_entry_id]));
+
+ SBMP_SESSION_ADD(session_bmp[sess_idx][last_entry_id], sess_idx);
+
+ session_data[sess_idx].used_entries[dir][type] += 1;
+
+ return last_entry_id;
+}
+
+int
+cfa_tcam_mgr_session_entry_free(unsigned int session_id,
+ unsigned int entry_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx);
+ session_data[sess_idx].used_entries[dir][type] -= 1;
+
+ return 0;
+}
+
+#if SBMP_WORD_WIDTH == 16
+#define SBMP_FORMAT PRIX16
+#define SBMP_PRECISION "4"
+#elif SBMP_WORD_WIDTH == 32
+#define SBMP_FORMAT PRIX32
+#define SBMP_PRECISION "8"
+#elif SBMP_WORD_WIDTH == 64
+#define SBMP_FORMAT PRIX64
+#define SBMP_PRECISION "16"
+#else
+#error "Invalid value for SBMP_WORD_WIDTH."
+#endif
+
+static void
+cfa_tcam_mgr_session_bitmap_print(struct sbmp *session_bmp)
+{
+ unsigned int i;
+
+ printf("0x");
+ for (i = 0;
+ i < ARRAY_SIZE(session_bmp->bits);
+ i++) {
+ printf("%0" SBMP_PRECISION SBMP_FORMAT,
+ session_bmp->bits[i]);
+ }
+}
+
+#define SESSION_DUMP_HEADER_1 " RX TX\n"
+#define SESSION_DUMP_HEADER_2 \
+ " Max Used Max Used\n"
+
+static void
+cfa_tcam_mgr_session_printf(struct cfa_tcam_mgr_session_data *session,
+ enum cfa_tcam_mgr_tbl_type tbl_type)
+{
+ printf("%-22s: %5u %5u %5u %5u\n",
+ cfa_tcam_mgr_tbl_2_str(tbl_type),
+ session->max_entries[TF_DIR_RX][tbl_type],
+ session->used_entries[TF_DIR_RX][tbl_type],
+ session->max_entries[TF_DIR_TX][tbl_type],
+ session->used_entries[TF_DIR_TX][tbl_type]);
+}
+
+void
+cfa_tcam_mgr_sessions_dump(void)
+{
+ struct cfa_tcam_mgr_session_data *session;
+ unsigned int sess_idx;
+ bool sess_found = false;
+ enum cfa_tcam_mgr_tbl_type tbl_type;
+
+ printf("\nTCAM Sessions Table:\n");
+ for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) {
+ if (session_data[sess_idx].session_id != 0) {
+ session = &session_data[sess_idx];
+ if (!sess_found) {
+ printf(SESSION_DUMP_HEADER_1);
+ printf(SESSION_DUMP_HEADER_2);
+ }
+ printf("Session 0x%08x:\n",
+ session->session_id);
+ for (tbl_type = CFA_TCAM_MGR_TBL_TYPE_START;
+ tbl_type < CFA_TCAM_MGR_TBL_TYPE_MAX;
+ tbl_type++) {
+ cfa_tcam_mgr_session_printf(session, tbl_type);
+ }
+ sess_found = true;
+ }
+ }
+
+ if (!sess_found)
+ printf("No sessions found.\n");
+}
+
+/* This dumps all the sessions using an entry */
+void
+cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id)
+{
+ bool session_found = false;
+
+ if (id >= cfa_tcam_mgr_max_entries[sess_idx]) {
+ printf("Entry ID %u out of range for sess_idx %d. Max ID %u.\n",
+ id, sess_idx, cfa_tcam_mgr_max_entries[sess_idx] - 1);
+ return;
+ }
+
+ if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) {
+ printf("Sessions using entry ID %u:\n", id);
+ for (sess_idx = 0; sess_idx < SBMP_SESSION_MAX; sess_idx++)
+ if (SBMP_MEMBER(session_bmp[sess_idx][id], (sess_idx))) {
+ if (session_data[sess_idx].session_id != 0) {
+ printf("0x%08x (index %d)\n",
+ session_data[sess_idx].session_id,
+ sess_idx);
+ session_found = true;
+ } else {
+ printf("Error! Entry ID %u used by "
+ "session index %d which is not "
+ "in use.\n",
+ id, sess_idx);
+ }
+ }
+ if (!session_found)
+ printf("No sessions using entry ID %u.\n", id);
+ } else {
+ printf("Entry ID %u not in use.\n",
+ id);
+ return;
+ }
+}
+
+/* This dumps all the entries in use by any session */
+void
+cfa_tcam_mgr_session_entries_dump(int sess_idx)
+{
+ bool entry_found = false;
+ uint16_t id;
+
+ printf("\nGlobal Maximum Entries for sess_idx %d: %d\n\n",
+ sess_idx, cfa_tcam_mgr_max_entries[sess_idx]);
+ printf("TCAM Session Entry Table:\n");
+ for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) {
+ if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) {
+ if (!entry_found)
+ printf(" EID Session bitmap\n");
+ printf("%5u ", id);
+ cfa_tcam_mgr_session_bitmap_print(&session_bmp[sess_idx][id]);
+ printf("\n");
+ entry_found = true;
+ }
+ }
+
+ if (!entry_found)
+ printf("No entries found.\n");
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
new file mode 100644
index 0000000000..69311b7e1d
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_SESSION_H
+#define CFA_TCAM_MGR_SESSION_H
+
+#include <inttypes.h>
+#include "cfa_tcam_mgr.h"
+
+int
+cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type);
+
+int
+cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context,
+ uint32_t *session_id);
+
+int
+cfa_tcam_mgr_session_find(unsigned int session_id);
+
+int
+cfa_tcam_mgr_session_add(unsigned int session_id);
+
+int
+cfa_tcam_mgr_session_free(unsigned int session_id,
+ struct cfa_tcam_mgr_context *context);
+
+int
+cfa_tcam_mgr_session_cfg(unsigned int session_id,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]);
+
+int
+cfa_tcam_mgr_session_entry_alloc(unsigned int session_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type);
+int
+cfa_tcam_mgr_session_entry_free(unsigned int session_id,
+ unsigned int entry_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type);
+
+void
+cfa_tcam_mgr_sessions_dump(void);
+void
+cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id);
+void
+cfa_tcam_mgr_session_entries_dump(int sess_idx);
+
+void
+cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type dst_type,
+ enum cfa_tcam_mgr_tbl_type src_type);
+#endif /* CFA_TCAM_MGR_SESSION_H */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f812e471d1..ae44aa34cf 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -1,36 +1,42 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2021 Broadcom
+# Copyright(c) 2023 Broadcom
#Include the folder for headers
includes += include_directories('.')
#Add the source files
sources += files(
- 'tf_core.c',
'bitalloc.c',
- 'tf_msg.c',
- 'll.c',
+ 'cfa_tcam_mgr.c',
+ 'cfa_tcam_mgr_hwop_msg.c',
+ 'cfa_tcam_mgr_p4.c',
+ 'cfa_tcam_mgr_p58.c',
+ 'cfa_tcam_mgr_session.c',
'dpool.c',
+ 'll.c',
'rand.c',
'stack.c',
- 'tf_rm.c',
- 'tf_tbl.c',
- 'tf_tbl_sram.c',
- 'tf_sram_mgr.c',
+ 'tf_core.c',
+ 'tf_device.c',
+ 'tf_device_p4.c',
+ 'tf_device_p58.c',
'tf_em_common.c',
+ 'tf_em_hash_internal.c',
'tf_em_host.c',
'tf_em_internal.c',
- 'tf_em_hash_internal.c',
- 'tfp.c',
- 'tf_util.c',
- 'tf_device.c',
- 'tf_device_p4.c',
'tf_global_cfg.c',
+ 'tf_hash.c',
'tf_identifier.c',
'tf_if_tbl.c',
+ 'tf_msg.c',
+ 'tfp.c',
+ 'tf_rm.c',
'tf_session.c',
+ 'tf_sram_mgr.c',
+ 'tf_tbl.c',
+ 'tf_tbl_sram.c',
'tf_tcam.c',
+ 'tf_tcam_mgr_msg.c',
'tf_tcam_shared.c',
- 'tf_hash.c',
- 'tf_device_p58.c')
+ 'tf_util.c')
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 038e439101..3a812bee3a 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -34,8 +34,8 @@ tf_open_session(struct tf *tfp,
* side. It is assumed that the Firmware will be supported if
* firmware open session succeeds.
*/
- if (parms->device_type != TF_DEVICE_TYPE_WH &&
- parms->device_type != TF_DEVICE_TYPE_THOR &&
+ if (parms->device_type != TF_DEVICE_TYPE_P4 &&
+ parms->device_type != TF_DEVICE_TYPE_P5 &&
parms->device_type != TF_DEVICE_TYPE_SR) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
@@ -83,7 +83,7 @@ tf_open_session(struct tf *tfp,
return rc;
TFP_DRV_LOG(INFO,
- "domain:%d, bus:%d, device:%u\n",
+ "domain:%x, bus:%x, device:%u\n",
parms->session_id.internal.domain,
parms->session_id.internal.bus,
parms->session_id.internal.device);
@@ -176,7 +176,7 @@ tf_close_session(struct tf *tfp)
return rc;
TFP_DRV_LOG(INFO,
- "domain:%d, bus:%d, device:%d\n",
+ "domain:%d, bus:%x, device:%d\n",
cparms.session_id->internal.domain,
cparms.session_id->internal.bus,
cparms.session_id->internal.device);
@@ -742,7 +742,6 @@ tf_set_tcam_entry(struct tf *tfp,
memset(&sparms, 0, sizeof(struct tf_tcam_set_parms));
-
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -790,6 +789,10 @@ tf_set_tcam_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ TFP_DRV_LOG(DEBUG,
+ "%s: TCAM type %d set idx:%d key size %d result size %d\n",
+ tf_dir_2_str(parms->dir), sparms.type,
+ sparms.idx, sparms.key_size, sparms.result_size);
return 0;
}
@@ -807,7 +810,6 @@ tf_get_tcam_entry(struct tf *tfp __rte_unused,
memset(&gparms, 0, sizeof(struct tf_tcam_get_parms));
-
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -1812,8 +1814,8 @@ int tf_get_version(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_WH &&
- parms->device_type != TF_DEVICE_TYPE_THOR &&
+ if (parms->device_type != TF_DEVICE_TYPE_P4 &&
+ parms->device_type != TF_DEVICE_TYPE_P5 &&
parms->device_type != TF_DEVICE_TYPE_SR) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
@@ -1845,7 +1847,7 @@ int tf_query_sram_resources(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1927,7 +1929,7 @@ int tf_set_sram_policy(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1968,7 +1970,7 @@ int tf_get_sram_policy(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1997,3 +1999,31 @@ int tf_get_sram_policy(struct tf *tfp,
return rc;
}
+
+int tf_set_session_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_set_hotup_state(tfp, parms);
+ if (rc)
+ return rc;
+
+ return rc;
+}
+
+int tf_get_session_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_hotup_state(tfp, parms);
+ if (rc)
+ return rc;
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index f5fe0a9098..3da1d2a5ca 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -112,6 +112,10 @@ enum tf_sram_bank_id {
* @ref tf_attach_session
*
* @ref tf_close_session
+ *
+ * @ref tf_get_session_info
+ *
+ * @ref tf_get_session_info
*/
/**
@@ -188,10 +192,10 @@ struct tf_session_version {
* Session supported device types
*/
enum tf_device_type {
- TF_DEVICE_TYPE_WH = 0, /**< Whitney+ */
- TF_DEVICE_TYPE_SR, /**< Stingray */
- TF_DEVICE_TYPE_THOR, /**< Thor */
- TF_DEVICE_TYPE_MAX /**< Maximum */
+ TF_DEVICE_TYPE_P4 = 0,
+ TF_DEVICE_TYPE_SR,
+ TF_DEVICE_TYPE_P5,
+ TF_DEVICE_TYPE_MAX
};
/**
@@ -286,6 +290,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_ENCAP_32B,
/** Wh+/SR/TH Action Encap 64 Bytes */
TF_TBL_TYPE_ACT_ENCAP_64B,
+ /* TH Action Encap 128 Bytes */
+ TF_TBL_TYPE_ACT_ENCAP_128B,
/** WH+/SR/TH Action Source Properties SMAC */
TF_TBL_TYPE_ACT_SP_SMAC,
/** Wh+/SR/TH Action Source Properties SMAC IPv4 */
@@ -331,7 +337,7 @@ enum tf_tbl_type {
* External table type - initially 1 poolsize entries.
* All External table types are associated with a table
* scope. Internal types are not. Currently this is
- * a pool of 64B entries.
+ * a pool of 128B entries.
*/
TF_TBL_TYPE_EXT,
TF_TBL_TYPE_MAX
@@ -914,6 +920,71 @@ int tf_attach_session(struct tf *tfp,
*/
int tf_close_session(struct tf *tfp);
+/**
+ * tf_set_session_hotup_state parameter definition.
+ */
+struct tf_set_session_hotup_state_parms {
+ /**
+ * [in] the structure is used to set the state of
+ * the hotup shared session.
+ *
+ */
+ uint16_t state;
+};
+
+/**
+ * set hot upgrade shared session state
+ *
+ * This API is used to set the state of the shared session.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to set hotup state parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_set_session_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms);
+
+/**
+ * tf_get_session_hotup_state parameter definition.
+ */
+struct tf_get_session_hotup_state_parms {
+ /**
+ * [out] the structure is used to get the state of
+ * the hotup shared session.
+ *
+ */
+ uint16_t state;
+ /**
+ * [out] get the ref_cnt of the hotup shared session.
+ *
+ */
+ uint16_t ref_cnt;
+};
+
+/**
+ * get hot upgrade shared session state
+ *
+ * This API is used to set the state of the shared session.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to get hotup state parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_get_session_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms);
+
/**
* @page ident Identity Management
*
@@ -1192,8 +1263,6 @@ int tf_free_tbl_scope(struct tf *tfp,
*
* @ref tf_get_tcam_entry
*
- * @ref tf_free_tcam_entry
- *
* @ref tf_move_tcam_shared_entries
*
* @ref tf_clear_tcam_shared_entries
@@ -1258,7 +1327,7 @@ struct tf_search_tcam_entry_parms {
};
/**
- * search TCAM entry (experimental)
+ * search TCAM entry
*
* Search for a TCAM entry
*
@@ -1732,7 +1801,7 @@ struct tf_get_shared_tbl_increment_parms {
* tf_get_shared_tbl_increment
*
* This API is currently only required for use in the shared
- * session for Thor (p58) actions. An increment count is returned per
+ * session for P5 actions. An increment count is returned per
* type to indicate how much to increment the start by for each
* entry (see tf_resource_info)
*
@@ -1898,6 +1967,7 @@ struct tf_insert_em_entry_parms {
*/
uint64_t flow_id;
};
+
/**
* tf_delete_em_entry parameter definition
*/
@@ -1927,6 +1997,7 @@ struct tf_delete_em_entry_parms {
*/
uint64_t flow_handle;
};
+
/**
* tf_move_em_entry parameter definition
*/
@@ -1969,6 +2040,7 @@ struct tf_move_em_entry_parms {
*/
uint64_t flow_handle;
};
+
/**
* tf_search_em_entry parameter definition (Future)
*/
@@ -2108,6 +2180,7 @@ int tf_search_em_entry(struct tf *tfp,
*
* @ref tf_get_global_cfg
*/
+
/**
* Tunnel Encapsulation Offsets
*/
@@ -2121,6 +2194,7 @@ enum tf_tunnel_encap_offsets {
TF_TUNNEL_ENCAP_GRE,
TF_TUNNEL_ENCAP_FULL_GENERIC
};
+
/**
* Global Configuration Table Types
*/
@@ -2193,9 +2267,8 @@ int tf_set_global_cfg(struct tf *tfp,
* @ref tf_set_if_tbl_entry
*
* @ref tf_get_if_tbl_entry
- *
- * @ref tf_restore_if_tbl_entry
*/
+
/**
* Enumeration of TruFlow interface table types.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 1c97218b5b..02a9ebd7b2 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -332,7 +332,7 @@ tf_dev_unbind_p4(struct tf *tfp)
}
/**
- * Device specific bind function, THOR
+ * Device specific bind function, P5
*
* [in] tfp
* Pointer to TF handle
@@ -504,7 +504,7 @@ tf_dev_bind_p58(struct tf *tfp,
}
/**
- * Device specific unbind function, THOR
+ * Device specific unbind function, P5
*
* [in] tfp
* Pointer to TF handle
@@ -602,14 +602,14 @@ tf_dev_bind(struct tf *tfp __rte_unused,
struct tf_dev_info *dev_handle)
{
switch (type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
dev_handle->type = type;
return tf_dev_bind_p4(tfp,
resources,
dev_handle,
wc_num_slices);
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
resources,
@@ -627,11 +627,11 @@ tf_dev_bind_ops(enum tf_device_type type,
struct tf_dev_info *dev_handle)
{
switch (type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
dev_handle->ops = &tf_dev_ops_p4_init;
break;
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
dev_handle->ops = &tf_dev_ops_p58_init;
break;
default:
@@ -648,10 +648,10 @@ tf_dev_unbind(struct tf *tfp,
struct tf_dev_info *dev_handle)
{
switch (dev_handle->type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
return tf_dev_unbind_p4(tfp);
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
return tf_dev_unbind_p58(tfp);
default:
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index 5a42180719..06c17a7212 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 72c6b1cde8..911ea92471 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -296,11 +296,15 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp,
return rc;
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICE_SIZE 12
-
+#define CFA_P4_WC_TCAM_SLICE_SIZE (12)
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = tfs->wc_num_slices_per_row;
- if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
+ if (key_sz <= 1 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+ else if (key_sz <= 2 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else if (key_sz <= 4 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW;
+ else
return -ENOTSUP;
} else { /* for other type of tcam */
*num_slices_per_row = 1;
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index f8b424ebc9..6916c50fdc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -16,6 +16,7 @@
#include "tfp.h"
#include "tf_msg_common.h"
#include "tf_tbl_sram.h"
+#include "tf_util.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -79,33 +80,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
[TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 8,
+ .slices = 16,
},
/* Policy - Encaps in bank 2 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_128B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
@@ -116,49 +123,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
/* Policy - SP in bank 0 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 2,
+ .slices = 4,
},
/* Policy - Stats in bank 3 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
@@ -192,33 +199,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
[TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 8,
+ .slices = 16,
},
/* Policy - Encaps in bank 2 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_128B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
@@ -229,49 +242,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
/* Policy - SP in bank 0 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 2,
+ .slices = 4,
},
/* Policy - Stats in bank 3 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 8,
+ .slices = 16,
},
};
@@ -406,10 +419,15 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp,
if (rc)
return rc;
-#define CFA_P58_WC_TCAM_SLICE_SIZE 24
+#define CFA_P58_WC_TCAM_SLICE_SIZE (24)
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = tfs->wc_num_slices_per_row;
- if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
+ if (key_sz <= 1 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+ else if (key_sz <= 2 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else if (key_sz <= 4 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW;
+ else
return -ENOTSUP;
} else { /* for other type of tcam */
*num_slices_per_row = 1;
@@ -452,6 +470,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
case TF_TBL_TYPE_ACT_SP_SMAC:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
@@ -461,7 +480,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_MODIFY_16B:
case TF_TBL_TYPE_ACT_MODIFY_32B:
case TF_TBL_TYPE_ACT_MODIFY_64B:
- parms->increment_cnt = 8;
+ parms->increment_cnt = 16;
break;
default:
parms->increment_cnt = 1;
@@ -493,6 +512,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
case TF_TBL_TYPE_ACT_SP_SMAC:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
@@ -527,7 +547,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
*
* [in/out] shift
* Pointer to the factor to be used as a multiplier to translate
- * between the RM units to the user address. SRAM manages 64B entries
+ * between the RM units to the user address. SRAM manages 128B entries
* Addresses must be shifted to an 8B address.
*
* Returns
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index b56b7cc188..c518150d1f 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1000,8 +1000,8 @@ tf_em_ext_common_unbind(struct tf *tfp)
strerror(-rc));
return rc;
}
- ext_db = (struct em_ext_db *)ext_ptr;
+ ext_db = (struct em_ext_db *)ext_ptr;
if (ext_db != NULL) {
entry = ext_db->tbl_scope_ll.head;
while (entry != NULL) {
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 8ea5d93672..46de63a9da 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -7,7 +7,6 @@
#include <rte_common.h>
#include <rte_errno.h>
#include <rte_log.h>
-
#include "tf_core.h"
#include "tf_util.h"
#include "tf_common.h"
@@ -63,7 +62,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return -1;
}
-
rptr_index = index;
rc = tf_msg_insert_em_internal_entry(tfp,
parms,
@@ -75,6 +73,7 @@ tf_em_insert_int_entry(struct tf *tfp,
dpool_free(pool, index);
return -1;
}
+
TF_SET_GFID(gfid,
((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) |
rptr_entry),
@@ -95,7 +94,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return 0;
}
-
/** Delete EM internal entry API
*
* returns:
@@ -253,7 +251,6 @@ tf_em_int_bind(struct tf *tfp,
return db_rc[TF_DIR_RX];
}
-
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++) {
iparms.rm_db = em_db->em_db[i];
@@ -335,11 +332,10 @@ tf_em_int_unbind(struct tf *tfp)
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
- if (rc) {
+ if (rc)
return 0;
- }
- em_db = (struct em_rm_db *)em_db_ptr;
+ em_db = (struct em_rm_db *)em_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
if (em_db->em_db[i] == NULL)
continue;
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index 1846675916..7d9d9595dd 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -89,6 +89,7 @@ tf_ident_unbind(struct tf *tfp)
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr);
if (rc)
return 0;
+
ident_db = (struct ident_rm_db *)ident_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.c b/drivers/net/bnxt/tf_core/tf_if_tbl.c
index e667d6fa6d..578d361417 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -21,12 +21,6 @@ struct tf_if_tbl_db {
struct tf_if_tbl_cfg *if_tbl_cfg_db[TF_DIR_MAX];
};
-/**
- * Init flag, set on bind and cleared on unbind
- * TODO: Store this data in session db
- */
-static uint8_t init;
-
/**
* Convert if_tbl_type to hwrm type.
*
@@ -80,8 +74,6 @@ tf_if_tbl_bind(struct tf *tfp,
if_tbl_db->if_tbl_cfg_db[TF_DIR_TX] = parms->cfg;
tf_session_set_if_tbl_db(tfp, (void *)if_tbl_db);
- init = 1;
-
TFP_DRV_LOG(INFO,
"Table Type - initialized\n");
@@ -92,14 +84,7 @@ int
tf_if_tbl_unbind(struct tf *tfp)
{
int rc;
- struct tf_if_tbl_db *if_tbl_db_ptr;
-
- /* Bail if nothing has been initialized */
- if (!init) {
- TFP_DRV_LOG(INFO,
- "No Table DBs created\n");
- return 0;
- }
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
TF_CHECK_PARMS1(tfp);
@@ -108,9 +93,15 @@ tf_if_tbl_unbind(struct tf *tfp)
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ /* Bail if nothing has been initialized */
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(INFO,
+ "No Table DBs created\n");
+ return 0;
+ }
tfp_free((void *)if_tbl_db_ptr);
- init = 0;
+ tf_session_set_if_tbl_db(tfp, NULL);
return 0;
}
@@ -120,24 +111,24 @@ tf_if_tbl_set(struct tf *tfp,
struct tf_if_tbl_set_parms *parms)
{
int rc;
- struct tf_if_tbl_db *if_tbl_db_ptr;
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
struct tf_if_tbl_get_hcapi_parms hparms;
TF_CHECK_PARMS3(tfp, parms, parms->data);
- if (!init) {
- TFP_DRV_LOG(ERR,
- "%s: No Table DBs created\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(ERR,
+ "%s: No Table DBs created\n",
+ tf_dir_2_str(parms->dir));
+ return -EINVAL;
+ }
+
/* Convert TF type to HCAPI type */
hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir];
hparms.db_index = parms->type;
@@ -163,24 +154,24 @@ tf_if_tbl_get(struct tf *tfp,
struct tf_if_tbl_get_parms *parms)
{
int rc = 0;
- struct tf_if_tbl_db *if_tbl_db_ptr;
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
struct tf_if_tbl_get_hcapi_parms hparms;
TF_CHECK_PARMS3(tfp, parms, parms->data);
- if (!init) {
- TFP_DRV_LOG(ERR,
- "%s: No Table DBs created\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(ERR,
+ "%s: No Table DBs created\n",
+ tf_dir_2_str(parms->dir));
+ return -EINVAL;
+ }
+
/* Convert TF type to HCAPI type */
hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir];
hparms.db_index = parms->type;
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index fbc96d374c..1c66c7e01a 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -47,7 +47,6 @@ static_assert(sizeof(struct hwrm_tf_global_cfg_set_input) ==
static_assert(sizeof(struct hwrm_tf_em_insert_input) ==
TF_MSG_SIZE_HWRM_TF_EM_INSERT,
"HWRM message size changed: hwrm_tf_em_insert_input");
-
#define TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET 128
static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) ==
TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET,
@@ -61,13 +60,18 @@ static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) ==
/**
* This is the length of shared session name "tf_share"
*/
-#define TF_SHARED_SESSION_NAME_LEN 8
+#define TF_SHARED_SESSION_NAME_LEN 9
/**
* This is the length of tcam shared session name "tf_shared-wc_tcam"
*/
#define TF_TCAM_SHARED_SESSION_NAME_LEN 17
+/**
+ * This is the length of tcam shared session name "tf_shared-poolx"
+ */
+#define TF_POOL_SHARED_SESSION_NAME_LEN 16
+
/**
* If data bigger than TF_PCI_BUF_SIZE_MAX then use DMA method
*/
@@ -135,18 +139,30 @@ tf_msg_session_open(struct bnxt *bp,
struct hwrm_tf_session_open_input req = { 0 };
struct hwrm_tf_session_open_output resp = { 0 };
struct tfp_send_msg_parms parms = { 0 };
- int name_len;
char *session_name;
char *tcam_session_name;
+ char *pool_session_name;
- /* Populate the request */
- name_len = strnlen(ctrl_chan_name, TF_SESSION_NAME_MAX);
- session_name = &ctrl_chan_name[name_len - strlen("tf_shared")];
- tcam_session_name = &ctrl_chan_name[name_len - strlen("tf_shared-wc_tcam")];
- if (!strncmp(tcam_session_name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam")))
- tfp_memcpy(&req.session_name, tcam_session_name, TF_TCAM_SHARED_SESSION_NAME_LEN);
- else if (!strncmp(session_name, "tf_shared", strlen("tf_shared")))
- tfp_memcpy(&req.session_name, session_name, TF_SHARED_SESSION_NAME_LEN);
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ * "tf_shared" is used by both verions.
+ */
+ tcam_session_name = strstr(ctrl_chan_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(ctrl_chan_name, "tf_shared-pool");
+ session_name = strstr(ctrl_chan_name, "tf_shared");
+ if (tcam_session_name)
+ tfp_memcpy(&req.session_name,
+ tcam_session_name,
+ TF_TCAM_SHARED_SESSION_NAME_LEN);
+ else if (pool_session_name)
+ tfp_memcpy(&req.session_name,
+ pool_session_name,
+ TF_POOL_SHARED_SESSION_NAME_LEN);
+ else if (session_name)
+ tfp_memcpy(&req.session_name,
+ session_name,
+ TF_SHARED_SESSION_NAME_LEN);
else
tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX);
@@ -191,9 +207,9 @@ tf_msg_session_client_register(struct tf *tfp,
struct tfp_send_msg_parms parms = { 0 };
uint8_t fw_session_id;
struct tf_dev_info *dev;
- int name_len;
char *session_name;
char *tcam_session_name;
+ char *pool_session_name;
/* Retrieve the device information */
rc = tf_session_get_device(tfs, &dev);
@@ -214,24 +230,31 @@ tf_msg_session_client_register(struct tf *tfp,
/* Populate the request */
req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
- name_len = strnlen(ctrl_channel_name, TF_SESSION_NAME_MAX);
- session_name = &ctrl_channel_name[name_len - strlen("tf_shared")];
- tcam_session_name = &ctrl_channel_name[name_len -
- strlen("tf_shared-wc_tcam")];
- if (!strncmp(tcam_session_name,
- "tf_shared-wc_tcam",
- strlen("tf_shared-wc_tcam")))
+
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ * "tf_shared" is used by both verions.
+ */
+ tcam_session_name = strstr(ctrl_channel_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(ctrl_channel_name, "tf_shared-pool");
+ session_name = strstr(ctrl_channel_name, "tf_shared");
+ if (tcam_session_name)
+ tfp_memcpy(&req.session_client_name,
+ tcam_session_name,
+ TF_TCAM_SHARED_SESSION_NAME_LEN);
+ else if (pool_session_name)
tfp_memcpy(&req.session_client_name,
- tcam_session_name,
- TF_TCAM_SHARED_SESSION_NAME_LEN);
- else if (!strncmp(session_name, "tf_shared", strlen("tf_shared")))
+ pool_session_name,
+ TF_POOL_SHARED_SESSION_NAME_LEN);
+ else if (session_name)
tfp_memcpy(&req.session_client_name,
- session_name,
- TF_SHARED_SESSION_NAME_LEN);
+ session_name,
+ TF_SHARED_SESSION_NAME_LEN);
else
tfp_memcpy(&req.session_client_name,
- ctrl_channel_name,
- TF_SESSION_NAME_MAX);
+ ctrl_channel_name,
+ TF_SESSION_NAME_MAX);
parms.tf_type = HWRM_TF_SESSION_REGISTER;
parms.req_data = (uint32_t *)&req;
@@ -431,7 +454,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp,
/* Post process the response */
data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr;
-
for (i = 0; i < resp.size; i++) {
query[i].type = tfp_le_to_cpu_32(data[i].type);
query[i].min = tfp_le_to_cpu_16(data[i].min);
@@ -1757,6 +1779,7 @@ tf_msg_set_tbl_entry(struct tf *tfp,
struct hwrm_tf_tbl_type_set_input req = { 0 };
struct hwrm_tf_tbl_type_set_output resp = { 0 };
struct tfp_send_msg_parms parms = { 0 };
+ struct tf_msg_dma_buf buf = { 0 };
uint8_t fw_session_id;
struct tf_dev_info *dev;
struct tf_session *tfs;
@@ -1802,18 +1825,19 @@ tf_msg_set_tbl_entry(struct tf *tfp,
/* Check for data size conformity */
if (size > TF_MSG_TBL_TYPE_SET_DATA_SIZE) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s: Invalid parameters for msg type, rc:%s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
+ /* use dma buffer */
+ req.flags |= HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA;
+ rc = tf_msg_alloc_dma_buf(&buf, size);
+ if (rc)
+ goto cleanup;
+ tfp_memcpy(buf.va_addr, data, size);
+ tfp_memcpy(&req.data[0],
+ &buf.pa_addr,
+ sizeof(buf.pa_addr));
+ } else {
+ tfp_memcpy(&req.data, data, size);
}
- tfp_memcpy(&req.data,
- data,
- size);
-
parms.tf_type = HWRM_TF_TBL_TYPE_SET;
parms.req_data = (uint32_t *)&req;
parms.req_size = sizeof(req);
@@ -1823,10 +1847,10 @@ tf_msg_set_tbl_entry(struct tf *tfp,
rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
&parms);
- if (rc)
- return rc;
+cleanup:
+ tf_msg_free_dma_buf(&buf);
- return 0;
+ return rc;
}
int
@@ -2325,3 +2349,114 @@ tf_msg_get_version(struct bnxt *bp,
return rc;
}
+
+int
+tf_msg_session_set_hotup_state(struct tf *tfp, uint16_t state)
+{
+ int rc;
+ struct hwrm_tf_session_hotup_state_set_input req = { 0 };
+ struct hwrm_tf_session_hotup_state_set_output resp = { 0 };
+ struct tfp_send_msg_parms parms = { 0 };
+ uint8_t fw_session_id;
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup device, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_session_get_fw_session_id(tfp, &fw_session_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Unable to lookup FW id, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Populate the request */
+ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
+ req.state = tfp_cpu_to_le_16(state);
+
+ parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_SET;
+ parms.req_data = (uint32_t *)&req;
+ parms.req_size = sizeof(req);
+ parms.resp_data = (uint32_t *)&resp;
+ parms.resp_size = sizeof(resp);
+ parms.mailbox = dev->ops->tf_dev_get_mailbox();
+
+ rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
+ &parms);
+ return rc;
+}
+
+int
+tf_msg_session_get_hotup_state(struct tf *tfp,
+ uint16_t *state,
+ uint16_t *ref_cnt)
+{
+ int rc;
+ struct hwrm_tf_session_hotup_state_get_input req = { 0 };
+ struct hwrm_tf_session_hotup_state_get_output resp = { 0 };
+ struct tfp_send_msg_parms parms = { 0 };
+ uint8_t fw_session_id;
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup device, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_session_get_fw_session_id(tfp, &fw_session_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Unable to lookup FW id, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Populate the request */
+ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
+
+ parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_GET;
+ parms.req_data = (uint32_t *)&req;
+ parms.req_size = sizeof(req);
+ parms.resp_data = (uint32_t *)&resp;
+ parms.resp_size = sizeof(resp);
+ parms.mailbox = dev->ops->tf_dev_get_mailbox();
+
+ rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
+ &parms);
+
+ *state = tfp_le_to_cpu_16(resp.state);
+ *ref_cnt = tfp_le_to_cpu_16(resp.ref_cnt);
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h
index 188b361d71..24d0ae5f43 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.h
+++ b/drivers/net/bnxt/tf_core/tf_msg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -761,4 +761,40 @@ int
tf_msg_get_version(struct bnxt *bp,
struct tf_dev_info *dev,
struct tf_get_version_parms *parms);
+
+/**
+ * Send set hot upgrade state request to the firmware.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [in] state
+ * Hot upgrade session state
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_msg_session_set_hotup_state(struct tf *tfp,
+ uint16_t state);
+
+/**
+ * Send get hot upgrade state request to the firmware.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [out] state
+ * Pointer to hot upgrade session state
+ *
+ * [out] ref_cnt
+ * Pointer to hot upgrade session reference count
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_msg_session_get_hotup_state(struct tf *tfp,
+ uint16_t *state,
+ uint16_t *ref_cnt);
#endif /* _TF_MSG_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index d2045921b9..1fccb698d0 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -1,15 +1,12 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include <rte_common.h>
#include <rte_debug.h>
-
#include <cfa_resource_types.h>
-
#include "tf_rm.h"
#include "tf_common.h"
#include "tf_util.h"
@@ -18,9 +15,6 @@
#include "tfp.h"
#include "tf_msg.h"
-/* Logging defines */
-#define TF_RM_DEBUG 0
-
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -210,45 +204,6 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
-/**
- * Logs an array of found residual entries to the console.
- *
- * [in] dir
- * Receive or transmit direction
- *
- * [in] module
- * Type of Device Module
- *
- * [in] count
- * Number of entries in the residual array
- *
- * [in] residuals
- * Pointer to an array of residual entries. Array is index same as
- * the DB in which this function is used. Each entry holds residual
- * value for that entry.
- */
-#if (TF_RM_DEBUG == 1)
-static void
-tf_rm_log_residuals(enum tf_dir dir,
- enum tf_module_type module,
- uint16_t count,
- uint16_t *residuals)
-{
- int i;
-
- /* Walk the residual array and log the types that wasn't
- * cleaned up to the console.
- */
- for (i = 0; i < count; i++) {
- if (residuals[i] != 0)
- TFP_DRV_LOG(INFO,
- "%s, %s was not cleaned up, %d outstanding\n",
- tf_dir_2_str(dir),
- tf_module_subtype_2_str(module, i),
- residuals[i]);
- }
-}
-#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -364,12 +319,6 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
-#if (TF_RM_DEBUG == 1)
- tf_rm_log_residuals(rm_db->dir,
- rm_db->module,
- rm_db->num_entries,
- residuals);
-#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -419,7 +368,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
bool shared_session)
{
int parent, child;
- const char *type_str;
+ const char *type_str = NULL;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -444,11 +393,6 @@ tf_rm_update_parent_reservations(struct tf *tfp,
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
-#if (TF_RM_DEBUG == 1)
- printf("%s:%s cnt(%d) slices(%d)\n",
- type_str, tf_tbl_type_2_str(parent),
- alloc_cnt[parent], p_slices);
-#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -469,13 +413,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
-#if (TF_RM_DEBUG == 1)
- printf("%s:%s cnt(%d) slices(%d)\n",
- type_str,
- tf_tbl_type_2_str(child),
- alloc_cnt[child],
- c_slices);
-#endif /* (TF_RM_DEBUG == 1) */
+
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM alloc item.
@@ -492,10 +430,6 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
-#if (TF_RM_DEBUG == 1)
- printf("%s calculated total:%d\n\n",
- type_str, req_cnt[parent]);
-#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -595,12 +529,6 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
-#if (TF_RM_DEBUG == 1)
- TFP_DRV_LOG(INFO,
- "%s: module: %s Empty RM DB create request\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -746,7 +674,7 @@ tf_rm_create_db(struct tf *tfp,
rc = ba_init(db[i].pool,
resv[j].stride,
- !tf_session_is_shared_session(tfs));
+ true);
if (rc) {
TFP_DRV_LOG(ERR,
"%s: Pool init failed, type:%d:%s\n",
@@ -773,13 +701,6 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
-#if (TF_RM_DEBUG == 1)
-
- printf("%s: module:%s\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif /* (TF_RM_DEBUG == 1) */
-
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -812,6 +733,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -841,6 +763,16 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
+ /* Update the req_cnt based upon the element configuration
+ */
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
+ parms->alloc_cnt,
+ parms->num_elements,
+ req_cnt,
+ shared_session);
+
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
* req msg content by removing those out of the request yet
@@ -855,11 +787,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
- TFP_DRV_LOG(ERR,
- "%s: module:%s Empty RM DB create request\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -938,6 +865,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -986,7 +914,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rc = ba_init(db[i].pool,
resv[j].stride,
- !tf_session_is_shared_session(tfs));
+ true);
if (rc) {
TFP_DRV_LOG(ERR,
"%s: Pool init failed, type:%d:%s\n",
@@ -1013,13 +941,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
-#if (TF_RM_DEBUG == 1)
-
- printf("%s: module:%s\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif /* (TF_RM_DEBUG == 1) */
-
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1036,6 +957,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
return -EINVAL;
}
+
int
tf_rm_free_db(struct tf *tfp,
struct tf_rm_free_db_parms *parms)
@@ -1110,6 +1032,7 @@ tf_rm_free_db(struct tf *tfp,
return rc;
}
+
/**
* Get the bit allocator pool associated with the subtype and the db
*
@@ -1388,6 +1311,7 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+
int
tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
{
@@ -1440,6 +1364,7 @@ tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
return rc;
}
+
/* Only used for table bulk get at this time
*/
int
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index d0a0916c6a..253d716572 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -1,12 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include <rte_common.h>
-
#include "tf_session.h"
#include "tf_common.h"
#include "tf_msg.h"
@@ -59,8 +57,9 @@ tf_session_create(struct tf *tfp,
union tf_session_id *session_id;
struct tf_dev_info dev;
bool shared_session_creator;
- int name_len;
- char *name;
+ char *shared_name;
+ char *tcam_session_name;
+ char *pool_session_name;
TF_CHECK_PARMS2(tfp, parms);
@@ -180,16 +179,18 @@ tf_session_create(struct tf *tfp,
session->em_ext_db_handle = NULL;
/* Populate the request */
- name_len = strnlen(parms->open_cfg->ctrl_chan_name,
- TF_SESSION_NAME_MAX);
- name = &parms->open_cfg->ctrl_chan_name[name_len - strlen("tf_shared")];
- if (!strncmp(name, "tf_shared", strlen("tf_shared")))
- session->shared_session = true;
-
- name = &parms->open_cfg->ctrl_chan_name[name_len -
- strlen("tf_shared-wc_tcam")];
- if (!strncmp(name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam")))
+ shared_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared");
+ if (shared_name) {
session->shared_session = true;
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ */
+ tcam_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-pool");
+ if (tcam_session_name || pool_session_name)
+ session->shared_session_hotup = true;
+ }
if (session->shared_session && shared_session_creator) {
session->shared_session_creator = true;
@@ -342,7 +343,6 @@ tf_session_client_create(struct tf *tfp,
return rc;
}
-
/**
* Destroys a Session Client on an existing Session.
*
@@ -441,7 +441,7 @@ tf_session_open_session(struct tf *tfp,
TFP_DRV_LOG(INFO,
"Session created, session_client_id:%d,"
- "session_id:0x%08x, fw_session_id:%d\n",
+ " session_id:0x%08x, fw_session_id:%d\n",
parms->open_cfg->session_client_id.id,
parms->open_cfg->session_id.id,
parms->open_cfg->session_id.internal.fw_session_id);
@@ -462,7 +462,7 @@ tf_session_open_session(struct tf *tfp,
}
TFP_DRV_LOG(INFO,
- "Session Client:%d registered on session:0x%8x\n",
+ "Session Client:%d registered on session:0x%08x\n",
scparms.session_client_id->internal.fw_session_client_id,
tfp->session->session_id.id);
}
@@ -535,6 +535,11 @@ tf_session_close_session(struct tf *tfp,
return rc;
}
+ /* Record the session we're closing so the caller knows the
+ * details.
+ */
+ *parms->session_id = tfs->session_id;
+
/* In case multiple clients we chose to close those first */
if (tfs->ref_count > 1) {
/* Linaro gcc can't static init this structure */
@@ -567,11 +572,6 @@ tf_session_close_session(struct tf *tfp,
return 0;
}
- /* Record the session we're closing so the caller knows the
- * details.
- */
- *parms->session_id = tfs->session_id;
-
rc = tf_session_get_device(tfs, &tfd);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1140,3 +1140,71 @@ tf_session_set_if_tbl_db(struct tf *tfp,
tfs->if_tbl_db_handle = if_tbl_handle;
return rc;
}
+
+int
+tf_session_set_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+ struct tf_session *tfs = NULL;
+
+ rc = tf_session_get_session(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Session lookup failed, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ if (!tf_session_is_shared_session(tfs)) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR,
+ "Only shared session able to set state, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_session_set_hotup_state(tfp, parms->state);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Set session hot upgrade state failed, rc:%s\n",
+ strerror(-rc));
+ }
+
+ return rc;
+}
+
+int
+tf_session_get_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+ struct tf_session *tfs = NULL;
+
+ rc = tf_session_get_session(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Session lookup failed, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ if (!tf_session_is_shared_session(tfs)) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR,
+ "Only shared session able to get state, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_session_get_hotup_state(tfp, &parms->state, &parms->ref_cnt);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Get session hot upgrade state failed, rc:%s\n",
+ strerror(-rc));
+ }
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index 5a94b941fa..9bbbccf125 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -8,7 +8,6 @@
#include <stdint.h>
#include <stdlib.h>
-
#include "bitalloc.h"
#include "tf_core.h"
#include "tf_device.h"
@@ -48,7 +47,7 @@
*
* Shared memory containing private TruFlow session information.
* Through this structure the session can keep track of resource
- * allocations. It also holds info about Session Clients.
+ * allocations. It also holds info about Session Clients.
*
* Memory is assigned to the Truflow instance by way of
* tf_open_session. Memory is allocated and owned by i.e. ULP.
@@ -78,6 +77,11 @@ struct tf_session {
*/
bool shared_session;
+ /**
+ * Boolean controlling the split of hardware resources for hotupgrade.
+ */
+ bool shared_session_hotup;
+
/**
* This flag indicates the shared session on firmware side is created
* by this session. Some privileges may be assigned to this session.
@@ -169,6 +173,12 @@ struct tf_session {
* Number of slices per row for WC TCAM
*/
uint16_t wc_num_slices_per_row;
+
+ /**
+ * Indicates if TCAM is controlled by TCAM Manager
+ */
+ int tcam_mgr_control[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX];
+
};
/**
@@ -276,11 +286,9 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_is_shared_session
*
- * #define TF_SHARED
* @ref tf_session_get_tcam_shared_db
*
* @ref tf_session_set_tcam_shared_db
- * #endif
*
* @ref tf_session_get_sram_db
*
@@ -588,6 +596,21 @@ tf_session_is_shared_session(struct tf_session *tfs)
return tfs->shared_session;
}
+/**
+ * Check if the session is shared session for hot upgrade.
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - true if it is shared session for hot upgrade
+ * - false if it is not shared session for hot upgrade
+ */
+static inline bool
+tf_session_is_shared_hotup_session(struct tf_session *tfs)
+{
+ return tfs->shared_session_hotup;
+}
+
/**
* Check if the session is the shared session creator
*
@@ -716,4 +739,36 @@ tf_session_set_if_tbl_db(struct tf *tfp,
int
tf_session_get_if_tbl_db(struct tf *tfp,
void **if_tbl_handle);
+
+/**
+ * Set hot upgrade session state.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [in] parms
+ * Hot upgrade session state parms
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_session_set_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms);
+
+/**
+ * Get hot upgrade session state.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [out] parms
+ * Pointer to hot upgrade session state parms
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_session_get_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms);
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
index acb3372486..87e8882fed 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.c
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <stdlib.h>
@@ -21,7 +21,7 @@
/**
* TF SRAM block info
*
- * Contains all the information about a particular 64B SRAM
+ * Contains all the information about a particular 128B SRAM
* block and the slices within it.
*/
struct tf_sram_block {
@@ -36,9 +36,9 @@ struct tf_sram_block {
* If a bit is set, it indicates the slice
* in the row is in use.
*/
- uint8_t in_use_mask;
+ uint16_t in_use_mask;
- /** Block id - this is a 64B offset
+ /** Block id - this is a 128B offset
*/
uint16_t block_id;
};
@@ -46,7 +46,7 @@ struct tf_sram_block {
/**
* TF SRAM block list
*
- * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ * List of 128B SRAM blocks used for fixed size slices (8, 16, 32, 64B, 128B)
*/
struct tf_sram_slice_list {
/** Pointer to head of linked list of blocks.
@@ -70,7 +70,6 @@ struct tf_sram_slice_list {
enum tf_sram_slice_size size;
};
-
/**
* TF SRAM bank info consists of lists of different slice sizes per bank
*/
@@ -111,6 +110,8 @@ const char
return "32B slice";
case TF_SRAM_SLICE_SIZE_64B:
return "64B slice";
+ case TF_SRAM_SLICE_SIZE_128B:
+ return "128B slice";
default:
return "Invalid slice size";
}
@@ -179,8 +180,8 @@ static void
tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
uint16_t *block_id, uint16_t *slice_offset)
{
- *slice_offset = offset & 0x7;
- *block_id = ((offset & ~0x7) >> 3) -
+ *slice_offset = offset & 0xf;
+ *block_id = ((offset & ~0xf) >> 3) -
tf_sram_bank_2_base_offset[bank_id];
}
@@ -232,31 +233,37 @@ tf_sram_free_slice(enum tf_sram_slice_size slice_size,
bool *block_is_empty)
{
int rc = 0;
- uint8_t shift;
- uint8_t slice_mask = 0;
+ uint16_t shift;
+ uint16_t slice_mask = 0;
TF_CHECK_PARMS2(block, block_is_empty);
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = slice_offset >> 0;
- assert(shift < 8);
+ assert(shift < 16);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = slice_offset >> 1;
- assert(shift < 4);
+ assert(shift < 8);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = slice_offset >> 2;
- assert(shift < 2);
+ assert(shift < 4);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ shift = slice_offset >> 3;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = slice_offset >> 0;
assert(shift < 1);
@@ -294,27 +301,32 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
bool *block_is_full)
{
int rc, free_id = -1;
- uint8_t shift, max_slices, mask, i, full_mask;
+ uint16_t shift, max_slices, mask, i, full_mask;
TF_CHECK_PARMS3(block, slice_offset, block_is_full);
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = 0;
- max_slices = 8;
- full_mask = 0xff;
+ max_slices = 16;
+ full_mask = 0xffff;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = 1;
- max_slices = 4;
- full_mask = 0xf;
+ max_slices = 8;
+ full_mask = 0xff;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = 2;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ shift = 3;
max_slices = 2;
full_mask = 0x3;
break;
- case TF_SRAM_SLICE_SIZE_64B:
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = 0;
max_slices = 1;
@@ -338,7 +350,6 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
else
*block_is_full = false;
-
if (free_id >= 0) {
*slice_offset = free_id << shift;
rc = 0;
@@ -362,8 +373,8 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
bool *is_allocated)
{
int rc = 0;
- uint8_t shift;
- uint8_t slice_mask = 0;
+ uint16_t shift;
+ uint16_t slice_mask = 0;
TF_CHECK_PARMS2(block, is_allocated);
@@ -372,23 +383,29 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = slice_offset >> 0;
- assert(shift < 8);
+ assert(shift < 16);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = slice_offset >> 1;
- assert(shift < 4);
+ assert(shift < 8);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = slice_offset >> 2;
- assert(shift < 2);
+ assert(shift < 4);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ shift = slice_offset >> 3;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = slice_offset >> 0;
assert(shift < 1);
@@ -416,7 +433,6 @@ tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
return slice_list->cnt;
}
-
/**
* Free a block data structure - does not free to the RM
*/
@@ -508,22 +524,26 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
struct tf_sram_block **first_not_full_block)
{
struct tf_sram_block *block = slice_list->head;
- uint8_t slice_mask, mask;
+ uint16_t slice_mask, mask;
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
- slice_mask = 0xff;
+ slice_mask = 0xffff;
break;
case TF_SRAM_SLICE_SIZE_16B:
- slice_mask = 0xf;
+ slice_mask = 0xff;
break;
case TF_SRAM_SLICE_SIZE_32B:
- slice_mask = 0x3;
+ slice_mask = 0xf;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
slice_mask = 0x1;
break;
@@ -543,7 +563,7 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
static void
tf_sram_dump_block(struct tf_sram_block *block)
{
- TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%04x)\n",
block->block_id,
block->in_use_mask);
}
@@ -631,9 +651,10 @@ int tf_sram_mgr_alloc(void *sram_handle,
struct tf_sram *sram;
struct tf_sram_slice_list *slice_list;
uint16_t block_id, slice_offset = 0;
- uint32_t index;
+ uint32_t index, next_index;
struct tf_sram_block *block;
struct tf_rm_allocate_parms aparms = { 0 };
+ struct tf_rm_free_parms fparms = { 0 };
bool block_is_full;
uint16_t block_offset;
@@ -662,11 +683,34 @@ int tf_sram_mgr_alloc(void *sram_handle,
aparms.subtype = parms->tbl_type;
aparms.rm_db = parms->rm_db;
rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+ /* to support 128B block rows, we are allocating
+ * 2 sequential 64B blocks from RM, if they are not next to
+ * each other we are going to have issues
+ */
+ aparms.index = &next_index;
+ rc = tf_rm_allocate(&aparms);
if (rc)
return rc;
+ /* make sure we do get the next 64B block, else free the
+ * allocated indexes and return error
+ */
+ if (unlikely(index + 1 != next_index)) {
+ fparms.index = index;
+ fparms.subtype = parms->tbl_type;
+ fparms.rm_db = parms->rm_db;
+ tf_rm_free(&fparms);
+ fparms.index = next_index;
+ tf_rm_free(&fparms);
+ TFP_DRV_LOG(ERR,
+ "Could not allocate two sequential 64B blocks\n");
+ return -ENOMEM;
+ }
block_id = index;
block = tf_sram_alloc_block(slice_list, block_id);
+
} else {
/* Block exists
*/
@@ -742,7 +786,7 @@ tf_sram_mgr_free(void *sram_handle,
}
#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
/* If this is a counter, clear it. In the future we need to switch to
- * using the special access registers on Thor to automatically clear on
+ * using the special access registers on P5 to automatically clear on
* read.
*/
/* If this is counter table, clear the entry on free */
@@ -794,6 +838,13 @@ tf_sram_mgr_free(void *sram_handle,
TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
block_id, strerror(-rc));
}
+ fparms.index = block_id + 1;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free next block_id(%d) failed error(%s)\n",
+ block_id + 1, strerror(-rc));
+ }
/* Free local entry regardless */
tf_sram_free_block(slice_list, block);
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
index fc78426130..878195c404 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -26,28 +26,28 @@
*/
#define STATS_CLEAR_ON_READ_SUPPORT 0
-#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 128
#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
/**
* TF slice size.
*
- * A slice is part of a 64B row
+ * A slice is part of a 128B row
*
* Each slice is a multiple of 8B
*/
enum tf_sram_slice_size {
- TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_128B, /**< 128 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
};
-
/** Initialize the SRAM slice manager
*
- * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * The SRAM slice manager manages slices within 128B rows. Slices are of size
* tf_sram_slice_size. This function provides a handle to the SRAM manager
* data.
*
@@ -181,7 +181,7 @@ struct tf_sram_mgr_free_parms {
/**
* Free an SRAM Slice
*
- * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * Free an SRAM slice to the indicated bank. This may result in a 128B row
* being returned to the RM SRAM bank pool.
*
* [in] sram_handle
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index f18e4ba346..f5f3889934 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -1,12 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
/* Truflow Table APIs and supporting code */
#include <rte_common.h>
-
#include "tf_tbl.h"
#include "tf_common.h"
#include "tf_rm.h"
@@ -18,8 +17,8 @@
struct tf;
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
}
int
@@ -98,6 +97,7 @@ tf_tbl_unbind(struct tf *tfp)
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc)
return 0;
+
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 567f912dfa..3a6f1c68c7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -73,11 +73,12 @@ const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
* Translate HCAPI type to SRAM Manager bank
*/
const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
- [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
- [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
- [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
- [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
- [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+ [0] = TF_SRAM_SLICE_SIZE_128B, /* if 0 slices assume 1 128B block */
+ [1] = TF_SRAM_SLICE_SIZE_128B, /* 1 slice per 128B block */
+ [2] = TF_SRAM_SLICE_SIZE_64B, /* 2 slice per 128B block */
+ [4] = TF_SRAM_SLICE_SIZE_32B, /* 4 slices per 128B block */
+ [8] = TF_SRAM_SLICE_SIZE_16B, /* 8 slices per 128B block */
+ [16] = TF_SRAM_SLICE_SIZE_8B /* 16 slices per 128B block */
};
/**
@@ -340,7 +341,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ "%s: Free of invalid entry:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -361,7 +362,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
rc = tf_sram_mgr_free(sram_handle, &fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed to free entry:%s idx(%d)\n",
+ "%s: Failed to free entry:%s idx(0x%x)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx);
@@ -469,7 +470,7 @@ tf_tbl_sram_set(struct tf *tfp,
if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:0x%x\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx);
@@ -484,7 +485,7 @@ tf_tbl_sram_set(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -587,7 +588,7 @@ tf_tbl_sram_get(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -711,7 +712,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s last_idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
idx,
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 1c42a6adc7..9e0671d47b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -14,6 +14,7 @@
#include "tfp.h"
#include "tf_session.h"
#include "tf_msg.h"
+#include "tf_tcam_mgr_msg.h"
struct tf;
@@ -23,17 +24,22 @@ tf_tcam_bind(struct tf *tfp,
{
int rc;
int db_rc[TF_DIR_MAX] = { 0 };
- int i, d;
+ int d, t;
struct tf_rm_alloc_info info;
struct tf_rm_free_db_parms fparms;
struct tf_rm_create_db_parms db_cfg;
+ struct tf_tcam_resources local_tcam_cnt[TF_DIR_MAX];
struct tf_tcam_resources *tcam_cnt;
struct tf_rm_get_alloc_info_parms ainfo;
- uint16_t num_slices = parms->wc_num_slices;
+ uint16_t num_slices = 1;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
struct tfp_calloc_parms cparms;
+ struct tf_resource_info resv_res[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX];
+ uint32_t rx_supported;
+ uint32_t tx_supported;
+ bool no_req = true;
TF_CHECK_PARMS2(tfp, parms);
@@ -47,7 +53,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -55,18 +61,28 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
- num_slices);
+ tcam_cnt = parms->resources->tcam_cnt;
+
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0,
+ &num_slices);
if (rc)
return rc;
- tcam_cnt = parms->resources->tcam_cnt;
- if ((tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices) ||
- (tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices)) {
- TFP_DRV_LOG(ERR,
- "Requested num of WC TCAM entries has to be multiple %d\n",
- num_slices);
- return -EINVAL;
+ if (num_slices == 1)
+ continue;
+
+ if (tcam_cnt[d].cnt[t] % num_slices) {
+ TFP_DRV_LOG(ERR,
+ "%s: Requested num of %s entries "
+ "has to be multiple of %d\n",
+ tf_dir_2_str(d),
+ tf_tcam_tbl_2_str(t),
+ num_slices);
+ return -EINVAL;
+ }
+ }
}
memset(&db_cfg, 0, sizeof(db_cfg));
@@ -80,8 +96,8 @@ tf_tcam_bind(struct tf *tfp,
}
tcam_db = cparms.mem_va;
- for (i = 0; i < TF_DIR_MAX; i++)
- tcam_db->tcam_db[i] = NULL;
+ for (d = 0; d < TF_DIR_MAX; d++)
+ tcam_db->tcam_db[d] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, tcam_db);
db_cfg.module = TF_MODULE_TYPE_TCAM;
@@ -90,7 +106,7 @@ tf_tcam_bind(struct tf *tfp,
for (d = 0; d < TF_DIR_MAX; d++) {
db_cfg.dir = d;
- db_cfg.alloc_cnt = parms->resources->tcam_cnt[d].cnt;
+ db_cfg.alloc_cnt = tcam_cnt[d].cnt;
db_cfg.rm_db = (void *)&tcam_db->tcam_db[d];
if (tf_session_is_shared_session(tfs) &&
(!tf_session_is_shared_session_creator(tfs)))
@@ -98,53 +114,112 @@ tf_tcam_bind(struct tf *tfp,
else
db_rc[d] = tf_rm_create_db(tfp, &db_cfg);
}
-
/* No db created */
if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) {
TFP_DRV_LOG(ERR, "No TCAM DB created\n");
return db_rc[TF_DIR_RX];
}
- /* check if reserved resource for WC is multiple of num_slices */
+ /* Collect info on which entries were reserved. */
for (d = 0; d < TF_DIR_MAX; d++) {
- if (!tcam_db->tcam_db[d])
- continue;
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ memset(&info, 0, sizeof(info));
+ if (tcam_cnt[d].cnt[t] == 0) {
+ resv_res[d][t].start = 0;
+ resv_res[d][t].stride = 0;
+ continue;
+ }
+ ainfo.rm_db = tcam_db->tcam_db[d];
+ ainfo.subtype = t;
+ ainfo.info = &info;
+ rc = tf_rm_get_info(&ainfo);
+ if (rc)
+ goto error;
+
+ rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ /* check if reserved resource for is multiple of
+ * num_slices
+ */
+ if (info.entry.start % num_slices != 0 ||
+ info.entry.stride % num_slices != 0) {
+ TFP_DRV_LOG(ERR,
+ "%s: %s reserved resource"
+ " is not multiple of %d\n",
+ tf_dir_2_str(d),
+ tf_tcam_tbl_2_str(t),
+ num_slices);
+ rc = -EINVAL;
+ goto error;
+ }
+ }
+
+ resv_res[d][t].start = info.entry.start;
+ resv_res[d][t].stride = info.entry.stride;
+ }
+ }
- memset(&info, 0, sizeof(info));
- ainfo.rm_db = tcam_db->tcam_db[d];
- ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- ainfo.info = &info;
- rc = tf_rm_get_info(&ainfo);
- if (rc)
- goto error;
-
- if (info.entry.start % num_slices != 0 ||
- info.entry.stride % num_slices != 0) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM reserved resource is not multiple of %d\n",
- tf_dir_2_str(d),
- num_slices);
- rc = -EINVAL;
- goto error;
+ rc = tf_tcam_mgr_bind_msg(tfp, dev, parms, resv_res);
+ if (rc)
+ return rc;
+
+ rc = tf_tcam_mgr_qcaps_msg(tfp, dev,
+ &rx_supported, &tx_supported);
+ if (rc)
+ return rc;
+
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ if (rx_supported & 1 << t)
+ tfs->tcam_mgr_control[TF_DIR_RX][t] = 1;
+ if (tx_supported & 1 << t)
+ tfs->tcam_mgr_control[TF_DIR_TX][t] = 1;
+ }
+
+ /*
+ * Make a local copy of tcam_cnt with only resources not managed by TCAM
+ * Manager requested.
+ */
+ memcpy(&local_tcam_cnt, tcam_cnt, sizeof(local_tcam_cnt));
+ tcam_cnt = local_tcam_cnt;
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ /* If controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[d][t])
+ tcam_cnt[d].cnt[t] = 0;
+ else if (tcam_cnt[d].cnt[t] > 0)
+ no_req = false;
}
}
- /* Initialize the TCAM manager. */
+ /* If no resources left to request */
+ if (no_req)
+ goto finished;
+
+finished:
TFP_DRV_LOG(INFO,
"TCAM - initialized\n");
return 0;
error:
- for (i = 0; i < TF_DIR_MAX; i++) {
- memset(&fparms, 0, sizeof(fparms));
- fparms.dir = i;
- fparms.rm_db = tcam_db->tcam_db[i];
- /* Ignoring return here since we are in the error case */
- (void)tf_rm_free_db(tfp, &fparms);
- tcam_db->tcam_db[i] = NULL;
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ if (tcam_db->tcam_db[d] != NULL) {
+ memset(&fparms, 0, sizeof(fparms));
+ fparms.dir = d;
+ fparms.rm_db = tcam_db->tcam_db[d];
+ /*
+ * Ignoring return here since we are in the error case
+ */
+ (void)tf_rm_free_db(tfp, &fparms);
+
+ tcam_db->tcam_db[d] = NULL;
+ }
+ tcam_db->tcam_db[d] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL);
}
-
return rc;
}
@@ -156,27 +231,43 @@ tf_tcam_unbind(struct tf *tfp)
struct tf_rm_free_db_parms fparms;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
TF_CHECK_PARMS1(tfp);
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc) {
+ if (rc)
return 0;
- }
+
tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
- if (tcam_db->tcam_db[i] == NULL)
- continue;
- memset(&fparms, 0, sizeof(fparms));
- fparms.dir = i;
- fparms.rm_db = tcam_db->tcam_db[i];
- rc = tf_rm_free_db(tfp, &fparms);
- if (rc)
- return rc;
+ if (tcam_db->tcam_db[i] != NULL) {
+ memset(&fparms, 0, sizeof(fparms));
+ fparms.dir = i;
+ fparms.rm_db = tcam_db->tcam_db[i];
+ rc = tf_rm_free_db(tfp, &fparms);
+ if (rc)
+ return rc;
+
+ tcam_db->tcam_db[i] = NULL;
+ }
- tcam_db->tcam_db[i] = NULL;
}
+ rc = tf_tcam_mgr_unbind_msg(tfp, dev);
+ if (rc)
+ return rc;
+
return 0;
}
@@ -222,6 +313,9 @@ tf_tcam_alloc(struct tf *tfp,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_alloc_msg(tfp, dev, parms);
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -251,12 +345,8 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (parms->priority == 0) {
if (i == 0)
parms->idx = index;
- } else {
- parms->idx = index;
- }
}
return 0;
@@ -307,6 +397,14 @@ tf_tcam_free(struct tf *tfp,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ /*
+ * If a session can have multiple references to an entry, check
+ * the reference count here before actually freeing the entry.
+ */
+ return tf_tcam_mgr_free_msg(tfp, dev, parms);
+
if (parms->idx % num_slices) {
TFP_DRV_LOG(ERR,
"%s: TCAM reserved resource is not multiple of %d\n",
@@ -429,6 +527,10 @@ tf_tcam_set(struct tf *tfp __rte_unused,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_set_msg(tfp, dev, parms);
+
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -508,6 +610,10 @@ tf_tcam_get(struct tf *tfp __rte_unused,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_get_msg(tfp, dev, parms);
+
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
new file mode 100644
index 0000000000..c535f4f4f6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
@@ -0,0 +1,286 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <errno.h>
+
+#include "tfp.h"
+#include "tf_tcam.h"
+#include "cfa_tcam_mgr.h"
+#include "tf_tcam_mgr_msg.h"
+
+/*
+ * Table to convert TCAM type to logical TCAM type for applications.
+ * Index is tf_tcam_tbl_type.
+ */
+static enum cfa_tcam_mgr_tbl_type tcam_types[TF_TCAM_TBL_TYPE_MAX] = {
+ [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS,
+ [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS,
+ [TF_TCAM_TBL_TYPE_PROF_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_SP_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_CT_RULE_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_VEB_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM_HIGH] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM_LOW] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+};
+
+static uint16_t hcapi_type[TF_TCAM_TBL_TYPE_MAX];
+
+/*
+ * This is the glue between the core tf_tcam and the TCAM manager. It is
+ * intended to abstract out the location of the TCAM manager so that the core
+ * code will be the same if the TCAM manager is in the core or in firmware.
+ *
+ * If the TCAM manager is in the core, then this file will just translate to
+ * TCAM manager APIs. If TCAM manager is in firmware, then this file will cause
+ * messages to be sent (except for bind and unbind).
+ */
+
+int
+tf_tcam_mgr_qcaps_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ uint32_t *rx_tcam_supported,
+ uint32_t *tx_tcam_supported)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_qcaps_parms mgr_parms;
+ int rc;
+
+ context.tfp = tfp;
+ memset(&mgr_parms, 0, sizeof(mgr_parms));
+ rc = cfa_tcam_mgr_qcaps(&context, &mgr_parms);
+ if (rc >= 0) {
+ *rx_tcam_supported = mgr_parms.rx_tcam_supported;
+ *tx_tcam_supported = mgr_parms.tx_tcam_supported;
+ }
+ return rc;
+}
+
+int
+tf_tcam_mgr_bind_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_cfg_parms *parms,
+ struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX]
+ __rte_unused
+ )
+{
+ /* Common Code */
+ int type;
+
+ if (parms->num_elements != TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "Invalid number of elements in bind request.\n");
+ TFP_DRV_LOG(ERR,
+ "Expected %d, received %d.\n",
+ TF_TCAM_TBL_TYPE_MAX,
+ parms->num_elements);
+ return -EINVAL;
+ }
+
+ for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++)
+ hcapi_type[type] = parms->cfg[type].hcapi_type;
+
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_cfg_parms mgr_parms;
+ struct tf_rm_resc_entry
+ mgr_resv_res[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ int dir, rc;
+
+ context.tfp = tfp;
+
+ memset(&mgr_parms, 0, sizeof(mgr_parms));
+
+ mgr_parms.num_elements = CFA_TCAM_MGR_TBL_TYPE_MAX;
+
+ /* Convert the data to logical tables */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++) {
+ mgr_parms.tcam_cnt[dir][tcam_types[type]] =
+ parms->resources->tcam_cnt[dir].cnt[type];
+ mgr_resv_res[dir][tcam_types[type]].start =
+ resv_res[dir][type].start;
+ mgr_resv_res[dir][tcam_types[type]].stride =
+ resv_res[dir][type].stride;
+ }
+ }
+ mgr_parms.resv_res = mgr_resv_res;
+
+ rc = cfa_tcam_mgr_bind(&context, &mgr_parms);
+
+ return rc;
+}
+
+int
+tf_tcam_mgr_unbind_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused)
+{
+ struct cfa_tcam_mgr_context context;
+
+ context.tfp = tfp;
+
+ return cfa_tcam_mgr_unbind(&context);
+}
+
+int
+tf_tcam_mgr_alloc_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_alloc_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_alloc_parms mgr_parms;
+ int rc;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.key_size = parms->key_size;
+ if (parms->priority > TF_TCAM_PRIORITY_MAX)
+ mgr_parms.priority = 0;
+ else
+ mgr_parms.priority = TF_TCAM_PRIORITY_MAX - parms->priority - 1;
+
+ rc = cfa_tcam_mgr_alloc(&context, &mgr_parms);
+ if (rc)
+ return rc;
+
+ parms->idx = mgr_parms.id;
+ return 0;
+}
+
+int
+tf_tcam_mgr_free_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_free_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_free_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+
+ return cfa_tcam_mgr_free(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_set_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_set_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_set_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+ mgr_parms.key = parms->key;
+ mgr_parms.mask = parms->mask;
+ mgr_parms.key_size = parms->key_size;
+ mgr_parms.result = parms->result;
+ mgr_parms.result_size = parms->result_size;
+
+ return cfa_tcam_mgr_set(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_get_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_get_parms *parms)
+{
+ int rc;
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_get_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+ mgr_parms.key = parms->key;
+ mgr_parms.mask = parms->mask;
+ mgr_parms.key_size = parms->key_size;
+ mgr_parms.result = parms->result;
+ mgr_parms.result_size = parms->result_size;
+
+ rc = cfa_tcam_mgr_get(&context, &mgr_parms);
+ if (rc)
+ return rc;
+
+ parms->key_size = mgr_parms.key_size;
+ parms->result_size = mgr_parms.result_size;
+
+ return rc;
+}
+
+int
+tf_tcam_mgr_shared_clear_msg(struct tf *tfp,
+ struct tf_clear_tcam_shared_entries_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_shared_clear_parms mgr_parms;
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->tcam_tbl_type];
+
+ return cfa_tcam_mgr_shared_clear(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_shared_move_msg(struct tf *tfp,
+ struct tf_move_tcam_shared_entries_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_shared_move_parms mgr_parms;
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->tcam_tbl_type];
+
+ return cfa_tcam_mgr_shared_move(&context, &mgr_parms);
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
new file mode 100644
index 0000000000..8a8d136f5e
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_TCAM_MGR_MSG_H_
+#define _TF_TCAM_MGR_MSG_H_
+
+#include "tf_tcam.h"
+#include "tf_rm.h"
+
+int
+tf_tcam_mgr_qcaps_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ uint32_t *rx_tcam_supported,
+ uint32_t *tx_tcam_supported);
+
+int
+tf_tcam_mgr_bind_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_cfg_parms *parms,
+ struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX]);
+int
+tf_tcam_mgr_unbind_msg(struct tf *tfp,
+ struct tf_dev_info *dev);
+int
+tf_tcam_mgr_alloc_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_alloc_parms *parms);
+int
+tf_tcam_mgr_free_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_free_parms *parms);
+int
+tf_tcam_mgr_set_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_set_parms *parms);
+int
+tf_tcam_mgr_get_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_get_parms *parms);
+int
+tf_tcam_mgr_shared_clear_msg(struct tf *tfp,
+ struct tf_clear_tcam_shared_entries_parms *parms);
+
+int
+tf_tcam_mgr_shared_move_msg(struct tf *tfp,
+ struct tf_move_tcam_shared_entries_parms *parms);
+#endif /* _TF_TCAM_MGR_MSG_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index c120c6f577..e853f616f9 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -1,11 +1,13 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
#include <rte_common.h>
+#include "tf_core.h"
+
#include "tf_tcam_shared.h"
#include "tf_tcam.h"
#include "tf_common.h"
@@ -16,229 +18,8 @@
#include "tf_session.h"
#include "tf_msg.h"
#include "bitalloc.h"
-#include "tf_core.h"
-
-/** Shared WC TCAM pool identifiers
- */
-enum tf_tcam_shared_wc_pool_id {
- TF_TCAM_SHARED_WC_POOL_HI = 0,
- TF_TCAM_SHARED_WC_POOL_LO = 1,
- TF_TCAM_SHARED_WC_POOL_MAX = 2
-};
-
-/** Get string representation of a WC TCAM shared pool id
- */
-static const char *
-tf_pool_2_str(enum tf_tcam_shared_wc_pool_id id)
-{
- switch (id) {
- case TF_TCAM_SHARED_WC_POOL_HI:
- return "TCAM_SHARED_WC_POOL_HI";
- case TF_TCAM_SHARED_WC_POOL_LO:
- return "TCAM_SHARED_WC_POOL_LO";
- default:
- return "Invalid TCAM_SHARED_WC_POOL";
- }
-}
-
-/** The WC TCAM shared pool datastructure
- */
-struct tf_tcam_shared_wc_pool {
- /** Start and stride data */
- struct tf_resource_info info;
- /** bitalloc pool */
- struct bitalloc *pool;
-};
-
-struct tf_tcam_shared_wc_pools {
- struct tf_tcam_shared_wc_pool db[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX];
-};
-
-/** The WC TCAM shared pool declarations
- */
-/* struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; */
-
-static int
-tf_tcam_shared_create_db(struct tf_tcam_shared_wc_pools **db)
-{
- struct tfp_calloc_parms cparms;
- int rc = 0;
-
- cparms.nitems = 1;
- cparms.alignment = 0;
- cparms.size = sizeof(struct tf_tcam_shared_wc_pools);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "TCAM shared db allocation failed (%s)\n",
- strerror(-rc));
- return rc;
- }
- *db = cparms.mem_va;
-
- return rc;
-}
-
-/** Create a WC TCAM shared pool
- */
-static int
-tf_tcam_shared_create_wc_pool(int dir,
- enum tf_tcam_shared_wc_pool_id id,
- int start,
- int stride,
- struct tf_tcam_shared_wc_pools *tcam_shared_wc)
-{
- int rc = 0;
- bool free = true;
- struct tfp_calloc_parms cparms;
- uint32_t pool_size;
-
- /* Create pool */
- pool_size = (BITALLOC_SIZEOF(stride) / sizeof(struct bitalloc));
- cparms.nitems = pool_size;
- cparms.alignment = 0;
- cparms.size = sizeof(struct bitalloc);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: pool memory alloc failed %s:%s\n",
- tf_dir_2_str(dir), tf_pool_2_str(id),
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc->db[dir][id].pool = (struct bitalloc *)cparms.mem_va;
-
- rc = ba_init(tcam_shared_wc->db[dir][id].pool,
- stride,
- free);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: pool bitalloc failed %s\n",
- tf_dir_2_str(dir), tf_pool_2_str(id));
- return rc;
- }
-
- tcam_shared_wc->db[dir][id].info.start = start;
- tcam_shared_wc->db[dir][id].info.stride = stride;
-
- return rc;
-}
-/** Free a WC TCAM shared pool
- */
-static int
-tf_tcam_shared_free_wc_pool(int dir,
- enum tf_tcam_shared_wc_pool_id id,
- struct tf_tcam_shared_wc_pools *tcam_shared_wc)
-{
- int rc = 0;
- TF_CHECK_PARMS1(tcam_shared_wc);
-
- tcam_shared_wc->db[dir][id].info.start = 0;
- tcam_shared_wc->db[dir][id].info.stride = 0;
-
- if (tcam_shared_wc->db[dir][id].pool)
- tfp_free((void *)tcam_shared_wc->db[dir][id].pool);
- return rc;
-}
-
-/** Get the number of WC TCAM slices allocated during 1 allocation/free
- */
-static int
-tf_tcam_shared_get_slices(struct tf *tfp,
- struct tf_dev_info *dev,
- uint16_t *num_slices)
-{
- int rc;
-
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "Operation not supported, rc:%s\n", strerror(-rc));
- return rc;
- }
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- num_slices);
- return rc;
-}
-
-static bool
-tf_tcam_db_valid(struct tf *tfp,
- enum tf_dir dir)
-{
- struct tcam_rm_db *tcam_db;
- void *tcam_db_ptr = NULL;
- int rc;
-
- TF_CHECK_PARMS1(tfp);
-
- rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc)
- return false;
-
- tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
-
- if (tcam_db->tcam_db[dir])
- return true;
-
- return false;
-}
-
-static int
-tf_tcam_shared_get_rm_info(struct tf *tfp,
- enum tf_dir dir,
- uint16_t *hcapi_type,
- struct tf_rm_alloc_info *info)
-{
- int rc;
- struct tcam_rm_db *tcam_db;
- void *tcam_db_ptr = NULL;
- struct tf_rm_get_alloc_info_parms ainfo;
- struct tf_rm_get_hcapi_parms hparms;
-
- TF_CHECK_PARMS3(tfp, hcapi_type, info);
-
- rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc) {
- TFP_DRV_LOG(INFO,
- "Tcam_db is not initialized, rc:%s\n",
- strerror(-rc));
- return 0;
- }
- tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
-
- /* Convert TF type to HCAPI RM type */
- memset(&hparms, 0, sizeof(hparms));
- hparms.rm_db = tcam_db->tcam_db[dir];
- hparms.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- hparms.hcapi_type = hcapi_type;
-
- rc = tf_rm_get_hcapi_type(&hparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Get RM hcapi type failed %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- memset(info, 0, sizeof(struct tf_rm_alloc_info));
- ainfo.rm_db = tcam_db->tcam_db[dir];
- ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- ainfo.info = info;
-
- rc = tf_rm_get_info(&ainfo);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
- return rc;
-}
+#include "tf_rm.h"
+#include "tf_tcam_mgr_msg.h"
/**
* tf_tcam_shared_bind
@@ -247,92 +28,15 @@ int
tf_tcam_shared_bind(struct tf *tfp,
struct tf_tcam_cfg_parms *parms)
{
- int rc, dir;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_rm_alloc_info info;
- uint16_t start, stride;
- uint16_t num_slices;
- uint16_t hcapi_type;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc = NULL;
+ int rc;
TF_CHECK_PARMS2(tfp, parms);
/* Perform normal bind
*/
rc = tf_tcam_bind(tfp, parms);
- if (rc)
- return rc;
-
- /* After the normal TCAM bind, if this is a shared session
- * create all required databases for the WC_HI and WC_LO pools
- */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Session access failure: %s\n", strerror(-rc));
- return rc;
- }
- if (tf_session_is_shared_session(tfs)) {
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- tf_tcam_shared_create_db(&tcam_shared_wc);
-
-
- /* If there are WC TCAM entries, create 2 pools each with 1/2
- * the total number of entries
- */
- for (dir = 0; dir < TF_DIR_MAX; dir++) {
- if (!tf_tcam_db_valid(tfp, dir))
- continue;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(dir));
- goto done;
- }
-
- start = info.entry.start;
- stride = info.entry.stride / 2;
-
- tf_tcam_shared_create_wc_pool(dir,
- TF_TCAM_SHARED_WC_POOL_HI,
- start,
- stride,
- tcam_shared_wc);
-
- start += stride;
- tf_tcam_shared_create_wc_pool(dir,
- TF_TCAM_SHARED_WC_POOL_LO,
- start,
- stride,
- tcam_shared_wc);
-
- tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
- }
-
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
- }
-done:
return rc;
+
}
/**
* tf_tcam_shared_unbind
@@ -340,132 +44,10 @@ tf_tcam_shared_bind(struct tf *tfp,
int
tf_tcam_shared_unbind(struct tf *tfp)
{
- int rc, dir;
- struct tf_dev_info *dev;
- struct tf_session *tfs;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- enum tf_tcam_shared_wc_pool_id pool_id;
- struct tf_tcam_free_parms parms;
- struct bitalloc *pool;
- uint16_t start;
- int log_idx, phy_idx;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- int i, pool_cnt;
+ int rc;
TF_CHECK_PARMS1(tfp);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If not the shared session, call the normal
- * tcam unbind and exit
- */
- if (!tf_session_is_shared_session(tfs)) {
- rc = tf_tcam_unbind(tfp);
- return rc;
- }
-
- /* We must be a shared session, get the database
- */
- rc = tf_session_get_tcam_shared_db(tfp,
- (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db, rc:%s\n",
- strerror(-rc));
- return rc;
- }
-
- tcam_shared_wc =
- (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- /* Get the device
- */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
-
- /* If there are WC TCAM entries allocated, free them
- */
- for (dir = 0; dir < TF_DIR_MAX; dir++) {
- /* If the database is invalid, skip
- */
- if (!tf_tcam_db_valid(tfp, dir))
- continue;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM shared rm info get failed\n",
- tf_dir_2_str(dir));
- return rc;
- }
-
- for (pool_id = TF_TCAM_SHARED_WC_POOL_HI;
- pool_id < TF_TCAM_SHARED_WC_POOL_MAX;
- pool_id++) {
- pool = tcam_shared_wc->db[dir][pool_id].pool;
- start = tcam_shared_wc->db[dir][pool_id].info.start;
- pool_cnt = ba_inuse_count(pool);
-
- if (pool_cnt) {
- TFP_DRV_LOG(INFO,
- "%s: %s: %d residuals found, freeing\n",
- tf_dir_2_str(dir),
- tf_pool_2_str(pool_id),
- pool_cnt);
- }
-
- log_idx = 0;
-
- for (i = 0; i < pool_cnt; i++) {
- log_idx = ba_find_next_inuse(pool, log_idx);
-
- if (log_idx < 0) {
- TFP_DRV_LOG(ERR,
- "Expected a found %s entry %d\n",
- tf_pool_2_str(pool_id),
- i);
- /* attempt normal unbind
- */
- goto done;
- }
- phy_idx = start + log_idx;
-
- parms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- parms.hcapi_type = hcapi_type;
- parms.idx = phy_idx;
- parms.dir = dir;
- rc = tf_msg_tcam_entry_free(tfp, dev, &parms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: %d free failed, rc:%s\n",
- tf_dir_2_str(parms.dir),
- tf_tcam_tbl_2_str(parms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- }
- /* Free the pool once all the entries
- * have been cleared
- */
- tf_tcam_shared_free_wc_pool(dir,
- pool_id,
- tcam_shared_wc);
- }
- }
-done:
rc = tf_tcam_unbind(tfp);
return rc;
}
@@ -478,79 +60,11 @@ tf_tcam_shared_alloc(struct tf *tfp,
struct tf_tcam_alloc_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int log_idx;
- struct bitalloc *pool;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or the type is
- * not one of the special WC TCAM types, call the normal
- * allocation.
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal alloc
- */
- rc = tf_tcam_alloc(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
-
- /*
- * priority 0: allocate from top of the tcam i.e. high
- * priority !0: allocate index from bottom i.e lowest
- */
- if (parms->priority)
- log_idx = ba_alloc_reverse(pool);
- else
- log_idx = ba_alloc(pool);
- if (log_idx == BA_FAIL) {
- TFP_DRV_LOG(ERR,
- "%s: Allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(ENOMEM));
- return -ENOMEM;
- }
- parms->idx = log_idx;
- return 0;
+ rc = tf_tcam_alloc(tfp, parms);
+ return rc;
}
int
@@ -558,118 +72,11 @@ tf_tcam_shared_free(struct tf *tfp,
struct tf_tcam_free_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- uint16_t start;
- int phy_idx;
- struct bitalloc *pool;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_free_parms nparms;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or the type is
- * not one of the special WC TCAM types, call the normal
- * allocation.
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal free
- */
- rc = tf_tcam_free(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir), parms->type, parms->idx);
- return -EINVAL;
- }
-
- rc = ba_free(pool, parms->idx);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%s, idx:%d\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- parms->idx);
- return rc;
- }
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms = *parms;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
- nparms.idx = phy_idx;
-
- rc = tf_msg_tcam_entry_free(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: log%d free failed, rc:%s\n",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- return 0;
+ rc = tf_tcam_free(tfp, parms);
+ return rc;
}
int
@@ -677,109 +84,11 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused,
struct tf_tcam_set_parms *parms __rte_unused)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- int phy_idx, log_idx;
- struct tf_tcam_set_parms nparms;
- struct bitalloc *pool;
- uint16_t start;
- enum tf_tcam_shared_wc_pool_id id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
-
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or one of our
- * special types
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal set and exit
- */
- rc = tf_tcam_set(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- log_idx = parms->idx;
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry is not allocated, type:%d, logid:%d\n",
- tf_dir_2_str(parms->dir), parms->type, log_idx);
- return -EINVAL;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc)
- return rc;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms.hcapi_type = hcapi_type;
- nparms.dir = parms->dir;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.idx = phy_idx;
- nparms.key = parms->key;
- nparms.mask = parms->mask;
- nparms.key_size = parms->key_size;
- nparms.result = parms->result;
- nparms.result_size = parms->result_size;
-
- rc = tf_msg_tcam_entry_set(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phy entry %d set failed, rc:%s",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- return 0;
+ rc = tf_tcam_set(tfp, parms);
+ return rc;
}
int
@@ -787,226 +96,10 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused,
struct tf_tcam_get_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- int phy_idx, log_idx;
- struct tf_tcam_get_parms nparms;
- struct bitalloc *pool;
- uint16_t start;
- enum tf_tcam_shared_wc_pool_id id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or one of our
- * special types
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal get and exit
- */
- rc = tf_tcam_get(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- log_idx = parms->idx;
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry is not allocated, type:%d, logid:%d\n",
- tf_dir_2_str(parms->dir), parms->type, log_idx);
- return -EINVAL;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc)
- return rc;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms = *parms;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
- nparms.idx = phy_idx;
-
- rc = tf_msg_tcam_entry_get(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: Entry %d set failed, rc:%s",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- nparms.idx,
- strerror(-rc));
- return rc;
- }
- return 0;
-}
-
-/* Normally, device specific code wouldn't reside here, it belongs
- * in a separate device specific function in tf_device_pxx.c.
- * But this code is placed here as it is not a long term solution
- * and we would like to have this code centrally located for easy
- * removal
- */
-#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12
-#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4
-#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24
-#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8
-
-/* Temporary builder defines pulled in here and adjusted
- * for max WC TCAM values
- */
-union tf_tmp_field_obj {
- uint32_t words[(TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 + 3) / 4];
- uint8_t bytes[TF_TCAM_SHARED_REMAP_SZ_BYTES_P58];
-};
-
-union tf_tmp_key {
- uint32_t words[(TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 + 3) / 4];
- uint8_t bytes[TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58];
-};
-
-/** p58 has an enable bit, p4 does not
- */
-#define TF_TCAM_SHARED_ENTRY_ENABLE 0x8
-
-/** Move a WC TCAM entry from the high offset to the same low offset
- */
-static int
-tf_tcam_shared_move_entry(struct tf *tfp,
- struct tf_dev_info *dev,
- uint16_t hcapi_type,
- enum tf_dir dir,
- int sphy_idx,
- int dphy_idx,
- int key_sz_bytes,
- int remap_sz_bytes,
- bool set_enable_bit)
-{
- int rc = 0;
- struct tf_tcam_get_parms gparms;
- struct tf_tcam_set_parms sparms;
- struct tf_tcam_free_parms fparms;
- union tf_tmp_key tcam_key_obj;
- union tf_tmp_key tcam_key_msk_obj;
- union tf_tmp_field_obj tcam_remap_obj;
-
- memset(&tcam_key_obj, 0, sizeof(tcam_key_obj));
- memset(&tcam_key_msk_obj, 0, sizeof(tcam_key_msk_obj));
- memset(&tcam_remap_obj, 0, sizeof(tcam_remap_obj));
- memset(&gparms, 0, sizeof(gparms));
-
- gparms.hcapi_type = hcapi_type;
- gparms.dir = dir;
- gparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- gparms.idx = sphy_idx;
- gparms.key = (uint8_t *)&tcam_key_obj;
- gparms.key_size = key_sz_bytes;
- gparms.mask = (uint8_t *)&tcam_key_msk_obj;
- gparms.result = (uint8_t *)&tcam_remap_obj;
- gparms.result_size = remap_sz_bytes;
-
- rc = tf_msg_tcam_entry_get(tfp, dev, &gparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phyid(%d) get failed, rc:%s\n",
- tf_tcam_tbl_2_str(gparms.type),
- tf_dir_2_str(dir),
- gparms.idx,
- strerror(-rc));
- return rc;
- }
-
- if (set_enable_bit)
- tcam_key_obj.bytes[0] |= TF_TCAM_SHARED_ENTRY_ENABLE;
-
- /* Override HI/LO type with parent WC TCAM type */
- sparms.hcapi_type = hcapi_type;
- sparms.dir = dir;
- sparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- sparms.idx = dphy_idx;
- sparms.key = gparms.key;
- sparms.mask = gparms.mask;
- sparms.key_size = key_sz_bytes;
- sparms.result = gparms.result;
- sparms.result_size = remap_sz_bytes;
-
- rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s phyid(%d/0x%x) set failed, rc:%s\n",
- tf_tcam_tbl_2_str(sparms.type),
- tf_dir_2_str(dir),
- sparms.idx,
- sparms.idx,
- strerror(-rc));
- return rc;
- }
-
- /* Override HI/LO type with parent WC TCAM type */
- fparms.dir = dir;
- fparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- fparms.hcapi_type = hcapi_type;
- fparms.idx = sphy_idx;
-
- rc = tf_msg_tcam_entry_free(tfp, dev, &fparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phyid(%d/0x%x) free failed, rc:%s\n",
- tf_dir_2_str(dir),
- tf_tcam_tbl_2_str(fparms.type),
- sphy_idx,
- sphy_idx,
- strerror(-rc));
- return rc;
- }
+ rc = tf_tcam_get(tfp, parms);
return rc;
}
@@ -1015,23 +108,10 @@ tf_tcam_shared_move_entry(struct tf *tfp,
*/
static
int tf_tcam_shared_move(struct tf *tfp,
- struct tf_move_tcam_shared_entries_parms *parms,
- int key_sz_bytes,
- int remap_sz_bytes,
- bool set_enable_bit)
+ struct tf_move_tcam_shared_entries_parms *parms)
{
- int rc;
struct tf_session *tfs;
- struct tf_dev_info *dev;
- int log_idx;
- struct bitalloc *hi_pool, *lo_pool;
- uint16_t hi_start, lo_start;
- enum tf_tcam_shared_wc_pool_id hi_id, lo_id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- int hi_cnt, i;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
+ int rc;
TF_CHECK_PARMS2(tfp, parms);
@@ -1052,104 +132,7 @@ int tf_tcam_shared_move(struct tf *tfp,
return -EOPNOTSUPP;
}
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- /* TODO print amazing error */
- return rc;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- hi_id = TF_TCAM_SHARED_WC_POOL_HI;
- hi_pool = tcam_shared_wc->db[parms->dir][hi_id].pool;
- hi_start = tcam_shared_wc->db[parms->dir][hi_id].info.start;
-
- lo_id = TF_TCAM_SHARED_WC_POOL_LO;
- lo_pool = tcam_shared_wc->db[parms->dir][lo_id].pool;
- lo_start = tcam_shared_wc->db[parms->dir][lo_id].info.start;
-
- if (hi_pool == NULL || lo_pool == NULL)
- return -ENOMEM;
-
- /* Get the total count of in use entries in the high pool
- */
- hi_cnt = ba_inuse_count(hi_pool);
-
- /* Copy each valid entry to the same low pool logical offset
- */
- log_idx = 0;
-
- for (i = 0; i < hi_cnt; i++) {
- /* Find next free index starting from where we left off
- */
- log_idx = ba_find_next_inuse(hi_pool, log_idx);
- if (log_idx < 0) {
- TFP_DRV_LOG(ERR,
- "Expected a found %s entry %d\n",
- tf_pool_2_str(hi_id),
- i);
- goto done;
- }
- /* The user should have never allocated from the low
- * pool because the move only happens when switching
- * from the high to the low pool
- */
- if (ba_alloc_index(lo_pool, log_idx) < 0) {
- TFP_DRV_LOG(ERR,
- "Warning %s index %d already allocated\n",
- tf_pool_2_str(lo_id),
- i);
-
- /* Since already allocated, continue with move
- */
- }
-
- rc = tf_tcam_shared_move_entry(tfp, dev,
- hcapi_type,
- parms->dir,
- hi_start + log_idx,
- lo_start + log_idx,
- key_sz_bytes,
- remap_sz_bytes,
- set_enable_bit);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Move error %s to %s index %d\n",
- tf_dir_2_str(parms->dir),
- tf_pool_2_str(hi_id),
- tf_pool_2_str(lo_id),
- i);
- goto done;
- }
- ba_free(hi_pool, log_idx);
- }
-done:
+ rc = tf_tcam_mgr_shared_move_msg(tfp, parms);
return rc;
}
@@ -1159,24 +142,17 @@ tf_tcam_shared_move_p4(struct tf *tfp,
{
int rc = 0;
rc = tf_tcam_shared_move(tfp,
- parms,
- TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4,
- TF_TCAM_SHARED_REMAP_SZ_BYTES_P4,
- false); /* no enable bit */
+ parms);
return rc;
}
-
int
tf_tcam_shared_move_p58(struct tf *tfp,
struct tf_move_tcam_shared_entries_parms *parms)
{
int rc = 0;
rc = tf_tcam_shared_move(tfp,
- parms,
- TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58,
- TF_TCAM_SHARED_REMAP_SZ_BYTES_P58,
- true); /* set enable bit */
+ parms);
return rc;
}
@@ -1186,16 +162,6 @@ tf_tcam_shared_clear(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
- struct tf_dev_info *dev;
- uint16_t start;
- int phy_idx;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_free_parms nparms;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- int i, cnt;
TF_CHECK_PARMS2(tfp, parms);
@@ -1209,74 +175,6 @@ tf_tcam_shared_clear(struct tf *tfp,
parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW))
return -EOPNOTSUPP;
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- if (parms->tcam_tbl_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- start = tcam_shared_wc->db[parms->dir][id].info.start;
- cnt = tcam_shared_wc->db[parms->dir][id].info.stride;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms.dir = parms->dir;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
-
- for (i = 0; i < cnt; i++) {
- phy_idx = start + i;
- nparms.idx = phy_idx;
-
- /* Clear entry */
- rc = tf_msg_tcam_entry_free(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: log%d free failed, rc:%s\n",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- }
-
- TFP_DRV_LOG(DEBUG,
- "%s: TCAM shared clear pool(%s)\n",
- tf_dir_2_str(nparms.dir),
- tf_pool_2_str(id));
- return 0;
+ rc = tf_tcam_mgr_shared_clear_msg(tfp, parms);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
index 524631f262..e25babcd18 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -129,7 +129,6 @@ int tf_tcam_shared_set(struct tf *tfp,
int tf_tcam_shared_get(struct tf *tfp,
struct tf_tcam_get_parms *parms);
-
/**
* Moves entries from the WC_TCAM_HI to the WC_TCAM_LO shared pools
* for the P4 device.
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 1bb38399e4..8513ee06a9 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -448,13 +448,13 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
switch (ulp_dev_id) {
case BNXT_ULP_DEVICE_ID_WH_PLUS:
- parms.device_type = TF_DEVICE_TYPE_WH;
+ parms.device_type = TF_DEVICE_TYPE_P5;
break;
case BNXT_ULP_DEVICE_ID_STINGRAY:
parms.device_type = TF_DEVICE_TYPE_SR;
break;
case BNXT_ULP_DEVICE_ID_THOR:
- parms.device_type = TF_DEVICE_TYPE_THOR;
+ parms.device_type = TF_DEVICE_TYPE_P4;
break;
default:
BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n");
@@ -563,13 +563,13 @@ ulp_ctx_session_open(struct bnxt *bp,
switch (ulp_dev_id) {
case BNXT_ULP_DEVICE_ID_WH_PLUS:
- params.device_type = TF_DEVICE_TYPE_WH;
+ params.device_type = TF_DEVICE_TYPE_P5;
break;
case BNXT_ULP_DEVICE_ID_STINGRAY:
params.device_type = TF_DEVICE_TYPE_SR;
break;
case BNXT_ULP_DEVICE_ID_THOR:
- params.device_type = TF_DEVICE_TYPE_THOR;
+ params.device_type = TF_DEVICE_TYPE_P4;
break;
default:
BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n");
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 05/11] net/bnxt: update ULP shared session support
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (3 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
` (6 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Kishore Padmanabha, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 3549314 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Update ulp generic templates
- Modify code to support shared sessions
This should allow more than one application to share a TruFlow
session.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 16 +-
drivers/net/bnxt/bnxt_ethdev.c | 8 +-
drivers/net/bnxt/bnxt_reps.c | 4 +-
drivers/net/bnxt/tf_core/tf_rm.c | 28 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 548 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 109 +-
.../bnxt/tf_ulp/generic_templates/meson.build | 18 +-
.../generic_templates/ulp_template_db_act.c | 7000 +++-
.../generic_templates/ulp_template_db_class.c | 33556 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 4366 +-
.../generic_templates/ulp_template_db_field.h | 689 +-
.../generic_templates/ulp_template_db_tbl.c | 16055 ++++++--
.../ulp_template_db_thor_act.c | 8714 ++--
.../ulp_template_db_thor_class.c | 10746 +++--
.../ulp_template_db_wh_plus_act.c | 1157 +-
.../ulp_template_db_wh_plus_class.c | 288 +-
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 25 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 7 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 15 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 281 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 17 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 22 +-
27 files changed, 63079 insertions(+), 20661 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 2bccdec7e0..bb2e7fe003 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -633,6 +633,13 @@ struct bnxt_ring_stats {
uint64_t rx_agg_aborts;
};
+enum bnxt_session_type {
+ BNXT_SESSION_TYPE_REGULAR = 0,
+ BNXT_SESSION_TYPE_SHARED_COMMON,
+ BNXT_SESSION_TYPE_SHARED_WC,
+ BNXT_SESSION_TYPE_LAST
+};
+
struct bnxt {
void *bar0;
@@ -690,6 +697,9 @@ struct bnxt {
#define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1)
#define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \
((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
+#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
+#define BNXT_TESTPMD_EN(bp) \
+ ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
uint16_t chip_num;
#define CHIP_NUM_58818 0xd818
@@ -855,8 +865,7 @@ struct bnxt {
uint16_t func_svif;
uint16_t port_svif;
- struct tf tfp;
- struct tf tfp_shared;
+ struct tf tfp[BNXT_SESSION_TYPE_LAST];
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_stat_info *flow_stat;
uint16_t max_num_kflows;
@@ -1044,4 +1053,5 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ef7b8859d9..bcde44bb14 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -6415,6 +6415,12 @@ bool is_bnxt_supported(struct rte_eth_dev *dev)
return is_device_supported(dev, &bnxt_rte_pmd);
}
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type)
+{
+ return (type >= BNXT_SESSION_TYPE_LAST) ?
+ &bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type];
+}
+
RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 8a5b777793..78337431af 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -327,7 +327,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
(void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
/* Update the ULP portdata base with the new VFR interface */
- rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
+ rc = ulp_port_db_port_update(parent_bp->ulp_ctx, vfr_ethdev);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n",
vfr->vf_id);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 1fccb698d0..9b85f5397d 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -364,8 +364,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt,
- bool shared_session)
+ uint16_t *req_cnt)
{
int parent, child;
const char *type_str = NULL;
@@ -376,11 +375,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- uint8_t p_slices = 1;
-
- /* Shared session doesn't support slices */
- if (!shared_session)
- p_slices = cfg[parent].slices;
+ uint8_t p_slices = cfg[parent].slices;
RTE_ASSERT(p_slices);
@@ -402,12 +397,9 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
- uint8_t c_slices = 1;
+ uint8_t c_slices = cfg[child].slices;
uint16_t cnt = 0;
- if (!shared_session)
- c_slices = cfg[child].slices;
-
RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
@@ -429,7 +421,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
}
/* Save the parent count to be requested */
- req_cnt[parent] = combined_cnt;
+ req_cnt[parent] = combined_cnt * 2;
}
}
return 0;
@@ -452,7 +444,6 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
- bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -505,15 +496,12 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
- shared_session = tf_session_is_shared_session(tfs);
-
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt,
- shared_session);
+ req_cnt);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -733,7 +721,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
- bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -763,15 +750,12 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
- shared_session = tf_session_is_shared_session(tfs);
-
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt,
- shared_session);
+ req_cnt);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 8513ee06a9..109bd0652a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -13,6 +13,7 @@
#include "bnxt.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "hsi_struct_def_dpdk.h"
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
@@ -26,6 +27,7 @@
#include "ulp_tun.h"
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#include "ulp_template_db_tbl.h"
/* Linked list of all TF sessions. */
STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list =
@@ -91,6 +93,17 @@ bnxt_ulp_app_cap_list_get(uint32_t *num_entries)
return ulp_app_cap_info_list;
}
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries)
+{
+ if (!num_entries)
+ return NULL;
+
+ *num_entries = BNXT_ULP_GEN_TBL_MAX_SZ;
+
+ return ulp_shared_act_info;
+}
+
static struct bnxt_ulp_resource_resv_info *
bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries)
{
@@ -122,6 +135,7 @@ static int32_t
bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_glb_resource_info *info,
uint32_t num,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i;
@@ -149,6 +163,11 @@ bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
for (i = 0; i < num; i++) {
if (dev_id != info[i].device_id || app_id != info[i].app_id)
continue;
+ /* check to see if the session type matches only then include */
+ if ((stype || info[i].session_type) &&
+ !(info[i].session_type & stype))
+ continue;
+
dir = info[i].direction;
res_type = info[i].resource_type;
@@ -179,6 +198,7 @@ static int32_t
bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_resource_resv_info *info,
uint32_t num,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
uint32_t dev_id, res_type, i;
@@ -206,6 +226,12 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
for (i = 0; i < num; i++) {
if (app_id != info[i].app_id || dev_id != info[i].device_id)
continue;
+
+ /* check to see if the session type matches only then include */
+ if ((stype || info[i].session_type) &&
+ !(info[i].session_type & stype))
+ continue;
+
dir = info[i].direction;
res_type = info[i].resource_type;
@@ -231,6 +257,7 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
static int32_t
bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
struct bnxt_ulp_resource_resv_info *unnamed = NULL;
@@ -242,13 +269,18 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
+ /* use DEFAULT_NON_HA instead of DEFAULT resources if HA is disabled */
+ if (ULP_APP_HA_IS_DYNAMIC(ulp_ctx))
+ stype = ulp_ctx->cfg_data->def_session_type;
+
unnamed = bnxt_ulp_resource_resv_list_get(&unum);
if (unnamed == NULL) {
BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n");
return -EINVAL;
}
- rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+ rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+ res);
if (rc)
BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n");
@@ -257,6 +289,7 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
static int32_t
bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
struct bnxt_ulp_resource_resv_info *unnamed;
@@ -272,6 +305,10 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
/* Make sure the resources are zero before accumulating. */
memset(res, 0, sizeof(struct tf_session_resources));
+ if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) &&
+ stype == BNXT_ULP_SESSION_TYPE_SHARED)
+ stype = ulp_ctx->cfg_data->hu_session_type;
+
/*
* Shared resources are comprised of both named and unnamed resources.
* First get the unnamed counts, and then add the named to the result.
@@ -282,9 +319,11 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Unable to get shared resource resv list.\n");
return -EINVAL;
}
- rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+ rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+ res);
if (rc) {
- BNXT_TF_DBG(ERR, "Unable to calc resources for shared session.\n");
+ BNXT_TF_DBG(ERR,
+ "Unable to calc resources for shared session.\n");
return -EINVAL;
}
@@ -294,7 +333,7 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Unable to get app global resource list\n");
return -EINVAL;
}
- rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, res);
+ rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, stype, res);
if (rc)
BNXT_TF_DBG(ERR, "Unable to calc named resources\n");
@@ -356,17 +395,127 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
return 0;
}
+/* Function to set the number for vxlan_ip (custom vxlan) port into the context */
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_ip_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->vxlan_ip_port = vxlan_ip_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->vxlan_ip_port;
+}
+
+/* Function to set the number for vxlan port into the context */
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->vxlan_port = vxlan_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan port from the context. */
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->vxlan_port;
+}
+
+static inline uint32_t
+bnxt_ulp_session_idx_get(enum bnxt_ulp_session_type session_type) {
+ if (session_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ return 1;
+ else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ return 2;
+ return 0;
+}
+
+/* Function to set the tfp session details in session */
+static int32_t
+bnxt_ulp_session_tfp_set(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type,
+ struct tf *tfp)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+ int32_t rc = 0;
+
+ if (!session->session_opened[idx]) {
+ session->g_tfp[idx] = rte_zmalloc("bnxt_ulp_session_tfp",
+ sizeof(struct tf), 0);
+ if (!session->g_tfp[idx]) {
+ BNXT_TF_DBG(DEBUG, "Failed to alloc session tfp\n");
+ return -ENOMEM;
+ }
+ session->g_tfp[idx]->session = tfp->session;
+ session->session_opened[idx] = 1;
+ }
+ return rc;
+}
+
+/* Function to get the tfp session details in session */
+static struct tf_session_info *
+bnxt_ulp_session_tfp_get(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ if (session->session_opened[idx])
+ return session->g_tfp[idx]->session;
+ return NULL;
+}
+
+static uint32_t
+bnxt_ulp_session_is_open(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ return session->session_opened[idx];
+}
+
+/* Function to reset the tfp session details in session */
+static void
+bnxt_ulp_session_tfp_reset(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ if (session->session_opened[idx]) {
+ session->session_opened[idx] = 0;
+ rte_free(session->g_tfp[idx]);
+ session->g_tfp[idx] = NULL;
+ }
+}
+
static void
ulp_ctx_shared_session_close(struct bnxt *bp,
+ enum bnxt_ulp_session_type session_type,
struct bnxt_ulp_session_state *session)
{
struct tf *tfp;
int32_t rc;
- if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
- return;
-
- tfp = bnxt_ulp_cntxt_shared_tfp_get(bp->ulp_ctx);
+ tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type);
if (!tfp) {
/*
* Log it under debug since this is likely a case of the
@@ -380,29 +529,26 @@ ulp_ctx_shared_session_close(struct bnxt *bp,
if (rc)
BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n",
rc);
- (void)bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, NULL);
-
- session->g_shared_tfp.session = NULL;
+ (void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL);
+ bnxt_ulp_session_tfp_reset(session, session_type);
}
static int32_t
ulp_ctx_shared_session_open(struct bnxt *bp,
+ enum bnxt_ulp_session_type session_type,
struct bnxt_ulp_session_state *session)
{
struct rte_eth_dev *ethdev = bp->eth_dev;
struct tf_session_resources *resources;
struct tf_open_session_parms parms;
- size_t copy_nbytes;
+ size_t nb;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
uint8_t app_id;
-
- /* only perform this if shared session is enabled. */
- if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
- return 0;
+ struct tf *tfp;
+ uint8_t pool_id;
memset(&parms, 0, sizeof(parms));
-
rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id,
parms.ctrl_chan_name);
if (rc) {
@@ -416,21 +562,39 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
* Need to account for size of ctrl_chan_name and 1 extra for Null
* terminator
*/
- copy_nbytes = sizeof(parms.ctrl_chan_name) -
- strlen(parms.ctrl_chan_name) - 1;
+ nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1;
/*
* Build the ctrl_chan_name with shared token.
* When HA is enabled, the WC TCAM needs extra management by the core,
* so add the wc_tcam string to the control channel.
*/
- if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
- strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam",
- copy_nbytes);
- else
- strncat(parms.ctrl_chan_name, "-tf_shared", copy_nbytes);
+ pool_id = bp->ulp_ctx->cfg_data->ha_pool_id;
+ if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
+ strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb);
+ else
+ strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+ } else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) {
+ strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+ } else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) {
+ char session_pool_name[64];
+
+ sprintf(session_pool_name, "-tf_shared-pool%d",
+ pool_id);
+
+ if (nb >= strlen(session_pool_name)) {
+ strncat(parms.ctrl_chan_name, session_pool_name, nb);
+ } else {
+ BNXT_TF_DBG(ERR, "No space left for session_name\n");
+ return -EINVAL;
+ }
+ }
+ }
- rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources);
+ rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type,
+ resources);
if (rc)
return rc;
@@ -446,32 +610,15 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
return rc;
}
- switch (ulp_dev_id) {
- case BNXT_ULP_DEVICE_ID_WH_PLUS:
- parms.device_type = TF_DEVICE_TYPE_P5;
- break;
- case BNXT_ULP_DEVICE_ID_STINGRAY:
- parms.device_type = TF_DEVICE_TYPE_SR;
- break;
- case BNXT_ULP_DEVICE_ID_THOR:
- parms.device_type = TF_DEVICE_TYPE_P4;
- break;
- default:
- BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n");
- return rc;
- }
-
+ tfp = bnxt_ulp_bp_tfp_get(bp, session_type);
+ parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
parms.bp = bp;
- if (app_id == 0)
- parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
- else
- parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
* mapper initialization.
*/
- rc = tf_open_session(&bp->tfp_shared, &parms);
+ rc = tf_open_session(tfp, &parms);
if (rc)
return rc;
@@ -481,40 +628,70 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
BNXT_TF_DBG(DEBUG, "Shared session attached.\n");
/* Save the shared session in global data */
- if (!session->g_shared_tfp.session)
- session->g_shared_tfp.session = bp->tfp_shared.session;
+ rc = bnxt_ulp_session_tfp_set(session, session_type, tfp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add shared tfp to session\n");
+ return rc;
+ }
- rc = bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, &bp->tfp_shared);
- if (rc)
+ rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp);
+ if (rc) {
BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc);
+ return rc;
+ }
return rc;
}
static int32_t
ulp_ctx_shared_session_attach(struct bnxt *bp,
- struct bnxt_ulp_session_state *session)
+ struct bnxt_ulp_session_state *ses)
{
+ enum bnxt_ulp_session_type type;
+ struct tf *tfp;
int32_t rc = 0;
/* Simply return success if shared session not enabled */
if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
- bp->tfp_shared.session = session->g_shared_tfp.session;
- rc = ulp_ctx_shared_session_open(bp, session);
+ type = BNXT_ULP_SESSION_TYPE_SHARED;
+ tfp = bnxt_ulp_bp_tfp_get(bp, type);
+ tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+ rc = ulp_ctx_shared_session_open(bp, type, ses);
+ }
+
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ type = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+ tfp = bnxt_ulp_bp_tfp_get(bp, type);
+ tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+ rc = ulp_ctx_shared_session_open(bp, type, ses);
}
+ if (!rc)
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
return rc;
}
static void
ulp_ctx_shared_session_detach(struct bnxt *bp)
{
+ struct tf *tfp;
+
if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
- if (bp->tfp_shared.session) {
- tf_close_session(&bp->tfp_shared);
- bp->tfp_shared.session = NULL;
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
}
}
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
+ }
+ }
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
}
/*
@@ -538,6 +715,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
uint8_t app_id;
+ struct tf *tfp;
memset(¶ms, 0, sizeof(params));
@@ -561,43 +739,29 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
}
- switch (ulp_dev_id) {
- case BNXT_ULP_DEVICE_ID_WH_PLUS:
- params.device_type = TF_DEVICE_TYPE_P5;
- break;
- case BNXT_ULP_DEVICE_ID_STINGRAY:
- params.device_type = TF_DEVICE_TYPE_SR;
- break;
- case BNXT_ULP_DEVICE_ID_THOR:
- params.device_type = TF_DEVICE_TYPE_P4;
- break;
- default:
- BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n");
- return rc;
- }
-
+ params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
resources = ¶ms.resources;
- rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources);
+ rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx,
+ BNXT_ULP_SESSION_TYPE_DEFAULT,
+ resources);
if (rc)
return rc;
params.bp = bp;
- if (app_id == 0)
- params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
- else
- params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
- rc = tf_open_session(&bp->tfp, ¶ms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_open_session(tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
params.ctrl_chan_name, rc);
return -EINVAL;
}
- if (!session->session_opened) {
- session->session_opened = 1;
- session->g_tfp = rte_zmalloc("bnxt_ulp_session_tfp",
- sizeof(struct tf), 0);
- session->g_tfp->session = bp->tfp.session;
+ rc = bnxt_ulp_session_tfp_set(session,
+ BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set TF session - %s, rc = %d\n",
+ params.ctrl_chan_name, rc);
+ return -EINVAL;
}
return rc;
}
@@ -610,12 +774,14 @@ static void
ulp_ctx_session_close(struct bnxt *bp,
struct bnxt_ulp_session_state *session)
{
+ struct tf *tfp;
+
/* close the session in the hardware */
- if (session->session_opened)
- tf_close_session(&bp->tfp);
- session->session_opened = 0;
- rte_free(session->g_tfp);
- session->g_tfp = NULL;
+ if (bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) {
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ tf_close_session(tfp);
+ }
+ bnxt_ulp_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT);
}
static void
@@ -678,6 +844,7 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
struct bnxt_ulp_device_params *dparms;
enum bnxt_ulp_flow_mem_type mtype;
uint32_t dev_id;
+ struct tf *tfp;
int rc;
/* Get the dev specific number of flows that needed to be supported. */
@@ -700,12 +867,14 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
}
bnxt_init_tbl_scope_parms(bp, ¶ms);
- rc = tf_alloc_tbl_scope(&bp->tfp, ¶ms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_alloc_tbl_scope(tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n",
rc);
return rc;
}
+
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -729,7 +898,7 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
if (!ulp_ctx || !ulp_ctx->cfg_data)
return -EINVAL;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
return -EINVAL;
@@ -777,7 +946,16 @@ ulp_ctx_deinit(struct bnxt *bp,
ulp_ctx_session_close(bp, session);
/* The shared session must be closed last. */
- ulp_ctx_shared_session_close(bp, session);
+ if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
+ ulp_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED,
+ session);
+
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx))
+ ulp_ctx_shared_session_close(bp,
+ BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ session);
+
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
/* Free the contents */
if (session->cfg_data) {
@@ -796,6 +974,8 @@ ulp_ctx_init(struct bnxt *bp,
struct bnxt_ulp_data *ulp_data;
int32_t rc = 0;
enum bnxt_ulp_device_id devid;
+ enum bnxt_ulp_session_type stype;
+ struct tf *tfp;
/* Initialize the context entries list */
bnxt_ulp_cntxt_list_init();
@@ -851,22 +1031,42 @@ ulp_ctx_init(struct bnxt *bp,
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
*/
- rc = ulp_ctx_shared_session_open(bp, session);
- if (rc) {
- BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", rc);
- goto error_deinit;
+ if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
+ rc = ulp_ctx_shared_session_open(bp,
+ BNXT_ULP_SESSION_TYPE_SHARED,
+ session);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n",
+ rc);
+ goto error_deinit;
+ }
}
+ /* Multiple session support */
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ stype = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+ rc = ulp_ctx_shared_session_open(bp, stype, session);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Unable to open shared wc session (%d)\n",
+ rc);
+ goto error_deinit;
+ }
+ }
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
+
/* Open the ulp session. */
rc = ulp_ctx_session_open(bp, session);
if (rc)
goto error_deinit;
- bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
error_deinit:
- session->session_opened = 1;
+ session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1;
(void)ulp_ctx_deinit(bp, session);
return rc;
}
@@ -932,6 +1132,7 @@ ulp_ctx_attach(struct bnxt *bp,
{
int32_t rc = 0;
uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ struct tf *tfp;
uint8_t app_id;
/* Increment the ulp context data reference count usage. */
@@ -939,7 +1140,9 @@ ulp_ctx_attach(struct bnxt *bp,
bp->ulp_ctx->cfg_data->ref_cnt++;
/* update the session details in bnxt tfp */
- bp->tfp.session = session->g_tfp->session;
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ tfp->session = bnxt_ulp_session_tfp_get(session,
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
/* Add the context to the context entries list */
rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx);
@@ -975,20 +1178,23 @@ ulp_ctx_attach(struct bnxt *bp,
rc = ulp_ctx_session_open(bp, session);
if (rc) {
PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc);
- bp->tfp.session = NULL;
+ tfp->session = NULL;
return rc;
}
- bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+ bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
}
static void
ulp_ctx_detach(struct bnxt *bp)
{
- if (bp->tfp.session) {
- tf_close_session(&bp->tfp);
- bp->tfp.session = NULL;
+ struct tf *tfp;
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
}
}
@@ -1121,6 +1327,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
uint32_t global_cfg = 0;
int rc;
struct tf_global_cfg_parms parms = { 0 };
+ struct tf *tfp;
/* Initialize the params */
parms.dir = dir,
@@ -1129,7 +1336,8 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
parms.config = (uint8_t *)&global_cfg,
parms.config_sz_in_bytes = sizeof(global_cfg);
- rc = tf_get_global_cfg(&bp->tfp, &parms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_global_cfg(tfp, &parms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n",
type, rc);
@@ -1142,7 +1350,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
global_cfg &= ~value;
/* SET the register RE_CFA_REG_ACT_TECT */
- rc = tf_set_global_cfg(&bp->tfp, &parms);
+ rc = tf_set_global_cfg(tfp, &parms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n",
type, rc);
@@ -1473,7 +1681,7 @@ bnxt_ulp_port_init(struct bnxt *bp)
}
/* update the port database for the given interface */
- rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+ rc = ulp_port_db_port_update(bp->ulp_ctx, bp->eth_dev);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to update port database\n");
goto jump_to_error;
@@ -1624,6 +1832,12 @@ bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
return ULP_SHARED_SESSION_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags);
}
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
+{
+ return ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx);
+}
+
int32_t
bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id)
{
@@ -1721,74 +1935,86 @@ bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
-/* Function to set the shared tfp session details from the ulp context. */
-int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
-{
- if (!ulp) {
- BNXT_TF_DBG(ERR, "Invalid arguments\n");
- return -EINVAL;
- }
-
- if (tfp == NULL) {
- if (ulp->cfg_data->num_shared_clients > 0)
- ulp->cfg_data->num_shared_clients--;
- } else {
- ulp->cfg_data->num_shared_clients++;
- }
-
- ulp->g_shared_tfp = tfp;
- return 0;
-}
-
-/* Function to get the shared tfp session details from the ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp)
+/* Function to get the number of shared clients attached */
+uint8_t
+bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
{
- if (!ulp) {
+ if (ulp == NULL || ulp->cfg_data == NULL) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
- return NULL;
+ return 0;
}
- return ulp->g_shared_tfp;
+ return ulp->cfg_data->num_shared_clients;
}
-/* Function to get the number of shared clients attached */
-uint8_t
-bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
+/* Function to set the number of shared clients */
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr)
{
if (ulp == NULL || ulp->cfg_data == NULL) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return 0;
}
- return ulp->cfg_data->num_shared_clients;
+ if (incr)
+ ulp->cfg_data->num_shared_clients++;
+ else if (ulp->cfg_data->num_shared_clients)
+ ulp->cfg_data->num_shared_clients--;
+
+ BNXT_TF_DBG(DEBUG, "%d:clients(%d)\n", incr,
+ ulp->cfg_data->num_shared_clients);
+
+ return 0;
}
/* Function to set the tfp session details from the ulp context. */
int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+ enum bnxt_ulp_session_type s_type,
+ struct tf *tfp)
{
+ uint32_t idx = 0;
+
if (!ulp) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return -EINVAL;
}
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+ if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ idx = 1;
+ else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ idx = 2;
+
+ } else {
+ if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+ (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ idx = 1;
+ }
- ulp->g_tfp = tfp;
+ ulp->g_tfp[idx] = tfp;
return 0;
}
/* Function to get the tfp session details from the ulp context. */
struct tf *
bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
- enum bnxt_ulp_shared_session shared)
+ enum bnxt_ulp_session_type s_type)
{
+ uint32_t idx = 0;
+
if (!ulp) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return NULL;
}
- if (shared)
- return ulp->g_shared_tfp;
- else
- return ulp->g_tfp;
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+ if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ idx = 1;
+ else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ idx = 2;
+ } else {
+ if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+ (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ idx = 1;
+ }
+ return ulp->g_tfp[idx];
}
/*
@@ -2079,3 +2305,41 @@ bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
return ulp->cfg_data->app_tun;
}
+
+/* Function to convert ulp dev id to regular dev id. */
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
+{
+ enum tf_device_type type = 0;
+
+ switch (ulp_dev_id) {
+ case BNXT_ULP_DEVICE_ID_WH_PLUS:
+ type = TF_DEVICE_TYPE_P4;
+ break;
+ case BNXT_ULP_DEVICE_ID_STINGRAY:
+ type = TF_DEVICE_TYPE_SR;
+ break;
+ case BNXT_ULP_DEVICE_ID_THOR:
+ type = TF_DEVICE_TYPE_P5;
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid device id\n");
+ break;
+ }
+ return type;
+}
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type)
+{
+ enum bnxt_session_type btype;
+
+ if (type & BNXT_ULP_SESSION_TYPE_SHARED)
+ btype = BNXT_SESSION_TYPE_SHARED_COMMON;
+ else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ btype = BNXT_SESSION_TYPE_SHARED_WC;
+ else
+ btype = BNXT_SESSION_TYPE_REGULAR;
+
+ return bnxt_get_tfp_session(bp, btype);
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 906d933af5..9b30851b13 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -35,6 +35,11 @@
#define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8
#define BNXT_ULP_APP_UNICAST_ONLY 0x10
#define BNXT_ULP_APP_SOCKET_DIRECT 0x20
+#define BNXT_ULP_APP_TOS_PROTO_SUPPORT 0x40
+#define BNXT_ULP_APP_BC_MC_SUPPORT 0x80
+#define BNXT_ULP_CUST_VXLAN_SUPPORT 0x100
+#define BNXT_ULP_MULTI_SHARED_SUPPORT 0x200
+#define BNXT_ULP_APP_HA_DYNAMIC 0x400
#define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED)
#define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\
@@ -43,6 +48,17 @@
BNXT_ULP_APP_DEV_UNSUPPORTED)
#define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED)
#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT)
+#define ULP_APP_TOS_PROTO_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_TOS_PROTO_SUPPORT)
+#define ULP_APP_BC_MC_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_BC_MC_SUPPORT)
+#define ULP_MULTI_SHARED_IS_SUPPORTED(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_MULTI_SHARED_SUPPORT)
+#define ULP_APP_HA_IS_DYNAMIC(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_HA_DYNAMIC)
+
+#define ULP_APP_CUST_VXLAN_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_port != 0)
+#define ULP_APP_CUST_VXLAN_IP_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_ip_port != 0)
enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
@@ -95,12 +111,19 @@ struct bnxt_ulp_data {
uint8_t app_id;
uint8_t num_shared_clients;
struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
+ uint32_t vxlan_port;
+ uint32_t vxlan_ip_port;
+ uint8_t hu_reg_state;
+ uint8_t hu_reg_cnt;
+ uint32_t hu_session_type;
+ uint8_t ha_pool_id;
+ enum bnxt_ulp_session_type def_session_type;
};
+#define BNXT_ULP_SESSION_MAX 3
struct bnxt_ulp_context {
struct bnxt_ulp_data *cfg_data;
- struct tf *g_tfp;
- struct tf *g_shared_tfp;
+ struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
};
struct bnxt_ulp_pci_info {
@@ -110,13 +133,12 @@ struct bnxt_ulp_pci_info {
struct bnxt_ulp_session_state {
STAILQ_ENTRY(bnxt_ulp_session_state) next;
- bool bnxt_ulp_init;
- pthread_mutex_t bnxt_ulp_mutex;
- struct bnxt_ulp_pci_info pci_info;
- struct bnxt_ulp_data *cfg_data;
- struct tf *g_tfp;
- struct tf g_shared_tfp;
- uint32_t session_opened;
+ bool bnxt_ulp_init;
+ pthread_mutex_t bnxt_ulp_mutex;
+ struct bnxt_ulp_pci_info pci_info;
+ struct bnxt_ulp_data *cfg_data;
+ struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
+ uint32_t session_opened[BNXT_ULP_SESSION_MAX];
};
/* ULP flow id structure */
@@ -172,20 +194,14 @@ bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx,
/* Function to set the tfp session details in the ulp context. */
int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
-
-/* Function to get the tfp session details from ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp);
-
-/* Function to set the tfp session details in the ulp context. */
-int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+ enum bnxt_ulp_session_type s_type,
+ struct tf *tfp);
/* Function to get the tfp session details from ulp context. */
struct tf *
bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
- enum bnxt_ulp_shared_session shared);
+ enum bnxt_ulp_session_type s_type);
/* Get the device table entry based on the device id. */
struct bnxt_ulp_device_params *
@@ -238,6 +254,7 @@ int32_t
ulp_default_flow_create(struct rte_eth_dev *eth_dev,
struct ulp_tlv_param *param_list,
uint32_t ulp_class_tid,
+ uint16_t port_id,
uint32_t *flow_id);
/* Function to destroy default flows. */
@@ -274,6 +291,20 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
+int32_t
+bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle,
+ uint32_t *action_handle_type);
+
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries);
+
+int32_t
+bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle,
+ uint32_t *dir);
+
+uint32_t
+bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle);
+
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -286,6 +317,9 @@ bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id);
bool
bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
+
struct bnxt_ulp_app_capabilities_info *
bnxt_ulp_app_cap_list_get(uint32_t *num_entries);
@@ -315,6 +349,41 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp_ctx,
+ bool incr);
+
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
+/* Function to get the truflow app id. This defined in the build file */
+uint32_t
+bnxt_ulp_default_app_id_get(void);
+
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_port);
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_ip_port);
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
+
+int32_t
+bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx,
+ uint8_t state, uint8_t cnt);
+
+uint32_t
+bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index 4ace838a3c..b1b92e61ab 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,15 +2,13 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
-#Include the folder for headers
includes += include_directories('.')
-
-#Add the source files
sources += files(
- 'ulp_template_db_class.c',
- 'ulp_template_db_act.c',
- 'ulp_template_db_tbl.c',
- 'ulp_template_db_wh_plus_act.c',
- 'ulp_template_db_wh_plus_class.c',
- 'ulp_template_db_thor_act.c',
- 'ulp_template_db_thor_class.c')
+ 'ulp_template_db_class.c',
+ 'ulp_template_db_act.c',
+ 'ulp_template_db_tbl.c',
+ 'ulp_template_db_wh_plus_act.c',
+ 'ulp_template_db_wh_plus_class.c',
+ 'ulp_template_db_thor_act.c',
+ 'ulp_template_db_thor_class.c')
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index ce878d8e02..c626fc64f5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Aug 25 14:37:06 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -16,98 +14,550 @@
*/
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_0000] = 1,
- [BNXT_ULP_ACT_HID_0001] = 2,
- [BNXT_ULP_ACT_HID_0400] = 3,
- [BNXT_ULP_ACT_HID_01ab] = 4,
- [BNXT_ULP_ACT_HID_0010] = 5,
- [BNXT_ULP_ACT_HID_05ab] = 6,
- [BNXT_ULP_ACT_HID_01bb] = 7,
- [BNXT_ULP_ACT_HID_0002] = 8,
- [BNXT_ULP_ACT_HID_0003] = 9,
- [BNXT_ULP_ACT_HID_0402] = 10,
- [BNXT_ULP_ACT_HID_01ad] = 11,
- [BNXT_ULP_ACT_HID_0012] = 12,
- [BNXT_ULP_ACT_HID_05ad] = 13,
- [BNXT_ULP_ACT_HID_01bd] = 14,
- [BNXT_ULP_ACT_HID_0613] = 15,
- [BNXT_ULP_ACT_HID_02a9] = 16,
- [BNXT_ULP_ACT_HID_0054] = 17,
- [BNXT_ULP_ACT_HID_0622] = 18,
- [BNXT_ULP_ACT_HID_0454] = 19,
- [BNXT_ULP_ACT_HID_0064] = 20,
- [BNXT_ULP_ACT_HID_0614] = 21,
- [BNXT_ULP_ACT_HID_0615] = 22,
- [BNXT_ULP_ACT_HID_02ab] = 23,
- [BNXT_ULP_ACT_HID_0056] = 24,
- [BNXT_ULP_ACT_HID_0624] = 25,
- [BNXT_ULP_ACT_HID_0456] = 26,
- [BNXT_ULP_ACT_HID_0066] = 27,
- [BNXT_ULP_ACT_HID_048d] = 28,
- [BNXT_ULP_ACT_HID_048f] = 29,
- [BNXT_ULP_ACT_HID_04bc] = 30,
- [BNXT_ULP_ACT_HID_00a9] = 31,
- [BNXT_ULP_ACT_HID_020f] = 32,
- [BNXT_ULP_ACT_HID_0153] = 33,
- [BNXT_ULP_ACT_HID_04a9] = 34,
- [BNXT_ULP_ACT_HID_01fc] = 35,
- [BNXT_ULP_ACT_HID_04be] = 36,
- [BNXT_ULP_ACT_HID_00ab] = 37,
- [BNXT_ULP_ACT_HID_0211] = 38,
- [BNXT_ULP_ACT_HID_0155] = 39,
- [BNXT_ULP_ACT_HID_04ab] = 40,
- [BNXT_ULP_ACT_HID_01fe] = 41,
- [BNXT_ULP_ACT_HID_0667] = 42,
- [BNXT_ULP_ACT_HID_0254] = 43,
- [BNXT_ULP_ACT_HID_03ba] = 44,
- [BNXT_ULP_ACT_HID_02fe] = 45,
- [BNXT_ULP_ACT_HID_0654] = 46,
- [BNXT_ULP_ACT_HID_03a7] = 47,
- [BNXT_ULP_ACT_HID_0669] = 48,
- [BNXT_ULP_ACT_HID_0256] = 49,
- [BNXT_ULP_ACT_HID_03bc] = 50,
- [BNXT_ULP_ACT_HID_0300] = 51,
- [BNXT_ULP_ACT_HID_0656] = 52,
- [BNXT_ULP_ACT_HID_03a9] = 53,
- [BNXT_ULP_ACT_HID_021b] = 54,
- [BNXT_ULP_ACT_HID_021c] = 55,
- [BNXT_ULP_ACT_HID_021e] = 56,
- [BNXT_ULP_ACT_HID_063f] = 57,
- [BNXT_ULP_ACT_HID_0510] = 58,
- [BNXT_ULP_ACT_HID_03c6] = 59,
- [BNXT_ULP_ACT_HID_0082] = 60,
- [BNXT_ULP_ACT_HID_06bb] = 61,
- [BNXT_ULP_ACT_HID_021d] = 62,
- [BNXT_ULP_ACT_HID_0641] = 63,
- [BNXT_ULP_ACT_HID_0512] = 64,
- [BNXT_ULP_ACT_HID_03c8] = 65,
- [BNXT_ULP_ACT_HID_0084] = 66,
- [BNXT_ULP_ACT_HID_06bd] = 67,
- [BNXT_ULP_ACT_HID_06d7] = 68,
- [BNXT_ULP_ACT_HID_02c4] = 69,
- [BNXT_ULP_ACT_HID_042a] = 70,
- [BNXT_ULP_ACT_HID_036e] = 71,
- [BNXT_ULP_ACT_HID_06c4] = 72,
- [BNXT_ULP_ACT_HID_0417] = 73,
- [BNXT_ULP_ACT_HID_06d9] = 74,
- [BNXT_ULP_ACT_HID_02c6] = 75,
- [BNXT_ULP_ACT_HID_042c] = 76,
- [BNXT_ULP_ACT_HID_0370] = 77,
- [BNXT_ULP_ACT_HID_06c6] = 78,
- [BNXT_ULP_ACT_HID_0419] = 79,
- [BNXT_ULP_ACT_HID_0119] = 80,
- [BNXT_ULP_ACT_HID_046f] = 81,
- [BNXT_ULP_ACT_HID_05d5] = 82,
- [BNXT_ULP_ACT_HID_0519] = 83,
- [BNXT_ULP_ACT_HID_0106] = 84,
- [BNXT_ULP_ACT_HID_05c2] = 85,
- [BNXT_ULP_ACT_HID_011b] = 86,
- [BNXT_ULP_ACT_HID_0471] = 87,
- [BNXT_ULP_ACT_HID_05d7] = 88,
- [BNXT_ULP_ACT_HID_051b] = 89,
- [BNXT_ULP_ACT_HID_0108] = 90,
- [BNXT_ULP_ACT_HID_05c4] = 91,
- [BNXT_ULP_ACT_HID_00a2] = 92,
- [BNXT_ULP_ACT_HID_00a4] = 93
+ [BNXT_ULP_ACT_HID_0008] = 2,
+ [BNXT_ULP_ACT_HID_2000] = 3,
+ [BNXT_ULP_ACT_HID_1988] = 4,
+ [BNXT_ULP_ACT_HID_0080] = 5,
+ [BNXT_ULP_ACT_HID_3988] = 6,
+ [BNXT_ULP_ACT_HID_1a08] = 7,
+ [BNXT_ULP_ACT_HID_0010] = 8,
+ [BNXT_ULP_ACT_HID_0040] = 9,
+ [BNXT_ULP_ACT_HID_0050] = 10,
+ [BNXT_ULP_ACT_HID_0018] = 11,
+ [BNXT_ULP_ACT_HID_2010] = 12,
+ [BNXT_ULP_ACT_HID_1998] = 13,
+ [BNXT_ULP_ACT_HID_0090] = 14,
+ [BNXT_ULP_ACT_HID_3998] = 15,
+ [BNXT_ULP_ACT_HID_1a18] = 16,
+ [BNXT_ULP_ACT_HID_32ea] = 17,
+ [BNXT_ULP_ACT_HID_32f2] = 18,
+ [BNXT_ULP_ACT_HID_52ea] = 19,
+ [BNXT_ULP_ACT_HID_4c72] = 20,
+ [BNXT_ULP_ACT_HID_336a] = 21,
+ [BNXT_ULP_ACT_HID_6c72] = 22,
+ [BNXT_ULP_ACT_HID_4cf2] = 23,
+ [BNXT_ULP_ACT_HID_32fa] = 24,
+ [BNXT_ULP_ACT_HID_3302] = 25,
+ [BNXT_ULP_ACT_HID_52fa] = 26,
+ [BNXT_ULP_ACT_HID_4c82] = 27,
+ [BNXT_ULP_ACT_HID_337a] = 28,
+ [BNXT_ULP_ACT_HID_6c82] = 29,
+ [BNXT_ULP_ACT_HID_4d02] = 30,
+ [BNXT_ULP_ACT_HID_0808] = 31,
+ [BNXT_ULP_ACT_HID_1008] = 32,
+ [BNXT_ULP_ACT_HID_1808] = 33,
+ [BNXT_ULP_ACT_HID_0818] = 34,
+ [BNXT_ULP_ACT_HID_1018] = 35,
+ [BNXT_ULP_ACT_HID_1818] = 36,
+ [BNXT_ULP_ACT_HID_0880] = 37,
+ [BNXT_ULP_ACT_HID_1080] = 38,
+ [BNXT_ULP_ACT_HID_1880] = 39,
+ [BNXT_ULP_ACT_HID_0890] = 40,
+ [BNXT_ULP_ACT_HID_1090] = 41,
+ [BNXT_ULP_ACT_HID_1890] = 42,
+ [BNXT_ULP_ACT_HID_3af2] = 43,
+ [BNXT_ULP_ACT_HID_42f2] = 44,
+ [BNXT_ULP_ACT_HID_4af2] = 45,
+ [BNXT_ULP_ACT_HID_3b02] = 46,
+ [BNXT_ULP_ACT_HID_4302] = 47,
+ [BNXT_ULP_ACT_HID_4b02] = 48,
+ [BNXT_ULP_ACT_HID_3b6a] = 49,
+ [BNXT_ULP_ACT_HID_436a] = 50,
+ [BNXT_ULP_ACT_HID_4b6a] = 51,
+ [BNXT_ULP_ACT_HID_3b7a] = 52,
+ [BNXT_ULP_ACT_HID_437a] = 53,
+ [BNXT_ULP_ACT_HID_4b7a] = 54,
+ [BNXT_ULP_ACT_HID_640d] = 55,
+ [BNXT_ULP_ACT_HID_641d] = 56,
+ [BNXT_ULP_ACT_HID_071a] = 57,
+ [BNXT_ULP_ACT_HID_0800] = 58,
+ [BNXT_ULP_ACT_HID_1000] = 59,
+ [BNXT_ULP_ACT_HID_1800] = 60,
+ [BNXT_ULP_ACT_HID_0810] = 61,
+ [BNXT_ULP_ACT_HID_1010] = 62,
+ [BNXT_ULP_ACT_HID_1810] = 63,
+ [BNXT_ULP_ACT_HID_1110] = 64,
+ [BNXT_ULP_ACT_HID_4420] = 65,
+ [BNXT_ULP_ACT_HID_2220] = 66,
+ [BNXT_ULP_ACT_HID_0c84] = 67,
+ [BNXT_ULP_ACT_HID_3f94] = 68,
+ [BNXT_ULP_ACT_HID_3330] = 69,
+ [BNXT_ULP_ACT_HID_50a4] = 70,
+ [BNXT_ULP_ACT_HID_1910] = 71,
+ [BNXT_ULP_ACT_HID_4c20] = 72,
+ [BNXT_ULP_ACT_HID_2a20] = 73,
+ [BNXT_ULP_ACT_HID_1484] = 74,
+ [BNXT_ULP_ACT_HID_4794] = 75,
+ [BNXT_ULP_ACT_HID_3b30] = 76,
+ [BNXT_ULP_ACT_HID_58a4] = 77,
+ [BNXT_ULP_ACT_HID_2110] = 78,
+ [BNXT_ULP_ACT_HID_5420] = 79,
+ [BNXT_ULP_ACT_HID_3220] = 80,
+ [BNXT_ULP_ACT_HID_1c84] = 81,
+ [BNXT_ULP_ACT_HID_4f94] = 82,
+ [BNXT_ULP_ACT_HID_4330] = 83,
+ [BNXT_ULP_ACT_HID_60a4] = 84,
+ [BNXT_ULP_ACT_HID_2910] = 85,
+ [BNXT_ULP_ACT_HID_5c20] = 86,
+ [BNXT_ULP_ACT_HID_3a20] = 87,
+ [BNXT_ULP_ACT_HID_2484] = 88,
+ [BNXT_ULP_ACT_HID_5794] = 89,
+ [BNXT_ULP_ACT_HID_4b30] = 90,
+ [BNXT_ULP_ACT_HID_68a4] = 91,
+ [BNXT_ULP_ACT_HID_1120] = 92,
+ [BNXT_ULP_ACT_HID_4430] = 93,
+ [BNXT_ULP_ACT_HID_2230] = 94,
+ [BNXT_ULP_ACT_HID_0c94] = 95,
+ [BNXT_ULP_ACT_HID_3fa4] = 96,
+ [BNXT_ULP_ACT_HID_3340] = 97,
+ [BNXT_ULP_ACT_HID_50b4] = 98,
+ [BNXT_ULP_ACT_HID_1920] = 99,
+ [BNXT_ULP_ACT_HID_4c30] = 100,
+ [BNXT_ULP_ACT_HID_2a30] = 101,
+ [BNXT_ULP_ACT_HID_1494] = 102,
+ [BNXT_ULP_ACT_HID_47a4] = 103,
+ [BNXT_ULP_ACT_HID_3b40] = 104,
+ [BNXT_ULP_ACT_HID_58b4] = 105,
+ [BNXT_ULP_ACT_HID_2120] = 106,
+ [BNXT_ULP_ACT_HID_5430] = 107,
+ [BNXT_ULP_ACT_HID_3230] = 108,
+ [BNXT_ULP_ACT_HID_1c94] = 109,
+ [BNXT_ULP_ACT_HID_4fa4] = 110,
+ [BNXT_ULP_ACT_HID_4340] = 111,
+ [BNXT_ULP_ACT_HID_60b4] = 112,
+ [BNXT_ULP_ACT_HID_2920] = 113,
+ [BNXT_ULP_ACT_HID_5c30] = 114,
+ [BNXT_ULP_ACT_HID_3a30] = 115,
+ [BNXT_ULP_ACT_HID_2494] = 116,
+ [BNXT_ULP_ACT_HID_57a4] = 117,
+ [BNXT_ULP_ACT_HID_4b40] = 118,
+ [BNXT_ULP_ACT_HID_68b4] = 119,
+ [BNXT_ULP_ACT_HID_2a98] = 120,
+ [BNXT_ULP_ACT_HID_5da8] = 121,
+ [BNXT_ULP_ACT_HID_3ba8] = 122,
+ [BNXT_ULP_ACT_HID_260c] = 123,
+ [BNXT_ULP_ACT_HID_591c] = 124,
+ [BNXT_ULP_ACT_HID_6a2c] = 125,
+ [BNXT_ULP_ACT_HID_2aa8] = 126,
+ [BNXT_ULP_ACT_HID_5db8] = 127,
+ [BNXT_ULP_ACT_HID_3bb8] = 128,
+ [BNXT_ULP_ACT_HID_261c] = 129,
+ [BNXT_ULP_ACT_HID_592c] = 130,
+ [BNXT_ULP_ACT_HID_6a3c] = 131,
+ [BNXT_ULP_ACT_HID_3298] = 132,
+ [BNXT_ULP_ACT_HID_65a8] = 133,
+ [BNXT_ULP_ACT_HID_43a8] = 134,
+ [BNXT_ULP_ACT_HID_2e0c] = 135,
+ [BNXT_ULP_ACT_HID_611c] = 136,
+ [BNXT_ULP_ACT_HID_722c] = 137,
+ [BNXT_ULP_ACT_HID_32a8] = 138,
+ [BNXT_ULP_ACT_HID_65b8] = 139,
+ [BNXT_ULP_ACT_HID_43b8] = 140,
+ [BNXT_ULP_ACT_HID_2e1c] = 141,
+ [BNXT_ULP_ACT_HID_612c] = 142,
+ [BNXT_ULP_ACT_HID_723c] = 143,
+ [BNXT_ULP_ACT_HID_3a98] = 144,
+ [BNXT_ULP_ACT_HID_6da8] = 145,
+ [BNXT_ULP_ACT_HID_4ba8] = 146,
+ [BNXT_ULP_ACT_HID_360c] = 147,
+ [BNXT_ULP_ACT_HID_691c] = 148,
+ [BNXT_ULP_ACT_HID_7a2c] = 149,
+ [BNXT_ULP_ACT_HID_3aa8] = 150,
+ [BNXT_ULP_ACT_HID_6db8] = 151,
+ [BNXT_ULP_ACT_HID_4bb8] = 152,
+ [BNXT_ULP_ACT_HID_361c] = 153,
+ [BNXT_ULP_ACT_HID_692c] = 154,
+ [BNXT_ULP_ACT_HID_7a3c] = 155,
+ [BNXT_ULP_ACT_HID_4298] = 156,
+ [BNXT_ULP_ACT_HID_75a8] = 157,
+ [BNXT_ULP_ACT_HID_53a8] = 158,
+ [BNXT_ULP_ACT_HID_3e0c] = 159,
+ [BNXT_ULP_ACT_HID_711c] = 160,
+ [BNXT_ULP_ACT_HID_0670] = 161,
+ [BNXT_ULP_ACT_HID_42a8] = 162,
+ [BNXT_ULP_ACT_HID_75b8] = 163,
+ [BNXT_ULP_ACT_HID_53b8] = 164,
+ [BNXT_ULP_ACT_HID_3e1c] = 165,
+ [BNXT_ULP_ACT_HID_712c] = 166,
+ [BNXT_ULP_ACT_HID_0680] = 167,
+ [BNXT_ULP_ACT_HID_3aea] = 168,
+ [BNXT_ULP_ACT_HID_42ea] = 169,
+ [BNXT_ULP_ACT_HID_4aea] = 170,
+ [BNXT_ULP_ACT_HID_3afa] = 171,
+ [BNXT_ULP_ACT_HID_42fa] = 172,
+ [BNXT_ULP_ACT_HID_4afa] = 173,
+ [BNXT_ULP_ACT_HID_43fa] = 174,
+ [BNXT_ULP_ACT_HID_770a] = 175,
+ [BNXT_ULP_ACT_HID_550a] = 176,
+ [BNXT_ULP_ACT_HID_3f6e] = 177,
+ [BNXT_ULP_ACT_HID_727e] = 178,
+ [BNXT_ULP_ACT_HID_661a] = 179,
+ [BNXT_ULP_ACT_HID_07d2] = 180,
+ [BNXT_ULP_ACT_HID_4bfa] = 181,
+ [BNXT_ULP_ACT_HID_034e] = 182,
+ [BNXT_ULP_ACT_HID_5d0a] = 183,
+ [BNXT_ULP_ACT_HID_476e] = 184,
+ [BNXT_ULP_ACT_HID_7a7e] = 185,
+ [BNXT_ULP_ACT_HID_6e1a] = 186,
+ [BNXT_ULP_ACT_HID_0fd2] = 187,
+ [BNXT_ULP_ACT_HID_53fa] = 188,
+ [BNXT_ULP_ACT_HID_0b4e] = 189,
+ [BNXT_ULP_ACT_HID_650a] = 190,
+ [BNXT_ULP_ACT_HID_4f6e] = 191,
+ [BNXT_ULP_ACT_HID_06c2] = 192,
+ [BNXT_ULP_ACT_HID_761a] = 193,
+ [BNXT_ULP_ACT_HID_17d2] = 194,
+ [BNXT_ULP_ACT_HID_5bfa] = 195,
+ [BNXT_ULP_ACT_HID_134e] = 196,
+ [BNXT_ULP_ACT_HID_6d0a] = 197,
+ [BNXT_ULP_ACT_HID_576e] = 198,
+ [BNXT_ULP_ACT_HID_0ec2] = 199,
+ [BNXT_ULP_ACT_HID_025e] = 200,
+ [BNXT_ULP_ACT_HID_1fd2] = 201,
+ [BNXT_ULP_ACT_HID_440a] = 202,
+ [BNXT_ULP_ACT_HID_771a] = 203,
+ [BNXT_ULP_ACT_HID_551a] = 204,
+ [BNXT_ULP_ACT_HID_3f7e] = 205,
+ [BNXT_ULP_ACT_HID_728e] = 206,
+ [BNXT_ULP_ACT_HID_662a] = 207,
+ [BNXT_ULP_ACT_HID_07e2] = 208,
+ [BNXT_ULP_ACT_HID_4c0a] = 209,
+ [BNXT_ULP_ACT_HID_035e] = 210,
+ [BNXT_ULP_ACT_HID_5d1a] = 211,
+ [BNXT_ULP_ACT_HID_477e] = 212,
+ [BNXT_ULP_ACT_HID_7a8e] = 213,
+ [BNXT_ULP_ACT_HID_6e2a] = 214,
+ [BNXT_ULP_ACT_HID_0fe2] = 215,
+ [BNXT_ULP_ACT_HID_540a] = 216,
+ [BNXT_ULP_ACT_HID_0b5e] = 217,
+ [BNXT_ULP_ACT_HID_651a] = 218,
+ [BNXT_ULP_ACT_HID_4f7e] = 219,
+ [BNXT_ULP_ACT_HID_06d2] = 220,
+ [BNXT_ULP_ACT_HID_762a] = 221,
+ [BNXT_ULP_ACT_HID_17e2] = 222,
+ [BNXT_ULP_ACT_HID_5c0a] = 223,
+ [BNXT_ULP_ACT_HID_135e] = 224,
+ [BNXT_ULP_ACT_HID_6d1a] = 225,
+ [BNXT_ULP_ACT_HID_577e] = 226,
+ [BNXT_ULP_ACT_HID_0ed2] = 227,
+ [BNXT_ULP_ACT_HID_026e] = 228,
+ [BNXT_ULP_ACT_HID_1fe2] = 229,
+ [BNXT_ULP_ACT_HID_5d82] = 230,
+ [BNXT_ULP_ACT_HID_14d6] = 231,
+ [BNXT_ULP_ACT_HID_6e92] = 232,
+ [BNXT_ULP_ACT_HID_58f6] = 233,
+ [BNXT_ULP_ACT_HID_104a] = 234,
+ [BNXT_ULP_ACT_HID_215a] = 235,
+ [BNXT_ULP_ACT_HID_5d92] = 236,
+ [BNXT_ULP_ACT_HID_14e6] = 237,
+ [BNXT_ULP_ACT_HID_6ea2] = 238,
+ [BNXT_ULP_ACT_HID_5906] = 239,
+ [BNXT_ULP_ACT_HID_105a] = 240,
+ [BNXT_ULP_ACT_HID_216a] = 241,
+ [BNXT_ULP_ACT_HID_6582] = 242,
+ [BNXT_ULP_ACT_HID_1cd6] = 243,
+ [BNXT_ULP_ACT_HID_7692] = 244,
+ [BNXT_ULP_ACT_HID_60f6] = 245,
+ [BNXT_ULP_ACT_HID_184a] = 246,
+ [BNXT_ULP_ACT_HID_295a] = 247,
+ [BNXT_ULP_ACT_HID_6592] = 248,
+ [BNXT_ULP_ACT_HID_1ce6] = 249,
+ [BNXT_ULP_ACT_HID_76a2] = 250,
+ [BNXT_ULP_ACT_HID_6106] = 251,
+ [BNXT_ULP_ACT_HID_185a] = 252,
+ [BNXT_ULP_ACT_HID_296a] = 253,
+ [BNXT_ULP_ACT_HID_6d82] = 254,
+ [BNXT_ULP_ACT_HID_24d6] = 255,
+ [BNXT_ULP_ACT_HID_02d6] = 256,
+ [BNXT_ULP_ACT_HID_68f6] = 257,
+ [BNXT_ULP_ACT_HID_204a] = 258,
+ [BNXT_ULP_ACT_HID_315a] = 259,
+ [BNXT_ULP_ACT_HID_6d92] = 260,
+ [BNXT_ULP_ACT_HID_24e6] = 261,
+ [BNXT_ULP_ACT_HID_02e6] = 262,
+ [BNXT_ULP_ACT_HID_6906] = 263,
+ [BNXT_ULP_ACT_HID_205a] = 264,
+ [BNXT_ULP_ACT_HID_316a] = 265,
+ [BNXT_ULP_ACT_HID_7582] = 266,
+ [BNXT_ULP_ACT_HID_2cd6] = 267,
+ [BNXT_ULP_ACT_HID_0ad6] = 268,
+ [BNXT_ULP_ACT_HID_70f6] = 269,
+ [BNXT_ULP_ACT_HID_284a] = 270,
+ [BNXT_ULP_ACT_HID_395a] = 271,
+ [BNXT_ULP_ACT_HID_7592] = 272,
+ [BNXT_ULP_ACT_HID_2ce6] = 273,
+ [BNXT_ULP_ACT_HID_0ae6] = 274,
+ [BNXT_ULP_ACT_HID_7106] = 275,
+ [BNXT_ULP_ACT_HID_285a] = 276,
+ [BNXT_ULP_ACT_HID_396a] = 277,
+ [BNXT_ULP_ACT_HID_0020] = 278,
+ [BNXT_ULP_ACT_HID_0030] = 279,
+ [BNXT_ULP_ACT_HID_65d4] = 280,
+ [BNXT_ULP_ACT_HID_65e4] = 281,
+ [BNXT_ULP_ACT_HID_330a] = 282,
+ [BNXT_ULP_ACT_HID_331a] = 283,
+ [BNXT_ULP_ACT_HID_1cfe] = 284,
+ [BNXT_ULP_ACT_HID_1d0e] = 285,
+ [BNXT_ULP_ACT_HID_1474] = 286,
+ [BNXT_ULP_ACT_HID_4838] = 287,
+ [BNXT_ULP_ACT_HID_6458] = 288,
+ [BNXT_ULP_ACT_HID_1c68] = 289,
+ [BNXT_ULP_ACT_HID_6c34] = 290,
+ [BNXT_ULP_ACT_HID_5d08] = 291,
+ [BNXT_ULP_ACT_HID_5d10] = 292,
+ [BNXT_ULP_ACT_HID_5d20] = 293,
+ [BNXT_ULP_ACT_HID_2e18] = 294,
+ [BNXT_ULP_ACT_HID_29d4] = 295,
+ [BNXT_ULP_ACT_HID_7690] = 296,
+ [BNXT_ULP_ACT_HID_47a0] = 297,
+ [BNXT_ULP_ACT_HID_435c] = 298,
+ [BNXT_ULP_ACT_HID_5d18] = 299,
+ [BNXT_ULP_ACT_HID_2e28] = 300,
+ [BNXT_ULP_ACT_HID_29e4] = 301,
+ [BNXT_ULP_ACT_HID_76a0] = 302,
+ [BNXT_ULP_ACT_HID_47b0] = 303,
+ [BNXT_ULP_ACT_HID_436c] = 304,
+ [BNXT_ULP_ACT_HID_1436] = 305,
+ [BNXT_ULP_ACT_HID_143e] = 306,
+ [BNXT_ULP_ACT_HID_144e] = 307,
+ [BNXT_ULP_ACT_HID_6102] = 308,
+ [BNXT_ULP_ACT_HID_5cbe] = 309,
+ [BNXT_ULP_ACT_HID_2dbe] = 310,
+ [BNXT_ULP_ACT_HID_7a8a] = 311,
+ [BNXT_ULP_ACT_HID_7646] = 312,
+ [BNXT_ULP_ACT_HID_1446] = 313,
+ [BNXT_ULP_ACT_HID_6112] = 314,
+ [BNXT_ULP_ACT_HID_5cce] = 315,
+ [BNXT_ULP_ACT_HID_2dce] = 316,
+ [BNXT_ULP_ACT_HID_7a9a] = 317,
+ [BNXT_ULP_ACT_HID_7656] = 318,
+ [BNXT_ULP_ACT_HID_6508] = 319,
+ [BNXT_ULP_ACT_HID_6d08] = 320,
+ [BNXT_ULP_ACT_HID_7508] = 321,
+ [BNXT_ULP_ACT_HID_6518] = 322,
+ [BNXT_ULP_ACT_HID_6d18] = 323,
+ [BNXT_ULP_ACT_HID_7518] = 324,
+ [BNXT_ULP_ACT_HID_6e18] = 325,
+ [BNXT_ULP_ACT_HID_256c] = 326,
+ [BNXT_ULP_ACT_HID_036c] = 327,
+ [BNXT_ULP_ACT_HID_698c] = 328,
+ [BNXT_ULP_ACT_HID_20e0] = 329,
+ [BNXT_ULP_ACT_HID_31f0] = 330,
+ [BNXT_ULP_ACT_HID_7618] = 331,
+ [BNXT_ULP_ACT_HID_2d6c] = 332,
+ [BNXT_ULP_ACT_HID_0b6c] = 333,
+ [BNXT_ULP_ACT_HID_718c] = 334,
+ [BNXT_ULP_ACT_HID_28e0] = 335,
+ [BNXT_ULP_ACT_HID_39f0] = 336,
+ [BNXT_ULP_ACT_HID_025c] = 337,
+ [BNXT_ULP_ACT_HID_356c] = 338,
+ [BNXT_ULP_ACT_HID_136c] = 339,
+ [BNXT_ULP_ACT_HID_798c] = 340,
+ [BNXT_ULP_ACT_HID_30e0] = 341,
+ [BNXT_ULP_ACT_HID_41f0] = 342,
+ [BNXT_ULP_ACT_HID_0a5c] = 343,
+ [BNXT_ULP_ACT_HID_3d6c] = 344,
+ [BNXT_ULP_ACT_HID_1b6c] = 345,
+ [BNXT_ULP_ACT_HID_05d0] = 346,
+ [BNXT_ULP_ACT_HID_38e0] = 347,
+ [BNXT_ULP_ACT_HID_49f0] = 348,
+ [BNXT_ULP_ACT_HID_6e28] = 349,
+ [BNXT_ULP_ACT_HID_257c] = 350,
+ [BNXT_ULP_ACT_HID_037c] = 351,
+ [BNXT_ULP_ACT_HID_699c] = 352,
+ [BNXT_ULP_ACT_HID_20f0] = 353,
+ [BNXT_ULP_ACT_HID_3200] = 354,
+ [BNXT_ULP_ACT_HID_7628] = 355,
+ [BNXT_ULP_ACT_HID_2d7c] = 356,
+ [BNXT_ULP_ACT_HID_0b7c] = 357,
+ [BNXT_ULP_ACT_HID_719c] = 358,
+ [BNXT_ULP_ACT_HID_28f0] = 359,
+ [BNXT_ULP_ACT_HID_3a00] = 360,
+ [BNXT_ULP_ACT_HID_026c] = 361,
+ [BNXT_ULP_ACT_HID_357c] = 362,
+ [BNXT_ULP_ACT_HID_137c] = 363,
+ [BNXT_ULP_ACT_HID_799c] = 364,
+ [BNXT_ULP_ACT_HID_30f0] = 365,
+ [BNXT_ULP_ACT_HID_4200] = 366,
+ [BNXT_ULP_ACT_HID_0a6c] = 367,
+ [BNXT_ULP_ACT_HID_3d7c] = 368,
+ [BNXT_ULP_ACT_HID_1b7c] = 369,
+ [BNXT_ULP_ACT_HID_05e0] = 370,
+ [BNXT_ULP_ACT_HID_38f0] = 371,
+ [BNXT_ULP_ACT_HID_4a00] = 372,
+ [BNXT_ULP_ACT_HID_0be4] = 373,
+ [BNXT_ULP_ACT_HID_3ef4] = 374,
+ [BNXT_ULP_ACT_HID_1cf4] = 375,
+ [BNXT_ULP_ACT_HID_0758] = 376,
+ [BNXT_ULP_ACT_HID_3a68] = 377,
+ [BNXT_ULP_ACT_HID_4b78] = 378,
+ [BNXT_ULP_ACT_HID_0bf4] = 379,
+ [BNXT_ULP_ACT_HID_3f04] = 380,
+ [BNXT_ULP_ACT_HID_1d04] = 381,
+ [BNXT_ULP_ACT_HID_0768] = 382,
+ [BNXT_ULP_ACT_HID_3a78] = 383,
+ [BNXT_ULP_ACT_HID_4b88] = 384,
+ [BNXT_ULP_ACT_HID_46f4] = 385,
+ [BNXT_ULP_ACT_HID_24f4] = 386,
+ [BNXT_ULP_ACT_HID_0f58] = 387,
+ [BNXT_ULP_ACT_HID_13e4] = 388,
+ [BNXT_ULP_ACT_HID_4268] = 389,
+ [BNXT_ULP_ACT_HID_5378] = 390,
+ [BNXT_ULP_ACT_HID_13f4] = 391,
+ [BNXT_ULP_ACT_HID_4704] = 392,
+ [BNXT_ULP_ACT_HID_2504] = 393,
+ [BNXT_ULP_ACT_HID_0f68] = 394,
+ [BNXT_ULP_ACT_HID_4278] = 395,
+ [BNXT_ULP_ACT_HID_5388] = 396,
+ [BNXT_ULP_ACT_HID_1be4] = 397,
+ [BNXT_ULP_ACT_HID_4ef4] = 398,
+ [BNXT_ULP_ACT_HID_2cf4] = 399,
+ [BNXT_ULP_ACT_HID_1758] = 400,
+ [BNXT_ULP_ACT_HID_4a68] = 401,
+ [BNXT_ULP_ACT_HID_5b78] = 402,
+ [BNXT_ULP_ACT_HID_1bf4] = 403,
+ [BNXT_ULP_ACT_HID_4f04] = 404,
+ [BNXT_ULP_ACT_HID_2d04] = 405,
+ [BNXT_ULP_ACT_HID_1768] = 406,
+ [BNXT_ULP_ACT_HID_4a78] = 407,
+ [BNXT_ULP_ACT_HID_5b88] = 408,
+ [BNXT_ULP_ACT_HID_23e4] = 409,
+ [BNXT_ULP_ACT_HID_56f4] = 410,
+ [BNXT_ULP_ACT_HID_34f4] = 411,
+ [BNXT_ULP_ACT_HID_1f58] = 412,
+ [BNXT_ULP_ACT_HID_5268] = 413,
+ [BNXT_ULP_ACT_HID_6378] = 414,
+ [BNXT_ULP_ACT_HID_23f4] = 415,
+ [BNXT_ULP_ACT_HID_5704] = 416,
+ [BNXT_ULP_ACT_HID_3504] = 417,
+ [BNXT_ULP_ACT_HID_1f68] = 418,
+ [BNXT_ULP_ACT_HID_5278] = 419,
+ [BNXT_ULP_ACT_HID_6388] = 420,
+ [BNXT_ULP_ACT_HID_1c36] = 421,
+ [BNXT_ULP_ACT_HID_2436] = 422,
+ [BNXT_ULP_ACT_HID_2c36] = 423,
+ [BNXT_ULP_ACT_HID_1c46] = 424,
+ [BNXT_ULP_ACT_HID_2446] = 425,
+ [BNXT_ULP_ACT_HID_2c46] = 426,
+ [BNXT_ULP_ACT_HID_2546] = 427,
+ [BNXT_ULP_ACT_HID_5856] = 428,
+ [BNXT_ULP_ACT_HID_3656] = 429,
+ [BNXT_ULP_ACT_HID_20ba] = 430,
+ [BNXT_ULP_ACT_HID_53ca] = 431,
+ [BNXT_ULP_ACT_HID_64da] = 432,
+ [BNXT_ULP_ACT_HID_2d46] = 433,
+ [BNXT_ULP_ACT_HID_6056] = 434,
+ [BNXT_ULP_ACT_HID_3e56] = 435,
+ [BNXT_ULP_ACT_HID_28ba] = 436,
+ [BNXT_ULP_ACT_HID_5bca] = 437,
+ [BNXT_ULP_ACT_HID_6cda] = 438,
+ [BNXT_ULP_ACT_HID_3546] = 439,
+ [BNXT_ULP_ACT_HID_6856] = 440,
+ [BNXT_ULP_ACT_HID_4656] = 441,
+ [BNXT_ULP_ACT_HID_30ba] = 442,
+ [BNXT_ULP_ACT_HID_63ca] = 443,
+ [BNXT_ULP_ACT_HID_74da] = 444,
+ [BNXT_ULP_ACT_HID_3d46] = 445,
+ [BNXT_ULP_ACT_HID_7056] = 446,
+ [BNXT_ULP_ACT_HID_4e56] = 447,
+ [BNXT_ULP_ACT_HID_38ba] = 448,
+ [BNXT_ULP_ACT_HID_6bca] = 449,
+ [BNXT_ULP_ACT_HID_011e] = 450,
+ [BNXT_ULP_ACT_HID_2556] = 451,
+ [BNXT_ULP_ACT_HID_5866] = 452,
+ [BNXT_ULP_ACT_HID_3666] = 453,
+ [BNXT_ULP_ACT_HID_20ca] = 454,
+ [BNXT_ULP_ACT_HID_53da] = 455,
+ [BNXT_ULP_ACT_HID_64ea] = 456,
+ [BNXT_ULP_ACT_HID_2d56] = 457,
+ [BNXT_ULP_ACT_HID_6066] = 458,
+ [BNXT_ULP_ACT_HID_3e66] = 459,
+ [BNXT_ULP_ACT_HID_28ca] = 460,
+ [BNXT_ULP_ACT_HID_5bda] = 461,
+ [BNXT_ULP_ACT_HID_6cea] = 462,
+ [BNXT_ULP_ACT_HID_3556] = 463,
+ [BNXT_ULP_ACT_HID_6866] = 464,
+ [BNXT_ULP_ACT_HID_4666] = 465,
+ [BNXT_ULP_ACT_HID_30ca] = 466,
+ [BNXT_ULP_ACT_HID_63da] = 467,
+ [BNXT_ULP_ACT_HID_74ea] = 468,
+ [BNXT_ULP_ACT_HID_3d56] = 469,
+ [BNXT_ULP_ACT_HID_7066] = 470,
+ [BNXT_ULP_ACT_HID_4e66] = 471,
+ [BNXT_ULP_ACT_HID_38ca] = 472,
+ [BNXT_ULP_ACT_HID_6bda] = 473,
+ [BNXT_ULP_ACT_HID_012e] = 474,
+ [BNXT_ULP_ACT_HID_3ece] = 475,
+ [BNXT_ULP_ACT_HID_71de] = 476,
+ [BNXT_ULP_ACT_HID_4fde] = 477,
+ [BNXT_ULP_ACT_HID_3a42] = 478,
+ [BNXT_ULP_ACT_HID_6d52] = 479,
+ [BNXT_ULP_ACT_HID_02a6] = 480,
+ [BNXT_ULP_ACT_HID_3ede] = 481,
+ [BNXT_ULP_ACT_HID_71ee] = 482,
+ [BNXT_ULP_ACT_HID_4fee] = 483,
+ [BNXT_ULP_ACT_HID_3a52] = 484,
+ [BNXT_ULP_ACT_HID_6d62] = 485,
+ [BNXT_ULP_ACT_HID_02b6] = 486,
+ [BNXT_ULP_ACT_HID_79de] = 487,
+ [BNXT_ULP_ACT_HID_57de] = 488,
+ [BNXT_ULP_ACT_HID_4242] = 489,
+ [BNXT_ULP_ACT_HID_46ce] = 490,
+ [BNXT_ULP_ACT_HID_7552] = 491,
+ [BNXT_ULP_ACT_HID_0aa6] = 492,
+ [BNXT_ULP_ACT_HID_46de] = 493,
+ [BNXT_ULP_ACT_HID_79ee] = 494,
+ [BNXT_ULP_ACT_HID_57ee] = 495,
+ [BNXT_ULP_ACT_HID_4252] = 496,
+ [BNXT_ULP_ACT_HID_7562] = 497,
+ [BNXT_ULP_ACT_HID_0ab6] = 498,
+ [BNXT_ULP_ACT_HID_4ece] = 499,
+ [BNXT_ULP_ACT_HID_0622] = 500,
+ [BNXT_ULP_ACT_HID_5fde] = 501,
+ [BNXT_ULP_ACT_HID_4a42] = 502,
+ [BNXT_ULP_ACT_HID_0196] = 503,
+ [BNXT_ULP_ACT_HID_12a6] = 504,
+ [BNXT_ULP_ACT_HID_4ede] = 505,
+ [BNXT_ULP_ACT_HID_0632] = 506,
+ [BNXT_ULP_ACT_HID_5fee] = 507,
+ [BNXT_ULP_ACT_HID_4a52] = 508,
+ [BNXT_ULP_ACT_HID_01a6] = 509,
+ [BNXT_ULP_ACT_HID_12b6] = 510,
+ [BNXT_ULP_ACT_HID_56ce] = 511,
+ [BNXT_ULP_ACT_HID_0e22] = 512,
+ [BNXT_ULP_ACT_HID_67de] = 513,
+ [BNXT_ULP_ACT_HID_5242] = 514,
+ [BNXT_ULP_ACT_HID_0996] = 515,
+ [BNXT_ULP_ACT_HID_1aa6] = 516,
+ [BNXT_ULP_ACT_HID_56de] = 517,
+ [BNXT_ULP_ACT_HID_0e32] = 518,
+ [BNXT_ULP_ACT_HID_67ee] = 519,
+ [BNXT_ULP_ACT_HID_5252] = 520,
+ [BNXT_ULP_ACT_HID_09a6] = 521,
+ [BNXT_ULP_ACT_HID_1ab6] = 522,
+ [BNXT_ULP_ACT_HID_31d0] = 523,
+ [BNXT_ULP_ACT_HID_31e0] = 524,
+ [BNXT_ULP_ACT_HID_39d0] = 525,
+ [BNXT_ULP_ACT_HID_39e0] = 526,
+ [BNXT_ULP_ACT_HID_41d0] = 527,
+ [BNXT_ULP_ACT_HID_41e0] = 528,
+ [BNXT_ULP_ACT_HID_49d0] = 529,
+ [BNXT_ULP_ACT_HID_49e0] = 530,
+ [BNXT_ULP_ACT_HID_64ba] = 531,
+ [BNXT_ULP_ACT_HID_64ca] = 532,
+ [BNXT_ULP_ACT_HID_6cba] = 533,
+ [BNXT_ULP_ACT_HID_6cca] = 534,
+ [BNXT_ULP_ACT_HID_74ba] = 535,
+ [BNXT_ULP_ACT_HID_74ca] = 536,
+ [BNXT_ULP_ACT_HID_00fe] = 537,
+ [BNXT_ULP_ACT_HID_010e] = 538,
+ [BNXT_ULP_ACT_HID_331c] = 539,
+ [BNXT_ULP_ACT_HID_332c] = 540,
+ [BNXT_ULP_ACT_HID_6706] = 541,
+ [BNXT_ULP_ACT_HID_6716] = 542,
+ [BNXT_ULP_ACT_HID_1b6d] = 543,
+ [BNXT_ULP_ACT_HID_1b7d] = 544,
+ [BNXT_ULP_ACT_HID_641a] = 545
};
/* Array for the act matcher list */
@@ -121,7 +571,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[2] = {
- .act_hid = BNXT_ULP_ACT_HID_0001,
+ .act_hid = BNXT_ULP_ACT_HID_0008,
.act_pattern_id = 1,
.app_sig = 0,
.act_sig = { .bits =
@@ -130,7 +580,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[3] = {
- .act_hid = BNXT_ULP_ACT_HID_0400,
+ .act_hid = BNXT_ULP_ACT_HID_2000,
.act_pattern_id = 2,
.app_sig = 0,
.act_sig = { .bits =
@@ -139,7 +589,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[4] = {
- .act_hid = BNXT_ULP_ACT_HID_01ab,
+ .act_hid = BNXT_ULP_ACT_HID_1988,
.act_pattern_id = 3,
.app_sig = 0,
.act_sig = { .bits =
@@ -148,7 +598,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[5] = {
- .act_hid = BNXT_ULP_ACT_HID_0010,
+ .act_hid = BNXT_ULP_ACT_HID_0080,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
@@ -157,7 +607,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[6] = {
- .act_hid = BNXT_ULP_ACT_HID_05ab,
+ .act_hid = BNXT_ULP_ACT_HID_3988,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
@@ -167,7 +617,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[7] = {
- .act_hid = BNXT_ULP_ACT_HID_01bb,
+ .act_hid = BNXT_ULP_ACT_HID_1a08,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
@@ -177,7 +627,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[8] = {
- .act_hid = BNXT_ULP_ACT_HID_0002,
+ .act_hid = BNXT_ULP_ACT_HID_0010,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
@@ -186,902 +636,6269 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[9] = {
- .act_hid = BNXT_ULP_ACT_HID_0003,
+ .act_hid = BNXT_ULP_ACT_HID_0040,
.act_pattern_id = 8,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_METER |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[10] = {
- .act_hid = BNXT_ULP_ACT_HID_0402,
+ .act_hid = BNXT_ULP_ACT_HID_0050,
.act_pattern_id = 9,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_METER |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[11] = {
- .act_hid = BNXT_ULP_ACT_HID_01ad,
+ .act_hid = BNXT_ULP_ACT_HID_0018,
.act_pattern_id = 10,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[12] = {
- .act_hid = BNXT_ULP_ACT_HID_0012,
+ .act_hid = BNXT_ULP_ACT_HID_2010,
.act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[13] = {
- .act_hid = BNXT_ULP_ACT_HID_05ad,
+ .act_hid = BNXT_ULP_ACT_HID_1998,
.act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[14] = {
- .act_hid = BNXT_ULP_ACT_HID_01bd,
+ .act_hid = BNXT_ULP_ACT_HID_0090,
.act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_VXLAN_DECAP |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[15] = {
- .act_hid = BNXT_ULP_ACT_HID_0613,
+ .act_hid = BNXT_ULP_ACT_HID_3998,
.act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[16] = {
- .act_hid = BNXT_ULP_ACT_HID_02a9,
+ .act_hid = BNXT_ULP_ACT_HID_1a18,
.act_pattern_id = 15,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[17] = {
- .act_hid = BNXT_ULP_ACT_HID_0054,
+ .act_hid = BNXT_ULP_ACT_HID_32ea,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[18] = {
- .act_hid = BNXT_ULP_ACT_HID_0622,
+ .act_hid = BNXT_ULP_ACT_HID_32f2,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[19] = {
- .act_hid = BNXT_ULP_ACT_HID_0454,
+ .act_hid = BNXT_ULP_ACT_HID_52ea,
.act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[20] = {
- .act_hid = BNXT_ULP_ACT_HID_0064,
+ .act_hid = BNXT_ULP_ACT_HID_4c72,
.act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[21] = {
- .act_hid = BNXT_ULP_ACT_HID_0614,
+ .act_hid = BNXT_ULP_ACT_HID_336a,
.act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[22] = {
- .act_hid = BNXT_ULP_ACT_HID_0615,
+ .act_hid = BNXT_ULP_ACT_HID_6c72,
.act_pattern_id = 21,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[23] = {
- .act_hid = BNXT_ULP_ACT_HID_02ab,
+ .act_hid = BNXT_ULP_ACT_HID_4cf2,
.act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[24] = {
- .act_hid = BNXT_ULP_ACT_HID_0056,
+ .act_hid = BNXT_ULP_ACT_HID_32fa,
.act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[25] = {
- .act_hid = BNXT_ULP_ACT_HID_0624,
+ .act_hid = BNXT_ULP_ACT_HID_3302,
.act_pattern_id = 24,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[26] = {
- .act_hid = BNXT_ULP_ACT_HID_0456,
+ .act_hid = BNXT_ULP_ACT_HID_52fa,
.act_pattern_id = 25,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[27] = {
- .act_hid = BNXT_ULP_ACT_HID_0066,
+ .act_hid = BNXT_ULP_ACT_HID_4c82,
.act_pattern_id = 26,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[28] = {
- .act_hid = BNXT_ULP_ACT_HID_048d,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_337a,
+ .act_pattern_id = 27,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED |
- BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 2
+ .act_tid = 1
},
[29] = {
- .act_hid = BNXT_ULP_ACT_HID_048f,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_6c82,
+ .act_pattern_id = 28,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED |
- BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 2
+ .act_tid = 1
},
[30] = {
- .act_hid = BNXT_ULP_ACT_HID_04bc,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_4d02,
+ .act_pattern_id = 29,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[31] = {
- .act_hid = BNXT_ULP_ACT_HID_00a9,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_0808,
+ .act_pattern_id = 30,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[32] = {
- .act_hid = BNXT_ULP_ACT_HID_020f,
- .act_pattern_id = 2,
+ .act_hid = BNXT_ULP_ACT_HID_1008,
+ .act_pattern_id = 31,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[33] = {
- .act_hid = BNXT_ULP_ACT_HID_0153,
- .act_pattern_id = 3,
+ .act_hid = BNXT_ULP_ACT_HID_1808,
+ .act_pattern_id = 32,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[34] = {
- .act_hid = BNXT_ULP_ACT_HID_04a9,
- .act_pattern_id = 4,
+ .act_hid = BNXT_ULP_ACT_HID_0818,
+ .act_pattern_id = 33,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[35] = {
- .act_hid = BNXT_ULP_ACT_HID_01fc,
- .act_pattern_id = 5,
+ .act_hid = BNXT_ULP_ACT_HID_1018,
+ .act_pattern_id = 34,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[36] = {
- .act_hid = BNXT_ULP_ACT_HID_04be,
- .act_pattern_id = 6,
+ .act_hid = BNXT_ULP_ACT_HID_1818,
+ .act_pattern_id = 35,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[37] = {
- .act_hid = BNXT_ULP_ACT_HID_00ab,
- .act_pattern_id = 7,
+ .act_hid = BNXT_ULP_ACT_HID_0880,
+ .act_pattern_id = 36,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[38] = {
- .act_hid = BNXT_ULP_ACT_HID_0211,
- .act_pattern_id = 8,
+ .act_hid = BNXT_ULP_ACT_HID_1080,
+ .act_pattern_id = 37,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[39] = {
- .act_hid = BNXT_ULP_ACT_HID_0155,
- .act_pattern_id = 9,
+ .act_hid = BNXT_ULP_ACT_HID_1880,
+ .act_pattern_id = 38,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[40] = {
- .act_hid = BNXT_ULP_ACT_HID_04ab,
- .act_pattern_id = 10,
+ .act_hid = BNXT_ULP_ACT_HID_0890,
+ .act_pattern_id = 39,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[41] = {
- .act_hid = BNXT_ULP_ACT_HID_01fe,
- .act_pattern_id = 11,
+ .act_hid = BNXT_ULP_ACT_HID_1090,
+ .act_pattern_id = 40,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[42] = {
- .act_hid = BNXT_ULP_ACT_HID_0667,
- .act_pattern_id = 12,
+ .act_hid = BNXT_ULP_ACT_HID_1890,
+ .act_pattern_id = 41,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[43] = {
- .act_hid = BNXT_ULP_ACT_HID_0254,
- .act_pattern_id = 13,
+ .act_hid = BNXT_ULP_ACT_HID_3af2,
+ .act_pattern_id = 42,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[44] = {
- .act_hid = BNXT_ULP_ACT_HID_03ba,
- .act_pattern_id = 14,
+ .act_hid = BNXT_ULP_ACT_HID_42f2,
+ .act_pattern_id = 43,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[45] = {
- .act_hid = BNXT_ULP_ACT_HID_02fe,
- .act_pattern_id = 15,
+ .act_hid = BNXT_ULP_ACT_HID_4af2,
+ .act_pattern_id = 44,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[46] = {
- .act_hid = BNXT_ULP_ACT_HID_0654,
- .act_pattern_id = 16,
+ .act_hid = BNXT_ULP_ACT_HID_3b02,
+ .act_pattern_id = 45,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[47] = {
- .act_hid = BNXT_ULP_ACT_HID_03a7,
- .act_pattern_id = 17,
+ .act_hid = BNXT_ULP_ACT_HID_4302,
+ .act_pattern_id = 46,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[48] = {
- .act_hid = BNXT_ULP_ACT_HID_0669,
- .act_pattern_id = 18,
+ .act_hid = BNXT_ULP_ACT_HID_4b02,
+ .act_pattern_id = 47,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[49] = {
- .act_hid = BNXT_ULP_ACT_HID_0256,
- .act_pattern_id = 19,
+ .act_hid = BNXT_ULP_ACT_HID_3b6a,
+ .act_pattern_id = 48,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[50] = {
- .act_hid = BNXT_ULP_ACT_HID_03bc,
- .act_pattern_id = 20,
+ .act_hid = BNXT_ULP_ACT_HID_436a,
+ .act_pattern_id = 49,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[51] = {
- .act_hid = BNXT_ULP_ACT_HID_0300,
- .act_pattern_id = 21,
+ .act_hid = BNXT_ULP_ACT_HID_4b6a,
+ .act_pattern_id = 50,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[52] = {
- .act_hid = BNXT_ULP_ACT_HID_0656,
- .act_pattern_id = 22,
+ .act_hid = BNXT_ULP_ACT_HID_3b7a,
+ .act_pattern_id = 51,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[53] = {
- .act_hid = BNXT_ULP_ACT_HID_03a9,
- .act_pattern_id = 23,
+ .act_hid = BNXT_ULP_ACT_HID_437a,
+ .act_pattern_id = 52,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[54] = {
- .act_hid = BNXT_ULP_ACT_HID_021b,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_4b7a,
+ .act_pattern_id = 53,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
},
[55] = {
- .act_hid = BNXT_ULP_ACT_HID_021c,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_640d,
+ .act_pattern_id = 0,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DROP |
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [56] = {
+ .act_hid = BNXT_ULP_ACT_HID_641d,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [57] = {
+ .act_hid = BNXT_ULP_ACT_HID_071a,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [58] = {
+ .act_hid = BNXT_ULP_ACT_HID_0800,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [59] = {
+ .act_hid = BNXT_ULP_ACT_HID_1000,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [60] = {
+ .act_hid = BNXT_ULP_ACT_HID_1800,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [61] = {
+ .act_hid = BNXT_ULP_ACT_HID_0810,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [62] = {
+ .act_hid = BNXT_ULP_ACT_HID_1010,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [63] = {
+ .act_hid = BNXT_ULP_ACT_HID_1810,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [64] = {
+ .act_hid = BNXT_ULP_ACT_HID_1110,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [65] = {
+ .act_hid = BNXT_ULP_ACT_HID_4420,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [66] = {
+ .act_hid = BNXT_ULP_ACT_HID_2220,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [67] = {
+ .act_hid = BNXT_ULP_ACT_HID_0c84,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [68] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f94,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [69] = {
+ .act_hid = BNXT_ULP_ACT_HID_3330,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [70] = {
+ .act_hid = BNXT_ULP_ACT_HID_50a4,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [71] = {
+ .act_hid = BNXT_ULP_ACT_HID_1910,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [72] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c20,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [73] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a20,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [74] = {
+ .act_hid = BNXT_ULP_ACT_HID_1484,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [75] = {
+ .act_hid = BNXT_ULP_ACT_HID_4794,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [76] = {
+ .act_hid = BNXT_ULP_ACT_HID_3b30,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [77] = {
+ .act_hid = BNXT_ULP_ACT_HID_58a4,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [78] = {
+ .act_hid = BNXT_ULP_ACT_HID_2110,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [79] = {
+ .act_hid = BNXT_ULP_ACT_HID_5420,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [80] = {
+ .act_hid = BNXT_ULP_ACT_HID_3220,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [81] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c84,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [82] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f94,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [83] = {
+ .act_hid = BNXT_ULP_ACT_HID_4330,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [84] = {
+ .act_hid = BNXT_ULP_ACT_HID_60a4,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [85] = {
+ .act_hid = BNXT_ULP_ACT_HID_2910,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [86] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c20,
+ .act_pattern_id = 28,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [87] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a20,
+ .act_pattern_id = 29,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [88] = {
+ .act_hid = BNXT_ULP_ACT_HID_2484,
+ .act_pattern_id = 30,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [89] = {
+ .act_hid = BNXT_ULP_ACT_HID_5794,
+ .act_pattern_id = 31,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [90] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b30,
+ .act_pattern_id = 32,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [91] = {
+ .act_hid = BNXT_ULP_ACT_HID_68a4,
+ .act_pattern_id = 33,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [92] = {
+ .act_hid = BNXT_ULP_ACT_HID_1120,
+ .act_pattern_id = 34,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [93] = {
+ .act_hid = BNXT_ULP_ACT_HID_4430,
+ .act_pattern_id = 35,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [94] = {
+ .act_hid = BNXT_ULP_ACT_HID_2230,
+ .act_pattern_id = 36,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [95] = {
+ .act_hid = BNXT_ULP_ACT_HID_0c94,
+ .act_pattern_id = 37,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [96] = {
+ .act_hid = BNXT_ULP_ACT_HID_3fa4,
+ .act_pattern_id = 38,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [97] = {
+ .act_hid = BNXT_ULP_ACT_HID_3340,
+ .act_pattern_id = 39,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [98] = {
+ .act_hid = BNXT_ULP_ACT_HID_50b4,
+ .act_pattern_id = 40,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [99] = {
+ .act_hid = BNXT_ULP_ACT_HID_1920,
+ .act_pattern_id = 41,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [100] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c30,
+ .act_pattern_id = 42,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [101] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a30,
+ .act_pattern_id = 43,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [102] = {
+ .act_hid = BNXT_ULP_ACT_HID_1494,
+ .act_pattern_id = 44,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [103] = {
+ .act_hid = BNXT_ULP_ACT_HID_47a4,
+ .act_pattern_id = 45,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [104] = {
+ .act_hid = BNXT_ULP_ACT_HID_3b40,
+ .act_pattern_id = 46,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [105] = {
+ .act_hid = BNXT_ULP_ACT_HID_58b4,
+ .act_pattern_id = 47,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [106] = {
+ .act_hid = BNXT_ULP_ACT_HID_2120,
+ .act_pattern_id = 48,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [107] = {
+ .act_hid = BNXT_ULP_ACT_HID_5430,
+ .act_pattern_id = 49,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [108] = {
+ .act_hid = BNXT_ULP_ACT_HID_3230,
+ .act_pattern_id = 50,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [109] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c94,
+ .act_pattern_id = 51,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [110] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fa4,
+ .act_pattern_id = 52,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [111] = {
+ .act_hid = BNXT_ULP_ACT_HID_4340,
+ .act_pattern_id = 53,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [112] = {
+ .act_hid = BNXT_ULP_ACT_HID_60b4,
+ .act_pattern_id = 54,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [113] = {
+ .act_hid = BNXT_ULP_ACT_HID_2920,
+ .act_pattern_id = 55,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [114] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c30,
+ .act_pattern_id = 56,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [115] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a30,
+ .act_pattern_id = 57,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [116] = {
+ .act_hid = BNXT_ULP_ACT_HID_2494,
+ .act_pattern_id = 58,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [117] = {
+ .act_hid = BNXT_ULP_ACT_HID_57a4,
+ .act_pattern_id = 59,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [118] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b40,
+ .act_pattern_id = 60,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [119] = {
+ .act_hid = BNXT_ULP_ACT_HID_68b4,
+ .act_pattern_id = 61,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [120] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a98,
+ .act_pattern_id = 62,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [121] = {
+ .act_hid = BNXT_ULP_ACT_HID_5da8,
+ .act_pattern_id = 63,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [122] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ba8,
+ .act_pattern_id = 64,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [123] = {
+ .act_hid = BNXT_ULP_ACT_HID_260c,
+ .act_pattern_id = 65,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [124] = {
+ .act_hid = BNXT_ULP_ACT_HID_591c,
+ .act_pattern_id = 66,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [125] = {
+ .act_hid = BNXT_ULP_ACT_HID_6a2c,
+ .act_pattern_id = 67,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [126] = {
+ .act_hid = BNXT_ULP_ACT_HID_2aa8,
+ .act_pattern_id = 68,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [127] = {
+ .act_hid = BNXT_ULP_ACT_HID_5db8,
+ .act_pattern_id = 69,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [128] = {
+ .act_hid = BNXT_ULP_ACT_HID_3bb8,
+ .act_pattern_id = 70,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [129] = {
+ .act_hid = BNXT_ULP_ACT_HID_261c,
+ .act_pattern_id = 71,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [130] = {
+ .act_hid = BNXT_ULP_ACT_HID_592c,
+ .act_pattern_id = 72,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [131] = {
+ .act_hid = BNXT_ULP_ACT_HID_6a3c,
+ .act_pattern_id = 73,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [132] = {
+ .act_hid = BNXT_ULP_ACT_HID_3298,
+ .act_pattern_id = 74,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [133] = {
+ .act_hid = BNXT_ULP_ACT_HID_65a8,
+ .act_pattern_id = 75,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [134] = {
+ .act_hid = BNXT_ULP_ACT_HID_43a8,
+ .act_pattern_id = 76,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [135] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e0c,
+ .act_pattern_id = 77,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [136] = {
+ .act_hid = BNXT_ULP_ACT_HID_611c,
+ .act_pattern_id = 78,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [137] = {
+ .act_hid = BNXT_ULP_ACT_HID_722c,
+ .act_pattern_id = 79,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [138] = {
+ .act_hid = BNXT_ULP_ACT_HID_32a8,
+ .act_pattern_id = 80,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [139] = {
+ .act_hid = BNXT_ULP_ACT_HID_65b8,
+ .act_pattern_id = 81,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [140] = {
+ .act_hid = BNXT_ULP_ACT_HID_43b8,
+ .act_pattern_id = 82,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [141] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e1c,
+ .act_pattern_id = 83,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [142] = {
+ .act_hid = BNXT_ULP_ACT_HID_612c,
+ .act_pattern_id = 84,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [143] = {
+ .act_hid = BNXT_ULP_ACT_HID_723c,
+ .act_pattern_id = 85,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [144] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a98,
+ .act_pattern_id = 86,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [145] = {
+ .act_hid = BNXT_ULP_ACT_HID_6da8,
+ .act_pattern_id = 87,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [146] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ba8,
+ .act_pattern_id = 88,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [147] = {
+ .act_hid = BNXT_ULP_ACT_HID_360c,
+ .act_pattern_id = 89,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [148] = {
+ .act_hid = BNXT_ULP_ACT_HID_691c,
+ .act_pattern_id = 90,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [149] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a2c,
+ .act_pattern_id = 91,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [150] = {
+ .act_hid = BNXT_ULP_ACT_HID_3aa8,
+ .act_pattern_id = 92,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [151] = {
+ .act_hid = BNXT_ULP_ACT_HID_6db8,
+ .act_pattern_id = 93,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [152] = {
+ .act_hid = BNXT_ULP_ACT_HID_4bb8,
+ .act_pattern_id = 94,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [153] = {
+ .act_hid = BNXT_ULP_ACT_HID_361c,
+ .act_pattern_id = 95,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [154] = {
+ .act_hid = BNXT_ULP_ACT_HID_692c,
+ .act_pattern_id = 96,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [155] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a3c,
+ .act_pattern_id = 97,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [156] = {
+ .act_hid = BNXT_ULP_ACT_HID_4298,
+ .act_pattern_id = 98,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [157] = {
+ .act_hid = BNXT_ULP_ACT_HID_75a8,
+ .act_pattern_id = 99,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [158] = {
+ .act_hid = BNXT_ULP_ACT_HID_53a8,
+ .act_pattern_id = 100,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [159] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e0c,
+ .act_pattern_id = 101,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [160] = {
+ .act_hid = BNXT_ULP_ACT_HID_711c,
+ .act_pattern_id = 102,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [161] = {
+ .act_hid = BNXT_ULP_ACT_HID_0670,
+ .act_pattern_id = 103,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [162] = {
+ .act_hid = BNXT_ULP_ACT_HID_42a8,
+ .act_pattern_id = 104,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [163] = {
+ .act_hid = BNXT_ULP_ACT_HID_75b8,
+ .act_pattern_id = 105,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [164] = {
+ .act_hid = BNXT_ULP_ACT_HID_53b8,
+ .act_pattern_id = 106,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [165] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e1c,
+ .act_pattern_id = 107,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [166] = {
+ .act_hid = BNXT_ULP_ACT_HID_712c,
+ .act_pattern_id = 108,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [167] = {
+ .act_hid = BNXT_ULP_ACT_HID_0680,
+ .act_pattern_id = 109,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [168] = {
+ .act_hid = BNXT_ULP_ACT_HID_3aea,
+ .act_pattern_id = 110,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [169] = {
+ .act_hid = BNXT_ULP_ACT_HID_42ea,
+ .act_pattern_id = 111,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [170] = {
+ .act_hid = BNXT_ULP_ACT_HID_4aea,
+ .act_pattern_id = 112,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [171] = {
+ .act_hid = BNXT_ULP_ACT_HID_3afa,
+ .act_pattern_id = 113,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [172] = {
+ .act_hid = BNXT_ULP_ACT_HID_42fa,
+ .act_pattern_id = 114,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [173] = {
+ .act_hid = BNXT_ULP_ACT_HID_4afa,
+ .act_pattern_id = 115,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [174] = {
+ .act_hid = BNXT_ULP_ACT_HID_43fa,
+ .act_pattern_id = 116,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [175] = {
+ .act_hid = BNXT_ULP_ACT_HID_770a,
+ .act_pattern_id = 117,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [176] = {
+ .act_hid = BNXT_ULP_ACT_HID_550a,
+ .act_pattern_id = 118,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [177] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f6e,
+ .act_pattern_id = 119,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [178] = {
+ .act_hid = BNXT_ULP_ACT_HID_727e,
+ .act_pattern_id = 120,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [179] = {
+ .act_hid = BNXT_ULP_ACT_HID_661a,
+ .act_pattern_id = 121,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [180] = {
+ .act_hid = BNXT_ULP_ACT_HID_07d2,
+ .act_pattern_id = 122,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [181] = {
+ .act_hid = BNXT_ULP_ACT_HID_4bfa,
+ .act_pattern_id = 123,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [182] = {
+ .act_hid = BNXT_ULP_ACT_HID_034e,
+ .act_pattern_id = 124,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [183] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d0a,
+ .act_pattern_id = 125,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [184] = {
+ .act_hid = BNXT_ULP_ACT_HID_476e,
+ .act_pattern_id = 126,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [185] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a7e,
+ .act_pattern_id = 127,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [186] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e1a,
+ .act_pattern_id = 128,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [187] = {
+ .act_hid = BNXT_ULP_ACT_HID_0fd2,
+ .act_pattern_id = 129,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [188] = {
+ .act_hid = BNXT_ULP_ACT_HID_53fa,
+ .act_pattern_id = 130,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [189] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b4e,
+ .act_pattern_id = 131,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [190] = {
+ .act_hid = BNXT_ULP_ACT_HID_650a,
+ .act_pattern_id = 132,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [191] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f6e,
+ .act_pattern_id = 133,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [192] = {
+ .act_hid = BNXT_ULP_ACT_HID_06c2,
+ .act_pattern_id = 134,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [193] = {
+ .act_hid = BNXT_ULP_ACT_HID_761a,
+ .act_pattern_id = 135,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [194] = {
+ .act_hid = BNXT_ULP_ACT_HID_17d2,
+ .act_pattern_id = 136,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [195] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bfa,
+ .act_pattern_id = 137,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [196] = {
+ .act_hid = BNXT_ULP_ACT_HID_134e,
+ .act_pattern_id = 138,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [197] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d0a,
+ .act_pattern_id = 139,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [198] = {
+ .act_hid = BNXT_ULP_ACT_HID_576e,
+ .act_pattern_id = 140,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [199] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ec2,
+ .act_pattern_id = 141,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [200] = {
+ .act_hid = BNXT_ULP_ACT_HID_025e,
+ .act_pattern_id = 142,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [201] = {
+ .act_hid = BNXT_ULP_ACT_HID_1fd2,
+ .act_pattern_id = 143,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [202] = {
+ .act_hid = BNXT_ULP_ACT_HID_440a,
+ .act_pattern_id = 144,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [203] = {
+ .act_hid = BNXT_ULP_ACT_HID_771a,
+ .act_pattern_id = 145,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [204] = {
+ .act_hid = BNXT_ULP_ACT_HID_551a,
+ .act_pattern_id = 146,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [205] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f7e,
+ .act_pattern_id = 147,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [206] = {
+ .act_hid = BNXT_ULP_ACT_HID_728e,
+ .act_pattern_id = 148,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [207] = {
+ .act_hid = BNXT_ULP_ACT_HID_662a,
+ .act_pattern_id = 149,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [208] = {
+ .act_hid = BNXT_ULP_ACT_HID_07e2,
+ .act_pattern_id = 150,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [209] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c0a,
+ .act_pattern_id = 151,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [210] = {
+ .act_hid = BNXT_ULP_ACT_HID_035e,
+ .act_pattern_id = 152,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [211] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d1a,
+ .act_pattern_id = 153,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [212] = {
+ .act_hid = BNXT_ULP_ACT_HID_477e,
+ .act_pattern_id = 154,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [213] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a8e,
+ .act_pattern_id = 155,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [214] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e2a,
+ .act_pattern_id = 156,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [215] = {
+ .act_hid = BNXT_ULP_ACT_HID_0fe2,
+ .act_pattern_id = 157,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [216] = {
+ .act_hid = BNXT_ULP_ACT_HID_540a,
+ .act_pattern_id = 158,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [217] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b5e,
+ .act_pattern_id = 159,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [218] = {
+ .act_hid = BNXT_ULP_ACT_HID_651a,
+ .act_pattern_id = 160,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [219] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f7e,
+ .act_pattern_id = 161,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [220] = {
+ .act_hid = BNXT_ULP_ACT_HID_06d2,
+ .act_pattern_id = 162,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [221] = {
+ .act_hid = BNXT_ULP_ACT_HID_762a,
+ .act_pattern_id = 163,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [222] = {
+ .act_hid = BNXT_ULP_ACT_HID_17e2,
+ .act_pattern_id = 164,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [223] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c0a,
+ .act_pattern_id = 165,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [224] = {
+ .act_hid = BNXT_ULP_ACT_HID_135e,
+ .act_pattern_id = 166,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [225] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d1a,
+ .act_pattern_id = 167,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [226] = {
+ .act_hid = BNXT_ULP_ACT_HID_577e,
+ .act_pattern_id = 168,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [227] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ed2,
+ .act_pattern_id = 169,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [228] = {
+ .act_hid = BNXT_ULP_ACT_HID_026e,
+ .act_pattern_id = 170,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [229] = {
+ .act_hid = BNXT_ULP_ACT_HID_1fe2,
+ .act_pattern_id = 171,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [230] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d82,
+ .act_pattern_id = 172,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [231] = {
+ .act_hid = BNXT_ULP_ACT_HID_14d6,
+ .act_pattern_id = 173,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [232] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e92,
+ .act_pattern_id = 174,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [233] = {
+ .act_hid = BNXT_ULP_ACT_HID_58f6,
+ .act_pattern_id = 175,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [234] = {
+ .act_hid = BNXT_ULP_ACT_HID_104a,
+ .act_pattern_id = 176,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [235] = {
+ .act_hid = BNXT_ULP_ACT_HID_215a,
+ .act_pattern_id = 177,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [236] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d92,
+ .act_pattern_id = 178,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [237] = {
+ .act_hid = BNXT_ULP_ACT_HID_14e6,
+ .act_pattern_id = 179,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [238] = {
+ .act_hid = BNXT_ULP_ACT_HID_6ea2,
+ .act_pattern_id = 180,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [239] = {
+ .act_hid = BNXT_ULP_ACT_HID_5906,
+ .act_pattern_id = 181,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [240] = {
+ .act_hid = BNXT_ULP_ACT_HID_105a,
+ .act_pattern_id = 182,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [241] = {
+ .act_hid = BNXT_ULP_ACT_HID_216a,
+ .act_pattern_id = 183,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [242] = {
+ .act_hid = BNXT_ULP_ACT_HID_6582,
+ .act_pattern_id = 184,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [243] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cd6,
+ .act_pattern_id = 185,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [244] = {
+ .act_hid = BNXT_ULP_ACT_HID_7692,
+ .act_pattern_id = 186,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [245] = {
+ .act_hid = BNXT_ULP_ACT_HID_60f6,
+ .act_pattern_id = 187,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [246] = {
+ .act_hid = BNXT_ULP_ACT_HID_184a,
+ .act_pattern_id = 188,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [247] = {
+ .act_hid = BNXT_ULP_ACT_HID_295a,
+ .act_pattern_id = 189,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [248] = {
+ .act_hid = BNXT_ULP_ACT_HID_6592,
+ .act_pattern_id = 190,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [249] = {
+ .act_hid = BNXT_ULP_ACT_HID_1ce6,
+ .act_pattern_id = 191,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [250] = {
+ .act_hid = BNXT_ULP_ACT_HID_76a2,
+ .act_pattern_id = 192,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [251] = {
+ .act_hid = BNXT_ULP_ACT_HID_6106,
+ .act_pattern_id = 193,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [252] = {
+ .act_hid = BNXT_ULP_ACT_HID_185a,
+ .act_pattern_id = 194,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [253] = {
+ .act_hid = BNXT_ULP_ACT_HID_296a,
+ .act_pattern_id = 195,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [254] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d82,
+ .act_pattern_id = 196,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [255] = {
+ .act_hid = BNXT_ULP_ACT_HID_24d6,
+ .act_pattern_id = 197,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [256] = {
+ .act_hid = BNXT_ULP_ACT_HID_02d6,
+ .act_pattern_id = 198,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [257] = {
+ .act_hid = BNXT_ULP_ACT_HID_68f6,
+ .act_pattern_id = 199,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [258] = {
+ .act_hid = BNXT_ULP_ACT_HID_204a,
+ .act_pattern_id = 200,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [259] = {
+ .act_hid = BNXT_ULP_ACT_HID_315a,
+ .act_pattern_id = 201,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [260] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d92,
+ .act_pattern_id = 202,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [261] = {
+ .act_hid = BNXT_ULP_ACT_HID_24e6,
+ .act_pattern_id = 203,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [262] = {
+ .act_hid = BNXT_ULP_ACT_HID_02e6,
+ .act_pattern_id = 204,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [263] = {
+ .act_hid = BNXT_ULP_ACT_HID_6906,
+ .act_pattern_id = 205,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [264] = {
+ .act_hid = BNXT_ULP_ACT_HID_205a,
+ .act_pattern_id = 206,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [265] = {
+ .act_hid = BNXT_ULP_ACT_HID_316a,
+ .act_pattern_id = 207,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [266] = {
+ .act_hid = BNXT_ULP_ACT_HID_7582,
+ .act_pattern_id = 208,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [267] = {
+ .act_hid = BNXT_ULP_ACT_HID_2cd6,
+ .act_pattern_id = 209,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [268] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ad6,
+ .act_pattern_id = 210,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [269] = {
+ .act_hid = BNXT_ULP_ACT_HID_70f6,
+ .act_pattern_id = 211,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [270] = {
+ .act_hid = BNXT_ULP_ACT_HID_284a,
+ .act_pattern_id = 212,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [271] = {
+ .act_hid = BNXT_ULP_ACT_HID_395a,
+ .act_pattern_id = 213,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [272] = {
+ .act_hid = BNXT_ULP_ACT_HID_7592,
+ .act_pattern_id = 214,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [273] = {
+ .act_hid = BNXT_ULP_ACT_HID_2ce6,
+ .act_pattern_id = 215,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [274] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ae6,
+ .act_pattern_id = 216,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [275] = {
+ .act_hid = BNXT_ULP_ACT_HID_7106,
+ .act_pattern_id = 217,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [276] = {
+ .act_hid = BNXT_ULP_ACT_HID_285a,
+ .act_pattern_id = 218,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [277] = {
+ .act_hid = BNXT_ULP_ACT_HID_396a,
+ .act_pattern_id = 219,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [278] = {
+ .act_hid = BNXT_ULP_ACT_HID_0020,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [279] = {
+ .act_hid = BNXT_ULP_ACT_HID_0030,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [280] = {
+ .act_hid = BNXT_ULP_ACT_HID_65d4,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [281] = {
+ .act_hid = BNXT_ULP_ACT_HID_65e4,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [282] = {
+ .act_hid = BNXT_ULP_ACT_HID_330a,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [283] = {
+ .act_hid = BNXT_ULP_ACT_HID_331a,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [284] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cfe,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [285] = {
+ .act_hid = BNXT_ULP_ACT_HID_1d0e,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 4
},
- [56] = {
- .act_hid = BNXT_ULP_ACT_HID_021e,
- .act_pattern_id = 2,
+ [286] = {
+ .act_hid = BNXT_ULP_ACT_HID_1474,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_METER_PROFILE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [287] = {
+ .act_hid = BNXT_ULP_ACT_HID_4838,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [288] = {
+ .act_hid = BNXT_ULP_ACT_HID_6458,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_METER_PROFILE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [289] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c68,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [290] = {
+ .act_hid = BNXT_ULP_ACT_HID_6c34,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_UPDATE |
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [291] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d08,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [292] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d10,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [293] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d20,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [294] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e18,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [295] = {
+ .act_hid = BNXT_ULP_ACT_HID_29d4,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [296] = {
+ .act_hid = BNXT_ULP_ACT_HID_7690,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [297] = {
+ .act_hid = BNXT_ULP_ACT_HID_47a0,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [298] = {
+ .act_hid = BNXT_ULP_ACT_HID_435c,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [299] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d18,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [300] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e28,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [301] = {
+ .act_hid = BNXT_ULP_ACT_HID_29e4,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [302] = {
+ .act_hid = BNXT_ULP_ACT_HID_76a0,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [303] = {
+ .act_hid = BNXT_ULP_ACT_HID_47b0,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [304] = {
+ .act_hid = BNXT_ULP_ACT_HID_436c,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [305] = {
+ .act_hid = BNXT_ULP_ACT_HID_1436,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [306] = {
+ .act_hid = BNXT_ULP_ACT_HID_143e,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [307] = {
+ .act_hid = BNXT_ULP_ACT_HID_144e,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [308] = {
+ .act_hid = BNXT_ULP_ACT_HID_6102,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [309] = {
+ .act_hid = BNXT_ULP_ACT_HID_5cbe,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [310] = {
+ .act_hid = BNXT_ULP_ACT_HID_2dbe,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [311] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a8a,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [312] = {
+ .act_hid = BNXT_ULP_ACT_HID_7646,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [313] = {
+ .act_hid = BNXT_ULP_ACT_HID_1446,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [314] = {
+ .act_hid = BNXT_ULP_ACT_HID_6112,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [315] = {
+ .act_hid = BNXT_ULP_ACT_HID_5cce,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [316] = {
+ .act_hid = BNXT_ULP_ACT_HID_2dce,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [317] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a9a,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [318] = {
+ .act_hid = BNXT_ULP_ACT_HID_7656,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [319] = {
+ .act_hid = BNXT_ULP_ACT_HID_6508,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [320] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d08,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [321] = {
+ .act_hid = BNXT_ULP_ACT_HID_7508,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [322] = {
+ .act_hid = BNXT_ULP_ACT_HID_6518,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [323] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d18,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [324] = {
+ .act_hid = BNXT_ULP_ACT_HID_7518,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [325] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e18,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [326] = {
+ .act_hid = BNXT_ULP_ACT_HID_256c,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [327] = {
+ .act_hid = BNXT_ULP_ACT_HID_036c,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [328] = {
+ .act_hid = BNXT_ULP_ACT_HID_698c,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [329] = {
+ .act_hid = BNXT_ULP_ACT_HID_20e0,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [330] = {
+ .act_hid = BNXT_ULP_ACT_HID_31f0,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [331] = {
+ .act_hid = BNXT_ULP_ACT_HID_7618,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [332] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d6c,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [333] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b6c,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [334] = {
+ .act_hid = BNXT_ULP_ACT_HID_718c,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [335] = {
+ .act_hid = BNXT_ULP_ACT_HID_28e0,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [336] = {
+ .act_hid = BNXT_ULP_ACT_HID_39f0,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [337] = {
+ .act_hid = BNXT_ULP_ACT_HID_025c,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [338] = {
+ .act_hid = BNXT_ULP_ACT_HID_356c,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [339] = {
+ .act_hid = BNXT_ULP_ACT_HID_136c,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [340] = {
+ .act_hid = BNXT_ULP_ACT_HID_798c,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [341] = {
+ .act_hid = BNXT_ULP_ACT_HID_30e0,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [342] = {
+ .act_hid = BNXT_ULP_ACT_HID_41f0,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [343] = {
+ .act_hid = BNXT_ULP_ACT_HID_0a5c,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [344] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d6c,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [345] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b6c,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [346] = {
+ .act_hid = BNXT_ULP_ACT_HID_05d0,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [347] = {
+ .act_hid = BNXT_ULP_ACT_HID_38e0,
+ .act_pattern_id = 28,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [348] = {
+ .act_hid = BNXT_ULP_ACT_HID_49f0,
+ .act_pattern_id = 29,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [349] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e28,
+ .act_pattern_id = 30,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [350] = {
+ .act_hid = BNXT_ULP_ACT_HID_257c,
+ .act_pattern_id = 31,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [351] = {
+ .act_hid = BNXT_ULP_ACT_HID_037c,
+ .act_pattern_id = 32,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [352] = {
+ .act_hid = BNXT_ULP_ACT_HID_699c,
+ .act_pattern_id = 33,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [353] = {
+ .act_hid = BNXT_ULP_ACT_HID_20f0,
+ .act_pattern_id = 34,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [354] = {
+ .act_hid = BNXT_ULP_ACT_HID_3200,
+ .act_pattern_id = 35,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [355] = {
+ .act_hid = BNXT_ULP_ACT_HID_7628,
+ .act_pattern_id = 36,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [356] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d7c,
+ .act_pattern_id = 37,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [357] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b7c,
+ .act_pattern_id = 38,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [358] = {
+ .act_hid = BNXT_ULP_ACT_HID_719c,
+ .act_pattern_id = 39,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [359] = {
+ .act_hid = BNXT_ULP_ACT_HID_28f0,
+ .act_pattern_id = 40,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [360] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a00,
+ .act_pattern_id = 41,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [361] = {
+ .act_hid = BNXT_ULP_ACT_HID_026c,
+ .act_pattern_id = 42,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [362] = {
+ .act_hid = BNXT_ULP_ACT_HID_357c,
+ .act_pattern_id = 43,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [363] = {
+ .act_hid = BNXT_ULP_ACT_HID_137c,
+ .act_pattern_id = 44,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [364] = {
+ .act_hid = BNXT_ULP_ACT_HID_799c,
+ .act_pattern_id = 45,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [365] = {
+ .act_hid = BNXT_ULP_ACT_HID_30f0,
+ .act_pattern_id = 46,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [366] = {
+ .act_hid = BNXT_ULP_ACT_HID_4200,
+ .act_pattern_id = 47,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [367] = {
+ .act_hid = BNXT_ULP_ACT_HID_0a6c,
+ .act_pattern_id = 48,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [368] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d7c,
+ .act_pattern_id = 49,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [369] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b7c,
+ .act_pattern_id = 50,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [370] = {
+ .act_hid = BNXT_ULP_ACT_HID_05e0,
+ .act_pattern_id = 51,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [371] = {
+ .act_hid = BNXT_ULP_ACT_HID_38f0,
+ .act_pattern_id = 52,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [372] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a00,
+ .act_pattern_id = 53,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [373] = {
+ .act_hid = BNXT_ULP_ACT_HID_0be4,
+ .act_pattern_id = 54,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [374] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ef4,
+ .act_pattern_id = 55,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [375] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cf4,
+ .act_pattern_id = 56,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [376] = {
+ .act_hid = BNXT_ULP_ACT_HID_0758,
+ .act_pattern_id = 57,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [377] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a68,
+ .act_pattern_id = 58,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [378] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b78,
+ .act_pattern_id = 59,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [379] = {
+ .act_hid = BNXT_ULP_ACT_HID_0bf4,
+ .act_pattern_id = 60,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [380] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f04,
+ .act_pattern_id = 61,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [381] = {
+ .act_hid = BNXT_ULP_ACT_HID_1d04,
+ .act_pattern_id = 62,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [382] = {
+ .act_hid = BNXT_ULP_ACT_HID_0768,
+ .act_pattern_id = 63,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [383] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a78,
+ .act_pattern_id = 64,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [384] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b88,
+ .act_pattern_id = 65,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [385] = {
+ .act_hid = BNXT_ULP_ACT_HID_46f4,
+ .act_pattern_id = 66,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [386] = {
+ .act_hid = BNXT_ULP_ACT_HID_24f4,
+ .act_pattern_id = 67,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [387] = {
+ .act_hid = BNXT_ULP_ACT_HID_0f58,
+ .act_pattern_id = 68,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [388] = {
+ .act_hid = BNXT_ULP_ACT_HID_13e4,
+ .act_pattern_id = 69,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [389] = {
+ .act_hid = BNXT_ULP_ACT_HID_4268,
+ .act_pattern_id = 70,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [390] = {
+ .act_hid = BNXT_ULP_ACT_HID_5378,
+ .act_pattern_id = 71,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [391] = {
+ .act_hid = BNXT_ULP_ACT_HID_13f4,
+ .act_pattern_id = 72,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [392] = {
+ .act_hid = BNXT_ULP_ACT_HID_4704,
+ .act_pattern_id = 73,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [393] = {
+ .act_hid = BNXT_ULP_ACT_HID_2504,
+ .act_pattern_id = 74,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [394] = {
+ .act_hid = BNXT_ULP_ACT_HID_0f68,
+ .act_pattern_id = 75,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [395] = {
+ .act_hid = BNXT_ULP_ACT_HID_4278,
+ .act_pattern_id = 76,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [396] = {
+ .act_hid = BNXT_ULP_ACT_HID_5388,
+ .act_pattern_id = 77,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [397] = {
+ .act_hid = BNXT_ULP_ACT_HID_1be4,
+ .act_pattern_id = 78,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [398] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ef4,
+ .act_pattern_id = 79,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [399] = {
+ .act_hid = BNXT_ULP_ACT_HID_2cf4,
+ .act_pattern_id = 80,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [400] = {
+ .act_hid = BNXT_ULP_ACT_HID_1758,
+ .act_pattern_id = 81,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [401] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a68,
+ .act_pattern_id = 82,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [402] = {
+ .act_hid = BNXT_ULP_ACT_HID_5b78,
+ .act_pattern_id = 83,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [403] = {
+ .act_hid = BNXT_ULP_ACT_HID_1bf4,
+ .act_pattern_id = 84,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [404] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f04,
+ .act_pattern_id = 85,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [405] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d04,
+ .act_pattern_id = 86,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [406] = {
+ .act_hid = BNXT_ULP_ACT_HID_1768,
+ .act_pattern_id = 87,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [407] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a78,
+ .act_pattern_id = 88,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [408] = {
+ .act_hid = BNXT_ULP_ACT_HID_5b88,
+ .act_pattern_id = 89,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [409] = {
+ .act_hid = BNXT_ULP_ACT_HID_23e4,
+ .act_pattern_id = 90,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [410] = {
+ .act_hid = BNXT_ULP_ACT_HID_56f4,
+ .act_pattern_id = 91,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [411] = {
+ .act_hid = BNXT_ULP_ACT_HID_34f4,
+ .act_pattern_id = 92,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [412] = {
+ .act_hid = BNXT_ULP_ACT_HID_1f58,
+ .act_pattern_id = 93,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [413] = {
+ .act_hid = BNXT_ULP_ACT_HID_5268,
+ .act_pattern_id = 94,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [414] = {
+ .act_hid = BNXT_ULP_ACT_HID_6378,
+ .act_pattern_id = 95,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [415] = {
+ .act_hid = BNXT_ULP_ACT_HID_23f4,
+ .act_pattern_id = 96,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [416] = {
+ .act_hid = BNXT_ULP_ACT_HID_5704,
+ .act_pattern_id = 97,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [417] = {
+ .act_hid = BNXT_ULP_ACT_HID_3504,
+ .act_pattern_id = 98,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [418] = {
+ .act_hid = BNXT_ULP_ACT_HID_1f68,
+ .act_pattern_id = 99,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [419] = {
+ .act_hid = BNXT_ULP_ACT_HID_5278,
+ .act_pattern_id = 100,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [420] = {
+ .act_hid = BNXT_ULP_ACT_HID_6388,
+ .act_pattern_id = 101,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [421] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c36,
+ .act_pattern_id = 102,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [422] = {
+ .act_hid = BNXT_ULP_ACT_HID_2436,
+ .act_pattern_id = 103,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [423] = {
+ .act_hid = BNXT_ULP_ACT_HID_2c36,
+ .act_pattern_id = 104,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [424] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c46,
+ .act_pattern_id = 105,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [425] = {
+ .act_hid = BNXT_ULP_ACT_HID_2446,
+ .act_pattern_id = 106,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [426] = {
+ .act_hid = BNXT_ULP_ACT_HID_2c46,
+ .act_pattern_id = 107,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [427] = {
+ .act_hid = BNXT_ULP_ACT_HID_2546,
+ .act_pattern_id = 108,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [428] = {
+ .act_hid = BNXT_ULP_ACT_HID_5856,
+ .act_pattern_id = 109,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [429] = {
+ .act_hid = BNXT_ULP_ACT_HID_3656,
+ .act_pattern_id = 110,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [430] = {
+ .act_hid = BNXT_ULP_ACT_HID_20ba,
+ .act_pattern_id = 111,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [431] = {
+ .act_hid = BNXT_ULP_ACT_HID_53ca,
+ .act_pattern_id = 112,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [432] = {
+ .act_hid = BNXT_ULP_ACT_HID_64da,
+ .act_pattern_id = 113,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [433] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d46,
+ .act_pattern_id = 114,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [434] = {
+ .act_hid = BNXT_ULP_ACT_HID_6056,
+ .act_pattern_id = 115,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [435] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e56,
+ .act_pattern_id = 116,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [436] = {
+ .act_hid = BNXT_ULP_ACT_HID_28ba,
+ .act_pattern_id = 117,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [437] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bca,
+ .act_pattern_id = 118,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [438] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cda,
+ .act_pattern_id = 119,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [439] = {
+ .act_hid = BNXT_ULP_ACT_HID_3546,
+ .act_pattern_id = 120,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [440] = {
+ .act_hid = BNXT_ULP_ACT_HID_6856,
+ .act_pattern_id = 121,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [441] = {
+ .act_hid = BNXT_ULP_ACT_HID_4656,
+ .act_pattern_id = 122,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [442] = {
+ .act_hid = BNXT_ULP_ACT_HID_30ba,
+ .act_pattern_id = 123,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [443] = {
+ .act_hid = BNXT_ULP_ACT_HID_63ca,
+ .act_pattern_id = 124,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [444] = {
+ .act_hid = BNXT_ULP_ACT_HID_74da,
+ .act_pattern_id = 125,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [445] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d46,
+ .act_pattern_id = 126,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [446] = {
+ .act_hid = BNXT_ULP_ACT_HID_7056,
+ .act_pattern_id = 127,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [447] = {
+ .act_hid = BNXT_ULP_ACT_HID_4e56,
+ .act_pattern_id = 128,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [448] = {
+ .act_hid = BNXT_ULP_ACT_HID_38ba,
+ .act_pattern_id = 129,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [449] = {
+ .act_hid = BNXT_ULP_ACT_HID_6bca,
+ .act_pattern_id = 130,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [450] = {
+ .act_hid = BNXT_ULP_ACT_HID_011e,
+ .act_pattern_id = 131,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [451] = {
+ .act_hid = BNXT_ULP_ACT_HID_2556,
+ .act_pattern_id = 132,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [452] = {
+ .act_hid = BNXT_ULP_ACT_HID_5866,
+ .act_pattern_id = 133,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [453] = {
+ .act_hid = BNXT_ULP_ACT_HID_3666,
+ .act_pattern_id = 134,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [454] = {
+ .act_hid = BNXT_ULP_ACT_HID_20ca,
+ .act_pattern_id = 135,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [455] = {
+ .act_hid = BNXT_ULP_ACT_HID_53da,
+ .act_pattern_id = 136,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [456] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ea,
+ .act_pattern_id = 137,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [457] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d56,
+ .act_pattern_id = 138,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [458] = {
+ .act_hid = BNXT_ULP_ACT_HID_6066,
+ .act_pattern_id = 139,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [459] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e66,
+ .act_pattern_id = 140,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [460] = {
+ .act_hid = BNXT_ULP_ACT_HID_28ca,
+ .act_pattern_id = 141,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [461] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bda,
+ .act_pattern_id = 142,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [462] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cea,
+ .act_pattern_id = 143,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [463] = {
+ .act_hid = BNXT_ULP_ACT_HID_3556,
+ .act_pattern_id = 144,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [464] = {
+ .act_hid = BNXT_ULP_ACT_HID_6866,
+ .act_pattern_id = 145,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [465] = {
+ .act_hid = BNXT_ULP_ACT_HID_4666,
+ .act_pattern_id = 146,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [466] = {
+ .act_hid = BNXT_ULP_ACT_HID_30ca,
+ .act_pattern_id = 147,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [467] = {
+ .act_hid = BNXT_ULP_ACT_HID_63da,
+ .act_pattern_id = 148,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [468] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ea,
+ .act_pattern_id = 149,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [469] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d56,
+ .act_pattern_id = 150,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [57] = {
- .act_hid = BNXT_ULP_ACT_HID_063f,
- .act_pattern_id = 3,
+ [470] = {
+ .act_hid = BNXT_ULP_ACT_HID_7066,
+ .act_pattern_id = 151,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [58] = {
- .act_hid = BNXT_ULP_ACT_HID_0510,
- .act_pattern_id = 4,
+ [471] = {
+ .act_hid = BNXT_ULP_ACT_HID_4e66,
+ .act_pattern_id = 152,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [59] = {
- .act_hid = BNXT_ULP_ACT_HID_03c6,
- .act_pattern_id = 5,
+ [472] = {
+ .act_hid = BNXT_ULP_ACT_HID_38ca,
+ .act_pattern_id = 153,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [473] = {
+ .act_hid = BNXT_ULP_ACT_HID_6bda,
+ .act_pattern_id = 154,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [474] = {
+ .act_hid = BNXT_ULP_ACT_HID_012e,
+ .act_pattern_id = 155,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [475] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ece,
+ .act_pattern_id = 156,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [60] = {
- .act_hid = BNXT_ULP_ACT_HID_0082,
- .act_pattern_id = 6,
+ [476] = {
+ .act_hid = BNXT_ULP_ACT_HID_71de,
+ .act_pattern_id = 157,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [61] = {
- .act_hid = BNXT_ULP_ACT_HID_06bb,
- .act_pattern_id = 7,
+ [477] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fde,
+ .act_pattern_id = 158,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [62] = {
- .act_hid = BNXT_ULP_ACT_HID_021d,
- .act_pattern_id = 8,
+ [478] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a42,
+ .act_pattern_id = 159,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [479] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d52,
+ .act_pattern_id = 160,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [480] = {
+ .act_hid = BNXT_ULP_ACT_HID_02a6,
+ .act_pattern_id = 161,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [481] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ede,
+ .act_pattern_id = 162,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [63] = {
- .act_hid = BNXT_ULP_ACT_HID_0641,
- .act_pattern_id = 9,
+ [482] = {
+ .act_hid = BNXT_ULP_ACT_HID_71ee,
+ .act_pattern_id = 163,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [64] = {
- .act_hid = BNXT_ULP_ACT_HID_0512,
- .act_pattern_id = 10,
+ [483] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fee,
+ .act_pattern_id = 164,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [65] = {
- .act_hid = BNXT_ULP_ACT_HID_03c8,
- .act_pattern_id = 11,
+ [484] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a52,
+ .act_pattern_id = 165,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [485] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d62,
+ .act_pattern_id = 166,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [486] = {
+ .act_hid = BNXT_ULP_ACT_HID_02b6,
+ .act_pattern_id = 167,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [66] = {
- .act_hid = BNXT_ULP_ACT_HID_0084,
- .act_pattern_id = 12,
+ [487] = {
+ .act_hid = BNXT_ULP_ACT_HID_79de,
+ .act_pattern_id = 168,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [488] = {
+ .act_hid = BNXT_ULP_ACT_HID_57de,
+ .act_pattern_id = 169,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [489] = {
+ .act_hid = BNXT_ULP_ACT_HID_4242,
+ .act_pattern_id = 170,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [490] = {
+ .act_hid = BNXT_ULP_ACT_HID_46ce,
+ .act_pattern_id = 171,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [491] = {
+ .act_hid = BNXT_ULP_ACT_HID_7552,
+ .act_pattern_id = 172,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [492] = {
+ .act_hid = BNXT_ULP_ACT_HID_0aa6,
+ .act_pattern_id = 173,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [493] = {
+ .act_hid = BNXT_ULP_ACT_HID_46de,
+ .act_pattern_id = 174,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [494] = {
+ .act_hid = BNXT_ULP_ACT_HID_79ee,
+ .act_pattern_id = 175,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [67] = {
- .act_hid = BNXT_ULP_ACT_HID_06bd,
- .act_pattern_id = 13,
+ [495] = {
+ .act_hid = BNXT_ULP_ACT_HID_57ee,
+ .act_pattern_id = 176,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [496] = {
+ .act_hid = BNXT_ULP_ACT_HID_4252,
+ .act_pattern_id = 177,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [497] = {
+ .act_hid = BNXT_ULP_ACT_HID_7562,
+ .act_pattern_id = 178,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [68] = {
- .act_hid = BNXT_ULP_ACT_HID_06d7,
- .act_pattern_id = 0,
+ [498] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ab6,
+ .act_pattern_id = 179,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [499] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ece,
+ .act_pattern_id = 180,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [69] = {
- .act_hid = BNXT_ULP_ACT_HID_02c4,
- .act_pattern_id = 1,
+ [500] = {
+ .act_hid = BNXT_ULP_ACT_HID_0622,
+ .act_pattern_id = 181,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [70] = {
- .act_hid = BNXT_ULP_ACT_HID_042a,
- .act_pattern_id = 2,
+ [501] = {
+ .act_hid = BNXT_ULP_ACT_HID_5fde,
+ .act_pattern_id = 182,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [71] = {
- .act_hid = BNXT_ULP_ACT_HID_036e,
- .act_pattern_id = 3,
+ [502] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a42,
+ .act_pattern_id = 183,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [72] = {
- .act_hid = BNXT_ULP_ACT_HID_06c4,
- .act_pattern_id = 4,
+ [503] = {
+ .act_hid = BNXT_ULP_ACT_HID_0196,
+ .act_pattern_id = 184,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [73] = {
- .act_hid = BNXT_ULP_ACT_HID_0417,
- .act_pattern_id = 5,
+ [504] = {
+ .act_hid = BNXT_ULP_ACT_HID_12a6,
+ .act_pattern_id = 185,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [74] = {
- .act_hid = BNXT_ULP_ACT_HID_06d9,
- .act_pattern_id = 6,
+ [505] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ede,
+ .act_pattern_id = 186,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [75] = {
- .act_hid = BNXT_ULP_ACT_HID_02c6,
- .act_pattern_id = 7,
+ [506] = {
+ .act_hid = BNXT_ULP_ACT_HID_0632,
+ .act_pattern_id = 187,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [76] = {
- .act_hid = BNXT_ULP_ACT_HID_042c,
- .act_pattern_id = 8,
+ [507] = {
+ .act_hid = BNXT_ULP_ACT_HID_5fee,
+ .act_pattern_id = 188,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [77] = {
- .act_hid = BNXT_ULP_ACT_HID_0370,
- .act_pattern_id = 9,
+ [508] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a52,
+ .act_pattern_id = 189,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [78] = {
- .act_hid = BNXT_ULP_ACT_HID_06c6,
- .act_pattern_id = 10,
+ [509] = {
+ .act_hid = BNXT_ULP_ACT_HID_01a6,
+ .act_pattern_id = 190,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [79] = {
- .act_hid = BNXT_ULP_ACT_HID_0419,
- .act_pattern_id = 11,
+ [510] = {
+ .act_hid = BNXT_ULP_ACT_HID_12b6,
+ .act_pattern_id = 191,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [80] = {
- .act_hid = BNXT_ULP_ACT_HID_0119,
- .act_pattern_id = 12,
+ [511] = {
+ .act_hid = BNXT_ULP_ACT_HID_56ce,
+ .act_pattern_id = 192,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [81] = {
- .act_hid = BNXT_ULP_ACT_HID_046f,
- .act_pattern_id = 13,
+ [512] = {
+ .act_hid = BNXT_ULP_ACT_HID_0e22,
+ .act_pattern_id = 193,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [82] = {
- .act_hid = BNXT_ULP_ACT_HID_05d5,
- .act_pattern_id = 14,
+ [513] = {
+ .act_hid = BNXT_ULP_ACT_HID_67de,
+ .act_pattern_id = 194,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [83] = {
- .act_hid = BNXT_ULP_ACT_HID_0519,
- .act_pattern_id = 15,
+ [514] = {
+ .act_hid = BNXT_ULP_ACT_HID_5242,
+ .act_pattern_id = 195,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [84] = {
- .act_hid = BNXT_ULP_ACT_HID_0106,
- .act_pattern_id = 16,
+ [515] = {
+ .act_hid = BNXT_ULP_ACT_HID_0996,
+ .act_pattern_id = 196,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [85] = {
- .act_hid = BNXT_ULP_ACT_HID_05c2,
- .act_pattern_id = 17,
+ [516] = {
+ .act_hid = BNXT_ULP_ACT_HID_1aa6,
+ .act_pattern_id = 197,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [86] = {
- .act_hid = BNXT_ULP_ACT_HID_011b,
- .act_pattern_id = 18,
+ [517] = {
+ .act_hid = BNXT_ULP_ACT_HID_56de,
+ .act_pattern_id = 198,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [87] = {
- .act_hid = BNXT_ULP_ACT_HID_0471,
- .act_pattern_id = 19,
+ [518] = {
+ .act_hid = BNXT_ULP_ACT_HID_0e32,
+ .act_pattern_id = 199,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [88] = {
- .act_hid = BNXT_ULP_ACT_HID_05d7,
- .act_pattern_id = 20,
+ [519] = {
+ .act_hid = BNXT_ULP_ACT_HID_67ee,
+ .act_pattern_id = 200,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [89] = {
- .act_hid = BNXT_ULP_ACT_HID_051b,
- .act_pattern_id = 21,
+ [520] = {
+ .act_hid = BNXT_ULP_ACT_HID_5252,
+ .act_pattern_id = 201,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [90] = {
- .act_hid = BNXT_ULP_ACT_HID_0108,
- .act_pattern_id = 22,
+ [521] = {
+ .act_hid = BNXT_ULP_ACT_HID_09a6,
+ .act_pattern_id = 202,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [91] = {
- .act_hid = BNXT_ULP_ACT_HID_05c4,
- .act_pattern_id = 23,
+ [522] = {
+ .act_hid = BNXT_ULP_ACT_HID_1ab6,
+ .act_pattern_id = 203,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
@@ -1089,25 +6906,256 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [92] = {
- .act_hid = BNXT_ULP_ACT_HID_00a2,
+ [523] = {
+ .act_hid = BNXT_ULP_ACT_HID_31d0,
.act_pattern_id = 0,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 6
+ .act_tid = 8
},
- [93] = {
- .act_hid = BNXT_ULP_ACT_HID_00a4,
+ [524] = {
+ .act_hid = BNXT_ULP_ACT_HID_31e0,
.act_pattern_id = 1,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 6
+ .act_tid = 8
+ },
+ [525] = {
+ .act_hid = BNXT_ULP_ACT_HID_39d0,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [526] = {
+ .act_hid = BNXT_ULP_ACT_HID_39e0,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [527] = {
+ .act_hid = BNXT_ULP_ACT_HID_41d0,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [528] = {
+ .act_hid = BNXT_ULP_ACT_HID_41e0,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [529] = {
+ .act_hid = BNXT_ULP_ACT_HID_49d0,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [530] = {
+ .act_hid = BNXT_ULP_ACT_HID_49e0,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [531] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ba,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [532] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ca,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [533] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cba,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [534] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cca,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [535] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ba,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [536] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ca,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [537] = {
+ .act_hid = BNXT_ULP_ACT_HID_00fe,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [538] = {
+ .act_hid = BNXT_ULP_ACT_HID_010e,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [539] = {
+ .act_hid = BNXT_ULP_ACT_HID_331c,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [540] = {
+ .act_hid = BNXT_ULP_ACT_HID_332c,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [541] = {
+ .act_hid = BNXT_ULP_ACT_HID_6706,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [542] = {
+ .act_hid = BNXT_ULP_ACT_HID_6716,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [543] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b6d,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
+ },
+ [544] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b7d,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
+ },
+ [545] = {
+ .act_hid = BNXT_ULP_ACT_HID_641a,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
}
};
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index c127a53b32..70409edb68 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -16,1308 +14,1918 @@
* maps hash id to ulp_class_match_list[] index
*/
uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_CLASS_HID_55dd] = 1,
- [BNXT_ULP_CLASS_HID_1df1] = 2,
- [BNXT_ULP_CLASS_HID_3e55] = 3,
- [BNXT_ULP_CLASS_HID_0649] = 4,
- [BNXT_ULP_CLASS_HID_1011] = 5,
- [BNXT_ULP_CLASS_HID_40e9] = 6,
- [BNXT_ULP_CLASS_HID_3e99] = 7,
- [BNXT_ULP_CLASS_HID_06ad] = 8,
- [BNXT_ULP_CLASS_HID_38c7] = 9,
- [BNXT_ULP_CLASS_HID_00fb] = 10,
- [BNXT_ULP_CLASS_HID_24d3] = 11,
- [BNXT_ULP_CLASS_HID_559b] = 12,
- [BNXT_ULP_CLASS_HID_5003] = 13,
- [BNXT_ULP_CLASS_HID_1837] = 14,
- [BNXT_ULP_CLASS_HID_3bef] = 15,
- [BNXT_ULP_CLASS_HID_0403] = 16,
- [BNXT_ULP_CLASS_HID_3d3f] = 17,
- [BNXT_ULP_CLASS_HID_0543] = 18,
- [BNXT_ULP_CLASS_HID_292b] = 19,
- [BNXT_ULP_CLASS_HID_59e3] = 20,
- [BNXT_ULP_CLASS_HID_5d3b] = 21,
- [BNXT_ULP_CLASS_HID_254f] = 22,
- [BNXT_ULP_CLASS_HID_4917] = 23,
- [BNXT_ULP_CLASS_HID_113b] = 24,
- [BNXT_ULP_CLASS_HID_55fd] = 25,
- [BNXT_ULP_CLASS_HID_1dd1] = 26,
- [BNXT_ULP_CLASS_HID_3e75] = 27,
- [BNXT_ULP_CLASS_HID_0669] = 28,
- [BNXT_ULP_CLASS_HID_1ba1] = 29,
- [BNXT_ULP_CLASS_HID_4c69] = 30,
- [BNXT_ULP_CLASS_HID_0439] = 31,
- [BNXT_ULP_CLASS_HID_34e1] = 32,
- [BNXT_ULP_CLASS_HID_0465] = 33,
- [BNXT_ULP_CLASS_HID_352d] = 34,
- [BNXT_ULP_CLASS_HID_55b1] = 35,
- [BNXT_ULP_CLASS_HID_1da5] = 36,
- [BNXT_ULP_CLASS_HID_32fd] = 37,
- [BNXT_ULP_CLASS_HID_63a5] = 38,
- [BNXT_ULP_CLASS_HID_1b75] = 39,
- [BNXT_ULP_CLASS_HID_4c3d] = 40,
- [BNXT_ULP_CLASS_HID_1031] = 41,
- [BNXT_ULP_CLASS_HID_40c9] = 42,
- [BNXT_ULP_CLASS_HID_3eb9] = 43,
- [BNXT_ULP_CLASS_HID_068d] = 44,
- [BNXT_ULP_CLASS_HID_5039] = 45,
- [BNXT_ULP_CLASS_HID_180d] = 46,
- [BNXT_ULP_CLASS_HID_15fd] = 47,
- [BNXT_ULP_CLASS_HID_46b5] = 48,
- [BNXT_ULP_CLASS_HID_303d] = 49,
- [BNXT_ULP_CLASS_HID_60f5] = 50,
- [BNXT_ULP_CLASS_HID_5ea5] = 51,
- [BNXT_ULP_CLASS_HID_2689] = 52,
- [BNXT_ULP_CLASS_HID_0771] = 53,
- [BNXT_ULP_CLASS_HID_3809] = 54,
- [BNXT_ULP_CLASS_HID_35f9] = 55,
- [BNXT_ULP_CLASS_HID_66b1] = 56,
- [BNXT_ULP_CLASS_HID_559d] = 57,
- [BNXT_ULP_CLASS_HID_1db1] = 58,
- [BNXT_ULP_CLASS_HID_3e15] = 59,
- [BNXT_ULP_CLASS_HID_0609] = 60,
- [BNXT_ULP_CLASS_HID_1bc1] = 61,
- [BNXT_ULP_CLASS_HID_4c09] = 62,
- [BNXT_ULP_CLASS_HID_0459] = 63,
- [BNXT_ULP_CLASS_HID_3481] = 64,
- [BNXT_ULP_CLASS_HID_0405] = 65,
- [BNXT_ULP_CLASS_HID_354d] = 66,
- [BNXT_ULP_CLASS_HID_55d1] = 67,
- [BNXT_ULP_CLASS_HID_1dc5] = 68,
- [BNXT_ULP_CLASS_HID_329d] = 69,
- [BNXT_ULP_CLASS_HID_63c5] = 70,
- [BNXT_ULP_CLASS_HID_1b15] = 71,
- [BNXT_ULP_CLASS_HID_4c5d] = 72,
- [BNXT_ULP_CLASS_HID_1051] = 73,
- [BNXT_ULP_CLASS_HID_40a9] = 74,
- [BNXT_ULP_CLASS_HID_3ed9] = 75,
- [BNXT_ULP_CLASS_HID_06ed] = 76,
- [BNXT_ULP_CLASS_HID_5059] = 77,
- [BNXT_ULP_CLASS_HID_186d] = 78,
- [BNXT_ULP_CLASS_HID_159d] = 79,
- [BNXT_ULP_CLASS_HID_46d5] = 80,
- [BNXT_ULP_CLASS_HID_305d] = 81,
- [BNXT_ULP_CLASS_HID_6095] = 82,
- [BNXT_ULP_CLASS_HID_5ec5] = 83,
- [BNXT_ULP_CLASS_HID_26e9] = 84,
- [BNXT_ULP_CLASS_HID_0711] = 85,
- [BNXT_ULP_CLASS_HID_3869] = 86,
- [BNXT_ULP_CLASS_HID_3599] = 87,
- [BNXT_ULP_CLASS_HID_66d1] = 88,
- [BNXT_ULP_CLASS_HID_38e7] = 89,
- [BNXT_ULP_CLASS_HID_00db] = 90,
- [BNXT_ULP_CLASS_HID_24f3] = 91,
- [BNXT_ULP_CLASS_HID_55bb] = 92,
- [BNXT_ULP_CLASS_HID_5023] = 93,
- [BNXT_ULP_CLASS_HID_1817] = 94,
- [BNXT_ULP_CLASS_HID_3bcf] = 95,
- [BNXT_ULP_CLASS_HID_0423] = 96,
- [BNXT_ULP_CLASS_HID_58e3] = 97,
- [BNXT_ULP_CLASS_HID_20d7] = 98,
- [BNXT_ULP_CLASS_HID_448f] = 99,
- [BNXT_ULP_CLASS_HID_0ce3] = 100,
- [BNXT_ULP_CLASS_HID_076b] = 101,
- [BNXT_ULP_CLASS_HID_3813] = 102,
- [BNXT_ULP_CLASS_HID_5bcb] = 103,
- [BNXT_ULP_CLASS_HID_243f] = 104,
- [BNXT_ULP_CLASS_HID_144b] = 105,
- [BNXT_ULP_CLASS_HID_4573] = 106,
- [BNXT_ULP_CLASS_HID_0057] = 107,
- [BNXT_ULP_CLASS_HID_311f] = 108,
- [BNXT_ULP_CLASS_HID_2b87] = 109,
- [BNXT_ULP_CLASS_HID_5c4f] = 110,
- [BNXT_ULP_CLASS_HID_1793] = 111,
- [BNXT_ULP_CLASS_HID_485b] = 112,
- [BNXT_ULP_CLASS_HID_3447] = 113,
- [BNXT_ULP_CLASS_HID_650f] = 114,
- [BNXT_ULP_CLASS_HID_2053] = 115,
- [BNXT_ULP_CLASS_HID_511b] = 116,
- [BNXT_ULP_CLASS_HID_4b83] = 117,
- [BNXT_ULP_CLASS_HID_13f7] = 118,
- [BNXT_ULP_CLASS_HID_37af] = 119,
- [BNXT_ULP_CLASS_HID_6857] = 120,
- [BNXT_ULP_CLASS_HID_3d1f] = 121,
- [BNXT_ULP_CLASS_HID_0563] = 122,
- [BNXT_ULP_CLASS_HID_290b] = 123,
- [BNXT_ULP_CLASS_HID_59c3] = 124,
- [BNXT_ULP_CLASS_HID_5d1b] = 125,
- [BNXT_ULP_CLASS_HID_256f] = 126,
- [BNXT_ULP_CLASS_HID_4937] = 127,
- [BNXT_ULP_CLASS_HID_111b] = 128,
- [BNXT_ULP_CLASS_HID_25f4b] = 129,
- [BNXT_ULP_CLASS_HID_2275f] = 130,
- [BNXT_ULP_CLASS_HID_24b67] = 131,
- [BNXT_ULP_CLASS_HID_2134b] = 132,
- [BNXT_ULP_CLASS_HID_21683] = 133,
- [BNXT_ULP_CLASS_HID_2475b] = 134,
- [BNXT_ULP_CLASS_HID_202bf] = 135,
- [BNXT_ULP_CLASS_HID_23377] = 136,
- [BNXT_ULP_CLASS_HID_119db] = 137,
- [BNXT_ULP_CLASS_HID_14a93] = 138,
- [BNXT_ULP_CLASS_HID_105f7] = 139,
- [BNXT_ULP_CLASS_HID_1368f] = 140,
- [BNXT_ULP_CLASS_HID_139c7] = 141,
- [BNXT_ULP_CLASS_HID_1022b] = 142,
- [BNXT_ULP_CLASS_HID_125f3] = 143,
- [BNXT_ULP_CLASS_HID_1568b] = 144,
- [BNXT_ULP_CLASS_HID_33c37] = 145,
- [BNXT_ULP_CLASS_HID_3041b] = 146,
- [BNXT_ULP_CLASS_HID_32823] = 147,
- [BNXT_ULP_CLASS_HID_358fb] = 148,
- [BNXT_ULP_CLASS_HID_35c33] = 149,
- [BNXT_ULP_CLASS_HID_32407] = 150,
- [BNXT_ULP_CLASS_HID_3482f] = 151,
- [BNXT_ULP_CLASS_HID_31033] = 152,
- [BNXT_ULP_CLASS_HID_3887] = 153,
- [BNXT_ULP_CLASS_HID_00bb] = 154,
- [BNXT_ULP_CLASS_HID_2493] = 155,
- [BNXT_ULP_CLASS_HID_55db] = 156,
- [BNXT_ULP_CLASS_HID_5043] = 157,
- [BNXT_ULP_CLASS_HID_1877] = 158,
- [BNXT_ULP_CLASS_HID_3baf] = 159,
- [BNXT_ULP_CLASS_HID_0443] = 160,
- [BNXT_ULP_CLASS_HID_5883] = 161,
- [BNXT_ULP_CLASS_HID_20b7] = 162,
- [BNXT_ULP_CLASS_HID_44ef] = 163,
- [BNXT_ULP_CLASS_HID_0c83] = 164,
- [BNXT_ULP_CLASS_HID_070b] = 165,
- [BNXT_ULP_CLASS_HID_3873] = 166,
- [BNXT_ULP_CLASS_HID_5bab] = 167,
- [BNXT_ULP_CLASS_HID_245f] = 168,
- [BNXT_ULP_CLASS_HID_142b] = 169,
- [BNXT_ULP_CLASS_HID_4513] = 170,
- [BNXT_ULP_CLASS_HID_0037] = 171,
- [BNXT_ULP_CLASS_HID_317f] = 172,
- [BNXT_ULP_CLASS_HID_2be7] = 173,
- [BNXT_ULP_CLASS_HID_5c2f] = 174,
- [BNXT_ULP_CLASS_HID_17f3] = 175,
- [BNXT_ULP_CLASS_HID_483b] = 176,
- [BNXT_ULP_CLASS_HID_3427] = 177,
- [BNXT_ULP_CLASS_HID_656f] = 178,
- [BNXT_ULP_CLASS_HID_2033] = 179,
- [BNXT_ULP_CLASS_HID_517b] = 180,
- [BNXT_ULP_CLASS_HID_4be3] = 181,
- [BNXT_ULP_CLASS_HID_1397] = 182,
- [BNXT_ULP_CLASS_HID_37cf] = 183,
- [BNXT_ULP_CLASS_HID_6837] = 184,
- [BNXT_ULP_CLASS_HID_3d7f] = 185,
- [BNXT_ULP_CLASS_HID_0503] = 186,
- [BNXT_ULP_CLASS_HID_296b] = 187,
- [BNXT_ULP_CLASS_HID_59a3] = 188,
- [BNXT_ULP_CLASS_HID_5d7b] = 189,
- [BNXT_ULP_CLASS_HID_250f] = 190,
- [BNXT_ULP_CLASS_HID_4957] = 191,
- [BNXT_ULP_CLASS_HID_117b] = 192,
- [BNXT_ULP_CLASS_HID_25f2b] = 193,
- [BNXT_ULP_CLASS_HID_2273f] = 194,
- [BNXT_ULP_CLASS_HID_24b07] = 195,
- [BNXT_ULP_CLASS_HID_2132b] = 196,
- [BNXT_ULP_CLASS_HID_216e3] = 197,
- [BNXT_ULP_CLASS_HID_2473b] = 198,
- [BNXT_ULP_CLASS_HID_202df] = 199,
- [BNXT_ULP_CLASS_HID_23317] = 200,
- [BNXT_ULP_CLASS_HID_119bb] = 201,
- [BNXT_ULP_CLASS_HID_14af3] = 202,
- [BNXT_ULP_CLASS_HID_10597] = 203,
- [BNXT_ULP_CLASS_HID_136ef] = 204,
- [BNXT_ULP_CLASS_HID_139a7] = 205,
- [BNXT_ULP_CLASS_HID_1024b] = 206,
- [BNXT_ULP_CLASS_HID_12593] = 207,
- [BNXT_ULP_CLASS_HID_156eb] = 208,
- [BNXT_ULP_CLASS_HID_33c57] = 209,
- [BNXT_ULP_CLASS_HID_3047b] = 210,
- [BNXT_ULP_CLASS_HID_32843] = 211,
- [BNXT_ULP_CLASS_HID_3589b] = 212,
- [BNXT_ULP_CLASS_HID_35c53] = 213,
- [BNXT_ULP_CLASS_HID_32467] = 214,
- [BNXT_ULP_CLASS_HID_3484f] = 215,
- [BNXT_ULP_CLASS_HID_31053] = 216,
- [BNXT_ULP_CLASS_HID_5ce1] = 217,
- [BNXT_ULP_CLASS_HID_4579] = 218,
- [BNXT_ULP_CLASS_HID_1735] = 219,
- [BNXT_ULP_CLASS_HID_45bd] = 220,
- [BNXT_ULP_CLASS_HID_3feb] = 221,
- [BNXT_ULP_CLASS_HID_2bf7] = 222,
- [BNXT_ULP_CLASS_HID_5727] = 223,
- [BNXT_ULP_CLASS_HID_4333] = 224,
- [BNXT_ULP_CLASS_HID_4453] = 225,
- [BNXT_ULP_CLASS_HID_304f] = 226,
- [BNXT_ULP_CLASS_HID_645f] = 227,
- [BNXT_ULP_CLASS_HID_504b] = 228,
- [BNXT_ULP_CLASS_HID_5cc1] = 229,
- [BNXT_ULP_CLASS_HID_4559] = 230,
- [BNXT_ULP_CLASS_HID_2285] = 231,
- [BNXT_ULP_CLASS_HID_0b1d] = 232,
- [BNXT_ULP_CLASS_HID_0b49] = 233,
- [BNXT_ULP_CLASS_HID_5c95] = 234,
- [BNXT_ULP_CLASS_HID_39c1] = 235,
- [BNXT_ULP_CLASS_HID_2259] = 236,
- [BNXT_ULP_CLASS_HID_1715] = 237,
- [BNXT_ULP_CLASS_HID_459d] = 238,
- [BNXT_ULP_CLASS_HID_571d] = 239,
- [BNXT_ULP_CLASS_HID_1cd1] = 240,
- [BNXT_ULP_CLASS_HID_3711] = 241,
- [BNXT_ULP_CLASS_HID_6599] = 242,
- [BNXT_ULP_CLASS_HID_0e55] = 243,
- [BNXT_ULP_CLASS_HID_3cdd] = 244,
- [BNXT_ULP_CLASS_HID_5ca1] = 245,
- [BNXT_ULP_CLASS_HID_4539] = 246,
- [BNXT_ULP_CLASS_HID_22e5] = 247,
- [BNXT_ULP_CLASS_HID_0b7d] = 248,
- [BNXT_ULP_CLASS_HID_0b29] = 249,
- [BNXT_ULP_CLASS_HID_5cf5] = 250,
- [BNXT_ULP_CLASS_HID_39a1] = 251,
- [BNXT_ULP_CLASS_HID_2239] = 252,
- [BNXT_ULP_CLASS_HID_1775] = 253,
- [BNXT_ULP_CLASS_HID_45fd] = 254,
- [BNXT_ULP_CLASS_HID_577d] = 255,
- [BNXT_ULP_CLASS_HID_1cb1] = 256,
- [BNXT_ULP_CLASS_HID_3771] = 257,
- [BNXT_ULP_CLASS_HID_65f9] = 258,
- [BNXT_ULP_CLASS_HID_0e35] = 259,
- [BNXT_ULP_CLASS_HID_3cbd] = 260,
- [BNXT_ULP_CLASS_HID_3fcb] = 261,
- [BNXT_ULP_CLASS_HID_2bd7] = 262,
- [BNXT_ULP_CLASS_HID_5707] = 263,
- [BNXT_ULP_CLASS_HID_4313] = 264,
- [BNXT_ULP_CLASS_HID_5fc7] = 265,
- [BNXT_ULP_CLASS_HID_4bd3] = 266,
- [BNXT_ULP_CLASS_HID_0e4f] = 267,
- [BNXT_ULP_CLASS_HID_632f] = 268,
- [BNXT_ULP_CLASS_HID_1baf] = 269,
- [BNXT_ULP_CLASS_HID_07bb] = 270,
- [BNXT_ULP_CLASS_HID_32eb] = 271,
- [BNXT_ULP_CLASS_HID_1ef7] = 272,
- [BNXT_ULP_CLASS_HID_3bab] = 273,
- [BNXT_ULP_CLASS_HID_27b7] = 274,
- [BNXT_ULP_CLASS_HID_52e7] = 275,
- [BNXT_ULP_CLASS_HID_3ef3] = 276,
- [BNXT_ULP_CLASS_HID_4473] = 277,
- [BNXT_ULP_CLASS_HID_306f] = 278,
- [BNXT_ULP_CLASS_HID_647f] = 279,
- [BNXT_ULP_CLASS_HID_506b] = 280,
- [BNXT_ULP_CLASS_HID_266af] = 281,
- [BNXT_ULP_CLASS_HID_2525b] = 282,
- [BNXT_ULP_CLASS_HID_21de7] = 283,
- [BNXT_ULP_CLASS_HID_20993] = 284,
- [BNXT_ULP_CLASS_HID_1213f] = 285,
- [BNXT_ULP_CLASS_HID_10d2b] = 286,
- [BNXT_ULP_CLASS_HID_1413b] = 287,
- [BNXT_ULP_CLASS_HID_12cd7] = 288,
- [BNXT_ULP_CLASS_HID_3436b] = 289,
- [BNXT_ULP_CLASS_HID_32f07] = 290,
- [BNXT_ULP_CLASS_HID_36317] = 291,
- [BNXT_ULP_CLASS_HID_34f03] = 292,
- [BNXT_ULP_CLASS_HID_3fab] = 293,
- [BNXT_ULP_CLASS_HID_2bb7] = 294,
- [BNXT_ULP_CLASS_HID_5767] = 295,
- [BNXT_ULP_CLASS_HID_4373] = 296,
- [BNXT_ULP_CLASS_HID_5fa7] = 297,
- [BNXT_ULP_CLASS_HID_4bb3] = 298,
- [BNXT_ULP_CLASS_HID_0e2f] = 299,
- [BNXT_ULP_CLASS_HID_634f] = 300,
- [BNXT_ULP_CLASS_HID_1bcf] = 301,
- [BNXT_ULP_CLASS_HID_07db] = 302,
- [BNXT_ULP_CLASS_HID_328b] = 303,
- [BNXT_ULP_CLASS_HID_1e97] = 304,
- [BNXT_ULP_CLASS_HID_3bcb] = 305,
- [BNXT_ULP_CLASS_HID_27d7] = 306,
- [BNXT_ULP_CLASS_HID_5287] = 307,
- [BNXT_ULP_CLASS_HID_3e93] = 308,
- [BNXT_ULP_CLASS_HID_4413] = 309,
- [BNXT_ULP_CLASS_HID_300f] = 310,
- [BNXT_ULP_CLASS_HID_641f] = 311,
- [BNXT_ULP_CLASS_HID_500b] = 312,
- [BNXT_ULP_CLASS_HID_266cf] = 313,
- [BNXT_ULP_CLASS_HID_2523b] = 314,
- [BNXT_ULP_CLASS_HID_21d87] = 315,
- [BNXT_ULP_CLASS_HID_209f3] = 316,
- [BNXT_ULP_CLASS_HID_1215f] = 317,
- [BNXT_ULP_CLASS_HID_10d4b] = 318,
- [BNXT_ULP_CLASS_HID_1415b] = 319,
- [BNXT_ULP_CLASS_HID_12cb7] = 320,
- [BNXT_ULP_CLASS_HID_3430b] = 321,
- [BNXT_ULP_CLASS_HID_32f67] = 322,
- [BNXT_ULP_CLASS_HID_36377] = 323,
- [BNXT_ULP_CLASS_HID_34f63] = 324,
- [BNXT_ULP_CLASS_HID_29b5] = 325,
- [BNXT_ULP_CLASS_HID_29ad] = 326,
- [BNXT_ULP_CLASS_HID_29b7] = 327,
- [BNXT_ULP_CLASS_HID_1583] = 328,
- [BNXT_ULP_CLASS_HID_29af] = 329,
- [BNXT_ULP_CLASS_HID_159b] = 330,
- [BNXT_ULP_CLASS_HID_2995] = 331,
- [BNXT_ULP_CLASS_HID_298d] = 332,
- [BNXT_ULP_CLASS_HID_29f5] = 333,
- [BNXT_ULP_CLASS_HID_29ed] = 334,
- [BNXT_ULP_CLASS_HID_2997] = 335,
- [BNXT_ULP_CLASS_HID_15a3] = 336,
- [BNXT_ULP_CLASS_HID_298f] = 337,
- [BNXT_ULP_CLASS_HID_15bb] = 338,
- [BNXT_ULP_CLASS_HID_29f7] = 339,
- [BNXT_ULP_CLASS_HID_15c3] = 340,
- [BNXT_ULP_CLASS_HID_29ef] = 341,
- [BNXT_ULP_CLASS_HID_15db] = 342,
- [BNXT_ULP_CLASS_HID_1151] = 343,
- [BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_3612] = 345,
- [BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_243ca] = 347,
- [BNXT_ULP_CLASS_HID_20d8e] = 348,
- [BNXT_ULP_CLASS_HID_2e082] = 349,
- [BNXT_ULP_CLASS_HID_2ab46] = 350,
- [BNXT_ULP_CLASS_HID_25226] = 351,
- [BNXT_ULP_CLASS_HID_25cea] = 352,
- [BNXT_ULP_CLASS_HID_2c82a] = 353,
- [BNXT_ULP_CLASS_HID_2f9a2] = 354,
- [BNXT_ULP_CLASS_HID_23b56] = 355,
- [BNXT_ULP_CLASS_HID_205da] = 356,
- [BNXT_ULP_CLASS_HID_2d8ce] = 357,
- [BNXT_ULP_CLASS_HID_2a2d2] = 358,
- [BNXT_ULP_CLASS_HID_24a72] = 359,
- [BNXT_ULP_CLASS_HID_25476] = 360,
- [BNXT_ULP_CLASS_HID_2c076] = 361,
- [BNXT_ULP_CLASS_HID_2f1ee] = 362,
- [BNXT_ULP_CLASS_HID_20bb6] = 363,
- [BNXT_ULP_CLASS_HID_23d2e] = 364,
- [BNXT_ULP_CLASS_HID_2a96e] = 365,
- [BNXT_ULP_CLASS_HID_2dae6] = 366,
- [BNXT_ULP_CLASS_HID_25af2] = 367,
- [BNXT_ULP_CLASS_HID_24c6a] = 368,
- [BNXT_ULP_CLASS_HID_2c7aa] = 369,
- [BNXT_ULP_CLASS_HID_2c26e] = 370,
- [BNXT_ULP_CLASS_HID_203e2] = 371,
- [BNXT_ULP_CLASS_HID_2357a] = 372,
- [BNXT_ULP_CLASS_HID_2a0fa] = 373,
- [BNXT_ULP_CLASS_HID_2d272] = 374,
- [BNXT_ULP_CLASS_HID_2527e] = 375,
- [BNXT_ULP_CLASS_HID_243f6] = 376,
- [BNXT_ULP_CLASS_HID_2fff6] = 377,
- [BNXT_ULP_CLASS_HID_2e16e] = 378,
- [BNXT_ULP_CLASS_HID_2422d] = 379,
- [BNXT_ULP_CLASS_HID_20c69] = 380,
- [BNXT_ULP_CLASS_HID_2e165] = 381,
- [BNXT_ULP_CLASS_HID_2aaa1] = 382,
- [BNXT_ULP_CLASS_HID_253c1] = 383,
- [BNXT_ULP_CLASS_HID_25d0d] = 384,
- [BNXT_ULP_CLASS_HID_2c9cd] = 385,
- [BNXT_ULP_CLASS_HID_2f845] = 386,
- [BNXT_ULP_CLASS_HID_25afd] = 387,
- [BNXT_ULP_CLASS_HID_22439] = 388,
- [BNXT_ULP_CLASS_HID_290f9] = 389,
- [BNXT_ULP_CLASS_HID_2c371] = 390,
- [BNXT_ULP_CLASS_HID_24355] = 391,
- [BNXT_ULP_CLASS_HID_275dd] = 392,
- [BNXT_ULP_CLASS_HID_2e19d] = 393,
- [BNXT_ULP_CLASS_HID_2d015] = 394,
- [BNXT_ULP_CLASS_HID_2560d] = 395,
- [BNXT_ULP_CLASS_HID_21049] = 396,
- [BNXT_ULP_CLASS_HID_28c09] = 397,
- [BNXT_ULP_CLASS_HID_2be89] = 398,
- [BNXT_ULP_CLASS_HID_267a9] = 399,
- [BNXT_ULP_CLASS_HID_261ed] = 400,
- [BNXT_ULP_CLASS_HID_2ddad] = 401,
- [BNXT_ULP_CLASS_HID_2cc2d] = 402,
- [BNXT_ULP_CLASS_HID_26edd] = 403,
- [BNXT_ULP_CLASS_HID_22819] = 404,
- [BNXT_ULP_CLASS_HID_2a4d9] = 405,
- [BNXT_ULP_CLASS_HID_2d759] = 406,
- [BNXT_ULP_CLASS_HID_2573d] = 407,
- [BNXT_ULP_CLASS_HID_279bd] = 408,
- [BNXT_ULP_CLASS_HID_2f27d] = 409,
- [BNXT_ULP_CLASS_HID_2e4fd] = 410,
- [BNXT_ULP_CLASS_HID_24fbe] = 411,
- [BNXT_ULP_CLASS_HID_201fa] = 412,
- [BNXT_ULP_CLASS_HID_2ecf6] = 413,
- [BNXT_ULP_CLASS_HID_2a732] = 414,
- [BNXT_ULP_CLASS_HID_25e52] = 415,
- [BNXT_ULP_CLASS_HID_2509e] = 416,
- [BNXT_ULP_CLASS_HID_2c45e] = 417,
- [BNXT_ULP_CLASS_HID_2f5d6] = 418,
- [BNXT_ULP_CLASS_HID_23722] = 419,
- [BNXT_ULP_CLASS_HID_209ae] = 420,
- [BNXT_ULP_CLASS_HID_2d4ba] = 421,
- [BNXT_ULP_CLASS_HID_2aea6] = 422,
- [BNXT_ULP_CLASS_HID_24606] = 423,
- [BNXT_ULP_CLASS_HID_25802] = 424,
- [BNXT_ULP_CLASS_HID_2cc02] = 425,
- [BNXT_ULP_CLASS_HID_2fd9a] = 426,
- [BNXT_ULP_CLASS_HID_207c2] = 427,
- [BNXT_ULP_CLASS_HID_2315a] = 428,
- [BNXT_ULP_CLASS_HID_2a51a] = 429,
- [BNXT_ULP_CLASS_HID_2d692] = 430,
- [BNXT_ULP_CLASS_HID_25686] = 431,
- [BNXT_ULP_CLASS_HID_2401e] = 432,
- [BNXT_ULP_CLASS_HID_2cbde] = 433,
- [BNXT_ULP_CLASS_HID_2ce1a] = 434,
- [BNXT_ULP_CLASS_HID_20f96] = 435,
- [BNXT_ULP_CLASS_HID_2390e] = 436,
- [BNXT_ULP_CLASS_HID_2ac8e] = 437,
- [BNXT_ULP_CLASS_HID_2de06] = 438,
- [BNXT_ULP_CLASS_HID_25e0a] = 439,
- [BNXT_ULP_CLASS_HID_24f82] = 440,
- [BNXT_ULP_CLASS_HID_2f382] = 441,
- [BNXT_ULP_CLASS_HID_2ed1a] = 442,
- [BNXT_ULP_CLASS_HID_2576e] = 443,
- [BNXT_ULP_CLASS_HID_229aa] = 444,
- [BNXT_ULP_CLASS_HID_29d6a] = 445,
- [BNXT_ULP_CLASS_HID_2cee2] = 446,
- [BNXT_ULP_CLASS_HID_24ec6] = 447,
- [BNXT_ULP_CLASS_HID_2784e] = 448,
- [BNXT_ULP_CLASS_HID_2ec0e] = 449,
- [BNXT_ULP_CLASS_HID_2dd86] = 450,
- [BNXT_ULP_CLASS_HID_25f22] = 451,
- [BNXT_ULP_CLASS_HID_2112e] = 452,
- [BNXT_ULP_CLASS_HID_2852e] = 453,
- [BNXT_ULP_CLASS_HID_2b6a6] = 454,
- [BNXT_ULP_CLASS_HID_26d86] = 455,
- [BNXT_ULP_CLASS_HID_26002] = 456,
- [BNXT_ULP_CLASS_HID_2eb82] = 457,
- [BNXT_ULP_CLASS_HID_2c50a] = 458,
- [BNXT_ULP_CLASS_HID_22f82] = 459,
- [BNXT_ULP_CLASS_HID_2590a] = 460,
- [BNXT_ULP_CLASS_HID_2ccca] = 461,
- [BNXT_ULP_CLASS_HID_28706] = 462,
- [BNXT_ULP_CLASS_HID_27e46] = 463,
- [BNXT_ULP_CLASS_HID_26fce] = 464,
- [BNXT_ULP_CLASS_HID_2d38e] = 465,
- [BNXT_ULP_CLASS_HID_2d5ca] = 466,
- [BNXT_ULP_CLASS_HID_21706] = 467,
- [BNXT_ULP_CLASS_HID_2408e] = 468,
- [BNXT_ULP_CLASS_HID_2b48e] = 469,
- [BNXT_ULP_CLASS_HID_28e8a] = 470,
- [BNXT_ULP_CLASS_HID_2660a] = 471,
- [BNXT_ULP_CLASS_HID_25782] = 472,
- [BNXT_ULP_CLASS_HID_2db02] = 473,
- [BNXT_ULP_CLASS_HID_2dd8e] = 474,
- [BNXT_ULP_CLASS_HID_25b9e] = 475,
- [BNXT_ULP_CLASS_HID_21dda] = 476,
- [BNXT_ULP_CLASS_HID_2819a] = 477,
- [BNXT_ULP_CLASS_HID_2b31a] = 478,
- [BNXT_ULP_CLASS_HID_26a3a] = 479,
- [BNXT_ULP_CLASS_HID_26c7e] = 480,
- [BNXT_ULP_CLASS_HID_2d03e] = 481,
- [BNXT_ULP_CLASS_HID_2c1be] = 482,
- [BNXT_ULP_CLASS_HID_2430a] = 483,
- [BNXT_ULP_CLASS_HID_2058e] = 484,
- [BNXT_ULP_CLASS_HID_2890e] = 485,
- [BNXT_ULP_CLASS_HID_2ba8e] = 486,
- [BNXT_ULP_CLASS_HID_251ae] = 487,
- [BNXT_ULP_CLASS_HID_2542a] = 488,
- [BNXT_ULP_CLASS_HID_2dfaa] = 489,
- [BNXT_ULP_CLASS_HID_2c93a] = 490,
- [BNXT_ULP_CLASS_HID_213ca] = 491,
- [BNXT_ULP_CLASS_HID_24d5a] = 492,
- [BNXT_ULP_CLASS_HID_2b11a] = 493,
- [BNXT_ULP_CLASS_HID_28b4e] = 494,
- [BNXT_ULP_CLASS_HID_2624e] = 495,
- [BNXT_ULP_CLASS_HID_253de] = 496,
- [BNXT_ULP_CLASS_HID_2c79e] = 497,
- [BNXT_ULP_CLASS_HID_2d9da] = 498,
- [BNXT_ULP_CLASS_HID_21b1e] = 499,
- [BNXT_ULP_CLASS_HID_2350e] = 500,
- [BNXT_ULP_CLASS_HID_2b88e] = 501,
- [BNXT_ULP_CLASS_HID_2ea0e] = 502,
- [BNXT_ULP_CLASS_HID_26a0a] = 503,
- [BNXT_ULP_CLASS_HID_25b8a] = 504,
- [BNXT_ULP_CLASS_HID_2cf0a] = 505,
- [BNXT_ULP_CLASS_HID_2c18e] = 506,
- [BNXT_ULP_CLASS_HID_2634e] = 507,
- [BNXT_ULP_CLASS_HID_2258a] = 508,
- [BNXT_ULP_CLASS_HID_2a94a] = 509,
- [BNXT_ULP_CLASS_HID_2daca] = 510,
- [BNXT_ULP_CLASS_HID_25aae] = 511,
- [BNXT_ULP_CLASS_HID_2742e] = 512,
- [BNXT_ULP_CLASS_HID_2ffee] = 513,
- [BNXT_ULP_CLASS_HID_2e96e] = 514,
- [BNXT_ULP_CLASS_HID_26b0a] = 515,
- [BNXT_ULP_CLASS_HID_22d0e] = 516,
- [BNXT_ULP_CLASS_HID_2910e] = 517,
- [BNXT_ULP_CLASS_HID_2c28e] = 518,
- [BNXT_ULP_CLASS_HID_2422a] = 519,
- [BNXT_ULP_CLASS_HID_273aa] = 520,
- [BNXT_ULP_CLASS_HID_2e7aa] = 521,
- [BNXT_ULP_CLASS_HID_2d12a] = 522,
- [BNXT_ULP_CLASS_HID_23b8a] = 523,
- [BNXT_ULP_CLASS_HID_2550a] = 524,
- [BNXT_ULP_CLASS_HID_2d8ca] = 525,
- [BNXT_ULP_CLASS_HID_2930e] = 526,
- [BNXT_ULP_CLASS_HID_24a0e] = 527,
- [BNXT_ULP_CLASS_HID_24c4a] = 528,
- [BNXT_ULP_CLASS_HID_2ef4e] = 529,
- [BNXT_ULP_CLASS_HID_2e18a] = 530,
- [BNXT_ULP_CLASS_HID_2230e] = 531,
- [BNXT_ULP_CLASS_HID_25c8e] = 532,
- [BNXT_ULP_CLASS_HID_2c08e] = 533,
- [BNXT_ULP_CLASS_HID_29a8a] = 534,
- [BNXT_ULP_CLASS_HID_2718a] = 535,
- [BNXT_ULP_CLASS_HID_2630a] = 536,
- [BNXT_ULP_CLASS_HID_2d70a] = 537,
- [BNXT_ULP_CLASS_HID_2e90e] = 538,
- [BNXT_ULP_CLASS_HID_24e91] = 539,
- [BNXT_ULP_CLASS_HID_200d5] = 540,
- [BNXT_ULP_CLASS_HID_2edd9] = 541,
- [BNXT_ULP_CLASS_HID_2a61d] = 542,
- [BNXT_ULP_CLASS_HID_25f7d] = 543,
- [BNXT_ULP_CLASS_HID_251b1] = 544,
- [BNXT_ULP_CLASS_HID_2c571] = 545,
- [BNXT_ULP_CLASS_HID_2f4f9] = 546,
- [BNXT_ULP_CLASS_HID_25641] = 547,
- [BNXT_ULP_CLASS_HID_22885] = 548,
- [BNXT_ULP_CLASS_HID_29c45] = 549,
- [BNXT_ULP_CLASS_HID_2cfcd] = 550,
- [BNXT_ULP_CLASS_HID_24fe9] = 551,
- [BNXT_ULP_CLASS_HID_27961] = 552,
- [BNXT_ULP_CLASS_HID_2ed21] = 553,
- [BNXT_ULP_CLASS_HID_2dca9] = 554,
- [BNXT_ULP_CLASS_HID_25ab1] = 555,
- [BNXT_ULP_CLASS_HID_21cf5] = 556,
- [BNXT_ULP_CLASS_HID_280b5] = 557,
- [BNXT_ULP_CLASS_HID_2b235] = 558,
- [BNXT_ULP_CLASS_HID_26b15] = 559,
- [BNXT_ULP_CLASS_HID_26d51] = 560,
- [BNXT_ULP_CLASS_HID_2d111] = 561,
- [BNXT_ULP_CLASS_HID_2c091] = 562,
- [BNXT_ULP_CLASS_HID_26261] = 563,
- [BNXT_ULP_CLASS_HID_224a5] = 564,
- [BNXT_ULP_CLASS_HID_2a865] = 565,
- [BNXT_ULP_CLASS_HID_2dbe5] = 566,
- [BNXT_ULP_CLASS_HID_25b81] = 567,
- [BNXT_ULP_CLASS_HID_27501] = 568,
- [BNXT_ULP_CLASS_HID_2fec1] = 569,
- [BNXT_ULP_CLASS_HID_2e841] = 570,
- [BNXT_ULP_CLASS_HID_24085] = 571,
- [BNXT_ULP_CLASS_HID_21ac5] = 572,
- [BNXT_ULP_CLASS_HID_28e85] = 573,
- [BNXT_ULP_CLASS_HID_2b80d] = 574,
- [BNXT_ULP_CLASS_HID_2516d] = 575,
- [BNXT_ULP_CLASS_HID_26ba5] = 576,
- [BNXT_ULP_CLASS_HID_2df65] = 577,
- [BNXT_ULP_CLASS_HID_2ceed] = 578,
- [BNXT_ULP_CLASS_HID_26845] = 579,
- [BNXT_ULP_CLASS_HID_22285] = 580,
- [BNXT_ULP_CLASS_HID_29645] = 581,
- [BNXT_ULP_CLASS_HID_2c1cd] = 582,
- [BNXT_ULP_CLASS_HID_2418d] = 583,
- [BNXT_ULP_CLASS_HID_27365] = 584,
- [BNXT_ULP_CLASS_HID_2e725] = 585,
- [BNXT_ULP_CLASS_HID_2d6ad] = 586,
- [BNXT_ULP_CLASS_HID_25ca5] = 587,
- [BNXT_ULP_CLASS_HID_216e5] = 588,
- [BNXT_ULP_CLASS_HID_29aa5] = 589,
- [BNXT_ULP_CLASS_HID_2b425] = 590,
- [BNXT_ULP_CLASS_HID_26d05] = 591,
- [BNXT_ULP_CLASS_HID_26745] = 592,
- [BNXT_ULP_CLASS_HID_2eb05] = 593,
- [BNXT_ULP_CLASS_HID_2da85] = 594,
- [BNXT_ULP_CLASS_HID_20cc5] = 595,
- [BNXT_ULP_CLASS_HID_23ea5] = 596,
- [BNXT_ULP_CLASS_HID_2a265] = 597,
- [BNXT_ULP_CLASS_HID_2dde5] = 598,
- [BNXT_ULP_CLASS_HID_25da5] = 599,
- [BNXT_ULP_CLASS_HID_24f05] = 600,
- [BNXT_ULP_CLASS_HID_2f0c5] = 601,
- [BNXT_ULP_CLASS_HID_2e245] = 602,
- [BNXT_ULP_CLASS_HID_24d8b] = 603,
- [BNXT_ULP_CLASS_HID_207cf] = 604,
- [BNXT_ULP_CLASS_HID_28b8f] = 605,
- [BNXT_ULP_CLASS_HID_2a517] = 606,
- [BNXT_ULP_CLASS_HID_25277] = 607,
- [BNXT_ULP_CLASS_HID_254ab] = 608,
- [BNXT_ULP_CLASS_HID_2d86b] = 609,
- [BNXT_ULP_CLASS_HID_2cbf3] = 610,
- [BNXT_ULP_CLASS_HID_2554b] = 611,
- [BNXT_ULP_CLASS_HID_22f8f] = 612,
- [BNXT_ULP_CLASS_HID_2934f] = 613,
- [BNXT_ULP_CLASS_HID_2c2c7] = 614,
- [BNXT_ULP_CLASS_HID_242e3] = 615,
- [BNXT_ULP_CLASS_HID_27c6b] = 616,
- [BNXT_ULP_CLASS_HID_2e02b] = 617,
- [BNXT_ULP_CLASS_HID_2d3a3] = 618,
- [BNXT_ULP_CLASS_HID_259a3] = 619,
- [BNXT_ULP_CLASS_HID_213e7] = 620,
- [BNXT_ULP_CLASS_HID_287a7] = 621,
- [BNXT_ULP_CLASS_HID_2b137] = 622,
- [BNXT_ULP_CLASS_HID_26e17] = 623,
- [BNXT_ULP_CLASS_HID_26043] = 624,
- [BNXT_ULP_CLASS_HID_2d403] = 625,
- [BNXT_ULP_CLASS_HID_2c793] = 626,
- [BNXT_ULP_CLASS_HID_20827] = 627,
- [BNXT_ULP_CLASS_HID_23ba7] = 628,
- [BNXT_ULP_CLASS_HID_2af67] = 629,
- [BNXT_ULP_CLASS_HID_2dee7] = 630,
- [BNXT_ULP_CLASS_HID_25e83] = 631,
- [BNXT_ULP_CLASS_HID_24803] = 632,
- [BNXT_ULP_CLASS_HID_2fdc3] = 633,
- [BNXT_ULP_CLASS_HID_2ef43] = 634,
- [BNXT_ULP_CLASS_HID_247bf] = 635,
- [BNXT_ULP_CLASS_HID_219ff] = 636,
- [BNXT_ULP_CLASS_HID_28dbf] = 637,
- [BNXT_ULP_CLASS_HID_2bf07] = 638,
- [BNXT_ULP_CLASS_HID_25467] = 639,
- [BNXT_ULP_CLASS_HID_26e5f] = 640,
- [BNXT_ULP_CLASS_HID_2d21f] = 641,
- [BNXT_ULP_CLASS_HID_2cde7] = 642,
- [BNXT_ULP_CLASS_HID_26f6f] = 643,
- [BNXT_ULP_CLASS_HID_221af] = 644,
- [BNXT_ULP_CLASS_HID_2956f] = 645,
- [BNXT_ULP_CLASS_HID_2c4c7] = 646,
- [BNXT_ULP_CLASS_HID_24487] = 647,
- [BNXT_ULP_CLASS_HID_2760f] = 648,
- [BNXT_ULP_CLASS_HID_2fbcf] = 649,
- [BNXT_ULP_CLASS_HID_2d5a7] = 650,
- [BNXT_ULP_CLASS_HID_25357] = 651,
- [BNXT_ULP_CLASS_HID_21597] = 652,
- [BNXT_ULP_CLASS_HID_29957] = 653,
- [BNXT_ULP_CLASS_HID_2cb27] = 654,
- [BNXT_ULP_CLASS_HID_248f7] = 655,
- [BNXT_ULP_CLASS_HID_27a77] = 656,
- [BNXT_ULP_CLASS_HID_2ee37] = 657,
- [BNXT_ULP_CLASS_HID_2d987] = 658,
- [BNXT_ULP_CLASS_HID_203c7] = 659,
- [BNXT_ULP_CLASS_HID_23d47] = 660,
- [BNXT_ULP_CLASS_HID_2a107] = 661,
- [BNXT_ULP_CLASS_HID_2d0e7] = 662,
- [BNXT_ULP_CLASS_HID_250a7] = 663,
- [BNXT_ULP_CLASS_HID_24227] = 664,
- [BNXT_ULP_CLASS_HID_2f7e7] = 665,
- [BNXT_ULP_CLASS_HID_2c827] = 666,
- [BNXT_ULP_CLASS_HID_25422] = 667,
- [BNXT_ULP_CLASS_HID_21a66] = 668,
- [BNXT_ULP_CLASS_HID_2f76a] = 669,
- [BNXT_ULP_CLASS_HID_2bcae] = 670,
- [BNXT_ULP_CLASS_HID_245ce] = 671,
- [BNXT_ULP_CLASS_HID_24b02] = 672,
- [BNXT_ULP_CLASS_HID_2dfc2] = 673,
- [BNXT_ULP_CLASS_HID_2ee4a] = 674,
- [BNXT_ULP_CLASS_HID_22cbe] = 675,
- [BNXT_ULP_CLASS_HID_21232] = 676,
- [BNXT_ULP_CLASS_HID_2cf26] = 677,
- [BNXT_ULP_CLASS_HID_2b53a] = 678,
- [BNXT_ULP_CLASS_HID_25d9a] = 679,
- [BNXT_ULP_CLASS_HID_2439e] = 680,
- [BNXT_ULP_CLASS_HID_2d79e] = 681,
- [BNXT_ULP_CLASS_HID_2e606] = 682,
- [BNXT_ULP_CLASS_HID_21c5e] = 683,
- [BNXT_ULP_CLASS_HID_22ac6] = 684,
- [BNXT_ULP_CLASS_HID_2be86] = 685,
- [BNXT_ULP_CLASS_HID_2cd0e] = 686,
- [BNXT_ULP_CLASS_HID_24d1a] = 687,
- [BNXT_ULP_CLASS_HID_25b82] = 688,
- [BNXT_ULP_CLASS_HID_2d042] = 689,
- [BNXT_ULP_CLASS_HID_2d586] = 690,
- [BNXT_ULP_CLASS_HID_2140a] = 691,
- [BNXT_ULP_CLASS_HID_22292] = 692,
- [BNXT_ULP_CLASS_HID_2b712] = 693,
- [BNXT_ULP_CLASS_HID_2c59a] = 694,
- [BNXT_ULP_CLASS_HID_24596] = 695,
- [BNXT_ULP_CLASS_HID_2541e] = 696,
- [BNXT_ULP_CLASS_HID_2e81e] = 697,
- [BNXT_ULP_CLASS_HID_2f686] = 698,
- [BNXT_ULP_CLASS_HID_24cf2] = 699,
- [BNXT_ULP_CLASS_HID_23236] = 700,
- [BNXT_ULP_CLASS_HID_286f6] = 701,
- [BNXT_ULP_CLASS_HID_2d57e] = 702,
- [BNXT_ULP_CLASS_HID_2555a] = 703,
- [BNXT_ULP_CLASS_HID_263d2] = 704,
- [BNXT_ULP_CLASS_HID_2f792] = 705,
- [BNXT_ULP_CLASS_HID_2c61a] = 706,
- [BNXT_ULP_CLASS_HID_244be] = 707,
- [BNXT_ULP_CLASS_HID_20ab2] = 708,
- [BNXT_ULP_CLASS_HID_29eb2] = 709,
- [BNXT_ULP_CLASS_HID_2ad3a] = 710,
- [BNXT_ULP_CLASS_HID_2761a] = 711,
- [BNXT_ULP_CLASS_HID_27b9e] = 712,
- [BNXT_ULP_CLASS_HID_2f01e] = 713,
- [BNXT_ULP_CLASS_HID_2de96] = 714,
- [BNXT_ULP_CLASS_HID_2341e] = 715,
- [BNXT_ULP_CLASS_HID_24296] = 716,
- [BNXT_ULP_CLASS_HID_2d756] = 717,
- [BNXT_ULP_CLASS_HID_29c9a] = 718,
- [BNXT_ULP_CLASS_HID_265da] = 719,
- [BNXT_ULP_CLASS_HID_27452] = 720,
- [BNXT_ULP_CLASS_HID_2c812] = 721,
- [BNXT_ULP_CLASS_HID_2ce56] = 722,
- [BNXT_ULP_CLASS_HID_20c9a] = 723,
- [BNXT_ULP_CLASS_HID_25b12] = 724,
- [BNXT_ULP_CLASS_HID_2af12] = 725,
- [BNXT_ULP_CLASS_HID_29516] = 726,
- [BNXT_ULP_CLASS_HID_27d96] = 727,
- [BNXT_ULP_CLASS_HID_24c1e] = 728,
- [BNXT_ULP_CLASS_HID_2c09e] = 729,
- [BNXT_ULP_CLASS_HID_2c612] = 730,
- [BNXT_ULP_CLASS_HID_24002] = 731,
- [BNXT_ULP_CLASS_HID_20646] = 732,
- [BNXT_ULP_CLASS_HID_29a06] = 733,
- [BNXT_ULP_CLASS_HID_2a886] = 734,
- [BNXT_ULP_CLASS_HID_271a6] = 735,
- [BNXT_ULP_CLASS_HID_277e2] = 736,
- [BNXT_ULP_CLASS_HID_2cba2] = 737,
- [BNXT_ULP_CLASS_HID_2da22] = 738,
- [BNXT_ULP_CLASS_HID_25896] = 739,
- [BNXT_ULP_CLASS_HID_21e12] = 740,
- [BNXT_ULP_CLASS_HID_29292] = 741,
- [BNXT_ULP_CLASS_HID_2a112] = 742,
- [BNXT_ULP_CLASS_HID_24a32] = 743,
- [BNXT_ULP_CLASS_HID_24fb6] = 744,
- [BNXT_ULP_CLASS_HID_2c436] = 745,
- [BNXT_ULP_CLASS_HID_2d2a6] = 746,
- [BNXT_ULP_CLASS_HID_20856] = 747,
- [BNXT_ULP_CLASS_HID_256c6] = 748,
- [BNXT_ULP_CLASS_HID_2aa86] = 749,
- [BNXT_ULP_CLASS_HID_290d2] = 750,
- [BNXT_ULP_CLASS_HID_279d2] = 751,
- [BNXT_ULP_CLASS_HID_24842] = 752,
- [BNXT_ULP_CLASS_HID_2dc02] = 753,
- [BNXT_ULP_CLASS_HID_2c246] = 754,
- [BNXT_ULP_CLASS_HID_20082] = 755,
- [BNXT_ULP_CLASS_HID_22e92] = 756,
- [BNXT_ULP_CLASS_HID_2a312] = 757,
- [BNXT_ULP_CLASS_HID_2f192] = 758,
- [BNXT_ULP_CLASS_HID_27196] = 759,
- [BNXT_ULP_CLASS_HID_24016] = 760,
- [BNXT_ULP_CLASS_HID_2d496] = 761,
- [BNXT_ULP_CLASS_HID_2da12] = 762,
- [BNXT_ULP_CLASS_HID_278d2] = 763,
- [BNXT_ULP_CLASS_HID_23e16] = 764,
- [BNXT_ULP_CLASS_HID_2b2d6] = 765,
- [BNXT_ULP_CLASS_HID_2c156] = 766,
- [BNXT_ULP_CLASS_HID_24132] = 767,
- [BNXT_ULP_CLASS_HID_26fb2] = 768,
- [BNXT_ULP_CLASS_HID_2e472] = 769,
- [BNXT_ULP_CLASS_HID_2f2f2] = 770,
- [BNXT_ULP_CLASS_HID_27096] = 771,
- [BNXT_ULP_CLASS_HID_23692] = 772,
- [BNXT_ULP_CLASS_HID_28a92] = 773,
- [BNXT_ULP_CLASS_HID_2d912] = 774,
- [BNXT_ULP_CLASS_HID_259b6] = 775,
- [BNXT_ULP_CLASS_HID_26836] = 776,
- [BNXT_ULP_CLASS_HID_2fc36] = 777,
- [BNXT_ULP_CLASS_HID_2cab6] = 778,
- [BNXT_ULP_CLASS_HID_22016] = 779,
- [BNXT_ULP_CLASS_HID_24e96] = 780,
- [BNXT_ULP_CLASS_HID_2c356] = 781,
- [BNXT_ULP_CLASS_HID_28892] = 782,
- [BNXT_ULP_CLASS_HID_25192] = 783,
- [BNXT_ULP_CLASS_HID_257d6] = 784,
- [BNXT_ULP_CLASS_HID_2f4d2] = 785,
- [BNXT_ULP_CLASS_HID_2fa16] = 786,
- [BNXT_ULP_CLASS_HID_23892] = 787,
- [BNXT_ULP_CLASS_HID_24712] = 788,
- [BNXT_ULP_CLASS_HID_2db12] = 789,
- [BNXT_ULP_CLASS_HID_28116] = 790,
- [BNXT_ULP_CLASS_HID_26a16] = 791,
- [BNXT_ULP_CLASS_HID_27896] = 792,
- [BNXT_ULP_CLASS_HID_2cc96] = 793,
- [BNXT_ULP_CLASS_HID_2f292] = 794,
- [BNXT_ULP_CLASS_HID_24b05] = 795,
- [BNXT_ULP_CLASS_HID_20541] = 796,
- [BNXT_ULP_CLASS_HID_2e84d] = 797,
- [BNXT_ULP_CLASS_HID_2a389] = 798,
- [BNXT_ULP_CLASS_HID_25ae9] = 799,
- [BNXT_ULP_CLASS_HID_25425] = 800,
- [BNXT_ULP_CLASS_HID_2c0e5] = 801,
- [BNXT_ULP_CLASS_HID_2f16d] = 802,
- [BNXT_ULP_CLASS_HID_253d5] = 803,
- [BNXT_ULP_CLASS_HID_22d11] = 804,
- [BNXT_ULP_CLASS_HID_299d1] = 805,
- [BNXT_ULP_CLASS_HID_2ca59] = 806,
- [BNXT_ULP_CLASS_HID_24a7d] = 807,
- [BNXT_ULP_CLASS_HID_27cf5] = 808,
- [BNXT_ULP_CLASS_HID_2e8b5] = 809,
- [BNXT_ULP_CLASS_HID_2d93d] = 810,
- [BNXT_ULP_CLASS_HID_25f25] = 811,
- [BNXT_ULP_CLASS_HID_21961] = 812,
- [BNXT_ULP_CLASS_HID_28521] = 813,
- [BNXT_ULP_CLASS_HID_2b7a1] = 814,
- [BNXT_ULP_CLASS_HID_26e81] = 815,
- [BNXT_ULP_CLASS_HID_268c5] = 816,
- [BNXT_ULP_CLASS_HID_2d485] = 817,
- [BNXT_ULP_CLASS_HID_2c505] = 818,
- [BNXT_ULP_CLASS_HID_267f5] = 819,
- [BNXT_ULP_CLASS_HID_22131] = 820,
- [BNXT_ULP_CLASS_HID_2adf1] = 821,
- [BNXT_ULP_CLASS_HID_2de71] = 822,
- [BNXT_ULP_CLASS_HID_25e15] = 823,
- [BNXT_ULP_CLASS_HID_27095] = 824,
- [BNXT_ULP_CLASS_HID_2fb55] = 825,
- [BNXT_ULP_CLASS_HID_2edd5] = 826,
- [BNXT_ULP_CLASS_HID_24511] = 827,
- [BNXT_ULP_CLASS_HID_21f51] = 828,
- [BNXT_ULP_CLASS_HID_28b11] = 829,
- [BNXT_ULP_CLASS_HID_2bd99] = 830,
- [BNXT_ULP_CLASS_HID_254f9] = 831,
- [BNXT_ULP_CLASS_HID_26e31] = 832,
- [BNXT_ULP_CLASS_HID_2daf1] = 833,
- [BNXT_ULP_CLASS_HID_2cb79] = 834,
- [BNXT_ULP_CLASS_HID_26dd1] = 835,
- [BNXT_ULP_CLASS_HID_22711] = 836,
- [BNXT_ULP_CLASS_HID_293d1] = 837,
- [BNXT_ULP_CLASS_HID_2c459] = 838,
- [BNXT_ULP_CLASS_HID_24419] = 839,
- [BNXT_ULP_CLASS_HID_276f1] = 840,
- [BNXT_ULP_CLASS_HID_2e2b1] = 841,
- [BNXT_ULP_CLASS_HID_2d339] = 842,
- [BNXT_ULP_CLASS_HID_25931] = 843,
- [BNXT_ULP_CLASS_HID_21371] = 844,
- [BNXT_ULP_CLASS_HID_29f31] = 845,
- [BNXT_ULP_CLASS_HID_2b1b1] = 846,
- [BNXT_ULP_CLASS_HID_26891] = 847,
- [BNXT_ULP_CLASS_HID_262d1] = 848,
- [BNXT_ULP_CLASS_HID_2ee91] = 849,
- [BNXT_ULP_CLASS_HID_2df11] = 850,
- [BNXT_ULP_CLASS_HID_20951] = 851,
- [BNXT_ULP_CLASS_HID_23b31] = 852,
- [BNXT_ULP_CLASS_HID_2a7f1] = 853,
- [BNXT_ULP_CLASS_HID_2d871] = 854,
- [BNXT_ULP_CLASS_HID_25831] = 855,
- [BNXT_ULP_CLASS_HID_24a91] = 856,
- [BNXT_ULP_CLASS_HID_2f551] = 857,
- [BNXT_ULP_CLASS_HID_2e7d1] = 858,
- [BNXT_ULP_CLASS_HID_2481f] = 859,
- [BNXT_ULP_CLASS_HID_2025b] = 860,
- [BNXT_ULP_CLASS_HID_28e1b] = 861,
- [BNXT_ULP_CLASS_HID_2a083] = 862,
- [BNXT_ULP_CLASS_HID_257e3] = 863,
- [BNXT_ULP_CLASS_HID_2513f] = 864,
- [BNXT_ULP_CLASS_HID_2ddff] = 865,
- [BNXT_ULP_CLASS_HID_2ce67] = 866,
- [BNXT_ULP_CLASS_HID_250df] = 867,
- [BNXT_ULP_CLASS_HID_22a1b] = 868,
- [BNXT_ULP_CLASS_HID_296db] = 869,
- [BNXT_ULP_CLASS_HID_2c753] = 870,
- [BNXT_ULP_CLASS_HID_24777] = 871,
- [BNXT_ULP_CLASS_HID_279ff] = 872,
- [BNXT_ULP_CLASS_HID_2e5bf] = 873,
- [BNXT_ULP_CLASS_HID_2d637] = 874,
- [BNXT_ULP_CLASS_HID_25c37] = 875,
- [BNXT_ULP_CLASS_HID_21673] = 876,
- [BNXT_ULP_CLASS_HID_28233] = 877,
- [BNXT_ULP_CLASS_HID_2b4a3] = 878,
- [BNXT_ULP_CLASS_HID_26b83] = 879,
- [BNXT_ULP_CLASS_HID_265d7] = 880,
- [BNXT_ULP_CLASS_HID_2d197] = 881,
- [BNXT_ULP_CLASS_HID_2c207] = 882,
- [BNXT_ULP_CLASS_HID_20db3] = 883,
- [BNXT_ULP_CLASS_HID_23e33] = 884,
- [BNXT_ULP_CLASS_HID_2aaf3] = 885,
- [BNXT_ULP_CLASS_HID_2db73] = 886,
- [BNXT_ULP_CLASS_HID_25b17] = 887,
- [BNXT_ULP_CLASS_HID_24d97] = 888,
- [BNXT_ULP_CLASS_HID_2f857] = 889,
- [BNXT_ULP_CLASS_HID_2ead7] = 890,
- [BNXT_ULP_CLASS_HID_2422b] = 891,
- [BNXT_ULP_CLASS_HID_21c6b] = 892,
- [BNXT_ULP_CLASS_HID_2882b] = 893,
- [BNXT_ULP_CLASS_HID_2ba93] = 894,
- [BNXT_ULP_CLASS_HID_251f3] = 895,
- [BNXT_ULP_CLASS_HID_26bcb] = 896,
- [BNXT_ULP_CLASS_HID_2d78b] = 897,
- [BNXT_ULP_CLASS_HID_2c873] = 898,
- [BNXT_ULP_CLASS_HID_26afb] = 899,
- [BNXT_ULP_CLASS_HID_2243b] = 900,
- [BNXT_ULP_CLASS_HID_290fb] = 901,
- [BNXT_ULP_CLASS_HID_2c153] = 902,
- [BNXT_ULP_CLASS_HID_24113] = 903,
- [BNXT_ULP_CLASS_HID_2739b] = 904,
- [BNXT_ULP_CLASS_HID_2fe5b] = 905,
- [BNXT_ULP_CLASS_HID_2d033] = 906,
- [BNXT_ULP_CLASS_HID_256c3] = 907,
- [BNXT_ULP_CLASS_HID_21003] = 908,
- [BNXT_ULP_CLASS_HID_29cc3] = 909,
- [BNXT_ULP_CLASS_HID_2ceb3] = 910,
- [BNXT_ULP_CLASS_HID_24d63] = 911,
- [BNXT_ULP_CLASS_HID_27fe3] = 912,
- [BNXT_ULP_CLASS_HID_2eba3] = 913,
- [BNXT_ULP_CLASS_HID_2dc13] = 914,
- [BNXT_ULP_CLASS_HID_20653] = 915,
- [BNXT_ULP_CLASS_HID_238d3] = 916,
- [BNXT_ULP_CLASS_HID_2a493] = 917,
- [BNXT_ULP_CLASS_HID_2d573] = 918,
- [BNXT_ULP_CLASS_HID_25533] = 919,
- [BNXT_ULP_CLASS_HID_247b3] = 920,
- [BNXT_ULP_CLASS_HID_2f273] = 921,
- [BNXT_ULP_CLASS_HID_2cdb3] = 922,
- [BNXT_ULP_CLASS_HID_25c7d] = 923,
- [BNXT_ULP_CLASS_HID_21239] = 924,
- [BNXT_ULP_CLASS_HID_2ff35] = 925,
- [BNXT_ULP_CLASS_HID_2b4f1] = 926,
- [BNXT_ULP_CLASS_HID_24d91] = 927,
- [BNXT_ULP_CLASS_HID_2435d] = 928,
- [BNXT_ULP_CLASS_HID_2d79d] = 929,
- [BNXT_ULP_CLASS_HID_2e615] = 930,
- [BNXT_ULP_CLASS_HID_244ad] = 931,
- [BNXT_ULP_CLASS_HID_23a69] = 932,
- [BNXT_ULP_CLASS_HID_28ea9] = 933,
- [BNXT_ULP_CLASS_HID_2dd21] = 934,
- [BNXT_ULP_CLASS_HID_25d05] = 935,
- [BNXT_ULP_CLASS_HID_26b8d] = 936,
- [BNXT_ULP_CLASS_HID_2ffcd] = 937,
- [BNXT_ULP_CLASS_HID_2ce45] = 938,
- [BNXT_ULP_CLASS_HID_2485d] = 939,
- [BNXT_ULP_CLASS_HID_20e19] = 940,
- [BNXT_ULP_CLASS_HID_29259] = 941,
- [BNXT_ULP_CLASS_HID_2a0d9] = 942,
- [BNXT_ULP_CLASS_HID_279f9] = 943,
- [BNXT_ULP_CLASS_HID_27fbd] = 944,
- [BNXT_ULP_CLASS_HID_2c3fd] = 945,
- [BNXT_ULP_CLASS_HID_2d27d] = 946,
- [BNXT_ULP_CLASS_HID_2708d] = 947,
- [BNXT_ULP_CLASS_HID_23649] = 948,
- [BNXT_ULP_CLASS_HID_2ba89] = 949,
- [BNXT_ULP_CLASS_HID_2c909] = 950,
- [BNXT_ULP_CLASS_HID_2496d] = 951,
- [BNXT_ULP_CLASS_HID_267ed] = 952,
- [BNXT_ULP_CLASS_HID_2ec2d] = 953,
- [BNXT_ULP_CLASS_HID_2faad] = 954,
- [BNXT_ULP_CLASS_HID_34c6] = 955,
- [BNXT_ULP_CLASS_HID_0c22] = 956,
- [BNXT_ULP_CLASS_HID_1cbe] = 957,
- [BNXT_ULP_CLASS_HID_179a] = 958,
- [BNXT_ULP_CLASS_HID_59be] = 959,
- [BNXT_ULP_CLASS_HID_515a] = 960,
- [BNXT_ULP_CLASS_HID_1c72] = 961,
- [BNXT_ULP_CLASS_HID_171e] = 962,
- [BNXT_ULP_CLASS_HID_19c8] = 963,
- [BNXT_ULP_CLASS_HID_112c] = 964,
- [BNXT_ULP_CLASS_HID_4d68] = 965,
- [BNXT_ULP_CLASS_HID_444c] = 966,
- [BNXT_ULP_CLASS_HID_0e8c] = 967,
- [BNXT_ULP_CLASS_HID_09e0] = 968,
- [BNXT_ULP_CLASS_HID_1af0] = 969,
- [BNXT_ULP_CLASS_HID_15d4] = 970,
- [BNXT_ULP_CLASS_HID_1dd0] = 971,
- [BNXT_ULP_CLASS_HID_14f4] = 972,
- [BNXT_ULP_CLASS_HID_70b0] = 973,
- [BNXT_ULP_CLASS_HID_4854] = 974,
- [BNXT_ULP_CLASS_HID_3dd4] = 975,
- [BNXT_ULP_CLASS_HID_34f8] = 976,
- [BNXT_ULP_CLASS_HID_09e8] = 977,
- [BNXT_ULP_CLASS_HID_008c] = 978,
- [BNXT_ULP_CLASS_HID_34e6] = 979,
- [BNXT_ULP_CLASS_HID_0c02] = 980,
- [BNXT_ULP_CLASS_HID_1c9e] = 981,
- [BNXT_ULP_CLASS_HID_17ba] = 982,
- [BNXT_ULP_CLASS_HID_429e] = 983,
- [BNXT_ULP_CLASS_HID_5dba] = 984,
- [BNXT_ULP_CLASS_HID_2a16] = 985,
- [BNXT_ULP_CLASS_HID_2532] = 986,
- [BNXT_ULP_CLASS_HID_2da2] = 987,
- [BNXT_ULP_CLASS_HID_24fe] = 988,
- [BNXT_ULP_CLASS_HID_355a] = 989,
- [BNXT_ULP_CLASS_HID_0c76] = 990,
- [BNXT_ULP_CLASS_HID_13e6] = 991,
- [BNXT_ULP_CLASS_HID_7276] = 992,
- [BNXT_ULP_CLASS_HID_42d2] = 993,
- [BNXT_ULP_CLASS_HID_5dee] = 994,
- [BNXT_ULP_CLASS_HID_59de] = 995,
- [BNXT_ULP_CLASS_HID_513a] = 996,
- [BNXT_ULP_CLASS_HID_1c12] = 997,
- [BNXT_ULP_CLASS_HID_177e] = 998,
- [BNXT_ULP_CLASS_HID_0e92] = 999,
- [BNXT_ULP_CLASS_HID_09fe] = 1000,
- [BNXT_ULP_CLASS_HID_5c1a] = 1001,
- [BNXT_ULP_CLASS_HID_5746] = 1002,
- [BNXT_ULP_CLASS_HID_79da] = 1003,
- [BNXT_ULP_CLASS_HID_7106] = 1004,
- [BNXT_ULP_CLASS_HID_3c1e] = 1005,
- [BNXT_ULP_CLASS_HID_377a] = 1006,
- [BNXT_ULP_CLASS_HID_2e9e] = 1007,
- [BNXT_ULP_CLASS_HID_29fa] = 1008,
- [BNXT_ULP_CLASS_HID_14d2] = 1009,
- [BNXT_ULP_CLASS_HID_7742] = 1010,
- [BNXT_ULP_CLASS_HID_3706] = 1011,
- [BNXT_ULP_CLASS_HID_0fe2] = 1012,
- [BNXT_ULP_CLASS_HID_1f7e] = 1013,
- [BNXT_ULP_CLASS_HID_145a] = 1014,
- [BNXT_ULP_CLASS_HID_417e] = 1015,
- [BNXT_ULP_CLASS_HID_5e5a] = 1016,
- [BNXT_ULP_CLASS_HID_29f6] = 1017,
- [BNXT_ULP_CLASS_HID_26d2] = 1018,
- [BNXT_ULP_CLASS_HID_2e42] = 1019,
- [BNXT_ULP_CLASS_HID_271e] = 1020,
- [BNXT_ULP_CLASS_HID_36ba] = 1021,
- [BNXT_ULP_CLASS_HID_0f96] = 1022,
- [BNXT_ULP_CLASS_HID_1006] = 1023,
- [BNXT_ULP_CLASS_HID_7196] = 1024,
- [BNXT_ULP_CLASS_HID_4132] = 1025,
- [BNXT_ULP_CLASS_HID_5e0e] = 1026,
- [BNXT_ULP_CLASS_HID_59fe] = 1027,
- [BNXT_ULP_CLASS_HID_511a] = 1028,
- [BNXT_ULP_CLASS_HID_1c32] = 1029,
- [BNXT_ULP_CLASS_HID_175e] = 1030,
- [BNXT_ULP_CLASS_HID_0eb2] = 1031,
- [BNXT_ULP_CLASS_HID_09de] = 1032,
- [BNXT_ULP_CLASS_HID_5c3a] = 1033,
- [BNXT_ULP_CLASS_HID_5766] = 1034,
- [BNXT_ULP_CLASS_HID_79fa] = 1035,
- [BNXT_ULP_CLASS_HID_7126] = 1036,
- [BNXT_ULP_CLASS_HID_3c3e] = 1037,
- [BNXT_ULP_CLASS_HID_375a] = 1038,
- [BNXT_ULP_CLASS_HID_2ebe] = 1039,
- [BNXT_ULP_CLASS_HID_29da] = 1040,
- [BNXT_ULP_CLASS_HID_14f2] = 1041,
- [BNXT_ULP_CLASS_HID_7762] = 1042,
- [BNXT_ULP_CLASS_HID_19e8] = 1043,
- [BNXT_ULP_CLASS_HID_110c] = 1044,
- [BNXT_ULP_CLASS_HID_4d48] = 1045,
- [BNXT_ULP_CLASS_HID_446c] = 1046,
- [BNXT_ULP_CLASS_HID_0eac] = 1047,
- [BNXT_ULP_CLASS_HID_09c0] = 1048,
- [BNXT_ULP_CLASS_HID_1ad0] = 1049,
- [BNXT_ULP_CLASS_HID_15f4] = 1050,
- [BNXT_ULP_CLASS_HID_39ec] = 1051,
- [BNXT_ULP_CLASS_HID_3100] = 1052,
- [BNXT_ULP_CLASS_HID_0210] = 1053,
- [BNXT_ULP_CLASS_HID_1d34] = 1054,
- [BNXT_ULP_CLASS_HID_2ea0] = 1055,
- [BNXT_ULP_CLASS_HID_29c4] = 1056,
- [BNXT_ULP_CLASS_HID_3ad4] = 1057,
- [BNXT_ULP_CLASS_HID_35e8] = 1058,
- [BNXT_ULP_CLASS_HID_5d80] = 1059,
- [BNXT_ULP_CLASS_HID_54a4] = 1060,
- [BNXT_ULP_CLASS_HID_29b4] = 1061,
- [BNXT_ULP_CLASS_HID_20c8] = 1062,
- [BNXT_ULP_CLASS_HID_7244] = 1063,
- [BNXT_ULP_CLASS_HID_4d98] = 1064,
- [BNXT_ULP_CLASS_HID_5e68] = 1065,
- [BNXT_ULP_CLASS_HID_598c] = 1066,
- [BNXT_ULP_CLASS_HID_1248] = 1067,
- [BNXT_ULP_CLASS_HID_74d8] = 1068,
- [BNXT_ULP_CLASS_HID_49a8] = 1069,
- [BNXT_ULP_CLASS_HID_40cc] = 1070,
- [BNXT_ULP_CLASS_HID_0b0c] = 1071,
- [BNXT_ULP_CLASS_HID_0220] = 1072,
- [BNXT_ULP_CLASS_HID_1730] = 1073,
- [BNXT_ULP_CLASS_HID_7980] = 1074,
- [BNXT_ULP_CLASS_HID_1db0] = 1075,
- [BNXT_ULP_CLASS_HID_1494] = 1076,
- [BNXT_ULP_CLASS_HID_70d0] = 1077,
- [BNXT_ULP_CLASS_HID_4834] = 1078,
- [BNXT_ULP_CLASS_HID_3db4] = 1079,
- [BNXT_ULP_CLASS_HID_3498] = 1080,
- [BNXT_ULP_CLASS_HID_0988] = 1081,
- [BNXT_ULP_CLASS_HID_00ec] = 1082,
- [BNXT_ULP_CLASS_HID_23f44] = 1083,
- [BNXT_ULP_CLASS_HID_236a8] = 1084,
- [BNXT_ULP_CLASS_HID_20b58] = 1085,
- [BNXT_ULP_CLASS_HID_202bc] = 1086,
- [BNXT_ULP_CLASS_HID_25f48] = 1087,
- [BNXT_ULP_CLASS_HID_256ac] = 1088,
- [BNXT_ULP_CLASS_HID_22b5c] = 1089,
- [BNXT_ULP_CLASS_HID_22280] = 1090,
- [BNXT_ULP_CLASS_HID_14000] = 1091,
- [BNXT_ULP_CLASS_HID_15b64] = 1092,
- [BNXT_ULP_CLASS_HID_12c14] = 1093,
- [BNXT_ULP_CLASS_HID_12778] = 1094,
- [BNXT_ULP_CLASS_HID_118f8] = 1095,
- [BNXT_ULP_CLASS_HID_113dc] = 1096,
- [BNXT_ULP_CLASS_HID_14c18] = 1097,
- [BNXT_ULP_CLASS_HID_1477c] = 1098,
- [BNXT_ULP_CLASS_HID_31a88] = 1099,
- [BNXT_ULP_CLASS_HID_315ec] = 1100,
- [BNXT_ULP_CLASS_HID_34e28] = 1101,
- [BNXT_ULP_CLASS_HID_3490c] = 1102,
- [BNXT_ULP_CLASS_HID_33a8c] = 1103,
- [BNXT_ULP_CLASS_HID_335f0] = 1104,
- [BNXT_ULP_CLASS_HID_306e0] = 1105,
- [BNXT_ULP_CLASS_HID_301c4] = 1106,
- [BNXT_ULP_CLASS_HID_1a08] = 1107,
- [BNXT_ULP_CLASS_HID_12ec] = 1108,
- [BNXT_ULP_CLASS_HID_4ea8] = 1109,
- [BNXT_ULP_CLASS_HID_478c] = 1110,
- [BNXT_ULP_CLASS_HID_0d4c] = 1111,
- [BNXT_ULP_CLASS_HID_0a20] = 1112,
- [BNXT_ULP_CLASS_HID_1930] = 1113,
- [BNXT_ULP_CLASS_HID_1614] = 1114,
- [BNXT_ULP_CLASS_HID_3a0c] = 1115,
- [BNXT_ULP_CLASS_HID_32e0] = 1116,
- [BNXT_ULP_CLASS_HID_01f0] = 1117,
- [BNXT_ULP_CLASS_HID_1ed4] = 1118,
- [BNXT_ULP_CLASS_HID_2d40] = 1119,
- [BNXT_ULP_CLASS_HID_2a24] = 1120,
- [BNXT_ULP_CLASS_HID_3934] = 1121,
- [BNXT_ULP_CLASS_HID_3608] = 1122,
- [BNXT_ULP_CLASS_HID_5e60] = 1123,
- [BNXT_ULP_CLASS_HID_5744] = 1124,
- [BNXT_ULP_CLASS_HID_2a54] = 1125,
- [BNXT_ULP_CLASS_HID_2328] = 1126,
- [BNXT_ULP_CLASS_HID_71a4] = 1127,
- [BNXT_ULP_CLASS_HID_4e78] = 1128,
- [BNXT_ULP_CLASS_HID_5d88] = 1129,
- [BNXT_ULP_CLASS_HID_5a6c] = 1130,
- [BNXT_ULP_CLASS_HID_11a8] = 1131,
- [BNXT_ULP_CLASS_HID_7738] = 1132,
- [BNXT_ULP_CLASS_HID_4a48] = 1133,
- [BNXT_ULP_CLASS_HID_432c] = 1134,
- [BNXT_ULP_CLASS_HID_08ec] = 1135,
- [BNXT_ULP_CLASS_HID_01c0] = 1136,
- [BNXT_ULP_CLASS_HID_14d0] = 1137,
- [BNXT_ULP_CLASS_HID_7a60] = 1138,
- [BNXT_ULP_CLASS_HID_1d90] = 1139,
- [BNXT_ULP_CLASS_HID_14b4] = 1140,
- [BNXT_ULP_CLASS_HID_70f0] = 1141,
- [BNXT_ULP_CLASS_HID_4814] = 1142,
- [BNXT_ULP_CLASS_HID_3d94] = 1143,
- [BNXT_ULP_CLASS_HID_34b8] = 1144,
- [BNXT_ULP_CLASS_HID_09a8] = 1145,
- [BNXT_ULP_CLASS_HID_00cc] = 1146,
- [BNXT_ULP_CLASS_HID_23f64] = 1147,
- [BNXT_ULP_CLASS_HID_23688] = 1148,
- [BNXT_ULP_CLASS_HID_20b78] = 1149,
- [BNXT_ULP_CLASS_HID_2029c] = 1150,
- [BNXT_ULP_CLASS_HID_25f68] = 1151,
- [BNXT_ULP_CLASS_HID_2568c] = 1152,
- [BNXT_ULP_CLASS_HID_22b7c] = 1153,
- [BNXT_ULP_CLASS_HID_222a0] = 1154,
- [BNXT_ULP_CLASS_HID_14020] = 1155,
- [BNXT_ULP_CLASS_HID_15b44] = 1156,
- [BNXT_ULP_CLASS_HID_12c34] = 1157,
- [BNXT_ULP_CLASS_HID_12758] = 1158,
- [BNXT_ULP_CLASS_HID_118d8] = 1159,
- [BNXT_ULP_CLASS_HID_113fc] = 1160,
- [BNXT_ULP_CLASS_HID_14c38] = 1161,
- [BNXT_ULP_CLASS_HID_1475c] = 1162,
- [BNXT_ULP_CLASS_HID_31aa8] = 1163,
- [BNXT_ULP_CLASS_HID_315cc] = 1164,
- [BNXT_ULP_CLASS_HID_34e08] = 1165,
- [BNXT_ULP_CLASS_HID_3492c] = 1166,
- [BNXT_ULP_CLASS_HID_33aac] = 1167,
- [BNXT_ULP_CLASS_HID_335d0] = 1168,
- [BNXT_ULP_CLASS_HID_306c0] = 1169,
- [BNXT_ULP_CLASS_HID_301e4] = 1170,
- [BNXT_ULP_CLASS_HID_4d32] = 1171,
- [BNXT_ULP_CLASS_HID_54aa] = 1172,
- [BNXT_ULP_CLASS_HID_0686] = 1173,
- [BNXT_ULP_CLASS_HID_540e] = 1174,
- [BNXT_ULP_CLASS_HID_2e3c] = 1175,
- [BNXT_ULP_CLASS_HID_3a20] = 1176,
- [BNXT_ULP_CLASS_HID_46f0] = 1177,
- [BNXT_ULP_CLASS_HID_52e4] = 1178,
- [BNXT_ULP_CLASS_HID_55e4] = 1179,
- [BNXT_ULP_CLASS_HID_21f8] = 1180,
- [BNXT_ULP_CLASS_HID_75e8] = 1181,
- [BNXT_ULP_CLASS_HID_41fc] = 1182,
- [BNXT_ULP_CLASS_HID_4d12] = 1183,
- [BNXT_ULP_CLASS_HID_548a] = 1184,
- [BNXT_ULP_CLASS_HID_3356] = 1185,
- [BNXT_ULP_CLASS_HID_1ace] = 1186,
- [BNXT_ULP_CLASS_HID_1a9a] = 1187,
- [BNXT_ULP_CLASS_HID_4d46] = 1188,
- [BNXT_ULP_CLASS_HID_2812] = 1189,
- [BNXT_ULP_CLASS_HID_338a] = 1190,
- [BNXT_ULP_CLASS_HID_06e6] = 1191,
- [BNXT_ULP_CLASS_HID_546e] = 1192,
- [BNXT_ULP_CLASS_HID_46ee] = 1193,
- [BNXT_ULP_CLASS_HID_0d22] = 1194,
- [BNXT_ULP_CLASS_HID_26e2] = 1195,
- [BNXT_ULP_CLASS_HID_746a] = 1196,
- [BNXT_ULP_CLASS_HID_1fa6] = 1197,
- [BNXT_ULP_CLASS_HID_2d2e] = 1198,
- [BNXT_ULP_CLASS_HID_4ef2] = 1199,
- [BNXT_ULP_CLASS_HID_576a] = 1200,
- [BNXT_ULP_CLASS_HID_30b6] = 1201,
- [BNXT_ULP_CLASS_HID_192e] = 1202,
- [BNXT_ULP_CLASS_HID_197a] = 1203,
- [BNXT_ULP_CLASS_HID_4ea6] = 1204,
- [BNXT_ULP_CLASS_HID_2bf2] = 1205,
- [BNXT_ULP_CLASS_HID_306a] = 1206,
- [BNXT_ULP_CLASS_HID_06c6] = 1207,
- [BNXT_ULP_CLASS_HID_544e] = 1208,
- [BNXT_ULP_CLASS_HID_46ce] = 1209,
- [BNXT_ULP_CLASS_HID_0d02] = 1210,
- [BNXT_ULP_CLASS_HID_26c2] = 1211,
- [BNXT_ULP_CLASS_HID_744a] = 1212,
- [BNXT_ULP_CLASS_HID_1f86] = 1213,
- [BNXT_ULP_CLASS_HID_2d0e] = 1214,
- [BNXT_ULP_CLASS_HID_2e1c] = 1215,
- [BNXT_ULP_CLASS_HID_3a00] = 1216,
- [BNXT_ULP_CLASS_HID_46d0] = 1217,
- [BNXT_ULP_CLASS_HID_52c4] = 1218,
- [BNXT_ULP_CLASS_HID_4e10] = 1219,
- [BNXT_ULP_CLASS_HID_5a04] = 1220,
- [BNXT_ULP_CLASS_HID_1f98] = 1221,
- [BNXT_ULP_CLASS_HID_72f8] = 1222,
- [BNXT_ULP_CLASS_HID_0a78] = 1223,
- [BNXT_ULP_CLASS_HID_166c] = 1224,
- [BNXT_ULP_CLASS_HID_233c] = 1225,
- [BNXT_ULP_CLASS_HID_0f20] = 1226,
- [BNXT_ULP_CLASS_HID_2a7c] = 1227,
- [BNXT_ULP_CLASS_HID_3660] = 1228,
- [BNXT_ULP_CLASS_HID_4330] = 1229,
- [BNXT_ULP_CLASS_HID_2f24] = 1230,
- [BNXT_ULP_CLASS_HID_5584] = 1231,
- [BNXT_ULP_CLASS_HID_2198] = 1232,
- [BNXT_ULP_CLASS_HID_7588] = 1233,
- [BNXT_ULP_CLASS_HID_419c] = 1234,
- [BNXT_ULP_CLASS_HID_27758] = 1235,
- [BNXT_ULP_CLASS_HID_243ac] = 1236,
- [BNXT_ULP_CLASS_HID_20c10] = 1237,
- [BNXT_ULP_CLASS_HID_21864] = 1238,
- [BNXT_ULP_CLASS_HID_130c8] = 1239,
- [BNXT_ULP_CLASS_HID_11cdc] = 1240,
- [BNXT_ULP_CLASS_HID_150cc] = 1241,
- [BNXT_ULP_CLASS_HID_13d20] = 1242,
- [BNXT_ULP_CLASS_HID_3529c] = 1243,
- [BNXT_ULP_CLASS_HID_33ef0] = 1244,
- [BNXT_ULP_CLASS_HID_372e0] = 1245,
- [BNXT_ULP_CLASS_HID_35ef4] = 1246,
- [BNXT_ULP_CLASS_HID_2dfc] = 1247,
- [BNXT_ULP_CLASS_HID_39e0] = 1248,
- [BNXT_ULP_CLASS_HID_4530] = 1249,
- [BNXT_ULP_CLASS_HID_5124] = 1250,
- [BNXT_ULP_CLASS_HID_4df0] = 1251,
- [BNXT_ULP_CLASS_HID_59e4] = 1252,
- [BNXT_ULP_CLASS_HID_1c78] = 1253,
- [BNXT_ULP_CLASS_HID_7118] = 1254,
- [BNXT_ULP_CLASS_HID_0998] = 1255,
- [BNXT_ULP_CLASS_HID_158c] = 1256,
- [BNXT_ULP_CLASS_HID_20dc] = 1257,
- [BNXT_ULP_CLASS_HID_0cc0] = 1258,
- [BNXT_ULP_CLASS_HID_299c] = 1259,
- [BNXT_ULP_CLASS_HID_3580] = 1260,
- [BNXT_ULP_CLASS_HID_40d0] = 1261,
- [BNXT_ULP_CLASS_HID_2cc4] = 1262,
- [BNXT_ULP_CLASS_HID_55a4] = 1263,
- [BNXT_ULP_CLASS_HID_21b8] = 1264,
- [BNXT_ULP_CLASS_HID_75a8] = 1265,
- [BNXT_ULP_CLASS_HID_41bc] = 1266,
- [BNXT_ULP_CLASS_HID_27778] = 1267,
- [BNXT_ULP_CLASS_HID_2438c] = 1268,
- [BNXT_ULP_CLASS_HID_20c30] = 1269,
- [BNXT_ULP_CLASS_HID_21844] = 1270,
- [BNXT_ULP_CLASS_HID_130e8] = 1271,
- [BNXT_ULP_CLASS_HID_11cfc] = 1272,
- [BNXT_ULP_CLASS_HID_150ec] = 1273,
- [BNXT_ULP_CLASS_HID_13d00] = 1274,
- [BNXT_ULP_CLASS_HID_352bc] = 1275,
- [BNXT_ULP_CLASS_HID_33ed0] = 1276,
- [BNXT_ULP_CLASS_HID_372c0] = 1277,
- [BNXT_ULP_CLASS_HID_35ed4] = 1278,
- [BNXT_ULP_CLASS_HID_3866] = 1279,
- [BNXT_ULP_CLASS_HID_381e] = 1280,
- [BNXT_ULP_CLASS_HID_3860] = 1281,
- [BNXT_ULP_CLASS_HID_0454] = 1282,
- [BNXT_ULP_CLASS_HID_3818] = 1283,
- [BNXT_ULP_CLASS_HID_042c] = 1284,
- [BNXT_ULP_CLASS_HID_3846] = 1285,
- [BNXT_ULP_CLASS_HID_387e] = 1286,
- [BNXT_ULP_CLASS_HID_3ba6] = 1287,
- [BNXT_ULP_CLASS_HID_385e] = 1288,
- [BNXT_ULP_CLASS_HID_3840] = 1289,
- [BNXT_ULP_CLASS_HID_0474] = 1290,
- [BNXT_ULP_CLASS_HID_3878] = 1291,
- [BNXT_ULP_CLASS_HID_044c] = 1292,
- [BNXT_ULP_CLASS_HID_3ba0] = 1293,
- [BNXT_ULP_CLASS_HID_0794] = 1294,
- [BNXT_ULP_CLASS_HID_3858] = 1295,
- [BNXT_ULP_CLASS_HID_046c] = 1296
+ [BNXT_ULP_CLASS_HID_00b8] = 1,
+ [BNXT_ULP_CLASS_HID_0cc2] = 2,
+ [BNXT_ULP_CLASS_HID_10e4] = 3,
+ [BNXT_ULP_CLASS_HID_1d0e] = 4,
+ [BNXT_ULP_CLASS_HID_0286] = 5,
+ [BNXT_ULP_CLASS_HID_0e98] = 6,
+ [BNXT_ULP_CLASS_HID_1666] = 7,
+ [BNXT_ULP_CLASS_HID_02de] = 8,
+ [BNXT_ULP_CLASS_HID_81d25] = 9,
+ [BNXT_ULP_CLASS_HID_809ad] = 10,
+ [BNXT_ULP_CLASS_HID_80ae3] = 11,
+ [BNXT_ULP_CLASS_HID_8170d] = 12,
+ [BNXT_ULP_CLASS_HID_80773] = 13,
+ [BNXT_ULP_CLASS_HID_8139d] = 14,
+ [BNXT_ULP_CLASS_HID_814d3] = 15,
+ [BNXT_ULP_CLASS_HID_8015b] = 16,
+ [BNXT_ULP_CLASS_HID_21977] = 17,
+ [BNXT_ULP_CLASS_HID_205ef] = 18,
+ [BNXT_ULP_CLASS_HID_20735] = 19,
+ [BNXT_ULP_CLASS_HID_2134f] = 20,
+ [BNXT_ULP_CLASS_HID_61beb] = 21,
+ [BNXT_ULP_CLASS_HID_60863] = 22,
+ [BNXT_ULP_CLASS_HID_609a9] = 23,
+ [BNXT_ULP_CLASS_HID_615c3] = 24,
+ [BNXT_ULP_CLASS_HID_00a8] = 25,
+ [BNXT_ULP_CLASS_HID_0cd2] = 26,
+ [BNXT_ULP_CLASS_HID_10f4] = 27,
+ [BNXT_ULP_CLASS_HID_1d1e] = 28,
+ [BNXT_ULP_CLASS_HID_1488] = 29,
+ [BNXT_ULP_CLASS_HID_0110] = 30,
+ [BNXT_ULP_CLASS_HID_0532] = 31,
+ [BNXT_ULP_CLASS_HID_115c] = 32,
+ [BNXT_ULP_CLASS_HID_0ab8] = 33,
+ [BNXT_ULP_CLASS_HID_16a2] = 34,
+ [BNXT_ULP_CLASS_HID_1ac4] = 35,
+ [BNXT_ULP_CLASS_HID_074c] = 36,
+ [BNXT_ULP_CLASS_HID_1e98] = 37,
+ [BNXT_ULP_CLASS_HID_0ae0] = 38,
+ [BNXT_ULP_CLASS_HID_0f02] = 39,
+ [BNXT_ULP_CLASS_HID_1b2c] = 40,
+ [BNXT_ULP_CLASS_HID_0296] = 41,
+ [BNXT_ULP_CLASS_HID_0e88] = 42,
+ [BNXT_ULP_CLASS_HID_1676] = 43,
+ [BNXT_ULP_CLASS_HID_02ce] = 44,
+ [BNXT_ULP_CLASS_HID_8076e] = 45,
+ [BNXT_ULP_CLASS_HID_81380] = 46,
+ [BNXT_ULP_CLASS_HID_81b4e] = 47,
+ [BNXT_ULP_CLASS_HID_807c6] = 48,
+ [BNXT_ULP_CLASS_HID_404ea] = 49,
+ [BNXT_ULP_CLASS_HID_4110c] = 50,
+ [BNXT_ULP_CLASS_HID_418ca] = 51,
+ [BNXT_ULP_CLASS_HID_40542] = 52,
+ [BNXT_ULP_CLASS_HID_c09e2] = 53,
+ [BNXT_ULP_CLASS_HID_c1604] = 54,
+ [BNXT_ULP_CLASS_HID_c1dc2] = 55,
+ [BNXT_ULP_CLASS_HID_c0a5a] = 56,
+ [BNXT_ULP_CLASS_HID_0098] = 57,
+ [BNXT_ULP_CLASS_HID_0ce2] = 58,
+ [BNXT_ULP_CLASS_HID_10c4] = 59,
+ [BNXT_ULP_CLASS_HID_1d2e] = 60,
+ [BNXT_ULP_CLASS_HID_14b8] = 61,
+ [BNXT_ULP_CLASS_HID_0120] = 62,
+ [BNXT_ULP_CLASS_HID_0502] = 63,
+ [BNXT_ULP_CLASS_HID_116c] = 64,
+ [BNXT_ULP_CLASS_HID_0a88] = 65,
+ [BNXT_ULP_CLASS_HID_1692] = 66,
+ [BNXT_ULP_CLASS_HID_1af4] = 67,
+ [BNXT_ULP_CLASS_HID_077c] = 68,
+ [BNXT_ULP_CLASS_HID_1ea8] = 69,
+ [BNXT_ULP_CLASS_HID_0ad0] = 70,
+ [BNXT_ULP_CLASS_HID_0f32] = 71,
+ [BNXT_ULP_CLASS_HID_1b1c] = 72,
+ [BNXT_ULP_CLASS_HID_02a6] = 73,
+ [BNXT_ULP_CLASS_HID_0eb8] = 74,
+ [BNXT_ULP_CLASS_HID_1646] = 75,
+ [BNXT_ULP_CLASS_HID_02fe] = 76,
+ [BNXT_ULP_CLASS_HID_8075e] = 77,
+ [BNXT_ULP_CLASS_HID_813b0] = 78,
+ [BNXT_ULP_CLASS_HID_81b7e] = 79,
+ [BNXT_ULP_CLASS_HID_807f6] = 80,
+ [BNXT_ULP_CLASS_HID_404da] = 81,
+ [BNXT_ULP_CLASS_HID_4113c] = 82,
+ [BNXT_ULP_CLASS_HID_418fa] = 83,
+ [BNXT_ULP_CLASS_HID_40572] = 84,
+ [BNXT_ULP_CLASS_HID_c09d2] = 85,
+ [BNXT_ULP_CLASS_HID_c1634] = 86,
+ [BNXT_ULP_CLASS_HID_c1df2] = 87,
+ [BNXT_ULP_CLASS_HID_c0a6a] = 88,
+ [BNXT_ULP_CLASS_HID_81d35] = 89,
+ [BNXT_ULP_CLASS_HID_809bd] = 90,
+ [BNXT_ULP_CLASS_HID_80af3] = 91,
+ [BNXT_ULP_CLASS_HID_8171d] = 92,
+ [BNXT_ULP_CLASS_HID_80763] = 93,
+ [BNXT_ULP_CLASS_HID_8138d] = 94,
+ [BNXT_ULP_CLASS_HID_814c3] = 95,
+ [BNXT_ULP_CLASS_HID_8014b] = 96,
+ [BNXT_ULP_CLASS_HID_c001f] = 97,
+ [BNXT_ULP_CLASS_HID_c0c39] = 98,
+ [BNXT_ULP_CLASS_HID_c0d7f] = 99,
+ [BNXT_ULP_CLASS_HID_c1999] = 100,
+ [BNXT_ULP_CLASS_HID_c09ef] = 101,
+ [BNXT_ULP_CLASS_HID_c1609] = 102,
+ [BNXT_ULP_CLASS_HID_c174f] = 103,
+ [BNXT_ULP_CLASS_HID_c03d7] = 104,
+ [BNXT_ULP_CLASS_HID_a1e73] = 105,
+ [BNXT_ULP_CLASS_HID_a0afb] = 106,
+ [BNXT_ULP_CLASS_HID_a0c31] = 107,
+ [BNXT_ULP_CLASS_HID_a185b] = 108,
+ [BNXT_ULP_CLASS_HID_a08a1] = 109,
+ [BNXT_ULP_CLASS_HID_a14cb] = 110,
+ [BNXT_ULP_CLASS_HID_a1601] = 111,
+ [BNXT_ULP_CLASS_HID_a0289] = 112,
+ [BNXT_ULP_CLASS_HID_e015d] = 113,
+ [BNXT_ULP_CLASS_HID_e0d47] = 114,
+ [BNXT_ULP_CLASS_HID_e0ebd] = 115,
+ [BNXT_ULP_CLASS_HID_e1aa7] = 116,
+ [BNXT_ULP_CLASS_HID_e0b2d] = 117,
+ [BNXT_ULP_CLASS_HID_e1757] = 118,
+ [BNXT_ULP_CLASS_HID_e188d] = 119,
+ [BNXT_ULP_CLASS_HID_e0515] = 120,
+ [BNXT_ULP_CLASS_HID_21967] = 121,
+ [BNXT_ULP_CLASS_HID_205ff] = 122,
+ [BNXT_ULP_CLASS_HID_20725] = 123,
+ [BNXT_ULP_CLASS_HID_2135f] = 124,
+ [BNXT_ULP_CLASS_HID_61bfb] = 125,
+ [BNXT_ULP_CLASS_HID_60873] = 126,
+ [BNXT_ULP_CLASS_HID_609b9] = 127,
+ [BNXT_ULP_CLASS_HID_615d3] = 128,
+ [BNXT_ULP_CLASS_HID_30a55] = 129,
+ [BNXT_ULP_CLASS_HID_3164f] = 130,
+ [BNXT_ULP_CLASS_HID_317b5] = 131,
+ [BNXT_ULP_CLASS_HID_3040d] = 132,
+ [BNXT_ULP_CLASS_HID_70ca9] = 133,
+ [BNXT_ULP_CLASS_HID_718c3] = 134,
+ [BNXT_ULP_CLASS_HID_71a09] = 135,
+ [BNXT_ULP_CLASS_HID_70681] = 136,
+ [BNXT_ULP_CLASS_HID_2821d] = 137,
+ [BNXT_ULP_CLASS_HID_28e37] = 138,
+ [BNXT_ULP_CLASS_HID_28f7d] = 139,
+ [BNXT_ULP_CLASS_HID_29b97] = 140,
+ [BNXT_ULP_CLASS_HID_68491] = 141,
+ [BNXT_ULP_CLASS_HID_6908b] = 142,
+ [BNXT_ULP_CLASS_HID_691f1] = 143,
+ [BNXT_ULP_CLASS_HID_69deb] = 144,
+ [BNXT_ULP_CLASS_HID_3926d] = 145,
+ [BNXT_ULP_CLASS_HID_39e87] = 146,
+ [BNXT_ULP_CLASS_HID_38023] = 147,
+ [BNXT_ULP_CLASS_HID_38c45] = 148,
+ [BNXT_ULP_CLASS_HID_794e1] = 149,
+ [BNXT_ULP_CLASS_HID_78179] = 150,
+ [BNXT_ULP_CLASS_HID_782a7] = 151,
+ [BNXT_ULP_CLASS_HID_78ed9] = 152,
+ [BNXT_ULP_CLASS_HID_81d05] = 153,
+ [BNXT_ULP_CLASS_HID_8098d] = 154,
+ [BNXT_ULP_CLASS_HID_80ac3] = 155,
+ [BNXT_ULP_CLASS_HID_8172d] = 156,
+ [BNXT_ULP_CLASS_HID_80753] = 157,
+ [BNXT_ULP_CLASS_HID_813bd] = 158,
+ [BNXT_ULP_CLASS_HID_814f3] = 159,
+ [BNXT_ULP_CLASS_HID_8017b] = 160,
+ [BNXT_ULP_CLASS_HID_c002f] = 161,
+ [BNXT_ULP_CLASS_HID_c0c09] = 162,
+ [BNXT_ULP_CLASS_HID_c0d4f] = 163,
+ [BNXT_ULP_CLASS_HID_c19a9] = 164,
+ [BNXT_ULP_CLASS_HID_c09df] = 165,
+ [BNXT_ULP_CLASS_HID_c1639] = 166,
+ [BNXT_ULP_CLASS_HID_c177f] = 167,
+ [BNXT_ULP_CLASS_HID_c03e7] = 168,
+ [BNXT_ULP_CLASS_HID_a1e43] = 169,
+ [BNXT_ULP_CLASS_HID_a0acb] = 170,
+ [BNXT_ULP_CLASS_HID_a0c01] = 171,
+ [BNXT_ULP_CLASS_HID_a186b] = 172,
+ [BNXT_ULP_CLASS_HID_a0891] = 173,
+ [BNXT_ULP_CLASS_HID_a14fb] = 174,
+ [BNXT_ULP_CLASS_HID_a1631] = 175,
+ [BNXT_ULP_CLASS_HID_a02b9] = 176,
+ [BNXT_ULP_CLASS_HID_e016d] = 177,
+ [BNXT_ULP_CLASS_HID_e0d77] = 178,
+ [BNXT_ULP_CLASS_HID_e0e8d] = 179,
+ [BNXT_ULP_CLASS_HID_e1a97] = 180,
+ [BNXT_ULP_CLASS_HID_e0b1d] = 181,
+ [BNXT_ULP_CLASS_HID_e1767] = 182,
+ [BNXT_ULP_CLASS_HID_e18bd] = 183,
+ [BNXT_ULP_CLASS_HID_e0525] = 184,
+ [BNXT_ULP_CLASS_HID_21957] = 185,
+ [BNXT_ULP_CLASS_HID_205cf] = 186,
+ [BNXT_ULP_CLASS_HID_20715] = 187,
+ [BNXT_ULP_CLASS_HID_2136f] = 188,
+ [BNXT_ULP_CLASS_HID_61bcb] = 189,
+ [BNXT_ULP_CLASS_HID_60843] = 190,
+ [BNXT_ULP_CLASS_HID_60989] = 191,
+ [BNXT_ULP_CLASS_HID_615e3] = 192,
+ [BNXT_ULP_CLASS_HID_30a65] = 193,
+ [BNXT_ULP_CLASS_HID_3167f] = 194,
+ [BNXT_ULP_CLASS_HID_31785] = 195,
+ [BNXT_ULP_CLASS_HID_3043d] = 196,
+ [BNXT_ULP_CLASS_HID_70c99] = 197,
+ [BNXT_ULP_CLASS_HID_718f3] = 198,
+ [BNXT_ULP_CLASS_HID_71a39] = 199,
+ [BNXT_ULP_CLASS_HID_706b1] = 200,
+ [BNXT_ULP_CLASS_HID_2822d] = 201,
+ [BNXT_ULP_CLASS_HID_28e07] = 202,
+ [BNXT_ULP_CLASS_HID_28f4d] = 203,
+ [BNXT_ULP_CLASS_HID_29ba7] = 204,
+ [BNXT_ULP_CLASS_HID_684a1] = 205,
+ [BNXT_ULP_CLASS_HID_690bb] = 206,
+ [BNXT_ULP_CLASS_HID_691c1] = 207,
+ [BNXT_ULP_CLASS_HID_69ddb] = 208,
+ [BNXT_ULP_CLASS_HID_3925d] = 209,
+ [BNXT_ULP_CLASS_HID_39eb7] = 210,
+ [BNXT_ULP_CLASS_HID_38013] = 211,
+ [BNXT_ULP_CLASS_HID_38c75] = 212,
+ [BNXT_ULP_CLASS_HID_794d1] = 213,
+ [BNXT_ULP_CLASS_HID_78149] = 214,
+ [BNXT_ULP_CLASS_HID_78297] = 215,
+ [BNXT_ULP_CLASS_HID_78ee9] = 216,
+ [BNXT_ULP_CLASS_HID_0816] = 217,
+ [BNXT_ULP_CLASS_HID_1852] = 218,
+ [BNXT_ULP_CLASS_HID_09f4] = 219,
+ [BNXT_ULP_CLASS_HID_1dd4] = 220,
+ [BNXT_ULP_CLASS_HID_804f1] = 221,
+ [BNXT_ULP_CLASS_HID_81251] = 222,
+ [BNXT_ULP_CLASS_HID_80ee1] = 223,
+ [BNXT_ULP_CLASS_HID_81c41] = 224,
+ [BNXT_ULP_CLASS_HID_2013b] = 225,
+ [BNXT_ULP_CLASS_HID_20e9b] = 226,
+ [BNXT_ULP_CLASS_HID_603bf] = 227,
+ [BNXT_ULP_CLASS_HID_6111f] = 228,
+ [BNXT_ULP_CLASS_HID_0806] = 229,
+ [BNXT_ULP_CLASS_HID_1842] = 230,
+ [BNXT_ULP_CLASS_HID_1be6] = 231,
+ [BNXT_ULP_CLASS_HID_0c80] = 232,
+ [BNXT_ULP_CLASS_HID_1216] = 233,
+ [BNXT_ULP_CLASS_HID_02b0] = 234,
+ [BNXT_ULP_CLASS_HID_0654] = 235,
+ [BNXT_ULP_CLASS_HID_1690] = 236,
+ [BNXT_ULP_CLASS_HID_09e4] = 237,
+ [BNXT_ULP_CLASS_HID_1dc4] = 238,
+ [BNXT_ULP_CLASS_HID_80efc] = 239,
+ [BNXT_ULP_CLASS_HID_80332] = 240,
+ [BNXT_ULP_CLASS_HID_40c78] = 241,
+ [BNXT_ULP_CLASS_HID_400be] = 242,
+ [BNXT_ULP_CLASS_HID_c1170] = 243,
+ [BNXT_ULP_CLASS_HID_c05b6] = 244,
+ [BNXT_ULP_CLASS_HID_0836] = 245,
+ [BNXT_ULP_CLASS_HID_1872] = 246,
+ [BNXT_ULP_CLASS_HID_1bd6] = 247,
+ [BNXT_ULP_CLASS_HID_0cb0] = 248,
+ [BNXT_ULP_CLASS_HID_1226] = 249,
+ [BNXT_ULP_CLASS_HID_0280] = 250,
+ [BNXT_ULP_CLASS_HID_0664] = 251,
+ [BNXT_ULP_CLASS_HID_16a0] = 252,
+ [BNXT_ULP_CLASS_HID_09d4] = 253,
+ [BNXT_ULP_CLASS_HID_1df4] = 254,
+ [BNXT_ULP_CLASS_HID_80ecc] = 255,
+ [BNXT_ULP_CLASS_HID_80302] = 256,
+ [BNXT_ULP_CLASS_HID_40c48] = 257,
+ [BNXT_ULP_CLASS_HID_4008e] = 258,
+ [BNXT_ULP_CLASS_HID_c1140] = 259,
+ [BNXT_ULP_CLASS_HID_c0586] = 260,
+ [BNXT_ULP_CLASS_HID_804e1] = 261,
+ [BNXT_ULP_CLASS_HID_81241] = 262,
+ [BNXT_ULP_CLASS_HID_80ef1] = 263,
+ [BNXT_ULP_CLASS_HID_81c51] = 264,
+ [BNXT_ULP_CLASS_HID_c076d] = 265,
+ [BNXT_ULP_CLASS_HID_c14cd] = 266,
+ [BNXT_ULP_CLASS_HID_c117d] = 267,
+ [BNXT_ULP_CLASS_HID_c1edd] = 268,
+ [BNXT_ULP_CLASS_HID_a062f] = 269,
+ [BNXT_ULP_CLASS_HID_a138f] = 270,
+ [BNXT_ULP_CLASS_HID_a103f] = 271,
+ [BNXT_ULP_CLASS_HID_a1d9f] = 272,
+ [BNXT_ULP_CLASS_HID_e08ab] = 273,
+ [BNXT_ULP_CLASS_HID_e160b] = 274,
+ [BNXT_ULP_CLASS_HID_e12bb] = 275,
+ [BNXT_ULP_CLASS_HID_e0079] = 276,
+ [BNXT_ULP_CLASS_HID_2012b] = 277,
+ [BNXT_ULP_CLASS_HID_20e8b] = 278,
+ [BNXT_ULP_CLASS_HID_603af] = 279,
+ [BNXT_ULP_CLASS_HID_6110f] = 280,
+ [BNXT_ULP_CLASS_HID_311bb] = 281,
+ [BNXT_ULP_CLASS_HID_31f1b] = 282,
+ [BNXT_ULP_CLASS_HID_7143f] = 283,
+ [BNXT_ULP_CLASS_HID_701fd] = 284,
+ [BNXT_ULP_CLASS_HID_28963] = 285,
+ [BNXT_ULP_CLASS_HID_296c3] = 286,
+ [BNXT_ULP_CLASS_HID_68be7] = 287,
+ [BNXT_ULP_CLASS_HID_69947] = 288,
+ [BNXT_ULP_CLASS_HID_399f3] = 289,
+ [BNXT_ULP_CLASS_HID_387b1] = 290,
+ [BNXT_ULP_CLASS_HID_79c77] = 291,
+ [BNXT_ULP_CLASS_HID_78a35] = 292,
+ [BNXT_ULP_CLASS_HID_804d1] = 293,
+ [BNXT_ULP_CLASS_HID_81271] = 294,
+ [BNXT_ULP_CLASS_HID_80ec1] = 295,
+ [BNXT_ULP_CLASS_HID_81c61] = 296,
+ [BNXT_ULP_CLASS_HID_c075d] = 297,
+ [BNXT_ULP_CLASS_HID_c14fd] = 298,
+ [BNXT_ULP_CLASS_HID_c114d] = 299,
+ [BNXT_ULP_CLASS_HID_c1eed] = 300,
+ [BNXT_ULP_CLASS_HID_a061f] = 301,
+ [BNXT_ULP_CLASS_HID_a13bf] = 302,
+ [BNXT_ULP_CLASS_HID_a100f] = 303,
+ [BNXT_ULP_CLASS_HID_a1daf] = 304,
+ [BNXT_ULP_CLASS_HID_e089b] = 305,
+ [BNXT_ULP_CLASS_HID_e163b] = 306,
+ [BNXT_ULP_CLASS_HID_e128b] = 307,
+ [BNXT_ULP_CLASS_HID_e0049] = 308,
+ [BNXT_ULP_CLASS_HID_2011b] = 309,
+ [BNXT_ULP_CLASS_HID_20ebb] = 310,
+ [BNXT_ULP_CLASS_HID_6039f] = 311,
+ [BNXT_ULP_CLASS_HID_6113f] = 312,
+ [BNXT_ULP_CLASS_HID_3118b] = 313,
+ [BNXT_ULP_CLASS_HID_31f2b] = 314,
+ [BNXT_ULP_CLASS_HID_7140f] = 315,
+ [BNXT_ULP_CLASS_HID_701cd] = 316,
+ [BNXT_ULP_CLASS_HID_28953] = 317,
+ [BNXT_ULP_CLASS_HID_296f3] = 318,
+ [BNXT_ULP_CLASS_HID_68bd7] = 319,
+ [BNXT_ULP_CLASS_HID_69977] = 320,
+ [BNXT_ULP_CLASS_HID_399c3] = 321,
+ [BNXT_ULP_CLASS_HID_38781] = 322,
+ [BNXT_ULP_CLASS_HID_79c47] = 323,
+ [BNXT_ULP_CLASS_HID_78a05] = 324,
+ [BNXT_ULP_CLASS_HID_04a4] = 325,
+ [BNXT_ULP_CLASS_HID_04a8] = 326,
+ [BNXT_ULP_CLASS_HID_04a5] = 327,
+ [BNXT_ULP_CLASS_HID_1205] = 328,
+ [BNXT_ULP_CLASS_HID_04a9] = 329,
+ [BNXT_ULP_CLASS_HID_1209] = 330,
+ [BNXT_ULP_CLASS_HID_04b4] = 331,
+ [BNXT_ULP_CLASS_HID_04b8] = 332,
+ [BNXT_ULP_CLASS_HID_0484] = 333,
+ [BNXT_ULP_CLASS_HID_0488] = 334,
+ [BNXT_ULP_CLASS_HID_04b5] = 335,
+ [BNXT_ULP_CLASS_HID_1215] = 336,
+ [BNXT_ULP_CLASS_HID_04b9] = 337,
+ [BNXT_ULP_CLASS_HID_1219] = 338,
+ [BNXT_ULP_CLASS_HID_0485] = 339,
+ [BNXT_ULP_CLASS_HID_1225] = 340,
+ [BNXT_ULP_CLASS_HID_0489] = 341,
+ [BNXT_ULP_CLASS_HID_1229] = 342,
+ [BNXT_ULP_CLASS_HID_0226] = 343,
+ [BNXT_ULP_CLASS_HID_4045a] = 344,
+ [BNXT_ULP_CLASS_HID_0daa] = 345,
+ [BNXT_ULP_CLASS_HID_11b0] = 346,
+ [BNXT_ULP_CLASS_HID_403f8] = 347,
+ [BNXT_ULP_CLASS_HID_4161e] = 348,
+ [BNXT_ULP_CLASS_HID_40439] = 349,
+ [BNXT_ULP_CLASS_HID_41405] = 350,
+ [BNXT_ULP_CLASS_HID_51449] = 351,
+ [BNXT_ULP_CLASS_HID_50b33] = 352,
+ [BNXT_ULP_CLASS_HID_48c01] = 353,
+ [BNXT_ULP_CLASS_HID_483eb] = 354,
+ [BNXT_ULP_CLASS_HID_5833f] = 355,
+ [BNXT_ULP_CLASS_HID_5937b] = 356,
+ [BNXT_ULP_CLASS_HID_41875] = 357,
+ [BNXT_ULP_CLASS_HID_40f5f] = 358,
+ [BNXT_ULP_CLASS_HID_50f23] = 359,
+ [BNXT_ULP_CLASS_HID_51f6f] = 360,
+ [BNXT_ULP_CLASS_HID_4875b] = 361,
+ [BNXT_ULP_CLASS_HID_49727] = 362,
+ [BNXT_ULP_CLASS_HID_5976b] = 363,
+ [BNXT_ULP_CLASS_HID_58655] = 364,
+ [BNXT_ULP_CLASS_HID_4125f] = 365,
+ [BNXT_ULP_CLASS_HID_401f9] = 366,
+ [BNXT_ULP_CLASS_HID_501cd] = 367,
+ [BNXT_ULP_CLASS_HID_51149] = 368,
+ [BNXT_ULP_CLASS_HID_49a67] = 369,
+ [BNXT_ULP_CLASS_HID_489c1] = 370,
+ [BNXT_ULP_CLASS_HID_58955] = 371,
+ [BNXT_ULP_CLASS_HID_59951] = 372,
+ [BNXT_ULP_CLASS_HID_40569] = 373,
+ [BNXT_ULP_CLASS_HID_41575] = 374,
+ [BNXT_ULP_CLASS_HID_51579] = 375,
+ [BNXT_ULP_CLASS_HID_50463] = 376,
+ [BNXT_ULP_CLASS_HID_48d71] = 377,
+ [BNXT_ULP_CLASS_HID_49d7d] = 378,
+ [BNXT_ULP_CLASS_HID_59d41] = 379,
+ [BNXT_ULP_CLASS_HID_58c6b] = 380,
+ [BNXT_ULP_CLASS_HID_10255] = 381,
+ [BNXT_ULP_CLASS_HID_11675] = 382,
+ [BNXT_ULP_CLASS_HID_14649] = 383,
+ [BNXT_ULP_CLASS_HID_15a69] = 384,
+ [BNXT_ULP_CLASS_HID_1205b] = 385,
+ [BNXT_ULP_CLASS_HID_1347b] = 386,
+ [BNXT_ULP_CLASS_HID_16bbf] = 387,
+ [BNXT_ULP_CLASS_HID_1785f] = 388,
+ [BNXT_ULP_CLASS_HID_11551] = 389,
+ [BNXT_ULP_CLASS_HID_10897] = 390,
+ [BNXT_ULP_CLASS_HID_15955] = 391,
+ [BNXT_ULP_CLASS_HID_14c8b] = 392,
+ [BNXT_ULP_CLASS_HID_13b47] = 393,
+ [BNXT_ULP_CLASS_HID_12e85] = 394,
+ [BNXT_ULP_CLASS_HID_17f5b] = 395,
+ [BNXT_ULP_CLASS_HID_17299] = 396,
+ [BNXT_ULP_CLASS_HID_10fe7] = 397,
+ [BNXT_ULP_CLASS_HID_10325] = 398,
+ [BNXT_ULP_CLASS_HID_153cb] = 399,
+ [BNXT_ULP_CLASS_HID_14709] = 400,
+ [BNXT_ULP_CLASS_HID_12dc5] = 401,
+ [BNXT_ULP_CLASS_HID_1212b] = 402,
+ [BNXT_ULP_CLASS_HID_171c9] = 403,
+ [BNXT_ULP_CLASS_HID_1650f] = 404,
+ [BNXT_ULP_CLASS_HID_10201] = 405,
+ [BNXT_ULP_CLASS_HID_116c1] = 406,
+ [BNXT_ULP_CLASS_HID_14605] = 407,
+ [BNXT_ULP_CLASS_HID_15a05] = 408,
+ [BNXT_ULP_CLASS_HID_12007] = 409,
+ [BNXT_ULP_CLASS_HID_13407] = 410,
+ [BNXT_ULP_CLASS_HID_1640b] = 411,
+ [BNXT_ULP_CLASS_HID_1780b] = 412,
+ [BNXT_ULP_CLASS_HID_404b0] = 413,
+ [BNXT_ULP_CLASS_HID_4148c] = 414,
+ [BNXT_ULP_CLASS_HID_514c0] = 415,
+ [BNXT_ULP_CLASS_HID_50bba] = 416,
+ [BNXT_ULP_CLASS_HID_48c88] = 417,
+ [BNXT_ULP_CLASS_HID_48362] = 418,
+ [BNXT_ULP_CLASS_HID_583b6] = 419,
+ [BNXT_ULP_CLASS_HID_593f2] = 420,
+ [BNXT_ULP_CLASS_HID_41f54] = 421,
+ [BNXT_ULP_CLASS_HID_40fce] = 422,
+ [BNXT_ULP_CLASS_HID_50e02] = 423,
+ [BNXT_ULP_CLASS_HID_51e5e] = 424,
+ [BNXT_ULP_CLASS_HID_487ca] = 425,
+ [BNXT_ULP_CLASS_HID_49606] = 426,
+ [BNXT_ULP_CLASS_HID_5965a] = 427,
+ [BNXT_ULP_CLASS_HID_58514] = 428,
+ [BNXT_ULP_CLASS_HID_412c2] = 429,
+ [BNXT_ULP_CLASS_HID_401ac] = 430,
+ [BNXT_ULP_CLASS_HID_501e0] = 431,
+ [BNXT_ULP_CLASS_HID_511cc] = 432,
+ [BNXT_ULP_CLASS_HID_4990a] = 433,
+ [BNXT_ULP_CLASS_HID_489e4] = 434,
+ [BNXT_ULP_CLASS_HID_589c8] = 435,
+ [BNXT_ULP_CLASS_HID_59804] = 436,
+ [BNXT_ULP_CLASS_HID_40404] = 437,
+ [BNXT_ULP_CLASS_HID_41440] = 438,
+ [BNXT_ULP_CLASS_HID_51484] = 439,
+ [BNXT_ULP_CLASS_HID_50b0e] = 440,
+ [BNXT_ULP_CLASS_HID_48c4c] = 441,
+ [BNXT_ULP_CLASS_HID_48306] = 442,
+ [BNXT_ULP_CLASS_HID_5830a] = 443,
+ [BNXT_ULP_CLASS_HID_59346] = 444,
+ [BNXT_ULP_CLASS_HID_102cc] = 445,
+ [BNXT_ULP_CLASS_HID_116ec] = 446,
+ [BNXT_ULP_CLASS_HID_146d0] = 447,
+ [BNXT_ULP_CLASS_HID_15af0] = 448,
+ [BNXT_ULP_CLASS_HID_120c2] = 449,
+ [BNXT_ULP_CLASS_HID_134e2] = 450,
+ [BNXT_ULP_CLASS_HID_16b26] = 451,
+ [BNXT_ULP_CLASS_HID_178c6] = 452,
+ [BNXT_ULP_CLASS_HID_115c6] = 453,
+ [BNXT_ULP_CLASS_HID_10804] = 454,
+ [BNXT_ULP_CLASS_HID_15822] = 455,
+ [BNXT_ULP_CLASS_HID_14c60] = 456,
+ [BNXT_ULP_CLASS_HID_13bd4] = 457,
+ [BNXT_ULP_CLASS_HID_12e12] = 458,
+ [BNXT_ULP_CLASS_HID_17e30] = 459,
+ [BNXT_ULP_CLASS_HID_17276] = 460,
+ [BNXT_ULP_CLASS_HID_11f1a] = 461,
+ [BNXT_ULP_CLASS_HID_11358] = 462,
+ [BNXT_ULP_CLASS_HID_14398] = 463,
+ [BNXT_ULP_CLASS_HID_157b8] = 464,
+ [BNXT_ULP_CLASS_HID_13d68] = 465,
+ [BNXT_ULP_CLASS_HID_131aa] = 466,
+ [BNXT_ULP_CLASS_HID_16192] = 467,
+ [BNXT_ULP_CLASS_HID_175b2] = 468,
+ [BNXT_ULP_CLASS_HID_112b2] = 469,
+ [BNXT_ULP_CLASS_HID_106f0] = 470,
+ [BNXT_ULP_CLASS_HID_15692] = 471,
+ [BNXT_ULP_CLASS_HID_14ad0] = 472,
+ [BNXT_ULP_CLASS_HID_13080] = 473,
+ [BNXT_ULP_CLASS_HID_124c2] = 474,
+ [BNXT_ULP_CLASS_HID_174e0] = 475,
+ [BNXT_ULP_CLASS_HID_16f22] = 476,
+ [BNXT_ULP_CLASS_HID_4025b] = 477,
+ [BNXT_ULP_CLASS_HID_41267] = 478,
+ [BNXT_ULP_CLASS_HID_5122b] = 479,
+ [BNXT_ULP_CLASS_HID_50d51] = 480,
+ [BNXT_ULP_CLASS_HID_48a63] = 481,
+ [BNXT_ULP_CLASS_HID_48589] = 482,
+ [BNXT_ULP_CLASS_HID_5855d] = 483,
+ [BNXT_ULP_CLASS_HID_59519] = 484,
+ [BNXT_ULP_CLASS_HID_41e17] = 485,
+ [BNXT_ULP_CLASS_HID_4093d] = 486,
+ [BNXT_ULP_CLASS_HID_50941] = 487,
+ [BNXT_ULP_CLASS_HID_5190d] = 488,
+ [BNXT_ULP_CLASS_HID_48139] = 489,
+ [BNXT_ULP_CLASS_HID_49145] = 490,
+ [BNXT_ULP_CLASS_HID_59109] = 491,
+ [BNXT_ULP_CLASS_HID_58037] = 492,
+ [BNXT_ULP_CLASS_HID_4143d] = 493,
+ [BNXT_ULP_CLASS_HID_4079b] = 494,
+ [BNXT_ULP_CLASS_HID_507af] = 495,
+ [BNXT_ULP_CLASS_HID_5172b] = 496,
+ [BNXT_ULP_CLASS_HID_49c05] = 497,
+ [BNXT_ULP_CLASS_HID_48fa3] = 498,
+ [BNXT_ULP_CLASS_HID_58f37] = 499,
+ [BNXT_ULP_CLASS_HID_59f33] = 500,
+ [BNXT_ULP_CLASS_HID_4030b] = 501,
+ [BNXT_ULP_CLASS_HID_41317] = 502,
+ [BNXT_ULP_CLASS_HID_5131b] = 503,
+ [BNXT_ULP_CLASS_HID_50201] = 504,
+ [BNXT_ULP_CLASS_HID_48b13] = 505,
+ [BNXT_ULP_CLASS_HID_49b1f] = 506,
+ [BNXT_ULP_CLASS_HID_59b23] = 507,
+ [BNXT_ULP_CLASS_HID_58a09] = 508,
+ [BNXT_ULP_CLASS_HID_419bf] = 509,
+ [BNXT_ULP_CLASS_HID_40925] = 510,
+ [BNXT_ULP_CLASS_HID_508e9] = 511,
+ [BNXT_ULP_CLASS_HID_518b5] = 512,
+ [BNXT_ULP_CLASS_HID_48121] = 513,
+ [BNXT_ULP_CLASS_HID_490ed] = 514,
+ [BNXT_ULP_CLASS_HID_590b1] = 515,
+ [BNXT_ULP_CLASS_HID_583ff] = 516,
+ [BNXT_ULP_CLASS_HID_41475] = 517,
+ [BNXT_ULP_CLASS_HID_40473] = 518,
+ [BNXT_ULP_CLASS_HID_50427] = 519,
+ [BNXT_ULP_CLASS_HID_51763] = 520,
+ [BNXT_ULP_CLASS_HID_49c3d] = 521,
+ [BNXT_ULP_CLASS_HID_48c3b] = 522,
+ [BNXT_ULP_CLASS_HID_58f6f] = 523,
+ [BNXT_ULP_CLASS_HID_59f2b] = 524,
+ [BNXT_ULP_CLASS_HID_40333] = 525,
+ [BNXT_ULP_CLASS_HID_412bf] = 526,
+ [BNXT_ULP_CLASS_HID_512a3] = 527,
+ [BNXT_ULP_CLASS_HID_50229] = 528,
+ [BNXT_ULP_CLASS_HID_48abb] = 529,
+ [BNXT_ULP_CLASS_HID_49aa7] = 530,
+ [BNXT_ULP_CLASS_HID_59a2b] = 531,
+ [BNXT_ULP_CLASS_HID_595b1] = 532,
+ [BNXT_ULP_CLASS_HID_41e2f] = 533,
+ [BNXT_ULP_CLASS_HID_40e35] = 534,
+ [BNXT_ULP_CLASS_HID_50939] = 535,
+ [BNXT_ULP_CLASS_HID_51925] = 536,
+ [BNXT_ULP_CLASS_HID_48631] = 537,
+ [BNXT_ULP_CLASS_HID_4913d] = 538,
+ [BNXT_ULP_CLASS_HID_59121] = 539,
+ [BNXT_ULP_CLASS_HID_5812f] = 540,
+ [BNXT_ULP_CLASS_HID_41429] = 541,
+ [BNXT_ULP_CLASS_HID_40747] = 542,
+ [BNXT_ULP_CLASS_HID_5070b] = 543,
+ [BNXT_ULP_CLASS_HID_51727] = 544,
+ [BNXT_ULP_CLASS_HID_49fe1] = 545,
+ [BNXT_ULP_CLASS_HID_48f0f] = 546,
+ [BNXT_ULP_CLASS_HID_58f23] = 547,
+ [BNXT_ULP_CLASS_HID_59eef] = 548,
+ [BNXT_ULP_CLASS_HID_40347] = 549,
+ [BNXT_ULP_CLASS_HID_41303] = 550,
+ [BNXT_ULP_CLASS_HID_51247] = 551,
+ [BNXT_ULP_CLASS_HID_5026d] = 552,
+ [BNXT_ULP_CLASS_HID_48b0f] = 553,
+ [BNXT_ULP_CLASS_HID_49a4b] = 554,
+ [BNXT_ULP_CLASS_HID_59a0f] = 555,
+ [BNXT_ULP_CLASS_HID_58a05] = 556,
+ [BNXT_ULP_CLASS_HID_41983] = 557,
+ [BNXT_ULP_CLASS_HID_40929] = 558,
+ [BNXT_ULP_CLASS_HID_5092d] = 559,
+ [BNXT_ULP_CLASS_HID_518a9] = 560,
+ [BNXT_ULP_CLASS_HID_48125] = 561,
+ [BNXT_ULP_CLASS_HID_49121] = 562,
+ [BNXT_ULP_CLASS_HID_59085] = 563,
+ [BNXT_ULP_CLASS_HID_58023] = 564,
+ [BNXT_ULP_CLASS_HID_41509] = 565,
+ [BNXT_ULP_CLASS_HID_40407] = 566,
+ [BNXT_ULP_CLASS_HID_5040b] = 567,
+ [BNXT_ULP_CLASS_HID_51407] = 568,
+ [BNXT_ULP_CLASS_HID_49d21] = 569,
+ [BNXT_ULP_CLASS_HID_48c0f] = 570,
+ [BNXT_ULP_CLASS_HID_58c03] = 571,
+ [BNXT_ULP_CLASS_HID_59f0f] = 572,
+ [BNXT_ULP_CLASS_HID_402ef] = 573,
+ [BNXT_ULP_CLASS_HID_412ab] = 574,
+ [BNXT_ULP_CLASS_HID_5126f] = 575,
+ [BNXT_ULP_CLASS_HID_50de5] = 576,
+ [BNXT_ULP_CLASS_HID_48aa7] = 577,
+ [BNXT_ULP_CLASS_HID_485ed] = 578,
+ [BNXT_ULP_CLASS_HID_585e1] = 579,
+ [BNXT_ULP_CLASS_HID_595ad] = 580,
+ [BNXT_ULP_CLASS_HID_41e6b] = 581,
+ [BNXT_ULP_CLASS_HID_40961] = 582,
+ [BNXT_ULP_CLASS_HID_50925] = 583,
+ [BNXT_ULP_CLASS_HID_51961] = 584,
+ [BNXT_ULP_CLASS_HID_4816d] = 585,
+ [BNXT_ULP_CLASS_HID_49129] = 586,
+ [BNXT_ULP_CLASS_HID_5916d] = 587,
+ [BNXT_ULP_CLASS_HID_5806b] = 588,
+ [BNXT_ULP_CLASS_HID_414a1] = 589,
+ [BNXT_ULP_CLASS_HID_4042f] = 590,
+ [BNXT_ULP_CLASS_HID_507a3] = 591,
+ [BNXT_ULP_CLASS_HID_517af] = 592,
+ [BNXT_ULP_CLASS_HID_49c29] = 593,
+ [BNXT_ULP_CLASS_HID_48fa7] = 594,
+ [BNXT_ULP_CLASS_HID_58fab] = 595,
+ [BNXT_ULP_CLASS_HID_59f27] = 596,
+ [BNXT_ULP_CLASS_HID_4032f] = 597,
+ [BNXT_ULP_CLASS_HID_4132b] = 598,
+ [BNXT_ULP_CLASS_HID_5132f] = 599,
+ [BNXT_ULP_CLASS_HID_50225] = 600,
+ [BNXT_ULP_CLASS_HID_48b27] = 601,
+ [BNXT_ULP_CLASS_HID_49b23] = 602,
+ [BNXT_ULP_CLASS_HID_59b27] = 603,
+ [BNXT_ULP_CLASS_HID_58a2d] = 604,
+ [BNXT_ULP_CLASS_HID_10437] = 605,
+ [BNXT_ULP_CLASS_HID_11017] = 606,
+ [BNXT_ULP_CLASS_HID_1402b] = 607,
+ [BNXT_ULP_CLASS_HID_15c0b] = 608,
+ [BNXT_ULP_CLASS_HID_12639] = 609,
+ [BNXT_ULP_CLASS_HID_13219] = 610,
+ [BNXT_ULP_CLASS_HID_16ddd] = 611,
+ [BNXT_ULP_CLASS_HID_17e3d] = 612,
+ [BNXT_ULP_CLASS_HID_11333] = 613,
+ [BNXT_ULP_CLASS_HID_10ef5] = 614,
+ [BNXT_ULP_CLASS_HID_15f37] = 615,
+ [BNXT_ULP_CLASS_HID_14ae9] = 616,
+ [BNXT_ULP_CLASS_HID_13d25] = 617,
+ [BNXT_ULP_CLASS_HID_128e7] = 618,
+ [BNXT_ULP_CLASS_HID_17939] = 619,
+ [BNXT_ULP_CLASS_HID_174fb] = 620,
+ [BNXT_ULP_CLASS_HID_10985] = 621,
+ [BNXT_ULP_CLASS_HID_10547] = 622,
+ [BNXT_ULP_CLASS_HID_155a9] = 623,
+ [BNXT_ULP_CLASS_HID_1416b] = 624,
+ [BNXT_ULP_CLASS_HID_12ba7] = 625,
+ [BNXT_ULP_CLASS_HID_12749] = 626,
+ [BNXT_ULP_CLASS_HID_177ab] = 627,
+ [BNXT_ULP_CLASS_HID_1636d] = 628,
+ [BNXT_ULP_CLASS_HID_10463] = 629,
+ [BNXT_ULP_CLASS_HID_110a3] = 630,
+ [BNXT_ULP_CLASS_HID_14067] = 631,
+ [BNXT_ULP_CLASS_HID_15c67] = 632,
+ [BNXT_ULP_CLASS_HID_12665] = 633,
+ [BNXT_ULP_CLASS_HID_13265] = 634,
+ [BNXT_ULP_CLASS_HID_16269] = 635,
+ [BNXT_ULP_CLASS_HID_17e69] = 636,
+ [BNXT_ULP_CLASS_HID_1133d] = 637,
+ [BNXT_ULP_CLASS_HID_10eff] = 638,
+ [BNXT_ULP_CLASS_HID_15ed9] = 639,
+ [BNXT_ULP_CLASS_HID_14a9b] = 640,
+ [BNXT_ULP_CLASS_HID_13d2f] = 641,
+ [BNXT_ULP_CLASS_HID_128e9] = 642,
+ [BNXT_ULP_CLASS_HID_178cb] = 643,
+ [BNXT_ULP_CLASS_HID_1748d] = 644,
+ [BNXT_ULP_CLASS_HID_109fb] = 645,
+ [BNXT_ULP_CLASS_HID_105bd] = 646,
+ [BNXT_ULP_CLASS_HID_155bf] = 647,
+ [BNXT_ULP_CLASS_HID_14179] = 648,
+ [BNXT_ULP_CLASS_HID_12bed] = 649,
+ [BNXT_ULP_CLASS_HID_127af] = 650,
+ [BNXT_ULP_CLASS_HID_177a9] = 651,
+ [BNXT_ULP_CLASS_HID_1636b] = 652,
+ [BNXT_ULP_CLASS_HID_1046d] = 653,
+ [BNXT_ULP_CLASS_HID_1104d] = 654,
+ [BNXT_ULP_CLASS_HID_14009] = 655,
+ [BNXT_ULP_CLASS_HID_15c69] = 656,
+ [BNXT_ULP_CLASS_HID_1260f] = 657,
+ [BNXT_ULP_CLASS_HID_1326f] = 658,
+ [BNXT_ULP_CLASS_HID_1622b] = 659,
+ [BNXT_ULP_CLASS_HID_17e0b] = 660,
+ [BNXT_ULP_CLASS_HID_11369] = 661,
+ [BNXT_ULP_CLASS_HID_10f2b] = 662,
+ [BNXT_ULP_CLASS_HID_15f6d] = 663,
+ [BNXT_ULP_CLASS_HID_14b2f] = 664,
+ [BNXT_ULP_CLASS_HID_13d6b] = 665,
+ [BNXT_ULP_CLASS_HID_1292d] = 666,
+ [BNXT_ULP_CLASS_HID_1792f] = 667,
+ [BNXT_ULP_CLASS_HID_174e9] = 668,
+ [BNXT_ULP_CLASS_HID_119e1] = 669,
+ [BNXT_ULP_CLASS_HID_115a3] = 670,
+ [BNXT_ULP_CLASS_HID_14563] = 671,
+ [BNXT_ULP_CLASS_HID_15143] = 672,
+ [BNXT_ULP_CLASS_HID_13b93] = 673,
+ [BNXT_ULP_CLASS_HID_13751] = 674,
+ [BNXT_ULP_CLASS_HID_16769] = 675,
+ [BNXT_ULP_CLASS_HID_17349] = 676,
+ [BNXT_ULP_CLASS_HID_114ab] = 677,
+ [BNXT_ULP_CLASS_HID_10061] = 678,
+ [BNXT_ULP_CLASS_HID_15063] = 679,
+ [BNXT_ULP_CLASS_HID_14c21] = 680,
+ [BNXT_ULP_CLASS_HID_13671] = 681,
+ [BNXT_ULP_CLASS_HID_12233] = 682,
+ [BNXT_ULP_CLASS_HID_17271] = 683,
+ [BNXT_ULP_CLASS_HID_16e33] = 684,
+ [BNXT_ULP_CLASS_HID_102c1] = 685,
+ [BNXT_ULP_CLASS_HID_11f21] = 686,
+ [BNXT_ULP_CLASS_HID_14ee1] = 687,
+ [BNXT_ULP_CLASS_HID_15ac1] = 688,
+ [BNXT_ULP_CLASS_HID_12cc3] = 689,
+ [BNXT_ULP_CLASS_HID_13923] = 690,
+ [BNXT_ULP_CLASS_HID_168e3] = 691,
+ [BNXT_ULP_CLASS_HID_164a9] = 692,
+ [BNXT_ULP_CLASS_HID_11e29] = 693,
+ [BNXT_ULP_CLASS_HID_115eb] = 694,
+ [BNXT_ULP_CLASS_HID_145a3] = 695,
+ [BNXT_ULP_CLASS_HID_151a3] = 696,
+ [BNXT_ULP_CLASS_HID_1382b] = 697,
+ [BNXT_ULP_CLASS_HID_137e1] = 698,
+ [BNXT_ULP_CLASS_HID_167a1] = 699,
+ [BNXT_ULP_CLASS_HID_173a1] = 700,
+ [BNXT_ULP_CLASS_HID_11449] = 701,
+ [BNXT_ULP_CLASS_HID_1000b] = 702,
+ [BNXT_ULP_CLASS_HID_15069] = 703,
+ [BNXT_ULP_CLASS_HID_14c2b] = 704,
+ [BNXT_ULP_CLASS_HID_1367b] = 705,
+ [BNXT_ULP_CLASS_HID_12239] = 706,
+ [BNXT_ULP_CLASS_HID_1721b] = 707,
+ [BNXT_ULP_CLASS_HID_169d9] = 708,
+ [BNXT_ULP_CLASS_HID_1033b] = 709,
+ [BNXT_ULP_CLASS_HID_11f3b] = 710,
+ [BNXT_ULP_CLASS_HID_14f2b] = 711,
+ [BNXT_ULP_CLASS_HID_15b2b] = 712,
+ [BNXT_ULP_CLASS_HID_12d39] = 713,
+ [BNXT_ULP_CLASS_HID_13939] = 714,
+ [BNXT_ULP_CLASS_HID_168f9] = 715,
+ [BNXT_ULP_CLASS_HID_164bb] = 716,
+ [BNXT_ULP_CLASS_HID_119cb] = 717,
+ [BNXT_ULP_CLASS_HID_11589] = 718,
+ [BNXT_ULP_CLASS_HID_14549] = 719,
+ [BNXT_ULP_CLASS_HID_151a9] = 720,
+ [BNXT_ULP_CLASS_HID_13bc9] = 721,
+ [BNXT_ULP_CLASS_HID_1378b] = 722,
+ [BNXT_ULP_CLASS_HID_1674b] = 723,
+ [BNXT_ULP_CLASS_HID_173ab] = 724,
+ [BNXT_ULP_CLASS_HID_114a9] = 725,
+ [BNXT_ULP_CLASS_HID_1006b] = 726,
+ [BNXT_ULP_CLASS_HID_150a9] = 727,
+ [BNXT_ULP_CLASS_HID_14c6b] = 728,
+ [BNXT_ULP_CLASS_HID_136ab] = 729,
+ [BNXT_ULP_CLASS_HID_12269] = 730,
+ [BNXT_ULP_CLASS_HID_172ab] = 731,
+ [BNXT_ULP_CLASS_HID_16e69] = 732,
+ [BNXT_ULP_CLASS_HID_402d2] = 733,
+ [BNXT_ULP_CLASS_HID_412ee] = 734,
+ [BNXT_ULP_CLASS_HID_512a2] = 735,
+ [BNXT_ULP_CLASS_HID_50dd8] = 736,
+ [BNXT_ULP_CLASS_HID_48aea] = 737,
+ [BNXT_ULP_CLASS_HID_48500] = 738,
+ [BNXT_ULP_CLASS_HID_585d4] = 739,
+ [BNXT_ULP_CLASS_HID_59590] = 740,
+ [BNXT_ULP_CLASS_HID_41936] = 741,
+ [BNXT_ULP_CLASS_HID_409ac] = 742,
+ [BNXT_ULP_CLASS_HID_50860] = 743,
+ [BNXT_ULP_CLASS_HID_5183c] = 744,
+ [BNXT_ULP_CLASS_HID_481a8] = 745,
+ [BNXT_ULP_CLASS_HID_49064] = 746,
+ [BNXT_ULP_CLASS_HID_59038] = 747,
+ [BNXT_ULP_CLASS_HID_58376] = 748,
+ [BNXT_ULP_CLASS_HID_414a0] = 749,
+ [BNXT_ULP_CLASS_HID_407ce] = 750,
+ [BNXT_ULP_CLASS_HID_50782] = 751,
+ [BNXT_ULP_CLASS_HID_517ae] = 752,
+ [BNXT_ULP_CLASS_HID_49f68] = 753,
+ [BNXT_ULP_CLASS_HID_48f86] = 754,
+ [BNXT_ULP_CLASS_HID_58faa] = 755,
+ [BNXT_ULP_CLASS_HID_59e66] = 756,
+ [BNXT_ULP_CLASS_HID_40266] = 757,
+ [BNXT_ULP_CLASS_HID_41222] = 758,
+ [BNXT_ULP_CLASS_HID_512e6] = 759,
+ [BNXT_ULP_CLASS_HID_50d6c] = 760,
+ [BNXT_ULP_CLASS_HID_48a2e] = 761,
+ [BNXT_ULP_CLASS_HID_48564] = 762,
+ [BNXT_ULP_CLASS_HID_58568] = 763,
+ [BNXT_ULP_CLASS_HID_59524] = 764,
+ [BNXT_ULP_CLASS_HID_419d8] = 765,
+ [BNXT_ULP_CLASS_HID_4087e] = 766,
+ [BNXT_ULP_CLASS_HID_5080a] = 767,
+ [BNXT_ULP_CLASS_HID_518ce] = 768,
+ [BNXT_ULP_CLASS_HID_4807a] = 769,
+ [BNXT_ULP_CLASS_HID_4900e] = 770,
+ [BNXT_ULP_CLASS_HID_590ca] = 771,
+ [BNXT_ULP_CLASS_HID_58378] = 772,
+ [BNXT_ULP_CLASS_HID_414be] = 773,
+ [BNXT_ULP_CLASS_HID_4073c] = 774,
+ [BNXT_ULP_CLASS_HID_507e8] = 775,
+ [BNXT_ULP_CLASS_HID_517ac] = 776,
+ [BNXT_ULP_CLASS_HID_49f7e] = 777,
+ [BNXT_ULP_CLASS_HID_48fec] = 778,
+ [BNXT_ULP_CLASS_HID_58fa8] = 779,
+ [BNXT_ULP_CLASS_HID_59e7c] = 780,
+ [BNXT_ULP_CLASS_HID_40208] = 781,
+ [BNXT_ULP_CLASS_HID_412cc] = 782,
+ [BNXT_ULP_CLASS_HID_51288] = 783,
+ [BNXT_ULP_CLASS_HID_50d2e] = 784,
+ [BNXT_ULP_CLASS_HID_48ac8] = 785,
+ [BNXT_ULP_CLASS_HID_4856e] = 786,
+ [BNXT_ULP_CLASS_HID_5852a] = 787,
+ [BNXT_ULP_CLASS_HID_595ce] = 788,
+ [BNXT_ULP_CLASS_HID_4196c] = 789,
+ [BNXT_ULP_CLASS_HID_409aa] = 790,
+ [BNXT_ULP_CLASS_HID_5086e] = 791,
+ [BNXT_ULP_CLASS_HID_5182a] = 792,
+ [BNXT_ULP_CLASS_HID_481ae] = 793,
+ [BNXT_ULP_CLASS_HID_4906a] = 794,
+ [BNXT_ULP_CLASS_HID_5902e] = 795,
+ [BNXT_ULP_CLASS_HID_580ac] = 796,
+ [BNXT_ULP_CLASS_HID_40766] = 797,
+ [BNXT_ULP_CLASS_HID_41726] = 798,
+ [BNXT_ULP_CLASS_HID_517f6] = 799,
+ [BNXT_ULP_CLASS_HID_5066c] = 800,
+ [BNXT_ULP_CLASS_HID_48f3e] = 801,
+ [BNXT_ULP_CLASS_HID_49ffe] = 802,
+ [BNXT_ULP_CLASS_HID_59f8e] = 803,
+ [BNXT_ULP_CLASS_HID_58e24] = 804,
+ [BNXT_ULP_CLASS_HID_4126e] = 805,
+ [BNXT_ULP_CLASS_HID_402e4] = 806,
+ [BNXT_ULP_CLASS_HID_502b4] = 807,
+ [BNXT_ULP_CLASS_HID_51d74] = 808,
+ [BNXT_ULP_CLASS_HID_49a26] = 809,
+ [BNXT_ULP_CLASS_HID_48abc] = 810,
+ [BNXT_ULP_CLASS_HID_5956c] = 811,
+ [BNXT_ULP_CLASS_HID_585ee] = 812,
+ [BNXT_ULP_CLASS_HID_409e4] = 813,
+ [BNXT_ULP_CLASS_HID_419a4] = 814,
+ [BNXT_ULP_CLASS_HID_51844] = 815,
+ [BNXT_ULP_CLASS_HID_508e6] = 816,
+ [BNXT_ULP_CLASS_HID_4918c] = 817,
+ [BNXT_ULP_CLASS_HID_4802e] = 818,
+ [BNXT_ULP_CLASS_HID_580ee] = 819,
+ [BNXT_ULP_CLASS_HID_590ae] = 820,
+ [BNXT_ULP_CLASS_HID_404ae] = 821,
+ [BNXT_ULP_CLASS_HID_41766] = 822,
+ [BNXT_ULP_CLASS_HID_5172e] = 823,
+ [BNXT_ULP_CLASS_HID_507a4] = 824,
+ [BNXT_ULP_CLASS_HID_48f66] = 825,
+ [BNXT_ULP_CLASS_HID_49f2e] = 826,
+ [BNXT_ULP_CLASS_HID_59fe6] = 827,
+ [BNXT_ULP_CLASS_HID_58e6c] = 828,
+ [BNXT_ULP_CLASS_HID_4126c] = 829,
+ [BNXT_ULP_CLASS_HID_4028e] = 830,
+ [BNXT_ULP_CLASS_HID_50d5e] = 831,
+ [BNXT_ULP_CLASS_HID_51d1e] = 832,
+ [BNXT_ULP_CLASS_HID_49a2c] = 833,
+ [BNXT_ULP_CLASS_HID_4954e] = 834,
+ [BNXT_ULP_CLASS_HID_5951e] = 835,
+ [BNXT_ULP_CLASS_HID_5858c] = 836,
+ [BNXT_ULP_CLASS_HID_409fe] = 837,
+ [BNXT_ULP_CLASS_HID_419ee] = 838,
+ [BNXT_ULP_CLASS_HID_519ae] = 839,
+ [BNXT_ULP_CLASS_HID_508fc] = 840,
+ [BNXT_ULP_CLASS_HID_491ee] = 841,
+ [BNXT_ULP_CLASS_HID_4802c] = 842,
+ [BNXT_ULP_CLASS_HID_580fc] = 843,
+ [BNXT_ULP_CLASS_HID_590bc] = 844,
+ [BNXT_ULP_CLASS_HID_4074c] = 845,
+ [BNXT_ULP_CLASS_HID_4170c] = 846,
+ [BNXT_ULP_CLASS_HID_5172c] = 847,
+ [BNXT_ULP_CLASS_HID_5064e] = 848,
+ [BNXT_ULP_CLASS_HID_48f0c] = 849,
+ [BNXT_ULP_CLASS_HID_49fcc] = 850,
+ [BNXT_ULP_CLASS_HID_59fec] = 851,
+ [BNXT_ULP_CLASS_HID_58e0e] = 852,
+ [BNXT_ULP_CLASS_HID_413ac] = 853,
+ [BNXT_ULP_CLASS_HID_402ee] = 854,
+ [BNXT_ULP_CLASS_HID_502ae] = 855,
+ [BNXT_ULP_CLASS_HID_512ae] = 856,
+ [BNXT_ULP_CLASS_HID_49a6c] = 857,
+ [BNXT_ULP_CLASS_HID_48aae] = 858,
+ [BNXT_ULP_CLASS_HID_58aae] = 859,
+ [BNXT_ULP_CLASS_HID_585ec] = 860,
+ [BNXT_ULP_CLASS_HID_104ae] = 861,
+ [BNXT_ULP_CLASS_HID_1108e] = 862,
+ [BNXT_ULP_CLASS_HID_140b2] = 863,
+ [BNXT_ULP_CLASS_HID_15c92] = 864,
+ [BNXT_ULP_CLASS_HID_126a0] = 865,
+ [BNXT_ULP_CLASS_HID_13280] = 866,
+ [BNXT_ULP_CLASS_HID_16d44] = 867,
+ [BNXT_ULP_CLASS_HID_17ea4] = 868,
+ [BNXT_ULP_CLASS_HID_113a4] = 869,
+ [BNXT_ULP_CLASS_HID_10e66] = 870,
+ [BNXT_ULP_CLASS_HID_15e40] = 871,
+ [BNXT_ULP_CLASS_HID_14a02] = 872,
+ [BNXT_ULP_CLASS_HID_13db6] = 873,
+ [BNXT_ULP_CLASS_HID_12870] = 874,
+ [BNXT_ULP_CLASS_HID_17852] = 875,
+ [BNXT_ULP_CLASS_HID_17414] = 876,
+ [BNXT_ULP_CLASS_HID_11978] = 877,
+ [BNXT_ULP_CLASS_HID_1153a] = 878,
+ [BNXT_ULP_CLASS_HID_145fa] = 879,
+ [BNXT_ULP_CLASS_HID_151da] = 880,
+ [BNXT_ULP_CLASS_HID_13b0a] = 881,
+ [BNXT_ULP_CLASS_HID_137c8] = 882,
+ [BNXT_ULP_CLASS_HID_167f0] = 883,
+ [BNXT_ULP_CLASS_HID_173d0] = 884,
+ [BNXT_ULP_CLASS_HID_114d0] = 885,
+ [BNXT_ULP_CLASS_HID_10092] = 886,
+ [BNXT_ULP_CLASS_HID_150f0] = 887,
+ [BNXT_ULP_CLASS_HID_14cb2] = 888,
+ [BNXT_ULP_CLASS_HID_136e2] = 889,
+ [BNXT_ULP_CLASS_HID_122a0] = 890,
+ [BNXT_ULP_CLASS_HID_17282] = 891,
+ [BNXT_ULP_CLASS_HID_16940] = 892,
+ [BNXT_ULP_CLASS_HID_11b90] = 893,
+ [BNXT_ULP_CLASS_HID_11654] = 894,
+ [BNXT_ULP_CLASS_HID_14618] = 895,
+ [BNXT_ULP_CLASS_HID_15278] = 896,
+ [BNXT_ULP_CLASS_HID_12404] = 897,
+ [BNXT_ULP_CLASS_HID_13064] = 898,
+ [BNXT_ULP_CLASS_HID_16028] = 899,
+ [BNXT_ULP_CLASS_HID_17c08] = 900,
+ [BNXT_ULP_CLASS_HID_11100] = 901,
+ [BNXT_ULP_CLASS_HID_10dc4] = 902,
+ [BNXT_ULP_CLASS_HID_15d24] = 903,
+ [BNXT_ULP_CLASS_HID_149d0] = 904,
+ [BNXT_ULP_CLASS_HID_13314] = 905,
+ [BNXT_ULP_CLASS_HID_12fd4] = 906,
+ [BNXT_ULP_CLASS_HID_17f20] = 907,
+ [BNXT_ULP_CLASS_HID_16be0] = 908,
+ [BNXT_ULP_CLASS_HID_11cd8] = 909,
+ [BNXT_ULP_CLASS_HID_10880] = 910,
+ [BNXT_ULP_CLASS_HID_158e0] = 911,
+ [BNXT_ULP_CLASS_HID_154a0] = 912,
+ [BNXT_ULP_CLASS_HID_13ed0] = 913,
+ [BNXT_ULP_CLASS_HID_12a90] = 914,
+ [BNXT_ULP_CLASS_HID_16550] = 915,
+ [BNXT_ULP_CLASS_HID_176b0] = 916,
+ [BNXT_ULP_CLASS_HID_10bb0] = 917,
+ [BNXT_ULP_CLASS_HID_10670] = 918,
+ [BNXT_ULP_CLASS_HID_15650] = 919,
+ [BNXT_ULP_CLASS_HID_14210] = 920,
+ [BNXT_ULP_CLASS_HID_13440] = 921,
+ [BNXT_ULP_CLASS_HID_12000] = 922,
+ [BNXT_ULP_CLASS_HID_17060] = 923,
+ [BNXT_ULP_CLASS_HID_16c20] = 924,
+ [BNXT_ULP_CLASS_HID_11511] = 925,
+ [BNXT_ULP_CLASS_HID_101d3] = 926,
+ [BNXT_ULP_CLASS_HID_15135] = 927,
+ [BNXT_ULP_CLASS_HID_14df7] = 928,
+ [BNXT_ULP_CLASS_HID_13723] = 929,
+ [BNXT_ULP_CLASS_HID_123e5] = 930,
+ [BNXT_ULP_CLASS_HID_173c7] = 931,
+ [BNXT_ULP_CLASS_HID_16f89] = 932,
+ [BNXT_ULP_CLASS_HID_10081] = 933,
+ [BNXT_ULP_CLASS_HID_11ce1] = 934,
+ [BNXT_ULP_CLASS_HID_14ca5] = 935,
+ [BNXT_ULP_CLASS_HID_15885] = 936,
+ [BNXT_ULP_CLASS_HID_12293] = 937,
+ [BNXT_ULP_CLASS_HID_13ef3] = 938,
+ [BNXT_ULP_CLASS_HID_16eb7] = 939,
+ [BNXT_ULP_CLASS_HID_16561] = 940,
+ [BNXT_ULP_CLASS_HID_10e59] = 941,
+ [BNXT_ULP_CLASS_HID_11bb9] = 942,
+ [BNXT_ULP_CLASS_HID_14a61] = 943,
+ [BNXT_ULP_CLASS_HID_14623] = 944,
+ [BNXT_ULP_CLASS_HID_1286b] = 945,
+ [BNXT_ULP_CLASS_HID_12411] = 946,
+ [BNXT_ULP_CLASS_HID_17473] = 947,
+ [BNXT_ULP_CLASS_HID_16031] = 948,
+ [BNXT_ULP_CLASS_HID_10531] = 949,
+ [BNXT_ULP_CLASS_HID_11111] = 950,
+ [BNXT_ULP_CLASS_HID_141d1] = 951,
+ [BNXT_ULP_CLASS_HID_15d31] = 952,
+ [BNXT_ULP_CLASS_HID_127c3] = 953,
+ [BNXT_ULP_CLASS_HID_13323] = 954,
+ [BNXT_ULP_CLASS_HID_163e3] = 955,
+ [BNXT_ULP_CLASS_HID_17fc3] = 956,
+ [BNXT_ULP_CLASS_HID_108f5] = 957,
+ [BNXT_ULP_CLASS_HID_104b9] = 958,
+ [BNXT_ULP_CLASS_HID_15499] = 959,
+ [BNXT_ULP_CLASS_HID_1435d] = 960,
+ [BNXT_ULP_CLASS_HID_12a89] = 961,
+ [BNXT_ULP_CLASS_HID_12149] = 962,
+ [BNXT_ULP_CLASS_HID_176ad] = 963,
+ [BNXT_ULP_CLASS_HID_16d6d] = 964,
+ [BNXT_ULP_CLASS_HID_10665] = 965,
+ [BNXT_ULP_CLASS_HID_11245] = 966,
+ [BNXT_ULP_CLASS_HID_14271] = 967,
+ [BNXT_ULP_CLASS_HID_15e51] = 968,
+ [BNXT_ULP_CLASS_HID_12061] = 969,
+ [BNXT_ULP_CLASS_HID_13c41] = 970,
+ [BNXT_ULP_CLASS_HID_16c05] = 971,
+ [BNXT_ULP_CLASS_HID_17865] = 972,
+ [BNXT_ULP_CLASS_HID_10d21] = 973,
+ [BNXT_ULP_CLASS_HID_11901] = 974,
+ [BNXT_ULP_CLASS_HID_149c1] = 975,
+ [BNXT_ULP_CLASS_HID_14589] = 976,
+ [BNXT_ULP_CLASS_HID_12f31] = 977,
+ [BNXT_ULP_CLASS_HID_13b11] = 978,
+ [BNXT_ULP_CLASS_HID_16bd9] = 979,
+ [BNXT_ULP_CLASS_HID_16799] = 980,
+ [BNXT_ULP_CLASS_HID_11831] = 981,
+ [BNXT_ULP_CLASS_HID_114f1] = 982,
+ [BNXT_ULP_CLASS_HID_144b1] = 983,
+ [BNXT_ULP_CLASS_HID_15091] = 984,
+ [BNXT_ULP_CLASS_HID_13ac1] = 985,
+ [BNXT_ULP_CLASS_HID_13681] = 986,
+ [BNXT_ULP_CLASS_HID_166b1] = 987,
+ [BNXT_ULP_CLASS_HID_17291] = 988,
+ [BNXT_ULP_CLASS_HID_4007d] = 989,
+ [BNXT_ULP_CLASS_HID_41041] = 990,
+ [BNXT_ULP_CLASS_HID_5100d] = 991,
+ [BNXT_ULP_CLASS_HID_50f77] = 992,
+ [BNXT_ULP_CLASS_HID_48845] = 993,
+ [BNXT_ULP_CLASS_HID_487af] = 994,
+ [BNXT_ULP_CLASS_HID_5877b] = 995,
+ [BNXT_ULP_CLASS_HID_5973f] = 996,
+ [BNXT_ULP_CLASS_HID_41c31] = 997,
+ [BNXT_ULP_CLASS_HID_40b1b] = 998,
+ [BNXT_ULP_CLASS_HID_50b67] = 999,
+ [BNXT_ULP_CLASS_HID_51b2b] = 1000,
+ [BNXT_ULP_CLASS_HID_4831f] = 1001,
+ [BNXT_ULP_CLASS_HID_49363] = 1002,
+ [BNXT_ULP_CLASS_HID_5932f] = 1003,
+ [BNXT_ULP_CLASS_HID_58211] = 1004,
+ [BNXT_ULP_CLASS_HID_4161b] = 1005,
+ [BNXT_ULP_CLASS_HID_405bd] = 1006,
+ [BNXT_ULP_CLASS_HID_50589] = 1007,
+ [BNXT_ULP_CLASS_HID_5150d] = 1008,
+ [BNXT_ULP_CLASS_HID_49e23] = 1009,
+ [BNXT_ULP_CLASS_HID_48d85] = 1010,
+ [BNXT_ULP_CLASS_HID_58d11] = 1011,
+ [BNXT_ULP_CLASS_HID_59d15] = 1012,
+ [BNXT_ULP_CLASS_HID_4012d] = 1013,
+ [BNXT_ULP_CLASS_HID_41131] = 1014,
+ [BNXT_ULP_CLASS_HID_5113d] = 1015,
+ [BNXT_ULP_CLASS_HID_50027] = 1016,
+ [BNXT_ULP_CLASS_HID_48935] = 1017,
+ [BNXT_ULP_CLASS_HID_49939] = 1018,
+ [BNXT_ULP_CLASS_HID_59905] = 1019,
+ [BNXT_ULP_CLASS_HID_5882f] = 1020,
+ [BNXT_ULP_CLASS_HID_41b99] = 1021,
+ [BNXT_ULP_CLASS_HID_40b03] = 1022,
+ [BNXT_ULP_CLASS_HID_50acf] = 1023,
+ [BNXT_ULP_CLASS_HID_51a93] = 1024,
+ [BNXT_ULP_CLASS_HID_48307] = 1025,
+ [BNXT_ULP_CLASS_HID_492cb] = 1026,
+ [BNXT_ULP_CLASS_HID_59297] = 1027,
+ [BNXT_ULP_CLASS_HID_581d9] = 1028,
+ [BNXT_ULP_CLASS_HID_41653] = 1029,
+ [BNXT_ULP_CLASS_HID_40655] = 1030,
+ [BNXT_ULP_CLASS_HID_50601] = 1031,
+ [BNXT_ULP_CLASS_HID_51545] = 1032,
+ [BNXT_ULP_CLASS_HID_49e1b] = 1033,
+ [BNXT_ULP_CLASS_HID_48e1d] = 1034,
+ [BNXT_ULP_CLASS_HID_58d49] = 1035,
+ [BNXT_ULP_CLASS_HID_59d0d] = 1036,
+ [BNXT_ULP_CLASS_HID_40115] = 1037,
+ [BNXT_ULP_CLASS_HID_41099] = 1038,
+ [BNXT_ULP_CLASS_HID_51085] = 1039,
+ [BNXT_ULP_CLASS_HID_5000f] = 1040,
+ [BNXT_ULP_CLASS_HID_4889d] = 1041,
+ [BNXT_ULP_CLASS_HID_49881] = 1042,
+ [BNXT_ULP_CLASS_HID_5980d] = 1043,
+ [BNXT_ULP_CLASS_HID_59797] = 1044,
+ [BNXT_ULP_CLASS_HID_41c09] = 1045,
+ [BNXT_ULP_CLASS_HID_40c13] = 1046,
+ [BNXT_ULP_CLASS_HID_50b1f] = 1047,
+ [BNXT_ULP_CLASS_HID_51b03] = 1048,
+ [BNXT_ULP_CLASS_HID_48417] = 1049,
+ [BNXT_ULP_CLASS_HID_4931b] = 1050,
+ [BNXT_ULP_CLASS_HID_59307] = 1051,
+ [BNXT_ULP_CLASS_HID_58309] = 1052,
+ [BNXT_ULP_CLASS_HID_4160f] = 1053,
+ [BNXT_ULP_CLASS_HID_40561] = 1054,
+ [BNXT_ULP_CLASS_HID_5052d] = 1055,
+ [BNXT_ULP_CLASS_HID_51501] = 1056,
+ [BNXT_ULP_CLASS_HID_49dc7] = 1057,
+ [BNXT_ULP_CLASS_HID_48d29] = 1058,
+ [BNXT_ULP_CLASS_HID_58d05] = 1059,
+ [BNXT_ULP_CLASS_HID_59cc9] = 1060,
+ [BNXT_ULP_CLASS_HID_40161] = 1061,
+ [BNXT_ULP_CLASS_HID_41125] = 1062,
+ [BNXT_ULP_CLASS_HID_51061] = 1063,
+ [BNXT_ULP_CLASS_HID_5004b] = 1064,
+ [BNXT_ULP_CLASS_HID_48929] = 1065,
+ [BNXT_ULP_CLASS_HID_4986d] = 1066,
+ [BNXT_ULP_CLASS_HID_59829] = 1067,
+ [BNXT_ULP_CLASS_HID_58823] = 1068,
+ [BNXT_ULP_CLASS_HID_41ba5] = 1069,
+ [BNXT_ULP_CLASS_HID_40b0f] = 1070,
+ [BNXT_ULP_CLASS_HID_50b0b] = 1071,
+ [BNXT_ULP_CLASS_HID_51a8f] = 1072,
+ [BNXT_ULP_CLASS_HID_48303] = 1073,
+ [BNXT_ULP_CLASS_HID_49307] = 1074,
+ [BNXT_ULP_CLASS_HID_592a3] = 1075,
+ [BNXT_ULP_CLASS_HID_58205] = 1076,
+ [BNXT_ULP_CLASS_HID_4172f] = 1077,
+ [BNXT_ULP_CLASS_HID_40621] = 1078,
+ [BNXT_ULP_CLASS_HID_5062d] = 1079,
+ [BNXT_ULP_CLASS_HID_51621] = 1080,
+ [BNXT_ULP_CLASS_HID_49f07] = 1081,
+ [BNXT_ULP_CLASS_HID_48e29] = 1082,
+ [BNXT_ULP_CLASS_HID_58e25] = 1083,
+ [BNXT_ULP_CLASS_HID_59d29] = 1084,
+ [BNXT_ULP_CLASS_HID_400c9] = 1085,
+ [BNXT_ULP_CLASS_HID_4108d] = 1086,
+ [BNXT_ULP_CLASS_HID_51049] = 1087,
+ [BNXT_ULP_CLASS_HID_50fc3] = 1088,
+ [BNXT_ULP_CLASS_HID_48881] = 1089,
+ [BNXT_ULP_CLASS_HID_487cb] = 1090,
+ [BNXT_ULP_CLASS_HID_587c7] = 1091,
+ [BNXT_ULP_CLASS_HID_5978b] = 1092,
+ [BNXT_ULP_CLASS_HID_41c4d] = 1093,
+ [BNXT_ULP_CLASS_HID_40b47] = 1094,
+ [BNXT_ULP_CLASS_HID_50b03] = 1095,
+ [BNXT_ULP_CLASS_HID_51b47] = 1096,
+ [BNXT_ULP_CLASS_HID_4834b] = 1097,
+ [BNXT_ULP_CLASS_HID_4930f] = 1098,
+ [BNXT_ULP_CLASS_HID_5934b] = 1099,
+ [BNXT_ULP_CLASS_HID_5824d] = 1100,
+ [BNXT_ULP_CLASS_HID_41687] = 1101,
+ [BNXT_ULP_CLASS_HID_40609] = 1102,
+ [BNXT_ULP_CLASS_HID_50585] = 1103,
+ [BNXT_ULP_CLASS_HID_51589] = 1104,
+ [BNXT_ULP_CLASS_HID_49e0f] = 1105,
+ [BNXT_ULP_CLASS_HID_48d81] = 1106,
+ [BNXT_ULP_CLASS_HID_58d8d] = 1107,
+ [BNXT_ULP_CLASS_HID_59d01] = 1108,
+ [BNXT_ULP_CLASS_HID_40109] = 1109,
+ [BNXT_ULP_CLASS_HID_4110d] = 1110,
+ [BNXT_ULP_CLASS_HID_51109] = 1111,
+ [BNXT_ULP_CLASS_HID_50003] = 1112,
+ [BNXT_ULP_CLASS_HID_48901] = 1113,
+ [BNXT_ULP_CLASS_HID_49905] = 1114,
+ [BNXT_ULP_CLASS_HID_59901] = 1115,
+ [BNXT_ULP_CLASS_HID_5880b] = 1116,
+ [BNXT_ULP_CLASS_HID_10619] = 1117,
+ [BNXT_ULP_CLASS_HID_11239] = 1118,
+ [BNXT_ULP_CLASS_HID_14205] = 1119,
+ [BNXT_ULP_CLASS_HID_15e25] = 1120,
+ [BNXT_ULP_CLASS_HID_12417] = 1121,
+ [BNXT_ULP_CLASS_HID_13037] = 1122,
+ [BNXT_ULP_CLASS_HID_16ff3] = 1123,
+ [BNXT_ULP_CLASS_HID_17c13] = 1124,
+ [BNXT_ULP_CLASS_HID_1111d] = 1125,
+ [BNXT_ULP_CLASS_HID_10cdb] = 1126,
+ [BNXT_ULP_CLASS_HID_15d19] = 1127,
+ [BNXT_ULP_CLASS_HID_148c7] = 1128,
+ [BNXT_ULP_CLASS_HID_13f0b] = 1129,
+ [BNXT_ULP_CLASS_HID_12ac9] = 1130,
+ [BNXT_ULP_CLASS_HID_17b17] = 1131,
+ [BNXT_ULP_CLASS_HID_176d5] = 1132,
+ [BNXT_ULP_CLASS_HID_10bab] = 1133,
+ [BNXT_ULP_CLASS_HID_10769] = 1134,
+ [BNXT_ULP_CLASS_HID_15787] = 1135,
+ [BNXT_ULP_CLASS_HID_14345] = 1136,
+ [BNXT_ULP_CLASS_HID_12989] = 1137,
+ [BNXT_ULP_CLASS_HID_12567] = 1138,
+ [BNXT_ULP_CLASS_HID_17585] = 1139,
+ [BNXT_ULP_CLASS_HID_16143] = 1140,
+ [BNXT_ULP_CLASS_HID_1064d] = 1141,
+ [BNXT_ULP_CLASS_HID_1128d] = 1142,
+ [BNXT_ULP_CLASS_HID_14249] = 1143,
+ [BNXT_ULP_CLASS_HID_15e49] = 1144,
+ [BNXT_ULP_CLASS_HID_1244b] = 1145,
+ [BNXT_ULP_CLASS_HID_1304b] = 1146,
+ [BNXT_ULP_CLASS_HID_16047] = 1147,
+ [BNXT_ULP_CLASS_HID_17c47] = 1148,
+ [BNXT_ULP_CLASS_HID_11113] = 1149,
+ [BNXT_ULP_CLASS_HID_10cd1] = 1150,
+ [BNXT_ULP_CLASS_HID_15cf7] = 1151,
+ [BNXT_ULP_CLASS_HID_148b5] = 1152,
+ [BNXT_ULP_CLASS_HID_13f01] = 1153,
+ [BNXT_ULP_CLASS_HID_12ac7] = 1154,
+ [BNXT_ULP_CLASS_HID_17ae5] = 1155,
+ [BNXT_ULP_CLASS_HID_176a3] = 1156,
+ [BNXT_ULP_CLASS_HID_10bd5] = 1157,
+ [BNXT_ULP_CLASS_HID_10793] = 1158,
+ [BNXT_ULP_CLASS_HID_15791] = 1159,
+ [BNXT_ULP_CLASS_HID_14357] = 1160,
+ [BNXT_ULP_CLASS_HID_129c3] = 1161,
+ [BNXT_ULP_CLASS_HID_12581] = 1162,
+ [BNXT_ULP_CLASS_HID_17587] = 1163,
+ [BNXT_ULP_CLASS_HID_16145] = 1164,
+ [BNXT_ULP_CLASS_HID_10643] = 1165,
+ [BNXT_ULP_CLASS_HID_11263] = 1166,
+ [BNXT_ULP_CLASS_HID_14227] = 1167,
+ [BNXT_ULP_CLASS_HID_15e47] = 1168,
+ [BNXT_ULP_CLASS_HID_12421] = 1169,
+ [BNXT_ULP_CLASS_HID_13041] = 1170,
+ [BNXT_ULP_CLASS_HID_16005] = 1171,
+ [BNXT_ULP_CLASS_HID_17c25] = 1172,
+ [BNXT_ULP_CLASS_HID_11147] = 1173,
+ [BNXT_ULP_CLASS_HID_10d05] = 1174,
+ [BNXT_ULP_CLASS_HID_15d43] = 1175,
+ [BNXT_ULP_CLASS_HID_14901] = 1176,
+ [BNXT_ULP_CLASS_HID_13f45] = 1177,
+ [BNXT_ULP_CLASS_HID_12b03] = 1178,
+ [BNXT_ULP_CLASS_HID_17b01] = 1179,
+ [BNXT_ULP_CLASS_HID_176c7] = 1180,
+ [BNXT_ULP_CLASS_HID_11bcf] = 1181,
+ [BNXT_ULP_CLASS_HID_1178d] = 1182,
+ [BNXT_ULP_CLASS_HID_1474d] = 1183,
+ [BNXT_ULP_CLASS_HID_1536d] = 1184,
+ [BNXT_ULP_CLASS_HID_139bd] = 1185,
+ [BNXT_ULP_CLASS_HID_1357f] = 1186,
+ [BNXT_ULP_CLASS_HID_16547] = 1187,
+ [BNXT_ULP_CLASS_HID_17167] = 1188,
+ [BNXT_ULP_CLASS_HID_11685] = 1189,
+ [BNXT_ULP_CLASS_HID_1024f] = 1190,
+ [BNXT_ULP_CLASS_HID_1524d] = 1191,
+ [BNXT_ULP_CLASS_HID_14e0f] = 1192,
+ [BNXT_ULP_CLASS_HID_1345f] = 1193,
+ [BNXT_ULP_CLASS_HID_1201d] = 1194,
+ [BNXT_ULP_CLASS_HID_1705f] = 1195,
+ [BNXT_ULP_CLASS_HID_16c1d] = 1196,
+ [BNXT_ULP_CLASS_HID_100ef] = 1197,
+ [BNXT_ULP_CLASS_HID_11d0f] = 1198,
+ [BNXT_ULP_CLASS_HID_14ccf] = 1199,
+ [BNXT_ULP_CLASS_HID_158ef] = 1200,
+ [BNXT_ULP_CLASS_HID_12eed] = 1201,
+ [BNXT_ULP_CLASS_HID_13b0d] = 1202,
+ [BNXT_ULP_CLASS_HID_16acd] = 1203,
+ [BNXT_ULP_CLASS_HID_16687] = 1204,
+ [BNXT_ULP_CLASS_HID_11c07] = 1205,
+ [BNXT_ULP_CLASS_HID_117c5] = 1206,
+ [BNXT_ULP_CLASS_HID_1478d] = 1207,
+ [BNXT_ULP_CLASS_HID_1538d] = 1208,
+ [BNXT_ULP_CLASS_HID_13a05] = 1209,
+ [BNXT_ULP_CLASS_HID_135cf] = 1210,
+ [BNXT_ULP_CLASS_HID_1658f] = 1211,
+ [BNXT_ULP_CLASS_HID_1718f] = 1212,
+ [BNXT_ULP_CLASS_HID_11667] = 1213,
+ [BNXT_ULP_CLASS_HID_10225] = 1214,
+ [BNXT_ULP_CLASS_HID_15247] = 1215,
+ [BNXT_ULP_CLASS_HID_14e05] = 1216,
+ [BNXT_ULP_CLASS_HID_13455] = 1217,
+ [BNXT_ULP_CLASS_HID_12017] = 1218,
+ [BNXT_ULP_CLASS_HID_17035] = 1219,
+ [BNXT_ULP_CLASS_HID_16bf7] = 1220,
+ [BNXT_ULP_CLASS_HID_10115] = 1221,
+ [BNXT_ULP_CLASS_HID_11d15] = 1222,
+ [BNXT_ULP_CLASS_HID_14d05] = 1223,
+ [BNXT_ULP_CLASS_HID_15905] = 1224,
+ [BNXT_ULP_CLASS_HID_12f17] = 1225,
+ [BNXT_ULP_CLASS_HID_13b17] = 1226,
+ [BNXT_ULP_CLASS_HID_16ad7] = 1227,
+ [BNXT_ULP_CLASS_HID_16695] = 1228,
+ [BNXT_ULP_CLASS_HID_11be5] = 1229,
+ [BNXT_ULP_CLASS_HID_117a7] = 1230,
+ [BNXT_ULP_CLASS_HID_14767] = 1231,
+ [BNXT_ULP_CLASS_HID_15387] = 1232,
+ [BNXT_ULP_CLASS_HID_139e7] = 1233,
+ [BNXT_ULP_CLASS_HID_135a5] = 1234,
+ [BNXT_ULP_CLASS_HID_16565] = 1235,
+ [BNXT_ULP_CLASS_HID_17185] = 1236,
+ [BNXT_ULP_CLASS_HID_11687] = 1237,
+ [BNXT_ULP_CLASS_HID_10245] = 1238,
+ [BNXT_ULP_CLASS_HID_15287] = 1239,
+ [BNXT_ULP_CLASS_HID_14e45] = 1240,
+ [BNXT_ULP_CLASS_HID_13485] = 1241,
+ [BNXT_ULP_CLASS_HID_12047] = 1242,
+ [BNXT_ULP_CLASS_HID_17085] = 1243,
+ [BNXT_ULP_CLASS_HID_16c47] = 1244,
+ [BNXT_ULP_CLASS_HID_400f4] = 1245,
+ [BNXT_ULP_CLASS_HID_410c8] = 1246,
+ [BNXT_ULP_CLASS_HID_51084] = 1247,
+ [BNXT_ULP_CLASS_HID_50ffe] = 1248,
+ [BNXT_ULP_CLASS_HID_488cc] = 1249,
+ [BNXT_ULP_CLASS_HID_48726] = 1250,
+ [BNXT_ULP_CLASS_HID_587f2] = 1251,
+ [BNXT_ULP_CLASS_HID_597b6] = 1252,
+ [BNXT_ULP_CLASS_HID_41b10] = 1253,
+ [BNXT_ULP_CLASS_HID_40b8a] = 1254,
+ [BNXT_ULP_CLASS_HID_50a46] = 1255,
+ [BNXT_ULP_CLASS_HID_51a1a] = 1256,
+ [BNXT_ULP_CLASS_HID_4838e] = 1257,
+ [BNXT_ULP_CLASS_HID_49242] = 1258,
+ [BNXT_ULP_CLASS_HID_5921e] = 1259,
+ [BNXT_ULP_CLASS_HID_58150] = 1260,
+ [BNXT_ULP_CLASS_HID_41686] = 1261,
+ [BNXT_ULP_CLASS_HID_405e8] = 1262,
+ [BNXT_ULP_CLASS_HID_505a4] = 1263,
+ [BNXT_ULP_CLASS_HID_51588] = 1264,
+ [BNXT_ULP_CLASS_HID_49d4e] = 1265,
+ [BNXT_ULP_CLASS_HID_48da0] = 1266,
+ [BNXT_ULP_CLASS_HID_58d8c] = 1267,
+ [BNXT_ULP_CLASS_HID_59c40] = 1268,
+ [BNXT_ULP_CLASS_HID_40040] = 1269,
+ [BNXT_ULP_CLASS_HID_41004] = 1270,
+ [BNXT_ULP_CLASS_HID_510c0] = 1271,
+ [BNXT_ULP_CLASS_HID_50f4a] = 1272,
+ [BNXT_ULP_CLASS_HID_48808] = 1273,
+ [BNXT_ULP_CLASS_HID_48742] = 1274,
+ [BNXT_ULP_CLASS_HID_5874e] = 1275,
+ [BNXT_ULP_CLASS_HID_59702] = 1276,
+ [BNXT_ULP_CLASS_HID_41bfe] = 1277,
+ [BNXT_ULP_CLASS_HID_40a58] = 1278,
+ [BNXT_ULP_CLASS_HID_50a2c] = 1279,
+ [BNXT_ULP_CLASS_HID_51ae8] = 1280,
+ [BNXT_ULP_CLASS_HID_4825c] = 1281,
+ [BNXT_ULP_CLASS_HID_49228] = 1282,
+ [BNXT_ULP_CLASS_HID_592ec] = 1283,
+ [BNXT_ULP_CLASS_HID_5815e] = 1284,
+ [BNXT_ULP_CLASS_HID_41698] = 1285,
+ [BNXT_ULP_CLASS_HID_4051a] = 1286,
+ [BNXT_ULP_CLASS_HID_505ce] = 1287,
+ [BNXT_ULP_CLASS_HID_5158a] = 1288,
+ [BNXT_ULP_CLASS_HID_49d58] = 1289,
+ [BNXT_ULP_CLASS_HID_48dca] = 1290,
+ [BNXT_ULP_CLASS_HID_58d8e] = 1291,
+ [BNXT_ULP_CLASS_HID_59c5a] = 1292,
+ [BNXT_ULP_CLASS_HID_4002e] = 1293,
+ [BNXT_ULP_CLASS_HID_410ea] = 1294,
+ [BNXT_ULP_CLASS_HID_510ae] = 1295,
+ [BNXT_ULP_CLASS_HID_50f08] = 1296,
+ [BNXT_ULP_CLASS_HID_488ee] = 1297,
+ [BNXT_ULP_CLASS_HID_48748] = 1298,
+ [BNXT_ULP_CLASS_HID_5870c] = 1299,
+ [BNXT_ULP_CLASS_HID_597e8] = 1300,
+ [BNXT_ULP_CLASS_HID_41b4a] = 1301,
+ [BNXT_ULP_CLASS_HID_40b8c] = 1302,
+ [BNXT_ULP_CLASS_HID_50a48] = 1303,
+ [BNXT_ULP_CLASS_HID_51a0c] = 1304,
+ [BNXT_ULP_CLASS_HID_48388] = 1305,
+ [BNXT_ULP_CLASS_HID_4924c] = 1306,
+ [BNXT_ULP_CLASS_HID_59208] = 1307,
+ [BNXT_ULP_CLASS_HID_5828a] = 1308,
+ [BNXT_ULP_CLASS_HID_40540] = 1309,
+ [BNXT_ULP_CLASS_HID_41500] = 1310,
+ [BNXT_ULP_CLASS_HID_515d0] = 1311,
+ [BNXT_ULP_CLASS_HID_5044a] = 1312,
+ [BNXT_ULP_CLASS_HID_48d18] = 1313,
+ [BNXT_ULP_CLASS_HID_49dd8] = 1314,
+ [BNXT_ULP_CLASS_HID_59da8] = 1315,
+ [BNXT_ULP_CLASS_HID_58c02] = 1316,
+ [BNXT_ULP_CLASS_HID_41048] = 1317,
+ [BNXT_ULP_CLASS_HID_400c2] = 1318,
+ [BNXT_ULP_CLASS_HID_50092] = 1319,
+ [BNXT_ULP_CLASS_HID_51f52] = 1320,
+ [BNXT_ULP_CLASS_HID_49800] = 1321,
+ [BNXT_ULP_CLASS_HID_4889a] = 1322,
+ [BNXT_ULP_CLASS_HID_5974a] = 1323,
+ [BNXT_ULP_CLASS_HID_587c8] = 1324,
+ [BNXT_ULP_CLASS_HID_40bc2] = 1325,
+ [BNXT_ULP_CLASS_HID_41b82] = 1326,
+ [BNXT_ULP_CLASS_HID_51a62] = 1327,
+ [BNXT_ULP_CLASS_HID_50ac0] = 1328,
+ [BNXT_ULP_CLASS_HID_493aa] = 1329,
+ [BNXT_ULP_CLASS_HID_48208] = 1330,
+ [BNXT_ULP_CLASS_HID_582c8] = 1331,
+ [BNXT_ULP_CLASS_HID_59288] = 1332,
+ [BNXT_ULP_CLASS_HID_40688] = 1333,
+ [BNXT_ULP_CLASS_HID_41540] = 1334,
+ [BNXT_ULP_CLASS_HID_51508] = 1335,
+ [BNXT_ULP_CLASS_HID_50582] = 1336,
+ [BNXT_ULP_CLASS_HID_48d40] = 1337,
+ [BNXT_ULP_CLASS_HID_49d08] = 1338,
+ [BNXT_ULP_CLASS_HID_59dc0] = 1339,
+ [BNXT_ULP_CLASS_HID_58c4a] = 1340,
+ [BNXT_ULP_CLASS_HID_4104a] = 1341,
+ [BNXT_ULP_CLASS_HID_400a8] = 1342,
+ [BNXT_ULP_CLASS_HID_50f78] = 1343,
+ [BNXT_ULP_CLASS_HID_51f38] = 1344,
+ [BNXT_ULP_CLASS_HID_4980a] = 1345,
+ [BNXT_ULP_CLASS_HID_49768] = 1346,
+ [BNXT_ULP_CLASS_HID_59738] = 1347,
+ [BNXT_ULP_CLASS_HID_587aa] = 1348,
+ [BNXT_ULP_CLASS_HID_40bd8] = 1349,
+ [BNXT_ULP_CLASS_HID_41bc8] = 1350,
+ [BNXT_ULP_CLASS_HID_51b88] = 1351,
+ [BNXT_ULP_CLASS_HID_50ada] = 1352,
+ [BNXT_ULP_CLASS_HID_493c8] = 1353,
+ [BNXT_ULP_CLASS_HID_4820a] = 1354,
+ [BNXT_ULP_CLASS_HID_582da] = 1355,
+ [BNXT_ULP_CLASS_HID_5929a] = 1356,
+ [BNXT_ULP_CLASS_HID_4056a] = 1357,
+ [BNXT_ULP_CLASS_HID_4152a] = 1358,
+ [BNXT_ULP_CLASS_HID_5150a] = 1359,
+ [BNXT_ULP_CLASS_HID_50468] = 1360,
+ [BNXT_ULP_CLASS_HID_48d2a] = 1361,
+ [BNXT_ULP_CLASS_HID_49dea] = 1362,
+ [BNXT_ULP_CLASS_HID_59dca] = 1363,
+ [BNXT_ULP_CLASS_HID_58c28] = 1364,
+ [BNXT_ULP_CLASS_HID_4118a] = 1365,
+ [BNXT_ULP_CLASS_HID_400c8] = 1366,
+ [BNXT_ULP_CLASS_HID_50088] = 1367,
+ [BNXT_ULP_CLASS_HID_51088] = 1368,
+ [BNXT_ULP_CLASS_HID_4984a] = 1369,
+ [BNXT_ULP_CLASS_HID_48888] = 1370,
+ [BNXT_ULP_CLASS_HID_58888] = 1371,
+ [BNXT_ULP_CLASS_HID_587ca] = 1372,
+ [BNXT_ULP_CLASS_HID_10690] = 1373,
+ [BNXT_ULP_CLASS_HID_112b0] = 1374,
+ [BNXT_ULP_CLASS_HID_1428c] = 1375,
+ [BNXT_ULP_CLASS_HID_15eac] = 1376,
+ [BNXT_ULP_CLASS_HID_1249e] = 1377,
+ [BNXT_ULP_CLASS_HID_130be] = 1378,
+ [BNXT_ULP_CLASS_HID_16f7a] = 1379,
+ [BNXT_ULP_CLASS_HID_17c9a] = 1380,
+ [BNXT_ULP_CLASS_HID_1119a] = 1381,
+ [BNXT_ULP_CLASS_HID_10c58] = 1382,
+ [BNXT_ULP_CLASS_HID_15c7e] = 1383,
+ [BNXT_ULP_CLASS_HID_1483c] = 1384,
+ [BNXT_ULP_CLASS_HID_13f88] = 1385,
+ [BNXT_ULP_CLASS_HID_12a4e] = 1386,
+ [BNXT_ULP_CLASS_HID_17a6c] = 1387,
+ [BNXT_ULP_CLASS_HID_1762a] = 1388,
+ [BNXT_ULP_CLASS_HID_11b46] = 1389,
+ [BNXT_ULP_CLASS_HID_11704] = 1390,
+ [BNXT_ULP_CLASS_HID_147c4] = 1391,
+ [BNXT_ULP_CLASS_HID_153e4] = 1392,
+ [BNXT_ULP_CLASS_HID_13934] = 1393,
+ [BNXT_ULP_CLASS_HID_135f6] = 1394,
+ [BNXT_ULP_CLASS_HID_165ce] = 1395,
+ [BNXT_ULP_CLASS_HID_171ee] = 1396,
+ [BNXT_ULP_CLASS_HID_116ee] = 1397,
+ [BNXT_ULP_CLASS_HID_102ac] = 1398,
+ [BNXT_ULP_CLASS_HID_152ce] = 1399,
+ [BNXT_ULP_CLASS_HID_14e8c] = 1400,
+ [BNXT_ULP_CLASS_HID_134dc] = 1401,
+ [BNXT_ULP_CLASS_HID_1209e] = 1402,
+ [BNXT_ULP_CLASS_HID_170bc] = 1403,
+ [BNXT_ULP_CLASS_HID_16b7e] = 1404,
+ [BNXT_ULP_CLASS_HID_119ae] = 1405,
+ [BNXT_ULP_CLASS_HID_1146a] = 1406,
+ [BNXT_ULP_CLASS_HID_14426] = 1407,
+ [BNXT_ULP_CLASS_HID_15046] = 1408,
+ [BNXT_ULP_CLASS_HID_1263a] = 1409,
+ [BNXT_ULP_CLASS_HID_1325a] = 1410,
+ [BNXT_ULP_CLASS_HID_16216] = 1411,
+ [BNXT_ULP_CLASS_HID_17e36] = 1412,
+ [BNXT_ULP_CLASS_HID_1133e] = 1413,
+ [BNXT_ULP_CLASS_HID_10ffa] = 1414,
+ [BNXT_ULP_CLASS_HID_15f1a] = 1415,
+ [BNXT_ULP_CLASS_HID_14bee] = 1416,
+ [BNXT_ULP_CLASS_HID_1312a] = 1417,
+ [BNXT_ULP_CLASS_HID_12dea] = 1418,
+ [BNXT_ULP_CLASS_HID_17d1e] = 1419,
+ [BNXT_ULP_CLASS_HID_169de] = 1420,
+ [BNXT_ULP_CLASS_HID_11ee6] = 1421,
+ [BNXT_ULP_CLASS_HID_10abe] = 1422,
+ [BNXT_ULP_CLASS_HID_15ade] = 1423,
+ [BNXT_ULP_CLASS_HID_1569e] = 1424,
+ [BNXT_ULP_CLASS_HID_13cee] = 1425,
+ [BNXT_ULP_CLASS_HID_128ae] = 1426,
+ [BNXT_ULP_CLASS_HID_1676e] = 1427,
+ [BNXT_ULP_CLASS_HID_1748e] = 1428,
+ [BNXT_ULP_CLASS_HID_1098e] = 1429,
+ [BNXT_ULP_CLASS_HID_1044e] = 1430,
+ [BNXT_ULP_CLASS_HID_1546e] = 1431,
+ [BNXT_ULP_CLASS_HID_1402e] = 1432,
+ [BNXT_ULP_CLASS_HID_1367e] = 1433,
+ [BNXT_ULP_CLASS_HID_1223e] = 1434,
+ [BNXT_ULP_CLASS_HID_1725e] = 1435,
+ [BNXT_ULP_CLASS_HID_16e1e] = 1436,
+ [BNXT_ULP_CLASS_HID_1172f] = 1437,
+ [BNXT_ULP_CLASS_HID_103ed] = 1438,
+ [BNXT_ULP_CLASS_HID_1530b] = 1439,
+ [BNXT_ULP_CLASS_HID_14fc9] = 1440,
+ [BNXT_ULP_CLASS_HID_1351d] = 1441,
+ [BNXT_ULP_CLASS_HID_121db] = 1442,
+ [BNXT_ULP_CLASS_HID_171f9] = 1443,
+ [BNXT_ULP_CLASS_HID_16db7] = 1444,
+ [BNXT_ULP_CLASS_HID_102bf] = 1445,
+ [BNXT_ULP_CLASS_HID_11edf] = 1446,
+ [BNXT_ULP_CLASS_HID_14e9b] = 1447,
+ [BNXT_ULP_CLASS_HID_15abb] = 1448,
+ [BNXT_ULP_CLASS_HID_120ad] = 1449,
+ [BNXT_ULP_CLASS_HID_13ccd] = 1450,
+ [BNXT_ULP_CLASS_HID_16c89] = 1451,
+ [BNXT_ULP_CLASS_HID_1675f] = 1452,
+ [BNXT_ULP_CLASS_HID_10c67] = 1453,
+ [BNXT_ULP_CLASS_HID_11987] = 1454,
+ [BNXT_ULP_CLASS_HID_1485f] = 1455,
+ [BNXT_ULP_CLASS_HID_1441d] = 1456,
+ [BNXT_ULP_CLASS_HID_12a55] = 1457,
+ [BNXT_ULP_CLASS_HID_1262f] = 1458,
+ [BNXT_ULP_CLASS_HID_1764d] = 1459,
+ [BNXT_ULP_CLASS_HID_1620f] = 1460,
+ [BNXT_ULP_CLASS_HID_1070f] = 1461,
+ [BNXT_ULP_CLASS_HID_1132f] = 1462,
+ [BNXT_ULP_CLASS_HID_143ef] = 1463,
+ [BNXT_ULP_CLASS_HID_15f0f] = 1464,
+ [BNXT_ULP_CLASS_HID_125fd] = 1465,
+ [BNXT_ULP_CLASS_HID_1311d] = 1466,
+ [BNXT_ULP_CLASS_HID_161dd] = 1467,
+ [BNXT_ULP_CLASS_HID_17dfd] = 1468,
+ [BNXT_ULP_CLASS_HID_10acb] = 1469,
+ [BNXT_ULP_CLASS_HID_10687] = 1470,
+ [BNXT_ULP_CLASS_HID_156a7] = 1471,
+ [BNXT_ULP_CLASS_HID_14163] = 1472,
+ [BNXT_ULP_CLASS_HID_128b7] = 1473,
+ [BNXT_ULP_CLASS_HID_12377] = 1474,
+ [BNXT_ULP_CLASS_HID_17493] = 1475,
+ [BNXT_ULP_CLASS_HID_16f53] = 1476,
+ [BNXT_ULP_CLASS_HID_1045b] = 1477,
+ [BNXT_ULP_CLASS_HID_1107b] = 1478,
+ [BNXT_ULP_CLASS_HID_1404f] = 1479,
+ [BNXT_ULP_CLASS_HID_15c6f] = 1480,
+ [BNXT_ULP_CLASS_HID_1225f] = 1481,
+ [BNXT_ULP_CLASS_HID_13e7f] = 1482,
+ [BNXT_ULP_CLASS_HID_16e3b] = 1483,
+ [BNXT_ULP_CLASS_HID_17a5b] = 1484,
+ [BNXT_ULP_CLASS_HID_10f1f] = 1485,
+ [BNXT_ULP_CLASS_HID_11b3f] = 1486,
+ [BNXT_ULP_CLASS_HID_14bff] = 1487,
+ [BNXT_ULP_CLASS_HID_147b7] = 1488,
+ [BNXT_ULP_CLASS_HID_12d0f] = 1489,
+ [BNXT_ULP_CLASS_HID_1392f] = 1490,
+ [BNXT_ULP_CLASS_HID_169e7] = 1491,
+ [BNXT_ULP_CLASS_HID_165a7] = 1492,
+ [BNXT_ULP_CLASS_HID_11a0f] = 1493,
+ [BNXT_ULP_CLASS_HID_116cf] = 1494,
+ [BNXT_ULP_CLASS_HID_1468f] = 1495,
+ [BNXT_ULP_CLASS_HID_152af] = 1496,
+ [BNXT_ULP_CLASS_HID_138ff] = 1497,
+ [BNXT_ULP_CLASS_HID_134bf] = 1498,
+ [BNXT_ULP_CLASS_HID_1648f] = 1499,
+ [BNXT_ULP_CLASS_HID_170af] = 1500,
+ [BNXT_ULP_CLASS_HID_40c38] = 1501,
+ [BNXT_ULP_CLASS_HID_41c04] = 1502,
+ [BNXT_ULP_CLASS_HID_51c48] = 1503,
+ [BNXT_ULP_CLASS_HID_50332] = 1504,
+ [BNXT_ULP_CLASS_HID_48400] = 1505,
+ [BNXT_ULP_CLASS_HID_48bea] = 1506,
+ [BNXT_ULP_CLASS_HID_58b3e] = 1507,
+ [BNXT_ULP_CLASS_HID_59b7a] = 1508,
+ [BNXT_ULP_CLASS_HID_417dc] = 1509,
+ [BNXT_ULP_CLASS_HID_40746] = 1510,
+ [BNXT_ULP_CLASS_HID_5068a] = 1511,
+ [BNXT_ULP_CLASS_HID_516d6] = 1512,
+ [BNXT_ULP_CLASS_HID_48f42] = 1513,
+ [BNXT_ULP_CLASS_HID_49e8e] = 1514,
+ [BNXT_ULP_CLASS_HID_59ed2] = 1515,
+ [BNXT_ULP_CLASS_HID_58d9c] = 1516,
+ [BNXT_ULP_CLASS_HID_41a4a] = 1517,
+ [BNXT_ULP_CLASS_HID_40924] = 1518,
+ [BNXT_ULP_CLASS_HID_50968] = 1519,
+ [BNXT_ULP_CLASS_HID_51944] = 1520,
+ [BNXT_ULP_CLASS_HID_49182] = 1521,
+ [BNXT_ULP_CLASS_HID_4816c] = 1522,
+ [BNXT_ULP_CLASS_HID_58140] = 1523,
+ [BNXT_ULP_CLASS_HID_5908c] = 1524,
+ [BNXT_ULP_CLASS_HID_40c8c] = 1525,
+ [BNXT_ULP_CLASS_HID_41cc8] = 1526,
+ [BNXT_ULP_CLASS_HID_51c0c] = 1527,
+ [BNXT_ULP_CLASS_HID_50386] = 1528,
+ [BNXT_ULP_CLASS_HID_484c4] = 1529,
+ [BNXT_ULP_CLASS_HID_48b8e] = 1530,
+ [BNXT_ULP_CLASS_HID_58b82] = 1531,
+ [BNXT_ULP_CLASS_HID_59bce] = 1532,
+ [BNXT_ULP_CLASS_HID_10a54] = 1533,
+ [BNXT_ULP_CLASS_HID_11e74] = 1534,
+ [BNXT_ULP_CLASS_HID_14e48] = 1535,
+ [BNXT_ULP_CLASS_HID_15268] = 1536,
+ [BNXT_ULP_CLASS_HID_1285a] = 1537,
+ [BNXT_ULP_CLASS_HID_13c7a] = 1538,
+ [BNXT_ULP_CLASS_HID_163be] = 1539,
+ [BNXT_ULP_CLASS_HID_1705e] = 1540,
+ [BNXT_ULP_CLASS_HID_11d5e] = 1541,
+ [BNXT_ULP_CLASS_HID_1009c] = 1542,
+ [BNXT_ULP_CLASS_HID_150ba] = 1543,
+ [BNXT_ULP_CLASS_HID_144f8] = 1544,
+ [BNXT_ULP_CLASS_HID_1334c] = 1545,
+ [BNXT_ULP_CLASS_HID_1268a] = 1546,
+ [BNXT_ULP_CLASS_HID_176a8] = 1547,
+ [BNXT_ULP_CLASS_HID_17aee] = 1548,
+ [BNXT_ULP_CLASS_HID_11782] = 1549,
+ [BNXT_ULP_CLASS_HID_11bc0] = 1550,
+ [BNXT_ULP_CLASS_HID_14b00] = 1551,
+ [BNXT_ULP_CLASS_HID_15f20] = 1552,
+ [BNXT_ULP_CLASS_HID_135f0] = 1553,
+ [BNXT_ULP_CLASS_HID_13932] = 1554,
+ [BNXT_ULP_CLASS_HID_1690a] = 1555,
+ [BNXT_ULP_CLASS_HID_17d2a] = 1556,
+ [BNXT_ULP_CLASS_HID_11a2a] = 1557,
+ [BNXT_ULP_CLASS_HID_10e68] = 1558,
+ [BNXT_ULP_CLASS_HID_15e0a] = 1559,
+ [BNXT_ULP_CLASS_HID_14248] = 1560,
+ [BNXT_ULP_CLASS_HID_13818] = 1561,
+ [BNXT_ULP_CLASS_HID_12c5a] = 1562,
+ [BNXT_ULP_CLASS_HID_17c78] = 1563,
+ [BNXT_ULP_CLASS_HID_167ba] = 1564,
+ [BNXT_ULP_CLASS_HID_1f91] = 1565,
+ [BNXT_ULP_CLASS_HID_0763] = 1566,
+ [BNXT_ULP_CLASS_HID_0f7b] = 1567,
+ [BNXT_ULP_CLASS_HID_16af] = 1568,
+ [BNXT_ULP_CLASS_HID_1daf] = 1569,
+ [BNXT_ULP_CLASS_HID_0539] = 1570,
+ [BNXT_ULP_CLASS_HID_01ed] = 1571,
+ [BNXT_ULP_CLASS_HID_097f] = 1572,
+ [BNXT_ULP_CLASS_HID_81ab8] = 1573,
+ [BNXT_ULP_CLASS_HID_8020e] = 1574,
+ [BNXT_ULP_CLASS_HID_815d8] = 1575,
+ [BNXT_ULP_CLASS_HID_81cae] = 1576,
+ [BNXT_ULP_CLASS_HID_810a8] = 1577,
+ [BNXT_ULP_CLASS_HID_8183e] = 1578,
+ [BNXT_ULP_CLASS_HID_8036a] = 1579,
+ [BNXT_ULP_CLASS_HID_80af8] = 1580,
+ [BNXT_ULP_CLASS_HID_206fe] = 1581,
+ [BNXT_ULP_CLASS_HID_20e4c] = 1582,
+ [BNXT_ULP_CLASS_HID_2111e] = 1583,
+ [BNXT_ULP_CLASS_HID_218ec] = 1584,
+ [BNXT_ULP_CLASS_HID_60472] = 1585,
+ [BNXT_ULP_CLASS_HID_603c0] = 1586,
+ [BNXT_ULP_CLASS_HID_61692] = 1587,
+ [BNXT_ULP_CLASS_HID_61e60] = 1588,
+ [BNXT_ULP_CLASS_HID_1f81] = 1589,
+ [BNXT_ULP_CLASS_HID_0773] = 1590,
+ [BNXT_ULP_CLASS_HID_0f6b] = 1591,
+ [BNXT_ULP_CLASS_HID_16bf] = 1592,
+ [BNXT_ULP_CLASS_HID_03cf] = 1593,
+ [BNXT_ULP_CLASS_HID_0ab1] = 1594,
+ [BNXT_ULP_CLASS_HID_130b] = 1595,
+ [BNXT_ULP_CLASS_HID_1afd] = 1596,
+ [BNXT_ULP_CLASS_HID_1591] = 1597,
+ [BNXT_ULP_CLASS_HID_1d03] = 1598,
+ [BNXT_ULP_CLASS_HID_057b] = 1599,
+ [BNXT_ULP_CLASS_HID_0ced] = 1600,
+ [BNXT_ULP_CLASS_HID_19df] = 1601,
+ [BNXT_ULP_CLASS_HID_0141] = 1602,
+ [BNXT_ULP_CLASS_HID_08b9] = 1603,
+ [BNXT_ULP_CLASS_HID_108d] = 1604,
+ [BNXT_ULP_CLASS_HID_1dbf] = 1605,
+ [BNXT_ULP_CLASS_HID_0529] = 1606,
+ [BNXT_ULP_CLASS_HID_01fd] = 1607,
+ [BNXT_ULP_CLASS_HID_096f] = 1608,
+ [BNXT_ULP_CLASS_HID_810b7] = 1609,
+ [BNXT_ULP_CLASS_HID_81821] = 1610,
+ [BNXT_ULP_CLASS_HID_804f5] = 1611,
+ [BNXT_ULP_CLASS_HID_80c67] = 1612,
+ [BNXT_ULP_CLASS_HID_41333] = 1613,
+ [BNXT_ULP_CLASS_HID_41aad] = 1614,
+ [BNXT_ULP_CLASS_HID_40771] = 1615,
+ [BNXT_ULP_CLASS_HID_40ee3] = 1616,
+ [BNXT_ULP_CLASS_HID_c16cb] = 1617,
+ [BNXT_ULP_CLASS_HID_c1da5] = 1618,
+ [BNXT_ULP_CLASS_HID_c1a09] = 1619,
+ [BNXT_ULP_CLASS_HID_c01fb] = 1620,
+ [BNXT_ULP_CLASS_HID_1ff1] = 1621,
+ [BNXT_ULP_CLASS_HID_0703] = 1622,
+ [BNXT_ULP_CLASS_HID_0f1b] = 1623,
+ [BNXT_ULP_CLASS_HID_16cf] = 1624,
+ [BNXT_ULP_CLASS_HID_03bf] = 1625,
+ [BNXT_ULP_CLASS_HID_0ac1] = 1626,
+ [BNXT_ULP_CLASS_HID_137b] = 1627,
+ [BNXT_ULP_CLASS_HID_1a8d] = 1628,
+ [BNXT_ULP_CLASS_HID_15e1] = 1629,
+ [BNXT_ULP_CLASS_HID_1d73] = 1630,
+ [BNXT_ULP_CLASS_HID_050b] = 1631,
+ [BNXT_ULP_CLASS_HID_0c9d] = 1632,
+ [BNXT_ULP_CLASS_HID_19af] = 1633,
+ [BNXT_ULP_CLASS_HID_0131] = 1634,
+ [BNXT_ULP_CLASS_HID_08c9] = 1635,
+ [BNXT_ULP_CLASS_HID_10fd] = 1636,
+ [BNXT_ULP_CLASS_HID_1dcf] = 1637,
+ [BNXT_ULP_CLASS_HID_0559] = 1638,
+ [BNXT_ULP_CLASS_HID_018d] = 1639,
+ [BNXT_ULP_CLASS_HID_091f] = 1640,
+ [BNXT_ULP_CLASS_HID_810c7] = 1641,
+ [BNXT_ULP_CLASS_HID_81851] = 1642,
+ [BNXT_ULP_CLASS_HID_80485] = 1643,
+ [BNXT_ULP_CLASS_HID_80c17] = 1644,
+ [BNXT_ULP_CLASS_HID_41343] = 1645,
+ [BNXT_ULP_CLASS_HID_41add] = 1646,
+ [BNXT_ULP_CLASS_HID_40701] = 1647,
+ [BNXT_ULP_CLASS_HID_40e93] = 1648,
+ [BNXT_ULP_CLASS_HID_c16bb] = 1649,
+ [BNXT_ULP_CLASS_HID_c1dd5] = 1650,
+ [BNXT_ULP_CLASS_HID_c1a79] = 1651,
+ [BNXT_ULP_CLASS_HID_c018b] = 1652,
+ [BNXT_ULP_CLASS_HID_81aa8] = 1653,
+ [BNXT_ULP_CLASS_HID_8021e] = 1654,
+ [BNXT_ULP_CLASS_HID_815c8] = 1655,
+ [BNXT_ULP_CLASS_HID_81cbe] = 1656,
+ [BNXT_ULP_CLASS_HID_810b8] = 1657,
+ [BNXT_ULP_CLASS_HID_8182e] = 1658,
+ [BNXT_ULP_CLASS_HID_8037a] = 1659,
+ [BNXT_ULP_CLASS_HID_80ae8] = 1660,
+ [BNXT_ULP_CLASS_HID_c1834] = 1661,
+ [BNXT_ULP_CLASS_HID_c079a] = 1662,
+ [BNXT_ULP_CLASS_HID_c0af6] = 1663,
+ [BNXT_ULP_CLASS_HID_c123a] = 1664,
+ [BNXT_ULP_CLASS_HID_c16c4] = 1665,
+ [BNXT_ULP_CLASS_HID_c1daa] = 1666,
+ [BNXT_ULP_CLASS_HID_c0086] = 1667,
+ [BNXT_ULP_CLASS_HID_c0874] = 1668,
+ [BNXT_ULP_CLASS_HID_a19ea] = 1669,
+ [BNXT_ULP_CLASS_HID_a0158] = 1670,
+ [BNXT_ULP_CLASS_HID_a0bb4] = 1671,
+ [BNXT_ULP_CLASS_HID_a13f8] = 1672,
+ [BNXT_ULP_CLASS_HID_a17fa] = 1673,
+ [BNXT_ULP_CLASS_HID_a1f68] = 1674,
+ [BNXT_ULP_CLASS_HID_a0244] = 1675,
+ [BNXT_ULP_CLASS_HID_a092a] = 1676,
+ [BNXT_ULP_CLASS_HID_e1f76] = 1677,
+ [BNXT_ULP_CLASS_HID_e06e4] = 1678,
+ [BNXT_ULP_CLASS_HID_e0930] = 1679,
+ [BNXT_ULP_CLASS_HID_e1104] = 1680,
+ [BNXT_ULP_CLASS_HID_e1506] = 1681,
+ [BNXT_ULP_CLASS_HID_e1cf4] = 1682,
+ [BNXT_ULP_CLASS_HID_e07c0] = 1683,
+ [BNXT_ULP_CLASS_HID_e0eb6] = 1684,
+ [BNXT_ULP_CLASS_HID_206ee] = 1685,
+ [BNXT_ULP_CLASS_HID_20e5c] = 1686,
+ [BNXT_ULP_CLASS_HID_2110e] = 1687,
+ [BNXT_ULP_CLASS_HID_218fc] = 1688,
+ [BNXT_ULP_CLASS_HID_60462] = 1689,
+ [BNXT_ULP_CLASS_HID_603d0] = 1690,
+ [BNXT_ULP_CLASS_HID_61682] = 1691,
+ [BNXT_ULP_CLASS_HID_61e70] = 1692,
+ [BNXT_ULP_CLASS_HID_3167e] = 1693,
+ [BNXT_ULP_CLASS_HID_31dec] = 1694,
+ [BNXT_ULP_CLASS_HID_30030] = 1695,
+ [BNXT_ULP_CLASS_HID_30fae] = 1696,
+ [BNXT_ULP_CLASS_HID_70b14] = 1697,
+ [BNXT_ULP_CLASS_HID_71360] = 1698,
+ [BNXT_ULP_CLASS_HID_705b4] = 1699,
+ [BNXT_ULP_CLASS_HID_70d22] = 1700,
+ [BNXT_ULP_CLASS_HID_29e26] = 1701,
+ [BNXT_ULP_CLASS_HID_28594] = 1702,
+ [BNXT_ULP_CLASS_HID_288f8] = 1703,
+ [BNXT_ULP_CLASS_HID_29034] = 1704,
+ [BNXT_ULP_CLASS_HID_693ba] = 1705,
+ [BNXT_ULP_CLASS_HID_69b28] = 1706,
+ [BNXT_ULP_CLASS_HID_68e7c] = 1707,
+ [BNXT_ULP_CLASS_HID_69648] = 1708,
+ [BNXT_ULP_CLASS_HID_38de8] = 1709,
+ [BNXT_ULP_CLASS_HID_39524] = 1710,
+ [BNXT_ULP_CLASS_HID_39808] = 1711,
+ [BNXT_ULP_CLASS_HID_387e6] = 1712,
+ [BNXT_ULP_CLASS_HID_7836c] = 1713,
+ [BNXT_ULP_CLASS_HID_78ada] = 1714,
+ [BNXT_ULP_CLASS_HID_79d8c] = 1715,
+ [BNXT_ULP_CLASS_HID_7857a] = 1716,
+ [BNXT_ULP_CLASS_HID_81ad8] = 1717,
+ [BNXT_ULP_CLASS_HID_8026e] = 1718,
+ [BNXT_ULP_CLASS_HID_815b8] = 1719,
+ [BNXT_ULP_CLASS_HID_81cce] = 1720,
+ [BNXT_ULP_CLASS_HID_810c8] = 1721,
+ [BNXT_ULP_CLASS_HID_8185e] = 1722,
+ [BNXT_ULP_CLASS_HID_8030a] = 1723,
+ [BNXT_ULP_CLASS_HID_80a98] = 1724,
+ [BNXT_ULP_CLASS_HID_c1844] = 1725,
+ [BNXT_ULP_CLASS_HID_c07ea] = 1726,
+ [BNXT_ULP_CLASS_HID_c0a86] = 1727,
+ [BNXT_ULP_CLASS_HID_c124a] = 1728,
+ [BNXT_ULP_CLASS_HID_c16b4] = 1729,
+ [BNXT_ULP_CLASS_HID_c1dda] = 1730,
+ [BNXT_ULP_CLASS_HID_c00f6] = 1731,
+ [BNXT_ULP_CLASS_HID_c0804] = 1732,
+ [BNXT_ULP_CLASS_HID_a199a] = 1733,
+ [BNXT_ULP_CLASS_HID_a0128] = 1734,
+ [BNXT_ULP_CLASS_HID_a0bc4] = 1735,
+ [BNXT_ULP_CLASS_HID_a1388] = 1736,
+ [BNXT_ULP_CLASS_HID_a178a] = 1737,
+ [BNXT_ULP_CLASS_HID_a1f18] = 1738,
+ [BNXT_ULP_CLASS_HID_a0234] = 1739,
+ [BNXT_ULP_CLASS_HID_a095a] = 1740,
+ [BNXT_ULP_CLASS_HID_e1f06] = 1741,
+ [BNXT_ULP_CLASS_HID_e0694] = 1742,
+ [BNXT_ULP_CLASS_HID_e0940] = 1743,
+ [BNXT_ULP_CLASS_HID_e1174] = 1744,
+ [BNXT_ULP_CLASS_HID_e1576] = 1745,
+ [BNXT_ULP_CLASS_HID_e1c84] = 1746,
+ [BNXT_ULP_CLASS_HID_e07b0] = 1747,
+ [BNXT_ULP_CLASS_HID_e0ec6] = 1748,
+ [BNXT_ULP_CLASS_HID_2069e] = 1749,
+ [BNXT_ULP_CLASS_HID_20e2c] = 1750,
+ [BNXT_ULP_CLASS_HID_2117e] = 1751,
+ [BNXT_ULP_CLASS_HID_2188c] = 1752,
+ [BNXT_ULP_CLASS_HID_60412] = 1753,
+ [BNXT_ULP_CLASS_HID_603a0] = 1754,
+ [BNXT_ULP_CLASS_HID_616f2] = 1755,
+ [BNXT_ULP_CLASS_HID_61e00] = 1756,
+ [BNXT_ULP_CLASS_HID_3160e] = 1757,
+ [BNXT_ULP_CLASS_HID_31d9c] = 1758,
+ [BNXT_ULP_CLASS_HID_30040] = 1759,
+ [BNXT_ULP_CLASS_HID_30fde] = 1760,
+ [BNXT_ULP_CLASS_HID_70b64] = 1761,
+ [BNXT_ULP_CLASS_HID_71310] = 1762,
+ [BNXT_ULP_CLASS_HID_705c4] = 1763,
+ [BNXT_ULP_CLASS_HID_70d52] = 1764,
+ [BNXT_ULP_CLASS_HID_29e56] = 1765,
+ [BNXT_ULP_CLASS_HID_285e4] = 1766,
+ [BNXT_ULP_CLASS_HID_28888] = 1767,
+ [BNXT_ULP_CLASS_HID_29044] = 1768,
+ [BNXT_ULP_CLASS_HID_693ca] = 1769,
+ [BNXT_ULP_CLASS_HID_69b58] = 1770,
+ [BNXT_ULP_CLASS_HID_68e0c] = 1771,
+ [BNXT_ULP_CLASS_HID_69638] = 1772,
+ [BNXT_ULP_CLASS_HID_38d98] = 1773,
+ [BNXT_ULP_CLASS_HID_39554] = 1774,
+ [BNXT_ULP_CLASS_HID_39878] = 1775,
+ [BNXT_ULP_CLASS_HID_38796] = 1776,
+ [BNXT_ULP_CLASS_HID_7831c] = 1777,
+ [BNXT_ULP_CLASS_HID_78aaa] = 1778,
+ [BNXT_ULP_CLASS_HID_79dfc] = 1779,
+ [BNXT_ULP_CLASS_HID_7850a] = 1780,
+ [BNXT_ULP_CLASS_HID_03b7] = 1781,
+ [BNXT_ULP_CLASS_HID_13f3] = 1782,
+ [BNXT_ULP_CLASS_HID_0255] = 1783,
+ [BNXT_ULP_CLASS_HID_1675] = 1784,
+ [BNXT_ULP_CLASS_HID_80f52] = 1785,
+ [BNXT_ULP_CLASS_HID_819f2] = 1786,
+ [BNXT_ULP_CLASS_HID_80542] = 1787,
+ [BNXT_ULP_CLASS_HID_817e2] = 1788,
+ [BNXT_ULP_CLASS_HID_20a98] = 1789,
+ [BNXT_ULP_CLASS_HID_20538] = 1790,
+ [BNXT_ULP_CLASS_HID_6081c] = 1791,
+ [BNXT_ULP_CLASS_HID_61abc] = 1792,
+ [BNXT_ULP_CLASS_HID_03a7] = 1793,
+ [BNXT_ULP_CLASS_HID_13e3] = 1794,
+ [BNXT_ULP_CLASS_HID_1047] = 1795,
+ [BNXT_ULP_CLASS_HID_0721] = 1796,
+ [BNXT_ULP_CLASS_HID_19b7] = 1797,
+ [BNXT_ULP_CLASS_HID_0911] = 1798,
+ [BNXT_ULP_CLASS_HID_0df5] = 1799,
+ [BNXT_ULP_CLASS_HID_1d31] = 1800,
+ [BNXT_ULP_CLASS_HID_0245] = 1801,
+ [BNXT_ULP_CLASS_HID_1665] = 1802,
+ [BNXT_ULP_CLASS_HID_8055d] = 1803,
+ [BNXT_ULP_CLASS_HID_80893] = 1804,
+ [BNXT_ULP_CLASS_HID_407d9] = 1805,
+ [BNXT_ULP_CLASS_HID_40b1f] = 1806,
+ [BNXT_ULP_CLASS_HID_c1ad1] = 1807,
+ [BNXT_ULP_CLASS_HID_c0e17] = 1808,
+ [BNXT_ULP_CLASS_HID_03d7] = 1809,
+ [BNXT_ULP_CLASS_HID_1393] = 1810,
+ [BNXT_ULP_CLASS_HID_1037] = 1811,
+ [BNXT_ULP_CLASS_HID_0751] = 1812,
+ [BNXT_ULP_CLASS_HID_19c7] = 1813,
+ [BNXT_ULP_CLASS_HID_0961] = 1814,
+ [BNXT_ULP_CLASS_HID_0d85] = 1815,
+ [BNXT_ULP_CLASS_HID_1d41] = 1816,
+ [BNXT_ULP_CLASS_HID_0235] = 1817,
+ [BNXT_ULP_CLASS_HID_1615] = 1818,
+ [BNXT_ULP_CLASS_HID_8052d] = 1819,
+ [BNXT_ULP_CLASS_HID_808e3] = 1820,
+ [BNXT_ULP_CLASS_HID_407a9] = 1821,
+ [BNXT_ULP_CLASS_HID_40b6f] = 1822,
+ [BNXT_ULP_CLASS_HID_c1aa1] = 1823,
+ [BNXT_ULP_CLASS_HID_c0e67] = 1824,
+ [BNXT_ULP_CLASS_HID_80f42] = 1825,
+ [BNXT_ULP_CLASS_HID_819e2] = 1826,
+ [BNXT_ULP_CLASS_HID_80552] = 1827,
+ [BNXT_ULP_CLASS_HID_817f2] = 1828,
+ [BNXT_ULP_CLASS_HID_c0cce] = 1829,
+ [BNXT_ULP_CLASS_HID_c1f6e] = 1830,
+ [BNXT_ULP_CLASS_HID_c1ade] = 1831,
+ [BNXT_ULP_CLASS_HID_c157e] = 1832,
+ [BNXT_ULP_CLASS_HID_a0d8c] = 1833,
+ [BNXT_ULP_CLASS_HID_a182c] = 1834,
+ [BNXT_ULP_CLASS_HID_a1b9c] = 1835,
+ [BNXT_ULP_CLASS_HID_a163c] = 1836,
+ [BNXT_ULP_CLASS_HID_e0308] = 1837,
+ [BNXT_ULP_CLASS_HID_e1da8] = 1838,
+ [BNXT_ULP_CLASS_HID_e1918] = 1839,
+ [BNXT_ULP_CLASS_HID_e0bda] = 1840,
+ [BNXT_ULP_CLASS_HID_20a88] = 1841,
+ [BNXT_ULP_CLASS_HID_20528] = 1842,
+ [BNXT_ULP_CLASS_HID_6080c] = 1843,
+ [BNXT_ULP_CLASS_HID_61aac] = 1844,
+ [BNXT_ULP_CLASS_HID_31a18] = 1845,
+ [BNXT_ULP_CLASS_HID_314b8] = 1846,
+ [BNXT_ULP_CLASS_HID_71f9c] = 1847,
+ [BNXT_ULP_CLASS_HID_70a5e] = 1848,
+ [BNXT_ULP_CLASS_HID_282c0] = 1849,
+ [BNXT_ULP_CLASS_HID_29d60] = 1850,
+ [BNXT_ULP_CLASS_HID_68044] = 1851,
+ [BNXT_ULP_CLASS_HID_692e4] = 1852,
+ [BNXT_ULP_CLASS_HID_39250] = 1853,
+ [BNXT_ULP_CLASS_HID_38c12] = 1854,
+ [BNXT_ULP_CLASS_HID_797d4] = 1855,
+ [BNXT_ULP_CLASS_HID_78196] = 1856,
+ [BNXT_ULP_CLASS_HID_80f32] = 1857,
+ [BNXT_ULP_CLASS_HID_81992] = 1858,
+ [BNXT_ULP_CLASS_HID_80522] = 1859,
+ [BNXT_ULP_CLASS_HID_81782] = 1860,
+ [BNXT_ULP_CLASS_HID_c0cbe] = 1861,
+ [BNXT_ULP_CLASS_HID_c1f1e] = 1862,
+ [BNXT_ULP_CLASS_HID_c1aae] = 1863,
+ [BNXT_ULP_CLASS_HID_c150e] = 1864,
+ [BNXT_ULP_CLASS_HID_a0dfc] = 1865,
+ [BNXT_ULP_CLASS_HID_a185c] = 1866,
+ [BNXT_ULP_CLASS_HID_a1bec] = 1867,
+ [BNXT_ULP_CLASS_HID_a164c] = 1868,
+ [BNXT_ULP_CLASS_HID_e0378] = 1869,
+ [BNXT_ULP_CLASS_HID_e1dd8] = 1870,
+ [BNXT_ULP_CLASS_HID_e1968] = 1871,
+ [BNXT_ULP_CLASS_HID_e0baa] = 1872,
+ [BNXT_ULP_CLASS_HID_20af8] = 1873,
+ [BNXT_ULP_CLASS_HID_20558] = 1874,
+ [BNXT_ULP_CLASS_HID_6087c] = 1875,
+ [BNXT_ULP_CLASS_HID_61adc] = 1876,
+ [BNXT_ULP_CLASS_HID_31a68] = 1877,
+ [BNXT_ULP_CLASS_HID_314c8] = 1878,
+ [BNXT_ULP_CLASS_HID_71fec] = 1879,
+ [BNXT_ULP_CLASS_HID_70a2e] = 1880,
+ [BNXT_ULP_CLASS_HID_282b0] = 1881,
+ [BNXT_ULP_CLASS_HID_29d10] = 1882,
+ [BNXT_ULP_CLASS_HID_68034] = 1883,
+ [BNXT_ULP_CLASS_HID_69294] = 1884,
+ [BNXT_ULP_CLASS_HID_39220] = 1885,
+ [BNXT_ULP_CLASS_HID_38c62] = 1886,
+ [BNXT_ULP_CLASS_HID_797a4] = 1887,
+ [BNXT_ULP_CLASS_HID_781e6] = 1888,
+ [BNXT_ULP_CLASS_HID_0f05] = 1889,
+ [BNXT_ULP_CLASS_HID_0f09] = 1890,
+ [BNXT_ULP_CLASS_HID_0f06] = 1891,
+ [BNXT_ULP_CLASS_HID_19a6] = 1892,
+ [BNXT_ULP_CLASS_HID_0f0a] = 1893,
+ [BNXT_ULP_CLASS_HID_19aa] = 1894,
+ [BNXT_ULP_CLASS_HID_0f15] = 1895,
+ [BNXT_ULP_CLASS_HID_0f19] = 1896,
+ [BNXT_ULP_CLASS_HID_0f65] = 1897,
+ [BNXT_ULP_CLASS_HID_0f69] = 1898,
+ [BNXT_ULP_CLASS_HID_0f16] = 1899,
+ [BNXT_ULP_CLASS_HID_19b6] = 1900,
+ [BNXT_ULP_CLASS_HID_0f1a] = 1901,
+ [BNXT_ULP_CLASS_HID_19ba] = 1902,
+ [BNXT_ULP_CLASS_HID_0f66] = 1903,
+ [BNXT_ULP_CLASS_HID_19c6] = 1904,
+ [BNXT_ULP_CLASS_HID_0f6a] = 1905,
+ [BNXT_ULP_CLASS_HID_19ca] = 1906
};
/* Array for the proto matcher list */
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
[1] = {
- .class_hid = BNXT_ULP_CLASS_HID_55dd,
+ .class_hid = BNXT_ULP_CLASS_HID_00b8,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -1332,7 +1940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[2] = {
- .class_hid = BNXT_ULP_CLASS_HID_1df1,
+ .class_hid = BNXT_ULP_CLASS_HID_0cc2,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4104UL,
@@ -1348,7 +1956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[3] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e55,
+ .class_hid = BNXT_ULP_CLASS_HID_10e4,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -1364,7 +1972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[4] = {
- .class_hid = BNXT_ULP_CLASS_HID_0649,
+ .class_hid = BNXT_ULP_CLASS_HID_1d0e,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6152UL,
@@ -1381,7 +1989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[5] = {
- .class_hid = BNXT_ULP_CLASS_HID_1011,
+ .class_hid = BNXT_ULP_CLASS_HID_0286,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -1396,7 +2004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[6] = {
- .class_hid = BNXT_ULP_CLASS_HID_40e9,
+ .class_hid = BNXT_ULP_CLASS_HID_0e98,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16392UL,
@@ -1412,7 +2020,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[7] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e99,
+ .class_hid = BNXT_ULP_CLASS_HID_1666,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -1428,7 +2036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[8] = {
- .class_hid = BNXT_ULP_CLASS_HID_06ad,
+ .class_hid = BNXT_ULP_CLASS_HID_02de,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24584UL,
@@ -1445,7 +2053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[9] = {
- .class_hid = BNXT_ULP_CLASS_HID_38c7,
+ .class_hid = BNXT_ULP_CLASS_HID_81d25,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -1461,7 +2069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[10] = {
- .class_hid = BNXT_ULP_CLASS_HID_00fb,
+ .class_hid = BNXT_ULP_CLASS_HID_809ad,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32776UL,
@@ -1478,7 +2086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[11] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d3,
+ .class_hid = BNXT_ULP_CLASS_HID_80ae3,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -1495,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[12] = {
- .class_hid = BNXT_ULP_CLASS_HID_559b,
+ .class_hid = BNXT_ULP_CLASS_HID_8170d,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32840UL,
@@ -1513,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[13] = {
- .class_hid = BNXT_ULP_CLASS_HID_5003,
+ .class_hid = BNXT_ULP_CLASS_HID_80773,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -1530,7 +2138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[14] = {
- .class_hid = BNXT_ULP_CLASS_HID_1837,
+ .class_hid = BNXT_ULP_CLASS_HID_8139d,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49160UL,
@@ -1548,7 +2156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[15] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bef,
+ .class_hid = BNXT_ULP_CLASS_HID_814d3,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -1566,7 +2174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[16] = {
- .class_hid = BNXT_ULP_CLASS_HID_0403,
+ .class_hid = BNXT_ULP_CLASS_HID_8015b,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49224UL,
@@ -1585,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[17] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d3f,
+ .class_hid = BNXT_ULP_CLASS_HID_21977,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -1601,7 +2209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[18] = {
- .class_hid = BNXT_ULP_CLASS_HID_0543,
+ .class_hid = BNXT_ULP_CLASS_HID_205ef,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131080UL,
@@ -1618,7 +2226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[19] = {
- .class_hid = BNXT_ULP_CLASS_HID_292b,
+ .class_hid = BNXT_ULP_CLASS_HID_20735,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -1635,7 +2243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[20] = {
- .class_hid = BNXT_ULP_CLASS_HID_59e3,
+ .class_hid = BNXT_ULP_CLASS_HID_2134f,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131144UL,
@@ -1653,7 +2261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[21] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d3b,
+ .class_hid = BNXT_ULP_CLASS_HID_61beb,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -1670,7 +2278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[22] = {
- .class_hid = BNXT_ULP_CLASS_HID_254f,
+ .class_hid = BNXT_ULP_CLASS_HID_60863,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196616UL,
@@ -1688,7 +2296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[23] = {
- .class_hid = BNXT_ULP_CLASS_HID_4917,
+ .class_hid = BNXT_ULP_CLASS_HID_609a9,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -1706,7 +2314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[24] = {
- .class_hid = BNXT_ULP_CLASS_HID_113b,
+ .class_hid = BNXT_ULP_CLASS_HID_615c3,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196680UL,
@@ -1725,7 +2333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[25] = {
- .class_hid = BNXT_ULP_CLASS_HID_55fd,
+ .class_hid = BNXT_ULP_CLASS_HID_00a8,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -1741,7 +2349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[26] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dd1,
+ .class_hid = BNXT_ULP_CLASS_HID_0cd2,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4104UL,
@@ -1758,7 +2366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[27] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e75,
+ .class_hid = BNXT_ULP_CLASS_HID_10f4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -1775,7 +2383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[28] = {
- .class_hid = BNXT_ULP_CLASS_HID_0669,
+ .class_hid = BNXT_ULP_CLASS_HID_1d1e,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6152UL,
@@ -1793,7 +2401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[29] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ba1,
+ .class_hid = BNXT_ULP_CLASS_HID_1488,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -1810,7 +2418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[30] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c69,
+ .class_hid = BNXT_ULP_CLASS_HID_0110,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12296UL,
@@ -1828,7 +2436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[31] = {
- .class_hid = BNXT_ULP_CLASS_HID_0439,
+ .class_hid = BNXT_ULP_CLASS_HID_0532,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -1846,7 +2454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[32] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e1,
+ .class_hid = BNXT_ULP_CLASS_HID_115c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14344UL,
@@ -1865,7 +2473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[33] = {
- .class_hid = BNXT_ULP_CLASS_HID_0465,
+ .class_hid = BNXT_ULP_CLASS_HID_0ab8,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -1882,7 +2490,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[34] = {
- .class_hid = BNXT_ULP_CLASS_HID_352d,
+ .class_hid = BNXT_ULP_CLASS_HID_16a2,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20488UL,
@@ -1900,7 +2508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[35] = {
- .class_hid = BNXT_ULP_CLASS_HID_55b1,
+ .class_hid = BNXT_ULP_CLASS_HID_1ac4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -1918,7 +2526,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[36] = {
- .class_hid = BNXT_ULP_CLASS_HID_1da5,
+ .class_hid = BNXT_ULP_CLASS_HID_074c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22536UL,
@@ -1937,7 +2545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[37] = {
- .class_hid = BNXT_ULP_CLASS_HID_32fd,
+ .class_hid = BNXT_ULP_CLASS_HID_1e98,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -1955,7 +2563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[38] = {
- .class_hid = BNXT_ULP_CLASS_HID_63a5,
+ .class_hid = BNXT_ULP_CLASS_HID_0ae0,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28680UL,
@@ -1974,7 +2582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[39] = {
- .class_hid = BNXT_ULP_CLASS_HID_1b75,
+ .class_hid = BNXT_ULP_CLASS_HID_0f02,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -1993,7 +2601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[40] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c3d,
+ .class_hid = BNXT_ULP_CLASS_HID_1b2c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30728UL,
@@ -2013,7 +2621,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[41] = {
- .class_hid = BNXT_ULP_CLASS_HID_1031,
+ .class_hid = BNXT_ULP_CLASS_HID_0296,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -2029,7 +2637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[42] = {
- .class_hid = BNXT_ULP_CLASS_HID_40c9,
+ .class_hid = BNXT_ULP_CLASS_HID_0e88,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16392UL,
@@ -2046,7 +2654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[43] = {
- .class_hid = BNXT_ULP_CLASS_HID_3eb9,
+ .class_hid = BNXT_ULP_CLASS_HID_1676,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -2063,7 +2671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[44] = {
- .class_hid = BNXT_ULP_CLASS_HID_068d,
+ .class_hid = BNXT_ULP_CLASS_HID_02ce,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24584UL,
@@ -2081,7 +2689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[45] = {
- .class_hid = BNXT_ULP_CLASS_HID_5039,
+ .class_hid = BNXT_ULP_CLASS_HID_8076e,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -2098,7 +2706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[46] = {
- .class_hid = BNXT_ULP_CLASS_HID_180d,
+ .class_hid = BNXT_ULP_CLASS_HID_81380,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49160UL,
@@ -2116,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[47] = {
- .class_hid = BNXT_ULP_CLASS_HID_15fd,
+ .class_hid = BNXT_ULP_CLASS_HID_81b4e,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -2134,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[48] = {
- .class_hid = BNXT_ULP_CLASS_HID_46b5,
+ .class_hid = BNXT_ULP_CLASS_HID_807c6,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57352UL,
@@ -2153,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[49] = {
- .class_hid = BNXT_ULP_CLASS_HID_303d,
+ .class_hid = BNXT_ULP_CLASS_HID_404ea,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -2170,7 +2778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[50] = {
- .class_hid = BNXT_ULP_CLASS_HID_60f5,
+ .class_hid = BNXT_ULP_CLASS_HID_4110c,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81928UL,
@@ -2188,7 +2796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[51] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ea5,
+ .class_hid = BNXT_ULP_CLASS_HID_418ca,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -2206,7 +2814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[52] = {
- .class_hid = BNXT_ULP_CLASS_HID_2689,
+ .class_hid = BNXT_ULP_CLASS_HID_40542,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90120UL,
@@ -2225,7 +2833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[53] = {
- .class_hid = BNXT_ULP_CLASS_HID_0771,
+ .class_hid = BNXT_ULP_CLASS_HID_c09e2,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -2243,7 +2851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[54] = {
- .class_hid = BNXT_ULP_CLASS_HID_3809,
+ .class_hid = BNXT_ULP_CLASS_HID_c1604,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114696UL,
@@ -2262,7 +2870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[55] = {
- .class_hid = BNXT_ULP_CLASS_HID_35f9,
+ .class_hid = BNXT_ULP_CLASS_HID_c1dc2,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -2281,7 +2889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[56] = {
- .class_hid = BNXT_ULP_CLASS_HID_66b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c0a5a,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122888UL,
@@ -2301,7 +2909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[57] = {
- .class_hid = BNXT_ULP_CLASS_HID_559d,
+ .class_hid = BNXT_ULP_CLASS_HID_0098,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -2317,7 +2925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[58] = {
- .class_hid = BNXT_ULP_CLASS_HID_1db1,
+ .class_hid = BNXT_ULP_CLASS_HID_0ce2,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4104UL,
@@ -2334,7 +2942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[59] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e15,
+ .class_hid = BNXT_ULP_CLASS_HID_10c4,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -2351,7 +2959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[60] = {
- .class_hid = BNXT_ULP_CLASS_HID_0609,
+ .class_hid = BNXT_ULP_CLASS_HID_1d2e,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6152UL,
@@ -2369,7 +2977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[61] = {
- .class_hid = BNXT_ULP_CLASS_HID_1bc1,
+ .class_hid = BNXT_ULP_CLASS_HID_14b8,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -2386,7 +2994,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[62] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c09,
+ .class_hid = BNXT_ULP_CLASS_HID_0120,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12296UL,
@@ -2404,7 +3012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[63] = {
- .class_hid = BNXT_ULP_CLASS_HID_0459,
+ .class_hid = BNXT_ULP_CLASS_HID_0502,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -2422,7 +3030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[64] = {
- .class_hid = BNXT_ULP_CLASS_HID_3481,
+ .class_hid = BNXT_ULP_CLASS_HID_116c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14344UL,
@@ -2441,7 +3049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[65] = {
- .class_hid = BNXT_ULP_CLASS_HID_0405,
+ .class_hid = BNXT_ULP_CLASS_HID_0a88,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -2458,7 +3066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[66] = {
- .class_hid = BNXT_ULP_CLASS_HID_354d,
+ .class_hid = BNXT_ULP_CLASS_HID_1692,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20488UL,
@@ -2476,7 +3084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[67] = {
- .class_hid = BNXT_ULP_CLASS_HID_55d1,
+ .class_hid = BNXT_ULP_CLASS_HID_1af4,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -2494,7 +3102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[68] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dc5,
+ .class_hid = BNXT_ULP_CLASS_HID_077c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22536UL,
@@ -2513,7 +3121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[69] = {
- .class_hid = BNXT_ULP_CLASS_HID_329d,
+ .class_hid = BNXT_ULP_CLASS_HID_1ea8,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -2531,7 +3139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[70] = {
- .class_hid = BNXT_ULP_CLASS_HID_63c5,
+ .class_hid = BNXT_ULP_CLASS_HID_0ad0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28680UL,
@@ -2550,7 +3158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[71] = {
- .class_hid = BNXT_ULP_CLASS_HID_1b15,
+ .class_hid = BNXT_ULP_CLASS_HID_0f32,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -2569,7 +3177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[72] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c5d,
+ .class_hid = BNXT_ULP_CLASS_HID_1b1c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30728UL,
@@ -2589,7 +3197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[73] = {
- .class_hid = BNXT_ULP_CLASS_HID_1051,
+ .class_hid = BNXT_ULP_CLASS_HID_02a6,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -2605,7 +3213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[74] = {
- .class_hid = BNXT_ULP_CLASS_HID_40a9,
+ .class_hid = BNXT_ULP_CLASS_HID_0eb8,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16392UL,
@@ -2622,7 +3230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[75] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ed9,
+ .class_hid = BNXT_ULP_CLASS_HID_1646,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -2639,7 +3247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[76] = {
- .class_hid = BNXT_ULP_CLASS_HID_06ed,
+ .class_hid = BNXT_ULP_CLASS_HID_02fe,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24584UL,
@@ -2657,7 +3265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[77] = {
- .class_hid = BNXT_ULP_CLASS_HID_5059,
+ .class_hid = BNXT_ULP_CLASS_HID_8075e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -2674,7 +3282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[78] = {
- .class_hid = BNXT_ULP_CLASS_HID_186d,
+ .class_hid = BNXT_ULP_CLASS_HID_813b0,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49160UL,
@@ -2692,7 +3300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[79] = {
- .class_hid = BNXT_ULP_CLASS_HID_159d,
+ .class_hid = BNXT_ULP_CLASS_HID_81b7e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -2710,7 +3318,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[80] = {
- .class_hid = BNXT_ULP_CLASS_HID_46d5,
+ .class_hid = BNXT_ULP_CLASS_HID_807f6,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57352UL,
@@ -2729,7 +3337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[81] = {
- .class_hid = BNXT_ULP_CLASS_HID_305d,
+ .class_hid = BNXT_ULP_CLASS_HID_404da,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -2746,7 +3354,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[82] = {
- .class_hid = BNXT_ULP_CLASS_HID_6095,
+ .class_hid = BNXT_ULP_CLASS_HID_4113c,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81928UL,
@@ -2764,7 +3372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[83] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ec5,
+ .class_hid = BNXT_ULP_CLASS_HID_418fa,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -2782,7 +3390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[84] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e9,
+ .class_hid = BNXT_ULP_CLASS_HID_40572,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90120UL,
@@ -2801,7 +3409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[85] = {
- .class_hid = BNXT_ULP_CLASS_HID_0711,
+ .class_hid = BNXT_ULP_CLASS_HID_c09d2,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -2819,7 +3427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[86] = {
- .class_hid = BNXT_ULP_CLASS_HID_3869,
+ .class_hid = BNXT_ULP_CLASS_HID_c1634,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114696UL,
@@ -2838,7 +3446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[87] = {
- .class_hid = BNXT_ULP_CLASS_HID_3599,
+ .class_hid = BNXT_ULP_CLASS_HID_c1df2,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -2857,7 +3465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[88] = {
- .class_hid = BNXT_ULP_CLASS_HID_66d1,
+ .class_hid = BNXT_ULP_CLASS_HID_c0a6a,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122888UL,
@@ -2877,7 +3485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[89] = {
- .class_hid = BNXT_ULP_CLASS_HID_38e7,
+ .class_hid = BNXT_ULP_CLASS_HID_81d35,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -2894,7 +3502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[90] = {
- .class_hid = BNXT_ULP_CLASS_HID_00db,
+ .class_hid = BNXT_ULP_CLASS_HID_809bd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32776UL,
@@ -2912,7 +3520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[91] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f3,
+ .class_hid = BNXT_ULP_CLASS_HID_80af3,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -2930,7 +3538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[92] = {
- .class_hid = BNXT_ULP_CLASS_HID_55bb,
+ .class_hid = BNXT_ULP_CLASS_HID_8171d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32840UL,
@@ -2949,7 +3557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[93] = {
- .class_hid = BNXT_ULP_CLASS_HID_5023,
+ .class_hid = BNXT_ULP_CLASS_HID_80763,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -2967,7 +3575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[94] = {
- .class_hid = BNXT_ULP_CLASS_HID_1817,
+ .class_hid = BNXT_ULP_CLASS_HID_8138d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49160UL,
@@ -2986,7 +3594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[95] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bcf,
+ .class_hid = BNXT_ULP_CLASS_HID_814c3,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -3005,7 +3613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[96] = {
- .class_hid = BNXT_ULP_CLASS_HID_0423,
+ .class_hid = BNXT_ULP_CLASS_HID_8014b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49224UL,
@@ -3025,7 +3633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[97] = {
- .class_hid = BNXT_ULP_CLASS_HID_58e3,
+ .class_hid = BNXT_ULP_CLASS_HID_c001f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -3043,7 +3651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[98] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d7,
+ .class_hid = BNXT_ULP_CLASS_HID_c0c39,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98312UL,
@@ -3062,7 +3670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[99] = {
- .class_hid = BNXT_ULP_CLASS_HID_448f,
+ .class_hid = BNXT_ULP_CLASS_HID_c0d7f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -3081,7 +3689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[100] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ce3,
+ .class_hid = BNXT_ULP_CLASS_HID_c1999,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98376UL,
@@ -3101,7 +3709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[101] = {
- .class_hid = BNXT_ULP_CLASS_HID_076b,
+ .class_hid = BNXT_ULP_CLASS_HID_c09ef,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -3120,7 +3728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[102] = {
- .class_hid = BNXT_ULP_CLASS_HID_3813,
+ .class_hid = BNXT_ULP_CLASS_HID_c1609,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114696UL,
@@ -3140,7 +3748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[103] = {
- .class_hid = BNXT_ULP_CLASS_HID_5bcb,
+ .class_hid = BNXT_ULP_CLASS_HID_c174f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -3160,7 +3768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[104] = {
- .class_hid = BNXT_ULP_CLASS_HID_243f,
+ .class_hid = BNXT_ULP_CLASS_HID_c03d7,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114760UL,
@@ -3181,7 +3789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[105] = {
- .class_hid = BNXT_ULP_CLASS_HID_144b,
+ .class_hid = BNXT_ULP_CLASS_HID_a1e73,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -3199,7 +3807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[106] = {
- .class_hid = BNXT_ULP_CLASS_HID_4573,
+ .class_hid = BNXT_ULP_CLASS_HID_a0afb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163848UL,
@@ -3218,7 +3826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[107] = {
- .class_hid = BNXT_ULP_CLASS_HID_0057,
+ .class_hid = BNXT_ULP_CLASS_HID_a0c31,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -3237,7 +3845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[108] = {
- .class_hid = BNXT_ULP_CLASS_HID_311f,
+ .class_hid = BNXT_ULP_CLASS_HID_a185b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163912UL,
@@ -3257,7 +3865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[109] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b87,
+ .class_hid = BNXT_ULP_CLASS_HID_a08a1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -3276,7 +3884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[110] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c4f,
+ .class_hid = BNXT_ULP_CLASS_HID_a14cb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180232UL,
@@ -3296,7 +3904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[111] = {
- .class_hid = BNXT_ULP_CLASS_HID_1793,
+ .class_hid = BNXT_ULP_CLASS_HID_a1601,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -3316,7 +3924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[112] = {
- .class_hid = BNXT_ULP_CLASS_HID_485b,
+ .class_hid = BNXT_ULP_CLASS_HID_a0289,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180296UL,
@@ -3337,7 +3945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[113] = {
- .class_hid = BNXT_ULP_CLASS_HID_3447,
+ .class_hid = BNXT_ULP_CLASS_HID_e015d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -3356,7 +3964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[114] = {
- .class_hid = BNXT_ULP_CLASS_HID_650f,
+ .class_hid = BNXT_ULP_CLASS_HID_e0d47,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229384UL,
@@ -3376,7 +3984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[115] = {
- .class_hid = BNXT_ULP_CLASS_HID_2053,
+ .class_hid = BNXT_ULP_CLASS_HID_e0ebd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -3396,7 +4004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[116] = {
- .class_hid = BNXT_ULP_CLASS_HID_511b,
+ .class_hid = BNXT_ULP_CLASS_HID_e1aa7,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229448UL,
@@ -3417,7 +4025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[117] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b83,
+ .class_hid = BNXT_ULP_CLASS_HID_e0b2d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -3437,7 +4045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[118] = {
- .class_hid = BNXT_ULP_CLASS_HID_13f7,
+ .class_hid = BNXT_ULP_CLASS_HID_e1757,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245768UL,
@@ -3458,7 +4066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[119] = {
- .class_hid = BNXT_ULP_CLASS_HID_37af,
+ .class_hid = BNXT_ULP_CLASS_HID_e188d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -3479,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[120] = {
- .class_hid = BNXT_ULP_CLASS_HID_6857,
+ .class_hid = BNXT_ULP_CLASS_HID_e0515,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245832UL,
@@ -3501,7 +4109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[121] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d1f,
+ .class_hid = BNXT_ULP_CLASS_HID_21967,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -3518,7 +4126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[122] = {
- .class_hid = BNXT_ULP_CLASS_HID_0563,
+ .class_hid = BNXT_ULP_CLASS_HID_205ff,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131080UL,
@@ -3536,7 +4144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[123] = {
- .class_hid = BNXT_ULP_CLASS_HID_290b,
+ .class_hid = BNXT_ULP_CLASS_HID_20725,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -3554,7 +4162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[124] = {
- .class_hid = BNXT_ULP_CLASS_HID_59c3,
+ .class_hid = BNXT_ULP_CLASS_HID_2135f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131144UL,
@@ -3573,7 +4181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[125] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d1b,
+ .class_hid = BNXT_ULP_CLASS_HID_61bfb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -3591,7 +4199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[126] = {
- .class_hid = BNXT_ULP_CLASS_HID_256f,
+ .class_hid = BNXT_ULP_CLASS_HID_60873,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196616UL,
@@ -3610,7 +4218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[127] = {
- .class_hid = BNXT_ULP_CLASS_HID_4937,
+ .class_hid = BNXT_ULP_CLASS_HID_609b9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -3629,7 +4237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[128] = {
- .class_hid = BNXT_ULP_CLASS_HID_111b,
+ .class_hid = BNXT_ULP_CLASS_HID_615d3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196680UL,
@@ -3649,7 +4257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[129] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f4b,
+ .class_hid = BNXT_ULP_CLASS_HID_30a55,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -3667,7 +4275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[130] = {
- .class_hid = BNXT_ULP_CLASS_HID_2275f,
+ .class_hid = BNXT_ULP_CLASS_HID_3164f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393224UL,
@@ -3686,7 +4294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[131] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b67,
+ .class_hid = BNXT_ULP_CLASS_HID_317b5,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -3705,7 +4313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[132] = {
- .class_hid = BNXT_ULP_CLASS_HID_2134b,
+ .class_hid = BNXT_ULP_CLASS_HID_3040d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393288UL,
@@ -3725,7 +4333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[133] = {
- .class_hid = BNXT_ULP_CLASS_HID_21683,
+ .class_hid = BNXT_ULP_CLASS_HID_70ca9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -3744,7 +4352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[134] = {
- .class_hid = BNXT_ULP_CLASS_HID_2475b,
+ .class_hid = BNXT_ULP_CLASS_HID_718c3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458760UL,
@@ -3764,7 +4372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[135] = {
- .class_hid = BNXT_ULP_CLASS_HID_202bf,
+ .class_hid = BNXT_ULP_CLASS_HID_71a09,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -3784,7 +4392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[136] = {
- .class_hid = BNXT_ULP_CLASS_HID_23377,
+ .class_hid = BNXT_ULP_CLASS_HID_70681,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458824UL,
@@ -3805,7 +4413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[137] = {
- .class_hid = BNXT_ULP_CLASS_HID_119db,
+ .class_hid = BNXT_ULP_CLASS_HID_2821d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -3823,7 +4431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[138] = {
- .class_hid = BNXT_ULP_CLASS_HID_14a93,
+ .class_hid = BNXT_ULP_CLASS_HID_28e37,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655368UL,
@@ -3842,7 +4450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[139] = {
- .class_hid = BNXT_ULP_CLASS_HID_105f7,
+ .class_hid = BNXT_ULP_CLASS_HID_28f7d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -3861,7 +4469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[140] = {
- .class_hid = BNXT_ULP_CLASS_HID_1368f,
+ .class_hid = BNXT_ULP_CLASS_HID_29b97,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655432UL,
@@ -3881,7 +4489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[141] = {
- .class_hid = BNXT_ULP_CLASS_HID_139c7,
+ .class_hid = BNXT_ULP_CLASS_HID_68491,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -3900,7 +4508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[142] = {
- .class_hid = BNXT_ULP_CLASS_HID_1022b,
+ .class_hid = BNXT_ULP_CLASS_HID_6908b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720904UL,
@@ -3920,7 +4528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[143] = {
- .class_hid = BNXT_ULP_CLASS_HID_125f3,
+ .class_hid = BNXT_ULP_CLASS_HID_691f1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -3940,7 +4548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[144] = {
- .class_hid = BNXT_ULP_CLASS_HID_1568b,
+ .class_hid = BNXT_ULP_CLASS_HID_69deb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720968UL,
@@ -3961,7 +4569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[145] = {
- .class_hid = BNXT_ULP_CLASS_HID_33c37,
+ .class_hid = BNXT_ULP_CLASS_HID_3926d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -3980,7 +4588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[146] = {
- .class_hid = BNXT_ULP_CLASS_HID_3041b,
+ .class_hid = BNXT_ULP_CLASS_HID_39e87,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917512UL,
@@ -4000,7 +4608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[147] = {
- .class_hid = BNXT_ULP_CLASS_HID_32823,
+ .class_hid = BNXT_ULP_CLASS_HID_38023,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -4020,7 +4628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[148] = {
- .class_hid = BNXT_ULP_CLASS_HID_358fb,
+ .class_hid = BNXT_ULP_CLASS_HID_38c45,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917576UL,
@@ -4041,7 +4649,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[149] = {
- .class_hid = BNXT_ULP_CLASS_HID_35c33,
+ .class_hid = BNXT_ULP_CLASS_HID_794e1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -4061,7 +4669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[150] = {
- .class_hid = BNXT_ULP_CLASS_HID_32407,
+ .class_hid = BNXT_ULP_CLASS_HID_78179,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983048UL,
@@ -4082,7 +4690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[151] = {
- .class_hid = BNXT_ULP_CLASS_HID_3482f,
+ .class_hid = BNXT_ULP_CLASS_HID_782a7,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -4103,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[152] = {
- .class_hid = BNXT_ULP_CLASS_HID_31033,
+ .class_hid = BNXT_ULP_CLASS_HID_78ed9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983112UL,
@@ -4125,7 +4733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[153] = {
- .class_hid = BNXT_ULP_CLASS_HID_3887,
+ .class_hid = BNXT_ULP_CLASS_HID_81d05,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -4142,7 +4750,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[154] = {
- .class_hid = BNXT_ULP_CLASS_HID_00bb,
+ .class_hid = BNXT_ULP_CLASS_HID_8098d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32776UL,
@@ -4160,7 +4768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[155] = {
- .class_hid = BNXT_ULP_CLASS_HID_2493,
+ .class_hid = BNXT_ULP_CLASS_HID_80ac3,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -4178,7 +4786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[156] = {
- .class_hid = BNXT_ULP_CLASS_HID_55db,
+ .class_hid = BNXT_ULP_CLASS_HID_8172d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32840UL,
@@ -4197,7 +4805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[157] = {
- .class_hid = BNXT_ULP_CLASS_HID_5043,
+ .class_hid = BNXT_ULP_CLASS_HID_80753,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -4215,7 +4823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[158] = {
- .class_hid = BNXT_ULP_CLASS_HID_1877,
+ .class_hid = BNXT_ULP_CLASS_HID_813bd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49160UL,
@@ -4234,7 +4842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[159] = {
- .class_hid = BNXT_ULP_CLASS_HID_3baf,
+ .class_hid = BNXT_ULP_CLASS_HID_814f3,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -4253,7 +4861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[160] = {
- .class_hid = BNXT_ULP_CLASS_HID_0443,
+ .class_hid = BNXT_ULP_CLASS_HID_8017b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49224UL,
@@ -4273,7 +4881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[161] = {
- .class_hid = BNXT_ULP_CLASS_HID_5883,
+ .class_hid = BNXT_ULP_CLASS_HID_c002f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -4291,7 +4899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[162] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b7,
+ .class_hid = BNXT_ULP_CLASS_HID_c0c09,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98312UL,
@@ -4310,7 +4918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[163] = {
- .class_hid = BNXT_ULP_CLASS_HID_44ef,
+ .class_hid = BNXT_ULP_CLASS_HID_c0d4f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -4329,7 +4937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[164] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c83,
+ .class_hid = BNXT_ULP_CLASS_HID_c19a9,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98376UL,
@@ -4349,7 +4957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[165] = {
- .class_hid = BNXT_ULP_CLASS_HID_070b,
+ .class_hid = BNXT_ULP_CLASS_HID_c09df,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -4368,7 +4976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[166] = {
- .class_hid = BNXT_ULP_CLASS_HID_3873,
+ .class_hid = BNXT_ULP_CLASS_HID_c1639,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114696UL,
@@ -4388,7 +4996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[167] = {
- .class_hid = BNXT_ULP_CLASS_HID_5bab,
+ .class_hid = BNXT_ULP_CLASS_HID_c177f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -4408,7 +5016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[168] = {
- .class_hid = BNXT_ULP_CLASS_HID_245f,
+ .class_hid = BNXT_ULP_CLASS_HID_c03e7,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114760UL,
@@ -4429,7 +5037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[169] = {
- .class_hid = BNXT_ULP_CLASS_HID_142b,
+ .class_hid = BNXT_ULP_CLASS_HID_a1e43,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -4447,7 +5055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[170] = {
- .class_hid = BNXT_ULP_CLASS_HID_4513,
+ .class_hid = BNXT_ULP_CLASS_HID_a0acb,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163848UL,
@@ -4466,7 +5074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[171] = {
- .class_hid = BNXT_ULP_CLASS_HID_0037,
+ .class_hid = BNXT_ULP_CLASS_HID_a0c01,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -4485,7 +5093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[172] = {
- .class_hid = BNXT_ULP_CLASS_HID_317f,
+ .class_hid = BNXT_ULP_CLASS_HID_a186b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163912UL,
@@ -4505,7 +5113,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[173] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be7,
+ .class_hid = BNXT_ULP_CLASS_HID_a0891,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -4524,7 +5132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[174] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c2f,
+ .class_hid = BNXT_ULP_CLASS_HID_a14fb,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180232UL,
@@ -4544,7 +5152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[175] = {
- .class_hid = BNXT_ULP_CLASS_HID_17f3,
+ .class_hid = BNXT_ULP_CLASS_HID_a1631,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -4564,7 +5172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[176] = {
- .class_hid = BNXT_ULP_CLASS_HID_483b,
+ .class_hid = BNXT_ULP_CLASS_HID_a02b9,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180296UL,
@@ -4585,7 +5193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[177] = {
- .class_hid = BNXT_ULP_CLASS_HID_3427,
+ .class_hid = BNXT_ULP_CLASS_HID_e016d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -4604,7 +5212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[178] = {
- .class_hid = BNXT_ULP_CLASS_HID_656f,
+ .class_hid = BNXT_ULP_CLASS_HID_e0d77,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229384UL,
@@ -4624,7 +5232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[179] = {
- .class_hid = BNXT_ULP_CLASS_HID_2033,
+ .class_hid = BNXT_ULP_CLASS_HID_e0e8d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -4644,7 +5252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[180] = {
- .class_hid = BNXT_ULP_CLASS_HID_517b,
+ .class_hid = BNXT_ULP_CLASS_HID_e1a97,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229448UL,
@@ -4665,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[181] = {
- .class_hid = BNXT_ULP_CLASS_HID_4be3,
+ .class_hid = BNXT_ULP_CLASS_HID_e0b1d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -4685,7 +5293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[182] = {
- .class_hid = BNXT_ULP_CLASS_HID_1397,
+ .class_hid = BNXT_ULP_CLASS_HID_e1767,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245768UL,
@@ -4706,7 +5314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[183] = {
- .class_hid = BNXT_ULP_CLASS_HID_37cf,
+ .class_hid = BNXT_ULP_CLASS_HID_e18bd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -4727,7 +5335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[184] = {
- .class_hid = BNXT_ULP_CLASS_HID_6837,
+ .class_hid = BNXT_ULP_CLASS_HID_e0525,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245832UL,
@@ -4749,7 +5357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[185] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d7f,
+ .class_hid = BNXT_ULP_CLASS_HID_21957,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -4766,7 +5374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[186] = {
- .class_hid = BNXT_ULP_CLASS_HID_0503,
+ .class_hid = BNXT_ULP_CLASS_HID_205cf,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131080UL,
@@ -4784,7 +5392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[187] = {
- .class_hid = BNXT_ULP_CLASS_HID_296b,
+ .class_hid = BNXT_ULP_CLASS_HID_20715,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -4802,7 +5410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[188] = {
- .class_hid = BNXT_ULP_CLASS_HID_59a3,
+ .class_hid = BNXT_ULP_CLASS_HID_2136f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131144UL,
@@ -4821,7 +5429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[189] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d7b,
+ .class_hid = BNXT_ULP_CLASS_HID_61bcb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -4839,7 +5447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[190] = {
- .class_hid = BNXT_ULP_CLASS_HID_250f,
+ .class_hid = BNXT_ULP_CLASS_HID_60843,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196616UL,
@@ -4858,7 +5466,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[191] = {
- .class_hid = BNXT_ULP_CLASS_HID_4957,
+ .class_hid = BNXT_ULP_CLASS_HID_60989,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -4877,7 +5485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[192] = {
- .class_hid = BNXT_ULP_CLASS_HID_117b,
+ .class_hid = BNXT_ULP_CLASS_HID_615e3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196680UL,
@@ -4897,7 +5505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[193] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f2b,
+ .class_hid = BNXT_ULP_CLASS_HID_30a65,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -4915,7 +5523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[194] = {
- .class_hid = BNXT_ULP_CLASS_HID_2273f,
+ .class_hid = BNXT_ULP_CLASS_HID_3167f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393224UL,
@@ -4934,7 +5542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[195] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b07,
+ .class_hid = BNXT_ULP_CLASS_HID_31785,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -4953,7 +5561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[196] = {
- .class_hid = BNXT_ULP_CLASS_HID_2132b,
+ .class_hid = BNXT_ULP_CLASS_HID_3043d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393288UL,
@@ -4973,7 +5581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[197] = {
- .class_hid = BNXT_ULP_CLASS_HID_216e3,
+ .class_hid = BNXT_ULP_CLASS_HID_70c99,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -4992,7 +5600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[198] = {
- .class_hid = BNXT_ULP_CLASS_HID_2473b,
+ .class_hid = BNXT_ULP_CLASS_HID_718f3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458760UL,
@@ -5012,7 +5620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[199] = {
- .class_hid = BNXT_ULP_CLASS_HID_202df,
+ .class_hid = BNXT_ULP_CLASS_HID_71a39,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -5032,7 +5640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[200] = {
- .class_hid = BNXT_ULP_CLASS_HID_23317,
+ .class_hid = BNXT_ULP_CLASS_HID_706b1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458824UL,
@@ -5053,7 +5661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[201] = {
- .class_hid = BNXT_ULP_CLASS_HID_119bb,
+ .class_hid = BNXT_ULP_CLASS_HID_2822d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -5071,7 +5679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[202] = {
- .class_hid = BNXT_ULP_CLASS_HID_14af3,
+ .class_hid = BNXT_ULP_CLASS_HID_28e07,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655368UL,
@@ -5090,7 +5698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[203] = {
- .class_hid = BNXT_ULP_CLASS_HID_10597,
+ .class_hid = BNXT_ULP_CLASS_HID_28f4d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -5109,7 +5717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[204] = {
- .class_hid = BNXT_ULP_CLASS_HID_136ef,
+ .class_hid = BNXT_ULP_CLASS_HID_29ba7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655432UL,
@@ -5129,7 +5737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[205] = {
- .class_hid = BNXT_ULP_CLASS_HID_139a7,
+ .class_hid = BNXT_ULP_CLASS_HID_684a1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -5148,7 +5756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[206] = {
- .class_hid = BNXT_ULP_CLASS_HID_1024b,
+ .class_hid = BNXT_ULP_CLASS_HID_690bb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720904UL,
@@ -5168,7 +5776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[207] = {
- .class_hid = BNXT_ULP_CLASS_HID_12593,
+ .class_hid = BNXT_ULP_CLASS_HID_691c1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -5188,7 +5796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[208] = {
- .class_hid = BNXT_ULP_CLASS_HID_156eb,
+ .class_hid = BNXT_ULP_CLASS_HID_69ddb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720968UL,
@@ -5209,7 +5817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[209] = {
- .class_hid = BNXT_ULP_CLASS_HID_33c57,
+ .class_hid = BNXT_ULP_CLASS_HID_3925d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -5228,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[210] = {
- .class_hid = BNXT_ULP_CLASS_HID_3047b,
+ .class_hid = BNXT_ULP_CLASS_HID_39eb7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917512UL,
@@ -5248,7 +5856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[211] = {
- .class_hid = BNXT_ULP_CLASS_HID_32843,
+ .class_hid = BNXT_ULP_CLASS_HID_38013,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -5268,7 +5876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[212] = {
- .class_hid = BNXT_ULP_CLASS_HID_3589b,
+ .class_hid = BNXT_ULP_CLASS_HID_38c75,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917576UL,
@@ -5289,7 +5897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[213] = {
- .class_hid = BNXT_ULP_CLASS_HID_35c53,
+ .class_hid = BNXT_ULP_CLASS_HID_794d1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -5309,7 +5917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[214] = {
- .class_hid = BNXT_ULP_CLASS_HID_32467,
+ .class_hid = BNXT_ULP_CLASS_HID_78149,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983048UL,
@@ -5330,7 +5938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[215] = {
- .class_hid = BNXT_ULP_CLASS_HID_3484f,
+ .class_hid = BNXT_ULP_CLASS_HID_78297,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -5351,7 +5959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[216] = {
- .class_hid = BNXT_ULP_CLASS_HID_31053,
+ .class_hid = BNXT_ULP_CLASS_HID_78ee9,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983112UL,
@@ -5373,7 +5981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[217] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ce1,
+ .class_hid = BNXT_ULP_CLASS_HID_0816,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -5387,7 +5995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[218] = {
- .class_hid = BNXT_ULP_CLASS_HID_4579,
+ .class_hid = BNXT_ULP_CLASS_HID_1852,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -5402,7 +6010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[219] = {
- .class_hid = BNXT_ULP_CLASS_HID_1735,
+ .class_hid = BNXT_ULP_CLASS_HID_09f4,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -5416,7 +6024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[220] = {
- .class_hid = BNXT_ULP_CLASS_HID_45bd,
+ .class_hid = BNXT_ULP_CLASS_HID_1dd4,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -5431,7 +6039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[221] = {
- .class_hid = BNXT_ULP_CLASS_HID_3feb,
+ .class_hid = BNXT_ULP_CLASS_HID_804f1,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -5446,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[222] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf7,
+ .class_hid = BNXT_ULP_CLASS_HID_81251,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -5462,7 +6070,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[223] = {
- .class_hid = BNXT_ULP_CLASS_HID_5727,
+ .class_hid = BNXT_ULP_CLASS_HID_80ee1,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -5478,7 +6086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[224] = {
- .class_hid = BNXT_ULP_CLASS_HID_4333,
+ .class_hid = BNXT_ULP_CLASS_HID_81c41,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -5495,7 +6103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[225] = {
- .class_hid = BNXT_ULP_CLASS_HID_4453,
+ .class_hid = BNXT_ULP_CLASS_HID_2013b,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -5510,7 +6118,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[226] = {
- .class_hid = BNXT_ULP_CLASS_HID_304f,
+ .class_hid = BNXT_ULP_CLASS_HID_20e9b,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -5526,7 +6134,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[227] = {
- .class_hid = BNXT_ULP_CLASS_HID_645f,
+ .class_hid = BNXT_ULP_CLASS_HID_603bf,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -5542,7 +6150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[228] = {
- .class_hid = BNXT_ULP_CLASS_HID_504b,
+ .class_hid = BNXT_ULP_CLASS_HID_6111f,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -5559,7 +6167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[229] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cc1,
+ .class_hid = BNXT_ULP_CLASS_HID_0806,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -5574,7 +6182,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[230] = {
- .class_hid = BNXT_ULP_CLASS_HID_4559,
+ .class_hid = BNXT_ULP_CLASS_HID_1842,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -5590,7 +6198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[231] = {
- .class_hid = BNXT_ULP_CLASS_HID_2285,
+ .class_hid = BNXT_ULP_CLASS_HID_1be6,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -5606,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[232] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b1d,
+ .class_hid = BNXT_ULP_CLASS_HID_0c80,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -5623,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[233] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b49,
+ .class_hid = BNXT_ULP_CLASS_HID_1216,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -5639,7 +6247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[234] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c95,
+ .class_hid = BNXT_ULP_CLASS_HID_02b0,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -5656,7 +6264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[235] = {
- .class_hid = BNXT_ULP_CLASS_HID_39c1,
+ .class_hid = BNXT_ULP_CLASS_HID_0654,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -5673,7 +6281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[236] = {
- .class_hid = BNXT_ULP_CLASS_HID_2259,
+ .class_hid = BNXT_ULP_CLASS_HID_1690,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -5691,7 +6299,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[237] = {
- .class_hid = BNXT_ULP_CLASS_HID_1715,
+ .class_hid = BNXT_ULP_CLASS_HID_09e4,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -5706,7 +6314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[238] = {
- .class_hid = BNXT_ULP_CLASS_HID_459d,
+ .class_hid = BNXT_ULP_CLASS_HID_1dc4,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -5722,7 +6330,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[239] = {
- .class_hid = BNXT_ULP_CLASS_HID_571d,
+ .class_hid = BNXT_ULP_CLASS_HID_80efc,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -5738,7 +6346,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[240] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cd1,
+ .class_hid = BNXT_ULP_CLASS_HID_80332,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -5755,7 +6363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[241] = {
- .class_hid = BNXT_ULP_CLASS_HID_3711,
+ .class_hid = BNXT_ULP_CLASS_HID_40c78,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -5771,7 +6379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[242] = {
- .class_hid = BNXT_ULP_CLASS_HID_6599,
+ .class_hid = BNXT_ULP_CLASS_HID_400be,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -5788,7 +6396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[243] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e55,
+ .class_hid = BNXT_ULP_CLASS_HID_c1170,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -5805,7 +6413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[244] = {
- .class_hid = BNXT_ULP_CLASS_HID_3cdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c05b6,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -5823,7 +6431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[245] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ca1,
+ .class_hid = BNXT_ULP_CLASS_HID_0836,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -5838,7 +6446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[246] = {
- .class_hid = BNXT_ULP_CLASS_HID_4539,
+ .class_hid = BNXT_ULP_CLASS_HID_1872,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -5854,7 +6462,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[247] = {
- .class_hid = BNXT_ULP_CLASS_HID_22e5,
+ .class_hid = BNXT_ULP_CLASS_HID_1bd6,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -5870,7 +6478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[248] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_0cb0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -5887,7 +6495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[249] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b29,
+ .class_hid = BNXT_ULP_CLASS_HID_1226,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -5903,7 +6511,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[250] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cf5,
+ .class_hid = BNXT_ULP_CLASS_HID_0280,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -5920,7 +6528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[251] = {
- .class_hid = BNXT_ULP_CLASS_HID_39a1,
+ .class_hid = BNXT_ULP_CLASS_HID_0664,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -5937,7 +6545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[252] = {
- .class_hid = BNXT_ULP_CLASS_HID_2239,
+ .class_hid = BNXT_ULP_CLASS_HID_16a0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -5955,7 +6563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[253] = {
- .class_hid = BNXT_ULP_CLASS_HID_1775,
+ .class_hid = BNXT_ULP_CLASS_HID_09d4,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -5970,7 +6578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[254] = {
- .class_hid = BNXT_ULP_CLASS_HID_45fd,
+ .class_hid = BNXT_ULP_CLASS_HID_1df4,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -5986,7 +6594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[255] = {
- .class_hid = BNXT_ULP_CLASS_HID_577d,
+ .class_hid = BNXT_ULP_CLASS_HID_80ecc,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -6002,7 +6610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[256] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cb1,
+ .class_hid = BNXT_ULP_CLASS_HID_80302,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -6019,7 +6627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[257] = {
- .class_hid = BNXT_ULP_CLASS_HID_3771,
+ .class_hid = BNXT_ULP_CLASS_HID_40c48,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -6035,7 +6643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[258] = {
- .class_hid = BNXT_ULP_CLASS_HID_65f9,
+ .class_hid = BNXT_ULP_CLASS_HID_4008e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -6052,7 +6660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[259] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e35,
+ .class_hid = BNXT_ULP_CLASS_HID_c1140,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -6069,7 +6677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[260] = {
- .class_hid = BNXT_ULP_CLASS_HID_3cbd,
+ .class_hid = BNXT_ULP_CLASS_HID_c0586,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -6087,7 +6695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[261] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fcb,
+ .class_hid = BNXT_ULP_CLASS_HID_804e1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -6103,7 +6711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[262] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bd7,
+ .class_hid = BNXT_ULP_CLASS_HID_81241,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -6120,7 +6728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[263] = {
- .class_hid = BNXT_ULP_CLASS_HID_5707,
+ .class_hid = BNXT_ULP_CLASS_HID_80ef1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -6137,7 +6745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[264] = {
- .class_hid = BNXT_ULP_CLASS_HID_4313,
+ .class_hid = BNXT_ULP_CLASS_HID_81c51,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -6155,7 +6763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[265] = {
- .class_hid = BNXT_ULP_CLASS_HID_5fc7,
+ .class_hid = BNXT_ULP_CLASS_HID_c076d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -6172,7 +6780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[266] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bd3,
+ .class_hid = BNXT_ULP_CLASS_HID_c14cd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -6190,7 +6798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[267] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e4f,
+ .class_hid = BNXT_ULP_CLASS_HID_c117d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -6208,7 +6816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[268] = {
- .class_hid = BNXT_ULP_CLASS_HID_632f,
+ .class_hid = BNXT_ULP_CLASS_HID_c1edd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -6227,7 +6835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[269] = {
- .class_hid = BNXT_ULP_CLASS_HID_1baf,
+ .class_hid = BNXT_ULP_CLASS_HID_a062f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -6244,7 +6852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[270] = {
- .class_hid = BNXT_ULP_CLASS_HID_07bb,
+ .class_hid = BNXT_ULP_CLASS_HID_a138f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -6262,7 +6870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[271] = {
- .class_hid = BNXT_ULP_CLASS_HID_32eb,
+ .class_hid = BNXT_ULP_CLASS_HID_a103f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -6280,7 +6888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[272] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ef7,
+ .class_hid = BNXT_ULP_CLASS_HID_a1d9f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -6299,7 +6907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[273] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bab,
+ .class_hid = BNXT_ULP_CLASS_HID_e08ab,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -6317,7 +6925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[274] = {
- .class_hid = BNXT_ULP_CLASS_HID_27b7,
+ .class_hid = BNXT_ULP_CLASS_HID_e160b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -6336,7 +6944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[275] = {
- .class_hid = BNXT_ULP_CLASS_HID_52e7,
+ .class_hid = BNXT_ULP_CLASS_HID_e12bb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -6355,7 +6963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[276] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ef3,
+ .class_hid = BNXT_ULP_CLASS_HID_e0079,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -6375,7 +6983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[277] = {
- .class_hid = BNXT_ULP_CLASS_HID_4473,
+ .class_hid = BNXT_ULP_CLASS_HID_2012b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -6391,7 +6999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[278] = {
- .class_hid = BNXT_ULP_CLASS_HID_306f,
+ .class_hid = BNXT_ULP_CLASS_HID_20e8b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -6408,7 +7016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[279] = {
- .class_hid = BNXT_ULP_CLASS_HID_647f,
+ .class_hid = BNXT_ULP_CLASS_HID_603af,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -6425,7 +7033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[280] = {
- .class_hid = BNXT_ULP_CLASS_HID_506b,
+ .class_hid = BNXT_ULP_CLASS_HID_6110f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -6443,7 +7051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[281] = {
- .class_hid = BNXT_ULP_CLASS_HID_266af,
+ .class_hid = BNXT_ULP_CLASS_HID_311bb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -6460,7 +7068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[282] = {
- .class_hid = BNXT_ULP_CLASS_HID_2525b,
+ .class_hid = BNXT_ULP_CLASS_HID_31f1b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -6478,7 +7086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[283] = {
- .class_hid = BNXT_ULP_CLASS_HID_21de7,
+ .class_hid = BNXT_ULP_CLASS_HID_7143f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -6496,7 +7104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[284] = {
- .class_hid = BNXT_ULP_CLASS_HID_20993,
+ .class_hid = BNXT_ULP_CLASS_HID_701fd,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -6515,7 +7123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[285] = {
- .class_hid = BNXT_ULP_CLASS_HID_1213f,
+ .class_hid = BNXT_ULP_CLASS_HID_28963,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -6532,7 +7140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[286] = {
- .class_hid = BNXT_ULP_CLASS_HID_10d2b,
+ .class_hid = BNXT_ULP_CLASS_HID_296c3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -6550,7 +7158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[287] = {
- .class_hid = BNXT_ULP_CLASS_HID_1413b,
+ .class_hid = BNXT_ULP_CLASS_HID_68be7,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -6568,7 +7176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[288] = {
- .class_hid = BNXT_ULP_CLASS_HID_12cd7,
+ .class_hid = BNXT_ULP_CLASS_HID_69947,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -6587,7 +7195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[289] = {
- .class_hid = BNXT_ULP_CLASS_HID_3436b,
+ .class_hid = BNXT_ULP_CLASS_HID_399f3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -6605,7 +7213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[290] = {
- .class_hid = BNXT_ULP_CLASS_HID_32f07,
+ .class_hid = BNXT_ULP_CLASS_HID_387b1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -6624,7 +7232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[291] = {
- .class_hid = BNXT_ULP_CLASS_HID_36317,
+ .class_hid = BNXT_ULP_CLASS_HID_79c77,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -6643,7 +7251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[292] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f03,
+ .class_hid = BNXT_ULP_CLASS_HID_78a35,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -6663,7 +7271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[293] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fab,
+ .class_hid = BNXT_ULP_CLASS_HID_804d1,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -6679,7 +7287,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[294] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bb7,
+ .class_hid = BNXT_ULP_CLASS_HID_81271,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -6696,7 +7304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[295] = {
- .class_hid = BNXT_ULP_CLASS_HID_5767,
+ .class_hid = BNXT_ULP_CLASS_HID_80ec1,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -6713,7 +7321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[296] = {
- .class_hid = BNXT_ULP_CLASS_HID_4373,
+ .class_hid = BNXT_ULP_CLASS_HID_81c61,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -6731,7 +7339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[297] = {
- .class_hid = BNXT_ULP_CLASS_HID_5fa7,
+ .class_hid = BNXT_ULP_CLASS_HID_c075d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -6748,7 +7356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[298] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bb3,
+ .class_hid = BNXT_ULP_CLASS_HID_c14fd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -6766,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[299] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e2f,
+ .class_hid = BNXT_ULP_CLASS_HID_c114d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -6784,7 +7392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[300] = {
- .class_hid = BNXT_ULP_CLASS_HID_634f,
+ .class_hid = BNXT_ULP_CLASS_HID_c1eed,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -6803,7 +7411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[301] = {
- .class_hid = BNXT_ULP_CLASS_HID_1bcf,
+ .class_hid = BNXT_ULP_CLASS_HID_a061f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -6820,7 +7428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[302] = {
- .class_hid = BNXT_ULP_CLASS_HID_07db,
+ .class_hid = BNXT_ULP_CLASS_HID_a13bf,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -6838,7 +7446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[303] = {
- .class_hid = BNXT_ULP_CLASS_HID_328b,
+ .class_hid = BNXT_ULP_CLASS_HID_a100f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -6856,7 +7464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[304] = {
- .class_hid = BNXT_ULP_CLASS_HID_1e97,
+ .class_hid = BNXT_ULP_CLASS_HID_a1daf,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -6875,7 +7483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[305] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bcb,
+ .class_hid = BNXT_ULP_CLASS_HID_e089b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -6893,7 +7501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[306] = {
- .class_hid = BNXT_ULP_CLASS_HID_27d7,
+ .class_hid = BNXT_ULP_CLASS_HID_e163b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -6912,7 +7520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[307] = {
- .class_hid = BNXT_ULP_CLASS_HID_5287,
+ .class_hid = BNXT_ULP_CLASS_HID_e128b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -6931,7 +7539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[308] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e93,
+ .class_hid = BNXT_ULP_CLASS_HID_e0049,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -6951,7 +7559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[309] = {
- .class_hid = BNXT_ULP_CLASS_HID_4413,
+ .class_hid = BNXT_ULP_CLASS_HID_2011b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -6967,7 +7575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[310] = {
- .class_hid = BNXT_ULP_CLASS_HID_300f,
+ .class_hid = BNXT_ULP_CLASS_HID_20ebb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -6984,7 +7592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[311] = {
- .class_hid = BNXT_ULP_CLASS_HID_641f,
+ .class_hid = BNXT_ULP_CLASS_HID_6039f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -7001,7 +7609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[312] = {
- .class_hid = BNXT_ULP_CLASS_HID_500b,
+ .class_hid = BNXT_ULP_CLASS_HID_6113f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -7019,7 +7627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[313] = {
- .class_hid = BNXT_ULP_CLASS_HID_266cf,
+ .class_hid = BNXT_ULP_CLASS_HID_3118b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -7036,7 +7644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[314] = {
- .class_hid = BNXT_ULP_CLASS_HID_2523b,
+ .class_hid = BNXT_ULP_CLASS_HID_31f2b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -7054,7 +7662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[315] = {
- .class_hid = BNXT_ULP_CLASS_HID_21d87,
+ .class_hid = BNXT_ULP_CLASS_HID_7140f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -7072,7 +7680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[316] = {
- .class_hid = BNXT_ULP_CLASS_HID_209f3,
+ .class_hid = BNXT_ULP_CLASS_HID_701cd,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -7091,7 +7699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[317] = {
- .class_hid = BNXT_ULP_CLASS_HID_1215f,
+ .class_hid = BNXT_ULP_CLASS_HID_28953,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -7108,7 +7716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[318] = {
- .class_hid = BNXT_ULP_CLASS_HID_10d4b,
+ .class_hid = BNXT_ULP_CLASS_HID_296f3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -7126,7 +7734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[319] = {
- .class_hid = BNXT_ULP_CLASS_HID_1415b,
+ .class_hid = BNXT_ULP_CLASS_HID_68bd7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -7144,7 +7752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[320] = {
- .class_hid = BNXT_ULP_CLASS_HID_12cb7,
+ .class_hid = BNXT_ULP_CLASS_HID_69977,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -7163,7 +7771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[321] = {
- .class_hid = BNXT_ULP_CLASS_HID_3430b,
+ .class_hid = BNXT_ULP_CLASS_HID_399c3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -7181,7 +7789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[322] = {
- .class_hid = BNXT_ULP_CLASS_HID_32f67,
+ .class_hid = BNXT_ULP_CLASS_HID_38781,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -7200,7 +7808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[323] = {
- .class_hid = BNXT_ULP_CLASS_HID_36377,
+ .class_hid = BNXT_ULP_CLASS_HID_79c47,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -7219,7 +7827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[324] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f63,
+ .class_hid = BNXT_ULP_CLASS_HID_78a05,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -7239,7 +7847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[325] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b5,
+ .class_hid = BNXT_ULP_CLASS_HID_04a4,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 8UL,
@@ -7254,7 +7862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC }
},
[326] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ad,
+ .class_hid = BNXT_ULP_CLASS_HID_04a8,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 8UL,
@@ -7269,7 +7877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC }
},
[327] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b7,
+ .class_hid = BNXT_ULP_CLASS_HID_04a5,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 8UL,
@@ -7285,7 +7893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC }
},
[328] = {
- .class_hid = BNXT_ULP_CLASS_HID_1583,
+ .class_hid = BNXT_ULP_CLASS_HID_1205,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 72UL,
@@ -7302,7 +7910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID }
},
[329] = {
- .class_hid = BNXT_ULP_CLASS_HID_29af,
+ .class_hid = BNXT_ULP_CLASS_HID_04a9,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 8UL,
@@ -7318,7 +7926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC }
},
[330] = {
- .class_hid = BNXT_ULP_CLASS_HID_159b,
+ .class_hid = BNXT_ULP_CLASS_HID_1209,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 72UL,
@@ -7335,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID }
},
[331] = {
- .class_hid = BNXT_ULP_CLASS_HID_2995,
+ .class_hid = BNXT_ULP_CLASS_HID_04b4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 8UL,
@@ -7351,7 +7959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC }
},
[332] = {
- .class_hid = BNXT_ULP_CLASS_HID_298d,
+ .class_hid = BNXT_ULP_CLASS_HID_04b8,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 8UL,
@@ -7367,7 +7975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC }
},
[333] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f5,
+ .class_hid = BNXT_ULP_CLASS_HID_0484,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 8UL,
@@ -7383,7 +7991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC }
},
[334] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ed,
+ .class_hid = BNXT_ULP_CLASS_HID_0488,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 8UL,
@@ -7399,7 +8007,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC }
},
[335] = {
- .class_hid = BNXT_ULP_CLASS_HID_2997,
+ .class_hid = BNXT_ULP_CLASS_HID_04b5,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 8UL,
@@ -7416,7 +8024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC }
},
[336] = {
- .class_hid = BNXT_ULP_CLASS_HID_15a3,
+ .class_hid = BNXT_ULP_CLASS_HID_1215,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 72UL,
@@ -7434,7 +8042,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID }
},
[337] = {
- .class_hid = BNXT_ULP_CLASS_HID_298f,
+ .class_hid = BNXT_ULP_CLASS_HID_04b9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 8UL,
@@ -7451,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC }
},
[338] = {
- .class_hid = BNXT_ULP_CLASS_HID_15bb,
+ .class_hid = BNXT_ULP_CLASS_HID_1219,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 72UL,
@@ -7469,7 +8077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID }
},
[339] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f7,
+ .class_hid = BNXT_ULP_CLASS_HID_0485,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 8UL,
@@ -7486,7 +8094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC }
},
[340] = {
- .class_hid = BNXT_ULP_CLASS_HID_15c3,
+ .class_hid = BNXT_ULP_CLASS_HID_1225,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 72UL,
@@ -7504,7 +8112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID }
},
[341] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ef,
+ .class_hid = BNXT_ULP_CLASS_HID_0489,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 8UL,
@@ -7521,7 +8129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC }
},
[342] = {
- .class_hid = BNXT_ULP_CLASS_HID_15db,
+ .class_hid = BNXT_ULP_CLASS_HID_1229,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 72UL,
@@ -7539,7 +8147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID }
},
[343] = {
- .class_hid = BNXT_ULP_CLASS_HID_1151,
+ .class_hid = BNXT_ULP_CLASS_HID_0226,
.class_tid = 1,
.hdr_sig_id = 12,
.flow_sig_id = 16384UL,
@@ -7556,7 +8164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR }
},
[344] = {
- .class_hid = BNXT_ULP_CLASS_HID_315d,
+ .class_hid = BNXT_ULP_CLASS_HID_4045a,
.class_tid = 1,
.hdr_sig_id = 12,
.flow_sig_id = 81920UL,
@@ -7574,776 +8182,776 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_hid = BNXT_ULP_CLASS_HID_0daa,
.class_tid = 2,
.hdr_sig_id = 0,
- .flow_sig_id = 81920UL,
+ .flow_sig_id = 20480UL,
.flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_F1 |
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[346] = {
- .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_hid = BNXT_ULP_CLASS_HID_11b0,
.class_tid = 2,
.hdr_sig_id = 0,
- .flow_sig_id = 81928UL,
+ .flow_sig_id = 20488UL,
.flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_F1 |
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_243ca,
+ .class_hid = BNXT_ULP_CLASS_HID_403f8,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 265216UL,
- .flow_pattern_id = 1,
+ .flow_sig_id = 81920UL,
+ .flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d8e,
+ .class_hid = BNXT_ULP_CLASS_HID_4161e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 273408UL,
- .flow_pattern_id = 1,
+ .flow_sig_id = 81928UL,
+ .flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e082,
+ .class_hid = BNXT_ULP_CLASS_HID_40439,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ab46,
+ .class_hid = BNXT_ULP_CLASS_HID_41405,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_25226,
+ .class_hid = BNXT_ULP_CLASS_HID_51449,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_25cea,
+ .class_hid = BNXT_ULP_CLASS_HID_50b33,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 330496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c82a,
+ .class_hid = BNXT_ULP_CLASS_HID_48c01,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 590592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f9a2,
+ .class_hid = BNXT_ULP_CLASS_HID_483eb,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 592640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b56,
+ .class_hid = BNXT_ULP_CLASS_HID_5833f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 852736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_205da,
+ .class_hid = BNXT_ULP_CLASS_HID_5937b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 854784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d8ce,
+ .class_hid = BNXT_ULP_CLASS_HID_41875,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134284032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a2d2,
+ .class_hid = BNXT_ULP_CLASS_HID_40f5f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134286080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a72,
+ .class_hid = BNXT_ULP_CLASS_HID_50f23,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134546176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_25476,
+ .class_hid = BNXT_ULP_CLASS_HID_51f6f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134548224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c076,
+ .class_hid = BNXT_ULP_CLASS_HID_4875b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134808320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f1ee,
+ .class_hid = BNXT_ULP_CLASS_HID_49727,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134810368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_20bb6,
+ .class_hid = BNXT_ULP_CLASS_HID_5976b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 135070464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_23d2e,
+ .class_hid = BNXT_ULP_CLASS_HID_58655,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 135072512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a96e,
+ .class_hid = BNXT_ULP_CLASS_HID_4125f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268501760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dae6,
+ .class_hid = BNXT_ULP_CLASS_HID_401f9,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268503808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_25af2,
+ .class_hid = BNXT_ULP_CLASS_HID_501cd,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268763904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c6a,
+ .class_hid = BNXT_ULP_CLASS_HID_51149,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268765952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c7aa,
+ .class_hid = BNXT_ULP_CLASS_HID_49a67,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269026048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c26e,
+ .class_hid = BNXT_ULP_CLASS_HID_489c1,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269028096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_203e2,
+ .class_hid = BNXT_ULP_CLASS_HID_58955,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269288192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_2357a,
+ .class_hid = BNXT_ULP_CLASS_HID_59951,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269290240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a0fa,
+ .class_hid = BNXT_ULP_CLASS_HID_40569,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402719488UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d272,
+ .class_hid = BNXT_ULP_CLASS_HID_41575,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402721536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2527e,
+ .class_hid = BNXT_ULP_CLASS_HID_51579,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402981632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_243f6,
+ .class_hid = BNXT_ULP_CLASS_HID_50463,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402983680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fff6,
+ .class_hid = BNXT_ULP_CLASS_HID_48d71,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 403243776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e16e,
+ .class_hid = BNXT_ULP_CLASS_HID_49d7d,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 403245824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422d,
+ .class_hid = BNXT_ULP_CLASS_HID_59d41,
.class_tid = 2,
.hdr_sig_id = 2,
- .flow_sig_id = 265216UL,
+ .flow_sig_id = 403505920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c69,
+ .class_hid = BNXT_ULP_CLASS_HID_58c6b,
.class_tid = 2,
.hdr_sig_id = 2,
- .flow_sig_id = 273408UL,
+ .flow_sig_id = 403507968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e165,
+ .class_hid = BNXT_ULP_CLASS_HID_10255,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8351,19 +8959,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aaa1,
+ .class_hid = BNXT_ULP_CLASS_HID_11675,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8371,20 +8978,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_253c1,
+ .class_hid = BNXT_ULP_CLASS_HID_14649,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8392,19 +8998,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d0d,
+ .class_hid = BNXT_ULP_CLASS_HID_15a69,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8412,20 +9018,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c9cd,
+ .class_hid = BNXT_ULP_CLASS_HID_1205b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8433,20 +9039,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f845,
+ .class_hid = BNXT_ULP_CLASS_HID_1347b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8454,21 +9059,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_25afd,
+ .class_hid = BNXT_ULP_CLASS_HID_16bbf,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8476,19 +9080,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_22439,
+ .class_hid = BNXT_ULP_CLASS_HID_1785f,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8496,20 +9101,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_290f9,
+ .class_hid = BNXT_ULP_CLASS_HID_11551,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 537136128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8517,20 +9123,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c371,
+ .class_hid = BNXT_ULP_CLASS_HID_10897,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 537144320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8538,21 +9143,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_24355,
+ .class_hid = BNXT_ULP_CLASS_HID_15955,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8560,20 +9164,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_275dd,
+ .class_hid = BNXT_ULP_CLASS_HID_14c8b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8581,21 +9185,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e19d,
+ .class_hid = BNXT_ULP_CLASS_HID_13b47,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 539233280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8603,21 +9207,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d015,
+ .class_hid = BNXT_ULP_CLASS_HID_12e85,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 539241472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8625,22 +9228,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_2560d,
+ .class_hid = BNXT_ULP_CLASS_HID_17f5b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8648,19 +9250,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_21049,
+ .class_hid = BNXT_ULP_CLASS_HID_17299,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8668,20 +9272,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_28c09,
+ .class_hid = BNXT_ULP_CLASS_HID_10fe7,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1074007040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8689,20 +9295,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be89,
+ .class_hid = BNXT_ULP_CLASS_HID_10325,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1074015232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8710,21 +9315,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_267a9,
+ .class_hid = BNXT_ULP_CLASS_HID_153cb,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8732,20 +9336,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_261ed,
+ .class_hid = BNXT_ULP_CLASS_HID_14709,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8753,21 +9357,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ddad,
+ .class_hid = BNXT_ULP_CLASS_HID_12dc5,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1076104192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8775,21 +9379,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc2d,
+ .class_hid = BNXT_ULP_CLASS_HID_1212b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1076112384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8797,22 +9400,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_26edd,
+ .class_hid = BNXT_ULP_CLASS_HID_171c9,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8820,20 +9422,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_22819,
+ .class_hid = BNXT_ULP_CLASS_HID_1650f,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8841,21 +9444,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a4d9,
+ .class_hid = BNXT_ULP_CLASS_HID_10201,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1610877952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8863,21 +9467,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d759,
+ .class_hid = BNXT_ULP_CLASS_HID_116c1,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1610886144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8885,22 +9488,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2573d,
+ .class_hid = BNXT_ULP_CLASS_HID_14605,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8908,21 +9510,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_279bd,
+ .class_hid = BNXT_ULP_CLASS_HID_15a05,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8930,22 +9532,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f27d,
+ .class_hid = BNXT_ULP_CLASS_HID_12007,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1612975104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8953,22 +9555,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e4fd,
+ .class_hid = BNXT_ULP_CLASS_HID_13407,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1612983296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8976,23 +9577,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[411] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fbe,
+ .class_hid = BNXT_ULP_CLASS_HID_1640b,
.class_tid = 2,
.hdr_sig_id = 3,
- .flow_sig_id = 265216UL,
+ .flow_sig_id = 1614023680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9001,18 +9601,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_201fa,
+ .class_hid = BNXT_ULP_CLASS_HID_1780b,
.class_tid = 2,
.hdr_sig_id = 3,
- .flow_sig_id = 273408UL,
+ .flow_sig_id = 1614031872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9021,2202 +9624,16438 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ecf6,
+ .class_hid = BNXT_ULP_CLASS_HID_404b0,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a732,
+ .class_hid = BNXT_ULP_CLASS_HID_4148c,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e52,
+ .class_hid = BNXT_ULP_CLASS_HID_514c0,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50bba,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c88,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48362,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_583b6,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_593f2,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41f54,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40fce,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50e02,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51e5e,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487ca,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49606,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5965a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58514,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412c2,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_401ac,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_501e0,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_511cc,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4990a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_489e4,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_589c8,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59804,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40404,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41440,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51484,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b0e,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c4c,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48306,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5830a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59346,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102cc,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116ec,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_146d0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15af0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_120c2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134e2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16b26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_178c6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115c6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10804,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15822,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c60,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13bd4,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12e12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e30,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17276,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f1a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11358,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14398,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_157b8,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d68,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_131aa,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_175b2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_112b2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_106f0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15692,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ad0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13080,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_124c2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174e0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4025b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41267,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5122b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d51,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48a63,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48589,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5855d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59519,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e17,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134284032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4093d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134286080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50941,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134546176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5190d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134548224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48139,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134808320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49145,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134810368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59109,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 135070464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58037,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 135072512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4143d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268501760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4079b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268503808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507af,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268763904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268765952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c05,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269026048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fa3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269028096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f37,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269288192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f33,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269290240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4030b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402719488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41317,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402721536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5131b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402981632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50201,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402983680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b13,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403243776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49b1f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403245824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403505920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a09,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403507968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419bf,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508e9,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518b5,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_490ed,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590b1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_583ff,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41475,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671154944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40473,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671156992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50427,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671417088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51763,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c3d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671679232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c3b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671681280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f6f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671941376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671943424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40333,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805372672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412bf,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805374720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512a3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805634816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50229,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805636864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48abb,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805896960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49aa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805899008UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59a2b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 806159104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595b1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 806161152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e2f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939590400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40e35,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939592448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50939,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939852544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939854592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48631,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940114688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4913d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940116736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940376832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5812f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940378880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41429,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40747,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5070b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51727,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49fe1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59eef,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40347,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208025856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41303,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208027904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51247,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208288000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5026d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208290048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208550144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a4b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208552192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59a0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208812288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a05,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208814336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41983,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342243584UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40929,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342245632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5092d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342505728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518a9,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342507776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48125,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342767872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342769920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59085,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1343030016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58023,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1343032064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41509,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476461312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40407,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476463360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5040b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476723456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51407,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476725504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d21,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476985600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476987648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c03,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1477247744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1477249792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402ef,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412ab,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5126f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50de5,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_485ed,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585e1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595ad,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e6b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1744896768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40961,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1744898816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745158912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51961,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745160960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4816d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745421056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49129,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745423104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5916d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745683200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5806b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745685248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414a1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879114496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4042f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879116544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507a3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879376640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517af,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879378688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c29,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879638784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879640832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58fab,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879900928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879902976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4032f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013332224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4132b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013334272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5132f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013594368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50225,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013596416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013856512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49b23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013858560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2014118656UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a2d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2014120704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10437,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ },
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11017,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ },
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1402b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ },
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c0b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ },
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12639,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13219,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ddd,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e3d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11333,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 537136128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10ef5,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 537144320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f37,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 538184704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ae9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 538192896UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d25,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 539233280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128e7,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 539241472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17939,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 540281856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174fb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 540290048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10985,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1074007040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10547,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1074015232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_155a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1075055616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1416b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1075063808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ba7,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1076104192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12749,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1076112384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_177ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1077152768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1636d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1077160960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10463,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1610877952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_110a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1610886144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14067,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1611926528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c67,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1611934720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12665,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1612975104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13265,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1612983296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16269,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1614023680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1614031872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1133d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10eff,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ed9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a9b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d2f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128e9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_178cb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1748d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_109fb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2684619776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_105bd,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2684627968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_155bf,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2685668352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14179,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2685676544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12bed,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2686716928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_127af,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2686725120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [651] = {
+ .class_hid = BNXT_ULP_CLASS_HID_177a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2687765504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [652] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1636b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2687773696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [653] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1046d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3221490688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [654] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1104d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3221498880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [655] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14009,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3222539264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [656] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3222547456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [657] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1260f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3223587840UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [658] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1326f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3223596032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [659] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1622b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3224636416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [660] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e0b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3224644608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [661] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11369,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3758361600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [662] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3758369792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [663] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3759410176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [664] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14b2f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3759418368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [665] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d6b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3760458752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [666] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1292d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3760466944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [667] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1792f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3761507328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [668] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174e9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3761515520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [669] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119e1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [670] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [671] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14563,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [672] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15143,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [673] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b93,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [674] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13751,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [675] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16769,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [676] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17349,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [677] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4832103424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [678] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10061,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4832111616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [679] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15063,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4833152000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [680] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c21,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4833160192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [681] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13671,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4834200576UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [682] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12233,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4834208768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [683] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17271,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4835249152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [684] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e33,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4835257344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [685] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102c1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5368974336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [686] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f21,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5368982528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [687] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ee1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5370022912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [688] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ac1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5370031104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [689] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12cc3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5371071488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [690] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13923,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5371079680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [691] = {
+ .class_hid = BNXT_ULP_CLASS_HID_168e3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5372120064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [692] = {
+ .class_hid = BNXT_ULP_CLASS_HID_164a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5372128256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [693] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e29,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5905845248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [694] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115eb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5905853440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [695] = {
+ .class_hid = BNXT_ULP_CLASS_HID_145a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5906893824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [696] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5906902016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [697] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1382b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5907942400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [698] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137e1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5907950592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [699] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167a1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5908990976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [700] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173a1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5908999168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [701] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11449,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [702] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1000b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [703] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15069,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [704] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [705] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1367b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [706] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12239,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [707] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1721b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [708] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169d9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [709] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1033b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6979587072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [710] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f3b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6979595264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [711] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6980635648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [712] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15b2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6980643840UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [713] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d39,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6981684224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [714] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13939,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6981692416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [715] = {
+ .class_hid = BNXT_ULP_CLASS_HID_168f9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6982732800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [716] = {
+ .class_hid = BNXT_ULP_CLASS_HID_164bb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6982740992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [717] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119cb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7516457984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [718] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11589,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7516466176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [719] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14549,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7517506560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [720] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7517514752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [721] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13bc9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7518555136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [722] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1378b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7518563328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [723] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1674b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7519603712UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [724] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7519611904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [725] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8053328896UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [726] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1006b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8053337088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [727] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8054377472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [728] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c6b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8054385664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [729] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8055426048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [730] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12269,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8055434240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [731] = {
+ .class_hid = BNXT_ULP_CLASS_HID_172ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8056474624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [732] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8056482816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [733] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402d2,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI }
+ },
+ [734] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI }
+ },
+ [735] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512a2,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC }
+ },
+ [736] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50dd8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC }
+ },
+ [737] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aea,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [738] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48500,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [739] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585d4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [740] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59590,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [741] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41936,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [742] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [743] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50860,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [744] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5183c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [745] = {
+ .class_hid = BNXT_ULP_CLASS_HID_481a8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [746] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49064,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [747] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59038,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [748] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58376,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [749] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414a0,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [750] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [751] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50782,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [752] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [753] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f68,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [754] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f86,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [755] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58faa,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [756] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59e66,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [757] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40266,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [758] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41222,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [759] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512e6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [760] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [761] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48a2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [762] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48564,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [763] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58568,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [764] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59524,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [765] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419d8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147549952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [766] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4087e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147552000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [767] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5080a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147812096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [768] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147814144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [769] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4807a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148074240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [770] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4900e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148076288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [771] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590ca,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148336384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [772] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58378,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148338432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [773] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414be,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684420864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [774] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4073c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684422912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [775] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507e8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684683008UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [776] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684685056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [777] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f7e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684945152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [778] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684947200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [779] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58fa8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2685207296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [780] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59e7c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2685209344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [781] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40208,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221291776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [782] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412cc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221293824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [783] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51288,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221553920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [784] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221555968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [785] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48ac8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221816064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [786] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4856e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221818112UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [787] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5852a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3222078208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [788] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3222080256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [789] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4196c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758162688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [790] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409aa,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758164736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [791] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5086e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758424832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [792] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5182a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758426880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [793] = {
+ .class_hid = BNXT_ULP_CLASS_HID_481ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758686976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [794] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4906a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758689024UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [795] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5902e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758949120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [796] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758951168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [797] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40766,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295033600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [798] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41726,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295035648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [799] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517f6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295295744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [800] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5066c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295297792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [801] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f3e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295557888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [802] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49ffe,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295559936UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [803] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f8e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295820032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [804] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e24,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295822080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [805] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4126e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4831904512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [806] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402e4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4831906560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [807] = {
+ .class_hid = BNXT_ULP_CLASS_HID_502b4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832166656UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [808] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51d74,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832168704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [809] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a26,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832428800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [810] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48abc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832430848UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [811] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5956c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832690944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [812] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832692992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [813] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409e4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5368775424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [814] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419a4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5368777472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [815] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51844,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369037568UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [816] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508e6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369039616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [817] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4918c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369299712UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [818] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4802e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369301760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [819] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369561856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [820] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369563904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [821] = {
+ .class_hid = BNXT_ULP_CLASS_HID_404ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905646336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [822] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41766,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905648384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [823] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905908480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [824] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507a4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905910528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [825] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f66,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906170624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [826] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906172672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [827] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59fe6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906432768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [828] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906434816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [829] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4126c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442517248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [830] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4028e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442519296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [831] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d5e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442779392UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [832] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51d1e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442781440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [833] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a2c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443041536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [834] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4954e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443043584UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [835] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5951e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443303680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [836] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5858c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443305728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [837] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409fe,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979388160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [838] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979390208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [839] = {
+ .class_hid = BNXT_ULP_CLASS_HID_519ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979650304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [840] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508fc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979652352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [841] = {
+ .class_hid = BNXT_ULP_CLASS_HID_491ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979912448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [842] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4802c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979914496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [843] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580fc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6980174592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [844] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590bc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6980176640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [845] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4074c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516259072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [846] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4170c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516261120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [847] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516521216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [848] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5064e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516523264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [849] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f0c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516783360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [850] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49fcc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516785408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [851] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59fec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7517045504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [852] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e0e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7517047552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [853] = {
+ .class_hid = BNXT_ULP_CLASS_HID_413ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053129984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [854] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053132032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [855] = {
+ .class_hid = BNXT_ULP_CLASS_HID_502ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053392128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [856] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053394176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [857] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053654272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [858] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053656320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [859] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58aae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053916416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [860] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585ec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053918464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [861] = {
+ .class_hid = BNXT_ULP_CLASS_HID_104ae,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI }
+ },
+ [862] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1108e,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI }
+ },
+ [863] = {
+ .class_hid = BNXT_ULP_CLASS_HID_140b2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC }
+ },
+ [864] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c92,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC }
+ },
+ [865] = {
+ .class_hid = BNXT_ULP_CLASS_HID_126a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [866] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13280,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [867] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16d44,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [868] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ea4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [869] = {
+ .class_hid = BNXT_ULP_CLASS_HID_113a4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [870] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e66,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [871] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e40,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [872] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a02,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [873] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13db6,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [874] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12870,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [875] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17852,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [876] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17414,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [877] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11978,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [878] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1153a,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [879] = {
+ .class_hid = BNXT_ULP_CLASS_HID_145fa,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [880] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151da,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [881] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b0a,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [882] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137c8,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [883] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167f0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [884] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [885] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [886] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10092,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [887] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150f0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [888] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14cb2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [889] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136e2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [890] = {
+ .class_hid = BNXT_ULP_CLASS_HID_122a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [891] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17282,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [892] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16940,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [893] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b90,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8590199808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [894] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11654,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8590208000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [895] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14618,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8591248384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [896] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15278,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8591256576UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [897] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12404,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8592296960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [898] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13064,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8592305152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [899] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16028,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8593345536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [900] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c08,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8593353728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [901] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11100,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10737683456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [902] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10dc4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10737691648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [903] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d24,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10738732032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [904] = {
+ .class_hid = BNXT_ULP_CLASS_HID_149d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10738740224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [905] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13314,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10739780608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [906] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12fd4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10739788800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [907] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17f20,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10740829184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [908] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16be0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10740837376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [909] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11cd8,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12885167104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [910] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10880,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12885175296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [911] = {
+ .class_hid = BNXT_ULP_CLASS_HID_158e0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12886215680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [912] = {
+ .class_hid = BNXT_ULP_CLASS_HID_154a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12886223872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [913] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ed0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12887264256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [914] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a90,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12887272448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [915] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16550,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12888312832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [916] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176b0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12888321024UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [917] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bb0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15032650752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [918] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10670,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15032658944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [919] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15650,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15033699328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [920] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14210,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15033707520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [921] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13440,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15034747904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [922] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12000,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15034756096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [923] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17060,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15035796480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [924] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c20,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15035804672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [925] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11511,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17180134400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [926] = {
+ .class_hid = BNXT_ULP_CLASS_HID_101d3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17180142592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [927] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15135,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17181182976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [928] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14df7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17181191168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [929] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13723,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17182231552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [930] = {
+ .class_hid = BNXT_ULP_CLASS_HID_123e5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17182239744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [931] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173c7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17183280128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [932] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f89,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17183288320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [933] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10081,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19327618048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [934] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19327626240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [935] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19328666624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [936] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15885,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19328674816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [937] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12293,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19329715200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [938] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ef3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19329723392UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [939] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16eb7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19330763776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [940] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16561,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19330771968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [941] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e59,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21475101696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [942] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21475109888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [943] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a61,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21476150272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [944] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14623,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21476158464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [945] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1286b,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21477198848UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [946] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12411,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21477207040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [947] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17473,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21478247424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [948] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16031,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21478255616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [949] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10531,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23622585344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [950] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11111,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23622593536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [951] = {
+ .class_hid = BNXT_ULP_CLASS_HID_141d1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23623633920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [952] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d31,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23623642112UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [953] = {
+ .class_hid = BNXT_ULP_CLASS_HID_127c3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23624682496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [954] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13323,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23624690688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [955] = {
+ .class_hid = BNXT_ULP_CLASS_HID_163e3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23625731072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [956] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17fc3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23625739264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [957] = {
+ .class_hid = BNXT_ULP_CLASS_HID_108f5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25770068992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [958] = {
+ .class_hid = BNXT_ULP_CLASS_HID_104b9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25770077184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [959] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15499,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25771117568UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [960] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1435d,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25771125760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [961] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a89,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25772166144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [962] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12149,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25772174336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [963] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176ad,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25773214720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [964] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16d6d,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25773222912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [965] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10665,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27917552640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [966] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11245,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27917560832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [967] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14271,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27918601216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [968] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e51,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27918609408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [969] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12061,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27919649792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [970] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13c41,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27919657984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [971] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c05,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27920698368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [972] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17865,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27920706560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [973] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10d21,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30065036288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [974] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11901,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30065044480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [975] = {
+ .class_hid = BNXT_ULP_CLASS_HID_149c1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30066084864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [976] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14589,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30066093056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [977] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12f31,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30067133440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [978] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b11,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30067141632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [979] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bd9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30068182016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [980] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16799,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30068190208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [981] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11831,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32212519936UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [982] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114f1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32212528128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [983] = {
+ .class_hid = BNXT_ULP_CLASS_HID_144b1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32213568512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [984] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15091,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32213576704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [985] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ac1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32214617088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [986] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13681,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32214625280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [987] = {
+ .class_hid = BNXT_ULP_CLASS_HID_166b1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32215665664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [988] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17291,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32215673856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [989] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4007d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI }
+ },
+ [990] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41041,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI }
+ },
+ [991] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5100d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC }
+ },
+ [992] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f77,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC }
+ },
+ [993] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48845,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [994] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487af,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [995] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5877b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [996] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5973f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [997] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c31,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134284032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [998] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b1b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134286080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [999] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b67,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134546176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1000] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b2b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134548224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1001] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4831f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134808320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1002] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49363,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134810368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1003] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5932f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 135070464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1004] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58211,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 135072512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1005] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4161b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268501760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1006] = {
+ .class_hid = BNXT_ULP_CLASS_HID_405bd,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268503808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1007] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50589,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268763904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1008] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5150d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268765952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1009] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e23,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269026048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1010] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d85,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269028096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1011] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d11,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269288192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1012] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d15,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269290240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1013] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4012d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402719488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1014] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41131,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402721536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [416] = {
- .class_hid = BNXT_ULP_CLASS_HID_2509e,
+ [1015] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5113d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402981632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [417] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c45e,
+ [1016] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50027,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402983680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [418] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f5d6,
+ [1017] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48935,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403243776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [419] = {
- .class_hid = BNXT_ULP_CLASS_HID_23722,
+ [1018] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49939,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403245824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [420] = {
- .class_hid = BNXT_ULP_CLASS_HID_209ae,
+ [1019] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59905,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403505920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d4ba,
+ [1020] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5882f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403507968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1021] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b99,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1022] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b03,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1023] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50acf,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1024] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a93,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1025] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48307,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1026] = {
+ .class_hid = BNXT_ULP_CLASS_HID_492cb,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1027] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59297,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1028] = {
+ .class_hid = BNXT_ULP_CLASS_HID_581d9,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1029] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41653,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671154944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1030] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40655,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671156992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1031] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50601,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671417088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [422] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aea6,
+ [1032] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51545,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [423] = {
- .class_hid = BNXT_ULP_CLASS_HID_24606,
+ [1033] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671679232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [424] = {
- .class_hid = BNXT_ULP_CLASS_HID_25802,
+ [1034] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48e1d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671681280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [425] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc02,
+ [1035] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d49,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671941376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [426] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fd9a,
+ [1036] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d0d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671943424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_207c2,
+ [1037] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40115,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805372672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2315a,
+ [1038] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41099,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805374720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a51a,
+ [1039] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51085,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805634816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d692,
+ [1040] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5000f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805636864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_25686,
+ [1041] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4889d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805896960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_2401e,
+ [1042] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49881,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805899008UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cbde,
+ [1043] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5980d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 806159104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1a,
+ [1044] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59797,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 806161152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_20f96,
+ [1045] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c09,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939590400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_2390e,
+ [1046] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c13,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939592448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ac8e,
+ [1047] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b1f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939852544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de06,
+ [1048] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b03,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939854592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e0a,
+ [1049] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48417,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940114688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f82,
+ [1050] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4931b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940116736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f382,
+ [1051] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59307,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940376832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ed1a,
+ [1052] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58309,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940378880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_2576e,
+ [1053] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4160f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1073808128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_229aa,
+ [1054] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40561,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1073810176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_29d6a,
+ [1055] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5052d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074070272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cee2,
+ [1056] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51501,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074072320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_24ec6,
+ [1057] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dc7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074332416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_2784e,
+ [1058] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074334464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ec0e,
+ [1059] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d05,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074594560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd86,
+ [1060] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59cc9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074596608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f22,
+ [1061] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40161,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2684619776UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208025856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_2112e,
+ [1062] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41125,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2684627968UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208027904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2852e,
+ [1063] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51061,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2685668352UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208288000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b6a6,
+ [1064] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5004b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2685676544UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d86,
+ [1065] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48929,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2686716928UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208550144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_26002,
+ [1066] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4986d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2686725120UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208552192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eb82,
+ [1067] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59829,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2687765504UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208812288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c50a,
+ [1068] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58823,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2687773696UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208814336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_22f82,
+ [1069] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41ba5,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3221490688UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342243584UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_2590a,
+ [1070] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b0f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3221498880UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342245632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ccca,
+ [1071] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b0b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3222539264UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342505728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_28706,
+ [1072] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a8f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3222547456UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342507776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_27e46,
+ [1073] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48303,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3223587840UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342767872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_26fce,
+ [1074] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49307,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3223596032UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342769920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d38e,
+ [1075] = {
+ .class_hid = BNXT_ULP_CLASS_HID_592a3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3224636416UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1343030016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d5ca,
+ [1076] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58205,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3224644608UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1343032064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_21706,
+ [1077] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4172f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3758361600UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476461312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_2408e,
+ [1078] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40621,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3758369792UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476463360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b48e,
+ [1079] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5062d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3759410176UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476723456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e8a,
+ [1080] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51621,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3759418368UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476725504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2660a,
+ [1081] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f07,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3760458752UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476985600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_25782,
+ [1082] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48e29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3760466944UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476987648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db02,
+ [1083] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e25,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3761507328UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1477247744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd8e,
+ [1084] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3761515520UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1477249792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
- BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b9e,
+ [1085] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610679040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_21dda,
+ [1086] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4108d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610681088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_2819a,
+ [1087] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51049,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610941184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b31a,
+ [1088] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50fc3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610943232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a3a,
+ [1089] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48881,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611203328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_26c7e,
+ [1090] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487cb,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611205376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d03e,
+ [1091] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587c7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611465472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c1be,
+ [1092] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5978b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611467520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_2430a,
+ [1093] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c4d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4832103424UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1744896768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_2058e,
+ [1094] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b47,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4832111616UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1744898816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2890e,
+ [1095] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b03,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4833152000UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745158912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba8e,
+ [1096] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b47,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4833160192UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_251ae,
+ [1097] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4834b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4834200576UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745421056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_2542a,
+ [1098] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4930f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4834208768UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745423104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfaa,
+ [1099] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5934b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4835249152UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745683200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c93a,
+ [1100] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5824d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4835257344UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745685248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_213ca,
+ [1101] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41687,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5368974336UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879114496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d5a,
+ [1102] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40609,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5368982528UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879116544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b11a,
+ [1103] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50585,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5370022912UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879376640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b4e,
+ [1104] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51589,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5370031104UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879378688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_2624e,
+ [1105] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e0f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5371071488UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879638784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_253de,
+ [1106] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d81,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5371079680UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879640832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c79e,
+ [1107] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5372120064UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879900928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d9da,
+ [1108] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d01,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5372128256UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879902976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_21b1e,
+ [1109] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40109,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5905845248UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013332224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_2350e,
+ [1110] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4110d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5905853440UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013334272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b88e,
+ [1111] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51109,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5906893824UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013594368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ea0e,
+ [1112] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50003,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5906902016UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013596416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a0a,
+ [1113] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48901,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5907942400UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013856512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b8a,
+ [1114] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49905,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5907950592UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013858560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cf0a,
+ [1115] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59901,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5908990976UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2014118656UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c18e,
+ [1116] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5880b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5908999168UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2014120704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [507] = {
- .class_hid = BNXT_ULP_CLASS_HID_2634e,
+ [1117] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10619,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11225,20 +26064,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI }
},
- [508] = {
- .class_hid = BNXT_ULP_CLASS_HID_2258a,
+ [1118] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11239,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11247,21 +26084,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI }
},
- [509] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a94a,
+ [1119] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14205,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11270,21 +26105,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC }
},
- [510] = {
- .class_hid = BNXT_ULP_CLASS_HID_2daca,
+ [1120] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e25,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11293,22 +26126,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC }
},
- [511] = {
- .class_hid = BNXT_ULP_CLASS_HID_25aae,
+ [1121] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12417,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11317,21 +26148,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
- BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [512] = {
- .class_hid = BNXT_ULP_CLASS_HID_2742e,
+ [1122] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13037,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11340,22 +26169,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [513] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ffee,
+ [1123] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ff3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11364,22 +26191,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [514] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e96e,
+ [1124] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c13,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11388,23 +26213,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [515] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b0a,
+ [1125] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6979587072UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 537136128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11413,21 +26236,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [516] = {
- .class_hid = BNXT_ULP_CLASS_HID_22d0e,
+ [1126] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10cdb,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6979595264UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 537144320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11436,22 +26257,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [517] = {
- .class_hid = BNXT_ULP_CLASS_HID_2910e,
+ [1127] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d19,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6980635648UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 538184704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11460,22 +26279,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [518] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c28e,
+ [1128] = {
+ .class_hid = BNXT_ULP_CLASS_HID_148c7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6980643840UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 538192896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11484,23 +26301,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [519] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422a,
+ [1129] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f0b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6981684224UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 539233280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11509,22 +26324,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [520] = {
- .class_hid = BNXT_ULP_CLASS_HID_273aa,
+ [1130] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ac9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6981692416UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 539241472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11533,23 +26346,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [521] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e7aa,
+ [1131] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17b17,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6982732800UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 540281856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11558,23 +26369,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [522] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d12a,
+ [1132] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176d5,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6982740992UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 540290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11583,24 +26392,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [523] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b8a,
+ [1133] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bab,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7516457984UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1074007040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11609,21 +26416,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [524] = {
- .class_hid = BNXT_ULP_CLASS_HID_2550a,
+ [1134] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10769,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7516466176UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1074015232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11632,22 +26437,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [525] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d8ca,
+ [1135] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15787,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7517506560UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1075055616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11656,22 +26459,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [526] = {
- .class_hid = BNXT_ULP_CLASS_HID_2930e,
+ [1136] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14345,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7517514752UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1075063808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11680,23 +26481,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [527] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a0e,
+ [1137] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12989,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7518555136UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1076104192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11705,22 +26504,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [528] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c4a,
+ [1138] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12567,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7518563328UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1076112384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11729,23 +26526,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [529] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ef4e,
+ [1139] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17585,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7519603712UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1077152768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11754,23 +26549,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [530] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e18a,
+ [1140] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16143,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7519611904UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1077160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11779,24 +26572,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [531] = {
- .class_hid = BNXT_ULP_CLASS_HID_2230e,
+ [1141] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1064d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8053328896UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1610877952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11805,22 +26596,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [532] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c8e,
+ [1142] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1128d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8053337088UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1610886144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11829,23 +26618,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [533] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c08e,
+ [1143] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14249,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8054377472UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1611926528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11854,23 +26641,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [534] = {
- .class_hid = BNXT_ULP_CLASS_HID_29a8a,
+ [1144] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e49,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8054385664UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1611934720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11879,24 +26664,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [535] = {
- .class_hid = BNXT_ULP_CLASS_HID_2718a,
+ [1145] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1244b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8055426048UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1612975104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11905,23 +26688,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [536] = {
- .class_hid = BNXT_ULP_CLASS_HID_2630a,
+ [1146] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1304b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8055434240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1612983296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11930,24 +26711,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [537] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d70a,
+ [1147] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16047,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8056474624UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1614023680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11956,24 +26735,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [538] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e90e,
+ [1148] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c47,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8056482816UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1614031872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11982,25 +26759,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [539] = {
- .class_hid = BNXT_ULP_CLASS_HID_24e91,
+ [1149] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11113,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2147748864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12008,19 +26783,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [540] = {
- .class_hid = BNXT_ULP_CLASS_HID_200d5,
+ [1150] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10cd1,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2147757056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12028,20 +26804,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [541] = {
- .class_hid = BNXT_ULP_CLASS_HID_2edd9,
+ [1151] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15cf7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2148797440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12049,20 +26826,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [542] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a61d,
+ [1152] = {
+ .class_hid = BNXT_ULP_CLASS_HID_148b5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2148805632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12070,21 +26848,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [543] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f7d,
+ [1153] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f01,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2149846016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12092,20 +26871,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [544] = {
- .class_hid = BNXT_ULP_CLASS_HID_251b1,
+ [1154] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ac7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2149854208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12113,21 +26893,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [545] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c571,
+ [1155] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ae5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2150894592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12135,21 +26916,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [546] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f4f9,
+ [1156] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176a3,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2150902784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12157,22 +26939,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [547] = {
- .class_hid = BNXT_ULP_CLASS_HID_25641,
+ [1157] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bd5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2684619776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12180,20 +26963,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [548] = {
- .class_hid = BNXT_ULP_CLASS_HID_22885,
+ [1158] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10793,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2684627968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12201,21 +26985,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [549] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c45,
+ [1159] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15791,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2685668352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12223,21 +27008,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [550] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cfcd,
+ [1160] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14357,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2685676544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12245,22 +27031,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [551] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fe9,
+ [1161] = {
+ .class_hid = BNXT_ULP_CLASS_HID_129c3,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2686716928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12268,21 +27055,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [552] = {
- .class_hid = BNXT_ULP_CLASS_HID_27961,
+ [1162] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12581,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2686725120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12290,22 +27078,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [553] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ed21,
+ [1163] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17587,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2687765504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12313,22 +27102,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [554] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dca9,
+ [1164] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16145,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2687773696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12336,23 +27126,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [555] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ab1,
+ [1165] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10643,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3221490688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12360,20 +27151,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [556] = {
- .class_hid = BNXT_ULP_CLASS_HID_21cf5,
+ [1166] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11263,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3221498880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12381,21 +27173,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [557] = {
- .class_hid = BNXT_ULP_CLASS_HID_280b5,
+ [1167] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14227,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3222539264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12403,21 +27196,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [558] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b235,
+ [1168] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e47,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3222547456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12425,22 +27219,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [559] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b15,
+ [1169] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12421,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3223587840UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12448,21 +27243,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [560] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d51,
+ [1170] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13041,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3223596032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12470,22 +27266,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [561] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d111,
+ [1171] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16005,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3224636416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12493,22 +27290,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [562] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c091,
+ [1172] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c25,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3224644608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12516,23 +27314,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [563] = {
- .class_hid = BNXT_ULP_CLASS_HID_26261,
+ [1173] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11147,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3758361600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12540,21 +27339,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [564] = {
- .class_hid = BNXT_ULP_CLASS_HID_224a5,
+ [1174] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10d05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3758369792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12562,22 +27362,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [565] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a865,
+ [1175] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d43,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3759410176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12585,22 +27386,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [566] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbe5,
+ [1176] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14901,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3759418368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12608,23 +27410,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [567] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b81,
+ [1177] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f45,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3760458752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12632,22 +27435,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [568] = {
- .class_hid = BNXT_ULP_CLASS_HID_27501,
+ [1178] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12b03,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3760466944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12655,23 +27459,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [569] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fec1,
+ [1179] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17b01,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3761507328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12679,23 +27484,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [570] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e841,
+ [1180] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176c7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3761515520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12703,24 +27509,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [571] = {
- .class_hid = BNXT_ULP_CLASS_HID_24085,
+ [1181] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bcf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8590199808UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4295232512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12728,20 +27535,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [572] = {
- .class_hid = BNXT_ULP_CLASS_HID_21ac5,
+ [1182] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1178d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8590208000UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4295240704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12749,21 +27556,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [573] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e85,
+ [1183] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1474d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8591248384UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4296281088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12771,21 +27578,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [574] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b80d,
+ [1184] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1536d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8591256576UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4296289280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12793,22 +27600,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [575] = {
- .class_hid = BNXT_ULP_CLASS_HID_2516d,
+ [1185] = {
+ .class_hid = BNXT_ULP_CLASS_HID_139bd,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8592296960UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4297329664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12816,21 +27623,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [576] = {
- .class_hid = BNXT_ULP_CLASS_HID_26ba5,
+ [1186] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1357f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8592305152UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4297337856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12838,22 +27645,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [577] = {
- .class_hid = BNXT_ULP_CLASS_HID_2df65,
+ [1187] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16547,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8593345536UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4298378240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12861,22 +27668,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [578] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ceed,
+ [1188] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17167,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8593353728UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4298386432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12884,23 +27691,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [579] = {
- .class_hid = BNXT_ULP_CLASS_HID_26845,
+ [1189] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11685,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10737683456UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4832103424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12908,21 +27715,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [580] = {
- .class_hid = BNXT_ULP_CLASS_HID_22285,
+ [1190] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1024f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10737691648UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4832111616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12930,22 +27737,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [581] = {
- .class_hid = BNXT_ULP_CLASS_HID_29645,
+ [1191] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1524d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10738732032UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4833152000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12953,22 +27760,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [582] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c1cd,
+ [1192] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e0f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10738740224UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4833160192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12976,23 +27783,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [583] = {
- .class_hid = BNXT_ULP_CLASS_HID_2418d,
+ [1193] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1345f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10739780608UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4834200576UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13000,22 +27807,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [584] = {
- .class_hid = BNXT_ULP_CLASS_HID_27365,
+ [1194] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1201d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10739788800UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4834208768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13023,23 +27830,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [585] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e725,
+ [1195] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10740829184UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4835249152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13047,23 +27854,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [586] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d6ad,
+ [1196] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c1d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10740837376UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4835257344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13071,24 +27878,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [587] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ca5,
+ [1197] = {
+ .class_hid = BNXT_ULP_CLASS_HID_100ef,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12885167104UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5368974336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13096,21 +27903,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [588] = {
- .class_hid = BNXT_ULP_CLASS_HID_216e5,
+ [1198] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d0f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12885175296UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5368982528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13118,22 +27925,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [589] = {
- .class_hid = BNXT_ULP_CLASS_HID_29aa5,
+ [1199] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ccf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12886215680UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5370022912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13141,22 +27948,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [590] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b425,
+ [1200] = {
+ .class_hid = BNXT_ULP_CLASS_HID_158ef,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12886223872UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5370031104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13164,23 +27971,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [591] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d05,
+ [1201] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12eed,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12887264256UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5371071488UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13188,22 +27995,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [592] = {
- .class_hid = BNXT_ULP_CLASS_HID_26745,
+ [1202] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b0d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12887272448UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5371079680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13211,23 +28018,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [593] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eb05,
+ [1203] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16acd,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12888312832UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5372120064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13235,23 +28042,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [594] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da85,
+ [1204] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16687,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12888321024UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5372128256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13259,24 +28066,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [595] = {
- .class_hid = BNXT_ULP_CLASS_HID_20cc5,
+ [1205] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11c07,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15032650752UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5905845248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13284,22 +28091,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [596] = {
- .class_hid = BNXT_ULP_CLASS_HID_23ea5,
+ [1206] = {
+ .class_hid = BNXT_ULP_CLASS_HID_117c5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15032658944UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5905853440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13307,23 +28114,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [597] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a265,
+ [1207] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1478d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15033699328UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5906893824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13331,23 +28138,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [598] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dde5,
+ [1208] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1538d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15033707520UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5906902016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13355,24 +28162,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [599] = {
- .class_hid = BNXT_ULP_CLASS_HID_25da5,
+ [1209] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13a05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15034747904UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5907942400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13380,23 +28187,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [600] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f05,
+ [1210] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135cf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15034756096UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5907950592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13404,24 +28211,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [601] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f0c5,
+ [1211] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1658f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15035796480UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5908990976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13429,24 +28236,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [602] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e245,
+ [1212] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1718f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15035804672UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5908999168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13454,25 +28261,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [603] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d8b,
+ [1213] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11667,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17180134400UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6442716160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13480,20 +28287,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [604] = {
- .class_hid = BNXT_ULP_CLASS_HID_207cf,
+ [1214] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10225,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17180142592UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6442724352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13501,21 +28309,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [605] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b8f,
+ [1215] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15247,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17181182976UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6443764736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13523,21 +28332,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [606] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a517,
+ [1216] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17181191168UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6443772928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13545,22 +28355,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [607] = {
- .class_hid = BNXT_ULP_CLASS_HID_25277,
+ [1217] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13455,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17182231552UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6444813312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13568,21 +28379,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [608] = {
- .class_hid = BNXT_ULP_CLASS_HID_254ab,
+ [1218] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12017,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17182239744UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6444821504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13590,22 +28402,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [609] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d86b,
+ [1219] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17035,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17183280128UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6445861888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13613,22 +28426,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [610] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cbf3,
+ [1220] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bf7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17183288320UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6445870080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13636,23 +28450,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [611] = {
- .class_hid = BNXT_ULP_CLASS_HID_2554b,
+ [1221] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10115,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19327618048UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6979587072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13660,21 +28475,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [612] = {
- .class_hid = BNXT_ULP_CLASS_HID_22f8f,
+ [1222] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d15,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19327626240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6979595264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13682,22 +28498,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [613] = {
- .class_hid = BNXT_ULP_CLASS_HID_2934f,
+ [1223] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14d05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19328666624UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6980635648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13705,22 +28522,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [614] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c2c7,
+ [1224] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15905,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19328674816UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6980643840UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13728,23 +28546,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [615] = {
- .class_hid = BNXT_ULP_CLASS_HID_242e3,
+ [1225] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12f17,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19329715200UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6981684224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13752,22 +28571,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [616] = {
- .class_hid = BNXT_ULP_CLASS_HID_27c6b,
+ [1226] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b17,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19329723392UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6981692416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13775,23 +28595,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [617] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e02b,
+ [1227] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ad7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19330763776UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6982732800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13799,23 +28620,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [618] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d3a3,
+ [1228] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16695,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19330771968UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6982740992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13823,24 +28645,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [619] = {
- .class_hid = BNXT_ULP_CLASS_HID_259a3,
+ [1229] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11be5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21475101696UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7516457984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13848,21 +28671,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [620] = {
- .class_hid = BNXT_ULP_CLASS_HID_213e7,
+ [1230] = {
+ .class_hid = BNXT_ULP_CLASS_HID_117a7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21475109888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7516466176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13870,22 +28694,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [621] = {
- .class_hid = BNXT_ULP_CLASS_HID_287a7,
+ [1231] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14767,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21476150272UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7517506560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13893,22 +28718,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [622] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b137,
+ [1232] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15387,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21476158464UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7517514752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13916,23 +28742,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [623] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e17,
+ [1233] = {
+ .class_hid = BNXT_ULP_CLASS_HID_139e7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21477198848UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7518555136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13940,22 +28767,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [624] = {
- .class_hid = BNXT_ULP_CLASS_HID_26043,
+ [1234] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135a5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21477207040UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7518563328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13963,23 +28791,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [625] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d403,
+ [1235] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16565,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21478247424UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7519603712UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13987,23 +28816,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [626] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c793,
+ [1236] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17185,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21478255616UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7519611904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14011,24 +28841,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [627] = {
- .class_hid = BNXT_ULP_CLASS_HID_20827,
+ [1237] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11687,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23622585344UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8053328896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14036,46 +28867,48 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [628] = {
- .class_hid = BNXT_ULP_CLASS_HID_23ba7,
+ [1238] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10245,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23622593536UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8053337088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [629] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af67,
+ [1239] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15287,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23623633920UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8054377472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14083,23 +28916,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [630] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dee7,
+ [1240] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e45,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23623642112UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8054385664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14107,24 +28941,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [631] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e83,
+ [1241] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13485,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23624682496UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8055426048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14132,23 +28967,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [632] = {
- .class_hid = BNXT_ULP_CLASS_HID_24803,
+ [1242] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12047,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23624690688UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8055434240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14156,24 +28992,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [633] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fdc3,
+ [1243] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17085,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23625731072UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8056474624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14181,24 +29018,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [634] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ef43,
+ [1244] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c47,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23625739264UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8056482816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14206,3033 +29044,3034 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [635] = {
- .class_hid = BNXT_ULP_CLASS_HID_247bf,
+ [1245] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400f4,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25770068992UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI }
},
- [636] = {
- .class_hid = BNXT_ULP_CLASS_HID_219ff,
+ [1246] = {
+ .class_hid = BNXT_ULP_CLASS_HID_410c8,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25770077184UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI }
},
- [637] = {
- .class_hid = BNXT_ULP_CLASS_HID_28dbf,
+ [1247] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51084,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25771117568UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC }
},
- [638] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf07,
+ [1248] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ffe,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25771125760UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 330496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC }
},
- [639] = {
- .class_hid = BNXT_ULP_CLASS_HID_25467,
+ [1249] = {
+ .class_hid = BNXT_ULP_CLASS_HID_488cc,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25772166144UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 590592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [640] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e5f,
+ [1250] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48726,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25772174336UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 592640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [641] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d21f,
+ [1251] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587f2,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25773214720UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 852736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [642] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cde7,
+ [1252] = {
+ .class_hid = BNXT_ULP_CLASS_HID_597b6,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25773222912UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 854784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [643] = {
- .class_hid = BNXT_ULP_CLASS_HID_26f6f,
+ [1253] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b10,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27917552640UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 536937216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [644] = {
- .class_hid = BNXT_ULP_CLASS_HID_221af,
+ [1254] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b8a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27917560832UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 536939264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [645] = {
- .class_hid = BNXT_ULP_CLASS_HID_2956f,
+ [1255] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a46,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27918601216UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537199360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [646] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c4c7,
+ [1256] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a1a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27918609408UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537201408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [647] = {
- .class_hid = BNXT_ULP_CLASS_HID_24487,
+ [1257] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4838e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27919649792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537461504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [648] = {
- .class_hid = BNXT_ULP_CLASS_HID_2760f,
+ [1258] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49242,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27919657984UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537463552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [649] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fbcf,
+ [1259] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27920698368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537723648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [650] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d5a7,
+ [1260] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58150,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27920706560UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537725696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [651] = {
- .class_hid = BNXT_ULP_CLASS_HID_25357,
+ [1261] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41686,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30065036288UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1073808128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [652] = {
- .class_hid = BNXT_ULP_CLASS_HID_21597,
+ [1262] = {
+ .class_hid = BNXT_ULP_CLASS_HID_405e8,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30065044480UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1073810176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [653] = {
- .class_hid = BNXT_ULP_CLASS_HID_29957,
+ [1263] = {
+ .class_hid = BNXT_ULP_CLASS_HID_505a4,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30066084864UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074070272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [654] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cb27,
+ [1264] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51588,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30066093056UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074072320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [655] = {
- .class_hid = BNXT_ULP_CLASS_HID_248f7,
+ [1265] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d4e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30067133440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074332416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [656] = {
- .class_hid = BNXT_ULP_CLASS_HID_27a77,
+ [1266] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48da0,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30067141632UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074334464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [657] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee37,
+ [1267] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8c,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30068182016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074594560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [658] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d987,
+ [1268] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59c40,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30068190208UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074596608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [659] = {
- .class_hid = BNXT_ULP_CLASS_HID_203c7,
+ [1269] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40040,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32212519936UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610679040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [660] = {
- .class_hid = BNXT_ULP_CLASS_HID_23d47,
+ [1270] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41004,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32212528128UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610681088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [661] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a107,
+ [1271] = {
+ .class_hid = BNXT_ULP_CLASS_HID_510c0,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32213568512UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610941184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [662] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d0e7,
+ [1272] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f4a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32213576704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610943232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [663] = {
- .class_hid = BNXT_ULP_CLASS_HID_250a7,
+ [1273] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48808,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32214617088UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611203328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [664] = {
- .class_hid = BNXT_ULP_CLASS_HID_24227,
+ [1274] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48742,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32214625280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611205376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [665] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f7e7,
+ [1275] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5874e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32215665664UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611465472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [666] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c827,
+ [1276] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59702,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32215673856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611467520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [667] = {
- .class_hid = BNXT_ULP_CLASS_HID_25422,
+ [1277] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41bfe,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147549952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [668] = {
- .class_hid = BNXT_ULP_CLASS_HID_21a66,
+ [1278] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40a58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147552000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [669] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f76a,
+ [1279] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a2c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147812096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [670] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bcae,
+ [1280] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51ae8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147814144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [671] = {
- .class_hid = BNXT_ULP_CLASS_HID_245ce,
+ [1281] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4825c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148074240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [672] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b02,
+ [1282] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49228,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148076288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [673] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfc2,
+ [1283] = {
+ .class_hid = BNXT_ULP_CLASS_HID_592ec,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148336384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [674] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee4a,
+ [1284] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5815e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148338432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [675] = {
- .class_hid = BNXT_ULP_CLASS_HID_22cbe,
+ [1285] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41698,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684420864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [676] = {
- .class_hid = BNXT_ULP_CLASS_HID_21232,
+ [1286] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4051a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684422912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [677] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cf26,
+ [1287] = {
+ .class_hid = BNXT_ULP_CLASS_HID_505ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684683008UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [678] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b53a,
+ [1288] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5158a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684685056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [679] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d9a,
+ [1289] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684945152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [680] = {
- .class_hid = BNXT_ULP_CLASS_HID_2439e,
+ [1290] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48dca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684947200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [681] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d79e,
+ [1291] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2685207296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [682] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e606,
+ [1292] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59c5a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2685209344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [683] = {
- .class_hid = BNXT_ULP_CLASS_HID_21c5e,
+ [1293] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4002e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221291776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [684] = {
- .class_hid = BNXT_ULP_CLASS_HID_22ac6,
+ [1294] = {
+ .class_hid = BNXT_ULP_CLASS_HID_410ea,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221293824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [685] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be86,
+ [1295] = {
+ .class_hid = BNXT_ULP_CLASS_HID_510ae,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221553920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [686] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cd0e,
+ [1296] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f08,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221555968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [687] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d1a,
+ [1297] = {
+ .class_hid = BNXT_ULP_CLASS_HID_488ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221816064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [688] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b82,
+ [1298] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48748,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221818112UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
- BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [689] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d042,
+ [1299] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5870c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3222078208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [690] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d586,
+ [1300] = {
+ .class_hid = BNXT_ULP_CLASS_HID_597e8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3222080256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [691] = {
- .class_hid = BNXT_ULP_CLASS_HID_2140a,
+ [1301] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b4a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758162688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [692] = {
- .class_hid = BNXT_ULP_CLASS_HID_22292,
+ [1302] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b8c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758164736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [693] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b712,
+ [1303] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a48,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758424832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [694] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c59a,
+ [1304] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a0c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758426880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [695] = {
- .class_hid = BNXT_ULP_CLASS_HID_24596,
+ [1305] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48388,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758686976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [696] = {
- .class_hid = BNXT_ULP_CLASS_HID_2541e,
+ [1306] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4924c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758689024UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [697] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e81e,
+ [1307] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59208,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758949120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [698] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f686,
+ [1308] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5828a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758951168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [699] = {
- .class_hid = BNXT_ULP_CLASS_HID_24cf2,
+ [1309] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40540,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295033600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [700] = {
- .class_hid = BNXT_ULP_CLASS_HID_23236,
+ [1310] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41500,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295035648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [701] = {
- .class_hid = BNXT_ULP_CLASS_HID_286f6,
+ [1311] = {
+ .class_hid = BNXT_ULP_CLASS_HID_515d0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295295744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [702] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d57e,
+ [1312] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5044a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295297792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [703] = {
- .class_hid = BNXT_ULP_CLASS_HID_2555a,
+ [1313] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d18,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295557888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [704] = {
- .class_hid = BNXT_ULP_CLASS_HID_263d2,
+ [1314] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dd8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295559936UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [705] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f792,
+ [1315] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59da8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295820032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [706] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c61a,
+ [1316] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c02,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295822080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [707] = {
- .class_hid = BNXT_ULP_CLASS_HID_244be,
+ [1317] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41048,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2684619776UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4831904512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [708] = {
- .class_hid = BNXT_ULP_CLASS_HID_20ab2,
+ [1318] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c2,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2684627968UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4831906560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [709] = {
- .class_hid = BNXT_ULP_CLASS_HID_29eb2,
- .class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2685668352UL,
+ [1319] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50092,
+ .class_tid = 2,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832166656UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [710] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ad3a,
+ [1320] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51f52,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2685676544UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832168704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [711] = {
- .class_hid = BNXT_ULP_CLASS_HID_2761a,
+ [1321] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49800,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2686716928UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832428800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [712] = {
- .class_hid = BNXT_ULP_CLASS_HID_27b9e,
+ [1322] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4889a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2686725120UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832430848UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [713] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f01e,
+ [1323] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5974a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2687765504UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832690944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [714] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de96,
+ [1324] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2687773696UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832692992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [715] = {
- .class_hid = BNXT_ULP_CLASS_HID_2341e,
+ [1325] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40bc2,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3221490688UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5368775424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [716] = {
- .class_hid = BNXT_ULP_CLASS_HID_24296,
+ [1326] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b82,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3221498880UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5368777472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [717] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d756,
+ [1327] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a62,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3222539264UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369037568UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [718] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c9a,
+ [1328] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ac0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3222547456UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369039616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [719] = {
- .class_hid = BNXT_ULP_CLASS_HID_265da,
+ [1329] = {
+ .class_hid = BNXT_ULP_CLASS_HID_493aa,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3223587840UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369299712UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [720] = {
- .class_hid = BNXT_ULP_CLASS_HID_27452,
+ [1330] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48208,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3223596032UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369301760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [721] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c812,
+ [1331] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3224636416UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369561856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [722] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce56,
+ [1332] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59288,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3224644608UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369563904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [723] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c9a,
+ [1333] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40688,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3758361600UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905646336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [724] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b12,
+ [1334] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41540,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3758369792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905648384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [725] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af12,
+ [1335] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51508,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3759410176UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905908480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [726] = {
- .class_hid = BNXT_ULP_CLASS_HID_29516,
+ [1336] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50582,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3759418368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905910528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [727] = {
- .class_hid = BNXT_ULP_CLASS_HID_27d96,
+ [1337] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d40,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3760458752UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906170624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [728] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c1e,
+ [1338] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d08,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3760466944UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906172672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [729] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c09e,
+ [1339] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59dc0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3761507328UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906432768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [730] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c612,
+ [1340] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c4a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3761515520UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906434816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [731] = {
- .class_hid = BNXT_ULP_CLASS_HID_24002,
+ [1341] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4104a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442517248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [732] = {
- .class_hid = BNXT_ULP_CLASS_HID_20646,
+ [1342] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400a8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442519296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [733] = {
- .class_hid = BNXT_ULP_CLASS_HID_29a06,
+ [1343] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f78,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442779392UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [734] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a886,
+ [1344] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51f38,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442781440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [735] = {
- .class_hid = BNXT_ULP_CLASS_HID_271a6,
+ [1345] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4980a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443041536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [736] = {
- .class_hid = BNXT_ULP_CLASS_HID_277e2,
+ [1346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49768,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443043584UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [737] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cba2,
+ [1347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59738,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443303680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [738] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da22,
+ [1348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587aa,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443305728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [739] = {
- .class_hid = BNXT_ULP_CLASS_HID_25896,
+ [1349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40bd8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4832103424UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979388160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [740] = {
- .class_hid = BNXT_ULP_CLASS_HID_21e12,
+ [1350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41bc8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4832111616UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979390208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [741] = {
- .class_hid = BNXT_ULP_CLASS_HID_29292,
+ [1351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b88,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4833152000UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979650304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [742] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a112,
+ [1352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ada,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4833160192UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979652352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [743] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a32,
+ [1353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_493c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4834200576UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979912448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [744] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fb6,
+ [1354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4820a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4834208768UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979914496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [745] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c436,
+ [1355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582da,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4835249152UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6980174592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [746] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d2a6,
+ [1356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5929a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4835257344UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6980176640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [747] = {
- .class_hid = BNXT_ULP_CLASS_HID_20856,
+ [1357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4056a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5368974336UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516259072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [748] = {
- .class_hid = BNXT_ULP_CLASS_HID_256c6,
+ [1358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4152a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5368982528UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516261120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [749] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa86,
+ [1359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5150a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5370022912UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516521216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
- BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [750] = {
- .class_hid = BNXT_ULP_CLASS_HID_290d2,
+ [1360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50468,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5370031104UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516523264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [751] = {
- .class_hid = BNXT_ULP_CLASS_HID_279d2,
+ [1361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d2a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5371071488UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516783360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [752] = {
- .class_hid = BNXT_ULP_CLASS_HID_24842,
+ [1362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dea,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5371079680UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516785408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [753] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dc02,
+ [1363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59dca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5372120064UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7517045504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [754] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c246,
+ [1364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c28,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5372128256UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7517047552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [755] = {
- .class_hid = BNXT_ULP_CLASS_HID_20082,
+ [1365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4118a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5905845248UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053129984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [756] = {
- .class_hid = BNXT_ULP_CLASS_HID_22e92,
+ [1366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5905853440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053132032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [757] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a312,
+ [1367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50088,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5906893824UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053392128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [758] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f192,
+ [1368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51088,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5906902016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053394176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [759] = {
- .class_hid = BNXT_ULP_CLASS_HID_27196,
+ [1369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4984a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5907942400UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053654272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [760] = {
- .class_hid = BNXT_ULP_CLASS_HID_24016,
+ [1370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48888,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5907950592UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053656320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [761] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d496,
+ [1371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58888,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5908990976UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053916416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [762] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da12,
+ [1372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587ca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5908999168UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053918464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [763] = {
- .class_hid = BNXT_ULP_CLASS_HID_278d2,
+ [1373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10690,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17240,21 +32079,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI }
},
- [764] = {
- .class_hid = BNXT_ULP_CLASS_HID_23e16,
+ [1374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_112b0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17262,22 +32099,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI }
},
- [765] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b2d6,
+ [1375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1428c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17285,22 +32120,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC }
},
- [766] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c156,
+ [1376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15eac,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17308,23 +32141,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC }
},
- [767] = {
- .class_hid = BNXT_ULP_CLASS_HID_24132,
+ [1377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1249e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17332,22 +32163,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [768] = {
- .class_hid = BNXT_ULP_CLASS_HID_26fb2,
+ [1378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_130be,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17355,23 +32184,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [769] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e472,
+ [1379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f7a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17379,23 +32206,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [770] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f2f2,
+ [1380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c9a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17403,24 +32228,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [771] = {
- .class_hid = BNXT_ULP_CLASS_HID_27096,
+ [1381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1119a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6979587072UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2147748864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17428,22 +32251,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [772] = {
- .class_hid = BNXT_ULP_CLASS_HID_23692,
+ [1382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10c58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6979595264UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2147757056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17451,23 +32272,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [773] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a92,
+ [1383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c7e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6980635648UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2148797440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17475,23 +32294,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [774] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d912,
+ [1384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1483c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6980643840UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2148805632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17499,24 +32316,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [775] = {
- .class_hid = BNXT_ULP_CLASS_HID_259b6,
+ [1385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f88,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6981684224UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2149846016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17524,23 +32339,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [776] = {
- .class_hid = BNXT_ULP_CLASS_HID_26836,
+ [1386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a4e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6981692416UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2149854208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17548,24 +32361,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [777] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fc36,
+ [1387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17a6c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6982732800UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2150894592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17573,24 +32384,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [778] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cab6,
+ [1388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1762a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6982740992UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2150902784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17598,25 +32407,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [779] = {
- .class_hid = BNXT_ULP_CLASS_HID_22016,
+ [1389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b46,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7516457984UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4295232512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17624,22 +32431,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [780] = {
- .class_hid = BNXT_ULP_CLASS_HID_24e96,
+ [1390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11704,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7516466176UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4295240704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17647,23 +32452,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [781] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c356,
+ [1391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_147c4,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7517506560UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4296281088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17671,23 +32474,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [782] = {
- .class_hid = BNXT_ULP_CLASS_HID_28892,
+ [1392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153e4,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7517514752UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4296289280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17695,24 +32496,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [783] = {
- .class_hid = BNXT_ULP_CLASS_HID_25192,
+ [1393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13934,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7518555136UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4297329664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17720,23 +32519,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [784] = {
- .class_hid = BNXT_ULP_CLASS_HID_257d6,
+ [1394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135f6,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7518563328UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4297337856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17744,24 +32541,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [785] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f4d2,
+ [1395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_165ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7519603712UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4298378240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17769,24 +32564,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [786] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fa16,
+ [1396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_171ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7519611904UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4298386432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17794,25 +32587,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [787] = {
- .class_hid = BNXT_ULP_CLASS_HID_23892,
+ [1397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8053328896UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6442716160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17820,23 +32611,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [788] = {
- .class_hid = BNXT_ULP_CLASS_HID_24712,
+ [1398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102ac,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8053337088UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6442724352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17844,24 +32633,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [789] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db12,
+ [1399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_152ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8054377472UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6443764736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17869,24 +32656,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [790] = {
- .class_hid = BNXT_ULP_CLASS_HID_28116,
+ [1400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e8c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8054385664UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6443772928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17894,25 +32679,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [791] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a16,
+ [1401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134dc,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8055426048UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6444813312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17920,24 +32703,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [792] = {
- .class_hid = BNXT_ULP_CLASS_HID_27896,
+ [1402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1209e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8055434240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6444821504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17945,25 +32726,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [793] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc96,
+ [1403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_170bc,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8056474624UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6445861888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17971,25 +32750,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [794] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f292,
+ [1404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16b7e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8056482816UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6445870080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17997,26 +32774,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [795] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b05,
+ [1405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119ae,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8590199808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18028,15 +32803,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [796] = {
- .class_hid = BNXT_ULP_CLASS_HID_20541,
+ [1406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1146a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8590208000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18048,16 +32824,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [797] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e84d,
+ [1407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14426,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8591248384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18069,16 +32846,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [798] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a389,
+ [1408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15046,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8591256576UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18090,17 +32868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [799] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ae9,
+ [1409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1263a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8592296960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18112,16 +32891,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [800] = {
- .class_hid = BNXT_ULP_CLASS_HID_25425,
+ [1410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1325a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8592305152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18133,17 +32913,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [801] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c0e5,
+ [1411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16216,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8593345536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18155,17 +32936,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [802] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f16d,
+ [1412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e36,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8593353728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18177,18 +32959,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [803] = {
- .class_hid = BNXT_ULP_CLASS_HID_253d5,
+ [1413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1133e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10737683456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18200,16 +32983,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [804] = {
- .class_hid = BNXT_ULP_CLASS_HID_22d11,
+ [1414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10ffa,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10737691648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18221,17 +33005,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [805] = {
- .class_hid = BNXT_ULP_CLASS_HID_299d1,
+ [1415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f1a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10738732032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18243,17 +33028,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [806] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ca59,
+ [1416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14bee,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10738740224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18265,18 +33051,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [807] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a7d,
+ [1417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1312a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10739780608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18288,17 +33075,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [808] = {
- .class_hid = BNXT_ULP_CLASS_HID_27cf5,
+ [1418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12dea,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10739788800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18310,18 +33098,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [809] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e8b5,
+ [1419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17d1e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10740829184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18333,18 +33122,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [810] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d93d,
+ [1420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169de,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10740837376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18356,19 +33146,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [811] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f25,
+ [1421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11ee6,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12885167104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18380,16 +33171,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [812] = {
- .class_hid = BNXT_ULP_CLASS_HID_21961,
+ [1422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10abe,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12885175296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18401,17 +33193,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [813] = {
- .class_hid = BNXT_ULP_CLASS_HID_28521,
+ [1423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ade,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12886215680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18423,17 +33216,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [814] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b7a1,
+ [1424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1569e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12886223872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18445,18 +33239,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [815] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e81,
+ [1425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13cee,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12887264256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18468,17 +33263,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [816] = {
- .class_hid = BNXT_ULP_CLASS_HID_268c5,
+ [1426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128ae,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12887272448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18490,18 +33286,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [817] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d485,
+ [1427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1676e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12888312832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18513,18 +33310,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [818] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c505,
+ [1428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1748e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12888321024UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18536,19 +33334,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [819] = {
- .class_hid = BNXT_ULP_CLASS_HID_267f5,
+ [1429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1098e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15032650752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18560,17 +33359,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [820] = {
- .class_hid = BNXT_ULP_CLASS_HID_22131,
+ [1430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1044e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15032658944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18582,18 +33382,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [821] = {
- .class_hid = BNXT_ULP_CLASS_HID_2adf1,
+ [1431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1546e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15033699328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18605,18 +33406,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [822] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de71,
+ [1432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1402e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15033707520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18628,19 +33430,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [823] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e15,
+ [1433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1367e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15034747904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18652,18 +33455,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [824] = {
- .class_hid = BNXT_ULP_CLASS_HID_27095,
+ [1434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1223e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15034756096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18675,19 +33479,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [825] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fb55,
+ [1435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1725e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15035796480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18699,19 +33504,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [826] = {
- .class_hid = BNXT_ULP_CLASS_HID_2edd5,
+ [1436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e1e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15035804672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18723,20 +33529,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [827] = {
- .class_hid = BNXT_ULP_CLASS_HID_24511,
+ [1437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1172f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8590199808UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17180134400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18748,16 +33555,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [828] = {
- .class_hid = BNXT_ULP_CLASS_HID_21f51,
+ [1438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_103ed,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8590208000UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17180142592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18769,17 +33576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [829] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b11,
+ [1439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1530b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8591248384UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17181182976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18791,17 +33598,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [830] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bd99,
+ [1440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14fc9,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8591256576UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17181191168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18813,18 +33620,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [831] = {
- .class_hid = BNXT_ULP_CLASS_HID_254f9,
+ [1441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1351d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8592296960UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17182231552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18836,17 +33643,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [832] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e31,
+ [1442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_121db,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8592305152UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17182239744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18858,18 +33665,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [833] = {
- .class_hid = BNXT_ULP_CLASS_HID_2daf1,
+ [1443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_171f9,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8593345536UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17183280128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18881,18 +33688,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [834] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cb79,
+ [1444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16db7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8593353728UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17183288320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18904,19 +33711,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [835] = {
- .class_hid = BNXT_ULP_CLASS_HID_26dd1,
+ [1445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102bf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10737683456UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19327618048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18928,17 +33735,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [836] = {
- .class_hid = BNXT_ULP_CLASS_HID_22711,
+ [1446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11edf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10737691648UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19327626240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18950,18 +33757,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [837] = {
- .class_hid = BNXT_ULP_CLASS_HID_293d1,
+ [1447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e9b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10738732032UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19328666624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18973,18 +33780,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [838] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c459,
+ [1448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15abb,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10738740224UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19328674816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18996,19 +33803,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [839] = {
- .class_hid = BNXT_ULP_CLASS_HID_24419,
+ [1449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_120ad,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10739780608UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19329715200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19020,18 +33827,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [840] = {
- .class_hid = BNXT_ULP_CLASS_HID_276f1,
+ [1450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ccd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10739788800UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19329723392UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19043,19 +33850,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [841] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e2b1,
+ [1451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c89,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10740829184UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19330763776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19067,19 +33874,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [842] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d339,
+ [1452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1675f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10740837376UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19330771968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19091,20 +33898,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [843] = {
- .class_hid = BNXT_ULP_CLASS_HID_25931,
+ [1453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10c67,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12885167104UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21475101696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19116,17 +33923,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [844] = {
- .class_hid = BNXT_ULP_CLASS_HID_21371,
+ [1454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11987,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12885175296UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21475109888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19138,18 +33945,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [845] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f31,
+ [1455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12886215680UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21476150272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19161,18 +33968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [846] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b1b1,
+ [1456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1441d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12886223872UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21476158464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19184,19 +33991,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [847] = {
- .class_hid = BNXT_ULP_CLASS_HID_26891,
+ [1457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a55,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12887264256UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21477198848UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19208,18 +34015,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [848] = {
- .class_hid = BNXT_ULP_CLASS_HID_262d1,
+ [1458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1262f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12887272448UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21477207040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19231,19 +34038,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [849] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee91,
+ [1459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1764d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12888312832UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21478247424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19255,19 +34062,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [850] = {
- .class_hid = BNXT_ULP_CLASS_HID_2df11,
+ [1460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1620f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12888321024UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21478255616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19279,20 +34086,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [851] = {
- .class_hid = BNXT_ULP_CLASS_HID_20951,
+ [1461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1070f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15032650752UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23622585344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19304,18 +34111,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [852] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b31,
+ [1462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1132f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15032658944UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23622593536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19327,19 +34134,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [853] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a7f1,
+ [1463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_143ef,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15033699328UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23623633920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19351,19 +34158,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [854] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d871,
+ [1464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15033707520UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23623642112UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19375,20 +34182,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [855] = {
- .class_hid = BNXT_ULP_CLASS_HID_25831,
+ [1465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_125fd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15034747904UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23624682496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19400,19 +34207,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [856] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a91,
+ [1466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1311d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15034756096UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23624690688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19424,20 +34231,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [857] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f551,
+ [1467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_161dd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15035796480UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23625731072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19449,20 +34256,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [858] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e7d1,
+ [1468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17dfd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15035804672UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23625739264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19474,21 +34281,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [859] = {
- .class_hid = BNXT_ULP_CLASS_HID_2481f,
+ [1469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10acb,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17180134400UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25770068992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19500,16 +34307,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [860] = {
- .class_hid = BNXT_ULP_CLASS_HID_2025b,
+ [1470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10687,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17180142592UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25770077184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19521,17 +34329,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [861] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e1b,
+ [1471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_156a7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17181182976UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25771117568UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19543,17 +34352,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [862] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a083,
+ [1472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14163,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17181191168UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25771125760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19565,18 +34375,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [863] = {
- .class_hid = BNXT_ULP_CLASS_HID_257e3,
+ [1473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128b7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17182231552UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25772166144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19588,17 +34399,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [864] = {
- .class_hid = BNXT_ULP_CLASS_HID_2513f,
+ [1474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12377,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17182239744UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25772174336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19610,18 +34422,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [865] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ddff,
+ [1475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17493,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17183280128UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25773214720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19633,18 +34446,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [866] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce67,
+ [1476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f53,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17183288320UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25773222912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19656,19 +34470,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [867] = {
- .class_hid = BNXT_ULP_CLASS_HID_250df,
+ [1477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1045b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19327618048UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27917552640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19680,17 +34495,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [868] = {
- .class_hid = BNXT_ULP_CLASS_HID_22a1b,
+ [1478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1107b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19327626240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27917560832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19702,18 +34518,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [869] = {
- .class_hid = BNXT_ULP_CLASS_HID_296db,
+ [1479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1404f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19328666624UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27918601216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19725,18 +34542,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [870] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c753,
+ [1480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c6f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19328674816UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27918609408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19748,19 +34566,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [871] = {
- .class_hid = BNXT_ULP_CLASS_HID_24777,
+ [1481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1225f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19329715200UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27919649792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19772,18 +34591,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [872] = {
- .class_hid = BNXT_ULP_CLASS_HID_279ff,
+ [1482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13e7f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19329723392UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27919657984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19795,19 +34615,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [873] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e5bf,
+ [1483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e3b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19330763776UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27920698368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19819,19 +34640,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [874] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d637,
+ [1484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17a5b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19330771968UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27920706560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19842,21 +34664,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [875] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c37,
+ [1485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10f1f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21475101696UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30065036288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19868,17 +34691,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [876] = {
- .class_hid = BNXT_ULP_CLASS_HID_21673,
+ [1486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b3f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21475109888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30065044480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19890,18 +34714,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [877] = {
- .class_hid = BNXT_ULP_CLASS_HID_28233,
+ [1487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14bff,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21476150272UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30066084864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19913,18 +34738,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [878] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b4a3,
+ [1488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_147b7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21476158464UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30066093056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19936,19 +34762,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [879] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b83,
+ [1489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21477198848UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30067133440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19960,18 +34787,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [880] = {
- .class_hid = BNXT_ULP_CLASS_HID_265d7,
+ [1490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1392f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21477207040UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30067141632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19983,19 +34811,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [881] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d197,
+ [1491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169e7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21478247424UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30068182016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20007,19 +34836,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [882] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c207,
+ [1492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_165a7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21478255616UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30068190208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20031,20 +34861,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [883] = {
- .class_hid = BNXT_ULP_CLASS_HID_20db3,
+ [1493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11a0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23622585344UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32212519936UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20056,18 +34887,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [884] = {
- .class_hid = BNXT_ULP_CLASS_HID_23e33,
+ [1494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116cf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23622593536UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32212528128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20079,19 +34911,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [885] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aaf3,
+ [1495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1468f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23623633920UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32213568512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20103,19 +34936,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [886] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db73,
+ [1496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_152af,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23623642112UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32213576704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20127,20 +34961,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [887] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b17,
+ [1497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_138ff,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23624682496UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32214617088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20152,19 +34987,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [888] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d97,
+ [1498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134bf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23624690688UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32214625280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20176,20 +35012,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [889] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f857,
+ [1499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1648f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23625731072UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32215665664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20201,20 +35038,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [890] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ead7,
+ [1500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_170af,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23625739264UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32215673856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20226,804 +35064,741 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [891] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422b,
+ [1501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c38,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25770068992UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI }
},
- [892] = {
- .class_hid = BNXT_ULP_CLASS_HID_21c6b,
+ [1502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c04,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25770077184UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI }
},
- [893] = {
- .class_hid = BNXT_ULP_CLASS_HID_2882b,
+ [1503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51c48,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25771117568UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC }
},
- [894] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba93,
+ [1504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50332,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25771125760UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC }
},
- [895] = {
- .class_hid = BNXT_ULP_CLASS_HID_251f3,
+ [1505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48400,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25772166144UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [896] = {
- .class_hid = BNXT_ULP_CLASS_HID_26bcb,
+ [1506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48bea,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25772174336UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [897] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d78b,
+ [1507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b3e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25773214720UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [898] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c873,
+ [1508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b7a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25773222912UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [899] = {
- .class_hid = BNXT_ULP_CLASS_HID_26afb,
+ [1509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_417dc,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27917552640UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [900] = {
- .class_hid = BNXT_ULP_CLASS_HID_2243b,
+ [1510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40746,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27917560832UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [901] = {
- .class_hid = BNXT_ULP_CLASS_HID_290fb,
+ [1511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5068a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27918601216UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [902] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c153,
+ [1512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_516d6,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27918609408UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [903] = {
- .class_hid = BNXT_ULP_CLASS_HID_24113,
+ [1513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f42,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27919649792UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [904] = {
- .class_hid = BNXT_ULP_CLASS_HID_2739b,
+ [1514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e8e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27919657984UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [905] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fe5b,
+ [1515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59ed2,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27920698368UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [906] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d033,
+ [1516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d9c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27920706560UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [907] = {
- .class_hid = BNXT_ULP_CLASS_HID_256c3,
+ [1517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41a4a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30065036288UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [908] = {
- .class_hid = BNXT_ULP_CLASS_HID_21003,
+ [1518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40924,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30065044480UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [909] = {
- .class_hid = BNXT_ULP_CLASS_HID_29cc3,
+ [1519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50968,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30066084864UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [910] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ceb3,
+ [1520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51944,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30066093056UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [911] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d63,
+ [1521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49182,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30067133440UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [912] = {
- .class_hid = BNXT_ULP_CLASS_HID_27fe3,
+ [1522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4816c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30067141632UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [913] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eba3,
+ [1523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58140,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30068182016UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [914] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dc13,
+ [1524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5908c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30068190208UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [915] = {
- .class_hid = BNXT_ULP_CLASS_HID_20653,
+ [1525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c8c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32212519936UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [916] = {
- .class_hid = BNXT_ULP_CLASS_HID_238d3,
+ [1526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41cc8,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32212528128UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [917] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a493,
+ [1527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51c0c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32213568512UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [918] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d573,
+ [1528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50386,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32213576704UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [919] = {
- .class_hid = BNXT_ULP_CLASS_HID_25533,
+ [1529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_484c4,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32214617088UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [920] = {
- .class_hid = BNXT_ULP_CLASS_HID_247b3,
+ [1530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b8e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32214625280UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [921] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f273,
+ [1531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b82,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32215665664UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [922] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cdb3,
+ [1532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59bce,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32215673856UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [923] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c7d,
+ [1533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a54,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 265216UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21036,14 +35811,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI }
},
- [924] = {
- .class_hid = BNXT_ULP_CLASS_HID_21239,
+ [1534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e74,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 273408UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21056,15 +35831,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI }
},
- [925] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ff35,
+ [1535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e48,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 1313792UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21077,15 +35852,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC }
},
- [926] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b4f1,
+ [1536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15268,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 1321984UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21098,16 +35873,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC }
},
- [927] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d91,
+ [1537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1285a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2362368UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21120,15 +35895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [928] = {
- .class_hid = BNXT_ULP_CLASS_HID_2435d,
+ [1538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13c7a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2370560UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21141,16 +35916,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [929] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d79d,
+ [1539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_163be,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 3410944UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21163,16 +35938,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [930] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e615,
+ [1540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705e,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 3419136UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21185,17 +35960,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [931] = {
- .class_hid = BNXT_ULP_CLASS_HID_244ad,
+ [1541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d5e,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2147748864UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21208,15 +35983,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [932] = {
- .class_hid = BNXT_ULP_CLASS_HID_23a69,
+ [1542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1009c,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2147757056UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21229,16 +36004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [933] = {
- .class_hid = BNXT_ULP_CLASS_HID_28ea9,
+ [1543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150ba,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2148797440UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21251,16 +36026,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [934] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd21,
+ [1544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_144f8,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2148805632UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21273,17 +36048,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [935] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d05,
+ [1545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1334c,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2149846016UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21296,16 +36071,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [936] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b8d,
+ [1546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1268a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2149854208UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21318,17 +36093,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [937] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ffcd,
+ [1547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176a8,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2150894592UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21341,17 +36116,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [938] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce45,
+ [1548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17aee,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2150902784UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21364,18 +36139,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [939] = {
- .class_hid = BNXT_ULP_CLASS_HID_2485d,
+ [1549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11782,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4295232512UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21388,15 +36163,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [940] = {
- .class_hid = BNXT_ULP_CLASS_HID_20e19,
+ [1550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bc0,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4295240704UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21409,16 +36184,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [941] = {
- .class_hid = BNXT_ULP_CLASS_HID_29259,
+ [1551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14b00,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4296281088UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21431,16 +36206,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [942] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a0d9,
+ [1552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f20,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4296289280UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21453,17 +36228,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [943] = {
- .class_hid = BNXT_ULP_CLASS_HID_279f9,
+ [1553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135f0,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4297329664UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21476,16 +36251,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [944] = {
- .class_hid = BNXT_ULP_CLASS_HID_27fbd,
+ [1554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13932,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4297337856UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21498,17 +36273,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [945] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c3fd,
+ [1555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1690a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4298378240UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21521,17 +36296,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [946] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d27d,
+ [1556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17d2a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4298386432UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21544,18 +36319,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [947] = {
- .class_hid = BNXT_ULP_CLASS_HID_2708d,
+ [1557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11a2a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6442716160UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21568,16 +36343,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [948] = {
- .class_hid = BNXT_ULP_CLASS_HID_23649,
+ [1558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e68,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6442724352UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21590,17 +36365,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [949] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba89,
+ [1559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e0a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6443764736UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21613,17 +36388,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [950] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c909,
+ [1560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14248,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6443772928UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21636,18 +36411,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [951] = {
- .class_hid = BNXT_ULP_CLASS_HID_2496d,
+ [1561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13818,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6444813312UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21660,17 +36435,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [952] = {
- .class_hid = BNXT_ULP_CLASS_HID_267ed,
+ [1562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12c5a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6444821504UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21683,18 +36458,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [953] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ec2d,
+ [1563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c78,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6445861888UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21707,18 +36482,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [954] = {
- .class_hid = BNXT_ULP_CLASS_HID_2faad,
+ [1564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167ba,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6445870080UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21731,17 +36506,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [955] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ [1565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f91,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -21755,8 +36530,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [956] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c22,
+ [1566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0763,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100UL,
@@ -21771,8 +36546,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [957] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cbe,
+ [1567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f7b,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -21787,8 +36562,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [958] = {
- .class_hid = BNXT_ULP_CLASS_HID_179a,
+ [1568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16af,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148UL,
@@ -21804,8 +36579,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [959] = {
- .class_hid = BNXT_ULP_CLASS_HID_59be,
+ [1569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1daf,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -21819,8 +36594,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [960] = {
- .class_hid = BNXT_ULP_CLASS_HID_515a,
+ [1570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0539,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388UL,
@@ -21835,8 +36610,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [961] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c72,
+ [1571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_01ed,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -21851,8 +36626,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [962] = {
- .class_hid = BNXT_ULP_CLASS_HID_171e,
+ [1572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_097f,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580UL,
@@ -21868,8 +36643,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [963] = {
- .class_hid = BNXT_ULP_CLASS_HID_19c8,
+ [1573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81ab8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -21884,8 +36659,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [964] = {
- .class_hid = BNXT_ULP_CLASS_HID_112c,
+ [1574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8020e,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772UL,
@@ -21901,8 +36676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [965] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d68,
+ [1575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815d8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -21918,8 +36693,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [966] = {
- .class_hid = BNXT_ULP_CLASS_HID_444c,
+ [1576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cae,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836UL,
@@ -21936,8 +36711,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [967] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e8c,
+ [1577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810a8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -21953,8 +36728,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [968] = {
- .class_hid = BNXT_ULP_CLASS_HID_09e0,
+ [1578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8183e,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156UL,
@@ -21971,8 +36746,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [969] = {
- .class_hid = BNXT_ULP_CLASS_HID_1af0,
+ [1579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8036a,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -21989,8 +36764,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [970] = {
- .class_hid = BNXT_ULP_CLASS_HID_15d4,
+ [1580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80af8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220UL,
@@ -22008,8 +36783,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [971] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dd0,
+ [1581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_206fe,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -22024,8 +36799,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [972] = {
- .class_hid = BNXT_ULP_CLASS_HID_14f4,
+ [1582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e4c,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076UL,
@@ -22041,8 +36816,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [973] = {
- .class_hid = BNXT_ULP_CLASS_HID_70b0,
+ [1583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2111e,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -22058,8 +36833,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [974] = {
- .class_hid = BNXT_ULP_CLASS_HID_4854,
+ [1584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218ec,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140UL,
@@ -22076,8 +36851,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [975] = {
- .class_hid = BNXT_ULP_CLASS_HID_3dd4,
+ [1585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60472,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -22093,8 +36868,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [976] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f8,
+ [1586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603c0,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612UL,
@@ -22111,8 +36886,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [977] = {
- .class_hid = BNXT_ULP_CLASS_HID_09e8,
+ [1587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61692,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -22129,8 +36904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [978] = {
- .class_hid = BNXT_ULP_CLASS_HID_008c,
+ [1588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e60,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676UL,
@@ -22148,8 +36923,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [979] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e6,
+ [1589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f81,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -22164,8 +36939,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [980] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c02,
+ [1590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0773,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100UL,
@@ -22181,8 +36956,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [981] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c9e,
+ [1591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f6b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -22198,8 +36973,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [982] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ba,
+ [1592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bf,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148UL,
@@ -22216,8 +36991,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [983] = {
- .class_hid = BNXT_ULP_CLASS_HID_429e,
+ [1593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03cf,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -22233,8 +37008,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [984] = {
- .class_hid = BNXT_ULP_CLASS_HID_5dba,
+ [1594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ab1,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292UL,
@@ -22251,8 +37026,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [985] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a16,
+ [1595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_130b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -22269,8 +37044,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [986] = {
- .class_hid = BNXT_ULP_CLASS_HID_2532,
+ [1596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1afd,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340UL,
@@ -22288,8 +37063,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [987] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da2,
+ [1597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1591,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -22305,8 +37080,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [988] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fe,
+ [1598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d03,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484UL,
@@ -22323,8 +37098,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [989] = {
- .class_hid = BNXT_ULP_CLASS_HID_355a,
+ [1599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_057b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -22341,8 +37116,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [990] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c76,
+ [1600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ced,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532UL,
@@ -22360,8 +37135,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [991] = {
- .class_hid = BNXT_ULP_CLASS_HID_13e6,
+ [1601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19df,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -22378,8 +37153,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [992] = {
- .class_hid = BNXT_ULP_CLASS_HID_7276,
+ [1602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0141,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676UL,
@@ -22397,8 +37172,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [993] = {
- .class_hid = BNXT_ULP_CLASS_HID_42d2,
+ [1603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_08b9,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -22416,8 +37191,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [994] = {
- .class_hid = BNXT_ULP_CLASS_HID_5dee,
+ [1604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_108d,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724UL,
@@ -22436,8 +37211,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [995] = {
- .class_hid = BNXT_ULP_CLASS_HID_59de,
+ [1605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dbf,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -22452,8 +37227,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [996] = {
- .class_hid = BNXT_ULP_CLASS_HID_513a,
+ [1606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0529,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388UL,
@@ -22469,8 +37244,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [997] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c12,
+ [1607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_01fd,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -22486,8 +37261,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [998] = {
- .class_hid = BNXT_ULP_CLASS_HID_177e,
+ [1608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_096f,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580UL,
@@ -22504,8 +37279,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [999] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e92,
+ [1609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810b7,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -22521,8 +37296,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1000] = {
- .class_hid = BNXT_ULP_CLASS_HID_09fe,
+ [1610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81821,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156UL,
@@ -22539,8 +37314,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1001] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c1a,
+ [1611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_804f5,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -22557,8 +37332,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1002] = {
- .class_hid = BNXT_ULP_CLASS_HID_5746,
+ [1612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80c67,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348UL,
@@ -22576,8 +37351,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1003] = {
- .class_hid = BNXT_ULP_CLASS_HID_79da,
+ [1613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41333,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -22593,8 +37368,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1004] = {
- .class_hid = BNXT_ULP_CLASS_HID_7106,
+ [1614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41aad,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924UL,
@@ -22611,8 +37386,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1005] = {
- .class_hid = BNXT_ULP_CLASS_HID_3c1e,
+ [1615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40771,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -22629,8 +37404,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1006] = {
- .class_hid = BNXT_ULP_CLASS_HID_377a,
+ [1616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40ee3,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116UL,
@@ -22648,8 +37423,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1007] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e9e,
+ [1617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16cb,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -22666,8 +37441,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1008] = {
- .class_hid = BNXT_ULP_CLASS_HID_29fa,
+ [1618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1da5,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692UL,
@@ -22685,8 +37460,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1009] = {
- .class_hid = BNXT_ULP_CLASS_HID_14d2,
+ [1619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1a09,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -22704,8 +37479,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1010] = {
- .class_hid = BNXT_ULP_CLASS_HID_7742,
+ [1620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c01fb,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884UL,
@@ -22724,8 +37499,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1011] = {
- .class_hid = BNXT_ULP_CLASS_HID_3706,
+ [1621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ff1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -22740,8 +37515,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1012] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fe2,
+ [1622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0703,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100UL,
@@ -22757,8 +37532,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1013] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f7e,
+ [1623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f1b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -22774,8 +37549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1014] = {
- .class_hid = BNXT_ULP_CLASS_HID_145a,
+ [1624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16cf,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148UL,
@@ -22792,8 +37567,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1015] = {
- .class_hid = BNXT_ULP_CLASS_HID_417e,
+ [1625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03bf,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -22809,8 +37584,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1016] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e5a,
+ [1626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ac1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292UL,
@@ -22827,8 +37602,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1017] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f6,
+ [1627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -22845,8 +37620,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1018] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d2,
+ [1628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a8d,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340UL,
@@ -22864,8 +37639,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1019] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e42,
+ [1629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -22881,8 +37656,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1020] = {
- .class_hid = BNXT_ULP_CLASS_HID_271e,
+ [1630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d73,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484UL,
@@ -22899,8 +37674,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1021] = {
- .class_hid = BNXT_ULP_CLASS_HID_36ba,
+ [1631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_050b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -22917,8 +37692,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1022] = {
- .class_hid = BNXT_ULP_CLASS_HID_0f96,
+ [1632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c9d,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532UL,
@@ -22936,8 +37711,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1023] = {
- .class_hid = BNXT_ULP_CLASS_HID_1006,
+ [1633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19af,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -22954,8 +37729,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1024] = {
- .class_hid = BNXT_ULP_CLASS_HID_7196,
+ [1634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0131,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676UL,
@@ -22973,8 +37748,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1025] = {
- .class_hid = BNXT_ULP_CLASS_HID_4132,
+ [1635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_08c9,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -22992,8 +37767,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1026] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e0e,
+ [1636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10fd,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724UL,
@@ -23012,8 +37787,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1027] = {
- .class_hid = BNXT_ULP_CLASS_HID_59fe,
+ [1637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dcf,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -23028,8 +37803,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1028] = {
- .class_hid = BNXT_ULP_CLASS_HID_511a,
+ [1638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0559,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388UL,
@@ -23045,8 +37820,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1029] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c32,
+ [1639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_018d,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -23062,8 +37837,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1030] = {
- .class_hid = BNXT_ULP_CLASS_HID_175e,
+ [1640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_091f,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580UL,
@@ -23080,8 +37855,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1031] = {
- .class_hid = BNXT_ULP_CLASS_HID_0eb2,
+ [1641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810c7,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -23097,8 +37872,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1032] = {
- .class_hid = BNXT_ULP_CLASS_HID_09de,
+ [1642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81851,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156UL,
@@ -23115,8 +37890,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1033] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c3a,
+ [1643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80485,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -23133,8 +37908,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1034] = {
- .class_hid = BNXT_ULP_CLASS_HID_5766,
+ [1644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80c17,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348UL,
@@ -23152,8 +37927,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1035] = {
- .class_hid = BNXT_ULP_CLASS_HID_79fa,
+ [1645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41343,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -23169,8 +37944,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1036] = {
- .class_hid = BNXT_ULP_CLASS_HID_7126,
+ [1646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41add,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924UL,
@@ -23187,8 +37962,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1037] = {
- .class_hid = BNXT_ULP_CLASS_HID_3c3e,
+ [1647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40701,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -23205,8 +37980,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1038] = {
- .class_hid = BNXT_ULP_CLASS_HID_375a,
+ [1648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40e93,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116UL,
@@ -23224,8 +37999,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1039] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ebe,
+ [1649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16bb,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -23242,8 +38017,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1040] = {
- .class_hid = BNXT_ULP_CLASS_HID_29da,
+ [1650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1dd5,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692UL,
@@ -23261,8 +38036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1041] = {
- .class_hid = BNXT_ULP_CLASS_HID_14f2,
+ [1651] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1a79,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -23280,8 +38055,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1042] = {
- .class_hid = BNXT_ULP_CLASS_HID_7762,
+ [1652] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c018b,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884UL,
@@ -23300,8 +38075,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1043] = {
- .class_hid = BNXT_ULP_CLASS_HID_19e8,
+ [1653] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81aa8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -23317,8 +38092,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1044] = {
- .class_hid = BNXT_ULP_CLASS_HID_110c,
+ [1654] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8021e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772UL,
@@ -23335,8 +38110,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1045] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d48,
+ [1655] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815c8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -23353,8 +38128,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1046] = {
- .class_hid = BNXT_ULP_CLASS_HID_446c,
+ [1656] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cbe,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836UL,
@@ -23372,8 +38147,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1047] = {
- .class_hid = BNXT_ULP_CLASS_HID_0eac,
+ [1657] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810b8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -23390,8 +38165,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1048] = {
- .class_hid = BNXT_ULP_CLASS_HID_09c0,
+ [1658] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8182e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156UL,
@@ -23409,8 +38184,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1049] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ad0,
+ [1659] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8037a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -23428,8 +38203,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1050] = {
- .class_hid = BNXT_ULP_CLASS_HID_15f4,
+ [1660] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80ae8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220UL,
@@ -23448,8 +38223,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1051] = {
- .class_hid = BNXT_ULP_CLASS_HID_39ec,
+ [1661] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1834,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -23466,8 +38241,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1052] = {
- .class_hid = BNXT_ULP_CLASS_HID_3100,
+ [1662] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c079a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308UL,
@@ -23485,8 +38260,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1053] = {
- .class_hid = BNXT_ULP_CLASS_HID_0210,
+ [1663] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0af6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -23504,8 +38279,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1054] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d34,
+ [1664] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c123a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372UL,
@@ -23524,8 +38299,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1055] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ea0,
+ [1665] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16c4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -23543,8 +38318,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1056] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c4,
+ [1666] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1daa,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692UL,
@@ -23563,8 +38338,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1057] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ad4,
+ [1667] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0086,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -23583,8 +38358,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1058] = {
- .class_hid = BNXT_ULP_CLASS_HID_35e8,
+ [1668] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0874,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756UL,
@@ -23604,8 +38379,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1059] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d80,
+ [1669] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a19ea,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -23622,8 +38397,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1060] = {
- .class_hid = BNXT_ULP_CLASS_HID_54a4,
+ [1670] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0158,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844UL,
@@ -23641,8 +38416,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1061] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b4,
+ [1671] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0bb4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -23660,8 +38435,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1062] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c8,
+ [1672] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a13f8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908UL,
@@ -23680,8 +38455,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1063] = {
- .class_hid = BNXT_ULP_CLASS_HID_7244,
+ [1673] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a17fa,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -23699,8 +38474,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1064] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d98,
+ [1674] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1f68,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228UL,
@@ -23719,8 +38494,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1065] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e68,
+ [1675] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0244,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -23739,8 +38514,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1066] = {
- .class_hid = BNXT_ULP_CLASS_HID_598c,
+ [1676] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a092a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292UL,
@@ -23760,8 +38535,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1067] = {
- .class_hid = BNXT_ULP_CLASS_HID_1248,
+ [1677] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1f76,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -23779,8 +38554,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1068] = {
- .class_hid = BNXT_ULP_CLASS_HID_74d8,
+ [1678] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e06e4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380UL,
@@ -23799,8 +38574,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1069] = {
- .class_hid = BNXT_ULP_CLASS_HID_49a8,
+ [1679] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0930,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -23819,8 +38594,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1070] = {
- .class_hid = BNXT_ULP_CLASS_HID_40cc,
+ [1680] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1104,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444UL,
@@ -23840,8 +38615,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1071] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b0c,
+ [1681] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1506,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -23860,8 +38635,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1072] = {
- .class_hid = BNXT_ULP_CLASS_HID_0220,
+ [1682] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1cf4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764UL,
@@ -23881,8 +38656,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1073] = {
- .class_hid = BNXT_ULP_CLASS_HID_1730,
+ [1683] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e07c0,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -23902,8 +38677,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1074] = {
- .class_hid = BNXT_ULP_CLASS_HID_7980,
+ [1684] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0eb6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828UL,
@@ -23924,8 +38699,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1075] = {
- .class_hid = BNXT_ULP_CLASS_HID_1db0,
+ [1685] = {
+ .class_hid = BNXT_ULP_CLASS_HID_206ee,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -23941,8 +38716,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1076] = {
- .class_hid = BNXT_ULP_CLASS_HID_1494,
+ [1686] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e5c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076UL,
@@ -23959,8 +38734,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1077] = {
- .class_hid = BNXT_ULP_CLASS_HID_70d0,
+ [1687] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2110e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -23977,8 +38752,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1078] = {
- .class_hid = BNXT_ULP_CLASS_HID_4834,
+ [1688] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218fc,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140UL,
@@ -23996,8 +38771,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1079] = {
- .class_hid = BNXT_ULP_CLASS_HID_3db4,
+ [1689] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60462,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -24014,8 +38789,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1080] = {
- .class_hid = BNXT_ULP_CLASS_HID_3498,
+ [1690] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603d0,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612UL,
@@ -24033,8 +38808,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1081] = {
- .class_hid = BNXT_ULP_CLASS_HID_0988,
+ [1691] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61682,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -24052,8 +38827,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1082] = {
- .class_hid = BNXT_ULP_CLASS_HID_00ec,
+ [1692] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e70,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676UL,
@@ -24072,8 +38847,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1083] = {
- .class_hid = BNXT_ULP_CLASS_HID_23f44,
+ [1693] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3167e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -24090,8 +38865,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1084] = {
- .class_hid = BNXT_ULP_CLASS_HID_236a8,
+ [1694] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31dec,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220UL,
@@ -24109,8 +38884,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1085] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b58,
+ [1695] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30030,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -24128,8 +38903,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1086] = {
- .class_hid = BNXT_ULP_CLASS_HID_202bc,
+ [1696] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30fae,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284UL,
@@ -24148,8 +38923,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1087] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f48,
+ [1697] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70b14,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -24167,8 +38942,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1088] = {
- .class_hid = BNXT_ULP_CLASS_HID_256ac,
+ [1698] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71360,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756UL,
@@ -24187,8 +38962,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1089] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5c,
+ [1699] = {
+ .class_hid = BNXT_ULP_CLASS_HID_705b4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -24207,8 +38982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1090] = {
- .class_hid = BNXT_ULP_CLASS_HID_22280,
+ [1700] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70d22,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820UL,
@@ -24228,8 +39003,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1091] = {
- .class_hid = BNXT_ULP_CLASS_HID_14000,
+ [1701] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29e26,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -24246,8 +39021,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1092] = {
- .class_hid = BNXT_ULP_CLASS_HID_15b64,
+ [1702] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28594,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364UL,
@@ -24265,8 +39040,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1093] = {
- .class_hid = BNXT_ULP_CLASS_HID_12c14,
+ [1703] = {
+ .class_hid = BNXT_ULP_CLASS_HID_288f8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -24284,8 +39059,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1094] = {
- .class_hid = BNXT_ULP_CLASS_HID_12778,
+ [1704] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29034,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428UL,
@@ -24304,8 +39079,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1095] = {
- .class_hid = BNXT_ULP_CLASS_HID_118f8,
+ [1705] = {
+ .class_hid = BNXT_ULP_CLASS_HID_693ba,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -24323,8 +39098,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1096] = {
- .class_hid = BNXT_ULP_CLASS_HID_113dc,
+ [1706] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69b28,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900UL,
@@ -24343,8 +39118,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1097] = {
- .class_hid = BNXT_ULP_CLASS_HID_14c18,
+ [1707] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68e7c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -24363,8 +39138,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1098] = {
- .class_hid = BNXT_ULP_CLASS_HID_1477c,
+ [1708] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69648,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964UL,
@@ -24384,8 +39159,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1099] = {
- .class_hid = BNXT_ULP_CLASS_HID_31a88,
+ [1709] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38de8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -24403,8 +39178,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1100] = {
- .class_hid = BNXT_ULP_CLASS_HID_315ec,
+ [1710] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39524,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508UL,
@@ -24423,8 +39198,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1101] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e28,
+ [1711] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39808,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -24443,8 +39218,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1102] = {
- .class_hid = BNXT_ULP_CLASS_HID_3490c,
+ [1712] = {
+ .class_hid = BNXT_ULP_CLASS_HID_387e6,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572UL,
@@ -24464,8 +39239,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1103] = {
- .class_hid = BNXT_ULP_CLASS_HID_33a8c,
+ [1713] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7836c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -24484,8 +39259,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1104] = {
- .class_hid = BNXT_ULP_CLASS_HID_335f0,
+ [1714] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78ada,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044UL,
@@ -24505,8 +39280,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1105] = {
- .class_hid = BNXT_ULP_CLASS_HID_306e0,
+ [1715] = {
+ .class_hid = BNXT_ULP_CLASS_HID_79d8c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -24526,8 +39301,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1106] = {
- .class_hid = BNXT_ULP_CLASS_HID_301c4,
+ [1716] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7857a,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108UL,
@@ -24548,8 +39323,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1107] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a08,
+ [1717] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81ad8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -24565,8 +39340,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1108] = {
- .class_hid = BNXT_ULP_CLASS_HID_12ec,
+ [1718] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8026e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772UL,
@@ -24583,8 +39358,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1109] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea8,
+ [1719] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815b8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -24601,8 +39376,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1110] = {
- .class_hid = BNXT_ULP_CLASS_HID_478c,
+ [1720] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cce,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836UL,
@@ -24620,8 +39395,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1111] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d4c,
+ [1721] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810c8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -24638,8 +39413,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1112] = {
- .class_hid = BNXT_ULP_CLASS_HID_0a20,
+ [1722] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8185e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156UL,
@@ -24657,8 +39432,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1113] = {
- .class_hid = BNXT_ULP_CLASS_HID_1930,
+ [1723] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8030a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -24676,8 +39451,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1114] = {
- .class_hid = BNXT_ULP_CLASS_HID_1614,
+ [1724] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80a98,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220UL,
@@ -24696,8 +39471,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1115] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a0c,
+ [1725] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1844,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -24714,8 +39489,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1116] = {
- .class_hid = BNXT_ULP_CLASS_HID_32e0,
+ [1726] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c07ea,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308UL,
@@ -24733,8 +39508,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1117] = {
- .class_hid = BNXT_ULP_CLASS_HID_01f0,
+ [1727] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0a86,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -24752,8 +39527,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1118] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ed4,
+ [1728] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c124a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372UL,
@@ -24772,8 +39547,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1119] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d40,
+ [1729] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16b4,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -24791,8 +39566,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1120] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a24,
+ [1730] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1dda,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692UL,
@@ -24811,8 +39586,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1121] = {
- .class_hid = BNXT_ULP_CLASS_HID_3934,
+ [1731] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c00f6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -24831,8 +39606,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1122] = {
- .class_hid = BNXT_ULP_CLASS_HID_3608,
+ [1732] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0804,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756UL,
@@ -24852,8 +39627,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1123] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e60,
+ [1733] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a199a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -24870,8 +39645,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1124] = {
- .class_hid = BNXT_ULP_CLASS_HID_5744,
+ [1734] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0128,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844UL,
@@ -24889,8 +39664,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1125] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a54,
+ [1735] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0bc4,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -24908,8 +39683,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1126] = {
- .class_hid = BNXT_ULP_CLASS_HID_2328,
+ [1736] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1388,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908UL,
@@ -24928,8 +39703,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1127] = {
- .class_hid = BNXT_ULP_CLASS_HID_71a4,
+ [1737] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a178a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -24947,8 +39722,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1128] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e78,
+ [1738] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1f18,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228UL,
@@ -24967,8 +39742,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1129] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d88,
+ [1739] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0234,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -24987,8 +39762,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1130] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a6c,
+ [1740] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a095a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292UL,
@@ -25008,8 +39783,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1131] = {
- .class_hid = BNXT_ULP_CLASS_HID_11a8,
+ [1741] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1f06,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -25027,8 +39802,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1132] = {
- .class_hid = BNXT_ULP_CLASS_HID_7738,
+ [1742] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0694,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380UL,
@@ -25047,8 +39822,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1133] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a48,
+ [1743] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0940,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -25067,8 +39842,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1134] = {
- .class_hid = BNXT_ULP_CLASS_HID_432c,
+ [1744] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1174,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444UL,
@@ -25088,8 +39863,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1135] = {
- .class_hid = BNXT_ULP_CLASS_HID_08ec,
+ [1745] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1576,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -25108,8 +39883,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1136] = {
- .class_hid = BNXT_ULP_CLASS_HID_01c0,
+ [1746] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1c84,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764UL,
@@ -25129,8 +39904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1137] = {
- .class_hid = BNXT_ULP_CLASS_HID_14d0,
+ [1747] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e07b0,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -25150,8 +39925,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1138] = {
- .class_hid = BNXT_ULP_CLASS_HID_7a60,
+ [1748] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0ec6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828UL,
@@ -25172,8 +39947,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1139] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d90,
+ [1749] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2069e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -25189,8 +39964,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1140] = {
- .class_hid = BNXT_ULP_CLASS_HID_14b4,
+ [1750] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e2c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076UL,
@@ -25207,8 +39982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1141] = {
- .class_hid = BNXT_ULP_CLASS_HID_70f0,
+ [1751] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2117e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -25225,8 +40000,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1142] = {
- .class_hid = BNXT_ULP_CLASS_HID_4814,
+ [1752] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2188c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140UL,
@@ -25244,8 +40019,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1143] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d94,
+ [1753] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60412,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -25262,8 +40037,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1144] = {
- .class_hid = BNXT_ULP_CLASS_HID_34b8,
+ [1754] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603a0,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612UL,
@@ -25281,8 +40056,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1145] = {
- .class_hid = BNXT_ULP_CLASS_HID_09a8,
+ [1755] = {
+ .class_hid = BNXT_ULP_CLASS_HID_616f2,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -25300,8 +40075,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1146] = {
- .class_hid = BNXT_ULP_CLASS_HID_00cc,
+ [1756] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e00,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676UL,
@@ -25320,8 +40095,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1147] = {
- .class_hid = BNXT_ULP_CLASS_HID_23f64,
+ [1757] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3160e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -25338,8 +40113,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1148] = {
- .class_hid = BNXT_ULP_CLASS_HID_23688,
+ [1758] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31d9c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220UL,
@@ -25357,8 +40132,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1149] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b78,
+ [1759] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30040,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -25376,8 +40151,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1150] = {
- .class_hid = BNXT_ULP_CLASS_HID_2029c,
+ [1760] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30fde,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284UL,
@@ -25396,8 +40171,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1151] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f68,
+ [1761] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70b64,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -25415,8 +40190,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1152] = {
- .class_hid = BNXT_ULP_CLASS_HID_2568c,
+ [1762] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71310,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756UL,
@@ -25435,8 +40210,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1153] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b7c,
+ [1763] = {
+ .class_hid = BNXT_ULP_CLASS_HID_705c4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -25455,8 +40230,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1154] = {
- .class_hid = BNXT_ULP_CLASS_HID_222a0,
+ [1764] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70d52,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820UL,
@@ -25476,8 +40251,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1155] = {
- .class_hid = BNXT_ULP_CLASS_HID_14020,
+ [1765] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29e56,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -25494,8 +40269,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1156] = {
- .class_hid = BNXT_ULP_CLASS_HID_15b44,
+ [1766] = {
+ .class_hid = BNXT_ULP_CLASS_HID_285e4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364UL,
@@ -25513,8 +40288,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1157] = {
- .class_hid = BNXT_ULP_CLASS_HID_12c34,
+ [1767] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28888,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -25532,8 +40307,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1158] = {
- .class_hid = BNXT_ULP_CLASS_HID_12758,
+ [1768] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29044,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428UL,
@@ -25552,8 +40327,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1159] = {
- .class_hid = BNXT_ULP_CLASS_HID_118d8,
+ [1769] = {
+ .class_hid = BNXT_ULP_CLASS_HID_693ca,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -25571,8 +40346,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1160] = {
- .class_hid = BNXT_ULP_CLASS_HID_113fc,
+ [1770] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69b58,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900UL,
@@ -25591,8 +40366,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1161] = {
- .class_hid = BNXT_ULP_CLASS_HID_14c38,
+ [1771] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68e0c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -25611,8 +40386,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1162] = {
- .class_hid = BNXT_ULP_CLASS_HID_1475c,
+ [1772] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69638,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964UL,
@@ -25632,8 +40407,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1163] = {
- .class_hid = BNXT_ULP_CLASS_HID_31aa8,
+ [1773] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38d98,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -25651,8 +40426,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1164] = {
- .class_hid = BNXT_ULP_CLASS_HID_315cc,
+ [1774] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39554,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508UL,
@@ -25671,8 +40446,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1165] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e08,
+ [1775] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39878,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -25691,8 +40466,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1166] = {
- .class_hid = BNXT_ULP_CLASS_HID_3492c,
+ [1776] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38796,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572UL,
@@ -25712,8 +40487,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1167] = {
- .class_hid = BNXT_ULP_CLASS_HID_33aac,
+ [1777] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7831c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -25732,8 +40507,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1168] = {
- .class_hid = BNXT_ULP_CLASS_HID_335d0,
+ [1778] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78aaa,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044UL,
@@ -25753,8 +40528,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1169] = {
- .class_hid = BNXT_ULP_CLASS_HID_306c0,
+ [1779] = {
+ .class_hid = BNXT_ULP_CLASS_HID_79dfc,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -25774,8 +40549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1170] = {
- .class_hid = BNXT_ULP_CLASS_HID_301e4,
+ [1780] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7850a,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108UL,
@@ -25796,8 +40571,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1171] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d32,
+ [1781] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03b7,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -25810,8 +40585,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [1172] = {
- .class_hid = BNXT_ULP_CLASS_HID_54aa,
+ [1782] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f3,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -25825,8 +40600,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [1173] = {
- .class_hid = BNXT_ULP_CLASS_HID_0686,
+ [1783] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0255,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -25839,8 +40614,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [1174] = {
- .class_hid = BNXT_ULP_CLASS_HID_540e,
+ [1784] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1675,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -25854,8 +40629,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [1175] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e3c,
+ [1785] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f52,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -25869,8 +40644,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1176] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a20,
+ [1786] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819f2,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -25885,8 +40660,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1177] = {
- .class_hid = BNXT_ULP_CLASS_HID_46f0,
+ [1787] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80542,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -25901,8 +40676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1178] = {
- .class_hid = BNXT_ULP_CLASS_HID_52e4,
+ [1788] = {
+ .class_hid = BNXT_ULP_CLASS_HID_817e2,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -25918,8 +40693,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1179] = {
- .class_hid = BNXT_ULP_CLASS_HID_55e4,
+ [1789] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a98,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -25933,8 +40708,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1180] = {
- .class_hid = BNXT_ULP_CLASS_HID_21f8,
+ [1790] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20538,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -25949,8 +40724,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1181] = {
- .class_hid = BNXT_ULP_CLASS_HID_75e8,
+ [1791] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6081c,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -25965,8 +40740,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1182] = {
- .class_hid = BNXT_ULP_CLASS_HID_41fc,
+ [1792] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61abc,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -25982,8 +40757,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1183] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d12,
+ [1793] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03a7,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -25997,8 +40772,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [1184] = {
- .class_hid = BNXT_ULP_CLASS_HID_548a,
+ [1794] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13e3,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -26013,8 +40788,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [1185] = {
- .class_hid = BNXT_ULP_CLASS_HID_3356,
+ [1795] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1047,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -26029,8 +40804,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [1186] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ace,
+ [1796] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0721,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -26046,8 +40821,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [1187] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a9a,
+ [1797] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19b7,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -26062,8 +40837,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1188] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d46,
+ [1798] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0911,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -26079,8 +40854,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1189] = {
- .class_hid = BNXT_ULP_CLASS_HID_2812,
+ [1799] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0df5,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -26096,8 +40871,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1190] = {
- .class_hid = BNXT_ULP_CLASS_HID_338a,
+ [1800] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d31,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -26114,8 +40889,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1191] = {
- .class_hid = BNXT_ULP_CLASS_HID_06e6,
+ [1801] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0245,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -26129,8 +40904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [1192] = {
- .class_hid = BNXT_ULP_CLASS_HID_546e,
+ [1802] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1665,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -26145,8 +40920,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [1193] = {
- .class_hid = BNXT_ULP_CLASS_HID_46ee,
+ [1803] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8055d,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -26161,8 +40936,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1194] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d22,
+ [1804] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80893,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -26178,8 +40953,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1195] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e2,
+ [1805] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407d9,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -26194,8 +40969,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1196] = {
- .class_hid = BNXT_ULP_CLASS_HID_746a,
+ [1806] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b1f,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -26211,8 +40986,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1197] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fa6,
+ [1807] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1ad1,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -26228,8 +41003,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1198] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d2e,
+ [1808] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e17,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -26246,8 +41021,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1199] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ef2,
+ [1809] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03d7,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -26261,8 +41036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1200] = {
- .class_hid = BNXT_ULP_CLASS_HID_576a,
+ [1810] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1393,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -26277,8 +41052,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1201] = {
- .class_hid = BNXT_ULP_CLASS_HID_30b6,
+ [1811] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1037,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -26293,8 +41068,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1202] = {
- .class_hid = BNXT_ULP_CLASS_HID_192e,
+ [1812] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0751,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -26310,8 +41085,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1203] = {
- .class_hid = BNXT_ULP_CLASS_HID_197a,
+ [1813] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19c7,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -26326,8 +41101,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1204] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea6,
+ [1814] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0961,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -26343,8 +41118,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1205] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf2,
+ [1815] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0d85,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -26360,8 +41135,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1206] = {
- .class_hid = BNXT_ULP_CLASS_HID_306a,
+ [1816] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d41,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -26378,8 +41153,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1207] = {
- .class_hid = BNXT_ULP_CLASS_HID_06c6,
+ [1817] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0235,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -26393,8 +41168,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1208] = {
- .class_hid = BNXT_ULP_CLASS_HID_544e,
+ [1818] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1615,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -26409,8 +41184,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1209] = {
- .class_hid = BNXT_ULP_CLASS_HID_46ce,
+ [1819] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8052d,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -26425,8 +41200,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1210] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d02,
+ [1820] = {
+ .class_hid = BNXT_ULP_CLASS_HID_808e3,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -26442,8 +41217,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1211] = {
- .class_hid = BNXT_ULP_CLASS_HID_26c2,
+ [1821] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407a9,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -26458,8 +41233,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1212] = {
- .class_hid = BNXT_ULP_CLASS_HID_744a,
+ [1822] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b6f,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -26475,8 +41250,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1213] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f86,
+ [1823] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1aa1,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -26492,8 +41267,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1214] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d0e,
+ [1824] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e67,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -26510,8 +41285,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1215] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e1c,
+ [1825] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f42,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -26526,8 +41301,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1216] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a00,
+ [1826] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819e2,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -26543,8 +41318,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1217] = {
- .class_hid = BNXT_ULP_CLASS_HID_46d0,
+ [1827] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80552,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -26560,8 +41335,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1218] = {
- .class_hid = BNXT_ULP_CLASS_HID_52c4,
+ [1828] = {
+ .class_hid = BNXT_ULP_CLASS_HID_817f2,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -26578,8 +41353,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1219] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e10,
+ [1829] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0cce,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -26595,8 +41370,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1220] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a04,
+ [1830] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1f6e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -26613,8 +41388,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1221] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f98,
+ [1831] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1ade,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -26631,8 +41406,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1222] = {
- .class_hid = BNXT_ULP_CLASS_HID_72f8,
+ [1832] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c157e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -26650,8 +41425,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1223] = {
- .class_hid = BNXT_ULP_CLASS_HID_0a78,
+ [1833] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d8c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -26667,8 +41442,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1224] = {
- .class_hid = BNXT_ULP_CLASS_HID_166c,
+ [1834] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a182c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -26685,8 +41460,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1225] = {
- .class_hid = BNXT_ULP_CLASS_HID_233c,
+ [1835] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1b9c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -26703,8 +41478,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1226] = {
- .class_hid = BNXT_ULP_CLASS_HID_0f20,
+ [1836] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a163c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -26722,8 +41497,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1227] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a7c,
+ [1837] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0308,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -26740,8 +41515,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1228] = {
- .class_hid = BNXT_ULP_CLASS_HID_3660,
+ [1838] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1da8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -26759,8 +41534,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1229] = {
- .class_hid = BNXT_ULP_CLASS_HID_4330,
+ [1839] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1918,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -26778,8 +41553,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1230] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f24,
+ [1840] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0bda,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -26798,8 +41573,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1231] = {
- .class_hid = BNXT_ULP_CLASS_HID_5584,
+ [1841] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a88,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -26814,8 +41589,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1232] = {
- .class_hid = BNXT_ULP_CLASS_HID_2198,
+ [1842] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20528,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -26831,8 +41606,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1233] = {
- .class_hid = BNXT_ULP_CLASS_HID_7588,
+ [1843] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6080c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -26848,8 +41623,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1234] = {
- .class_hid = BNXT_ULP_CLASS_HID_419c,
+ [1844] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61aac,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -26866,8 +41641,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1235] = {
- .class_hid = BNXT_ULP_CLASS_HID_27758,
+ [1845] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31a18,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -26883,8 +41658,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1236] = {
- .class_hid = BNXT_ULP_CLASS_HID_243ac,
+ [1846] = {
+ .class_hid = BNXT_ULP_CLASS_HID_314b8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -26901,8 +41676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1237] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c10,
+ [1847] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71f9c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -26919,8 +41694,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1238] = {
- .class_hid = BNXT_ULP_CLASS_HID_21864,
+ [1848] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70a5e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -26938,8 +41713,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1239] = {
- .class_hid = BNXT_ULP_CLASS_HID_130c8,
+ [1849] = {
+ .class_hid = BNXT_ULP_CLASS_HID_282c0,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -26955,8 +41730,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1240] = {
- .class_hid = BNXT_ULP_CLASS_HID_11cdc,
+ [1850] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29d60,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -26973,8 +41748,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1241] = {
- .class_hid = BNXT_ULP_CLASS_HID_150cc,
+ [1851] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68044,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -26991,8 +41766,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1242] = {
- .class_hid = BNXT_ULP_CLASS_HID_13d20,
+ [1852] = {
+ .class_hid = BNXT_ULP_CLASS_HID_692e4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -27010,8 +41785,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1243] = {
- .class_hid = BNXT_ULP_CLASS_HID_3529c,
+ [1853] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39250,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -27028,8 +41803,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1244] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ef0,
+ [1854] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38c12,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -27047,8 +41822,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1245] = {
- .class_hid = BNXT_ULP_CLASS_HID_372e0,
+ [1855] = {
+ .class_hid = BNXT_ULP_CLASS_HID_797d4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -27066,8 +41841,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1246] = {
- .class_hid = BNXT_ULP_CLASS_HID_35ef4,
+ [1856] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78196,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -27086,8 +41861,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1247] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfc,
+ [1857] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f32,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -27102,8 +41877,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1248] = {
- .class_hid = BNXT_ULP_CLASS_HID_39e0,
+ [1858] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81992,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -27119,8 +41894,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1249] = {
- .class_hid = BNXT_ULP_CLASS_HID_4530,
+ [1859] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80522,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -27136,8 +41911,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1250] = {
- .class_hid = BNXT_ULP_CLASS_HID_5124,
+ [1860] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81782,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -27154,8 +41929,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1251] = {
- .class_hid = BNXT_ULP_CLASS_HID_4df0,
+ [1861] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0cbe,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -27171,8 +41946,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1252] = {
- .class_hid = BNXT_ULP_CLASS_HID_59e4,
+ [1862] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1f1e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -27189,8 +41964,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1253] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c78,
+ [1863] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1aae,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -27207,8 +41982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1254] = {
- .class_hid = BNXT_ULP_CLASS_HID_7118,
+ [1864] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c150e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -27226,8 +42001,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1255] = {
- .class_hid = BNXT_ULP_CLASS_HID_0998,
+ [1865] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0dfc,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -27243,8 +42018,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1256] = {
- .class_hid = BNXT_ULP_CLASS_HID_158c,
+ [1866] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a185c,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -27261,8 +42036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1257] = {
- .class_hid = BNXT_ULP_CLASS_HID_20dc,
+ [1867] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1bec,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -27279,8 +42054,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1258] = {
- .class_hid = BNXT_ULP_CLASS_HID_0cc0,
+ [1868] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a164c,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -27298,8 +42073,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1259] = {
- .class_hid = BNXT_ULP_CLASS_HID_299c,
+ [1869] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0378,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -27316,8 +42091,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1260] = {
- .class_hid = BNXT_ULP_CLASS_HID_3580,
+ [1870] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1dd8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -27335,8 +42110,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1261] = {
- .class_hid = BNXT_ULP_CLASS_HID_40d0,
+ [1871] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1968,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -27354,8 +42129,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1262] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc4,
+ [1872] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0baa,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -27374,8 +42149,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1263] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a4,
+ [1873] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20af8,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -27390,8 +42165,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1264] = {
- .class_hid = BNXT_ULP_CLASS_HID_21b8,
+ [1874] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20558,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -27407,8 +42182,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1265] = {
- .class_hid = BNXT_ULP_CLASS_HID_75a8,
+ [1875] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6087c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -27424,8 +42199,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1266] = {
- .class_hid = BNXT_ULP_CLASS_HID_41bc,
+ [1876] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61adc,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -27442,8 +42217,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1267] = {
- .class_hid = BNXT_ULP_CLASS_HID_27778,
+ [1877] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31a68,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -27459,8 +42234,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1268] = {
- .class_hid = BNXT_ULP_CLASS_HID_2438c,
+ [1878] = {
+ .class_hid = BNXT_ULP_CLASS_HID_314c8,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -27477,8 +42252,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1269] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c30,
+ [1879] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71fec,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -27495,8 +42270,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1270] = {
- .class_hid = BNXT_ULP_CLASS_HID_21844,
+ [1880] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70a2e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -27514,8 +42289,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1271] = {
- .class_hid = BNXT_ULP_CLASS_HID_130e8,
+ [1881] = {
+ .class_hid = BNXT_ULP_CLASS_HID_282b0,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -27531,8 +42306,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1272] = {
- .class_hid = BNXT_ULP_CLASS_HID_11cfc,
+ [1882] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29d10,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -27549,8 +42324,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1273] = {
- .class_hid = BNXT_ULP_CLASS_HID_150ec,
+ [1883] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68034,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -27567,8 +42342,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1274] = {
- .class_hid = BNXT_ULP_CLASS_HID_13d00,
+ [1884] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69294,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -27586,8 +42361,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1275] = {
- .class_hid = BNXT_ULP_CLASS_HID_352bc,
+ [1885] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39220,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -27604,8 +42379,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1276] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed0,
+ [1886] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38c62,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -27623,8 +42398,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1277] = {
- .class_hid = BNXT_ULP_CLASS_HID_372c0,
+ [1887] = {
+ .class_hid = BNXT_ULP_CLASS_HID_797a4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -27642,8 +42417,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1278] = {
- .class_hid = BNXT_ULP_CLASS_HID_35ed4,
+ [1888] = {
+ .class_hid = BNXT_ULP_CLASS_HID_781e6,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -27662,8 +42437,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1279] = {
- .class_hid = BNXT_ULP_CLASS_HID_3866,
+ [1889] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f05,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4UL,
@@ -27677,8 +42452,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [1280] = {
- .class_hid = BNXT_ULP_CLASS_HID_381e,
+ [1890] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f09,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4UL,
@@ -27692,8 +42467,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [1281] = {
- .class_hid = BNXT_ULP_CLASS_HID_3860,
+ [1891] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f06,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4UL,
@@ -27708,8 +42483,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [1282] = {
- .class_hid = BNXT_ULP_CLASS_HID_0454,
+ [1892] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19a6,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68UL,
@@ -27725,8 +42500,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [1283] = {
- .class_hid = BNXT_ULP_CLASS_HID_3818,
+ [1893] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f0a,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4UL,
@@ -27741,8 +42516,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [1284] = {
- .class_hid = BNXT_ULP_CLASS_HID_042c,
+ [1894] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19aa,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68UL,
@@ -27758,8 +42533,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [1285] = {
- .class_hid = BNXT_ULP_CLASS_HID_3846,
+ [1895] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f15,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4UL,
@@ -27774,8 +42549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [1286] = {
- .class_hid = BNXT_ULP_CLASS_HID_387e,
+ [1896] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f19,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4UL,
@@ -27790,8 +42565,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [1287] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ba6,
+ [1897] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f65,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4UL,
@@ -27806,8 +42581,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [1288] = {
- .class_hid = BNXT_ULP_CLASS_HID_385e,
+ [1898] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f69,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4UL,
@@ -27822,8 +42597,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [1289] = {
- .class_hid = BNXT_ULP_CLASS_HID_3840,
+ [1899] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f16,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4UL,
@@ -27839,8 +42614,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [1290] = {
- .class_hid = BNXT_ULP_CLASS_HID_0474,
+ [1900] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19b6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68UL,
@@ -27857,8 +42632,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [1291] = {
- .class_hid = BNXT_ULP_CLASS_HID_3878,
+ [1901] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f1a,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4UL,
@@ -27874,8 +42649,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [1292] = {
- .class_hid = BNXT_ULP_CLASS_HID_044c,
+ [1902] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19ba,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68UL,
@@ -27892,8 +42667,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [1293] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ba0,
+ [1903] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f66,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4UL,
@@ -27909,8 +42684,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [1294] = {
- .class_hid = BNXT_ULP_CLASS_HID_0794,
+ [1904] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19c6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68UL,
@@ -27927,8 +42702,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [1295] = {
- .class_hid = BNXT_ULP_CLASS_HID_3858,
+ [1905] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f6a,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4UL,
@@ -27944,8 +42719,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [1296] = {
- .class_hid = BNXT_ULP_CLASS_HID_046c,
+ [1906] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19ca,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68UL,
@@ -27963,3 +42738,4 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID }
}
};
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 739c546d9e..8afbc37e38 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -1,66 +1,65 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 46
+#define BNXT_ULP_REGFILE_MAX_SZ 61
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 18
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 1297
-#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_GEN_TBL_MAX_SZ 36
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 1048576
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 1907
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
+#define BNXT_ULP_CLASS_HID_SHFTR 29
#define BNXT_ULP_CLASS_HID_SHFTL 28
-#define BNXT_ULP_CLASS_HID_MASK 262143
-#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
+#define BNXT_ULP_CLASS_HID_MASK 1048575
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 32768
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 546
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
-#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
-#define BNXT_ULP_ACT_HID_SHFTR 27
-#define BNXT_ULP_ACT_HID_SHFTL 26
-#define BNXT_ULP_ACT_HID_MASK 2047
-#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132
-#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 144
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 25
+#define BNXT_ULP_ACT_HID_SHFTL 27
+#define BNXT_ULP_ACT_HID_MASK 32767
+#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 46
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 537
+#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 187
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 970
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 25
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
-#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
+#define BNXT_ULP_HDR_SIG_ID_SHIFT 5
+#define BNXT_ULP_APP_ID_CONFIG 0
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 13805
#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 606
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 124
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2514
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
-#define ULP_THOR_CLASS_COND_LIST_SIZE 54
-#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1517
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
+#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 11
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 46
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
-#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 36
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
-#define ULP_THOR_ACT_COND_LIST_SIZE 27
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 616
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 65
+#define ULP_THOR_ACT_TMPL_LIST_SIZE 11
+#define ULP_THOR_ACT_TBL_LIST_SIZE 96
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 34
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 19
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 794
+#define ULP_THOR_ACT_COND_LIST_SIZE 75
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -90,7 +89,18 @@ enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_SHARED = 0x0000000001000000,
BNXT_ULP_ACT_BIT_SAMPLE = 0x0000000002000000,
BNXT_ULP_ACT_BIT_SHARED_SAMPLE = 0x0000000004000000,
- BNXT_ULP_ACT_BIT_LAST = 0x0000000008000000
+ BNXT_ULP_ACT_BIT_QUEUE = 0x0000000008000000,
+ BNXT_ULP_ACT_BIT_DELETE = 0x0000000010000000,
+ BNXT_ULP_ACT_BIT_UPDATE = 0x0000000020000000,
+ BNXT_ULP_ACT_BIT_SHARED_METER = 0x0000000040000000,
+ BNXT_ULP_ACT_BIT_METER_PROFILE = 0x0000000080000000,
+ BNXT_ULP_ACT_BIT_GOTO_CHAIN = 0x0000000100000000,
+ BNXT_ULP_ACT_BIT_VF_TO_VF = 0x0000000200000000,
+ BNXT_ULP_ACT_BIT_IP_ENCAP = 0x0000000400000000,
+ BNXT_ULP_ACT_BIT_IP_DECAP = 0x0000000800000000,
+ BNXT_ULP_ACT_BIT_L2_ENCAP = 0x0000001000000000,
+ BNXT_ULP_ACT_BIT_L2_DECAP = 0x0000002000000000,
+ BNXT_ULP_ACT_BIT_LAST = 0x0000004000000000
};
enum bnxt_ulp_hdr_bit {
@@ -112,10 +122,13 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000008000,
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
- BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
- BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000
+ BNXT_ULP_HDR_BIT_O_ECPRI = 0x0000000000040000,
+ BNXT_ULP_HDR_BIT_O_ROE = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_F1 = 0x0000000000100000,
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000200000,
+ BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000400000,
+ BNXT_ULP_HDR_BIT_O_SRV6 = 0x0000000000800000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000001000000
};
enum bnxt_ulp_accept_opc {
@@ -141,11 +154,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_NOT_USED = 0,
BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1,
BNXT_ULP_CF_IDX_O_VTAG_NUM = 2,
- BNXT_ULP_CF_IDX_O_NO_VTAG = 3,
+ BNXT_ULP_CF_IDX_O_HAS_VTAG = 3,
BNXT_ULP_CF_IDX_O_ONE_VTAG = 4,
BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5,
BNXT_ULP_CF_IDX_I_VTAG_NUM = 6,
- BNXT_ULP_CF_IDX_I_NO_VTAG = 7,
+ BNXT_ULP_CF_IDX_I_HAS_VTAG = 7,
BNXT_ULP_CF_IDX_I_ONE_VTAG = 8,
BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9,
BNXT_ULP_CF_IDX_INCOMING_IF = 10,
@@ -214,7 +227,17 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74,
BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75,
- BNXT_ULP_CF_IDX_LAST = 76
+ BNXT_ULP_CF_IDX_TUNNEL_SPORT = 76,
+ BNXT_ULP_CF_IDX_VF_META_FID = 77,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID = 78,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE = 79,
+ BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE = 80,
+ BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED = 81,
+ BNXT_ULP_CF_IDX_CHAIN_ID_METADATA = 82,
+ BNXT_ULP_CF_IDX_SRV6_UPAR_ID = 83,
+ BNXT_ULP_CF_IDX_SRV6_T_ID = 84,
+ BNXT_ULP_CF_IDX_GENERIC_SIZE = 85,
+ BNXT_ULP_CF_IDX_LAST = 86
};
enum bnxt_ulp_cond_list_opc {
@@ -242,7 +265,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
- BNXT_ULP_COND_OPC_LAST = 16
+ BNXT_ULP_COND_OPC_ACT_PROP_IS_SET = 16,
+ BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET = 17,
+ BNXT_ULP_COND_OPC_LAST = 18
};
enum bnxt_ulp_critical_resource {
@@ -297,15 +322,30 @@ enum bnxt_ulp_enc_field {
BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
- BNXT_ULP_ENC_FIELD_LAST = 26
+ BNXT_ULP_ENC_FIELD_SRV6_NEXT_HDR = 26,
+ BNXT_ULP_ENC_FIELD_SRV6_HDR_LEN = 27,
+ BNXT_ULP_ENC_FIELD_SRV6_ROUTING_TYPE = 28,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LEFT = 29,
+ BNXT_ULP_ENC_FIELD_SRV6_LAST_ENTRY = 30,
+ BNXT_ULP_ENC_FIELD_SRV6_FLAGS = 31,
+ BNXT_ULP_ENC_FIELD_SRV6_TAG = 32,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST0 = 33,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST1 = 34,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST2 = 35,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST3 = 36,
+ BNXT_ULP_ENC_FIELD_GENERIC_SIZE = 37,
+ BNXT_ULP_ENC_FIELD_GENERIC_RSVD = 38,
+ BNXT_ULP_ENC_FIELD_LAST = 39
};
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE = 2,
- BNXT_ULP_FDB_OPC_NOP = 3,
- BNXT_ULP_FDB_OPC_LAST = 4
+ BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE = 3,
+ BNXT_ULP_FDB_OPC_CLEAR_RID_REGFILE = 4,
+ BNXT_ULP_FDB_OPC_NOP = 5,
+ BNXT_ULP_FDB_OPC_LAST = 6
};
enum bnxt_ulp_fdb_type {
@@ -364,7 +404,9 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
- BNXT_ULP_FUNC_OPC_LAST = 11
+ BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_ALLOC = 11,
+ BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_FREE = 12,
+ BNXT_ULP_FUNC_OPC_LAST = 13
};
enum bnxt_ulp_func_src {
@@ -391,71 +433,101 @@ enum bnxt_ulp_generic_tbl_opc {
enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_NOT_USED = 0,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID = 1,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 2,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4,
- BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 61,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 62,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 63,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 64,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 65,
- BNXT_ULP_GLB_RF_IDX_LAST = 66
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0 = 2,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1 = 3,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_2 = 4,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 5,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 6,
+ BNXT_ULP_GLB_RF_IDX_GLB_L2_CNTXT_ID_0 = 7,
+ BNXT_ULP_GLB_RF_IDX_GLB_L2_CNTXT_ID_1 = 8,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 9,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID = 10,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR = 13,
+ BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_8 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_9 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_5 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_6 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_7 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_8 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 36,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 37,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 38,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 39,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 40,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 41,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_8 = 42,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_9 = 43,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 47,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 48,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_5 = 49,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 50,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 51,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 52,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 = 53,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 54,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 = 55,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 56,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 57,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 58,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 59,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 60,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 61,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2 = 62,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3 = 63,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 64,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 65,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 66,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 67,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 68,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 69,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 70,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 71,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 72,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 73,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 74,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 75,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 76,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 77,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 78,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 79,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 80,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 81,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 82,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 83,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 84,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 85,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 86,
+ BNXT_ULP_GLB_RF_IDX_RECYCLE_PROF_FUNC_ID = 87,
+ BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_UPAR_ID = 88,
+ BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_PROF_FUNC_ID = 89,
+ BNXT_ULP_GLB_RF_IDX_LAST = 90
+};
+
+enum bnxt_ulp_global_register_tbl_opc {
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_WR_REGFILE = 1,
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_LAST = 2
};
enum bnxt_ulp_hdr_type {
@@ -482,7 +554,8 @@ enum bnxt_ulp_index_tbl_opc {
BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 4,
BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE = 5,
BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 6,
- BNXT_ULP_INDEX_TBL_OPC_LAST = 7
+ BNXT_ULP_INDEX_TBL_OPC_UPDATE_REGFILE = 7,
+ BNXT_ULP_INDEX_TBL_OPC_LAST = 8
};
enum bnxt_ulp_mark_db_opc {
@@ -516,14 +589,25 @@ enum bnxt_ulp_port_table {
BNXT_ULP_PORT_TABLE_PHY_PORT_SPIF = 14,
BNXT_ULP_PORT_TABLE_PHY_PORT_PARIF = 15,
BNXT_ULP_PORT_TABLE_PHY_PORT_VPORT = 16,
- BNXT_ULP_PORT_TABLE_LAST = 17
+ BNXT_ULP_PORT_TABLE_PORT_IS_PF = 17,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA = 18,
+ BNXT_ULP_PORT_TABLE_LAST = 19
};
enum bnxt_ulp_pri_opc {
BNXT_ULP_PRI_OPC_NOT_USED = 0,
BNXT_ULP_PRI_OPC_CONST = 1,
BNXT_ULP_PRI_OPC_APP_PRI = 2,
- BNXT_ULP_PRI_OPC_LAST = 3
+ BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST = 3,
+ BNXT_ULP_PRI_OPC_LAST = 4
+};
+
+enum bnxt_ulp_ref_cnt_opc {
+ BNXT_ULP_REF_CNT_OPC_DEFAULT = 0,
+ BNXT_ULP_REF_CNT_OPC_NOP = 1,
+ BNXT_ULP_REF_CNT_OPC_DEC = 2,
+ BNXT_ULP_REF_CNT_OPC_INC = 3,
+ BNXT_ULP_REF_CNT_OPC_LAST = 4
};
enum bnxt_ulp_rf_idx {
@@ -573,13 +657,22 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43,
BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44,
BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45,
- BNXT_ULP_RF_IDX_LAST = 46
-};
-
-enum bnxt_ulp_shared_session {
- BNXT_ULP_SHARED_SESSION_NO = 0,
- BNXT_ULP_SHARED_SESSION_YES = 1,
- BNXT_ULP_SHARED_SESSION_LAST = 2
+ BNXT_ULP_RF_IDX_RSS_VNIC = 46,
+ BNXT_ULP_RF_IDX_PORT_IS_PF = 47,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 = 48,
+ BNXT_ULP_RF_IDX_METER_PTR_0 = 49,
+ BNXT_ULP_RF_IDX_REF_CNT = 50,
+ BNXT_ULP_RF_IDX_RF_0 = 51,
+ BNXT_ULP_RF_IDX_RF_1 = 52,
+ BNXT_ULP_RF_IDX_RF_2 = 53,
+ BNXT_ULP_RF_IDX_RF_3 = 54,
+ BNXT_ULP_RF_IDX_RF_4 = 55,
+ BNXT_ULP_RF_IDX_RF_5 = 56,
+ BNXT_ULP_RF_IDX_RF_6 = 57,
+ BNXT_ULP_RF_IDX_RF_7 = 58,
+ BNXT_ULP_RF_IDX_VF_FUNC_METADATA = 59,
+ BNXT_ULP_RF_IDX_CHAIN_ID_METADATA = 60,
+ BNXT_ULP_RF_IDX_LAST = 61
};
enum bnxt_ulp_tcam_tbl_opc {
@@ -598,11 +691,22 @@ enum bnxt_ulp_template_type {
BNXT_ULP_TEMPLATE_TYPE_LAST = 2
};
+enum bnxt_ulp_vnic_tbl_opc {
+ BNXT_ULP_VNIC_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE = 1,
+ BNXT_ULP_VNIC_TBL_OPC_LAST = 2
+};
+
enum bnxt_ulp_app_cap {
BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001,
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002,
BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004,
- BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008,
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT = 0x00000010,
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT = 0x00000020,
+ BNXT_ULP_APP_CAP_CUST_VXLAN = 0x00000040,
+ BNXT_ULP_APP_CAP_HA_DYNAMIC = 0x00000080,
+ BNXT_ULP_APP_CAP_SRV6 = 0x00000100
};
enum bnxt_ulp_fdb_resource_flags {
@@ -628,7 +732,9 @@ enum bnxt_ulp_resource_func {
BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,
BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,
- BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88
+ BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88,
+ BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE = 0x89,
+ BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE = 0x8a
};
enum bnxt_ulp_resource_sub_type {
@@ -646,7 +752,30 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE = 9,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE = 10,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE = 11,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE = 12,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE = 13,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL = 14,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE = 15,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE = 16,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE = 17,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS = 18,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI = 1
+};
+
+enum bnxt_ulp_session_type {
+ BNXT_ULP_SESSION_TYPE_DEFAULT = 0x00,
+ BNXT_ULP_SESSION_TYPE_SHARED = 0x01,
+ BNXT_ULP_SESSION_TYPE_SHARED_WC = 0x02,
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC = 0x04,
+ BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA = 0x08,
+ BNXT_ULP_SESSION_TYPE_LAST = 0x10
};
enum bnxt_ulp_act_prop_sz {
@@ -664,8 +793,8 @@ enum bnxt_ulp_act_prop_sz {
BNXT_ULP_ACT_PROP_SZ_MARK = 4,
BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
BNXT_ULP_ACT_PROP_SZ_METER = 4,
- BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
- BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 6,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 6,
BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN = 2,
BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP = 1,
BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID = 2,
@@ -696,6 +825,28 @@ enum bnxt_ulp_act_prop_sz {
BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL = 4,
BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN = 4,
BNXT_ULP_ACT_PROP_SZ_RSS_KEY = 40,
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM = 2,
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE = 32,
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR = 3,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR = 3,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698 = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBND = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBND = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBSM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBSM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CF = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL = 1,
+ BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID = 2,
BNXT_ULP_ACT_PROP_SZ_LAST = 4
};
@@ -715,38 +866,60 @@ enum bnxt_ulp_act_prop_idx {
BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
BNXT_ULP_ACT_PROP_IDX_METER = 52,
BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
- BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
- BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 72,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 74,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 75,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 77,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 81,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 85,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 101,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 117,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 119,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 121,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 125,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 129,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 133,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 137,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 141,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 145,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 149,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 153,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 159,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 165,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 173,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
- BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
- BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261,
- BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 269,
- BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 277,
- BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 281,
- BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 285,
- BNXT_ULP_ACT_PROP_IDX_LAST = 325
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 62,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 68,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 70,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 71,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 73,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 77,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 81,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 97,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 113,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 115,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 117,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 121,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 125,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 129,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 133,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 137,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 141,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 145,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 149,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 155,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 161,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 169,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 201,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 217,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 221,
+ BNXT_ULP_ACT_PROP_IDX_JUMP = 253,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 257,
+ BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 265,
+ BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 273,
+ BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 277,
+ BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 281,
+ BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM = 321,
+ BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE = 323,
+ BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX = 355,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE = 357,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID = 358,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR = 362,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR = 365,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS = 368,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS = 370,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 = 372,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM = 373,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND = 374,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND = 375,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM = 376,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM = 377,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF = 378,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID = 379,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE = 383,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN = 384,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE = 385,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL = 386,
+ BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID = 387,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 389
};
enum ulp_wp_sym {
@@ -905,6 +1078,11 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_NORMAL = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_FAST = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_FAST = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_ACT = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RECYCLE = 0,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
@@ -980,7 +1158,15 @@ enum ulp_wp_sym {
ULP_WP_SYM_VF_FUNC_PARIF = 15,
ULP_WP_SYM_NO = 0,
ULP_WP_SYM_YES = 1,
- ULP_WP_SYM_RECYCLE_DST = 0x800
+ ULP_WP_SYM_RECYCLE_DST = 0x800,
+ ULP_WP_SYM_VF_2_VFR_META_VAL = 0,
+ ULP_WP_SYM_VF_2_VF_META_VAL = 0,
+ ULP_WP_SYM_VF_2_VFR_META_MASK = 0,
+ ULP_WP_SYM_META_PROFILE_0 = 0,
+ ULP_WP_SYM_CHAIN_META_VAL = 0,
+ ULP_WP_SYM_L2_ECPRI_ETYPE = 0,
+ ULP_WP_SYM_L4_ECPRI_ETYPE = 0,
+ ULP_WP_SYM_L2_ROE_ETYPE = 0
};
enum ulp_thor_sym {
@@ -1139,6 +1325,11 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_NORMAL = 0,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_FAST = 1,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_FAST = 2,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_ACT = 3,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RECYCLE = 4,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
@@ -1214,1402 +1405,2472 @@ enum ulp_thor_sym {
ULP_THOR_SYM_VF_FUNC_PARIF = 15,
ULP_THOR_SYM_NO = 0,
ULP_THOR_SYM_YES = 1,
- ULP_THOR_SYM_RECYCLE_DST = 0x800
+ ULP_THOR_SYM_RECYCLE_DST = 1039,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL = 8192,
+ ULP_THOR_SYM_VF_2_VF_META_VAL = 4096,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK = 61440,
+ ULP_THOR_SYM_META_PROFILE_0 = 0,
+ ULP_THOR_SYM_CHAIN_META_VAL = 12288,
+ ULP_THOR_SYM_L2_ECPRI_ETYPE = 44798,
+ ULP_THOR_SYM_L4_ECPRI_ETYPE = 2048,
+ ULP_THOR_SYM_L2_ROE_ETYPE = 64573
};
enum bnxt_ulp_class_hid {
- BNXT_ULP_CLASS_HID_55dd = 0x55dd,
- BNXT_ULP_CLASS_HID_1df1 = 0x1df1,
- BNXT_ULP_CLASS_HID_3e55 = 0x3e55,
- BNXT_ULP_CLASS_HID_0649 = 0x0649,
- BNXT_ULP_CLASS_HID_1011 = 0x1011,
- BNXT_ULP_CLASS_HID_40e9 = 0x40e9,
- BNXT_ULP_CLASS_HID_3e99 = 0x3e99,
- BNXT_ULP_CLASS_HID_06ad = 0x06ad,
- BNXT_ULP_CLASS_HID_38c7 = 0x38c7,
- BNXT_ULP_CLASS_HID_00fb = 0x00fb,
- BNXT_ULP_CLASS_HID_24d3 = 0x24d3,
- BNXT_ULP_CLASS_HID_559b = 0x559b,
- BNXT_ULP_CLASS_HID_5003 = 0x5003,
- BNXT_ULP_CLASS_HID_1837 = 0x1837,
- BNXT_ULP_CLASS_HID_3bef = 0x3bef,
- BNXT_ULP_CLASS_HID_0403 = 0x0403,
- BNXT_ULP_CLASS_HID_3d3f = 0x3d3f,
- BNXT_ULP_CLASS_HID_0543 = 0x0543,
- BNXT_ULP_CLASS_HID_292b = 0x292b,
- BNXT_ULP_CLASS_HID_59e3 = 0x59e3,
- BNXT_ULP_CLASS_HID_5d3b = 0x5d3b,
- BNXT_ULP_CLASS_HID_254f = 0x254f,
- BNXT_ULP_CLASS_HID_4917 = 0x4917,
- BNXT_ULP_CLASS_HID_113b = 0x113b,
- BNXT_ULP_CLASS_HID_55fd = 0x55fd,
- BNXT_ULP_CLASS_HID_1dd1 = 0x1dd1,
- BNXT_ULP_CLASS_HID_3e75 = 0x3e75,
- BNXT_ULP_CLASS_HID_0669 = 0x0669,
- BNXT_ULP_CLASS_HID_1ba1 = 0x1ba1,
- BNXT_ULP_CLASS_HID_4c69 = 0x4c69,
- BNXT_ULP_CLASS_HID_0439 = 0x0439,
- BNXT_ULP_CLASS_HID_34e1 = 0x34e1,
- BNXT_ULP_CLASS_HID_0465 = 0x0465,
- BNXT_ULP_CLASS_HID_352d = 0x352d,
- BNXT_ULP_CLASS_HID_55b1 = 0x55b1,
- BNXT_ULP_CLASS_HID_1da5 = 0x1da5,
- BNXT_ULP_CLASS_HID_32fd = 0x32fd,
- BNXT_ULP_CLASS_HID_63a5 = 0x63a5,
- BNXT_ULP_CLASS_HID_1b75 = 0x1b75,
- BNXT_ULP_CLASS_HID_4c3d = 0x4c3d,
- BNXT_ULP_CLASS_HID_1031 = 0x1031,
- BNXT_ULP_CLASS_HID_40c9 = 0x40c9,
- BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9,
- BNXT_ULP_CLASS_HID_068d = 0x068d,
- BNXT_ULP_CLASS_HID_5039 = 0x5039,
- BNXT_ULP_CLASS_HID_180d = 0x180d,
- BNXT_ULP_CLASS_HID_15fd = 0x15fd,
- BNXT_ULP_CLASS_HID_46b5 = 0x46b5,
- BNXT_ULP_CLASS_HID_303d = 0x303d,
- BNXT_ULP_CLASS_HID_60f5 = 0x60f5,
- BNXT_ULP_CLASS_HID_5ea5 = 0x5ea5,
- BNXT_ULP_CLASS_HID_2689 = 0x2689,
- BNXT_ULP_CLASS_HID_0771 = 0x0771,
- BNXT_ULP_CLASS_HID_3809 = 0x3809,
- BNXT_ULP_CLASS_HID_35f9 = 0x35f9,
- BNXT_ULP_CLASS_HID_66b1 = 0x66b1,
- BNXT_ULP_CLASS_HID_559d = 0x559d,
- BNXT_ULP_CLASS_HID_1db1 = 0x1db1,
- BNXT_ULP_CLASS_HID_3e15 = 0x3e15,
- BNXT_ULP_CLASS_HID_0609 = 0x0609,
- BNXT_ULP_CLASS_HID_1bc1 = 0x1bc1,
- BNXT_ULP_CLASS_HID_4c09 = 0x4c09,
- BNXT_ULP_CLASS_HID_0459 = 0x0459,
- BNXT_ULP_CLASS_HID_3481 = 0x3481,
- BNXT_ULP_CLASS_HID_0405 = 0x0405,
- BNXT_ULP_CLASS_HID_354d = 0x354d,
- BNXT_ULP_CLASS_HID_55d1 = 0x55d1,
- BNXT_ULP_CLASS_HID_1dc5 = 0x1dc5,
- BNXT_ULP_CLASS_HID_329d = 0x329d,
- BNXT_ULP_CLASS_HID_63c5 = 0x63c5,
- BNXT_ULP_CLASS_HID_1b15 = 0x1b15,
- BNXT_ULP_CLASS_HID_4c5d = 0x4c5d,
- BNXT_ULP_CLASS_HID_1051 = 0x1051,
- BNXT_ULP_CLASS_HID_40a9 = 0x40a9,
- BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9,
- BNXT_ULP_CLASS_HID_06ed = 0x06ed,
- BNXT_ULP_CLASS_HID_5059 = 0x5059,
- BNXT_ULP_CLASS_HID_186d = 0x186d,
- BNXT_ULP_CLASS_HID_159d = 0x159d,
- BNXT_ULP_CLASS_HID_46d5 = 0x46d5,
- BNXT_ULP_CLASS_HID_305d = 0x305d,
- BNXT_ULP_CLASS_HID_6095 = 0x6095,
- BNXT_ULP_CLASS_HID_5ec5 = 0x5ec5,
- BNXT_ULP_CLASS_HID_26e9 = 0x26e9,
- BNXT_ULP_CLASS_HID_0711 = 0x0711,
- BNXT_ULP_CLASS_HID_3869 = 0x3869,
- BNXT_ULP_CLASS_HID_3599 = 0x3599,
- BNXT_ULP_CLASS_HID_66d1 = 0x66d1,
- BNXT_ULP_CLASS_HID_38e7 = 0x38e7,
- BNXT_ULP_CLASS_HID_00db = 0x00db,
- BNXT_ULP_CLASS_HID_24f3 = 0x24f3,
- BNXT_ULP_CLASS_HID_55bb = 0x55bb,
- BNXT_ULP_CLASS_HID_5023 = 0x5023,
- BNXT_ULP_CLASS_HID_1817 = 0x1817,
- BNXT_ULP_CLASS_HID_3bcf = 0x3bcf,
- BNXT_ULP_CLASS_HID_0423 = 0x0423,
- BNXT_ULP_CLASS_HID_58e3 = 0x58e3,
- BNXT_ULP_CLASS_HID_20d7 = 0x20d7,
- BNXT_ULP_CLASS_HID_448f = 0x448f,
- BNXT_ULP_CLASS_HID_0ce3 = 0x0ce3,
- BNXT_ULP_CLASS_HID_076b = 0x076b,
- BNXT_ULP_CLASS_HID_3813 = 0x3813,
- BNXT_ULP_CLASS_HID_5bcb = 0x5bcb,
- BNXT_ULP_CLASS_HID_243f = 0x243f,
- BNXT_ULP_CLASS_HID_144b = 0x144b,
- BNXT_ULP_CLASS_HID_4573 = 0x4573,
- BNXT_ULP_CLASS_HID_0057 = 0x0057,
- BNXT_ULP_CLASS_HID_311f = 0x311f,
- BNXT_ULP_CLASS_HID_2b87 = 0x2b87,
- BNXT_ULP_CLASS_HID_5c4f = 0x5c4f,
- BNXT_ULP_CLASS_HID_1793 = 0x1793,
- BNXT_ULP_CLASS_HID_485b = 0x485b,
- BNXT_ULP_CLASS_HID_3447 = 0x3447,
- BNXT_ULP_CLASS_HID_650f = 0x650f,
- BNXT_ULP_CLASS_HID_2053 = 0x2053,
- BNXT_ULP_CLASS_HID_511b = 0x511b,
- BNXT_ULP_CLASS_HID_4b83 = 0x4b83,
- BNXT_ULP_CLASS_HID_13f7 = 0x13f7,
- BNXT_ULP_CLASS_HID_37af = 0x37af,
- BNXT_ULP_CLASS_HID_6857 = 0x6857,
- BNXT_ULP_CLASS_HID_3d1f = 0x3d1f,
- BNXT_ULP_CLASS_HID_0563 = 0x0563,
- BNXT_ULP_CLASS_HID_290b = 0x290b,
- BNXT_ULP_CLASS_HID_59c3 = 0x59c3,
- BNXT_ULP_CLASS_HID_5d1b = 0x5d1b,
- BNXT_ULP_CLASS_HID_256f = 0x256f,
- BNXT_ULP_CLASS_HID_4937 = 0x4937,
- BNXT_ULP_CLASS_HID_111b = 0x111b,
- BNXT_ULP_CLASS_HID_25f4b = 0x25f4b,
- BNXT_ULP_CLASS_HID_2275f = 0x2275f,
- BNXT_ULP_CLASS_HID_24b67 = 0x24b67,
- BNXT_ULP_CLASS_HID_2134b = 0x2134b,
- BNXT_ULP_CLASS_HID_21683 = 0x21683,
- BNXT_ULP_CLASS_HID_2475b = 0x2475b,
- BNXT_ULP_CLASS_HID_202bf = 0x202bf,
- BNXT_ULP_CLASS_HID_23377 = 0x23377,
- BNXT_ULP_CLASS_HID_119db = 0x119db,
- BNXT_ULP_CLASS_HID_14a93 = 0x14a93,
- BNXT_ULP_CLASS_HID_105f7 = 0x105f7,
- BNXT_ULP_CLASS_HID_1368f = 0x1368f,
- BNXT_ULP_CLASS_HID_139c7 = 0x139c7,
- BNXT_ULP_CLASS_HID_1022b = 0x1022b,
- BNXT_ULP_CLASS_HID_125f3 = 0x125f3,
- BNXT_ULP_CLASS_HID_1568b = 0x1568b,
- BNXT_ULP_CLASS_HID_33c37 = 0x33c37,
- BNXT_ULP_CLASS_HID_3041b = 0x3041b,
- BNXT_ULP_CLASS_HID_32823 = 0x32823,
- BNXT_ULP_CLASS_HID_358fb = 0x358fb,
- BNXT_ULP_CLASS_HID_35c33 = 0x35c33,
- BNXT_ULP_CLASS_HID_32407 = 0x32407,
- BNXT_ULP_CLASS_HID_3482f = 0x3482f,
- BNXT_ULP_CLASS_HID_31033 = 0x31033,
- BNXT_ULP_CLASS_HID_3887 = 0x3887,
- BNXT_ULP_CLASS_HID_00bb = 0x00bb,
- BNXT_ULP_CLASS_HID_2493 = 0x2493,
- BNXT_ULP_CLASS_HID_55db = 0x55db,
- BNXT_ULP_CLASS_HID_5043 = 0x5043,
- BNXT_ULP_CLASS_HID_1877 = 0x1877,
- BNXT_ULP_CLASS_HID_3baf = 0x3baf,
- BNXT_ULP_CLASS_HID_0443 = 0x0443,
- BNXT_ULP_CLASS_HID_5883 = 0x5883,
- BNXT_ULP_CLASS_HID_20b7 = 0x20b7,
- BNXT_ULP_CLASS_HID_44ef = 0x44ef,
- BNXT_ULP_CLASS_HID_0c83 = 0x0c83,
- BNXT_ULP_CLASS_HID_070b = 0x070b,
- BNXT_ULP_CLASS_HID_3873 = 0x3873,
- BNXT_ULP_CLASS_HID_5bab = 0x5bab,
- BNXT_ULP_CLASS_HID_245f = 0x245f,
- BNXT_ULP_CLASS_HID_142b = 0x142b,
- BNXT_ULP_CLASS_HID_4513 = 0x4513,
- BNXT_ULP_CLASS_HID_0037 = 0x0037,
- BNXT_ULP_CLASS_HID_317f = 0x317f,
- BNXT_ULP_CLASS_HID_2be7 = 0x2be7,
- BNXT_ULP_CLASS_HID_5c2f = 0x5c2f,
- BNXT_ULP_CLASS_HID_17f3 = 0x17f3,
- BNXT_ULP_CLASS_HID_483b = 0x483b,
- BNXT_ULP_CLASS_HID_3427 = 0x3427,
- BNXT_ULP_CLASS_HID_656f = 0x656f,
- BNXT_ULP_CLASS_HID_2033 = 0x2033,
- BNXT_ULP_CLASS_HID_517b = 0x517b,
- BNXT_ULP_CLASS_HID_4be3 = 0x4be3,
- BNXT_ULP_CLASS_HID_1397 = 0x1397,
- BNXT_ULP_CLASS_HID_37cf = 0x37cf,
- BNXT_ULP_CLASS_HID_6837 = 0x6837,
- BNXT_ULP_CLASS_HID_3d7f = 0x3d7f,
- BNXT_ULP_CLASS_HID_0503 = 0x0503,
- BNXT_ULP_CLASS_HID_296b = 0x296b,
- BNXT_ULP_CLASS_HID_59a3 = 0x59a3,
- BNXT_ULP_CLASS_HID_5d7b = 0x5d7b,
- BNXT_ULP_CLASS_HID_250f = 0x250f,
- BNXT_ULP_CLASS_HID_4957 = 0x4957,
- BNXT_ULP_CLASS_HID_117b = 0x117b,
- BNXT_ULP_CLASS_HID_25f2b = 0x25f2b,
- BNXT_ULP_CLASS_HID_2273f = 0x2273f,
- BNXT_ULP_CLASS_HID_24b07 = 0x24b07,
- BNXT_ULP_CLASS_HID_2132b = 0x2132b,
- BNXT_ULP_CLASS_HID_216e3 = 0x216e3,
- BNXT_ULP_CLASS_HID_2473b = 0x2473b,
- BNXT_ULP_CLASS_HID_202df = 0x202df,
- BNXT_ULP_CLASS_HID_23317 = 0x23317,
- BNXT_ULP_CLASS_HID_119bb = 0x119bb,
- BNXT_ULP_CLASS_HID_14af3 = 0x14af3,
- BNXT_ULP_CLASS_HID_10597 = 0x10597,
- BNXT_ULP_CLASS_HID_136ef = 0x136ef,
- BNXT_ULP_CLASS_HID_139a7 = 0x139a7,
- BNXT_ULP_CLASS_HID_1024b = 0x1024b,
- BNXT_ULP_CLASS_HID_12593 = 0x12593,
- BNXT_ULP_CLASS_HID_156eb = 0x156eb,
- BNXT_ULP_CLASS_HID_33c57 = 0x33c57,
- BNXT_ULP_CLASS_HID_3047b = 0x3047b,
- BNXT_ULP_CLASS_HID_32843 = 0x32843,
- BNXT_ULP_CLASS_HID_3589b = 0x3589b,
- BNXT_ULP_CLASS_HID_35c53 = 0x35c53,
- BNXT_ULP_CLASS_HID_32467 = 0x32467,
- BNXT_ULP_CLASS_HID_3484f = 0x3484f,
- BNXT_ULP_CLASS_HID_31053 = 0x31053,
- BNXT_ULP_CLASS_HID_5ce1 = 0x5ce1,
- BNXT_ULP_CLASS_HID_4579 = 0x4579,
- BNXT_ULP_CLASS_HID_1735 = 0x1735,
- BNXT_ULP_CLASS_HID_45bd = 0x45bd,
- BNXT_ULP_CLASS_HID_3feb = 0x3feb,
- BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7,
- BNXT_ULP_CLASS_HID_5727 = 0x5727,
- BNXT_ULP_CLASS_HID_4333 = 0x4333,
- BNXT_ULP_CLASS_HID_4453 = 0x4453,
- BNXT_ULP_CLASS_HID_304f = 0x304f,
- BNXT_ULP_CLASS_HID_645f = 0x645f,
- BNXT_ULP_CLASS_HID_504b = 0x504b,
- BNXT_ULP_CLASS_HID_5cc1 = 0x5cc1,
- BNXT_ULP_CLASS_HID_4559 = 0x4559,
- BNXT_ULP_CLASS_HID_2285 = 0x2285,
- BNXT_ULP_CLASS_HID_0b1d = 0x0b1d,
- BNXT_ULP_CLASS_HID_0b49 = 0x0b49,
- BNXT_ULP_CLASS_HID_5c95 = 0x5c95,
- BNXT_ULP_CLASS_HID_39c1 = 0x39c1,
- BNXT_ULP_CLASS_HID_2259 = 0x2259,
- BNXT_ULP_CLASS_HID_1715 = 0x1715,
- BNXT_ULP_CLASS_HID_459d = 0x459d,
- BNXT_ULP_CLASS_HID_571d = 0x571d,
- BNXT_ULP_CLASS_HID_1cd1 = 0x1cd1,
- BNXT_ULP_CLASS_HID_3711 = 0x3711,
- BNXT_ULP_CLASS_HID_6599 = 0x6599,
- BNXT_ULP_CLASS_HID_0e55 = 0x0e55,
- BNXT_ULP_CLASS_HID_3cdd = 0x3cdd,
- BNXT_ULP_CLASS_HID_5ca1 = 0x5ca1,
- BNXT_ULP_CLASS_HID_4539 = 0x4539,
- BNXT_ULP_CLASS_HID_22e5 = 0x22e5,
- BNXT_ULP_CLASS_HID_0b7d = 0x0b7d,
- BNXT_ULP_CLASS_HID_0b29 = 0x0b29,
- BNXT_ULP_CLASS_HID_5cf5 = 0x5cf5,
- BNXT_ULP_CLASS_HID_39a1 = 0x39a1,
- BNXT_ULP_CLASS_HID_2239 = 0x2239,
- BNXT_ULP_CLASS_HID_1775 = 0x1775,
- BNXT_ULP_CLASS_HID_45fd = 0x45fd,
- BNXT_ULP_CLASS_HID_577d = 0x577d,
- BNXT_ULP_CLASS_HID_1cb1 = 0x1cb1,
- BNXT_ULP_CLASS_HID_3771 = 0x3771,
- BNXT_ULP_CLASS_HID_65f9 = 0x65f9,
- BNXT_ULP_CLASS_HID_0e35 = 0x0e35,
- BNXT_ULP_CLASS_HID_3cbd = 0x3cbd,
- BNXT_ULP_CLASS_HID_3fcb = 0x3fcb,
- BNXT_ULP_CLASS_HID_2bd7 = 0x2bd7,
- BNXT_ULP_CLASS_HID_5707 = 0x5707,
- BNXT_ULP_CLASS_HID_4313 = 0x4313,
- BNXT_ULP_CLASS_HID_5fc7 = 0x5fc7,
- BNXT_ULP_CLASS_HID_4bd3 = 0x4bd3,
- BNXT_ULP_CLASS_HID_0e4f = 0x0e4f,
- BNXT_ULP_CLASS_HID_632f = 0x632f,
- BNXT_ULP_CLASS_HID_1baf = 0x1baf,
- BNXT_ULP_CLASS_HID_07bb = 0x07bb,
- BNXT_ULP_CLASS_HID_32eb = 0x32eb,
- BNXT_ULP_CLASS_HID_1ef7 = 0x1ef7,
- BNXT_ULP_CLASS_HID_3bab = 0x3bab,
- BNXT_ULP_CLASS_HID_27b7 = 0x27b7,
- BNXT_ULP_CLASS_HID_52e7 = 0x52e7,
- BNXT_ULP_CLASS_HID_3ef3 = 0x3ef3,
- BNXT_ULP_CLASS_HID_4473 = 0x4473,
- BNXT_ULP_CLASS_HID_306f = 0x306f,
- BNXT_ULP_CLASS_HID_647f = 0x647f,
- BNXT_ULP_CLASS_HID_506b = 0x506b,
- BNXT_ULP_CLASS_HID_266af = 0x266af,
- BNXT_ULP_CLASS_HID_2525b = 0x2525b,
- BNXT_ULP_CLASS_HID_21de7 = 0x21de7,
- BNXT_ULP_CLASS_HID_20993 = 0x20993,
- BNXT_ULP_CLASS_HID_1213f = 0x1213f,
- BNXT_ULP_CLASS_HID_10d2b = 0x10d2b,
- BNXT_ULP_CLASS_HID_1413b = 0x1413b,
- BNXT_ULP_CLASS_HID_12cd7 = 0x12cd7,
- BNXT_ULP_CLASS_HID_3436b = 0x3436b,
- BNXT_ULP_CLASS_HID_32f07 = 0x32f07,
- BNXT_ULP_CLASS_HID_36317 = 0x36317,
- BNXT_ULP_CLASS_HID_34f03 = 0x34f03,
- BNXT_ULP_CLASS_HID_3fab = 0x3fab,
- BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7,
- BNXT_ULP_CLASS_HID_5767 = 0x5767,
- BNXT_ULP_CLASS_HID_4373 = 0x4373,
- BNXT_ULP_CLASS_HID_5fa7 = 0x5fa7,
- BNXT_ULP_CLASS_HID_4bb3 = 0x4bb3,
- BNXT_ULP_CLASS_HID_0e2f = 0x0e2f,
- BNXT_ULP_CLASS_HID_634f = 0x634f,
- BNXT_ULP_CLASS_HID_1bcf = 0x1bcf,
- BNXT_ULP_CLASS_HID_07db = 0x07db,
- BNXT_ULP_CLASS_HID_328b = 0x328b,
- BNXT_ULP_CLASS_HID_1e97 = 0x1e97,
- BNXT_ULP_CLASS_HID_3bcb = 0x3bcb,
- BNXT_ULP_CLASS_HID_27d7 = 0x27d7,
- BNXT_ULP_CLASS_HID_5287 = 0x5287,
- BNXT_ULP_CLASS_HID_3e93 = 0x3e93,
- BNXT_ULP_CLASS_HID_4413 = 0x4413,
- BNXT_ULP_CLASS_HID_300f = 0x300f,
- BNXT_ULP_CLASS_HID_641f = 0x641f,
- BNXT_ULP_CLASS_HID_500b = 0x500b,
- BNXT_ULP_CLASS_HID_266cf = 0x266cf,
- BNXT_ULP_CLASS_HID_2523b = 0x2523b,
- BNXT_ULP_CLASS_HID_21d87 = 0x21d87,
- BNXT_ULP_CLASS_HID_209f3 = 0x209f3,
- BNXT_ULP_CLASS_HID_1215f = 0x1215f,
- BNXT_ULP_CLASS_HID_10d4b = 0x10d4b,
- BNXT_ULP_CLASS_HID_1415b = 0x1415b,
- BNXT_ULP_CLASS_HID_12cb7 = 0x12cb7,
- BNXT_ULP_CLASS_HID_3430b = 0x3430b,
- BNXT_ULP_CLASS_HID_32f67 = 0x32f67,
- BNXT_ULP_CLASS_HID_36377 = 0x36377,
- BNXT_ULP_CLASS_HID_34f63 = 0x34f63,
- BNXT_ULP_CLASS_HID_29b5 = 0x29b5,
- BNXT_ULP_CLASS_HID_29ad = 0x29ad,
- BNXT_ULP_CLASS_HID_29b7 = 0x29b7,
- BNXT_ULP_CLASS_HID_1583 = 0x1583,
- BNXT_ULP_CLASS_HID_29af = 0x29af,
- BNXT_ULP_CLASS_HID_159b = 0x159b,
- BNXT_ULP_CLASS_HID_2995 = 0x2995,
- BNXT_ULP_CLASS_HID_298d = 0x298d,
- BNXT_ULP_CLASS_HID_29f5 = 0x29f5,
- BNXT_ULP_CLASS_HID_29ed = 0x29ed,
- BNXT_ULP_CLASS_HID_2997 = 0x2997,
- BNXT_ULP_CLASS_HID_15a3 = 0x15a3,
- BNXT_ULP_CLASS_HID_298f = 0x298f,
- BNXT_ULP_CLASS_HID_15bb = 0x15bb,
- BNXT_ULP_CLASS_HID_29f7 = 0x29f7,
- BNXT_ULP_CLASS_HID_15c3 = 0x15c3,
- BNXT_ULP_CLASS_HID_29ef = 0x29ef,
- BNXT_ULP_CLASS_HID_15db = 0x15db,
- BNXT_ULP_CLASS_HID_1151 = 0x1151,
- BNXT_ULP_CLASS_HID_315d = 0x315d,
- BNXT_ULP_CLASS_HID_3612 = 0x3612,
- BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_243ca = 0x243ca,
- BNXT_ULP_CLASS_HID_20d8e = 0x20d8e,
- BNXT_ULP_CLASS_HID_2e082 = 0x2e082,
- BNXT_ULP_CLASS_HID_2ab46 = 0x2ab46,
- BNXT_ULP_CLASS_HID_25226 = 0x25226,
- BNXT_ULP_CLASS_HID_25cea = 0x25cea,
- BNXT_ULP_CLASS_HID_2c82a = 0x2c82a,
- BNXT_ULP_CLASS_HID_2f9a2 = 0x2f9a2,
- BNXT_ULP_CLASS_HID_23b56 = 0x23b56,
- BNXT_ULP_CLASS_HID_205da = 0x205da,
- BNXT_ULP_CLASS_HID_2d8ce = 0x2d8ce,
- BNXT_ULP_CLASS_HID_2a2d2 = 0x2a2d2,
- BNXT_ULP_CLASS_HID_24a72 = 0x24a72,
- BNXT_ULP_CLASS_HID_25476 = 0x25476,
- BNXT_ULP_CLASS_HID_2c076 = 0x2c076,
- BNXT_ULP_CLASS_HID_2f1ee = 0x2f1ee,
- BNXT_ULP_CLASS_HID_20bb6 = 0x20bb6,
- BNXT_ULP_CLASS_HID_23d2e = 0x23d2e,
- BNXT_ULP_CLASS_HID_2a96e = 0x2a96e,
- BNXT_ULP_CLASS_HID_2dae6 = 0x2dae6,
- BNXT_ULP_CLASS_HID_25af2 = 0x25af2,
- BNXT_ULP_CLASS_HID_24c6a = 0x24c6a,
- BNXT_ULP_CLASS_HID_2c7aa = 0x2c7aa,
- BNXT_ULP_CLASS_HID_2c26e = 0x2c26e,
- BNXT_ULP_CLASS_HID_203e2 = 0x203e2,
- BNXT_ULP_CLASS_HID_2357a = 0x2357a,
- BNXT_ULP_CLASS_HID_2a0fa = 0x2a0fa,
- BNXT_ULP_CLASS_HID_2d272 = 0x2d272,
- BNXT_ULP_CLASS_HID_2527e = 0x2527e,
- BNXT_ULP_CLASS_HID_243f6 = 0x243f6,
- BNXT_ULP_CLASS_HID_2fff6 = 0x2fff6,
- BNXT_ULP_CLASS_HID_2e16e = 0x2e16e,
- BNXT_ULP_CLASS_HID_2422d = 0x2422d,
- BNXT_ULP_CLASS_HID_20c69 = 0x20c69,
- BNXT_ULP_CLASS_HID_2e165 = 0x2e165,
- BNXT_ULP_CLASS_HID_2aaa1 = 0x2aaa1,
- BNXT_ULP_CLASS_HID_253c1 = 0x253c1,
- BNXT_ULP_CLASS_HID_25d0d = 0x25d0d,
- BNXT_ULP_CLASS_HID_2c9cd = 0x2c9cd,
- BNXT_ULP_CLASS_HID_2f845 = 0x2f845,
- BNXT_ULP_CLASS_HID_25afd = 0x25afd,
- BNXT_ULP_CLASS_HID_22439 = 0x22439,
- BNXT_ULP_CLASS_HID_290f9 = 0x290f9,
- BNXT_ULP_CLASS_HID_2c371 = 0x2c371,
- BNXT_ULP_CLASS_HID_24355 = 0x24355,
- BNXT_ULP_CLASS_HID_275dd = 0x275dd,
- BNXT_ULP_CLASS_HID_2e19d = 0x2e19d,
- BNXT_ULP_CLASS_HID_2d015 = 0x2d015,
- BNXT_ULP_CLASS_HID_2560d = 0x2560d,
- BNXT_ULP_CLASS_HID_21049 = 0x21049,
- BNXT_ULP_CLASS_HID_28c09 = 0x28c09,
- BNXT_ULP_CLASS_HID_2be89 = 0x2be89,
- BNXT_ULP_CLASS_HID_267a9 = 0x267a9,
- BNXT_ULP_CLASS_HID_261ed = 0x261ed,
- BNXT_ULP_CLASS_HID_2ddad = 0x2ddad,
- BNXT_ULP_CLASS_HID_2cc2d = 0x2cc2d,
- BNXT_ULP_CLASS_HID_26edd = 0x26edd,
- BNXT_ULP_CLASS_HID_22819 = 0x22819,
- BNXT_ULP_CLASS_HID_2a4d9 = 0x2a4d9,
- BNXT_ULP_CLASS_HID_2d759 = 0x2d759,
- BNXT_ULP_CLASS_HID_2573d = 0x2573d,
- BNXT_ULP_CLASS_HID_279bd = 0x279bd,
- BNXT_ULP_CLASS_HID_2f27d = 0x2f27d,
- BNXT_ULP_CLASS_HID_2e4fd = 0x2e4fd,
- BNXT_ULP_CLASS_HID_24fbe = 0x24fbe,
- BNXT_ULP_CLASS_HID_201fa = 0x201fa,
- BNXT_ULP_CLASS_HID_2ecf6 = 0x2ecf6,
- BNXT_ULP_CLASS_HID_2a732 = 0x2a732,
- BNXT_ULP_CLASS_HID_25e52 = 0x25e52,
- BNXT_ULP_CLASS_HID_2509e = 0x2509e,
- BNXT_ULP_CLASS_HID_2c45e = 0x2c45e,
- BNXT_ULP_CLASS_HID_2f5d6 = 0x2f5d6,
- BNXT_ULP_CLASS_HID_23722 = 0x23722,
- BNXT_ULP_CLASS_HID_209ae = 0x209ae,
- BNXT_ULP_CLASS_HID_2d4ba = 0x2d4ba,
- BNXT_ULP_CLASS_HID_2aea6 = 0x2aea6,
- BNXT_ULP_CLASS_HID_24606 = 0x24606,
- BNXT_ULP_CLASS_HID_25802 = 0x25802,
- BNXT_ULP_CLASS_HID_2cc02 = 0x2cc02,
- BNXT_ULP_CLASS_HID_2fd9a = 0x2fd9a,
- BNXT_ULP_CLASS_HID_207c2 = 0x207c2,
- BNXT_ULP_CLASS_HID_2315a = 0x2315a,
- BNXT_ULP_CLASS_HID_2a51a = 0x2a51a,
- BNXT_ULP_CLASS_HID_2d692 = 0x2d692,
- BNXT_ULP_CLASS_HID_25686 = 0x25686,
- BNXT_ULP_CLASS_HID_2401e = 0x2401e,
- BNXT_ULP_CLASS_HID_2cbde = 0x2cbde,
- BNXT_ULP_CLASS_HID_2ce1a = 0x2ce1a,
- BNXT_ULP_CLASS_HID_20f96 = 0x20f96,
- BNXT_ULP_CLASS_HID_2390e = 0x2390e,
- BNXT_ULP_CLASS_HID_2ac8e = 0x2ac8e,
- BNXT_ULP_CLASS_HID_2de06 = 0x2de06,
- BNXT_ULP_CLASS_HID_25e0a = 0x25e0a,
- BNXT_ULP_CLASS_HID_24f82 = 0x24f82,
- BNXT_ULP_CLASS_HID_2f382 = 0x2f382,
- BNXT_ULP_CLASS_HID_2ed1a = 0x2ed1a,
- BNXT_ULP_CLASS_HID_2576e = 0x2576e,
- BNXT_ULP_CLASS_HID_229aa = 0x229aa,
- BNXT_ULP_CLASS_HID_29d6a = 0x29d6a,
- BNXT_ULP_CLASS_HID_2cee2 = 0x2cee2,
- BNXT_ULP_CLASS_HID_24ec6 = 0x24ec6,
- BNXT_ULP_CLASS_HID_2784e = 0x2784e,
- BNXT_ULP_CLASS_HID_2ec0e = 0x2ec0e,
- BNXT_ULP_CLASS_HID_2dd86 = 0x2dd86,
- BNXT_ULP_CLASS_HID_25f22 = 0x25f22,
- BNXT_ULP_CLASS_HID_2112e = 0x2112e,
- BNXT_ULP_CLASS_HID_2852e = 0x2852e,
- BNXT_ULP_CLASS_HID_2b6a6 = 0x2b6a6,
- BNXT_ULP_CLASS_HID_26d86 = 0x26d86,
- BNXT_ULP_CLASS_HID_26002 = 0x26002,
- BNXT_ULP_CLASS_HID_2eb82 = 0x2eb82,
- BNXT_ULP_CLASS_HID_2c50a = 0x2c50a,
- BNXT_ULP_CLASS_HID_22f82 = 0x22f82,
- BNXT_ULP_CLASS_HID_2590a = 0x2590a,
- BNXT_ULP_CLASS_HID_2ccca = 0x2ccca,
- BNXT_ULP_CLASS_HID_28706 = 0x28706,
- BNXT_ULP_CLASS_HID_27e46 = 0x27e46,
- BNXT_ULP_CLASS_HID_26fce = 0x26fce,
- BNXT_ULP_CLASS_HID_2d38e = 0x2d38e,
- BNXT_ULP_CLASS_HID_2d5ca = 0x2d5ca,
- BNXT_ULP_CLASS_HID_21706 = 0x21706,
- BNXT_ULP_CLASS_HID_2408e = 0x2408e,
- BNXT_ULP_CLASS_HID_2b48e = 0x2b48e,
- BNXT_ULP_CLASS_HID_28e8a = 0x28e8a,
- BNXT_ULP_CLASS_HID_2660a = 0x2660a,
- BNXT_ULP_CLASS_HID_25782 = 0x25782,
- BNXT_ULP_CLASS_HID_2db02 = 0x2db02,
- BNXT_ULP_CLASS_HID_2dd8e = 0x2dd8e,
- BNXT_ULP_CLASS_HID_25b9e = 0x25b9e,
- BNXT_ULP_CLASS_HID_21dda = 0x21dda,
- BNXT_ULP_CLASS_HID_2819a = 0x2819a,
- BNXT_ULP_CLASS_HID_2b31a = 0x2b31a,
- BNXT_ULP_CLASS_HID_26a3a = 0x26a3a,
- BNXT_ULP_CLASS_HID_26c7e = 0x26c7e,
- BNXT_ULP_CLASS_HID_2d03e = 0x2d03e,
- BNXT_ULP_CLASS_HID_2c1be = 0x2c1be,
- BNXT_ULP_CLASS_HID_2430a = 0x2430a,
- BNXT_ULP_CLASS_HID_2058e = 0x2058e,
- BNXT_ULP_CLASS_HID_2890e = 0x2890e,
- BNXT_ULP_CLASS_HID_2ba8e = 0x2ba8e,
- BNXT_ULP_CLASS_HID_251ae = 0x251ae,
- BNXT_ULP_CLASS_HID_2542a = 0x2542a,
- BNXT_ULP_CLASS_HID_2dfaa = 0x2dfaa,
- BNXT_ULP_CLASS_HID_2c93a = 0x2c93a,
- BNXT_ULP_CLASS_HID_213ca = 0x213ca,
- BNXT_ULP_CLASS_HID_24d5a = 0x24d5a,
- BNXT_ULP_CLASS_HID_2b11a = 0x2b11a,
- BNXT_ULP_CLASS_HID_28b4e = 0x28b4e,
- BNXT_ULP_CLASS_HID_2624e = 0x2624e,
- BNXT_ULP_CLASS_HID_253de = 0x253de,
- BNXT_ULP_CLASS_HID_2c79e = 0x2c79e,
- BNXT_ULP_CLASS_HID_2d9da = 0x2d9da,
- BNXT_ULP_CLASS_HID_21b1e = 0x21b1e,
- BNXT_ULP_CLASS_HID_2350e = 0x2350e,
- BNXT_ULP_CLASS_HID_2b88e = 0x2b88e,
- BNXT_ULP_CLASS_HID_2ea0e = 0x2ea0e,
- BNXT_ULP_CLASS_HID_26a0a = 0x26a0a,
- BNXT_ULP_CLASS_HID_25b8a = 0x25b8a,
- BNXT_ULP_CLASS_HID_2cf0a = 0x2cf0a,
- BNXT_ULP_CLASS_HID_2c18e = 0x2c18e,
- BNXT_ULP_CLASS_HID_2634e = 0x2634e,
- BNXT_ULP_CLASS_HID_2258a = 0x2258a,
- BNXT_ULP_CLASS_HID_2a94a = 0x2a94a,
- BNXT_ULP_CLASS_HID_2daca = 0x2daca,
- BNXT_ULP_CLASS_HID_25aae = 0x25aae,
- BNXT_ULP_CLASS_HID_2742e = 0x2742e,
- BNXT_ULP_CLASS_HID_2ffee = 0x2ffee,
- BNXT_ULP_CLASS_HID_2e96e = 0x2e96e,
- BNXT_ULP_CLASS_HID_26b0a = 0x26b0a,
- BNXT_ULP_CLASS_HID_22d0e = 0x22d0e,
- BNXT_ULP_CLASS_HID_2910e = 0x2910e,
- BNXT_ULP_CLASS_HID_2c28e = 0x2c28e,
- BNXT_ULP_CLASS_HID_2422a = 0x2422a,
- BNXT_ULP_CLASS_HID_273aa = 0x273aa,
- BNXT_ULP_CLASS_HID_2e7aa = 0x2e7aa,
- BNXT_ULP_CLASS_HID_2d12a = 0x2d12a,
- BNXT_ULP_CLASS_HID_23b8a = 0x23b8a,
- BNXT_ULP_CLASS_HID_2550a = 0x2550a,
- BNXT_ULP_CLASS_HID_2d8ca = 0x2d8ca,
- BNXT_ULP_CLASS_HID_2930e = 0x2930e,
- BNXT_ULP_CLASS_HID_24a0e = 0x24a0e,
- BNXT_ULP_CLASS_HID_24c4a = 0x24c4a,
- BNXT_ULP_CLASS_HID_2ef4e = 0x2ef4e,
- BNXT_ULP_CLASS_HID_2e18a = 0x2e18a,
- BNXT_ULP_CLASS_HID_2230e = 0x2230e,
- BNXT_ULP_CLASS_HID_25c8e = 0x25c8e,
- BNXT_ULP_CLASS_HID_2c08e = 0x2c08e,
- BNXT_ULP_CLASS_HID_29a8a = 0x29a8a,
- BNXT_ULP_CLASS_HID_2718a = 0x2718a,
- BNXT_ULP_CLASS_HID_2630a = 0x2630a,
- BNXT_ULP_CLASS_HID_2d70a = 0x2d70a,
- BNXT_ULP_CLASS_HID_2e90e = 0x2e90e,
- BNXT_ULP_CLASS_HID_24e91 = 0x24e91,
- BNXT_ULP_CLASS_HID_200d5 = 0x200d5,
- BNXT_ULP_CLASS_HID_2edd9 = 0x2edd9,
- BNXT_ULP_CLASS_HID_2a61d = 0x2a61d,
- BNXT_ULP_CLASS_HID_25f7d = 0x25f7d,
- BNXT_ULP_CLASS_HID_251b1 = 0x251b1,
- BNXT_ULP_CLASS_HID_2c571 = 0x2c571,
- BNXT_ULP_CLASS_HID_2f4f9 = 0x2f4f9,
- BNXT_ULP_CLASS_HID_25641 = 0x25641,
- BNXT_ULP_CLASS_HID_22885 = 0x22885,
- BNXT_ULP_CLASS_HID_29c45 = 0x29c45,
- BNXT_ULP_CLASS_HID_2cfcd = 0x2cfcd,
- BNXT_ULP_CLASS_HID_24fe9 = 0x24fe9,
- BNXT_ULP_CLASS_HID_27961 = 0x27961,
- BNXT_ULP_CLASS_HID_2ed21 = 0x2ed21,
- BNXT_ULP_CLASS_HID_2dca9 = 0x2dca9,
- BNXT_ULP_CLASS_HID_25ab1 = 0x25ab1,
- BNXT_ULP_CLASS_HID_21cf5 = 0x21cf5,
- BNXT_ULP_CLASS_HID_280b5 = 0x280b5,
- BNXT_ULP_CLASS_HID_2b235 = 0x2b235,
- BNXT_ULP_CLASS_HID_26b15 = 0x26b15,
- BNXT_ULP_CLASS_HID_26d51 = 0x26d51,
- BNXT_ULP_CLASS_HID_2d111 = 0x2d111,
- BNXT_ULP_CLASS_HID_2c091 = 0x2c091,
- BNXT_ULP_CLASS_HID_26261 = 0x26261,
- BNXT_ULP_CLASS_HID_224a5 = 0x224a5,
- BNXT_ULP_CLASS_HID_2a865 = 0x2a865,
- BNXT_ULP_CLASS_HID_2dbe5 = 0x2dbe5,
- BNXT_ULP_CLASS_HID_25b81 = 0x25b81,
- BNXT_ULP_CLASS_HID_27501 = 0x27501,
- BNXT_ULP_CLASS_HID_2fec1 = 0x2fec1,
- BNXT_ULP_CLASS_HID_2e841 = 0x2e841,
- BNXT_ULP_CLASS_HID_24085 = 0x24085,
- BNXT_ULP_CLASS_HID_21ac5 = 0x21ac5,
- BNXT_ULP_CLASS_HID_28e85 = 0x28e85,
- BNXT_ULP_CLASS_HID_2b80d = 0x2b80d,
- BNXT_ULP_CLASS_HID_2516d = 0x2516d,
- BNXT_ULP_CLASS_HID_26ba5 = 0x26ba5,
- BNXT_ULP_CLASS_HID_2df65 = 0x2df65,
- BNXT_ULP_CLASS_HID_2ceed = 0x2ceed,
- BNXT_ULP_CLASS_HID_26845 = 0x26845,
- BNXT_ULP_CLASS_HID_22285 = 0x22285,
- BNXT_ULP_CLASS_HID_29645 = 0x29645,
- BNXT_ULP_CLASS_HID_2c1cd = 0x2c1cd,
- BNXT_ULP_CLASS_HID_2418d = 0x2418d,
- BNXT_ULP_CLASS_HID_27365 = 0x27365,
- BNXT_ULP_CLASS_HID_2e725 = 0x2e725,
- BNXT_ULP_CLASS_HID_2d6ad = 0x2d6ad,
- BNXT_ULP_CLASS_HID_25ca5 = 0x25ca5,
- BNXT_ULP_CLASS_HID_216e5 = 0x216e5,
- BNXT_ULP_CLASS_HID_29aa5 = 0x29aa5,
- BNXT_ULP_CLASS_HID_2b425 = 0x2b425,
- BNXT_ULP_CLASS_HID_26d05 = 0x26d05,
- BNXT_ULP_CLASS_HID_26745 = 0x26745,
- BNXT_ULP_CLASS_HID_2eb05 = 0x2eb05,
- BNXT_ULP_CLASS_HID_2da85 = 0x2da85,
- BNXT_ULP_CLASS_HID_20cc5 = 0x20cc5,
- BNXT_ULP_CLASS_HID_23ea5 = 0x23ea5,
- BNXT_ULP_CLASS_HID_2a265 = 0x2a265,
- BNXT_ULP_CLASS_HID_2dde5 = 0x2dde5,
- BNXT_ULP_CLASS_HID_25da5 = 0x25da5,
- BNXT_ULP_CLASS_HID_24f05 = 0x24f05,
- BNXT_ULP_CLASS_HID_2f0c5 = 0x2f0c5,
- BNXT_ULP_CLASS_HID_2e245 = 0x2e245,
- BNXT_ULP_CLASS_HID_24d8b = 0x24d8b,
- BNXT_ULP_CLASS_HID_207cf = 0x207cf,
- BNXT_ULP_CLASS_HID_28b8f = 0x28b8f,
- BNXT_ULP_CLASS_HID_2a517 = 0x2a517,
- BNXT_ULP_CLASS_HID_25277 = 0x25277,
- BNXT_ULP_CLASS_HID_254ab = 0x254ab,
- BNXT_ULP_CLASS_HID_2d86b = 0x2d86b,
- BNXT_ULP_CLASS_HID_2cbf3 = 0x2cbf3,
- BNXT_ULP_CLASS_HID_2554b = 0x2554b,
- BNXT_ULP_CLASS_HID_22f8f = 0x22f8f,
- BNXT_ULP_CLASS_HID_2934f = 0x2934f,
- BNXT_ULP_CLASS_HID_2c2c7 = 0x2c2c7,
- BNXT_ULP_CLASS_HID_242e3 = 0x242e3,
- BNXT_ULP_CLASS_HID_27c6b = 0x27c6b,
- BNXT_ULP_CLASS_HID_2e02b = 0x2e02b,
- BNXT_ULP_CLASS_HID_2d3a3 = 0x2d3a3,
- BNXT_ULP_CLASS_HID_259a3 = 0x259a3,
- BNXT_ULP_CLASS_HID_213e7 = 0x213e7,
- BNXT_ULP_CLASS_HID_287a7 = 0x287a7,
- BNXT_ULP_CLASS_HID_2b137 = 0x2b137,
- BNXT_ULP_CLASS_HID_26e17 = 0x26e17,
- BNXT_ULP_CLASS_HID_26043 = 0x26043,
- BNXT_ULP_CLASS_HID_2d403 = 0x2d403,
- BNXT_ULP_CLASS_HID_2c793 = 0x2c793,
- BNXT_ULP_CLASS_HID_20827 = 0x20827,
- BNXT_ULP_CLASS_HID_23ba7 = 0x23ba7,
- BNXT_ULP_CLASS_HID_2af67 = 0x2af67,
- BNXT_ULP_CLASS_HID_2dee7 = 0x2dee7,
- BNXT_ULP_CLASS_HID_25e83 = 0x25e83,
- BNXT_ULP_CLASS_HID_24803 = 0x24803,
- BNXT_ULP_CLASS_HID_2fdc3 = 0x2fdc3,
- BNXT_ULP_CLASS_HID_2ef43 = 0x2ef43,
- BNXT_ULP_CLASS_HID_247bf = 0x247bf,
- BNXT_ULP_CLASS_HID_219ff = 0x219ff,
- BNXT_ULP_CLASS_HID_28dbf = 0x28dbf,
- BNXT_ULP_CLASS_HID_2bf07 = 0x2bf07,
- BNXT_ULP_CLASS_HID_25467 = 0x25467,
- BNXT_ULP_CLASS_HID_26e5f = 0x26e5f,
- BNXT_ULP_CLASS_HID_2d21f = 0x2d21f,
- BNXT_ULP_CLASS_HID_2cde7 = 0x2cde7,
- BNXT_ULP_CLASS_HID_26f6f = 0x26f6f,
- BNXT_ULP_CLASS_HID_221af = 0x221af,
- BNXT_ULP_CLASS_HID_2956f = 0x2956f,
- BNXT_ULP_CLASS_HID_2c4c7 = 0x2c4c7,
- BNXT_ULP_CLASS_HID_24487 = 0x24487,
- BNXT_ULP_CLASS_HID_2760f = 0x2760f,
- BNXT_ULP_CLASS_HID_2fbcf = 0x2fbcf,
- BNXT_ULP_CLASS_HID_2d5a7 = 0x2d5a7,
- BNXT_ULP_CLASS_HID_25357 = 0x25357,
- BNXT_ULP_CLASS_HID_21597 = 0x21597,
- BNXT_ULP_CLASS_HID_29957 = 0x29957,
- BNXT_ULP_CLASS_HID_2cb27 = 0x2cb27,
- BNXT_ULP_CLASS_HID_248f7 = 0x248f7,
- BNXT_ULP_CLASS_HID_27a77 = 0x27a77,
- BNXT_ULP_CLASS_HID_2ee37 = 0x2ee37,
- BNXT_ULP_CLASS_HID_2d987 = 0x2d987,
- BNXT_ULP_CLASS_HID_203c7 = 0x203c7,
- BNXT_ULP_CLASS_HID_23d47 = 0x23d47,
- BNXT_ULP_CLASS_HID_2a107 = 0x2a107,
- BNXT_ULP_CLASS_HID_2d0e7 = 0x2d0e7,
- BNXT_ULP_CLASS_HID_250a7 = 0x250a7,
- BNXT_ULP_CLASS_HID_24227 = 0x24227,
- BNXT_ULP_CLASS_HID_2f7e7 = 0x2f7e7,
- BNXT_ULP_CLASS_HID_2c827 = 0x2c827,
- BNXT_ULP_CLASS_HID_25422 = 0x25422,
- BNXT_ULP_CLASS_HID_21a66 = 0x21a66,
- BNXT_ULP_CLASS_HID_2f76a = 0x2f76a,
- BNXT_ULP_CLASS_HID_2bcae = 0x2bcae,
- BNXT_ULP_CLASS_HID_245ce = 0x245ce,
- BNXT_ULP_CLASS_HID_24b02 = 0x24b02,
- BNXT_ULP_CLASS_HID_2dfc2 = 0x2dfc2,
- BNXT_ULP_CLASS_HID_2ee4a = 0x2ee4a,
- BNXT_ULP_CLASS_HID_22cbe = 0x22cbe,
- BNXT_ULP_CLASS_HID_21232 = 0x21232,
- BNXT_ULP_CLASS_HID_2cf26 = 0x2cf26,
- BNXT_ULP_CLASS_HID_2b53a = 0x2b53a,
- BNXT_ULP_CLASS_HID_25d9a = 0x25d9a,
- BNXT_ULP_CLASS_HID_2439e = 0x2439e,
- BNXT_ULP_CLASS_HID_2d79e = 0x2d79e,
- BNXT_ULP_CLASS_HID_2e606 = 0x2e606,
- BNXT_ULP_CLASS_HID_21c5e = 0x21c5e,
- BNXT_ULP_CLASS_HID_22ac6 = 0x22ac6,
- BNXT_ULP_CLASS_HID_2be86 = 0x2be86,
- BNXT_ULP_CLASS_HID_2cd0e = 0x2cd0e,
- BNXT_ULP_CLASS_HID_24d1a = 0x24d1a,
- BNXT_ULP_CLASS_HID_25b82 = 0x25b82,
- BNXT_ULP_CLASS_HID_2d042 = 0x2d042,
- BNXT_ULP_CLASS_HID_2d586 = 0x2d586,
- BNXT_ULP_CLASS_HID_2140a = 0x2140a,
- BNXT_ULP_CLASS_HID_22292 = 0x22292,
- BNXT_ULP_CLASS_HID_2b712 = 0x2b712,
- BNXT_ULP_CLASS_HID_2c59a = 0x2c59a,
- BNXT_ULP_CLASS_HID_24596 = 0x24596,
- BNXT_ULP_CLASS_HID_2541e = 0x2541e,
- BNXT_ULP_CLASS_HID_2e81e = 0x2e81e,
- BNXT_ULP_CLASS_HID_2f686 = 0x2f686,
- BNXT_ULP_CLASS_HID_24cf2 = 0x24cf2,
- BNXT_ULP_CLASS_HID_23236 = 0x23236,
- BNXT_ULP_CLASS_HID_286f6 = 0x286f6,
- BNXT_ULP_CLASS_HID_2d57e = 0x2d57e,
- BNXT_ULP_CLASS_HID_2555a = 0x2555a,
- BNXT_ULP_CLASS_HID_263d2 = 0x263d2,
- BNXT_ULP_CLASS_HID_2f792 = 0x2f792,
- BNXT_ULP_CLASS_HID_2c61a = 0x2c61a,
- BNXT_ULP_CLASS_HID_244be = 0x244be,
- BNXT_ULP_CLASS_HID_20ab2 = 0x20ab2,
- BNXT_ULP_CLASS_HID_29eb2 = 0x29eb2,
- BNXT_ULP_CLASS_HID_2ad3a = 0x2ad3a,
- BNXT_ULP_CLASS_HID_2761a = 0x2761a,
- BNXT_ULP_CLASS_HID_27b9e = 0x27b9e,
- BNXT_ULP_CLASS_HID_2f01e = 0x2f01e,
- BNXT_ULP_CLASS_HID_2de96 = 0x2de96,
- BNXT_ULP_CLASS_HID_2341e = 0x2341e,
- BNXT_ULP_CLASS_HID_24296 = 0x24296,
- BNXT_ULP_CLASS_HID_2d756 = 0x2d756,
- BNXT_ULP_CLASS_HID_29c9a = 0x29c9a,
- BNXT_ULP_CLASS_HID_265da = 0x265da,
- BNXT_ULP_CLASS_HID_27452 = 0x27452,
- BNXT_ULP_CLASS_HID_2c812 = 0x2c812,
- BNXT_ULP_CLASS_HID_2ce56 = 0x2ce56,
- BNXT_ULP_CLASS_HID_20c9a = 0x20c9a,
- BNXT_ULP_CLASS_HID_25b12 = 0x25b12,
- BNXT_ULP_CLASS_HID_2af12 = 0x2af12,
- BNXT_ULP_CLASS_HID_29516 = 0x29516,
- BNXT_ULP_CLASS_HID_27d96 = 0x27d96,
- BNXT_ULP_CLASS_HID_24c1e = 0x24c1e,
- BNXT_ULP_CLASS_HID_2c09e = 0x2c09e,
- BNXT_ULP_CLASS_HID_2c612 = 0x2c612,
- BNXT_ULP_CLASS_HID_24002 = 0x24002,
- BNXT_ULP_CLASS_HID_20646 = 0x20646,
- BNXT_ULP_CLASS_HID_29a06 = 0x29a06,
- BNXT_ULP_CLASS_HID_2a886 = 0x2a886,
- BNXT_ULP_CLASS_HID_271a6 = 0x271a6,
- BNXT_ULP_CLASS_HID_277e2 = 0x277e2,
- BNXT_ULP_CLASS_HID_2cba2 = 0x2cba2,
- BNXT_ULP_CLASS_HID_2da22 = 0x2da22,
- BNXT_ULP_CLASS_HID_25896 = 0x25896,
- BNXT_ULP_CLASS_HID_21e12 = 0x21e12,
- BNXT_ULP_CLASS_HID_29292 = 0x29292,
- BNXT_ULP_CLASS_HID_2a112 = 0x2a112,
- BNXT_ULP_CLASS_HID_24a32 = 0x24a32,
- BNXT_ULP_CLASS_HID_24fb6 = 0x24fb6,
- BNXT_ULP_CLASS_HID_2c436 = 0x2c436,
- BNXT_ULP_CLASS_HID_2d2a6 = 0x2d2a6,
- BNXT_ULP_CLASS_HID_20856 = 0x20856,
- BNXT_ULP_CLASS_HID_256c6 = 0x256c6,
- BNXT_ULP_CLASS_HID_2aa86 = 0x2aa86,
- BNXT_ULP_CLASS_HID_290d2 = 0x290d2,
- BNXT_ULP_CLASS_HID_279d2 = 0x279d2,
- BNXT_ULP_CLASS_HID_24842 = 0x24842,
- BNXT_ULP_CLASS_HID_2dc02 = 0x2dc02,
- BNXT_ULP_CLASS_HID_2c246 = 0x2c246,
- BNXT_ULP_CLASS_HID_20082 = 0x20082,
- BNXT_ULP_CLASS_HID_22e92 = 0x22e92,
- BNXT_ULP_CLASS_HID_2a312 = 0x2a312,
- BNXT_ULP_CLASS_HID_2f192 = 0x2f192,
- BNXT_ULP_CLASS_HID_27196 = 0x27196,
- BNXT_ULP_CLASS_HID_24016 = 0x24016,
- BNXT_ULP_CLASS_HID_2d496 = 0x2d496,
- BNXT_ULP_CLASS_HID_2da12 = 0x2da12,
- BNXT_ULP_CLASS_HID_278d2 = 0x278d2,
- BNXT_ULP_CLASS_HID_23e16 = 0x23e16,
- BNXT_ULP_CLASS_HID_2b2d6 = 0x2b2d6,
- BNXT_ULP_CLASS_HID_2c156 = 0x2c156,
- BNXT_ULP_CLASS_HID_24132 = 0x24132,
- BNXT_ULP_CLASS_HID_26fb2 = 0x26fb2,
- BNXT_ULP_CLASS_HID_2e472 = 0x2e472,
- BNXT_ULP_CLASS_HID_2f2f2 = 0x2f2f2,
- BNXT_ULP_CLASS_HID_27096 = 0x27096,
- BNXT_ULP_CLASS_HID_23692 = 0x23692,
- BNXT_ULP_CLASS_HID_28a92 = 0x28a92,
- BNXT_ULP_CLASS_HID_2d912 = 0x2d912,
- BNXT_ULP_CLASS_HID_259b6 = 0x259b6,
- BNXT_ULP_CLASS_HID_26836 = 0x26836,
- BNXT_ULP_CLASS_HID_2fc36 = 0x2fc36,
- BNXT_ULP_CLASS_HID_2cab6 = 0x2cab6,
- BNXT_ULP_CLASS_HID_22016 = 0x22016,
- BNXT_ULP_CLASS_HID_24e96 = 0x24e96,
- BNXT_ULP_CLASS_HID_2c356 = 0x2c356,
- BNXT_ULP_CLASS_HID_28892 = 0x28892,
- BNXT_ULP_CLASS_HID_25192 = 0x25192,
- BNXT_ULP_CLASS_HID_257d6 = 0x257d6,
- BNXT_ULP_CLASS_HID_2f4d2 = 0x2f4d2,
- BNXT_ULP_CLASS_HID_2fa16 = 0x2fa16,
- BNXT_ULP_CLASS_HID_23892 = 0x23892,
- BNXT_ULP_CLASS_HID_24712 = 0x24712,
- BNXT_ULP_CLASS_HID_2db12 = 0x2db12,
- BNXT_ULP_CLASS_HID_28116 = 0x28116,
- BNXT_ULP_CLASS_HID_26a16 = 0x26a16,
- BNXT_ULP_CLASS_HID_27896 = 0x27896,
- BNXT_ULP_CLASS_HID_2cc96 = 0x2cc96,
- BNXT_ULP_CLASS_HID_2f292 = 0x2f292,
- BNXT_ULP_CLASS_HID_24b05 = 0x24b05,
- BNXT_ULP_CLASS_HID_20541 = 0x20541,
- BNXT_ULP_CLASS_HID_2e84d = 0x2e84d,
- BNXT_ULP_CLASS_HID_2a389 = 0x2a389,
- BNXT_ULP_CLASS_HID_25ae9 = 0x25ae9,
- BNXT_ULP_CLASS_HID_25425 = 0x25425,
- BNXT_ULP_CLASS_HID_2c0e5 = 0x2c0e5,
- BNXT_ULP_CLASS_HID_2f16d = 0x2f16d,
- BNXT_ULP_CLASS_HID_253d5 = 0x253d5,
- BNXT_ULP_CLASS_HID_22d11 = 0x22d11,
- BNXT_ULP_CLASS_HID_299d1 = 0x299d1,
- BNXT_ULP_CLASS_HID_2ca59 = 0x2ca59,
- BNXT_ULP_CLASS_HID_24a7d = 0x24a7d,
- BNXT_ULP_CLASS_HID_27cf5 = 0x27cf5,
- BNXT_ULP_CLASS_HID_2e8b5 = 0x2e8b5,
- BNXT_ULP_CLASS_HID_2d93d = 0x2d93d,
- BNXT_ULP_CLASS_HID_25f25 = 0x25f25,
- BNXT_ULP_CLASS_HID_21961 = 0x21961,
- BNXT_ULP_CLASS_HID_28521 = 0x28521,
- BNXT_ULP_CLASS_HID_2b7a1 = 0x2b7a1,
- BNXT_ULP_CLASS_HID_26e81 = 0x26e81,
- BNXT_ULP_CLASS_HID_268c5 = 0x268c5,
- BNXT_ULP_CLASS_HID_2d485 = 0x2d485,
- BNXT_ULP_CLASS_HID_2c505 = 0x2c505,
- BNXT_ULP_CLASS_HID_267f5 = 0x267f5,
- BNXT_ULP_CLASS_HID_22131 = 0x22131,
- BNXT_ULP_CLASS_HID_2adf1 = 0x2adf1,
- BNXT_ULP_CLASS_HID_2de71 = 0x2de71,
- BNXT_ULP_CLASS_HID_25e15 = 0x25e15,
- BNXT_ULP_CLASS_HID_27095 = 0x27095,
- BNXT_ULP_CLASS_HID_2fb55 = 0x2fb55,
- BNXT_ULP_CLASS_HID_2edd5 = 0x2edd5,
- BNXT_ULP_CLASS_HID_24511 = 0x24511,
- BNXT_ULP_CLASS_HID_21f51 = 0x21f51,
- BNXT_ULP_CLASS_HID_28b11 = 0x28b11,
- BNXT_ULP_CLASS_HID_2bd99 = 0x2bd99,
- BNXT_ULP_CLASS_HID_254f9 = 0x254f9,
- BNXT_ULP_CLASS_HID_26e31 = 0x26e31,
- BNXT_ULP_CLASS_HID_2daf1 = 0x2daf1,
- BNXT_ULP_CLASS_HID_2cb79 = 0x2cb79,
- BNXT_ULP_CLASS_HID_26dd1 = 0x26dd1,
- BNXT_ULP_CLASS_HID_22711 = 0x22711,
- BNXT_ULP_CLASS_HID_293d1 = 0x293d1,
- BNXT_ULP_CLASS_HID_2c459 = 0x2c459,
- BNXT_ULP_CLASS_HID_24419 = 0x24419,
- BNXT_ULP_CLASS_HID_276f1 = 0x276f1,
- BNXT_ULP_CLASS_HID_2e2b1 = 0x2e2b1,
- BNXT_ULP_CLASS_HID_2d339 = 0x2d339,
- BNXT_ULP_CLASS_HID_25931 = 0x25931,
- BNXT_ULP_CLASS_HID_21371 = 0x21371,
- BNXT_ULP_CLASS_HID_29f31 = 0x29f31,
- BNXT_ULP_CLASS_HID_2b1b1 = 0x2b1b1,
- BNXT_ULP_CLASS_HID_26891 = 0x26891,
- BNXT_ULP_CLASS_HID_262d1 = 0x262d1,
- BNXT_ULP_CLASS_HID_2ee91 = 0x2ee91,
- BNXT_ULP_CLASS_HID_2df11 = 0x2df11,
- BNXT_ULP_CLASS_HID_20951 = 0x20951,
- BNXT_ULP_CLASS_HID_23b31 = 0x23b31,
- BNXT_ULP_CLASS_HID_2a7f1 = 0x2a7f1,
- BNXT_ULP_CLASS_HID_2d871 = 0x2d871,
- BNXT_ULP_CLASS_HID_25831 = 0x25831,
- BNXT_ULP_CLASS_HID_24a91 = 0x24a91,
- BNXT_ULP_CLASS_HID_2f551 = 0x2f551,
- BNXT_ULP_CLASS_HID_2e7d1 = 0x2e7d1,
- BNXT_ULP_CLASS_HID_2481f = 0x2481f,
- BNXT_ULP_CLASS_HID_2025b = 0x2025b,
- BNXT_ULP_CLASS_HID_28e1b = 0x28e1b,
- BNXT_ULP_CLASS_HID_2a083 = 0x2a083,
- BNXT_ULP_CLASS_HID_257e3 = 0x257e3,
- BNXT_ULP_CLASS_HID_2513f = 0x2513f,
- BNXT_ULP_CLASS_HID_2ddff = 0x2ddff,
- BNXT_ULP_CLASS_HID_2ce67 = 0x2ce67,
- BNXT_ULP_CLASS_HID_250df = 0x250df,
- BNXT_ULP_CLASS_HID_22a1b = 0x22a1b,
- BNXT_ULP_CLASS_HID_296db = 0x296db,
- BNXT_ULP_CLASS_HID_2c753 = 0x2c753,
- BNXT_ULP_CLASS_HID_24777 = 0x24777,
- BNXT_ULP_CLASS_HID_279ff = 0x279ff,
- BNXT_ULP_CLASS_HID_2e5bf = 0x2e5bf,
- BNXT_ULP_CLASS_HID_2d637 = 0x2d637,
- BNXT_ULP_CLASS_HID_25c37 = 0x25c37,
- BNXT_ULP_CLASS_HID_21673 = 0x21673,
- BNXT_ULP_CLASS_HID_28233 = 0x28233,
- BNXT_ULP_CLASS_HID_2b4a3 = 0x2b4a3,
- BNXT_ULP_CLASS_HID_26b83 = 0x26b83,
- BNXT_ULP_CLASS_HID_265d7 = 0x265d7,
- BNXT_ULP_CLASS_HID_2d197 = 0x2d197,
- BNXT_ULP_CLASS_HID_2c207 = 0x2c207,
- BNXT_ULP_CLASS_HID_20db3 = 0x20db3,
- BNXT_ULP_CLASS_HID_23e33 = 0x23e33,
- BNXT_ULP_CLASS_HID_2aaf3 = 0x2aaf3,
- BNXT_ULP_CLASS_HID_2db73 = 0x2db73,
- BNXT_ULP_CLASS_HID_25b17 = 0x25b17,
- BNXT_ULP_CLASS_HID_24d97 = 0x24d97,
- BNXT_ULP_CLASS_HID_2f857 = 0x2f857,
- BNXT_ULP_CLASS_HID_2ead7 = 0x2ead7,
- BNXT_ULP_CLASS_HID_2422b = 0x2422b,
- BNXT_ULP_CLASS_HID_21c6b = 0x21c6b,
- BNXT_ULP_CLASS_HID_2882b = 0x2882b,
- BNXT_ULP_CLASS_HID_2ba93 = 0x2ba93,
- BNXT_ULP_CLASS_HID_251f3 = 0x251f3,
- BNXT_ULP_CLASS_HID_26bcb = 0x26bcb,
- BNXT_ULP_CLASS_HID_2d78b = 0x2d78b,
- BNXT_ULP_CLASS_HID_2c873 = 0x2c873,
- BNXT_ULP_CLASS_HID_26afb = 0x26afb,
- BNXT_ULP_CLASS_HID_2243b = 0x2243b,
- BNXT_ULP_CLASS_HID_290fb = 0x290fb,
- BNXT_ULP_CLASS_HID_2c153 = 0x2c153,
- BNXT_ULP_CLASS_HID_24113 = 0x24113,
- BNXT_ULP_CLASS_HID_2739b = 0x2739b,
- BNXT_ULP_CLASS_HID_2fe5b = 0x2fe5b,
- BNXT_ULP_CLASS_HID_2d033 = 0x2d033,
- BNXT_ULP_CLASS_HID_256c3 = 0x256c3,
- BNXT_ULP_CLASS_HID_21003 = 0x21003,
- BNXT_ULP_CLASS_HID_29cc3 = 0x29cc3,
- BNXT_ULP_CLASS_HID_2ceb3 = 0x2ceb3,
- BNXT_ULP_CLASS_HID_24d63 = 0x24d63,
- BNXT_ULP_CLASS_HID_27fe3 = 0x27fe3,
- BNXT_ULP_CLASS_HID_2eba3 = 0x2eba3,
- BNXT_ULP_CLASS_HID_2dc13 = 0x2dc13,
- BNXT_ULP_CLASS_HID_20653 = 0x20653,
- BNXT_ULP_CLASS_HID_238d3 = 0x238d3,
- BNXT_ULP_CLASS_HID_2a493 = 0x2a493,
- BNXT_ULP_CLASS_HID_2d573 = 0x2d573,
- BNXT_ULP_CLASS_HID_25533 = 0x25533,
- BNXT_ULP_CLASS_HID_247b3 = 0x247b3,
- BNXT_ULP_CLASS_HID_2f273 = 0x2f273,
- BNXT_ULP_CLASS_HID_2cdb3 = 0x2cdb3,
- BNXT_ULP_CLASS_HID_25c7d = 0x25c7d,
- BNXT_ULP_CLASS_HID_21239 = 0x21239,
- BNXT_ULP_CLASS_HID_2ff35 = 0x2ff35,
- BNXT_ULP_CLASS_HID_2b4f1 = 0x2b4f1,
- BNXT_ULP_CLASS_HID_24d91 = 0x24d91,
- BNXT_ULP_CLASS_HID_2435d = 0x2435d,
- BNXT_ULP_CLASS_HID_2d79d = 0x2d79d,
- BNXT_ULP_CLASS_HID_2e615 = 0x2e615,
- BNXT_ULP_CLASS_HID_244ad = 0x244ad,
- BNXT_ULP_CLASS_HID_23a69 = 0x23a69,
- BNXT_ULP_CLASS_HID_28ea9 = 0x28ea9,
- BNXT_ULP_CLASS_HID_2dd21 = 0x2dd21,
- BNXT_ULP_CLASS_HID_25d05 = 0x25d05,
- BNXT_ULP_CLASS_HID_26b8d = 0x26b8d,
- BNXT_ULP_CLASS_HID_2ffcd = 0x2ffcd,
- BNXT_ULP_CLASS_HID_2ce45 = 0x2ce45,
- BNXT_ULP_CLASS_HID_2485d = 0x2485d,
- BNXT_ULP_CLASS_HID_20e19 = 0x20e19,
- BNXT_ULP_CLASS_HID_29259 = 0x29259,
- BNXT_ULP_CLASS_HID_2a0d9 = 0x2a0d9,
- BNXT_ULP_CLASS_HID_279f9 = 0x279f9,
- BNXT_ULP_CLASS_HID_27fbd = 0x27fbd,
- BNXT_ULP_CLASS_HID_2c3fd = 0x2c3fd,
- BNXT_ULP_CLASS_HID_2d27d = 0x2d27d,
- BNXT_ULP_CLASS_HID_2708d = 0x2708d,
- BNXT_ULP_CLASS_HID_23649 = 0x23649,
- BNXT_ULP_CLASS_HID_2ba89 = 0x2ba89,
- BNXT_ULP_CLASS_HID_2c909 = 0x2c909,
- BNXT_ULP_CLASS_HID_2496d = 0x2496d,
- BNXT_ULP_CLASS_HID_267ed = 0x267ed,
- BNXT_ULP_CLASS_HID_2ec2d = 0x2ec2d,
- BNXT_ULP_CLASS_HID_2faad = 0x2faad,
- BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
- BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
- BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
- BNXT_ULP_CLASS_HID_179a = 0x179a,
- BNXT_ULP_CLASS_HID_59be = 0x59be,
- BNXT_ULP_CLASS_HID_515a = 0x515a,
- BNXT_ULP_CLASS_HID_1c72 = 0x1c72,
- BNXT_ULP_CLASS_HID_171e = 0x171e,
- BNXT_ULP_CLASS_HID_19c8 = 0x19c8,
- BNXT_ULP_CLASS_HID_112c = 0x112c,
- BNXT_ULP_CLASS_HID_4d68 = 0x4d68,
- BNXT_ULP_CLASS_HID_444c = 0x444c,
- BNXT_ULP_CLASS_HID_0e8c = 0x0e8c,
- BNXT_ULP_CLASS_HID_09e0 = 0x09e0,
- BNXT_ULP_CLASS_HID_1af0 = 0x1af0,
- BNXT_ULP_CLASS_HID_15d4 = 0x15d4,
- BNXT_ULP_CLASS_HID_1dd0 = 0x1dd0,
- BNXT_ULP_CLASS_HID_14f4 = 0x14f4,
- BNXT_ULP_CLASS_HID_70b0 = 0x70b0,
- BNXT_ULP_CLASS_HID_4854 = 0x4854,
- BNXT_ULP_CLASS_HID_3dd4 = 0x3dd4,
- BNXT_ULP_CLASS_HID_34f8 = 0x34f8,
- BNXT_ULP_CLASS_HID_09e8 = 0x09e8,
- BNXT_ULP_CLASS_HID_008c = 0x008c,
- BNXT_ULP_CLASS_HID_34e6 = 0x34e6,
- BNXT_ULP_CLASS_HID_0c02 = 0x0c02,
- BNXT_ULP_CLASS_HID_1c9e = 0x1c9e,
- BNXT_ULP_CLASS_HID_17ba = 0x17ba,
- BNXT_ULP_CLASS_HID_429e = 0x429e,
- BNXT_ULP_CLASS_HID_5dba = 0x5dba,
- BNXT_ULP_CLASS_HID_2a16 = 0x2a16,
- BNXT_ULP_CLASS_HID_2532 = 0x2532,
- BNXT_ULP_CLASS_HID_2da2 = 0x2da2,
- BNXT_ULP_CLASS_HID_24fe = 0x24fe,
- BNXT_ULP_CLASS_HID_355a = 0x355a,
- BNXT_ULP_CLASS_HID_0c76 = 0x0c76,
- BNXT_ULP_CLASS_HID_13e6 = 0x13e6,
- BNXT_ULP_CLASS_HID_7276 = 0x7276,
- BNXT_ULP_CLASS_HID_42d2 = 0x42d2,
- BNXT_ULP_CLASS_HID_5dee = 0x5dee,
- BNXT_ULP_CLASS_HID_59de = 0x59de,
- BNXT_ULP_CLASS_HID_513a = 0x513a,
- BNXT_ULP_CLASS_HID_1c12 = 0x1c12,
- BNXT_ULP_CLASS_HID_177e = 0x177e,
- BNXT_ULP_CLASS_HID_0e92 = 0x0e92,
- BNXT_ULP_CLASS_HID_09fe = 0x09fe,
- BNXT_ULP_CLASS_HID_5c1a = 0x5c1a,
- BNXT_ULP_CLASS_HID_5746 = 0x5746,
- BNXT_ULP_CLASS_HID_79da = 0x79da,
- BNXT_ULP_CLASS_HID_7106 = 0x7106,
- BNXT_ULP_CLASS_HID_3c1e = 0x3c1e,
- BNXT_ULP_CLASS_HID_377a = 0x377a,
- BNXT_ULP_CLASS_HID_2e9e = 0x2e9e,
- BNXT_ULP_CLASS_HID_29fa = 0x29fa,
- BNXT_ULP_CLASS_HID_14d2 = 0x14d2,
- BNXT_ULP_CLASS_HID_7742 = 0x7742,
- BNXT_ULP_CLASS_HID_3706 = 0x3706,
- BNXT_ULP_CLASS_HID_0fe2 = 0x0fe2,
- BNXT_ULP_CLASS_HID_1f7e = 0x1f7e,
- BNXT_ULP_CLASS_HID_145a = 0x145a,
- BNXT_ULP_CLASS_HID_417e = 0x417e,
- BNXT_ULP_CLASS_HID_5e5a = 0x5e5a,
- BNXT_ULP_CLASS_HID_29f6 = 0x29f6,
- BNXT_ULP_CLASS_HID_26d2 = 0x26d2,
- BNXT_ULP_CLASS_HID_2e42 = 0x2e42,
- BNXT_ULP_CLASS_HID_271e = 0x271e,
- BNXT_ULP_CLASS_HID_36ba = 0x36ba,
- BNXT_ULP_CLASS_HID_0f96 = 0x0f96,
- BNXT_ULP_CLASS_HID_1006 = 0x1006,
- BNXT_ULP_CLASS_HID_7196 = 0x7196,
- BNXT_ULP_CLASS_HID_4132 = 0x4132,
- BNXT_ULP_CLASS_HID_5e0e = 0x5e0e,
- BNXT_ULP_CLASS_HID_59fe = 0x59fe,
- BNXT_ULP_CLASS_HID_511a = 0x511a,
- BNXT_ULP_CLASS_HID_1c32 = 0x1c32,
- BNXT_ULP_CLASS_HID_175e = 0x175e,
- BNXT_ULP_CLASS_HID_0eb2 = 0x0eb2,
- BNXT_ULP_CLASS_HID_09de = 0x09de,
- BNXT_ULP_CLASS_HID_5c3a = 0x5c3a,
- BNXT_ULP_CLASS_HID_5766 = 0x5766,
- BNXT_ULP_CLASS_HID_79fa = 0x79fa,
- BNXT_ULP_CLASS_HID_7126 = 0x7126,
- BNXT_ULP_CLASS_HID_3c3e = 0x3c3e,
- BNXT_ULP_CLASS_HID_375a = 0x375a,
- BNXT_ULP_CLASS_HID_2ebe = 0x2ebe,
- BNXT_ULP_CLASS_HID_29da = 0x29da,
- BNXT_ULP_CLASS_HID_14f2 = 0x14f2,
- BNXT_ULP_CLASS_HID_7762 = 0x7762,
- BNXT_ULP_CLASS_HID_19e8 = 0x19e8,
- BNXT_ULP_CLASS_HID_110c = 0x110c,
- BNXT_ULP_CLASS_HID_4d48 = 0x4d48,
- BNXT_ULP_CLASS_HID_446c = 0x446c,
- BNXT_ULP_CLASS_HID_0eac = 0x0eac,
- BNXT_ULP_CLASS_HID_09c0 = 0x09c0,
- BNXT_ULP_CLASS_HID_1ad0 = 0x1ad0,
- BNXT_ULP_CLASS_HID_15f4 = 0x15f4,
- BNXT_ULP_CLASS_HID_39ec = 0x39ec,
- BNXT_ULP_CLASS_HID_3100 = 0x3100,
- BNXT_ULP_CLASS_HID_0210 = 0x0210,
- BNXT_ULP_CLASS_HID_1d34 = 0x1d34,
- BNXT_ULP_CLASS_HID_2ea0 = 0x2ea0,
- BNXT_ULP_CLASS_HID_29c4 = 0x29c4,
- BNXT_ULP_CLASS_HID_3ad4 = 0x3ad4,
- BNXT_ULP_CLASS_HID_35e8 = 0x35e8,
- BNXT_ULP_CLASS_HID_5d80 = 0x5d80,
- BNXT_ULP_CLASS_HID_54a4 = 0x54a4,
- BNXT_ULP_CLASS_HID_29b4 = 0x29b4,
- BNXT_ULP_CLASS_HID_20c8 = 0x20c8,
- BNXT_ULP_CLASS_HID_7244 = 0x7244,
- BNXT_ULP_CLASS_HID_4d98 = 0x4d98,
- BNXT_ULP_CLASS_HID_5e68 = 0x5e68,
- BNXT_ULP_CLASS_HID_598c = 0x598c,
- BNXT_ULP_CLASS_HID_1248 = 0x1248,
- BNXT_ULP_CLASS_HID_74d8 = 0x74d8,
- BNXT_ULP_CLASS_HID_49a8 = 0x49a8,
- BNXT_ULP_CLASS_HID_40cc = 0x40cc,
- BNXT_ULP_CLASS_HID_0b0c = 0x0b0c,
- BNXT_ULP_CLASS_HID_0220 = 0x0220,
- BNXT_ULP_CLASS_HID_1730 = 0x1730,
- BNXT_ULP_CLASS_HID_7980 = 0x7980,
- BNXT_ULP_CLASS_HID_1db0 = 0x1db0,
- BNXT_ULP_CLASS_HID_1494 = 0x1494,
- BNXT_ULP_CLASS_HID_70d0 = 0x70d0,
- BNXT_ULP_CLASS_HID_4834 = 0x4834,
- BNXT_ULP_CLASS_HID_3db4 = 0x3db4,
- BNXT_ULP_CLASS_HID_3498 = 0x3498,
- BNXT_ULP_CLASS_HID_0988 = 0x0988,
- BNXT_ULP_CLASS_HID_00ec = 0x00ec,
- BNXT_ULP_CLASS_HID_23f44 = 0x23f44,
- BNXT_ULP_CLASS_HID_236a8 = 0x236a8,
- BNXT_ULP_CLASS_HID_20b58 = 0x20b58,
- BNXT_ULP_CLASS_HID_202bc = 0x202bc,
- BNXT_ULP_CLASS_HID_25f48 = 0x25f48,
- BNXT_ULP_CLASS_HID_256ac = 0x256ac,
- BNXT_ULP_CLASS_HID_22b5c = 0x22b5c,
- BNXT_ULP_CLASS_HID_22280 = 0x22280,
- BNXT_ULP_CLASS_HID_14000 = 0x14000,
- BNXT_ULP_CLASS_HID_15b64 = 0x15b64,
- BNXT_ULP_CLASS_HID_12c14 = 0x12c14,
- BNXT_ULP_CLASS_HID_12778 = 0x12778,
- BNXT_ULP_CLASS_HID_118f8 = 0x118f8,
- BNXT_ULP_CLASS_HID_113dc = 0x113dc,
- BNXT_ULP_CLASS_HID_14c18 = 0x14c18,
- BNXT_ULP_CLASS_HID_1477c = 0x1477c,
- BNXT_ULP_CLASS_HID_31a88 = 0x31a88,
- BNXT_ULP_CLASS_HID_315ec = 0x315ec,
- BNXT_ULP_CLASS_HID_34e28 = 0x34e28,
- BNXT_ULP_CLASS_HID_3490c = 0x3490c,
- BNXT_ULP_CLASS_HID_33a8c = 0x33a8c,
- BNXT_ULP_CLASS_HID_335f0 = 0x335f0,
- BNXT_ULP_CLASS_HID_306e0 = 0x306e0,
- BNXT_ULP_CLASS_HID_301c4 = 0x301c4,
- BNXT_ULP_CLASS_HID_1a08 = 0x1a08,
- BNXT_ULP_CLASS_HID_12ec = 0x12ec,
- BNXT_ULP_CLASS_HID_4ea8 = 0x4ea8,
- BNXT_ULP_CLASS_HID_478c = 0x478c,
- BNXT_ULP_CLASS_HID_0d4c = 0x0d4c,
- BNXT_ULP_CLASS_HID_0a20 = 0x0a20,
- BNXT_ULP_CLASS_HID_1930 = 0x1930,
- BNXT_ULP_CLASS_HID_1614 = 0x1614,
- BNXT_ULP_CLASS_HID_3a0c = 0x3a0c,
- BNXT_ULP_CLASS_HID_32e0 = 0x32e0,
- BNXT_ULP_CLASS_HID_01f0 = 0x01f0,
- BNXT_ULP_CLASS_HID_1ed4 = 0x1ed4,
- BNXT_ULP_CLASS_HID_2d40 = 0x2d40,
- BNXT_ULP_CLASS_HID_2a24 = 0x2a24,
- BNXT_ULP_CLASS_HID_3934 = 0x3934,
- BNXT_ULP_CLASS_HID_3608 = 0x3608,
- BNXT_ULP_CLASS_HID_5e60 = 0x5e60,
- BNXT_ULP_CLASS_HID_5744 = 0x5744,
- BNXT_ULP_CLASS_HID_2a54 = 0x2a54,
- BNXT_ULP_CLASS_HID_2328 = 0x2328,
- BNXT_ULP_CLASS_HID_71a4 = 0x71a4,
- BNXT_ULP_CLASS_HID_4e78 = 0x4e78,
- BNXT_ULP_CLASS_HID_5d88 = 0x5d88,
- BNXT_ULP_CLASS_HID_5a6c = 0x5a6c,
- BNXT_ULP_CLASS_HID_11a8 = 0x11a8,
- BNXT_ULP_CLASS_HID_7738 = 0x7738,
- BNXT_ULP_CLASS_HID_4a48 = 0x4a48,
- BNXT_ULP_CLASS_HID_432c = 0x432c,
- BNXT_ULP_CLASS_HID_08ec = 0x08ec,
- BNXT_ULP_CLASS_HID_01c0 = 0x01c0,
- BNXT_ULP_CLASS_HID_14d0 = 0x14d0,
- BNXT_ULP_CLASS_HID_7a60 = 0x7a60,
- BNXT_ULP_CLASS_HID_1d90 = 0x1d90,
- BNXT_ULP_CLASS_HID_14b4 = 0x14b4,
- BNXT_ULP_CLASS_HID_70f0 = 0x70f0,
- BNXT_ULP_CLASS_HID_4814 = 0x4814,
- BNXT_ULP_CLASS_HID_3d94 = 0x3d94,
- BNXT_ULP_CLASS_HID_34b8 = 0x34b8,
- BNXT_ULP_CLASS_HID_09a8 = 0x09a8,
- BNXT_ULP_CLASS_HID_00cc = 0x00cc,
- BNXT_ULP_CLASS_HID_23f64 = 0x23f64,
- BNXT_ULP_CLASS_HID_23688 = 0x23688,
- BNXT_ULP_CLASS_HID_20b78 = 0x20b78,
- BNXT_ULP_CLASS_HID_2029c = 0x2029c,
- BNXT_ULP_CLASS_HID_25f68 = 0x25f68,
- BNXT_ULP_CLASS_HID_2568c = 0x2568c,
- BNXT_ULP_CLASS_HID_22b7c = 0x22b7c,
- BNXT_ULP_CLASS_HID_222a0 = 0x222a0,
- BNXT_ULP_CLASS_HID_14020 = 0x14020,
- BNXT_ULP_CLASS_HID_15b44 = 0x15b44,
- BNXT_ULP_CLASS_HID_12c34 = 0x12c34,
- BNXT_ULP_CLASS_HID_12758 = 0x12758,
- BNXT_ULP_CLASS_HID_118d8 = 0x118d8,
- BNXT_ULP_CLASS_HID_113fc = 0x113fc,
- BNXT_ULP_CLASS_HID_14c38 = 0x14c38,
- BNXT_ULP_CLASS_HID_1475c = 0x1475c,
- BNXT_ULP_CLASS_HID_31aa8 = 0x31aa8,
- BNXT_ULP_CLASS_HID_315cc = 0x315cc,
- BNXT_ULP_CLASS_HID_34e08 = 0x34e08,
- BNXT_ULP_CLASS_HID_3492c = 0x3492c,
- BNXT_ULP_CLASS_HID_33aac = 0x33aac,
- BNXT_ULP_CLASS_HID_335d0 = 0x335d0,
- BNXT_ULP_CLASS_HID_306c0 = 0x306c0,
- BNXT_ULP_CLASS_HID_301e4 = 0x301e4,
- BNXT_ULP_CLASS_HID_4d32 = 0x4d32,
- BNXT_ULP_CLASS_HID_54aa = 0x54aa,
- BNXT_ULP_CLASS_HID_0686 = 0x0686,
- BNXT_ULP_CLASS_HID_540e = 0x540e,
- BNXT_ULP_CLASS_HID_2e3c = 0x2e3c,
- BNXT_ULP_CLASS_HID_3a20 = 0x3a20,
- BNXT_ULP_CLASS_HID_46f0 = 0x46f0,
- BNXT_ULP_CLASS_HID_52e4 = 0x52e4,
- BNXT_ULP_CLASS_HID_55e4 = 0x55e4,
- BNXT_ULP_CLASS_HID_21f8 = 0x21f8,
- BNXT_ULP_CLASS_HID_75e8 = 0x75e8,
- BNXT_ULP_CLASS_HID_41fc = 0x41fc,
- BNXT_ULP_CLASS_HID_4d12 = 0x4d12,
- BNXT_ULP_CLASS_HID_548a = 0x548a,
- BNXT_ULP_CLASS_HID_3356 = 0x3356,
- BNXT_ULP_CLASS_HID_1ace = 0x1ace,
- BNXT_ULP_CLASS_HID_1a9a = 0x1a9a,
- BNXT_ULP_CLASS_HID_4d46 = 0x4d46,
- BNXT_ULP_CLASS_HID_2812 = 0x2812,
- BNXT_ULP_CLASS_HID_338a = 0x338a,
- BNXT_ULP_CLASS_HID_06e6 = 0x06e6,
- BNXT_ULP_CLASS_HID_546e = 0x546e,
- BNXT_ULP_CLASS_HID_46ee = 0x46ee,
- BNXT_ULP_CLASS_HID_0d22 = 0x0d22,
- BNXT_ULP_CLASS_HID_26e2 = 0x26e2,
- BNXT_ULP_CLASS_HID_746a = 0x746a,
- BNXT_ULP_CLASS_HID_1fa6 = 0x1fa6,
- BNXT_ULP_CLASS_HID_2d2e = 0x2d2e,
- BNXT_ULP_CLASS_HID_4ef2 = 0x4ef2,
- BNXT_ULP_CLASS_HID_576a = 0x576a,
- BNXT_ULP_CLASS_HID_30b6 = 0x30b6,
- BNXT_ULP_CLASS_HID_192e = 0x192e,
- BNXT_ULP_CLASS_HID_197a = 0x197a,
- BNXT_ULP_CLASS_HID_4ea6 = 0x4ea6,
- BNXT_ULP_CLASS_HID_2bf2 = 0x2bf2,
- BNXT_ULP_CLASS_HID_306a = 0x306a,
- BNXT_ULP_CLASS_HID_06c6 = 0x06c6,
- BNXT_ULP_CLASS_HID_544e = 0x544e,
- BNXT_ULP_CLASS_HID_46ce = 0x46ce,
- BNXT_ULP_CLASS_HID_0d02 = 0x0d02,
- BNXT_ULP_CLASS_HID_26c2 = 0x26c2,
- BNXT_ULP_CLASS_HID_744a = 0x744a,
- BNXT_ULP_CLASS_HID_1f86 = 0x1f86,
- BNXT_ULP_CLASS_HID_2d0e = 0x2d0e,
- BNXT_ULP_CLASS_HID_2e1c = 0x2e1c,
- BNXT_ULP_CLASS_HID_3a00 = 0x3a00,
- BNXT_ULP_CLASS_HID_46d0 = 0x46d0,
- BNXT_ULP_CLASS_HID_52c4 = 0x52c4,
- BNXT_ULP_CLASS_HID_4e10 = 0x4e10,
- BNXT_ULP_CLASS_HID_5a04 = 0x5a04,
- BNXT_ULP_CLASS_HID_1f98 = 0x1f98,
- BNXT_ULP_CLASS_HID_72f8 = 0x72f8,
- BNXT_ULP_CLASS_HID_0a78 = 0x0a78,
- BNXT_ULP_CLASS_HID_166c = 0x166c,
- BNXT_ULP_CLASS_HID_233c = 0x233c,
- BNXT_ULP_CLASS_HID_0f20 = 0x0f20,
- BNXT_ULP_CLASS_HID_2a7c = 0x2a7c,
- BNXT_ULP_CLASS_HID_3660 = 0x3660,
- BNXT_ULP_CLASS_HID_4330 = 0x4330,
- BNXT_ULP_CLASS_HID_2f24 = 0x2f24,
- BNXT_ULP_CLASS_HID_5584 = 0x5584,
- BNXT_ULP_CLASS_HID_2198 = 0x2198,
- BNXT_ULP_CLASS_HID_7588 = 0x7588,
- BNXT_ULP_CLASS_HID_419c = 0x419c,
- BNXT_ULP_CLASS_HID_27758 = 0x27758,
- BNXT_ULP_CLASS_HID_243ac = 0x243ac,
- BNXT_ULP_CLASS_HID_20c10 = 0x20c10,
- BNXT_ULP_CLASS_HID_21864 = 0x21864,
- BNXT_ULP_CLASS_HID_130c8 = 0x130c8,
- BNXT_ULP_CLASS_HID_11cdc = 0x11cdc,
- BNXT_ULP_CLASS_HID_150cc = 0x150cc,
- BNXT_ULP_CLASS_HID_13d20 = 0x13d20,
- BNXT_ULP_CLASS_HID_3529c = 0x3529c,
- BNXT_ULP_CLASS_HID_33ef0 = 0x33ef0,
- BNXT_ULP_CLASS_HID_372e0 = 0x372e0,
- BNXT_ULP_CLASS_HID_35ef4 = 0x35ef4,
- BNXT_ULP_CLASS_HID_2dfc = 0x2dfc,
- BNXT_ULP_CLASS_HID_39e0 = 0x39e0,
- BNXT_ULP_CLASS_HID_4530 = 0x4530,
- BNXT_ULP_CLASS_HID_5124 = 0x5124,
- BNXT_ULP_CLASS_HID_4df0 = 0x4df0,
- BNXT_ULP_CLASS_HID_59e4 = 0x59e4,
- BNXT_ULP_CLASS_HID_1c78 = 0x1c78,
- BNXT_ULP_CLASS_HID_7118 = 0x7118,
- BNXT_ULP_CLASS_HID_0998 = 0x0998,
- BNXT_ULP_CLASS_HID_158c = 0x158c,
- BNXT_ULP_CLASS_HID_20dc = 0x20dc,
- BNXT_ULP_CLASS_HID_0cc0 = 0x0cc0,
- BNXT_ULP_CLASS_HID_299c = 0x299c,
- BNXT_ULP_CLASS_HID_3580 = 0x3580,
- BNXT_ULP_CLASS_HID_40d0 = 0x40d0,
- BNXT_ULP_CLASS_HID_2cc4 = 0x2cc4,
- BNXT_ULP_CLASS_HID_55a4 = 0x55a4,
- BNXT_ULP_CLASS_HID_21b8 = 0x21b8,
- BNXT_ULP_CLASS_HID_75a8 = 0x75a8,
- BNXT_ULP_CLASS_HID_41bc = 0x41bc,
- BNXT_ULP_CLASS_HID_27778 = 0x27778,
- BNXT_ULP_CLASS_HID_2438c = 0x2438c,
- BNXT_ULP_CLASS_HID_20c30 = 0x20c30,
- BNXT_ULP_CLASS_HID_21844 = 0x21844,
- BNXT_ULP_CLASS_HID_130e8 = 0x130e8,
- BNXT_ULP_CLASS_HID_11cfc = 0x11cfc,
- BNXT_ULP_CLASS_HID_150ec = 0x150ec,
- BNXT_ULP_CLASS_HID_13d00 = 0x13d00,
- BNXT_ULP_CLASS_HID_352bc = 0x352bc,
- BNXT_ULP_CLASS_HID_33ed0 = 0x33ed0,
- BNXT_ULP_CLASS_HID_372c0 = 0x372c0,
- BNXT_ULP_CLASS_HID_35ed4 = 0x35ed4,
- BNXT_ULP_CLASS_HID_3866 = 0x3866,
- BNXT_ULP_CLASS_HID_381e = 0x381e,
- BNXT_ULP_CLASS_HID_3860 = 0x3860,
- BNXT_ULP_CLASS_HID_0454 = 0x0454,
- BNXT_ULP_CLASS_HID_3818 = 0x3818,
- BNXT_ULP_CLASS_HID_042c = 0x042c,
- BNXT_ULP_CLASS_HID_3846 = 0x3846,
- BNXT_ULP_CLASS_HID_387e = 0x387e,
- BNXT_ULP_CLASS_HID_3ba6 = 0x3ba6,
- BNXT_ULP_CLASS_HID_385e = 0x385e,
- BNXT_ULP_CLASS_HID_3840 = 0x3840,
- BNXT_ULP_CLASS_HID_0474 = 0x0474,
- BNXT_ULP_CLASS_HID_3878 = 0x3878,
- BNXT_ULP_CLASS_HID_044c = 0x044c,
- BNXT_ULP_CLASS_HID_3ba0 = 0x3ba0,
- BNXT_ULP_CLASS_HID_0794 = 0x0794,
- BNXT_ULP_CLASS_HID_3858 = 0x3858,
- BNXT_ULP_CLASS_HID_046c = 0x046c
+ BNXT_ULP_CLASS_HID_00b8 = 0x00b8,
+ BNXT_ULP_CLASS_HID_0cc2 = 0x0cc2,
+ BNXT_ULP_CLASS_HID_10e4 = 0x10e4,
+ BNXT_ULP_CLASS_HID_1d0e = 0x1d0e,
+ BNXT_ULP_CLASS_HID_0286 = 0x0286,
+ BNXT_ULP_CLASS_HID_0e98 = 0x0e98,
+ BNXT_ULP_CLASS_HID_1666 = 0x1666,
+ BNXT_ULP_CLASS_HID_02de = 0x02de,
+ BNXT_ULP_CLASS_HID_81d25 = 0x81d25,
+ BNXT_ULP_CLASS_HID_809ad = 0x809ad,
+ BNXT_ULP_CLASS_HID_80ae3 = 0x80ae3,
+ BNXT_ULP_CLASS_HID_8170d = 0x8170d,
+ BNXT_ULP_CLASS_HID_80773 = 0x80773,
+ BNXT_ULP_CLASS_HID_8139d = 0x8139d,
+ BNXT_ULP_CLASS_HID_814d3 = 0x814d3,
+ BNXT_ULP_CLASS_HID_8015b = 0x8015b,
+ BNXT_ULP_CLASS_HID_21977 = 0x21977,
+ BNXT_ULP_CLASS_HID_205ef = 0x205ef,
+ BNXT_ULP_CLASS_HID_20735 = 0x20735,
+ BNXT_ULP_CLASS_HID_2134f = 0x2134f,
+ BNXT_ULP_CLASS_HID_61beb = 0x61beb,
+ BNXT_ULP_CLASS_HID_60863 = 0x60863,
+ BNXT_ULP_CLASS_HID_609a9 = 0x609a9,
+ BNXT_ULP_CLASS_HID_615c3 = 0x615c3,
+ BNXT_ULP_CLASS_HID_00a8 = 0x00a8,
+ BNXT_ULP_CLASS_HID_0cd2 = 0x0cd2,
+ BNXT_ULP_CLASS_HID_10f4 = 0x10f4,
+ BNXT_ULP_CLASS_HID_1d1e = 0x1d1e,
+ BNXT_ULP_CLASS_HID_1488 = 0x1488,
+ BNXT_ULP_CLASS_HID_0110 = 0x0110,
+ BNXT_ULP_CLASS_HID_0532 = 0x0532,
+ BNXT_ULP_CLASS_HID_115c = 0x115c,
+ BNXT_ULP_CLASS_HID_0ab8 = 0x0ab8,
+ BNXT_ULP_CLASS_HID_16a2 = 0x16a2,
+ BNXT_ULP_CLASS_HID_1ac4 = 0x1ac4,
+ BNXT_ULP_CLASS_HID_074c = 0x074c,
+ BNXT_ULP_CLASS_HID_1e98 = 0x1e98,
+ BNXT_ULP_CLASS_HID_0ae0 = 0x0ae0,
+ BNXT_ULP_CLASS_HID_0f02 = 0x0f02,
+ BNXT_ULP_CLASS_HID_1b2c = 0x1b2c,
+ BNXT_ULP_CLASS_HID_0296 = 0x0296,
+ BNXT_ULP_CLASS_HID_0e88 = 0x0e88,
+ BNXT_ULP_CLASS_HID_1676 = 0x1676,
+ BNXT_ULP_CLASS_HID_02ce = 0x02ce,
+ BNXT_ULP_CLASS_HID_8076e = 0x8076e,
+ BNXT_ULP_CLASS_HID_81380 = 0x81380,
+ BNXT_ULP_CLASS_HID_81b4e = 0x81b4e,
+ BNXT_ULP_CLASS_HID_807c6 = 0x807c6,
+ BNXT_ULP_CLASS_HID_404ea = 0x404ea,
+ BNXT_ULP_CLASS_HID_4110c = 0x4110c,
+ BNXT_ULP_CLASS_HID_418ca = 0x418ca,
+ BNXT_ULP_CLASS_HID_40542 = 0x40542,
+ BNXT_ULP_CLASS_HID_c09e2 = 0xc09e2,
+ BNXT_ULP_CLASS_HID_c1604 = 0xc1604,
+ BNXT_ULP_CLASS_HID_c1dc2 = 0xc1dc2,
+ BNXT_ULP_CLASS_HID_c0a5a = 0xc0a5a,
+ BNXT_ULP_CLASS_HID_0098 = 0x0098,
+ BNXT_ULP_CLASS_HID_0ce2 = 0x0ce2,
+ BNXT_ULP_CLASS_HID_10c4 = 0x10c4,
+ BNXT_ULP_CLASS_HID_1d2e = 0x1d2e,
+ BNXT_ULP_CLASS_HID_14b8 = 0x14b8,
+ BNXT_ULP_CLASS_HID_0120 = 0x0120,
+ BNXT_ULP_CLASS_HID_0502 = 0x0502,
+ BNXT_ULP_CLASS_HID_116c = 0x116c,
+ BNXT_ULP_CLASS_HID_0a88 = 0x0a88,
+ BNXT_ULP_CLASS_HID_1692 = 0x1692,
+ BNXT_ULP_CLASS_HID_1af4 = 0x1af4,
+ BNXT_ULP_CLASS_HID_077c = 0x077c,
+ BNXT_ULP_CLASS_HID_1ea8 = 0x1ea8,
+ BNXT_ULP_CLASS_HID_0ad0 = 0x0ad0,
+ BNXT_ULP_CLASS_HID_0f32 = 0x0f32,
+ BNXT_ULP_CLASS_HID_1b1c = 0x1b1c,
+ BNXT_ULP_CLASS_HID_02a6 = 0x02a6,
+ BNXT_ULP_CLASS_HID_0eb8 = 0x0eb8,
+ BNXT_ULP_CLASS_HID_1646 = 0x1646,
+ BNXT_ULP_CLASS_HID_02fe = 0x02fe,
+ BNXT_ULP_CLASS_HID_8075e = 0x8075e,
+ BNXT_ULP_CLASS_HID_813b0 = 0x813b0,
+ BNXT_ULP_CLASS_HID_81b7e = 0x81b7e,
+ BNXT_ULP_CLASS_HID_807f6 = 0x807f6,
+ BNXT_ULP_CLASS_HID_404da = 0x404da,
+ BNXT_ULP_CLASS_HID_4113c = 0x4113c,
+ BNXT_ULP_CLASS_HID_418fa = 0x418fa,
+ BNXT_ULP_CLASS_HID_40572 = 0x40572,
+ BNXT_ULP_CLASS_HID_c09d2 = 0xc09d2,
+ BNXT_ULP_CLASS_HID_c1634 = 0xc1634,
+ BNXT_ULP_CLASS_HID_c1df2 = 0xc1df2,
+ BNXT_ULP_CLASS_HID_c0a6a = 0xc0a6a,
+ BNXT_ULP_CLASS_HID_81d35 = 0x81d35,
+ BNXT_ULP_CLASS_HID_809bd = 0x809bd,
+ BNXT_ULP_CLASS_HID_80af3 = 0x80af3,
+ BNXT_ULP_CLASS_HID_8171d = 0x8171d,
+ BNXT_ULP_CLASS_HID_80763 = 0x80763,
+ BNXT_ULP_CLASS_HID_8138d = 0x8138d,
+ BNXT_ULP_CLASS_HID_814c3 = 0x814c3,
+ BNXT_ULP_CLASS_HID_8014b = 0x8014b,
+ BNXT_ULP_CLASS_HID_c001f = 0xc001f,
+ BNXT_ULP_CLASS_HID_c0c39 = 0xc0c39,
+ BNXT_ULP_CLASS_HID_c0d7f = 0xc0d7f,
+ BNXT_ULP_CLASS_HID_c1999 = 0xc1999,
+ BNXT_ULP_CLASS_HID_c09ef = 0xc09ef,
+ BNXT_ULP_CLASS_HID_c1609 = 0xc1609,
+ BNXT_ULP_CLASS_HID_c174f = 0xc174f,
+ BNXT_ULP_CLASS_HID_c03d7 = 0xc03d7,
+ BNXT_ULP_CLASS_HID_a1e73 = 0xa1e73,
+ BNXT_ULP_CLASS_HID_a0afb = 0xa0afb,
+ BNXT_ULP_CLASS_HID_a0c31 = 0xa0c31,
+ BNXT_ULP_CLASS_HID_a185b = 0xa185b,
+ BNXT_ULP_CLASS_HID_a08a1 = 0xa08a1,
+ BNXT_ULP_CLASS_HID_a14cb = 0xa14cb,
+ BNXT_ULP_CLASS_HID_a1601 = 0xa1601,
+ BNXT_ULP_CLASS_HID_a0289 = 0xa0289,
+ BNXT_ULP_CLASS_HID_e015d = 0xe015d,
+ BNXT_ULP_CLASS_HID_e0d47 = 0xe0d47,
+ BNXT_ULP_CLASS_HID_e0ebd = 0xe0ebd,
+ BNXT_ULP_CLASS_HID_e1aa7 = 0xe1aa7,
+ BNXT_ULP_CLASS_HID_e0b2d = 0xe0b2d,
+ BNXT_ULP_CLASS_HID_e1757 = 0xe1757,
+ BNXT_ULP_CLASS_HID_e188d = 0xe188d,
+ BNXT_ULP_CLASS_HID_e0515 = 0xe0515,
+ BNXT_ULP_CLASS_HID_21967 = 0x21967,
+ BNXT_ULP_CLASS_HID_205ff = 0x205ff,
+ BNXT_ULP_CLASS_HID_20725 = 0x20725,
+ BNXT_ULP_CLASS_HID_2135f = 0x2135f,
+ BNXT_ULP_CLASS_HID_61bfb = 0x61bfb,
+ BNXT_ULP_CLASS_HID_60873 = 0x60873,
+ BNXT_ULP_CLASS_HID_609b9 = 0x609b9,
+ BNXT_ULP_CLASS_HID_615d3 = 0x615d3,
+ BNXT_ULP_CLASS_HID_30a55 = 0x30a55,
+ BNXT_ULP_CLASS_HID_3164f = 0x3164f,
+ BNXT_ULP_CLASS_HID_317b5 = 0x317b5,
+ BNXT_ULP_CLASS_HID_3040d = 0x3040d,
+ BNXT_ULP_CLASS_HID_70ca9 = 0x70ca9,
+ BNXT_ULP_CLASS_HID_718c3 = 0x718c3,
+ BNXT_ULP_CLASS_HID_71a09 = 0x71a09,
+ BNXT_ULP_CLASS_HID_70681 = 0x70681,
+ BNXT_ULP_CLASS_HID_2821d = 0x2821d,
+ BNXT_ULP_CLASS_HID_28e37 = 0x28e37,
+ BNXT_ULP_CLASS_HID_28f7d = 0x28f7d,
+ BNXT_ULP_CLASS_HID_29b97 = 0x29b97,
+ BNXT_ULP_CLASS_HID_68491 = 0x68491,
+ BNXT_ULP_CLASS_HID_6908b = 0x6908b,
+ BNXT_ULP_CLASS_HID_691f1 = 0x691f1,
+ BNXT_ULP_CLASS_HID_69deb = 0x69deb,
+ BNXT_ULP_CLASS_HID_3926d = 0x3926d,
+ BNXT_ULP_CLASS_HID_39e87 = 0x39e87,
+ BNXT_ULP_CLASS_HID_38023 = 0x38023,
+ BNXT_ULP_CLASS_HID_38c45 = 0x38c45,
+ BNXT_ULP_CLASS_HID_794e1 = 0x794e1,
+ BNXT_ULP_CLASS_HID_78179 = 0x78179,
+ BNXT_ULP_CLASS_HID_782a7 = 0x782a7,
+ BNXT_ULP_CLASS_HID_78ed9 = 0x78ed9,
+ BNXT_ULP_CLASS_HID_81d05 = 0x81d05,
+ BNXT_ULP_CLASS_HID_8098d = 0x8098d,
+ BNXT_ULP_CLASS_HID_80ac3 = 0x80ac3,
+ BNXT_ULP_CLASS_HID_8172d = 0x8172d,
+ BNXT_ULP_CLASS_HID_80753 = 0x80753,
+ BNXT_ULP_CLASS_HID_813bd = 0x813bd,
+ BNXT_ULP_CLASS_HID_814f3 = 0x814f3,
+ BNXT_ULP_CLASS_HID_8017b = 0x8017b,
+ BNXT_ULP_CLASS_HID_c002f = 0xc002f,
+ BNXT_ULP_CLASS_HID_c0c09 = 0xc0c09,
+ BNXT_ULP_CLASS_HID_c0d4f = 0xc0d4f,
+ BNXT_ULP_CLASS_HID_c19a9 = 0xc19a9,
+ BNXT_ULP_CLASS_HID_c09df = 0xc09df,
+ BNXT_ULP_CLASS_HID_c1639 = 0xc1639,
+ BNXT_ULP_CLASS_HID_c177f = 0xc177f,
+ BNXT_ULP_CLASS_HID_c03e7 = 0xc03e7,
+ BNXT_ULP_CLASS_HID_a1e43 = 0xa1e43,
+ BNXT_ULP_CLASS_HID_a0acb = 0xa0acb,
+ BNXT_ULP_CLASS_HID_a0c01 = 0xa0c01,
+ BNXT_ULP_CLASS_HID_a186b = 0xa186b,
+ BNXT_ULP_CLASS_HID_a0891 = 0xa0891,
+ BNXT_ULP_CLASS_HID_a14fb = 0xa14fb,
+ BNXT_ULP_CLASS_HID_a1631 = 0xa1631,
+ BNXT_ULP_CLASS_HID_a02b9 = 0xa02b9,
+ BNXT_ULP_CLASS_HID_e016d = 0xe016d,
+ BNXT_ULP_CLASS_HID_e0d77 = 0xe0d77,
+ BNXT_ULP_CLASS_HID_e0e8d = 0xe0e8d,
+ BNXT_ULP_CLASS_HID_e1a97 = 0xe1a97,
+ BNXT_ULP_CLASS_HID_e0b1d = 0xe0b1d,
+ BNXT_ULP_CLASS_HID_e1767 = 0xe1767,
+ BNXT_ULP_CLASS_HID_e18bd = 0xe18bd,
+ BNXT_ULP_CLASS_HID_e0525 = 0xe0525,
+ BNXT_ULP_CLASS_HID_21957 = 0x21957,
+ BNXT_ULP_CLASS_HID_205cf = 0x205cf,
+ BNXT_ULP_CLASS_HID_20715 = 0x20715,
+ BNXT_ULP_CLASS_HID_2136f = 0x2136f,
+ BNXT_ULP_CLASS_HID_61bcb = 0x61bcb,
+ BNXT_ULP_CLASS_HID_60843 = 0x60843,
+ BNXT_ULP_CLASS_HID_60989 = 0x60989,
+ BNXT_ULP_CLASS_HID_615e3 = 0x615e3,
+ BNXT_ULP_CLASS_HID_30a65 = 0x30a65,
+ BNXT_ULP_CLASS_HID_3167f = 0x3167f,
+ BNXT_ULP_CLASS_HID_31785 = 0x31785,
+ BNXT_ULP_CLASS_HID_3043d = 0x3043d,
+ BNXT_ULP_CLASS_HID_70c99 = 0x70c99,
+ BNXT_ULP_CLASS_HID_718f3 = 0x718f3,
+ BNXT_ULP_CLASS_HID_71a39 = 0x71a39,
+ BNXT_ULP_CLASS_HID_706b1 = 0x706b1,
+ BNXT_ULP_CLASS_HID_2822d = 0x2822d,
+ BNXT_ULP_CLASS_HID_28e07 = 0x28e07,
+ BNXT_ULP_CLASS_HID_28f4d = 0x28f4d,
+ BNXT_ULP_CLASS_HID_29ba7 = 0x29ba7,
+ BNXT_ULP_CLASS_HID_684a1 = 0x684a1,
+ BNXT_ULP_CLASS_HID_690bb = 0x690bb,
+ BNXT_ULP_CLASS_HID_691c1 = 0x691c1,
+ BNXT_ULP_CLASS_HID_69ddb = 0x69ddb,
+ BNXT_ULP_CLASS_HID_3925d = 0x3925d,
+ BNXT_ULP_CLASS_HID_39eb7 = 0x39eb7,
+ BNXT_ULP_CLASS_HID_38013 = 0x38013,
+ BNXT_ULP_CLASS_HID_38c75 = 0x38c75,
+ BNXT_ULP_CLASS_HID_794d1 = 0x794d1,
+ BNXT_ULP_CLASS_HID_78149 = 0x78149,
+ BNXT_ULP_CLASS_HID_78297 = 0x78297,
+ BNXT_ULP_CLASS_HID_78ee9 = 0x78ee9,
+ BNXT_ULP_CLASS_HID_0816 = 0x0816,
+ BNXT_ULP_CLASS_HID_1852 = 0x1852,
+ BNXT_ULP_CLASS_HID_09f4 = 0x09f4,
+ BNXT_ULP_CLASS_HID_1dd4 = 0x1dd4,
+ BNXT_ULP_CLASS_HID_804f1 = 0x804f1,
+ BNXT_ULP_CLASS_HID_81251 = 0x81251,
+ BNXT_ULP_CLASS_HID_80ee1 = 0x80ee1,
+ BNXT_ULP_CLASS_HID_81c41 = 0x81c41,
+ BNXT_ULP_CLASS_HID_2013b = 0x2013b,
+ BNXT_ULP_CLASS_HID_20e9b = 0x20e9b,
+ BNXT_ULP_CLASS_HID_603bf = 0x603bf,
+ BNXT_ULP_CLASS_HID_6111f = 0x6111f,
+ BNXT_ULP_CLASS_HID_0806 = 0x0806,
+ BNXT_ULP_CLASS_HID_1842 = 0x1842,
+ BNXT_ULP_CLASS_HID_1be6 = 0x1be6,
+ BNXT_ULP_CLASS_HID_0c80 = 0x0c80,
+ BNXT_ULP_CLASS_HID_1216 = 0x1216,
+ BNXT_ULP_CLASS_HID_02b0 = 0x02b0,
+ BNXT_ULP_CLASS_HID_0654 = 0x0654,
+ BNXT_ULP_CLASS_HID_1690 = 0x1690,
+ BNXT_ULP_CLASS_HID_09e4 = 0x09e4,
+ BNXT_ULP_CLASS_HID_1dc4 = 0x1dc4,
+ BNXT_ULP_CLASS_HID_80efc = 0x80efc,
+ BNXT_ULP_CLASS_HID_80332 = 0x80332,
+ BNXT_ULP_CLASS_HID_40c78 = 0x40c78,
+ BNXT_ULP_CLASS_HID_400be = 0x400be,
+ BNXT_ULP_CLASS_HID_c1170 = 0xc1170,
+ BNXT_ULP_CLASS_HID_c05b6 = 0xc05b6,
+ BNXT_ULP_CLASS_HID_0836 = 0x0836,
+ BNXT_ULP_CLASS_HID_1872 = 0x1872,
+ BNXT_ULP_CLASS_HID_1bd6 = 0x1bd6,
+ BNXT_ULP_CLASS_HID_0cb0 = 0x0cb0,
+ BNXT_ULP_CLASS_HID_1226 = 0x1226,
+ BNXT_ULP_CLASS_HID_0280 = 0x0280,
+ BNXT_ULP_CLASS_HID_0664 = 0x0664,
+ BNXT_ULP_CLASS_HID_16a0 = 0x16a0,
+ BNXT_ULP_CLASS_HID_09d4 = 0x09d4,
+ BNXT_ULP_CLASS_HID_1df4 = 0x1df4,
+ BNXT_ULP_CLASS_HID_80ecc = 0x80ecc,
+ BNXT_ULP_CLASS_HID_80302 = 0x80302,
+ BNXT_ULP_CLASS_HID_40c48 = 0x40c48,
+ BNXT_ULP_CLASS_HID_4008e = 0x4008e,
+ BNXT_ULP_CLASS_HID_c1140 = 0xc1140,
+ BNXT_ULP_CLASS_HID_c0586 = 0xc0586,
+ BNXT_ULP_CLASS_HID_804e1 = 0x804e1,
+ BNXT_ULP_CLASS_HID_81241 = 0x81241,
+ BNXT_ULP_CLASS_HID_80ef1 = 0x80ef1,
+ BNXT_ULP_CLASS_HID_81c51 = 0x81c51,
+ BNXT_ULP_CLASS_HID_c076d = 0xc076d,
+ BNXT_ULP_CLASS_HID_c14cd = 0xc14cd,
+ BNXT_ULP_CLASS_HID_c117d = 0xc117d,
+ BNXT_ULP_CLASS_HID_c1edd = 0xc1edd,
+ BNXT_ULP_CLASS_HID_a062f = 0xa062f,
+ BNXT_ULP_CLASS_HID_a138f = 0xa138f,
+ BNXT_ULP_CLASS_HID_a103f = 0xa103f,
+ BNXT_ULP_CLASS_HID_a1d9f = 0xa1d9f,
+ BNXT_ULP_CLASS_HID_e08ab = 0xe08ab,
+ BNXT_ULP_CLASS_HID_e160b = 0xe160b,
+ BNXT_ULP_CLASS_HID_e12bb = 0xe12bb,
+ BNXT_ULP_CLASS_HID_e0079 = 0xe0079,
+ BNXT_ULP_CLASS_HID_2012b = 0x2012b,
+ BNXT_ULP_CLASS_HID_20e8b = 0x20e8b,
+ BNXT_ULP_CLASS_HID_603af = 0x603af,
+ BNXT_ULP_CLASS_HID_6110f = 0x6110f,
+ BNXT_ULP_CLASS_HID_311bb = 0x311bb,
+ BNXT_ULP_CLASS_HID_31f1b = 0x31f1b,
+ BNXT_ULP_CLASS_HID_7143f = 0x7143f,
+ BNXT_ULP_CLASS_HID_701fd = 0x701fd,
+ BNXT_ULP_CLASS_HID_28963 = 0x28963,
+ BNXT_ULP_CLASS_HID_296c3 = 0x296c3,
+ BNXT_ULP_CLASS_HID_68be7 = 0x68be7,
+ BNXT_ULP_CLASS_HID_69947 = 0x69947,
+ BNXT_ULP_CLASS_HID_399f3 = 0x399f3,
+ BNXT_ULP_CLASS_HID_387b1 = 0x387b1,
+ BNXT_ULP_CLASS_HID_79c77 = 0x79c77,
+ BNXT_ULP_CLASS_HID_78a35 = 0x78a35,
+ BNXT_ULP_CLASS_HID_804d1 = 0x804d1,
+ BNXT_ULP_CLASS_HID_81271 = 0x81271,
+ BNXT_ULP_CLASS_HID_80ec1 = 0x80ec1,
+ BNXT_ULP_CLASS_HID_81c61 = 0x81c61,
+ BNXT_ULP_CLASS_HID_c075d = 0xc075d,
+ BNXT_ULP_CLASS_HID_c14fd = 0xc14fd,
+ BNXT_ULP_CLASS_HID_c114d = 0xc114d,
+ BNXT_ULP_CLASS_HID_c1eed = 0xc1eed,
+ BNXT_ULP_CLASS_HID_a061f = 0xa061f,
+ BNXT_ULP_CLASS_HID_a13bf = 0xa13bf,
+ BNXT_ULP_CLASS_HID_a100f = 0xa100f,
+ BNXT_ULP_CLASS_HID_a1daf = 0xa1daf,
+ BNXT_ULP_CLASS_HID_e089b = 0xe089b,
+ BNXT_ULP_CLASS_HID_e163b = 0xe163b,
+ BNXT_ULP_CLASS_HID_e128b = 0xe128b,
+ BNXT_ULP_CLASS_HID_e0049 = 0xe0049,
+ BNXT_ULP_CLASS_HID_2011b = 0x2011b,
+ BNXT_ULP_CLASS_HID_20ebb = 0x20ebb,
+ BNXT_ULP_CLASS_HID_6039f = 0x6039f,
+ BNXT_ULP_CLASS_HID_6113f = 0x6113f,
+ BNXT_ULP_CLASS_HID_3118b = 0x3118b,
+ BNXT_ULP_CLASS_HID_31f2b = 0x31f2b,
+ BNXT_ULP_CLASS_HID_7140f = 0x7140f,
+ BNXT_ULP_CLASS_HID_701cd = 0x701cd,
+ BNXT_ULP_CLASS_HID_28953 = 0x28953,
+ BNXT_ULP_CLASS_HID_296f3 = 0x296f3,
+ BNXT_ULP_CLASS_HID_68bd7 = 0x68bd7,
+ BNXT_ULP_CLASS_HID_69977 = 0x69977,
+ BNXT_ULP_CLASS_HID_399c3 = 0x399c3,
+ BNXT_ULP_CLASS_HID_38781 = 0x38781,
+ BNXT_ULP_CLASS_HID_79c47 = 0x79c47,
+ BNXT_ULP_CLASS_HID_78a05 = 0x78a05,
+ BNXT_ULP_CLASS_HID_04a4 = 0x04a4,
+ BNXT_ULP_CLASS_HID_04a8 = 0x04a8,
+ BNXT_ULP_CLASS_HID_04a5 = 0x04a5,
+ BNXT_ULP_CLASS_HID_1205 = 0x1205,
+ BNXT_ULP_CLASS_HID_04a9 = 0x04a9,
+ BNXT_ULP_CLASS_HID_1209 = 0x1209,
+ BNXT_ULP_CLASS_HID_04b4 = 0x04b4,
+ BNXT_ULP_CLASS_HID_04b8 = 0x04b8,
+ BNXT_ULP_CLASS_HID_0484 = 0x0484,
+ BNXT_ULP_CLASS_HID_0488 = 0x0488,
+ BNXT_ULP_CLASS_HID_04b5 = 0x04b5,
+ BNXT_ULP_CLASS_HID_1215 = 0x1215,
+ BNXT_ULP_CLASS_HID_04b9 = 0x04b9,
+ BNXT_ULP_CLASS_HID_1219 = 0x1219,
+ BNXT_ULP_CLASS_HID_0485 = 0x0485,
+ BNXT_ULP_CLASS_HID_1225 = 0x1225,
+ BNXT_ULP_CLASS_HID_0489 = 0x0489,
+ BNXT_ULP_CLASS_HID_1229 = 0x1229,
+ BNXT_ULP_CLASS_HID_0226 = 0x0226,
+ BNXT_ULP_CLASS_HID_4045a = 0x4045a,
+ BNXT_ULP_CLASS_HID_0daa = 0x0daa,
+ BNXT_ULP_CLASS_HID_11b0 = 0x11b0,
+ BNXT_ULP_CLASS_HID_403f8 = 0x403f8,
+ BNXT_ULP_CLASS_HID_4161e = 0x4161e,
+ BNXT_ULP_CLASS_HID_40439 = 0x40439,
+ BNXT_ULP_CLASS_HID_41405 = 0x41405,
+ BNXT_ULP_CLASS_HID_51449 = 0x51449,
+ BNXT_ULP_CLASS_HID_50b33 = 0x50b33,
+ BNXT_ULP_CLASS_HID_48c01 = 0x48c01,
+ BNXT_ULP_CLASS_HID_483eb = 0x483eb,
+ BNXT_ULP_CLASS_HID_5833f = 0x5833f,
+ BNXT_ULP_CLASS_HID_5937b = 0x5937b,
+ BNXT_ULP_CLASS_HID_41875 = 0x41875,
+ BNXT_ULP_CLASS_HID_40f5f = 0x40f5f,
+ BNXT_ULP_CLASS_HID_50f23 = 0x50f23,
+ BNXT_ULP_CLASS_HID_51f6f = 0x51f6f,
+ BNXT_ULP_CLASS_HID_4875b = 0x4875b,
+ BNXT_ULP_CLASS_HID_49727 = 0x49727,
+ BNXT_ULP_CLASS_HID_5976b = 0x5976b,
+ BNXT_ULP_CLASS_HID_58655 = 0x58655,
+ BNXT_ULP_CLASS_HID_4125f = 0x4125f,
+ BNXT_ULP_CLASS_HID_401f9 = 0x401f9,
+ BNXT_ULP_CLASS_HID_501cd = 0x501cd,
+ BNXT_ULP_CLASS_HID_51149 = 0x51149,
+ BNXT_ULP_CLASS_HID_49a67 = 0x49a67,
+ BNXT_ULP_CLASS_HID_489c1 = 0x489c1,
+ BNXT_ULP_CLASS_HID_58955 = 0x58955,
+ BNXT_ULP_CLASS_HID_59951 = 0x59951,
+ BNXT_ULP_CLASS_HID_40569 = 0x40569,
+ BNXT_ULP_CLASS_HID_41575 = 0x41575,
+ BNXT_ULP_CLASS_HID_51579 = 0x51579,
+ BNXT_ULP_CLASS_HID_50463 = 0x50463,
+ BNXT_ULP_CLASS_HID_48d71 = 0x48d71,
+ BNXT_ULP_CLASS_HID_49d7d = 0x49d7d,
+ BNXT_ULP_CLASS_HID_59d41 = 0x59d41,
+ BNXT_ULP_CLASS_HID_58c6b = 0x58c6b,
+ BNXT_ULP_CLASS_HID_10255 = 0x10255,
+ BNXT_ULP_CLASS_HID_11675 = 0x11675,
+ BNXT_ULP_CLASS_HID_14649 = 0x14649,
+ BNXT_ULP_CLASS_HID_15a69 = 0x15a69,
+ BNXT_ULP_CLASS_HID_1205b = 0x1205b,
+ BNXT_ULP_CLASS_HID_1347b = 0x1347b,
+ BNXT_ULP_CLASS_HID_16bbf = 0x16bbf,
+ BNXT_ULP_CLASS_HID_1785f = 0x1785f,
+ BNXT_ULP_CLASS_HID_11551 = 0x11551,
+ BNXT_ULP_CLASS_HID_10897 = 0x10897,
+ BNXT_ULP_CLASS_HID_15955 = 0x15955,
+ BNXT_ULP_CLASS_HID_14c8b = 0x14c8b,
+ BNXT_ULP_CLASS_HID_13b47 = 0x13b47,
+ BNXT_ULP_CLASS_HID_12e85 = 0x12e85,
+ BNXT_ULP_CLASS_HID_17f5b = 0x17f5b,
+ BNXT_ULP_CLASS_HID_17299 = 0x17299,
+ BNXT_ULP_CLASS_HID_10fe7 = 0x10fe7,
+ BNXT_ULP_CLASS_HID_10325 = 0x10325,
+ BNXT_ULP_CLASS_HID_153cb = 0x153cb,
+ BNXT_ULP_CLASS_HID_14709 = 0x14709,
+ BNXT_ULP_CLASS_HID_12dc5 = 0x12dc5,
+ BNXT_ULP_CLASS_HID_1212b = 0x1212b,
+ BNXT_ULP_CLASS_HID_171c9 = 0x171c9,
+ BNXT_ULP_CLASS_HID_1650f = 0x1650f,
+ BNXT_ULP_CLASS_HID_10201 = 0x10201,
+ BNXT_ULP_CLASS_HID_116c1 = 0x116c1,
+ BNXT_ULP_CLASS_HID_14605 = 0x14605,
+ BNXT_ULP_CLASS_HID_15a05 = 0x15a05,
+ BNXT_ULP_CLASS_HID_12007 = 0x12007,
+ BNXT_ULP_CLASS_HID_13407 = 0x13407,
+ BNXT_ULP_CLASS_HID_1640b = 0x1640b,
+ BNXT_ULP_CLASS_HID_1780b = 0x1780b,
+ BNXT_ULP_CLASS_HID_404b0 = 0x404b0,
+ BNXT_ULP_CLASS_HID_4148c = 0x4148c,
+ BNXT_ULP_CLASS_HID_514c0 = 0x514c0,
+ BNXT_ULP_CLASS_HID_50bba = 0x50bba,
+ BNXT_ULP_CLASS_HID_48c88 = 0x48c88,
+ BNXT_ULP_CLASS_HID_48362 = 0x48362,
+ BNXT_ULP_CLASS_HID_583b6 = 0x583b6,
+ BNXT_ULP_CLASS_HID_593f2 = 0x593f2,
+ BNXT_ULP_CLASS_HID_41f54 = 0x41f54,
+ BNXT_ULP_CLASS_HID_40fce = 0x40fce,
+ BNXT_ULP_CLASS_HID_50e02 = 0x50e02,
+ BNXT_ULP_CLASS_HID_51e5e = 0x51e5e,
+ BNXT_ULP_CLASS_HID_487ca = 0x487ca,
+ BNXT_ULP_CLASS_HID_49606 = 0x49606,
+ BNXT_ULP_CLASS_HID_5965a = 0x5965a,
+ BNXT_ULP_CLASS_HID_58514 = 0x58514,
+ BNXT_ULP_CLASS_HID_412c2 = 0x412c2,
+ BNXT_ULP_CLASS_HID_401ac = 0x401ac,
+ BNXT_ULP_CLASS_HID_501e0 = 0x501e0,
+ BNXT_ULP_CLASS_HID_511cc = 0x511cc,
+ BNXT_ULP_CLASS_HID_4990a = 0x4990a,
+ BNXT_ULP_CLASS_HID_489e4 = 0x489e4,
+ BNXT_ULP_CLASS_HID_589c8 = 0x589c8,
+ BNXT_ULP_CLASS_HID_59804 = 0x59804,
+ BNXT_ULP_CLASS_HID_40404 = 0x40404,
+ BNXT_ULP_CLASS_HID_41440 = 0x41440,
+ BNXT_ULP_CLASS_HID_51484 = 0x51484,
+ BNXT_ULP_CLASS_HID_50b0e = 0x50b0e,
+ BNXT_ULP_CLASS_HID_48c4c = 0x48c4c,
+ BNXT_ULP_CLASS_HID_48306 = 0x48306,
+ BNXT_ULP_CLASS_HID_5830a = 0x5830a,
+ BNXT_ULP_CLASS_HID_59346 = 0x59346,
+ BNXT_ULP_CLASS_HID_102cc = 0x102cc,
+ BNXT_ULP_CLASS_HID_116ec = 0x116ec,
+ BNXT_ULP_CLASS_HID_146d0 = 0x146d0,
+ BNXT_ULP_CLASS_HID_15af0 = 0x15af0,
+ BNXT_ULP_CLASS_HID_120c2 = 0x120c2,
+ BNXT_ULP_CLASS_HID_134e2 = 0x134e2,
+ BNXT_ULP_CLASS_HID_16b26 = 0x16b26,
+ BNXT_ULP_CLASS_HID_178c6 = 0x178c6,
+ BNXT_ULP_CLASS_HID_115c6 = 0x115c6,
+ BNXT_ULP_CLASS_HID_10804 = 0x10804,
+ BNXT_ULP_CLASS_HID_15822 = 0x15822,
+ BNXT_ULP_CLASS_HID_14c60 = 0x14c60,
+ BNXT_ULP_CLASS_HID_13bd4 = 0x13bd4,
+ BNXT_ULP_CLASS_HID_12e12 = 0x12e12,
+ BNXT_ULP_CLASS_HID_17e30 = 0x17e30,
+ BNXT_ULP_CLASS_HID_17276 = 0x17276,
+ BNXT_ULP_CLASS_HID_11f1a = 0x11f1a,
+ BNXT_ULP_CLASS_HID_11358 = 0x11358,
+ BNXT_ULP_CLASS_HID_14398 = 0x14398,
+ BNXT_ULP_CLASS_HID_157b8 = 0x157b8,
+ BNXT_ULP_CLASS_HID_13d68 = 0x13d68,
+ BNXT_ULP_CLASS_HID_131aa = 0x131aa,
+ BNXT_ULP_CLASS_HID_16192 = 0x16192,
+ BNXT_ULP_CLASS_HID_175b2 = 0x175b2,
+ BNXT_ULP_CLASS_HID_112b2 = 0x112b2,
+ BNXT_ULP_CLASS_HID_106f0 = 0x106f0,
+ BNXT_ULP_CLASS_HID_15692 = 0x15692,
+ BNXT_ULP_CLASS_HID_14ad0 = 0x14ad0,
+ BNXT_ULP_CLASS_HID_13080 = 0x13080,
+ BNXT_ULP_CLASS_HID_124c2 = 0x124c2,
+ BNXT_ULP_CLASS_HID_174e0 = 0x174e0,
+ BNXT_ULP_CLASS_HID_16f22 = 0x16f22,
+ BNXT_ULP_CLASS_HID_4025b = 0x4025b,
+ BNXT_ULP_CLASS_HID_41267 = 0x41267,
+ BNXT_ULP_CLASS_HID_5122b = 0x5122b,
+ BNXT_ULP_CLASS_HID_50d51 = 0x50d51,
+ BNXT_ULP_CLASS_HID_48a63 = 0x48a63,
+ BNXT_ULP_CLASS_HID_48589 = 0x48589,
+ BNXT_ULP_CLASS_HID_5855d = 0x5855d,
+ BNXT_ULP_CLASS_HID_59519 = 0x59519,
+ BNXT_ULP_CLASS_HID_41e17 = 0x41e17,
+ BNXT_ULP_CLASS_HID_4093d = 0x4093d,
+ BNXT_ULP_CLASS_HID_50941 = 0x50941,
+ BNXT_ULP_CLASS_HID_5190d = 0x5190d,
+ BNXT_ULP_CLASS_HID_48139 = 0x48139,
+ BNXT_ULP_CLASS_HID_49145 = 0x49145,
+ BNXT_ULP_CLASS_HID_59109 = 0x59109,
+ BNXT_ULP_CLASS_HID_58037 = 0x58037,
+ BNXT_ULP_CLASS_HID_4143d = 0x4143d,
+ BNXT_ULP_CLASS_HID_4079b = 0x4079b,
+ BNXT_ULP_CLASS_HID_507af = 0x507af,
+ BNXT_ULP_CLASS_HID_5172b = 0x5172b,
+ BNXT_ULP_CLASS_HID_49c05 = 0x49c05,
+ BNXT_ULP_CLASS_HID_48fa3 = 0x48fa3,
+ BNXT_ULP_CLASS_HID_58f37 = 0x58f37,
+ BNXT_ULP_CLASS_HID_59f33 = 0x59f33,
+ BNXT_ULP_CLASS_HID_4030b = 0x4030b,
+ BNXT_ULP_CLASS_HID_41317 = 0x41317,
+ BNXT_ULP_CLASS_HID_5131b = 0x5131b,
+ BNXT_ULP_CLASS_HID_50201 = 0x50201,
+ BNXT_ULP_CLASS_HID_48b13 = 0x48b13,
+ BNXT_ULP_CLASS_HID_49b1f = 0x49b1f,
+ BNXT_ULP_CLASS_HID_59b23 = 0x59b23,
+ BNXT_ULP_CLASS_HID_58a09 = 0x58a09,
+ BNXT_ULP_CLASS_HID_419bf = 0x419bf,
+ BNXT_ULP_CLASS_HID_40925 = 0x40925,
+ BNXT_ULP_CLASS_HID_508e9 = 0x508e9,
+ BNXT_ULP_CLASS_HID_518b5 = 0x518b5,
+ BNXT_ULP_CLASS_HID_48121 = 0x48121,
+ BNXT_ULP_CLASS_HID_490ed = 0x490ed,
+ BNXT_ULP_CLASS_HID_590b1 = 0x590b1,
+ BNXT_ULP_CLASS_HID_583ff = 0x583ff,
+ BNXT_ULP_CLASS_HID_41475 = 0x41475,
+ BNXT_ULP_CLASS_HID_40473 = 0x40473,
+ BNXT_ULP_CLASS_HID_50427 = 0x50427,
+ BNXT_ULP_CLASS_HID_51763 = 0x51763,
+ BNXT_ULP_CLASS_HID_49c3d = 0x49c3d,
+ BNXT_ULP_CLASS_HID_48c3b = 0x48c3b,
+ BNXT_ULP_CLASS_HID_58f6f = 0x58f6f,
+ BNXT_ULP_CLASS_HID_59f2b = 0x59f2b,
+ BNXT_ULP_CLASS_HID_40333 = 0x40333,
+ BNXT_ULP_CLASS_HID_412bf = 0x412bf,
+ BNXT_ULP_CLASS_HID_512a3 = 0x512a3,
+ BNXT_ULP_CLASS_HID_50229 = 0x50229,
+ BNXT_ULP_CLASS_HID_48abb = 0x48abb,
+ BNXT_ULP_CLASS_HID_49aa7 = 0x49aa7,
+ BNXT_ULP_CLASS_HID_59a2b = 0x59a2b,
+ BNXT_ULP_CLASS_HID_595b1 = 0x595b1,
+ BNXT_ULP_CLASS_HID_41e2f = 0x41e2f,
+ BNXT_ULP_CLASS_HID_40e35 = 0x40e35,
+ BNXT_ULP_CLASS_HID_50939 = 0x50939,
+ BNXT_ULP_CLASS_HID_51925 = 0x51925,
+ BNXT_ULP_CLASS_HID_48631 = 0x48631,
+ BNXT_ULP_CLASS_HID_4913d = 0x4913d,
+ BNXT_ULP_CLASS_HID_59121 = 0x59121,
+ BNXT_ULP_CLASS_HID_5812f = 0x5812f,
+ BNXT_ULP_CLASS_HID_41429 = 0x41429,
+ BNXT_ULP_CLASS_HID_40747 = 0x40747,
+ BNXT_ULP_CLASS_HID_5070b = 0x5070b,
+ BNXT_ULP_CLASS_HID_51727 = 0x51727,
+ BNXT_ULP_CLASS_HID_49fe1 = 0x49fe1,
+ BNXT_ULP_CLASS_HID_48f0f = 0x48f0f,
+ BNXT_ULP_CLASS_HID_58f23 = 0x58f23,
+ BNXT_ULP_CLASS_HID_59eef = 0x59eef,
+ BNXT_ULP_CLASS_HID_40347 = 0x40347,
+ BNXT_ULP_CLASS_HID_41303 = 0x41303,
+ BNXT_ULP_CLASS_HID_51247 = 0x51247,
+ BNXT_ULP_CLASS_HID_5026d = 0x5026d,
+ BNXT_ULP_CLASS_HID_48b0f = 0x48b0f,
+ BNXT_ULP_CLASS_HID_49a4b = 0x49a4b,
+ BNXT_ULP_CLASS_HID_59a0f = 0x59a0f,
+ BNXT_ULP_CLASS_HID_58a05 = 0x58a05,
+ BNXT_ULP_CLASS_HID_41983 = 0x41983,
+ BNXT_ULP_CLASS_HID_40929 = 0x40929,
+ BNXT_ULP_CLASS_HID_5092d = 0x5092d,
+ BNXT_ULP_CLASS_HID_518a9 = 0x518a9,
+ BNXT_ULP_CLASS_HID_48125 = 0x48125,
+ BNXT_ULP_CLASS_HID_49121 = 0x49121,
+ BNXT_ULP_CLASS_HID_59085 = 0x59085,
+ BNXT_ULP_CLASS_HID_58023 = 0x58023,
+ BNXT_ULP_CLASS_HID_41509 = 0x41509,
+ BNXT_ULP_CLASS_HID_40407 = 0x40407,
+ BNXT_ULP_CLASS_HID_5040b = 0x5040b,
+ BNXT_ULP_CLASS_HID_51407 = 0x51407,
+ BNXT_ULP_CLASS_HID_49d21 = 0x49d21,
+ BNXT_ULP_CLASS_HID_48c0f = 0x48c0f,
+ BNXT_ULP_CLASS_HID_58c03 = 0x58c03,
+ BNXT_ULP_CLASS_HID_59f0f = 0x59f0f,
+ BNXT_ULP_CLASS_HID_402ef = 0x402ef,
+ BNXT_ULP_CLASS_HID_412ab = 0x412ab,
+ BNXT_ULP_CLASS_HID_5126f = 0x5126f,
+ BNXT_ULP_CLASS_HID_50de5 = 0x50de5,
+ BNXT_ULP_CLASS_HID_48aa7 = 0x48aa7,
+ BNXT_ULP_CLASS_HID_485ed = 0x485ed,
+ BNXT_ULP_CLASS_HID_585e1 = 0x585e1,
+ BNXT_ULP_CLASS_HID_595ad = 0x595ad,
+ BNXT_ULP_CLASS_HID_41e6b = 0x41e6b,
+ BNXT_ULP_CLASS_HID_40961 = 0x40961,
+ BNXT_ULP_CLASS_HID_50925 = 0x50925,
+ BNXT_ULP_CLASS_HID_51961 = 0x51961,
+ BNXT_ULP_CLASS_HID_4816d = 0x4816d,
+ BNXT_ULP_CLASS_HID_49129 = 0x49129,
+ BNXT_ULP_CLASS_HID_5916d = 0x5916d,
+ BNXT_ULP_CLASS_HID_5806b = 0x5806b,
+ BNXT_ULP_CLASS_HID_414a1 = 0x414a1,
+ BNXT_ULP_CLASS_HID_4042f = 0x4042f,
+ BNXT_ULP_CLASS_HID_507a3 = 0x507a3,
+ BNXT_ULP_CLASS_HID_517af = 0x517af,
+ BNXT_ULP_CLASS_HID_49c29 = 0x49c29,
+ BNXT_ULP_CLASS_HID_48fa7 = 0x48fa7,
+ BNXT_ULP_CLASS_HID_58fab = 0x58fab,
+ BNXT_ULP_CLASS_HID_59f27 = 0x59f27,
+ BNXT_ULP_CLASS_HID_4032f = 0x4032f,
+ BNXT_ULP_CLASS_HID_4132b = 0x4132b,
+ BNXT_ULP_CLASS_HID_5132f = 0x5132f,
+ BNXT_ULP_CLASS_HID_50225 = 0x50225,
+ BNXT_ULP_CLASS_HID_48b27 = 0x48b27,
+ BNXT_ULP_CLASS_HID_49b23 = 0x49b23,
+ BNXT_ULP_CLASS_HID_59b27 = 0x59b27,
+ BNXT_ULP_CLASS_HID_58a2d = 0x58a2d,
+ BNXT_ULP_CLASS_HID_10437 = 0x10437,
+ BNXT_ULP_CLASS_HID_11017 = 0x11017,
+ BNXT_ULP_CLASS_HID_1402b = 0x1402b,
+ BNXT_ULP_CLASS_HID_15c0b = 0x15c0b,
+ BNXT_ULP_CLASS_HID_12639 = 0x12639,
+ BNXT_ULP_CLASS_HID_13219 = 0x13219,
+ BNXT_ULP_CLASS_HID_16ddd = 0x16ddd,
+ BNXT_ULP_CLASS_HID_17e3d = 0x17e3d,
+ BNXT_ULP_CLASS_HID_11333 = 0x11333,
+ BNXT_ULP_CLASS_HID_10ef5 = 0x10ef5,
+ BNXT_ULP_CLASS_HID_15f37 = 0x15f37,
+ BNXT_ULP_CLASS_HID_14ae9 = 0x14ae9,
+ BNXT_ULP_CLASS_HID_13d25 = 0x13d25,
+ BNXT_ULP_CLASS_HID_128e7 = 0x128e7,
+ BNXT_ULP_CLASS_HID_17939 = 0x17939,
+ BNXT_ULP_CLASS_HID_174fb = 0x174fb,
+ BNXT_ULP_CLASS_HID_10985 = 0x10985,
+ BNXT_ULP_CLASS_HID_10547 = 0x10547,
+ BNXT_ULP_CLASS_HID_155a9 = 0x155a9,
+ BNXT_ULP_CLASS_HID_1416b = 0x1416b,
+ BNXT_ULP_CLASS_HID_12ba7 = 0x12ba7,
+ BNXT_ULP_CLASS_HID_12749 = 0x12749,
+ BNXT_ULP_CLASS_HID_177ab = 0x177ab,
+ BNXT_ULP_CLASS_HID_1636d = 0x1636d,
+ BNXT_ULP_CLASS_HID_10463 = 0x10463,
+ BNXT_ULP_CLASS_HID_110a3 = 0x110a3,
+ BNXT_ULP_CLASS_HID_14067 = 0x14067,
+ BNXT_ULP_CLASS_HID_15c67 = 0x15c67,
+ BNXT_ULP_CLASS_HID_12665 = 0x12665,
+ BNXT_ULP_CLASS_HID_13265 = 0x13265,
+ BNXT_ULP_CLASS_HID_16269 = 0x16269,
+ BNXT_ULP_CLASS_HID_17e69 = 0x17e69,
+ BNXT_ULP_CLASS_HID_1133d = 0x1133d,
+ BNXT_ULP_CLASS_HID_10eff = 0x10eff,
+ BNXT_ULP_CLASS_HID_15ed9 = 0x15ed9,
+ BNXT_ULP_CLASS_HID_14a9b = 0x14a9b,
+ BNXT_ULP_CLASS_HID_13d2f = 0x13d2f,
+ BNXT_ULP_CLASS_HID_128e9 = 0x128e9,
+ BNXT_ULP_CLASS_HID_178cb = 0x178cb,
+ BNXT_ULP_CLASS_HID_1748d = 0x1748d,
+ BNXT_ULP_CLASS_HID_109fb = 0x109fb,
+ BNXT_ULP_CLASS_HID_105bd = 0x105bd,
+ BNXT_ULP_CLASS_HID_155bf = 0x155bf,
+ BNXT_ULP_CLASS_HID_14179 = 0x14179,
+ BNXT_ULP_CLASS_HID_12bed = 0x12bed,
+ BNXT_ULP_CLASS_HID_127af = 0x127af,
+ BNXT_ULP_CLASS_HID_177a9 = 0x177a9,
+ BNXT_ULP_CLASS_HID_1636b = 0x1636b,
+ BNXT_ULP_CLASS_HID_1046d = 0x1046d,
+ BNXT_ULP_CLASS_HID_1104d = 0x1104d,
+ BNXT_ULP_CLASS_HID_14009 = 0x14009,
+ BNXT_ULP_CLASS_HID_15c69 = 0x15c69,
+ BNXT_ULP_CLASS_HID_1260f = 0x1260f,
+ BNXT_ULP_CLASS_HID_1326f = 0x1326f,
+ BNXT_ULP_CLASS_HID_1622b = 0x1622b,
+ BNXT_ULP_CLASS_HID_17e0b = 0x17e0b,
+ BNXT_ULP_CLASS_HID_11369 = 0x11369,
+ BNXT_ULP_CLASS_HID_10f2b = 0x10f2b,
+ BNXT_ULP_CLASS_HID_15f6d = 0x15f6d,
+ BNXT_ULP_CLASS_HID_14b2f = 0x14b2f,
+ BNXT_ULP_CLASS_HID_13d6b = 0x13d6b,
+ BNXT_ULP_CLASS_HID_1292d = 0x1292d,
+ BNXT_ULP_CLASS_HID_1792f = 0x1792f,
+ BNXT_ULP_CLASS_HID_174e9 = 0x174e9,
+ BNXT_ULP_CLASS_HID_119e1 = 0x119e1,
+ BNXT_ULP_CLASS_HID_115a3 = 0x115a3,
+ BNXT_ULP_CLASS_HID_14563 = 0x14563,
+ BNXT_ULP_CLASS_HID_15143 = 0x15143,
+ BNXT_ULP_CLASS_HID_13b93 = 0x13b93,
+ BNXT_ULP_CLASS_HID_13751 = 0x13751,
+ BNXT_ULP_CLASS_HID_16769 = 0x16769,
+ BNXT_ULP_CLASS_HID_17349 = 0x17349,
+ BNXT_ULP_CLASS_HID_114ab = 0x114ab,
+ BNXT_ULP_CLASS_HID_10061 = 0x10061,
+ BNXT_ULP_CLASS_HID_15063 = 0x15063,
+ BNXT_ULP_CLASS_HID_14c21 = 0x14c21,
+ BNXT_ULP_CLASS_HID_13671 = 0x13671,
+ BNXT_ULP_CLASS_HID_12233 = 0x12233,
+ BNXT_ULP_CLASS_HID_17271 = 0x17271,
+ BNXT_ULP_CLASS_HID_16e33 = 0x16e33,
+ BNXT_ULP_CLASS_HID_102c1 = 0x102c1,
+ BNXT_ULP_CLASS_HID_11f21 = 0x11f21,
+ BNXT_ULP_CLASS_HID_14ee1 = 0x14ee1,
+ BNXT_ULP_CLASS_HID_15ac1 = 0x15ac1,
+ BNXT_ULP_CLASS_HID_12cc3 = 0x12cc3,
+ BNXT_ULP_CLASS_HID_13923 = 0x13923,
+ BNXT_ULP_CLASS_HID_168e3 = 0x168e3,
+ BNXT_ULP_CLASS_HID_164a9 = 0x164a9,
+ BNXT_ULP_CLASS_HID_11e29 = 0x11e29,
+ BNXT_ULP_CLASS_HID_115eb = 0x115eb,
+ BNXT_ULP_CLASS_HID_145a3 = 0x145a3,
+ BNXT_ULP_CLASS_HID_151a3 = 0x151a3,
+ BNXT_ULP_CLASS_HID_1382b = 0x1382b,
+ BNXT_ULP_CLASS_HID_137e1 = 0x137e1,
+ BNXT_ULP_CLASS_HID_167a1 = 0x167a1,
+ BNXT_ULP_CLASS_HID_173a1 = 0x173a1,
+ BNXT_ULP_CLASS_HID_11449 = 0x11449,
+ BNXT_ULP_CLASS_HID_1000b = 0x1000b,
+ BNXT_ULP_CLASS_HID_15069 = 0x15069,
+ BNXT_ULP_CLASS_HID_14c2b = 0x14c2b,
+ BNXT_ULP_CLASS_HID_1367b = 0x1367b,
+ BNXT_ULP_CLASS_HID_12239 = 0x12239,
+ BNXT_ULP_CLASS_HID_1721b = 0x1721b,
+ BNXT_ULP_CLASS_HID_169d9 = 0x169d9,
+ BNXT_ULP_CLASS_HID_1033b = 0x1033b,
+ BNXT_ULP_CLASS_HID_11f3b = 0x11f3b,
+ BNXT_ULP_CLASS_HID_14f2b = 0x14f2b,
+ BNXT_ULP_CLASS_HID_15b2b = 0x15b2b,
+ BNXT_ULP_CLASS_HID_12d39 = 0x12d39,
+ BNXT_ULP_CLASS_HID_13939 = 0x13939,
+ BNXT_ULP_CLASS_HID_168f9 = 0x168f9,
+ BNXT_ULP_CLASS_HID_164bb = 0x164bb,
+ BNXT_ULP_CLASS_HID_119cb = 0x119cb,
+ BNXT_ULP_CLASS_HID_11589 = 0x11589,
+ BNXT_ULP_CLASS_HID_14549 = 0x14549,
+ BNXT_ULP_CLASS_HID_151a9 = 0x151a9,
+ BNXT_ULP_CLASS_HID_13bc9 = 0x13bc9,
+ BNXT_ULP_CLASS_HID_1378b = 0x1378b,
+ BNXT_ULP_CLASS_HID_1674b = 0x1674b,
+ BNXT_ULP_CLASS_HID_173ab = 0x173ab,
+ BNXT_ULP_CLASS_HID_114a9 = 0x114a9,
+ BNXT_ULP_CLASS_HID_1006b = 0x1006b,
+ BNXT_ULP_CLASS_HID_150a9 = 0x150a9,
+ BNXT_ULP_CLASS_HID_14c6b = 0x14c6b,
+ BNXT_ULP_CLASS_HID_136ab = 0x136ab,
+ BNXT_ULP_CLASS_HID_12269 = 0x12269,
+ BNXT_ULP_CLASS_HID_172ab = 0x172ab,
+ BNXT_ULP_CLASS_HID_16e69 = 0x16e69,
+ BNXT_ULP_CLASS_HID_402d2 = 0x402d2,
+ BNXT_ULP_CLASS_HID_412ee = 0x412ee,
+ BNXT_ULP_CLASS_HID_512a2 = 0x512a2,
+ BNXT_ULP_CLASS_HID_50dd8 = 0x50dd8,
+ BNXT_ULP_CLASS_HID_48aea = 0x48aea,
+ BNXT_ULP_CLASS_HID_48500 = 0x48500,
+ BNXT_ULP_CLASS_HID_585d4 = 0x585d4,
+ BNXT_ULP_CLASS_HID_59590 = 0x59590,
+ BNXT_ULP_CLASS_HID_41936 = 0x41936,
+ BNXT_ULP_CLASS_HID_409ac = 0x409ac,
+ BNXT_ULP_CLASS_HID_50860 = 0x50860,
+ BNXT_ULP_CLASS_HID_5183c = 0x5183c,
+ BNXT_ULP_CLASS_HID_481a8 = 0x481a8,
+ BNXT_ULP_CLASS_HID_49064 = 0x49064,
+ BNXT_ULP_CLASS_HID_59038 = 0x59038,
+ BNXT_ULP_CLASS_HID_58376 = 0x58376,
+ BNXT_ULP_CLASS_HID_414a0 = 0x414a0,
+ BNXT_ULP_CLASS_HID_407ce = 0x407ce,
+ BNXT_ULP_CLASS_HID_50782 = 0x50782,
+ BNXT_ULP_CLASS_HID_517ae = 0x517ae,
+ BNXT_ULP_CLASS_HID_49f68 = 0x49f68,
+ BNXT_ULP_CLASS_HID_48f86 = 0x48f86,
+ BNXT_ULP_CLASS_HID_58faa = 0x58faa,
+ BNXT_ULP_CLASS_HID_59e66 = 0x59e66,
+ BNXT_ULP_CLASS_HID_40266 = 0x40266,
+ BNXT_ULP_CLASS_HID_41222 = 0x41222,
+ BNXT_ULP_CLASS_HID_512e6 = 0x512e6,
+ BNXT_ULP_CLASS_HID_50d6c = 0x50d6c,
+ BNXT_ULP_CLASS_HID_48a2e = 0x48a2e,
+ BNXT_ULP_CLASS_HID_48564 = 0x48564,
+ BNXT_ULP_CLASS_HID_58568 = 0x58568,
+ BNXT_ULP_CLASS_HID_59524 = 0x59524,
+ BNXT_ULP_CLASS_HID_419d8 = 0x419d8,
+ BNXT_ULP_CLASS_HID_4087e = 0x4087e,
+ BNXT_ULP_CLASS_HID_5080a = 0x5080a,
+ BNXT_ULP_CLASS_HID_518ce = 0x518ce,
+ BNXT_ULP_CLASS_HID_4807a = 0x4807a,
+ BNXT_ULP_CLASS_HID_4900e = 0x4900e,
+ BNXT_ULP_CLASS_HID_590ca = 0x590ca,
+ BNXT_ULP_CLASS_HID_58378 = 0x58378,
+ BNXT_ULP_CLASS_HID_414be = 0x414be,
+ BNXT_ULP_CLASS_HID_4073c = 0x4073c,
+ BNXT_ULP_CLASS_HID_507e8 = 0x507e8,
+ BNXT_ULP_CLASS_HID_517ac = 0x517ac,
+ BNXT_ULP_CLASS_HID_49f7e = 0x49f7e,
+ BNXT_ULP_CLASS_HID_48fec = 0x48fec,
+ BNXT_ULP_CLASS_HID_58fa8 = 0x58fa8,
+ BNXT_ULP_CLASS_HID_59e7c = 0x59e7c,
+ BNXT_ULP_CLASS_HID_40208 = 0x40208,
+ BNXT_ULP_CLASS_HID_412cc = 0x412cc,
+ BNXT_ULP_CLASS_HID_51288 = 0x51288,
+ BNXT_ULP_CLASS_HID_50d2e = 0x50d2e,
+ BNXT_ULP_CLASS_HID_48ac8 = 0x48ac8,
+ BNXT_ULP_CLASS_HID_4856e = 0x4856e,
+ BNXT_ULP_CLASS_HID_5852a = 0x5852a,
+ BNXT_ULP_CLASS_HID_595ce = 0x595ce,
+ BNXT_ULP_CLASS_HID_4196c = 0x4196c,
+ BNXT_ULP_CLASS_HID_409aa = 0x409aa,
+ BNXT_ULP_CLASS_HID_5086e = 0x5086e,
+ BNXT_ULP_CLASS_HID_5182a = 0x5182a,
+ BNXT_ULP_CLASS_HID_481ae = 0x481ae,
+ BNXT_ULP_CLASS_HID_4906a = 0x4906a,
+ BNXT_ULP_CLASS_HID_5902e = 0x5902e,
+ BNXT_ULP_CLASS_HID_580ac = 0x580ac,
+ BNXT_ULP_CLASS_HID_40766 = 0x40766,
+ BNXT_ULP_CLASS_HID_41726 = 0x41726,
+ BNXT_ULP_CLASS_HID_517f6 = 0x517f6,
+ BNXT_ULP_CLASS_HID_5066c = 0x5066c,
+ BNXT_ULP_CLASS_HID_48f3e = 0x48f3e,
+ BNXT_ULP_CLASS_HID_49ffe = 0x49ffe,
+ BNXT_ULP_CLASS_HID_59f8e = 0x59f8e,
+ BNXT_ULP_CLASS_HID_58e24 = 0x58e24,
+ BNXT_ULP_CLASS_HID_4126e = 0x4126e,
+ BNXT_ULP_CLASS_HID_402e4 = 0x402e4,
+ BNXT_ULP_CLASS_HID_502b4 = 0x502b4,
+ BNXT_ULP_CLASS_HID_51d74 = 0x51d74,
+ BNXT_ULP_CLASS_HID_49a26 = 0x49a26,
+ BNXT_ULP_CLASS_HID_48abc = 0x48abc,
+ BNXT_ULP_CLASS_HID_5956c = 0x5956c,
+ BNXT_ULP_CLASS_HID_585ee = 0x585ee,
+ BNXT_ULP_CLASS_HID_409e4 = 0x409e4,
+ BNXT_ULP_CLASS_HID_419a4 = 0x419a4,
+ BNXT_ULP_CLASS_HID_51844 = 0x51844,
+ BNXT_ULP_CLASS_HID_508e6 = 0x508e6,
+ BNXT_ULP_CLASS_HID_4918c = 0x4918c,
+ BNXT_ULP_CLASS_HID_4802e = 0x4802e,
+ BNXT_ULP_CLASS_HID_580ee = 0x580ee,
+ BNXT_ULP_CLASS_HID_590ae = 0x590ae,
+ BNXT_ULP_CLASS_HID_404ae = 0x404ae,
+ BNXT_ULP_CLASS_HID_41766 = 0x41766,
+ BNXT_ULP_CLASS_HID_5172e = 0x5172e,
+ BNXT_ULP_CLASS_HID_507a4 = 0x507a4,
+ BNXT_ULP_CLASS_HID_48f66 = 0x48f66,
+ BNXT_ULP_CLASS_HID_49f2e = 0x49f2e,
+ BNXT_ULP_CLASS_HID_59fe6 = 0x59fe6,
+ BNXT_ULP_CLASS_HID_58e6c = 0x58e6c,
+ BNXT_ULP_CLASS_HID_4126c = 0x4126c,
+ BNXT_ULP_CLASS_HID_4028e = 0x4028e,
+ BNXT_ULP_CLASS_HID_50d5e = 0x50d5e,
+ BNXT_ULP_CLASS_HID_51d1e = 0x51d1e,
+ BNXT_ULP_CLASS_HID_49a2c = 0x49a2c,
+ BNXT_ULP_CLASS_HID_4954e = 0x4954e,
+ BNXT_ULP_CLASS_HID_5951e = 0x5951e,
+ BNXT_ULP_CLASS_HID_5858c = 0x5858c,
+ BNXT_ULP_CLASS_HID_409fe = 0x409fe,
+ BNXT_ULP_CLASS_HID_419ee = 0x419ee,
+ BNXT_ULP_CLASS_HID_519ae = 0x519ae,
+ BNXT_ULP_CLASS_HID_508fc = 0x508fc,
+ BNXT_ULP_CLASS_HID_491ee = 0x491ee,
+ BNXT_ULP_CLASS_HID_4802c = 0x4802c,
+ BNXT_ULP_CLASS_HID_580fc = 0x580fc,
+ BNXT_ULP_CLASS_HID_590bc = 0x590bc,
+ BNXT_ULP_CLASS_HID_4074c = 0x4074c,
+ BNXT_ULP_CLASS_HID_4170c = 0x4170c,
+ BNXT_ULP_CLASS_HID_5172c = 0x5172c,
+ BNXT_ULP_CLASS_HID_5064e = 0x5064e,
+ BNXT_ULP_CLASS_HID_48f0c = 0x48f0c,
+ BNXT_ULP_CLASS_HID_49fcc = 0x49fcc,
+ BNXT_ULP_CLASS_HID_59fec = 0x59fec,
+ BNXT_ULP_CLASS_HID_58e0e = 0x58e0e,
+ BNXT_ULP_CLASS_HID_413ac = 0x413ac,
+ BNXT_ULP_CLASS_HID_402ee = 0x402ee,
+ BNXT_ULP_CLASS_HID_502ae = 0x502ae,
+ BNXT_ULP_CLASS_HID_512ae = 0x512ae,
+ BNXT_ULP_CLASS_HID_49a6c = 0x49a6c,
+ BNXT_ULP_CLASS_HID_48aae = 0x48aae,
+ BNXT_ULP_CLASS_HID_58aae = 0x58aae,
+ BNXT_ULP_CLASS_HID_585ec = 0x585ec,
+ BNXT_ULP_CLASS_HID_104ae = 0x104ae,
+ BNXT_ULP_CLASS_HID_1108e = 0x1108e,
+ BNXT_ULP_CLASS_HID_140b2 = 0x140b2,
+ BNXT_ULP_CLASS_HID_15c92 = 0x15c92,
+ BNXT_ULP_CLASS_HID_126a0 = 0x126a0,
+ BNXT_ULP_CLASS_HID_13280 = 0x13280,
+ BNXT_ULP_CLASS_HID_16d44 = 0x16d44,
+ BNXT_ULP_CLASS_HID_17ea4 = 0x17ea4,
+ BNXT_ULP_CLASS_HID_113a4 = 0x113a4,
+ BNXT_ULP_CLASS_HID_10e66 = 0x10e66,
+ BNXT_ULP_CLASS_HID_15e40 = 0x15e40,
+ BNXT_ULP_CLASS_HID_14a02 = 0x14a02,
+ BNXT_ULP_CLASS_HID_13db6 = 0x13db6,
+ BNXT_ULP_CLASS_HID_12870 = 0x12870,
+ BNXT_ULP_CLASS_HID_17852 = 0x17852,
+ BNXT_ULP_CLASS_HID_17414 = 0x17414,
+ BNXT_ULP_CLASS_HID_11978 = 0x11978,
+ BNXT_ULP_CLASS_HID_1153a = 0x1153a,
+ BNXT_ULP_CLASS_HID_145fa = 0x145fa,
+ BNXT_ULP_CLASS_HID_151da = 0x151da,
+ BNXT_ULP_CLASS_HID_13b0a = 0x13b0a,
+ BNXT_ULP_CLASS_HID_137c8 = 0x137c8,
+ BNXT_ULP_CLASS_HID_167f0 = 0x167f0,
+ BNXT_ULP_CLASS_HID_173d0 = 0x173d0,
+ BNXT_ULP_CLASS_HID_114d0 = 0x114d0,
+ BNXT_ULP_CLASS_HID_10092 = 0x10092,
+ BNXT_ULP_CLASS_HID_150f0 = 0x150f0,
+ BNXT_ULP_CLASS_HID_14cb2 = 0x14cb2,
+ BNXT_ULP_CLASS_HID_136e2 = 0x136e2,
+ BNXT_ULP_CLASS_HID_122a0 = 0x122a0,
+ BNXT_ULP_CLASS_HID_17282 = 0x17282,
+ BNXT_ULP_CLASS_HID_16940 = 0x16940,
+ BNXT_ULP_CLASS_HID_11b90 = 0x11b90,
+ BNXT_ULP_CLASS_HID_11654 = 0x11654,
+ BNXT_ULP_CLASS_HID_14618 = 0x14618,
+ BNXT_ULP_CLASS_HID_15278 = 0x15278,
+ BNXT_ULP_CLASS_HID_12404 = 0x12404,
+ BNXT_ULP_CLASS_HID_13064 = 0x13064,
+ BNXT_ULP_CLASS_HID_16028 = 0x16028,
+ BNXT_ULP_CLASS_HID_17c08 = 0x17c08,
+ BNXT_ULP_CLASS_HID_11100 = 0x11100,
+ BNXT_ULP_CLASS_HID_10dc4 = 0x10dc4,
+ BNXT_ULP_CLASS_HID_15d24 = 0x15d24,
+ BNXT_ULP_CLASS_HID_149d0 = 0x149d0,
+ BNXT_ULP_CLASS_HID_13314 = 0x13314,
+ BNXT_ULP_CLASS_HID_12fd4 = 0x12fd4,
+ BNXT_ULP_CLASS_HID_17f20 = 0x17f20,
+ BNXT_ULP_CLASS_HID_16be0 = 0x16be0,
+ BNXT_ULP_CLASS_HID_11cd8 = 0x11cd8,
+ BNXT_ULP_CLASS_HID_10880 = 0x10880,
+ BNXT_ULP_CLASS_HID_158e0 = 0x158e0,
+ BNXT_ULP_CLASS_HID_154a0 = 0x154a0,
+ BNXT_ULP_CLASS_HID_13ed0 = 0x13ed0,
+ BNXT_ULP_CLASS_HID_12a90 = 0x12a90,
+ BNXT_ULP_CLASS_HID_16550 = 0x16550,
+ BNXT_ULP_CLASS_HID_176b0 = 0x176b0,
+ BNXT_ULP_CLASS_HID_10bb0 = 0x10bb0,
+ BNXT_ULP_CLASS_HID_10670 = 0x10670,
+ BNXT_ULP_CLASS_HID_15650 = 0x15650,
+ BNXT_ULP_CLASS_HID_14210 = 0x14210,
+ BNXT_ULP_CLASS_HID_13440 = 0x13440,
+ BNXT_ULP_CLASS_HID_12000 = 0x12000,
+ BNXT_ULP_CLASS_HID_17060 = 0x17060,
+ BNXT_ULP_CLASS_HID_16c20 = 0x16c20,
+ BNXT_ULP_CLASS_HID_11511 = 0x11511,
+ BNXT_ULP_CLASS_HID_101d3 = 0x101d3,
+ BNXT_ULP_CLASS_HID_15135 = 0x15135,
+ BNXT_ULP_CLASS_HID_14df7 = 0x14df7,
+ BNXT_ULP_CLASS_HID_13723 = 0x13723,
+ BNXT_ULP_CLASS_HID_123e5 = 0x123e5,
+ BNXT_ULP_CLASS_HID_173c7 = 0x173c7,
+ BNXT_ULP_CLASS_HID_16f89 = 0x16f89,
+ BNXT_ULP_CLASS_HID_10081 = 0x10081,
+ BNXT_ULP_CLASS_HID_11ce1 = 0x11ce1,
+ BNXT_ULP_CLASS_HID_14ca5 = 0x14ca5,
+ BNXT_ULP_CLASS_HID_15885 = 0x15885,
+ BNXT_ULP_CLASS_HID_12293 = 0x12293,
+ BNXT_ULP_CLASS_HID_13ef3 = 0x13ef3,
+ BNXT_ULP_CLASS_HID_16eb7 = 0x16eb7,
+ BNXT_ULP_CLASS_HID_16561 = 0x16561,
+ BNXT_ULP_CLASS_HID_10e59 = 0x10e59,
+ BNXT_ULP_CLASS_HID_11bb9 = 0x11bb9,
+ BNXT_ULP_CLASS_HID_14a61 = 0x14a61,
+ BNXT_ULP_CLASS_HID_14623 = 0x14623,
+ BNXT_ULP_CLASS_HID_1286b = 0x1286b,
+ BNXT_ULP_CLASS_HID_12411 = 0x12411,
+ BNXT_ULP_CLASS_HID_17473 = 0x17473,
+ BNXT_ULP_CLASS_HID_16031 = 0x16031,
+ BNXT_ULP_CLASS_HID_10531 = 0x10531,
+ BNXT_ULP_CLASS_HID_11111 = 0x11111,
+ BNXT_ULP_CLASS_HID_141d1 = 0x141d1,
+ BNXT_ULP_CLASS_HID_15d31 = 0x15d31,
+ BNXT_ULP_CLASS_HID_127c3 = 0x127c3,
+ BNXT_ULP_CLASS_HID_13323 = 0x13323,
+ BNXT_ULP_CLASS_HID_163e3 = 0x163e3,
+ BNXT_ULP_CLASS_HID_17fc3 = 0x17fc3,
+ BNXT_ULP_CLASS_HID_108f5 = 0x108f5,
+ BNXT_ULP_CLASS_HID_104b9 = 0x104b9,
+ BNXT_ULP_CLASS_HID_15499 = 0x15499,
+ BNXT_ULP_CLASS_HID_1435d = 0x1435d,
+ BNXT_ULP_CLASS_HID_12a89 = 0x12a89,
+ BNXT_ULP_CLASS_HID_12149 = 0x12149,
+ BNXT_ULP_CLASS_HID_176ad = 0x176ad,
+ BNXT_ULP_CLASS_HID_16d6d = 0x16d6d,
+ BNXT_ULP_CLASS_HID_10665 = 0x10665,
+ BNXT_ULP_CLASS_HID_11245 = 0x11245,
+ BNXT_ULP_CLASS_HID_14271 = 0x14271,
+ BNXT_ULP_CLASS_HID_15e51 = 0x15e51,
+ BNXT_ULP_CLASS_HID_12061 = 0x12061,
+ BNXT_ULP_CLASS_HID_13c41 = 0x13c41,
+ BNXT_ULP_CLASS_HID_16c05 = 0x16c05,
+ BNXT_ULP_CLASS_HID_17865 = 0x17865,
+ BNXT_ULP_CLASS_HID_10d21 = 0x10d21,
+ BNXT_ULP_CLASS_HID_11901 = 0x11901,
+ BNXT_ULP_CLASS_HID_149c1 = 0x149c1,
+ BNXT_ULP_CLASS_HID_14589 = 0x14589,
+ BNXT_ULP_CLASS_HID_12f31 = 0x12f31,
+ BNXT_ULP_CLASS_HID_13b11 = 0x13b11,
+ BNXT_ULP_CLASS_HID_16bd9 = 0x16bd9,
+ BNXT_ULP_CLASS_HID_16799 = 0x16799,
+ BNXT_ULP_CLASS_HID_11831 = 0x11831,
+ BNXT_ULP_CLASS_HID_114f1 = 0x114f1,
+ BNXT_ULP_CLASS_HID_144b1 = 0x144b1,
+ BNXT_ULP_CLASS_HID_15091 = 0x15091,
+ BNXT_ULP_CLASS_HID_13ac1 = 0x13ac1,
+ BNXT_ULP_CLASS_HID_13681 = 0x13681,
+ BNXT_ULP_CLASS_HID_166b1 = 0x166b1,
+ BNXT_ULP_CLASS_HID_17291 = 0x17291,
+ BNXT_ULP_CLASS_HID_4007d = 0x4007d,
+ BNXT_ULP_CLASS_HID_41041 = 0x41041,
+ BNXT_ULP_CLASS_HID_5100d = 0x5100d,
+ BNXT_ULP_CLASS_HID_50f77 = 0x50f77,
+ BNXT_ULP_CLASS_HID_48845 = 0x48845,
+ BNXT_ULP_CLASS_HID_487af = 0x487af,
+ BNXT_ULP_CLASS_HID_5877b = 0x5877b,
+ BNXT_ULP_CLASS_HID_5973f = 0x5973f,
+ BNXT_ULP_CLASS_HID_41c31 = 0x41c31,
+ BNXT_ULP_CLASS_HID_40b1b = 0x40b1b,
+ BNXT_ULP_CLASS_HID_50b67 = 0x50b67,
+ BNXT_ULP_CLASS_HID_51b2b = 0x51b2b,
+ BNXT_ULP_CLASS_HID_4831f = 0x4831f,
+ BNXT_ULP_CLASS_HID_49363 = 0x49363,
+ BNXT_ULP_CLASS_HID_5932f = 0x5932f,
+ BNXT_ULP_CLASS_HID_58211 = 0x58211,
+ BNXT_ULP_CLASS_HID_4161b = 0x4161b,
+ BNXT_ULP_CLASS_HID_405bd = 0x405bd,
+ BNXT_ULP_CLASS_HID_50589 = 0x50589,
+ BNXT_ULP_CLASS_HID_5150d = 0x5150d,
+ BNXT_ULP_CLASS_HID_49e23 = 0x49e23,
+ BNXT_ULP_CLASS_HID_48d85 = 0x48d85,
+ BNXT_ULP_CLASS_HID_58d11 = 0x58d11,
+ BNXT_ULP_CLASS_HID_59d15 = 0x59d15,
+ BNXT_ULP_CLASS_HID_4012d = 0x4012d,
+ BNXT_ULP_CLASS_HID_41131 = 0x41131,
+ BNXT_ULP_CLASS_HID_5113d = 0x5113d,
+ BNXT_ULP_CLASS_HID_50027 = 0x50027,
+ BNXT_ULP_CLASS_HID_48935 = 0x48935,
+ BNXT_ULP_CLASS_HID_49939 = 0x49939,
+ BNXT_ULP_CLASS_HID_59905 = 0x59905,
+ BNXT_ULP_CLASS_HID_5882f = 0x5882f,
+ BNXT_ULP_CLASS_HID_41b99 = 0x41b99,
+ BNXT_ULP_CLASS_HID_40b03 = 0x40b03,
+ BNXT_ULP_CLASS_HID_50acf = 0x50acf,
+ BNXT_ULP_CLASS_HID_51a93 = 0x51a93,
+ BNXT_ULP_CLASS_HID_48307 = 0x48307,
+ BNXT_ULP_CLASS_HID_492cb = 0x492cb,
+ BNXT_ULP_CLASS_HID_59297 = 0x59297,
+ BNXT_ULP_CLASS_HID_581d9 = 0x581d9,
+ BNXT_ULP_CLASS_HID_41653 = 0x41653,
+ BNXT_ULP_CLASS_HID_40655 = 0x40655,
+ BNXT_ULP_CLASS_HID_50601 = 0x50601,
+ BNXT_ULP_CLASS_HID_51545 = 0x51545,
+ BNXT_ULP_CLASS_HID_49e1b = 0x49e1b,
+ BNXT_ULP_CLASS_HID_48e1d = 0x48e1d,
+ BNXT_ULP_CLASS_HID_58d49 = 0x58d49,
+ BNXT_ULP_CLASS_HID_59d0d = 0x59d0d,
+ BNXT_ULP_CLASS_HID_40115 = 0x40115,
+ BNXT_ULP_CLASS_HID_41099 = 0x41099,
+ BNXT_ULP_CLASS_HID_51085 = 0x51085,
+ BNXT_ULP_CLASS_HID_5000f = 0x5000f,
+ BNXT_ULP_CLASS_HID_4889d = 0x4889d,
+ BNXT_ULP_CLASS_HID_49881 = 0x49881,
+ BNXT_ULP_CLASS_HID_5980d = 0x5980d,
+ BNXT_ULP_CLASS_HID_59797 = 0x59797,
+ BNXT_ULP_CLASS_HID_41c09 = 0x41c09,
+ BNXT_ULP_CLASS_HID_40c13 = 0x40c13,
+ BNXT_ULP_CLASS_HID_50b1f = 0x50b1f,
+ BNXT_ULP_CLASS_HID_51b03 = 0x51b03,
+ BNXT_ULP_CLASS_HID_48417 = 0x48417,
+ BNXT_ULP_CLASS_HID_4931b = 0x4931b,
+ BNXT_ULP_CLASS_HID_59307 = 0x59307,
+ BNXT_ULP_CLASS_HID_58309 = 0x58309,
+ BNXT_ULP_CLASS_HID_4160f = 0x4160f,
+ BNXT_ULP_CLASS_HID_40561 = 0x40561,
+ BNXT_ULP_CLASS_HID_5052d = 0x5052d,
+ BNXT_ULP_CLASS_HID_51501 = 0x51501,
+ BNXT_ULP_CLASS_HID_49dc7 = 0x49dc7,
+ BNXT_ULP_CLASS_HID_48d29 = 0x48d29,
+ BNXT_ULP_CLASS_HID_58d05 = 0x58d05,
+ BNXT_ULP_CLASS_HID_59cc9 = 0x59cc9,
+ BNXT_ULP_CLASS_HID_40161 = 0x40161,
+ BNXT_ULP_CLASS_HID_41125 = 0x41125,
+ BNXT_ULP_CLASS_HID_51061 = 0x51061,
+ BNXT_ULP_CLASS_HID_5004b = 0x5004b,
+ BNXT_ULP_CLASS_HID_48929 = 0x48929,
+ BNXT_ULP_CLASS_HID_4986d = 0x4986d,
+ BNXT_ULP_CLASS_HID_59829 = 0x59829,
+ BNXT_ULP_CLASS_HID_58823 = 0x58823,
+ BNXT_ULP_CLASS_HID_41ba5 = 0x41ba5,
+ BNXT_ULP_CLASS_HID_40b0f = 0x40b0f,
+ BNXT_ULP_CLASS_HID_50b0b = 0x50b0b,
+ BNXT_ULP_CLASS_HID_51a8f = 0x51a8f,
+ BNXT_ULP_CLASS_HID_48303 = 0x48303,
+ BNXT_ULP_CLASS_HID_49307 = 0x49307,
+ BNXT_ULP_CLASS_HID_592a3 = 0x592a3,
+ BNXT_ULP_CLASS_HID_58205 = 0x58205,
+ BNXT_ULP_CLASS_HID_4172f = 0x4172f,
+ BNXT_ULP_CLASS_HID_40621 = 0x40621,
+ BNXT_ULP_CLASS_HID_5062d = 0x5062d,
+ BNXT_ULP_CLASS_HID_51621 = 0x51621,
+ BNXT_ULP_CLASS_HID_49f07 = 0x49f07,
+ BNXT_ULP_CLASS_HID_48e29 = 0x48e29,
+ BNXT_ULP_CLASS_HID_58e25 = 0x58e25,
+ BNXT_ULP_CLASS_HID_59d29 = 0x59d29,
+ BNXT_ULP_CLASS_HID_400c9 = 0x400c9,
+ BNXT_ULP_CLASS_HID_4108d = 0x4108d,
+ BNXT_ULP_CLASS_HID_51049 = 0x51049,
+ BNXT_ULP_CLASS_HID_50fc3 = 0x50fc3,
+ BNXT_ULP_CLASS_HID_48881 = 0x48881,
+ BNXT_ULP_CLASS_HID_487cb = 0x487cb,
+ BNXT_ULP_CLASS_HID_587c7 = 0x587c7,
+ BNXT_ULP_CLASS_HID_5978b = 0x5978b,
+ BNXT_ULP_CLASS_HID_41c4d = 0x41c4d,
+ BNXT_ULP_CLASS_HID_40b47 = 0x40b47,
+ BNXT_ULP_CLASS_HID_50b03 = 0x50b03,
+ BNXT_ULP_CLASS_HID_51b47 = 0x51b47,
+ BNXT_ULP_CLASS_HID_4834b = 0x4834b,
+ BNXT_ULP_CLASS_HID_4930f = 0x4930f,
+ BNXT_ULP_CLASS_HID_5934b = 0x5934b,
+ BNXT_ULP_CLASS_HID_5824d = 0x5824d,
+ BNXT_ULP_CLASS_HID_41687 = 0x41687,
+ BNXT_ULP_CLASS_HID_40609 = 0x40609,
+ BNXT_ULP_CLASS_HID_50585 = 0x50585,
+ BNXT_ULP_CLASS_HID_51589 = 0x51589,
+ BNXT_ULP_CLASS_HID_49e0f = 0x49e0f,
+ BNXT_ULP_CLASS_HID_48d81 = 0x48d81,
+ BNXT_ULP_CLASS_HID_58d8d = 0x58d8d,
+ BNXT_ULP_CLASS_HID_59d01 = 0x59d01,
+ BNXT_ULP_CLASS_HID_40109 = 0x40109,
+ BNXT_ULP_CLASS_HID_4110d = 0x4110d,
+ BNXT_ULP_CLASS_HID_51109 = 0x51109,
+ BNXT_ULP_CLASS_HID_50003 = 0x50003,
+ BNXT_ULP_CLASS_HID_48901 = 0x48901,
+ BNXT_ULP_CLASS_HID_49905 = 0x49905,
+ BNXT_ULP_CLASS_HID_59901 = 0x59901,
+ BNXT_ULP_CLASS_HID_5880b = 0x5880b,
+ BNXT_ULP_CLASS_HID_10619 = 0x10619,
+ BNXT_ULP_CLASS_HID_11239 = 0x11239,
+ BNXT_ULP_CLASS_HID_14205 = 0x14205,
+ BNXT_ULP_CLASS_HID_15e25 = 0x15e25,
+ BNXT_ULP_CLASS_HID_12417 = 0x12417,
+ BNXT_ULP_CLASS_HID_13037 = 0x13037,
+ BNXT_ULP_CLASS_HID_16ff3 = 0x16ff3,
+ BNXT_ULP_CLASS_HID_17c13 = 0x17c13,
+ BNXT_ULP_CLASS_HID_1111d = 0x1111d,
+ BNXT_ULP_CLASS_HID_10cdb = 0x10cdb,
+ BNXT_ULP_CLASS_HID_15d19 = 0x15d19,
+ BNXT_ULP_CLASS_HID_148c7 = 0x148c7,
+ BNXT_ULP_CLASS_HID_13f0b = 0x13f0b,
+ BNXT_ULP_CLASS_HID_12ac9 = 0x12ac9,
+ BNXT_ULP_CLASS_HID_17b17 = 0x17b17,
+ BNXT_ULP_CLASS_HID_176d5 = 0x176d5,
+ BNXT_ULP_CLASS_HID_10bab = 0x10bab,
+ BNXT_ULP_CLASS_HID_10769 = 0x10769,
+ BNXT_ULP_CLASS_HID_15787 = 0x15787,
+ BNXT_ULP_CLASS_HID_14345 = 0x14345,
+ BNXT_ULP_CLASS_HID_12989 = 0x12989,
+ BNXT_ULP_CLASS_HID_12567 = 0x12567,
+ BNXT_ULP_CLASS_HID_17585 = 0x17585,
+ BNXT_ULP_CLASS_HID_16143 = 0x16143,
+ BNXT_ULP_CLASS_HID_1064d = 0x1064d,
+ BNXT_ULP_CLASS_HID_1128d = 0x1128d,
+ BNXT_ULP_CLASS_HID_14249 = 0x14249,
+ BNXT_ULP_CLASS_HID_15e49 = 0x15e49,
+ BNXT_ULP_CLASS_HID_1244b = 0x1244b,
+ BNXT_ULP_CLASS_HID_1304b = 0x1304b,
+ BNXT_ULP_CLASS_HID_16047 = 0x16047,
+ BNXT_ULP_CLASS_HID_17c47 = 0x17c47,
+ BNXT_ULP_CLASS_HID_11113 = 0x11113,
+ BNXT_ULP_CLASS_HID_10cd1 = 0x10cd1,
+ BNXT_ULP_CLASS_HID_15cf7 = 0x15cf7,
+ BNXT_ULP_CLASS_HID_148b5 = 0x148b5,
+ BNXT_ULP_CLASS_HID_13f01 = 0x13f01,
+ BNXT_ULP_CLASS_HID_12ac7 = 0x12ac7,
+ BNXT_ULP_CLASS_HID_17ae5 = 0x17ae5,
+ BNXT_ULP_CLASS_HID_176a3 = 0x176a3,
+ BNXT_ULP_CLASS_HID_10bd5 = 0x10bd5,
+ BNXT_ULP_CLASS_HID_10793 = 0x10793,
+ BNXT_ULP_CLASS_HID_15791 = 0x15791,
+ BNXT_ULP_CLASS_HID_14357 = 0x14357,
+ BNXT_ULP_CLASS_HID_129c3 = 0x129c3,
+ BNXT_ULP_CLASS_HID_12581 = 0x12581,
+ BNXT_ULP_CLASS_HID_17587 = 0x17587,
+ BNXT_ULP_CLASS_HID_16145 = 0x16145,
+ BNXT_ULP_CLASS_HID_10643 = 0x10643,
+ BNXT_ULP_CLASS_HID_11263 = 0x11263,
+ BNXT_ULP_CLASS_HID_14227 = 0x14227,
+ BNXT_ULP_CLASS_HID_15e47 = 0x15e47,
+ BNXT_ULP_CLASS_HID_12421 = 0x12421,
+ BNXT_ULP_CLASS_HID_13041 = 0x13041,
+ BNXT_ULP_CLASS_HID_16005 = 0x16005,
+ BNXT_ULP_CLASS_HID_17c25 = 0x17c25,
+ BNXT_ULP_CLASS_HID_11147 = 0x11147,
+ BNXT_ULP_CLASS_HID_10d05 = 0x10d05,
+ BNXT_ULP_CLASS_HID_15d43 = 0x15d43,
+ BNXT_ULP_CLASS_HID_14901 = 0x14901,
+ BNXT_ULP_CLASS_HID_13f45 = 0x13f45,
+ BNXT_ULP_CLASS_HID_12b03 = 0x12b03,
+ BNXT_ULP_CLASS_HID_17b01 = 0x17b01,
+ BNXT_ULP_CLASS_HID_176c7 = 0x176c7,
+ BNXT_ULP_CLASS_HID_11bcf = 0x11bcf,
+ BNXT_ULP_CLASS_HID_1178d = 0x1178d,
+ BNXT_ULP_CLASS_HID_1474d = 0x1474d,
+ BNXT_ULP_CLASS_HID_1536d = 0x1536d,
+ BNXT_ULP_CLASS_HID_139bd = 0x139bd,
+ BNXT_ULP_CLASS_HID_1357f = 0x1357f,
+ BNXT_ULP_CLASS_HID_16547 = 0x16547,
+ BNXT_ULP_CLASS_HID_17167 = 0x17167,
+ BNXT_ULP_CLASS_HID_11685 = 0x11685,
+ BNXT_ULP_CLASS_HID_1024f = 0x1024f,
+ BNXT_ULP_CLASS_HID_1524d = 0x1524d,
+ BNXT_ULP_CLASS_HID_14e0f = 0x14e0f,
+ BNXT_ULP_CLASS_HID_1345f = 0x1345f,
+ BNXT_ULP_CLASS_HID_1201d = 0x1201d,
+ BNXT_ULP_CLASS_HID_1705f = 0x1705f,
+ BNXT_ULP_CLASS_HID_16c1d = 0x16c1d,
+ BNXT_ULP_CLASS_HID_100ef = 0x100ef,
+ BNXT_ULP_CLASS_HID_11d0f = 0x11d0f,
+ BNXT_ULP_CLASS_HID_14ccf = 0x14ccf,
+ BNXT_ULP_CLASS_HID_158ef = 0x158ef,
+ BNXT_ULP_CLASS_HID_12eed = 0x12eed,
+ BNXT_ULP_CLASS_HID_13b0d = 0x13b0d,
+ BNXT_ULP_CLASS_HID_16acd = 0x16acd,
+ BNXT_ULP_CLASS_HID_16687 = 0x16687,
+ BNXT_ULP_CLASS_HID_11c07 = 0x11c07,
+ BNXT_ULP_CLASS_HID_117c5 = 0x117c5,
+ BNXT_ULP_CLASS_HID_1478d = 0x1478d,
+ BNXT_ULP_CLASS_HID_1538d = 0x1538d,
+ BNXT_ULP_CLASS_HID_13a05 = 0x13a05,
+ BNXT_ULP_CLASS_HID_135cf = 0x135cf,
+ BNXT_ULP_CLASS_HID_1658f = 0x1658f,
+ BNXT_ULP_CLASS_HID_1718f = 0x1718f,
+ BNXT_ULP_CLASS_HID_11667 = 0x11667,
+ BNXT_ULP_CLASS_HID_10225 = 0x10225,
+ BNXT_ULP_CLASS_HID_15247 = 0x15247,
+ BNXT_ULP_CLASS_HID_14e05 = 0x14e05,
+ BNXT_ULP_CLASS_HID_13455 = 0x13455,
+ BNXT_ULP_CLASS_HID_12017 = 0x12017,
+ BNXT_ULP_CLASS_HID_17035 = 0x17035,
+ BNXT_ULP_CLASS_HID_16bf7 = 0x16bf7,
+ BNXT_ULP_CLASS_HID_10115 = 0x10115,
+ BNXT_ULP_CLASS_HID_11d15 = 0x11d15,
+ BNXT_ULP_CLASS_HID_14d05 = 0x14d05,
+ BNXT_ULP_CLASS_HID_15905 = 0x15905,
+ BNXT_ULP_CLASS_HID_12f17 = 0x12f17,
+ BNXT_ULP_CLASS_HID_13b17 = 0x13b17,
+ BNXT_ULP_CLASS_HID_16ad7 = 0x16ad7,
+ BNXT_ULP_CLASS_HID_16695 = 0x16695,
+ BNXT_ULP_CLASS_HID_11be5 = 0x11be5,
+ BNXT_ULP_CLASS_HID_117a7 = 0x117a7,
+ BNXT_ULP_CLASS_HID_14767 = 0x14767,
+ BNXT_ULP_CLASS_HID_15387 = 0x15387,
+ BNXT_ULP_CLASS_HID_139e7 = 0x139e7,
+ BNXT_ULP_CLASS_HID_135a5 = 0x135a5,
+ BNXT_ULP_CLASS_HID_16565 = 0x16565,
+ BNXT_ULP_CLASS_HID_17185 = 0x17185,
+ BNXT_ULP_CLASS_HID_11687 = 0x11687,
+ BNXT_ULP_CLASS_HID_10245 = 0x10245,
+ BNXT_ULP_CLASS_HID_15287 = 0x15287,
+ BNXT_ULP_CLASS_HID_14e45 = 0x14e45,
+ BNXT_ULP_CLASS_HID_13485 = 0x13485,
+ BNXT_ULP_CLASS_HID_12047 = 0x12047,
+ BNXT_ULP_CLASS_HID_17085 = 0x17085,
+ BNXT_ULP_CLASS_HID_16c47 = 0x16c47,
+ BNXT_ULP_CLASS_HID_400f4 = 0x400f4,
+ BNXT_ULP_CLASS_HID_410c8 = 0x410c8,
+ BNXT_ULP_CLASS_HID_51084 = 0x51084,
+ BNXT_ULP_CLASS_HID_50ffe = 0x50ffe,
+ BNXT_ULP_CLASS_HID_488cc = 0x488cc,
+ BNXT_ULP_CLASS_HID_48726 = 0x48726,
+ BNXT_ULP_CLASS_HID_587f2 = 0x587f2,
+ BNXT_ULP_CLASS_HID_597b6 = 0x597b6,
+ BNXT_ULP_CLASS_HID_41b10 = 0x41b10,
+ BNXT_ULP_CLASS_HID_40b8a = 0x40b8a,
+ BNXT_ULP_CLASS_HID_50a46 = 0x50a46,
+ BNXT_ULP_CLASS_HID_51a1a = 0x51a1a,
+ BNXT_ULP_CLASS_HID_4838e = 0x4838e,
+ BNXT_ULP_CLASS_HID_49242 = 0x49242,
+ BNXT_ULP_CLASS_HID_5921e = 0x5921e,
+ BNXT_ULP_CLASS_HID_58150 = 0x58150,
+ BNXT_ULP_CLASS_HID_41686 = 0x41686,
+ BNXT_ULP_CLASS_HID_405e8 = 0x405e8,
+ BNXT_ULP_CLASS_HID_505a4 = 0x505a4,
+ BNXT_ULP_CLASS_HID_51588 = 0x51588,
+ BNXT_ULP_CLASS_HID_49d4e = 0x49d4e,
+ BNXT_ULP_CLASS_HID_48da0 = 0x48da0,
+ BNXT_ULP_CLASS_HID_58d8c = 0x58d8c,
+ BNXT_ULP_CLASS_HID_59c40 = 0x59c40,
+ BNXT_ULP_CLASS_HID_40040 = 0x40040,
+ BNXT_ULP_CLASS_HID_41004 = 0x41004,
+ BNXT_ULP_CLASS_HID_510c0 = 0x510c0,
+ BNXT_ULP_CLASS_HID_50f4a = 0x50f4a,
+ BNXT_ULP_CLASS_HID_48808 = 0x48808,
+ BNXT_ULP_CLASS_HID_48742 = 0x48742,
+ BNXT_ULP_CLASS_HID_5874e = 0x5874e,
+ BNXT_ULP_CLASS_HID_59702 = 0x59702,
+ BNXT_ULP_CLASS_HID_41bfe = 0x41bfe,
+ BNXT_ULP_CLASS_HID_40a58 = 0x40a58,
+ BNXT_ULP_CLASS_HID_50a2c = 0x50a2c,
+ BNXT_ULP_CLASS_HID_51ae8 = 0x51ae8,
+ BNXT_ULP_CLASS_HID_4825c = 0x4825c,
+ BNXT_ULP_CLASS_HID_49228 = 0x49228,
+ BNXT_ULP_CLASS_HID_592ec = 0x592ec,
+ BNXT_ULP_CLASS_HID_5815e = 0x5815e,
+ BNXT_ULP_CLASS_HID_41698 = 0x41698,
+ BNXT_ULP_CLASS_HID_4051a = 0x4051a,
+ BNXT_ULP_CLASS_HID_505ce = 0x505ce,
+ BNXT_ULP_CLASS_HID_5158a = 0x5158a,
+ BNXT_ULP_CLASS_HID_49d58 = 0x49d58,
+ BNXT_ULP_CLASS_HID_48dca = 0x48dca,
+ BNXT_ULP_CLASS_HID_58d8e = 0x58d8e,
+ BNXT_ULP_CLASS_HID_59c5a = 0x59c5a,
+ BNXT_ULP_CLASS_HID_4002e = 0x4002e,
+ BNXT_ULP_CLASS_HID_410ea = 0x410ea,
+ BNXT_ULP_CLASS_HID_510ae = 0x510ae,
+ BNXT_ULP_CLASS_HID_50f08 = 0x50f08,
+ BNXT_ULP_CLASS_HID_488ee = 0x488ee,
+ BNXT_ULP_CLASS_HID_48748 = 0x48748,
+ BNXT_ULP_CLASS_HID_5870c = 0x5870c,
+ BNXT_ULP_CLASS_HID_597e8 = 0x597e8,
+ BNXT_ULP_CLASS_HID_41b4a = 0x41b4a,
+ BNXT_ULP_CLASS_HID_40b8c = 0x40b8c,
+ BNXT_ULP_CLASS_HID_50a48 = 0x50a48,
+ BNXT_ULP_CLASS_HID_51a0c = 0x51a0c,
+ BNXT_ULP_CLASS_HID_48388 = 0x48388,
+ BNXT_ULP_CLASS_HID_4924c = 0x4924c,
+ BNXT_ULP_CLASS_HID_59208 = 0x59208,
+ BNXT_ULP_CLASS_HID_5828a = 0x5828a,
+ BNXT_ULP_CLASS_HID_40540 = 0x40540,
+ BNXT_ULP_CLASS_HID_41500 = 0x41500,
+ BNXT_ULP_CLASS_HID_515d0 = 0x515d0,
+ BNXT_ULP_CLASS_HID_5044a = 0x5044a,
+ BNXT_ULP_CLASS_HID_48d18 = 0x48d18,
+ BNXT_ULP_CLASS_HID_49dd8 = 0x49dd8,
+ BNXT_ULP_CLASS_HID_59da8 = 0x59da8,
+ BNXT_ULP_CLASS_HID_58c02 = 0x58c02,
+ BNXT_ULP_CLASS_HID_41048 = 0x41048,
+ BNXT_ULP_CLASS_HID_400c2 = 0x400c2,
+ BNXT_ULP_CLASS_HID_50092 = 0x50092,
+ BNXT_ULP_CLASS_HID_51f52 = 0x51f52,
+ BNXT_ULP_CLASS_HID_49800 = 0x49800,
+ BNXT_ULP_CLASS_HID_4889a = 0x4889a,
+ BNXT_ULP_CLASS_HID_5974a = 0x5974a,
+ BNXT_ULP_CLASS_HID_587c8 = 0x587c8,
+ BNXT_ULP_CLASS_HID_40bc2 = 0x40bc2,
+ BNXT_ULP_CLASS_HID_41b82 = 0x41b82,
+ BNXT_ULP_CLASS_HID_51a62 = 0x51a62,
+ BNXT_ULP_CLASS_HID_50ac0 = 0x50ac0,
+ BNXT_ULP_CLASS_HID_493aa = 0x493aa,
+ BNXT_ULP_CLASS_HID_48208 = 0x48208,
+ BNXT_ULP_CLASS_HID_582c8 = 0x582c8,
+ BNXT_ULP_CLASS_HID_59288 = 0x59288,
+ BNXT_ULP_CLASS_HID_40688 = 0x40688,
+ BNXT_ULP_CLASS_HID_41540 = 0x41540,
+ BNXT_ULP_CLASS_HID_51508 = 0x51508,
+ BNXT_ULP_CLASS_HID_50582 = 0x50582,
+ BNXT_ULP_CLASS_HID_48d40 = 0x48d40,
+ BNXT_ULP_CLASS_HID_49d08 = 0x49d08,
+ BNXT_ULP_CLASS_HID_59dc0 = 0x59dc0,
+ BNXT_ULP_CLASS_HID_58c4a = 0x58c4a,
+ BNXT_ULP_CLASS_HID_4104a = 0x4104a,
+ BNXT_ULP_CLASS_HID_400a8 = 0x400a8,
+ BNXT_ULP_CLASS_HID_50f78 = 0x50f78,
+ BNXT_ULP_CLASS_HID_51f38 = 0x51f38,
+ BNXT_ULP_CLASS_HID_4980a = 0x4980a,
+ BNXT_ULP_CLASS_HID_49768 = 0x49768,
+ BNXT_ULP_CLASS_HID_59738 = 0x59738,
+ BNXT_ULP_CLASS_HID_587aa = 0x587aa,
+ BNXT_ULP_CLASS_HID_40bd8 = 0x40bd8,
+ BNXT_ULP_CLASS_HID_41bc8 = 0x41bc8,
+ BNXT_ULP_CLASS_HID_51b88 = 0x51b88,
+ BNXT_ULP_CLASS_HID_50ada = 0x50ada,
+ BNXT_ULP_CLASS_HID_493c8 = 0x493c8,
+ BNXT_ULP_CLASS_HID_4820a = 0x4820a,
+ BNXT_ULP_CLASS_HID_582da = 0x582da,
+ BNXT_ULP_CLASS_HID_5929a = 0x5929a,
+ BNXT_ULP_CLASS_HID_4056a = 0x4056a,
+ BNXT_ULP_CLASS_HID_4152a = 0x4152a,
+ BNXT_ULP_CLASS_HID_5150a = 0x5150a,
+ BNXT_ULP_CLASS_HID_50468 = 0x50468,
+ BNXT_ULP_CLASS_HID_48d2a = 0x48d2a,
+ BNXT_ULP_CLASS_HID_49dea = 0x49dea,
+ BNXT_ULP_CLASS_HID_59dca = 0x59dca,
+ BNXT_ULP_CLASS_HID_58c28 = 0x58c28,
+ BNXT_ULP_CLASS_HID_4118a = 0x4118a,
+ BNXT_ULP_CLASS_HID_400c8 = 0x400c8,
+ BNXT_ULP_CLASS_HID_50088 = 0x50088,
+ BNXT_ULP_CLASS_HID_51088 = 0x51088,
+ BNXT_ULP_CLASS_HID_4984a = 0x4984a,
+ BNXT_ULP_CLASS_HID_48888 = 0x48888,
+ BNXT_ULP_CLASS_HID_58888 = 0x58888,
+ BNXT_ULP_CLASS_HID_587ca = 0x587ca,
+ BNXT_ULP_CLASS_HID_10690 = 0x10690,
+ BNXT_ULP_CLASS_HID_112b0 = 0x112b0,
+ BNXT_ULP_CLASS_HID_1428c = 0x1428c,
+ BNXT_ULP_CLASS_HID_15eac = 0x15eac,
+ BNXT_ULP_CLASS_HID_1249e = 0x1249e,
+ BNXT_ULP_CLASS_HID_130be = 0x130be,
+ BNXT_ULP_CLASS_HID_16f7a = 0x16f7a,
+ BNXT_ULP_CLASS_HID_17c9a = 0x17c9a,
+ BNXT_ULP_CLASS_HID_1119a = 0x1119a,
+ BNXT_ULP_CLASS_HID_10c58 = 0x10c58,
+ BNXT_ULP_CLASS_HID_15c7e = 0x15c7e,
+ BNXT_ULP_CLASS_HID_1483c = 0x1483c,
+ BNXT_ULP_CLASS_HID_13f88 = 0x13f88,
+ BNXT_ULP_CLASS_HID_12a4e = 0x12a4e,
+ BNXT_ULP_CLASS_HID_17a6c = 0x17a6c,
+ BNXT_ULP_CLASS_HID_1762a = 0x1762a,
+ BNXT_ULP_CLASS_HID_11b46 = 0x11b46,
+ BNXT_ULP_CLASS_HID_11704 = 0x11704,
+ BNXT_ULP_CLASS_HID_147c4 = 0x147c4,
+ BNXT_ULP_CLASS_HID_153e4 = 0x153e4,
+ BNXT_ULP_CLASS_HID_13934 = 0x13934,
+ BNXT_ULP_CLASS_HID_135f6 = 0x135f6,
+ BNXT_ULP_CLASS_HID_165ce = 0x165ce,
+ BNXT_ULP_CLASS_HID_171ee = 0x171ee,
+ BNXT_ULP_CLASS_HID_116ee = 0x116ee,
+ BNXT_ULP_CLASS_HID_102ac = 0x102ac,
+ BNXT_ULP_CLASS_HID_152ce = 0x152ce,
+ BNXT_ULP_CLASS_HID_14e8c = 0x14e8c,
+ BNXT_ULP_CLASS_HID_134dc = 0x134dc,
+ BNXT_ULP_CLASS_HID_1209e = 0x1209e,
+ BNXT_ULP_CLASS_HID_170bc = 0x170bc,
+ BNXT_ULP_CLASS_HID_16b7e = 0x16b7e,
+ BNXT_ULP_CLASS_HID_119ae = 0x119ae,
+ BNXT_ULP_CLASS_HID_1146a = 0x1146a,
+ BNXT_ULP_CLASS_HID_14426 = 0x14426,
+ BNXT_ULP_CLASS_HID_15046 = 0x15046,
+ BNXT_ULP_CLASS_HID_1263a = 0x1263a,
+ BNXT_ULP_CLASS_HID_1325a = 0x1325a,
+ BNXT_ULP_CLASS_HID_16216 = 0x16216,
+ BNXT_ULP_CLASS_HID_17e36 = 0x17e36,
+ BNXT_ULP_CLASS_HID_1133e = 0x1133e,
+ BNXT_ULP_CLASS_HID_10ffa = 0x10ffa,
+ BNXT_ULP_CLASS_HID_15f1a = 0x15f1a,
+ BNXT_ULP_CLASS_HID_14bee = 0x14bee,
+ BNXT_ULP_CLASS_HID_1312a = 0x1312a,
+ BNXT_ULP_CLASS_HID_12dea = 0x12dea,
+ BNXT_ULP_CLASS_HID_17d1e = 0x17d1e,
+ BNXT_ULP_CLASS_HID_169de = 0x169de,
+ BNXT_ULP_CLASS_HID_11ee6 = 0x11ee6,
+ BNXT_ULP_CLASS_HID_10abe = 0x10abe,
+ BNXT_ULP_CLASS_HID_15ade = 0x15ade,
+ BNXT_ULP_CLASS_HID_1569e = 0x1569e,
+ BNXT_ULP_CLASS_HID_13cee = 0x13cee,
+ BNXT_ULP_CLASS_HID_128ae = 0x128ae,
+ BNXT_ULP_CLASS_HID_1676e = 0x1676e,
+ BNXT_ULP_CLASS_HID_1748e = 0x1748e,
+ BNXT_ULP_CLASS_HID_1098e = 0x1098e,
+ BNXT_ULP_CLASS_HID_1044e = 0x1044e,
+ BNXT_ULP_CLASS_HID_1546e = 0x1546e,
+ BNXT_ULP_CLASS_HID_1402e = 0x1402e,
+ BNXT_ULP_CLASS_HID_1367e = 0x1367e,
+ BNXT_ULP_CLASS_HID_1223e = 0x1223e,
+ BNXT_ULP_CLASS_HID_1725e = 0x1725e,
+ BNXT_ULP_CLASS_HID_16e1e = 0x16e1e,
+ BNXT_ULP_CLASS_HID_1172f = 0x1172f,
+ BNXT_ULP_CLASS_HID_103ed = 0x103ed,
+ BNXT_ULP_CLASS_HID_1530b = 0x1530b,
+ BNXT_ULP_CLASS_HID_14fc9 = 0x14fc9,
+ BNXT_ULP_CLASS_HID_1351d = 0x1351d,
+ BNXT_ULP_CLASS_HID_121db = 0x121db,
+ BNXT_ULP_CLASS_HID_171f9 = 0x171f9,
+ BNXT_ULP_CLASS_HID_16db7 = 0x16db7,
+ BNXT_ULP_CLASS_HID_102bf = 0x102bf,
+ BNXT_ULP_CLASS_HID_11edf = 0x11edf,
+ BNXT_ULP_CLASS_HID_14e9b = 0x14e9b,
+ BNXT_ULP_CLASS_HID_15abb = 0x15abb,
+ BNXT_ULP_CLASS_HID_120ad = 0x120ad,
+ BNXT_ULP_CLASS_HID_13ccd = 0x13ccd,
+ BNXT_ULP_CLASS_HID_16c89 = 0x16c89,
+ BNXT_ULP_CLASS_HID_1675f = 0x1675f,
+ BNXT_ULP_CLASS_HID_10c67 = 0x10c67,
+ BNXT_ULP_CLASS_HID_11987 = 0x11987,
+ BNXT_ULP_CLASS_HID_1485f = 0x1485f,
+ BNXT_ULP_CLASS_HID_1441d = 0x1441d,
+ BNXT_ULP_CLASS_HID_12a55 = 0x12a55,
+ BNXT_ULP_CLASS_HID_1262f = 0x1262f,
+ BNXT_ULP_CLASS_HID_1764d = 0x1764d,
+ BNXT_ULP_CLASS_HID_1620f = 0x1620f,
+ BNXT_ULP_CLASS_HID_1070f = 0x1070f,
+ BNXT_ULP_CLASS_HID_1132f = 0x1132f,
+ BNXT_ULP_CLASS_HID_143ef = 0x143ef,
+ BNXT_ULP_CLASS_HID_15f0f = 0x15f0f,
+ BNXT_ULP_CLASS_HID_125fd = 0x125fd,
+ BNXT_ULP_CLASS_HID_1311d = 0x1311d,
+ BNXT_ULP_CLASS_HID_161dd = 0x161dd,
+ BNXT_ULP_CLASS_HID_17dfd = 0x17dfd,
+ BNXT_ULP_CLASS_HID_10acb = 0x10acb,
+ BNXT_ULP_CLASS_HID_10687 = 0x10687,
+ BNXT_ULP_CLASS_HID_156a7 = 0x156a7,
+ BNXT_ULP_CLASS_HID_14163 = 0x14163,
+ BNXT_ULP_CLASS_HID_128b7 = 0x128b7,
+ BNXT_ULP_CLASS_HID_12377 = 0x12377,
+ BNXT_ULP_CLASS_HID_17493 = 0x17493,
+ BNXT_ULP_CLASS_HID_16f53 = 0x16f53,
+ BNXT_ULP_CLASS_HID_1045b = 0x1045b,
+ BNXT_ULP_CLASS_HID_1107b = 0x1107b,
+ BNXT_ULP_CLASS_HID_1404f = 0x1404f,
+ BNXT_ULP_CLASS_HID_15c6f = 0x15c6f,
+ BNXT_ULP_CLASS_HID_1225f = 0x1225f,
+ BNXT_ULP_CLASS_HID_13e7f = 0x13e7f,
+ BNXT_ULP_CLASS_HID_16e3b = 0x16e3b,
+ BNXT_ULP_CLASS_HID_17a5b = 0x17a5b,
+ BNXT_ULP_CLASS_HID_10f1f = 0x10f1f,
+ BNXT_ULP_CLASS_HID_11b3f = 0x11b3f,
+ BNXT_ULP_CLASS_HID_14bff = 0x14bff,
+ BNXT_ULP_CLASS_HID_147b7 = 0x147b7,
+ BNXT_ULP_CLASS_HID_12d0f = 0x12d0f,
+ BNXT_ULP_CLASS_HID_1392f = 0x1392f,
+ BNXT_ULP_CLASS_HID_169e7 = 0x169e7,
+ BNXT_ULP_CLASS_HID_165a7 = 0x165a7,
+ BNXT_ULP_CLASS_HID_11a0f = 0x11a0f,
+ BNXT_ULP_CLASS_HID_116cf = 0x116cf,
+ BNXT_ULP_CLASS_HID_1468f = 0x1468f,
+ BNXT_ULP_CLASS_HID_152af = 0x152af,
+ BNXT_ULP_CLASS_HID_138ff = 0x138ff,
+ BNXT_ULP_CLASS_HID_134bf = 0x134bf,
+ BNXT_ULP_CLASS_HID_1648f = 0x1648f,
+ BNXT_ULP_CLASS_HID_170af = 0x170af,
+ BNXT_ULP_CLASS_HID_40c38 = 0x40c38,
+ BNXT_ULP_CLASS_HID_41c04 = 0x41c04,
+ BNXT_ULP_CLASS_HID_51c48 = 0x51c48,
+ BNXT_ULP_CLASS_HID_50332 = 0x50332,
+ BNXT_ULP_CLASS_HID_48400 = 0x48400,
+ BNXT_ULP_CLASS_HID_48bea = 0x48bea,
+ BNXT_ULP_CLASS_HID_58b3e = 0x58b3e,
+ BNXT_ULP_CLASS_HID_59b7a = 0x59b7a,
+ BNXT_ULP_CLASS_HID_417dc = 0x417dc,
+ BNXT_ULP_CLASS_HID_40746 = 0x40746,
+ BNXT_ULP_CLASS_HID_5068a = 0x5068a,
+ BNXT_ULP_CLASS_HID_516d6 = 0x516d6,
+ BNXT_ULP_CLASS_HID_48f42 = 0x48f42,
+ BNXT_ULP_CLASS_HID_49e8e = 0x49e8e,
+ BNXT_ULP_CLASS_HID_59ed2 = 0x59ed2,
+ BNXT_ULP_CLASS_HID_58d9c = 0x58d9c,
+ BNXT_ULP_CLASS_HID_41a4a = 0x41a4a,
+ BNXT_ULP_CLASS_HID_40924 = 0x40924,
+ BNXT_ULP_CLASS_HID_50968 = 0x50968,
+ BNXT_ULP_CLASS_HID_51944 = 0x51944,
+ BNXT_ULP_CLASS_HID_49182 = 0x49182,
+ BNXT_ULP_CLASS_HID_4816c = 0x4816c,
+ BNXT_ULP_CLASS_HID_58140 = 0x58140,
+ BNXT_ULP_CLASS_HID_5908c = 0x5908c,
+ BNXT_ULP_CLASS_HID_40c8c = 0x40c8c,
+ BNXT_ULP_CLASS_HID_41cc8 = 0x41cc8,
+ BNXT_ULP_CLASS_HID_51c0c = 0x51c0c,
+ BNXT_ULP_CLASS_HID_50386 = 0x50386,
+ BNXT_ULP_CLASS_HID_484c4 = 0x484c4,
+ BNXT_ULP_CLASS_HID_48b8e = 0x48b8e,
+ BNXT_ULP_CLASS_HID_58b82 = 0x58b82,
+ BNXT_ULP_CLASS_HID_59bce = 0x59bce,
+ BNXT_ULP_CLASS_HID_10a54 = 0x10a54,
+ BNXT_ULP_CLASS_HID_11e74 = 0x11e74,
+ BNXT_ULP_CLASS_HID_14e48 = 0x14e48,
+ BNXT_ULP_CLASS_HID_15268 = 0x15268,
+ BNXT_ULP_CLASS_HID_1285a = 0x1285a,
+ BNXT_ULP_CLASS_HID_13c7a = 0x13c7a,
+ BNXT_ULP_CLASS_HID_163be = 0x163be,
+ BNXT_ULP_CLASS_HID_1705e = 0x1705e,
+ BNXT_ULP_CLASS_HID_11d5e = 0x11d5e,
+ BNXT_ULP_CLASS_HID_1009c = 0x1009c,
+ BNXT_ULP_CLASS_HID_150ba = 0x150ba,
+ BNXT_ULP_CLASS_HID_144f8 = 0x144f8,
+ BNXT_ULP_CLASS_HID_1334c = 0x1334c,
+ BNXT_ULP_CLASS_HID_1268a = 0x1268a,
+ BNXT_ULP_CLASS_HID_176a8 = 0x176a8,
+ BNXT_ULP_CLASS_HID_17aee = 0x17aee,
+ BNXT_ULP_CLASS_HID_11782 = 0x11782,
+ BNXT_ULP_CLASS_HID_11bc0 = 0x11bc0,
+ BNXT_ULP_CLASS_HID_14b00 = 0x14b00,
+ BNXT_ULP_CLASS_HID_15f20 = 0x15f20,
+ BNXT_ULP_CLASS_HID_135f0 = 0x135f0,
+ BNXT_ULP_CLASS_HID_13932 = 0x13932,
+ BNXT_ULP_CLASS_HID_1690a = 0x1690a,
+ BNXT_ULP_CLASS_HID_17d2a = 0x17d2a,
+ BNXT_ULP_CLASS_HID_11a2a = 0x11a2a,
+ BNXT_ULP_CLASS_HID_10e68 = 0x10e68,
+ BNXT_ULP_CLASS_HID_15e0a = 0x15e0a,
+ BNXT_ULP_CLASS_HID_14248 = 0x14248,
+ BNXT_ULP_CLASS_HID_13818 = 0x13818,
+ BNXT_ULP_CLASS_HID_12c5a = 0x12c5a,
+ BNXT_ULP_CLASS_HID_17c78 = 0x17c78,
+ BNXT_ULP_CLASS_HID_167ba = 0x167ba,
+ BNXT_ULP_CLASS_HID_1f91 = 0x1f91,
+ BNXT_ULP_CLASS_HID_0763 = 0x0763,
+ BNXT_ULP_CLASS_HID_0f7b = 0x0f7b,
+ BNXT_ULP_CLASS_HID_16af = 0x16af,
+ BNXT_ULP_CLASS_HID_1daf = 0x1daf,
+ BNXT_ULP_CLASS_HID_0539 = 0x0539,
+ BNXT_ULP_CLASS_HID_01ed = 0x01ed,
+ BNXT_ULP_CLASS_HID_097f = 0x097f,
+ BNXT_ULP_CLASS_HID_81ab8 = 0x81ab8,
+ BNXT_ULP_CLASS_HID_8020e = 0x8020e,
+ BNXT_ULP_CLASS_HID_815d8 = 0x815d8,
+ BNXT_ULP_CLASS_HID_81cae = 0x81cae,
+ BNXT_ULP_CLASS_HID_810a8 = 0x810a8,
+ BNXT_ULP_CLASS_HID_8183e = 0x8183e,
+ BNXT_ULP_CLASS_HID_8036a = 0x8036a,
+ BNXT_ULP_CLASS_HID_80af8 = 0x80af8,
+ BNXT_ULP_CLASS_HID_206fe = 0x206fe,
+ BNXT_ULP_CLASS_HID_20e4c = 0x20e4c,
+ BNXT_ULP_CLASS_HID_2111e = 0x2111e,
+ BNXT_ULP_CLASS_HID_218ec = 0x218ec,
+ BNXT_ULP_CLASS_HID_60472 = 0x60472,
+ BNXT_ULP_CLASS_HID_603c0 = 0x603c0,
+ BNXT_ULP_CLASS_HID_61692 = 0x61692,
+ BNXT_ULP_CLASS_HID_61e60 = 0x61e60,
+ BNXT_ULP_CLASS_HID_1f81 = 0x1f81,
+ BNXT_ULP_CLASS_HID_0773 = 0x0773,
+ BNXT_ULP_CLASS_HID_0f6b = 0x0f6b,
+ BNXT_ULP_CLASS_HID_16bf = 0x16bf,
+ BNXT_ULP_CLASS_HID_03cf = 0x03cf,
+ BNXT_ULP_CLASS_HID_0ab1 = 0x0ab1,
+ BNXT_ULP_CLASS_HID_130b = 0x130b,
+ BNXT_ULP_CLASS_HID_1afd = 0x1afd,
+ BNXT_ULP_CLASS_HID_1591 = 0x1591,
+ BNXT_ULP_CLASS_HID_1d03 = 0x1d03,
+ BNXT_ULP_CLASS_HID_057b = 0x057b,
+ BNXT_ULP_CLASS_HID_0ced = 0x0ced,
+ BNXT_ULP_CLASS_HID_19df = 0x19df,
+ BNXT_ULP_CLASS_HID_0141 = 0x0141,
+ BNXT_ULP_CLASS_HID_08b9 = 0x08b9,
+ BNXT_ULP_CLASS_HID_108d = 0x108d,
+ BNXT_ULP_CLASS_HID_1dbf = 0x1dbf,
+ BNXT_ULP_CLASS_HID_0529 = 0x0529,
+ BNXT_ULP_CLASS_HID_01fd = 0x01fd,
+ BNXT_ULP_CLASS_HID_096f = 0x096f,
+ BNXT_ULP_CLASS_HID_810b7 = 0x810b7,
+ BNXT_ULP_CLASS_HID_81821 = 0x81821,
+ BNXT_ULP_CLASS_HID_804f5 = 0x804f5,
+ BNXT_ULP_CLASS_HID_80c67 = 0x80c67,
+ BNXT_ULP_CLASS_HID_41333 = 0x41333,
+ BNXT_ULP_CLASS_HID_41aad = 0x41aad,
+ BNXT_ULP_CLASS_HID_40771 = 0x40771,
+ BNXT_ULP_CLASS_HID_40ee3 = 0x40ee3,
+ BNXT_ULP_CLASS_HID_c16cb = 0xc16cb,
+ BNXT_ULP_CLASS_HID_c1da5 = 0xc1da5,
+ BNXT_ULP_CLASS_HID_c1a09 = 0xc1a09,
+ BNXT_ULP_CLASS_HID_c01fb = 0xc01fb,
+ BNXT_ULP_CLASS_HID_1ff1 = 0x1ff1,
+ BNXT_ULP_CLASS_HID_0703 = 0x0703,
+ BNXT_ULP_CLASS_HID_0f1b = 0x0f1b,
+ BNXT_ULP_CLASS_HID_16cf = 0x16cf,
+ BNXT_ULP_CLASS_HID_03bf = 0x03bf,
+ BNXT_ULP_CLASS_HID_0ac1 = 0x0ac1,
+ BNXT_ULP_CLASS_HID_137b = 0x137b,
+ BNXT_ULP_CLASS_HID_1a8d = 0x1a8d,
+ BNXT_ULP_CLASS_HID_15e1 = 0x15e1,
+ BNXT_ULP_CLASS_HID_1d73 = 0x1d73,
+ BNXT_ULP_CLASS_HID_050b = 0x050b,
+ BNXT_ULP_CLASS_HID_0c9d = 0x0c9d,
+ BNXT_ULP_CLASS_HID_19af = 0x19af,
+ BNXT_ULP_CLASS_HID_0131 = 0x0131,
+ BNXT_ULP_CLASS_HID_08c9 = 0x08c9,
+ BNXT_ULP_CLASS_HID_10fd = 0x10fd,
+ BNXT_ULP_CLASS_HID_1dcf = 0x1dcf,
+ BNXT_ULP_CLASS_HID_0559 = 0x0559,
+ BNXT_ULP_CLASS_HID_018d = 0x018d,
+ BNXT_ULP_CLASS_HID_091f = 0x091f,
+ BNXT_ULP_CLASS_HID_810c7 = 0x810c7,
+ BNXT_ULP_CLASS_HID_81851 = 0x81851,
+ BNXT_ULP_CLASS_HID_80485 = 0x80485,
+ BNXT_ULP_CLASS_HID_80c17 = 0x80c17,
+ BNXT_ULP_CLASS_HID_41343 = 0x41343,
+ BNXT_ULP_CLASS_HID_41add = 0x41add,
+ BNXT_ULP_CLASS_HID_40701 = 0x40701,
+ BNXT_ULP_CLASS_HID_40e93 = 0x40e93,
+ BNXT_ULP_CLASS_HID_c16bb = 0xc16bb,
+ BNXT_ULP_CLASS_HID_c1dd5 = 0xc1dd5,
+ BNXT_ULP_CLASS_HID_c1a79 = 0xc1a79,
+ BNXT_ULP_CLASS_HID_c018b = 0xc018b,
+ BNXT_ULP_CLASS_HID_81aa8 = 0x81aa8,
+ BNXT_ULP_CLASS_HID_8021e = 0x8021e,
+ BNXT_ULP_CLASS_HID_815c8 = 0x815c8,
+ BNXT_ULP_CLASS_HID_81cbe = 0x81cbe,
+ BNXT_ULP_CLASS_HID_810b8 = 0x810b8,
+ BNXT_ULP_CLASS_HID_8182e = 0x8182e,
+ BNXT_ULP_CLASS_HID_8037a = 0x8037a,
+ BNXT_ULP_CLASS_HID_80ae8 = 0x80ae8,
+ BNXT_ULP_CLASS_HID_c1834 = 0xc1834,
+ BNXT_ULP_CLASS_HID_c079a = 0xc079a,
+ BNXT_ULP_CLASS_HID_c0af6 = 0xc0af6,
+ BNXT_ULP_CLASS_HID_c123a = 0xc123a,
+ BNXT_ULP_CLASS_HID_c16c4 = 0xc16c4,
+ BNXT_ULP_CLASS_HID_c1daa = 0xc1daa,
+ BNXT_ULP_CLASS_HID_c0086 = 0xc0086,
+ BNXT_ULP_CLASS_HID_c0874 = 0xc0874,
+ BNXT_ULP_CLASS_HID_a19ea = 0xa19ea,
+ BNXT_ULP_CLASS_HID_a0158 = 0xa0158,
+ BNXT_ULP_CLASS_HID_a0bb4 = 0xa0bb4,
+ BNXT_ULP_CLASS_HID_a13f8 = 0xa13f8,
+ BNXT_ULP_CLASS_HID_a17fa = 0xa17fa,
+ BNXT_ULP_CLASS_HID_a1f68 = 0xa1f68,
+ BNXT_ULP_CLASS_HID_a0244 = 0xa0244,
+ BNXT_ULP_CLASS_HID_a092a = 0xa092a,
+ BNXT_ULP_CLASS_HID_e1f76 = 0xe1f76,
+ BNXT_ULP_CLASS_HID_e06e4 = 0xe06e4,
+ BNXT_ULP_CLASS_HID_e0930 = 0xe0930,
+ BNXT_ULP_CLASS_HID_e1104 = 0xe1104,
+ BNXT_ULP_CLASS_HID_e1506 = 0xe1506,
+ BNXT_ULP_CLASS_HID_e1cf4 = 0xe1cf4,
+ BNXT_ULP_CLASS_HID_e07c0 = 0xe07c0,
+ BNXT_ULP_CLASS_HID_e0eb6 = 0xe0eb6,
+ BNXT_ULP_CLASS_HID_206ee = 0x206ee,
+ BNXT_ULP_CLASS_HID_20e5c = 0x20e5c,
+ BNXT_ULP_CLASS_HID_2110e = 0x2110e,
+ BNXT_ULP_CLASS_HID_218fc = 0x218fc,
+ BNXT_ULP_CLASS_HID_60462 = 0x60462,
+ BNXT_ULP_CLASS_HID_603d0 = 0x603d0,
+ BNXT_ULP_CLASS_HID_61682 = 0x61682,
+ BNXT_ULP_CLASS_HID_61e70 = 0x61e70,
+ BNXT_ULP_CLASS_HID_3167e = 0x3167e,
+ BNXT_ULP_CLASS_HID_31dec = 0x31dec,
+ BNXT_ULP_CLASS_HID_30030 = 0x30030,
+ BNXT_ULP_CLASS_HID_30fae = 0x30fae,
+ BNXT_ULP_CLASS_HID_70b14 = 0x70b14,
+ BNXT_ULP_CLASS_HID_71360 = 0x71360,
+ BNXT_ULP_CLASS_HID_705b4 = 0x705b4,
+ BNXT_ULP_CLASS_HID_70d22 = 0x70d22,
+ BNXT_ULP_CLASS_HID_29e26 = 0x29e26,
+ BNXT_ULP_CLASS_HID_28594 = 0x28594,
+ BNXT_ULP_CLASS_HID_288f8 = 0x288f8,
+ BNXT_ULP_CLASS_HID_29034 = 0x29034,
+ BNXT_ULP_CLASS_HID_693ba = 0x693ba,
+ BNXT_ULP_CLASS_HID_69b28 = 0x69b28,
+ BNXT_ULP_CLASS_HID_68e7c = 0x68e7c,
+ BNXT_ULP_CLASS_HID_69648 = 0x69648,
+ BNXT_ULP_CLASS_HID_38de8 = 0x38de8,
+ BNXT_ULP_CLASS_HID_39524 = 0x39524,
+ BNXT_ULP_CLASS_HID_39808 = 0x39808,
+ BNXT_ULP_CLASS_HID_387e6 = 0x387e6,
+ BNXT_ULP_CLASS_HID_7836c = 0x7836c,
+ BNXT_ULP_CLASS_HID_78ada = 0x78ada,
+ BNXT_ULP_CLASS_HID_79d8c = 0x79d8c,
+ BNXT_ULP_CLASS_HID_7857a = 0x7857a,
+ BNXT_ULP_CLASS_HID_81ad8 = 0x81ad8,
+ BNXT_ULP_CLASS_HID_8026e = 0x8026e,
+ BNXT_ULP_CLASS_HID_815b8 = 0x815b8,
+ BNXT_ULP_CLASS_HID_81cce = 0x81cce,
+ BNXT_ULP_CLASS_HID_810c8 = 0x810c8,
+ BNXT_ULP_CLASS_HID_8185e = 0x8185e,
+ BNXT_ULP_CLASS_HID_8030a = 0x8030a,
+ BNXT_ULP_CLASS_HID_80a98 = 0x80a98,
+ BNXT_ULP_CLASS_HID_c1844 = 0xc1844,
+ BNXT_ULP_CLASS_HID_c07ea = 0xc07ea,
+ BNXT_ULP_CLASS_HID_c0a86 = 0xc0a86,
+ BNXT_ULP_CLASS_HID_c124a = 0xc124a,
+ BNXT_ULP_CLASS_HID_c16b4 = 0xc16b4,
+ BNXT_ULP_CLASS_HID_c1dda = 0xc1dda,
+ BNXT_ULP_CLASS_HID_c00f6 = 0xc00f6,
+ BNXT_ULP_CLASS_HID_c0804 = 0xc0804,
+ BNXT_ULP_CLASS_HID_a199a = 0xa199a,
+ BNXT_ULP_CLASS_HID_a0128 = 0xa0128,
+ BNXT_ULP_CLASS_HID_a0bc4 = 0xa0bc4,
+ BNXT_ULP_CLASS_HID_a1388 = 0xa1388,
+ BNXT_ULP_CLASS_HID_a178a = 0xa178a,
+ BNXT_ULP_CLASS_HID_a1f18 = 0xa1f18,
+ BNXT_ULP_CLASS_HID_a0234 = 0xa0234,
+ BNXT_ULP_CLASS_HID_a095a = 0xa095a,
+ BNXT_ULP_CLASS_HID_e1f06 = 0xe1f06,
+ BNXT_ULP_CLASS_HID_e0694 = 0xe0694,
+ BNXT_ULP_CLASS_HID_e0940 = 0xe0940,
+ BNXT_ULP_CLASS_HID_e1174 = 0xe1174,
+ BNXT_ULP_CLASS_HID_e1576 = 0xe1576,
+ BNXT_ULP_CLASS_HID_e1c84 = 0xe1c84,
+ BNXT_ULP_CLASS_HID_e07b0 = 0xe07b0,
+ BNXT_ULP_CLASS_HID_e0ec6 = 0xe0ec6,
+ BNXT_ULP_CLASS_HID_2069e = 0x2069e,
+ BNXT_ULP_CLASS_HID_20e2c = 0x20e2c,
+ BNXT_ULP_CLASS_HID_2117e = 0x2117e,
+ BNXT_ULP_CLASS_HID_2188c = 0x2188c,
+ BNXT_ULP_CLASS_HID_60412 = 0x60412,
+ BNXT_ULP_CLASS_HID_603a0 = 0x603a0,
+ BNXT_ULP_CLASS_HID_616f2 = 0x616f2,
+ BNXT_ULP_CLASS_HID_61e00 = 0x61e00,
+ BNXT_ULP_CLASS_HID_3160e = 0x3160e,
+ BNXT_ULP_CLASS_HID_31d9c = 0x31d9c,
+ BNXT_ULP_CLASS_HID_30040 = 0x30040,
+ BNXT_ULP_CLASS_HID_30fde = 0x30fde,
+ BNXT_ULP_CLASS_HID_70b64 = 0x70b64,
+ BNXT_ULP_CLASS_HID_71310 = 0x71310,
+ BNXT_ULP_CLASS_HID_705c4 = 0x705c4,
+ BNXT_ULP_CLASS_HID_70d52 = 0x70d52,
+ BNXT_ULP_CLASS_HID_29e56 = 0x29e56,
+ BNXT_ULP_CLASS_HID_285e4 = 0x285e4,
+ BNXT_ULP_CLASS_HID_28888 = 0x28888,
+ BNXT_ULP_CLASS_HID_29044 = 0x29044,
+ BNXT_ULP_CLASS_HID_693ca = 0x693ca,
+ BNXT_ULP_CLASS_HID_69b58 = 0x69b58,
+ BNXT_ULP_CLASS_HID_68e0c = 0x68e0c,
+ BNXT_ULP_CLASS_HID_69638 = 0x69638,
+ BNXT_ULP_CLASS_HID_38d98 = 0x38d98,
+ BNXT_ULP_CLASS_HID_39554 = 0x39554,
+ BNXT_ULP_CLASS_HID_39878 = 0x39878,
+ BNXT_ULP_CLASS_HID_38796 = 0x38796,
+ BNXT_ULP_CLASS_HID_7831c = 0x7831c,
+ BNXT_ULP_CLASS_HID_78aaa = 0x78aaa,
+ BNXT_ULP_CLASS_HID_79dfc = 0x79dfc,
+ BNXT_ULP_CLASS_HID_7850a = 0x7850a,
+ BNXT_ULP_CLASS_HID_03b7 = 0x03b7,
+ BNXT_ULP_CLASS_HID_13f3 = 0x13f3,
+ BNXT_ULP_CLASS_HID_0255 = 0x0255,
+ BNXT_ULP_CLASS_HID_1675 = 0x1675,
+ BNXT_ULP_CLASS_HID_80f52 = 0x80f52,
+ BNXT_ULP_CLASS_HID_819f2 = 0x819f2,
+ BNXT_ULP_CLASS_HID_80542 = 0x80542,
+ BNXT_ULP_CLASS_HID_817e2 = 0x817e2,
+ BNXT_ULP_CLASS_HID_20a98 = 0x20a98,
+ BNXT_ULP_CLASS_HID_20538 = 0x20538,
+ BNXT_ULP_CLASS_HID_6081c = 0x6081c,
+ BNXT_ULP_CLASS_HID_61abc = 0x61abc,
+ BNXT_ULP_CLASS_HID_03a7 = 0x03a7,
+ BNXT_ULP_CLASS_HID_13e3 = 0x13e3,
+ BNXT_ULP_CLASS_HID_1047 = 0x1047,
+ BNXT_ULP_CLASS_HID_0721 = 0x0721,
+ BNXT_ULP_CLASS_HID_19b7 = 0x19b7,
+ BNXT_ULP_CLASS_HID_0911 = 0x0911,
+ BNXT_ULP_CLASS_HID_0df5 = 0x0df5,
+ BNXT_ULP_CLASS_HID_1d31 = 0x1d31,
+ BNXT_ULP_CLASS_HID_0245 = 0x0245,
+ BNXT_ULP_CLASS_HID_1665 = 0x1665,
+ BNXT_ULP_CLASS_HID_8055d = 0x8055d,
+ BNXT_ULP_CLASS_HID_80893 = 0x80893,
+ BNXT_ULP_CLASS_HID_407d9 = 0x407d9,
+ BNXT_ULP_CLASS_HID_40b1f = 0x40b1f,
+ BNXT_ULP_CLASS_HID_c1ad1 = 0xc1ad1,
+ BNXT_ULP_CLASS_HID_c0e17 = 0xc0e17,
+ BNXT_ULP_CLASS_HID_03d7 = 0x03d7,
+ BNXT_ULP_CLASS_HID_1393 = 0x1393,
+ BNXT_ULP_CLASS_HID_1037 = 0x1037,
+ BNXT_ULP_CLASS_HID_0751 = 0x0751,
+ BNXT_ULP_CLASS_HID_19c7 = 0x19c7,
+ BNXT_ULP_CLASS_HID_0961 = 0x0961,
+ BNXT_ULP_CLASS_HID_0d85 = 0x0d85,
+ BNXT_ULP_CLASS_HID_1d41 = 0x1d41,
+ BNXT_ULP_CLASS_HID_0235 = 0x0235,
+ BNXT_ULP_CLASS_HID_1615 = 0x1615,
+ BNXT_ULP_CLASS_HID_8052d = 0x8052d,
+ BNXT_ULP_CLASS_HID_808e3 = 0x808e3,
+ BNXT_ULP_CLASS_HID_407a9 = 0x407a9,
+ BNXT_ULP_CLASS_HID_40b6f = 0x40b6f,
+ BNXT_ULP_CLASS_HID_c1aa1 = 0xc1aa1,
+ BNXT_ULP_CLASS_HID_c0e67 = 0xc0e67,
+ BNXT_ULP_CLASS_HID_80f42 = 0x80f42,
+ BNXT_ULP_CLASS_HID_819e2 = 0x819e2,
+ BNXT_ULP_CLASS_HID_80552 = 0x80552,
+ BNXT_ULP_CLASS_HID_817f2 = 0x817f2,
+ BNXT_ULP_CLASS_HID_c0cce = 0xc0cce,
+ BNXT_ULP_CLASS_HID_c1f6e = 0xc1f6e,
+ BNXT_ULP_CLASS_HID_c1ade = 0xc1ade,
+ BNXT_ULP_CLASS_HID_c157e = 0xc157e,
+ BNXT_ULP_CLASS_HID_a0d8c = 0xa0d8c,
+ BNXT_ULP_CLASS_HID_a182c = 0xa182c,
+ BNXT_ULP_CLASS_HID_a1b9c = 0xa1b9c,
+ BNXT_ULP_CLASS_HID_a163c = 0xa163c,
+ BNXT_ULP_CLASS_HID_e0308 = 0xe0308,
+ BNXT_ULP_CLASS_HID_e1da8 = 0xe1da8,
+ BNXT_ULP_CLASS_HID_e1918 = 0xe1918,
+ BNXT_ULP_CLASS_HID_e0bda = 0xe0bda,
+ BNXT_ULP_CLASS_HID_20a88 = 0x20a88,
+ BNXT_ULP_CLASS_HID_20528 = 0x20528,
+ BNXT_ULP_CLASS_HID_6080c = 0x6080c,
+ BNXT_ULP_CLASS_HID_61aac = 0x61aac,
+ BNXT_ULP_CLASS_HID_31a18 = 0x31a18,
+ BNXT_ULP_CLASS_HID_314b8 = 0x314b8,
+ BNXT_ULP_CLASS_HID_71f9c = 0x71f9c,
+ BNXT_ULP_CLASS_HID_70a5e = 0x70a5e,
+ BNXT_ULP_CLASS_HID_282c0 = 0x282c0,
+ BNXT_ULP_CLASS_HID_29d60 = 0x29d60,
+ BNXT_ULP_CLASS_HID_68044 = 0x68044,
+ BNXT_ULP_CLASS_HID_692e4 = 0x692e4,
+ BNXT_ULP_CLASS_HID_39250 = 0x39250,
+ BNXT_ULP_CLASS_HID_38c12 = 0x38c12,
+ BNXT_ULP_CLASS_HID_797d4 = 0x797d4,
+ BNXT_ULP_CLASS_HID_78196 = 0x78196,
+ BNXT_ULP_CLASS_HID_80f32 = 0x80f32,
+ BNXT_ULP_CLASS_HID_81992 = 0x81992,
+ BNXT_ULP_CLASS_HID_80522 = 0x80522,
+ BNXT_ULP_CLASS_HID_81782 = 0x81782,
+ BNXT_ULP_CLASS_HID_c0cbe = 0xc0cbe,
+ BNXT_ULP_CLASS_HID_c1f1e = 0xc1f1e,
+ BNXT_ULP_CLASS_HID_c1aae = 0xc1aae,
+ BNXT_ULP_CLASS_HID_c150e = 0xc150e,
+ BNXT_ULP_CLASS_HID_a0dfc = 0xa0dfc,
+ BNXT_ULP_CLASS_HID_a185c = 0xa185c,
+ BNXT_ULP_CLASS_HID_a1bec = 0xa1bec,
+ BNXT_ULP_CLASS_HID_a164c = 0xa164c,
+ BNXT_ULP_CLASS_HID_e0378 = 0xe0378,
+ BNXT_ULP_CLASS_HID_e1dd8 = 0xe1dd8,
+ BNXT_ULP_CLASS_HID_e1968 = 0xe1968,
+ BNXT_ULP_CLASS_HID_e0baa = 0xe0baa,
+ BNXT_ULP_CLASS_HID_20af8 = 0x20af8,
+ BNXT_ULP_CLASS_HID_20558 = 0x20558,
+ BNXT_ULP_CLASS_HID_6087c = 0x6087c,
+ BNXT_ULP_CLASS_HID_61adc = 0x61adc,
+ BNXT_ULP_CLASS_HID_31a68 = 0x31a68,
+ BNXT_ULP_CLASS_HID_314c8 = 0x314c8,
+ BNXT_ULP_CLASS_HID_71fec = 0x71fec,
+ BNXT_ULP_CLASS_HID_70a2e = 0x70a2e,
+ BNXT_ULP_CLASS_HID_282b0 = 0x282b0,
+ BNXT_ULP_CLASS_HID_29d10 = 0x29d10,
+ BNXT_ULP_CLASS_HID_68034 = 0x68034,
+ BNXT_ULP_CLASS_HID_69294 = 0x69294,
+ BNXT_ULP_CLASS_HID_39220 = 0x39220,
+ BNXT_ULP_CLASS_HID_38c62 = 0x38c62,
+ BNXT_ULP_CLASS_HID_797a4 = 0x797a4,
+ BNXT_ULP_CLASS_HID_781e6 = 0x781e6,
+ BNXT_ULP_CLASS_HID_0f05 = 0x0f05,
+ BNXT_ULP_CLASS_HID_0f09 = 0x0f09,
+ BNXT_ULP_CLASS_HID_0f06 = 0x0f06,
+ BNXT_ULP_CLASS_HID_19a6 = 0x19a6,
+ BNXT_ULP_CLASS_HID_0f0a = 0x0f0a,
+ BNXT_ULP_CLASS_HID_19aa = 0x19aa,
+ BNXT_ULP_CLASS_HID_0f15 = 0x0f15,
+ BNXT_ULP_CLASS_HID_0f19 = 0x0f19,
+ BNXT_ULP_CLASS_HID_0f65 = 0x0f65,
+ BNXT_ULP_CLASS_HID_0f69 = 0x0f69,
+ BNXT_ULP_CLASS_HID_0f16 = 0x0f16,
+ BNXT_ULP_CLASS_HID_19b6 = 0x19b6,
+ BNXT_ULP_CLASS_HID_0f1a = 0x0f1a,
+ BNXT_ULP_CLASS_HID_19ba = 0x19ba,
+ BNXT_ULP_CLASS_HID_0f66 = 0x0f66,
+ BNXT_ULP_CLASS_HID_19c6 = 0x19c6,
+ BNXT_ULP_CLASS_HID_0f6a = 0x0f6a,
+ BNXT_ULP_CLASS_HID_19ca = 0x19ca
};
enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_0000 = 0x0000,
- BNXT_ULP_ACT_HID_0001 = 0x0001,
- BNXT_ULP_ACT_HID_0400 = 0x0400,
- BNXT_ULP_ACT_HID_01ab = 0x01ab,
+ BNXT_ULP_ACT_HID_0008 = 0x0008,
+ BNXT_ULP_ACT_HID_2000 = 0x2000,
+ BNXT_ULP_ACT_HID_1988 = 0x1988,
+ BNXT_ULP_ACT_HID_0080 = 0x0080,
+ BNXT_ULP_ACT_HID_3988 = 0x3988,
+ BNXT_ULP_ACT_HID_1a08 = 0x1a08,
BNXT_ULP_ACT_HID_0010 = 0x0010,
- BNXT_ULP_ACT_HID_05ab = 0x05ab,
- BNXT_ULP_ACT_HID_01bb = 0x01bb,
- BNXT_ULP_ACT_HID_0002 = 0x0002,
- BNXT_ULP_ACT_HID_0003 = 0x0003,
- BNXT_ULP_ACT_HID_0402 = 0x0402,
- BNXT_ULP_ACT_HID_01ad = 0x01ad,
- BNXT_ULP_ACT_HID_0012 = 0x0012,
- BNXT_ULP_ACT_HID_05ad = 0x05ad,
- BNXT_ULP_ACT_HID_01bd = 0x01bd,
- BNXT_ULP_ACT_HID_0613 = 0x0613,
- BNXT_ULP_ACT_HID_02a9 = 0x02a9,
- BNXT_ULP_ACT_HID_0054 = 0x0054,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
+ BNXT_ULP_ACT_HID_0050 = 0x0050,
+ BNXT_ULP_ACT_HID_0018 = 0x0018,
+ BNXT_ULP_ACT_HID_2010 = 0x2010,
+ BNXT_ULP_ACT_HID_1998 = 0x1998,
+ BNXT_ULP_ACT_HID_0090 = 0x0090,
+ BNXT_ULP_ACT_HID_3998 = 0x3998,
+ BNXT_ULP_ACT_HID_1a18 = 0x1a18,
+ BNXT_ULP_ACT_HID_32ea = 0x32ea,
+ BNXT_ULP_ACT_HID_32f2 = 0x32f2,
+ BNXT_ULP_ACT_HID_52ea = 0x52ea,
+ BNXT_ULP_ACT_HID_4c72 = 0x4c72,
+ BNXT_ULP_ACT_HID_336a = 0x336a,
+ BNXT_ULP_ACT_HID_6c72 = 0x6c72,
+ BNXT_ULP_ACT_HID_4cf2 = 0x4cf2,
+ BNXT_ULP_ACT_HID_32fa = 0x32fa,
+ BNXT_ULP_ACT_HID_3302 = 0x3302,
+ BNXT_ULP_ACT_HID_52fa = 0x52fa,
+ BNXT_ULP_ACT_HID_4c82 = 0x4c82,
+ BNXT_ULP_ACT_HID_337a = 0x337a,
+ BNXT_ULP_ACT_HID_6c82 = 0x6c82,
+ BNXT_ULP_ACT_HID_4d02 = 0x4d02,
+ BNXT_ULP_ACT_HID_0808 = 0x0808,
+ BNXT_ULP_ACT_HID_1008 = 0x1008,
+ BNXT_ULP_ACT_HID_1808 = 0x1808,
+ BNXT_ULP_ACT_HID_0818 = 0x0818,
+ BNXT_ULP_ACT_HID_1018 = 0x1018,
+ BNXT_ULP_ACT_HID_1818 = 0x1818,
+ BNXT_ULP_ACT_HID_0880 = 0x0880,
+ BNXT_ULP_ACT_HID_1080 = 0x1080,
+ BNXT_ULP_ACT_HID_1880 = 0x1880,
+ BNXT_ULP_ACT_HID_0890 = 0x0890,
+ BNXT_ULP_ACT_HID_1090 = 0x1090,
+ BNXT_ULP_ACT_HID_1890 = 0x1890,
+ BNXT_ULP_ACT_HID_3af2 = 0x3af2,
+ BNXT_ULP_ACT_HID_42f2 = 0x42f2,
+ BNXT_ULP_ACT_HID_4af2 = 0x4af2,
+ BNXT_ULP_ACT_HID_3b02 = 0x3b02,
+ BNXT_ULP_ACT_HID_4302 = 0x4302,
+ BNXT_ULP_ACT_HID_4b02 = 0x4b02,
+ BNXT_ULP_ACT_HID_3b6a = 0x3b6a,
+ BNXT_ULP_ACT_HID_436a = 0x436a,
+ BNXT_ULP_ACT_HID_4b6a = 0x4b6a,
+ BNXT_ULP_ACT_HID_3b7a = 0x3b7a,
+ BNXT_ULP_ACT_HID_437a = 0x437a,
+ BNXT_ULP_ACT_HID_4b7a = 0x4b7a,
+ BNXT_ULP_ACT_HID_640d = 0x640d,
+ BNXT_ULP_ACT_HID_641d = 0x641d,
+ BNXT_ULP_ACT_HID_071a = 0x071a,
+ BNXT_ULP_ACT_HID_0800 = 0x0800,
+ BNXT_ULP_ACT_HID_1000 = 0x1000,
+ BNXT_ULP_ACT_HID_1800 = 0x1800,
+ BNXT_ULP_ACT_HID_0810 = 0x0810,
+ BNXT_ULP_ACT_HID_1010 = 0x1010,
+ BNXT_ULP_ACT_HID_1810 = 0x1810,
+ BNXT_ULP_ACT_HID_1110 = 0x1110,
+ BNXT_ULP_ACT_HID_4420 = 0x4420,
+ BNXT_ULP_ACT_HID_2220 = 0x2220,
+ BNXT_ULP_ACT_HID_0c84 = 0x0c84,
+ BNXT_ULP_ACT_HID_3f94 = 0x3f94,
+ BNXT_ULP_ACT_HID_3330 = 0x3330,
+ BNXT_ULP_ACT_HID_50a4 = 0x50a4,
+ BNXT_ULP_ACT_HID_1910 = 0x1910,
+ BNXT_ULP_ACT_HID_4c20 = 0x4c20,
+ BNXT_ULP_ACT_HID_2a20 = 0x2a20,
+ BNXT_ULP_ACT_HID_1484 = 0x1484,
+ BNXT_ULP_ACT_HID_4794 = 0x4794,
+ BNXT_ULP_ACT_HID_3b30 = 0x3b30,
+ BNXT_ULP_ACT_HID_58a4 = 0x58a4,
+ BNXT_ULP_ACT_HID_2110 = 0x2110,
+ BNXT_ULP_ACT_HID_5420 = 0x5420,
+ BNXT_ULP_ACT_HID_3220 = 0x3220,
+ BNXT_ULP_ACT_HID_1c84 = 0x1c84,
+ BNXT_ULP_ACT_HID_4f94 = 0x4f94,
+ BNXT_ULP_ACT_HID_4330 = 0x4330,
+ BNXT_ULP_ACT_HID_60a4 = 0x60a4,
+ BNXT_ULP_ACT_HID_2910 = 0x2910,
+ BNXT_ULP_ACT_HID_5c20 = 0x5c20,
+ BNXT_ULP_ACT_HID_3a20 = 0x3a20,
+ BNXT_ULP_ACT_HID_2484 = 0x2484,
+ BNXT_ULP_ACT_HID_5794 = 0x5794,
+ BNXT_ULP_ACT_HID_4b30 = 0x4b30,
+ BNXT_ULP_ACT_HID_68a4 = 0x68a4,
+ BNXT_ULP_ACT_HID_1120 = 0x1120,
+ BNXT_ULP_ACT_HID_4430 = 0x4430,
+ BNXT_ULP_ACT_HID_2230 = 0x2230,
+ BNXT_ULP_ACT_HID_0c94 = 0x0c94,
+ BNXT_ULP_ACT_HID_3fa4 = 0x3fa4,
+ BNXT_ULP_ACT_HID_3340 = 0x3340,
+ BNXT_ULP_ACT_HID_50b4 = 0x50b4,
+ BNXT_ULP_ACT_HID_1920 = 0x1920,
+ BNXT_ULP_ACT_HID_4c30 = 0x4c30,
+ BNXT_ULP_ACT_HID_2a30 = 0x2a30,
+ BNXT_ULP_ACT_HID_1494 = 0x1494,
+ BNXT_ULP_ACT_HID_47a4 = 0x47a4,
+ BNXT_ULP_ACT_HID_3b40 = 0x3b40,
+ BNXT_ULP_ACT_HID_58b4 = 0x58b4,
+ BNXT_ULP_ACT_HID_2120 = 0x2120,
+ BNXT_ULP_ACT_HID_5430 = 0x5430,
+ BNXT_ULP_ACT_HID_3230 = 0x3230,
+ BNXT_ULP_ACT_HID_1c94 = 0x1c94,
+ BNXT_ULP_ACT_HID_4fa4 = 0x4fa4,
+ BNXT_ULP_ACT_HID_4340 = 0x4340,
+ BNXT_ULP_ACT_HID_60b4 = 0x60b4,
+ BNXT_ULP_ACT_HID_2920 = 0x2920,
+ BNXT_ULP_ACT_HID_5c30 = 0x5c30,
+ BNXT_ULP_ACT_HID_3a30 = 0x3a30,
+ BNXT_ULP_ACT_HID_2494 = 0x2494,
+ BNXT_ULP_ACT_HID_57a4 = 0x57a4,
+ BNXT_ULP_ACT_HID_4b40 = 0x4b40,
+ BNXT_ULP_ACT_HID_68b4 = 0x68b4,
+ BNXT_ULP_ACT_HID_2a98 = 0x2a98,
+ BNXT_ULP_ACT_HID_5da8 = 0x5da8,
+ BNXT_ULP_ACT_HID_3ba8 = 0x3ba8,
+ BNXT_ULP_ACT_HID_260c = 0x260c,
+ BNXT_ULP_ACT_HID_591c = 0x591c,
+ BNXT_ULP_ACT_HID_6a2c = 0x6a2c,
+ BNXT_ULP_ACT_HID_2aa8 = 0x2aa8,
+ BNXT_ULP_ACT_HID_5db8 = 0x5db8,
+ BNXT_ULP_ACT_HID_3bb8 = 0x3bb8,
+ BNXT_ULP_ACT_HID_261c = 0x261c,
+ BNXT_ULP_ACT_HID_592c = 0x592c,
+ BNXT_ULP_ACT_HID_6a3c = 0x6a3c,
+ BNXT_ULP_ACT_HID_3298 = 0x3298,
+ BNXT_ULP_ACT_HID_65a8 = 0x65a8,
+ BNXT_ULP_ACT_HID_43a8 = 0x43a8,
+ BNXT_ULP_ACT_HID_2e0c = 0x2e0c,
+ BNXT_ULP_ACT_HID_611c = 0x611c,
+ BNXT_ULP_ACT_HID_722c = 0x722c,
+ BNXT_ULP_ACT_HID_32a8 = 0x32a8,
+ BNXT_ULP_ACT_HID_65b8 = 0x65b8,
+ BNXT_ULP_ACT_HID_43b8 = 0x43b8,
+ BNXT_ULP_ACT_HID_2e1c = 0x2e1c,
+ BNXT_ULP_ACT_HID_612c = 0x612c,
+ BNXT_ULP_ACT_HID_723c = 0x723c,
+ BNXT_ULP_ACT_HID_3a98 = 0x3a98,
+ BNXT_ULP_ACT_HID_6da8 = 0x6da8,
+ BNXT_ULP_ACT_HID_4ba8 = 0x4ba8,
+ BNXT_ULP_ACT_HID_360c = 0x360c,
+ BNXT_ULP_ACT_HID_691c = 0x691c,
+ BNXT_ULP_ACT_HID_7a2c = 0x7a2c,
+ BNXT_ULP_ACT_HID_3aa8 = 0x3aa8,
+ BNXT_ULP_ACT_HID_6db8 = 0x6db8,
+ BNXT_ULP_ACT_HID_4bb8 = 0x4bb8,
+ BNXT_ULP_ACT_HID_361c = 0x361c,
+ BNXT_ULP_ACT_HID_692c = 0x692c,
+ BNXT_ULP_ACT_HID_7a3c = 0x7a3c,
+ BNXT_ULP_ACT_HID_4298 = 0x4298,
+ BNXT_ULP_ACT_HID_75a8 = 0x75a8,
+ BNXT_ULP_ACT_HID_53a8 = 0x53a8,
+ BNXT_ULP_ACT_HID_3e0c = 0x3e0c,
+ BNXT_ULP_ACT_HID_711c = 0x711c,
+ BNXT_ULP_ACT_HID_0670 = 0x0670,
+ BNXT_ULP_ACT_HID_42a8 = 0x42a8,
+ BNXT_ULP_ACT_HID_75b8 = 0x75b8,
+ BNXT_ULP_ACT_HID_53b8 = 0x53b8,
+ BNXT_ULP_ACT_HID_3e1c = 0x3e1c,
+ BNXT_ULP_ACT_HID_712c = 0x712c,
+ BNXT_ULP_ACT_HID_0680 = 0x0680,
+ BNXT_ULP_ACT_HID_3aea = 0x3aea,
+ BNXT_ULP_ACT_HID_42ea = 0x42ea,
+ BNXT_ULP_ACT_HID_4aea = 0x4aea,
+ BNXT_ULP_ACT_HID_3afa = 0x3afa,
+ BNXT_ULP_ACT_HID_42fa = 0x42fa,
+ BNXT_ULP_ACT_HID_4afa = 0x4afa,
+ BNXT_ULP_ACT_HID_43fa = 0x43fa,
+ BNXT_ULP_ACT_HID_770a = 0x770a,
+ BNXT_ULP_ACT_HID_550a = 0x550a,
+ BNXT_ULP_ACT_HID_3f6e = 0x3f6e,
+ BNXT_ULP_ACT_HID_727e = 0x727e,
+ BNXT_ULP_ACT_HID_661a = 0x661a,
+ BNXT_ULP_ACT_HID_07d2 = 0x07d2,
+ BNXT_ULP_ACT_HID_4bfa = 0x4bfa,
+ BNXT_ULP_ACT_HID_034e = 0x034e,
+ BNXT_ULP_ACT_HID_5d0a = 0x5d0a,
+ BNXT_ULP_ACT_HID_476e = 0x476e,
+ BNXT_ULP_ACT_HID_7a7e = 0x7a7e,
+ BNXT_ULP_ACT_HID_6e1a = 0x6e1a,
+ BNXT_ULP_ACT_HID_0fd2 = 0x0fd2,
+ BNXT_ULP_ACT_HID_53fa = 0x53fa,
+ BNXT_ULP_ACT_HID_0b4e = 0x0b4e,
+ BNXT_ULP_ACT_HID_650a = 0x650a,
+ BNXT_ULP_ACT_HID_4f6e = 0x4f6e,
+ BNXT_ULP_ACT_HID_06c2 = 0x06c2,
+ BNXT_ULP_ACT_HID_761a = 0x761a,
+ BNXT_ULP_ACT_HID_17d2 = 0x17d2,
+ BNXT_ULP_ACT_HID_5bfa = 0x5bfa,
+ BNXT_ULP_ACT_HID_134e = 0x134e,
+ BNXT_ULP_ACT_HID_6d0a = 0x6d0a,
+ BNXT_ULP_ACT_HID_576e = 0x576e,
+ BNXT_ULP_ACT_HID_0ec2 = 0x0ec2,
+ BNXT_ULP_ACT_HID_025e = 0x025e,
+ BNXT_ULP_ACT_HID_1fd2 = 0x1fd2,
+ BNXT_ULP_ACT_HID_440a = 0x440a,
+ BNXT_ULP_ACT_HID_771a = 0x771a,
+ BNXT_ULP_ACT_HID_551a = 0x551a,
+ BNXT_ULP_ACT_HID_3f7e = 0x3f7e,
+ BNXT_ULP_ACT_HID_728e = 0x728e,
+ BNXT_ULP_ACT_HID_662a = 0x662a,
+ BNXT_ULP_ACT_HID_07e2 = 0x07e2,
+ BNXT_ULP_ACT_HID_4c0a = 0x4c0a,
+ BNXT_ULP_ACT_HID_035e = 0x035e,
+ BNXT_ULP_ACT_HID_5d1a = 0x5d1a,
+ BNXT_ULP_ACT_HID_477e = 0x477e,
+ BNXT_ULP_ACT_HID_7a8e = 0x7a8e,
+ BNXT_ULP_ACT_HID_6e2a = 0x6e2a,
+ BNXT_ULP_ACT_HID_0fe2 = 0x0fe2,
+ BNXT_ULP_ACT_HID_540a = 0x540a,
+ BNXT_ULP_ACT_HID_0b5e = 0x0b5e,
+ BNXT_ULP_ACT_HID_651a = 0x651a,
+ BNXT_ULP_ACT_HID_4f7e = 0x4f7e,
+ BNXT_ULP_ACT_HID_06d2 = 0x06d2,
+ BNXT_ULP_ACT_HID_762a = 0x762a,
+ BNXT_ULP_ACT_HID_17e2 = 0x17e2,
+ BNXT_ULP_ACT_HID_5c0a = 0x5c0a,
+ BNXT_ULP_ACT_HID_135e = 0x135e,
+ BNXT_ULP_ACT_HID_6d1a = 0x6d1a,
+ BNXT_ULP_ACT_HID_577e = 0x577e,
+ BNXT_ULP_ACT_HID_0ed2 = 0x0ed2,
+ BNXT_ULP_ACT_HID_026e = 0x026e,
+ BNXT_ULP_ACT_HID_1fe2 = 0x1fe2,
+ BNXT_ULP_ACT_HID_5d82 = 0x5d82,
+ BNXT_ULP_ACT_HID_14d6 = 0x14d6,
+ BNXT_ULP_ACT_HID_6e92 = 0x6e92,
+ BNXT_ULP_ACT_HID_58f6 = 0x58f6,
+ BNXT_ULP_ACT_HID_104a = 0x104a,
+ BNXT_ULP_ACT_HID_215a = 0x215a,
+ BNXT_ULP_ACT_HID_5d92 = 0x5d92,
+ BNXT_ULP_ACT_HID_14e6 = 0x14e6,
+ BNXT_ULP_ACT_HID_6ea2 = 0x6ea2,
+ BNXT_ULP_ACT_HID_5906 = 0x5906,
+ BNXT_ULP_ACT_HID_105a = 0x105a,
+ BNXT_ULP_ACT_HID_216a = 0x216a,
+ BNXT_ULP_ACT_HID_6582 = 0x6582,
+ BNXT_ULP_ACT_HID_1cd6 = 0x1cd6,
+ BNXT_ULP_ACT_HID_7692 = 0x7692,
+ BNXT_ULP_ACT_HID_60f6 = 0x60f6,
+ BNXT_ULP_ACT_HID_184a = 0x184a,
+ BNXT_ULP_ACT_HID_295a = 0x295a,
+ BNXT_ULP_ACT_HID_6592 = 0x6592,
+ BNXT_ULP_ACT_HID_1ce6 = 0x1ce6,
+ BNXT_ULP_ACT_HID_76a2 = 0x76a2,
+ BNXT_ULP_ACT_HID_6106 = 0x6106,
+ BNXT_ULP_ACT_HID_185a = 0x185a,
+ BNXT_ULP_ACT_HID_296a = 0x296a,
+ BNXT_ULP_ACT_HID_6d82 = 0x6d82,
+ BNXT_ULP_ACT_HID_24d6 = 0x24d6,
+ BNXT_ULP_ACT_HID_02d6 = 0x02d6,
+ BNXT_ULP_ACT_HID_68f6 = 0x68f6,
+ BNXT_ULP_ACT_HID_204a = 0x204a,
+ BNXT_ULP_ACT_HID_315a = 0x315a,
+ BNXT_ULP_ACT_HID_6d92 = 0x6d92,
+ BNXT_ULP_ACT_HID_24e6 = 0x24e6,
+ BNXT_ULP_ACT_HID_02e6 = 0x02e6,
+ BNXT_ULP_ACT_HID_6906 = 0x6906,
+ BNXT_ULP_ACT_HID_205a = 0x205a,
+ BNXT_ULP_ACT_HID_316a = 0x316a,
+ BNXT_ULP_ACT_HID_7582 = 0x7582,
+ BNXT_ULP_ACT_HID_2cd6 = 0x2cd6,
+ BNXT_ULP_ACT_HID_0ad6 = 0x0ad6,
+ BNXT_ULP_ACT_HID_70f6 = 0x70f6,
+ BNXT_ULP_ACT_HID_284a = 0x284a,
+ BNXT_ULP_ACT_HID_395a = 0x395a,
+ BNXT_ULP_ACT_HID_7592 = 0x7592,
+ BNXT_ULP_ACT_HID_2ce6 = 0x2ce6,
+ BNXT_ULP_ACT_HID_0ae6 = 0x0ae6,
+ BNXT_ULP_ACT_HID_7106 = 0x7106,
+ BNXT_ULP_ACT_HID_285a = 0x285a,
+ BNXT_ULP_ACT_HID_396a = 0x396a,
+ BNXT_ULP_ACT_HID_0020 = 0x0020,
+ BNXT_ULP_ACT_HID_0030 = 0x0030,
+ BNXT_ULP_ACT_HID_65d4 = 0x65d4,
+ BNXT_ULP_ACT_HID_65e4 = 0x65e4,
+ BNXT_ULP_ACT_HID_330a = 0x330a,
+ BNXT_ULP_ACT_HID_331a = 0x331a,
+ BNXT_ULP_ACT_HID_1cfe = 0x1cfe,
+ BNXT_ULP_ACT_HID_1d0e = 0x1d0e,
+ BNXT_ULP_ACT_HID_1474 = 0x1474,
+ BNXT_ULP_ACT_HID_4838 = 0x4838,
+ BNXT_ULP_ACT_HID_6458 = 0x6458,
+ BNXT_ULP_ACT_HID_1c68 = 0x1c68,
+ BNXT_ULP_ACT_HID_6c34 = 0x6c34,
+ BNXT_ULP_ACT_HID_5d08 = 0x5d08,
+ BNXT_ULP_ACT_HID_5d10 = 0x5d10,
+ BNXT_ULP_ACT_HID_5d20 = 0x5d20,
+ BNXT_ULP_ACT_HID_2e18 = 0x2e18,
+ BNXT_ULP_ACT_HID_29d4 = 0x29d4,
+ BNXT_ULP_ACT_HID_7690 = 0x7690,
+ BNXT_ULP_ACT_HID_47a0 = 0x47a0,
+ BNXT_ULP_ACT_HID_435c = 0x435c,
+ BNXT_ULP_ACT_HID_5d18 = 0x5d18,
+ BNXT_ULP_ACT_HID_2e28 = 0x2e28,
+ BNXT_ULP_ACT_HID_29e4 = 0x29e4,
+ BNXT_ULP_ACT_HID_76a0 = 0x76a0,
+ BNXT_ULP_ACT_HID_47b0 = 0x47b0,
+ BNXT_ULP_ACT_HID_436c = 0x436c,
+ BNXT_ULP_ACT_HID_1436 = 0x1436,
+ BNXT_ULP_ACT_HID_143e = 0x143e,
+ BNXT_ULP_ACT_HID_144e = 0x144e,
+ BNXT_ULP_ACT_HID_6102 = 0x6102,
+ BNXT_ULP_ACT_HID_5cbe = 0x5cbe,
+ BNXT_ULP_ACT_HID_2dbe = 0x2dbe,
+ BNXT_ULP_ACT_HID_7a8a = 0x7a8a,
+ BNXT_ULP_ACT_HID_7646 = 0x7646,
+ BNXT_ULP_ACT_HID_1446 = 0x1446,
+ BNXT_ULP_ACT_HID_6112 = 0x6112,
+ BNXT_ULP_ACT_HID_5cce = 0x5cce,
+ BNXT_ULP_ACT_HID_2dce = 0x2dce,
+ BNXT_ULP_ACT_HID_7a9a = 0x7a9a,
+ BNXT_ULP_ACT_HID_7656 = 0x7656,
+ BNXT_ULP_ACT_HID_6508 = 0x6508,
+ BNXT_ULP_ACT_HID_6d08 = 0x6d08,
+ BNXT_ULP_ACT_HID_7508 = 0x7508,
+ BNXT_ULP_ACT_HID_6518 = 0x6518,
+ BNXT_ULP_ACT_HID_6d18 = 0x6d18,
+ BNXT_ULP_ACT_HID_7518 = 0x7518,
+ BNXT_ULP_ACT_HID_6e18 = 0x6e18,
+ BNXT_ULP_ACT_HID_256c = 0x256c,
+ BNXT_ULP_ACT_HID_036c = 0x036c,
+ BNXT_ULP_ACT_HID_698c = 0x698c,
+ BNXT_ULP_ACT_HID_20e0 = 0x20e0,
+ BNXT_ULP_ACT_HID_31f0 = 0x31f0,
+ BNXT_ULP_ACT_HID_7618 = 0x7618,
+ BNXT_ULP_ACT_HID_2d6c = 0x2d6c,
+ BNXT_ULP_ACT_HID_0b6c = 0x0b6c,
+ BNXT_ULP_ACT_HID_718c = 0x718c,
+ BNXT_ULP_ACT_HID_28e0 = 0x28e0,
+ BNXT_ULP_ACT_HID_39f0 = 0x39f0,
+ BNXT_ULP_ACT_HID_025c = 0x025c,
+ BNXT_ULP_ACT_HID_356c = 0x356c,
+ BNXT_ULP_ACT_HID_136c = 0x136c,
+ BNXT_ULP_ACT_HID_798c = 0x798c,
+ BNXT_ULP_ACT_HID_30e0 = 0x30e0,
+ BNXT_ULP_ACT_HID_41f0 = 0x41f0,
+ BNXT_ULP_ACT_HID_0a5c = 0x0a5c,
+ BNXT_ULP_ACT_HID_3d6c = 0x3d6c,
+ BNXT_ULP_ACT_HID_1b6c = 0x1b6c,
+ BNXT_ULP_ACT_HID_05d0 = 0x05d0,
+ BNXT_ULP_ACT_HID_38e0 = 0x38e0,
+ BNXT_ULP_ACT_HID_49f0 = 0x49f0,
+ BNXT_ULP_ACT_HID_6e28 = 0x6e28,
+ BNXT_ULP_ACT_HID_257c = 0x257c,
+ BNXT_ULP_ACT_HID_037c = 0x037c,
+ BNXT_ULP_ACT_HID_699c = 0x699c,
+ BNXT_ULP_ACT_HID_20f0 = 0x20f0,
+ BNXT_ULP_ACT_HID_3200 = 0x3200,
+ BNXT_ULP_ACT_HID_7628 = 0x7628,
+ BNXT_ULP_ACT_HID_2d7c = 0x2d7c,
+ BNXT_ULP_ACT_HID_0b7c = 0x0b7c,
+ BNXT_ULP_ACT_HID_719c = 0x719c,
+ BNXT_ULP_ACT_HID_28f0 = 0x28f0,
+ BNXT_ULP_ACT_HID_3a00 = 0x3a00,
+ BNXT_ULP_ACT_HID_026c = 0x026c,
+ BNXT_ULP_ACT_HID_357c = 0x357c,
+ BNXT_ULP_ACT_HID_137c = 0x137c,
+ BNXT_ULP_ACT_HID_799c = 0x799c,
+ BNXT_ULP_ACT_HID_30f0 = 0x30f0,
+ BNXT_ULP_ACT_HID_4200 = 0x4200,
+ BNXT_ULP_ACT_HID_0a6c = 0x0a6c,
+ BNXT_ULP_ACT_HID_3d7c = 0x3d7c,
+ BNXT_ULP_ACT_HID_1b7c = 0x1b7c,
+ BNXT_ULP_ACT_HID_05e0 = 0x05e0,
+ BNXT_ULP_ACT_HID_38f0 = 0x38f0,
+ BNXT_ULP_ACT_HID_4a00 = 0x4a00,
+ BNXT_ULP_ACT_HID_0be4 = 0x0be4,
+ BNXT_ULP_ACT_HID_3ef4 = 0x3ef4,
+ BNXT_ULP_ACT_HID_1cf4 = 0x1cf4,
+ BNXT_ULP_ACT_HID_0758 = 0x0758,
+ BNXT_ULP_ACT_HID_3a68 = 0x3a68,
+ BNXT_ULP_ACT_HID_4b78 = 0x4b78,
+ BNXT_ULP_ACT_HID_0bf4 = 0x0bf4,
+ BNXT_ULP_ACT_HID_3f04 = 0x3f04,
+ BNXT_ULP_ACT_HID_1d04 = 0x1d04,
+ BNXT_ULP_ACT_HID_0768 = 0x0768,
+ BNXT_ULP_ACT_HID_3a78 = 0x3a78,
+ BNXT_ULP_ACT_HID_4b88 = 0x4b88,
+ BNXT_ULP_ACT_HID_46f4 = 0x46f4,
+ BNXT_ULP_ACT_HID_24f4 = 0x24f4,
+ BNXT_ULP_ACT_HID_0f58 = 0x0f58,
+ BNXT_ULP_ACT_HID_13e4 = 0x13e4,
+ BNXT_ULP_ACT_HID_4268 = 0x4268,
+ BNXT_ULP_ACT_HID_5378 = 0x5378,
+ BNXT_ULP_ACT_HID_13f4 = 0x13f4,
+ BNXT_ULP_ACT_HID_4704 = 0x4704,
+ BNXT_ULP_ACT_HID_2504 = 0x2504,
+ BNXT_ULP_ACT_HID_0f68 = 0x0f68,
+ BNXT_ULP_ACT_HID_4278 = 0x4278,
+ BNXT_ULP_ACT_HID_5388 = 0x5388,
+ BNXT_ULP_ACT_HID_1be4 = 0x1be4,
+ BNXT_ULP_ACT_HID_4ef4 = 0x4ef4,
+ BNXT_ULP_ACT_HID_2cf4 = 0x2cf4,
+ BNXT_ULP_ACT_HID_1758 = 0x1758,
+ BNXT_ULP_ACT_HID_4a68 = 0x4a68,
+ BNXT_ULP_ACT_HID_5b78 = 0x5b78,
+ BNXT_ULP_ACT_HID_1bf4 = 0x1bf4,
+ BNXT_ULP_ACT_HID_4f04 = 0x4f04,
+ BNXT_ULP_ACT_HID_2d04 = 0x2d04,
+ BNXT_ULP_ACT_HID_1768 = 0x1768,
+ BNXT_ULP_ACT_HID_4a78 = 0x4a78,
+ BNXT_ULP_ACT_HID_5b88 = 0x5b88,
+ BNXT_ULP_ACT_HID_23e4 = 0x23e4,
+ BNXT_ULP_ACT_HID_56f4 = 0x56f4,
+ BNXT_ULP_ACT_HID_34f4 = 0x34f4,
+ BNXT_ULP_ACT_HID_1f58 = 0x1f58,
+ BNXT_ULP_ACT_HID_5268 = 0x5268,
+ BNXT_ULP_ACT_HID_6378 = 0x6378,
+ BNXT_ULP_ACT_HID_23f4 = 0x23f4,
+ BNXT_ULP_ACT_HID_5704 = 0x5704,
+ BNXT_ULP_ACT_HID_3504 = 0x3504,
+ BNXT_ULP_ACT_HID_1f68 = 0x1f68,
+ BNXT_ULP_ACT_HID_5278 = 0x5278,
+ BNXT_ULP_ACT_HID_6388 = 0x6388,
+ BNXT_ULP_ACT_HID_1c36 = 0x1c36,
+ BNXT_ULP_ACT_HID_2436 = 0x2436,
+ BNXT_ULP_ACT_HID_2c36 = 0x2c36,
+ BNXT_ULP_ACT_HID_1c46 = 0x1c46,
+ BNXT_ULP_ACT_HID_2446 = 0x2446,
+ BNXT_ULP_ACT_HID_2c46 = 0x2c46,
+ BNXT_ULP_ACT_HID_2546 = 0x2546,
+ BNXT_ULP_ACT_HID_5856 = 0x5856,
+ BNXT_ULP_ACT_HID_3656 = 0x3656,
+ BNXT_ULP_ACT_HID_20ba = 0x20ba,
+ BNXT_ULP_ACT_HID_53ca = 0x53ca,
+ BNXT_ULP_ACT_HID_64da = 0x64da,
+ BNXT_ULP_ACT_HID_2d46 = 0x2d46,
+ BNXT_ULP_ACT_HID_6056 = 0x6056,
+ BNXT_ULP_ACT_HID_3e56 = 0x3e56,
+ BNXT_ULP_ACT_HID_28ba = 0x28ba,
+ BNXT_ULP_ACT_HID_5bca = 0x5bca,
+ BNXT_ULP_ACT_HID_6cda = 0x6cda,
+ BNXT_ULP_ACT_HID_3546 = 0x3546,
+ BNXT_ULP_ACT_HID_6856 = 0x6856,
+ BNXT_ULP_ACT_HID_4656 = 0x4656,
+ BNXT_ULP_ACT_HID_30ba = 0x30ba,
+ BNXT_ULP_ACT_HID_63ca = 0x63ca,
+ BNXT_ULP_ACT_HID_74da = 0x74da,
+ BNXT_ULP_ACT_HID_3d46 = 0x3d46,
+ BNXT_ULP_ACT_HID_7056 = 0x7056,
+ BNXT_ULP_ACT_HID_4e56 = 0x4e56,
+ BNXT_ULP_ACT_HID_38ba = 0x38ba,
+ BNXT_ULP_ACT_HID_6bca = 0x6bca,
+ BNXT_ULP_ACT_HID_011e = 0x011e,
+ BNXT_ULP_ACT_HID_2556 = 0x2556,
+ BNXT_ULP_ACT_HID_5866 = 0x5866,
+ BNXT_ULP_ACT_HID_3666 = 0x3666,
+ BNXT_ULP_ACT_HID_20ca = 0x20ca,
+ BNXT_ULP_ACT_HID_53da = 0x53da,
+ BNXT_ULP_ACT_HID_64ea = 0x64ea,
+ BNXT_ULP_ACT_HID_2d56 = 0x2d56,
+ BNXT_ULP_ACT_HID_6066 = 0x6066,
+ BNXT_ULP_ACT_HID_3e66 = 0x3e66,
+ BNXT_ULP_ACT_HID_28ca = 0x28ca,
+ BNXT_ULP_ACT_HID_5bda = 0x5bda,
+ BNXT_ULP_ACT_HID_6cea = 0x6cea,
+ BNXT_ULP_ACT_HID_3556 = 0x3556,
+ BNXT_ULP_ACT_HID_6866 = 0x6866,
+ BNXT_ULP_ACT_HID_4666 = 0x4666,
+ BNXT_ULP_ACT_HID_30ca = 0x30ca,
+ BNXT_ULP_ACT_HID_63da = 0x63da,
+ BNXT_ULP_ACT_HID_74ea = 0x74ea,
+ BNXT_ULP_ACT_HID_3d56 = 0x3d56,
+ BNXT_ULP_ACT_HID_7066 = 0x7066,
+ BNXT_ULP_ACT_HID_4e66 = 0x4e66,
+ BNXT_ULP_ACT_HID_38ca = 0x38ca,
+ BNXT_ULP_ACT_HID_6bda = 0x6bda,
+ BNXT_ULP_ACT_HID_012e = 0x012e,
+ BNXT_ULP_ACT_HID_3ece = 0x3ece,
+ BNXT_ULP_ACT_HID_71de = 0x71de,
+ BNXT_ULP_ACT_HID_4fde = 0x4fde,
+ BNXT_ULP_ACT_HID_3a42 = 0x3a42,
+ BNXT_ULP_ACT_HID_6d52 = 0x6d52,
+ BNXT_ULP_ACT_HID_02a6 = 0x02a6,
+ BNXT_ULP_ACT_HID_3ede = 0x3ede,
+ BNXT_ULP_ACT_HID_71ee = 0x71ee,
+ BNXT_ULP_ACT_HID_4fee = 0x4fee,
+ BNXT_ULP_ACT_HID_3a52 = 0x3a52,
+ BNXT_ULP_ACT_HID_6d62 = 0x6d62,
+ BNXT_ULP_ACT_HID_02b6 = 0x02b6,
+ BNXT_ULP_ACT_HID_79de = 0x79de,
+ BNXT_ULP_ACT_HID_57de = 0x57de,
+ BNXT_ULP_ACT_HID_4242 = 0x4242,
+ BNXT_ULP_ACT_HID_46ce = 0x46ce,
+ BNXT_ULP_ACT_HID_7552 = 0x7552,
+ BNXT_ULP_ACT_HID_0aa6 = 0x0aa6,
+ BNXT_ULP_ACT_HID_46de = 0x46de,
+ BNXT_ULP_ACT_HID_79ee = 0x79ee,
+ BNXT_ULP_ACT_HID_57ee = 0x57ee,
+ BNXT_ULP_ACT_HID_4252 = 0x4252,
+ BNXT_ULP_ACT_HID_7562 = 0x7562,
+ BNXT_ULP_ACT_HID_0ab6 = 0x0ab6,
+ BNXT_ULP_ACT_HID_4ece = 0x4ece,
BNXT_ULP_ACT_HID_0622 = 0x0622,
- BNXT_ULP_ACT_HID_0454 = 0x0454,
- BNXT_ULP_ACT_HID_0064 = 0x0064,
- BNXT_ULP_ACT_HID_0614 = 0x0614,
- BNXT_ULP_ACT_HID_0615 = 0x0615,
- BNXT_ULP_ACT_HID_02ab = 0x02ab,
- BNXT_ULP_ACT_HID_0056 = 0x0056,
- BNXT_ULP_ACT_HID_0624 = 0x0624,
- BNXT_ULP_ACT_HID_0456 = 0x0456,
- BNXT_ULP_ACT_HID_0066 = 0x0066,
- BNXT_ULP_ACT_HID_048d = 0x048d,
- BNXT_ULP_ACT_HID_048f = 0x048f,
- BNXT_ULP_ACT_HID_04bc = 0x04bc,
- BNXT_ULP_ACT_HID_00a9 = 0x00a9,
- BNXT_ULP_ACT_HID_020f = 0x020f,
- BNXT_ULP_ACT_HID_0153 = 0x0153,
- BNXT_ULP_ACT_HID_04a9 = 0x04a9,
- BNXT_ULP_ACT_HID_01fc = 0x01fc,
- BNXT_ULP_ACT_HID_04be = 0x04be,
- BNXT_ULP_ACT_HID_00ab = 0x00ab,
- BNXT_ULP_ACT_HID_0211 = 0x0211,
- BNXT_ULP_ACT_HID_0155 = 0x0155,
- BNXT_ULP_ACT_HID_04ab = 0x04ab,
- BNXT_ULP_ACT_HID_01fe = 0x01fe,
- BNXT_ULP_ACT_HID_0667 = 0x0667,
- BNXT_ULP_ACT_HID_0254 = 0x0254,
- BNXT_ULP_ACT_HID_03ba = 0x03ba,
- BNXT_ULP_ACT_HID_02fe = 0x02fe,
- BNXT_ULP_ACT_HID_0654 = 0x0654,
- BNXT_ULP_ACT_HID_03a7 = 0x03a7,
- BNXT_ULP_ACT_HID_0669 = 0x0669,
- BNXT_ULP_ACT_HID_0256 = 0x0256,
- BNXT_ULP_ACT_HID_03bc = 0x03bc,
- BNXT_ULP_ACT_HID_0300 = 0x0300,
- BNXT_ULP_ACT_HID_0656 = 0x0656,
- BNXT_ULP_ACT_HID_03a9 = 0x03a9,
- BNXT_ULP_ACT_HID_021b = 0x021b,
- BNXT_ULP_ACT_HID_021c = 0x021c,
- BNXT_ULP_ACT_HID_021e = 0x021e,
- BNXT_ULP_ACT_HID_063f = 0x063f,
- BNXT_ULP_ACT_HID_0510 = 0x0510,
- BNXT_ULP_ACT_HID_03c6 = 0x03c6,
- BNXT_ULP_ACT_HID_0082 = 0x0082,
- BNXT_ULP_ACT_HID_06bb = 0x06bb,
- BNXT_ULP_ACT_HID_021d = 0x021d,
- BNXT_ULP_ACT_HID_0641 = 0x0641,
- BNXT_ULP_ACT_HID_0512 = 0x0512,
- BNXT_ULP_ACT_HID_03c8 = 0x03c8,
- BNXT_ULP_ACT_HID_0084 = 0x0084,
- BNXT_ULP_ACT_HID_06bd = 0x06bd,
- BNXT_ULP_ACT_HID_06d7 = 0x06d7,
- BNXT_ULP_ACT_HID_02c4 = 0x02c4,
- BNXT_ULP_ACT_HID_042a = 0x042a,
- BNXT_ULP_ACT_HID_036e = 0x036e,
- BNXT_ULP_ACT_HID_06c4 = 0x06c4,
- BNXT_ULP_ACT_HID_0417 = 0x0417,
- BNXT_ULP_ACT_HID_06d9 = 0x06d9,
- BNXT_ULP_ACT_HID_02c6 = 0x02c6,
- BNXT_ULP_ACT_HID_042c = 0x042c,
- BNXT_ULP_ACT_HID_0370 = 0x0370,
- BNXT_ULP_ACT_HID_06c6 = 0x06c6,
- BNXT_ULP_ACT_HID_0419 = 0x0419,
- BNXT_ULP_ACT_HID_0119 = 0x0119,
- BNXT_ULP_ACT_HID_046f = 0x046f,
- BNXT_ULP_ACT_HID_05d5 = 0x05d5,
- BNXT_ULP_ACT_HID_0519 = 0x0519,
- BNXT_ULP_ACT_HID_0106 = 0x0106,
- BNXT_ULP_ACT_HID_05c2 = 0x05c2,
- BNXT_ULP_ACT_HID_011b = 0x011b,
- BNXT_ULP_ACT_HID_0471 = 0x0471,
- BNXT_ULP_ACT_HID_05d7 = 0x05d7,
- BNXT_ULP_ACT_HID_051b = 0x051b,
- BNXT_ULP_ACT_HID_0108 = 0x0108,
- BNXT_ULP_ACT_HID_05c4 = 0x05c4,
- BNXT_ULP_ACT_HID_00a2 = 0x00a2,
- BNXT_ULP_ACT_HID_00a4 = 0x00a4
+ BNXT_ULP_ACT_HID_5fde = 0x5fde,
+ BNXT_ULP_ACT_HID_4a42 = 0x4a42,
+ BNXT_ULP_ACT_HID_0196 = 0x0196,
+ BNXT_ULP_ACT_HID_12a6 = 0x12a6,
+ BNXT_ULP_ACT_HID_4ede = 0x4ede,
+ BNXT_ULP_ACT_HID_0632 = 0x0632,
+ BNXT_ULP_ACT_HID_5fee = 0x5fee,
+ BNXT_ULP_ACT_HID_4a52 = 0x4a52,
+ BNXT_ULP_ACT_HID_01a6 = 0x01a6,
+ BNXT_ULP_ACT_HID_12b6 = 0x12b6,
+ BNXT_ULP_ACT_HID_56ce = 0x56ce,
+ BNXT_ULP_ACT_HID_0e22 = 0x0e22,
+ BNXT_ULP_ACT_HID_67de = 0x67de,
+ BNXT_ULP_ACT_HID_5242 = 0x5242,
+ BNXT_ULP_ACT_HID_0996 = 0x0996,
+ BNXT_ULP_ACT_HID_1aa6 = 0x1aa6,
+ BNXT_ULP_ACT_HID_56de = 0x56de,
+ BNXT_ULP_ACT_HID_0e32 = 0x0e32,
+ BNXT_ULP_ACT_HID_67ee = 0x67ee,
+ BNXT_ULP_ACT_HID_5252 = 0x5252,
+ BNXT_ULP_ACT_HID_09a6 = 0x09a6,
+ BNXT_ULP_ACT_HID_1ab6 = 0x1ab6,
+ BNXT_ULP_ACT_HID_31d0 = 0x31d0,
+ BNXT_ULP_ACT_HID_31e0 = 0x31e0,
+ BNXT_ULP_ACT_HID_39d0 = 0x39d0,
+ BNXT_ULP_ACT_HID_39e0 = 0x39e0,
+ BNXT_ULP_ACT_HID_41d0 = 0x41d0,
+ BNXT_ULP_ACT_HID_41e0 = 0x41e0,
+ BNXT_ULP_ACT_HID_49d0 = 0x49d0,
+ BNXT_ULP_ACT_HID_49e0 = 0x49e0,
+ BNXT_ULP_ACT_HID_64ba = 0x64ba,
+ BNXT_ULP_ACT_HID_64ca = 0x64ca,
+ BNXT_ULP_ACT_HID_6cba = 0x6cba,
+ BNXT_ULP_ACT_HID_6cca = 0x6cca,
+ BNXT_ULP_ACT_HID_74ba = 0x74ba,
+ BNXT_ULP_ACT_HID_74ca = 0x74ca,
+ BNXT_ULP_ACT_HID_00fe = 0x00fe,
+ BNXT_ULP_ACT_HID_010e = 0x010e,
+ BNXT_ULP_ACT_HID_331c = 0x331c,
+ BNXT_ULP_ACT_HID_332c = 0x332c,
+ BNXT_ULP_ACT_HID_6706 = 0x6706,
+ BNXT_ULP_ACT_HID_6716 = 0x6716,
+ BNXT_ULP_ACT_HID_1b6d = 0x1b6d,
+ BNXT_ULP_ACT_HID_1b7d = 0x1b7d,
+ BNXT_ULP_ACT_HID_641a = 0x641a
};
enum bnxt_ulp_df_tpl {
@@ -2618,3 +3879,4 @@ enum bnxt_ulp_df_tpl {
};
#endif
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 0a5c7e3d6e..73cd7762e5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -1,16 +1,18 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Aug 6 11:15:47 2021 */
-
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_WM,
BNXT_ULP_GLB_HF_ID_SVIF_INDEX,
+ BNXT_ULP_GLB_HF_ID_O_ECPRI_TYPE,
+ BNXT_ULP_GLB_HF_ID_I_ECPRI_TYPE,
+ BNXT_ULP_GLB_HF_ID_O_ECPRI_ID,
+ BNXT_ULP_GLB_HF_ID_I_ECPRI_ID,
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC,
BNXT_ULP_GLB_HF_ID_I_ETH_DMAC,
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC,
@@ -65,6 +67,20 @@ enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR,
BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR,
BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_NEXT_HDR,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_NEXT_HDR,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_HDR_LEN,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_HDR_LEN,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_ROUTING_TYPE,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_ROUTING_TYPE,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_SEG_LEFT,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_SEG_LEFT,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_LAST_ENTRY,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_LAST_ENTRY,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_FLAGS,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_FLAGS,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_TAG,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_TAG,
BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT,
@@ -415,94 +431,80 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000080000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -536,61 +538,41 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_5_bitmask {
@@ -617,58 +599,57 @@ enum bnxt_ulp_hf_0_2_5_bitmask {
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_6_bitmask {
BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SENT_SEQ = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_RECV_ACK = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DATA_OFF = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_TCP_FLAGS = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_RX_WIN = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_CSUM = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_URP = 0x0000000004000000
};
enum bnxt_ulp_hf_0_2_7_bitmask {
@@ -695,21 +676,343 @@ enum bnxt_ulp_hf_0_2_7_bitmask {
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_URP = 0x0000000001000000
+};
+
+enum bnxt_ulp_hf_0_2_8_bitmask {
+ BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_URP = 0x0000000001000000
+};
+
+enum bnxt_ulp_hf_0_2_9_bitmask {
+ BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_10_bitmask {
+ BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_LENGTH = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_CSUM = 0x0000000080000000
+};
+
+enum bnxt_ulp_hf_0_2_11_bitmask {
+ BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_12_bitmask {
+ BNXT_ULP_HF_0_2_12_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_13_bitmask {
+ BNXT_ULP_HF_0_2_13_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_14_bitmask {
+ BNXT_ULP_HF_0_2_14_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_TYPE = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_CODE = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_CSUM = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_IDENT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_SEQ_NUM = 0x0000000010000000
+};
+
+enum bnxt_ulp_hf_0_2_15_bitmask {
+ BNXT_ULP_HF_0_2_15_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 305e516a7f..d08443ff43 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Nov 12 19:33:52 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -77,7 +75,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE",
.result_num_entries = 512,
.result_num_bytes = 8,
- .key_num_bytes = 10,
+ .key_num_bytes = 12,
.num_buckets = 8,
.hash_tbl_entries = 2048,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
@@ -87,7 +85,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE",
.result_num_entries = 512,
.result_num_bytes = 8,
- .key_num_bytes = 10,
+ .key_num_bytes = 12,
.num_buckets = 8,
.hash_tbl_entries = 2048,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
@@ -96,7 +94,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
- .result_num_bytes = 19,
+ .result_num_bytes = 21,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
@@ -106,7 +104,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
BNXT_ULP_DIRECTION_EGRESS] = {
.name = "EGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
- .result_num_bytes = 19,
+ .result_num_bytes = 21,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
@@ -135,16 +133,16 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
- .result_num_entries = 0,
+ .result_num_entries = 4096,
.result_num_bytes = 6,
.key_num_bytes = 10,
.num_buckets = 4,
- .hash_tbl_entries = 0,
+ .hash_tbl_entries = 8192,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
BNXT_ULP_DIRECTION_EGRESS] = {
- .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
.result_num_entries = 128,
.result_num_bytes = 6,
.key_num_bytes = 10,
@@ -152,6 +150,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.hash_tbl_entries = 512,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_L2_ENCAP_REC_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 6,
+ .key_num_bytes = 14,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_L2_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 14,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
@@ -191,6 +209,166 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 22,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE",
+ .result_num_entries = 2048,
+ .result_num_bytes = 6,
+ .key_num_bytes = 22,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 16384,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE",
+ .result_num_entries = 2048,
+ .result_num_bytes = 6,
+ .key_num_bytes = 86,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_OUTER_TUNNEL_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 4,
+ .key_num_bytes = 32,
+ .num_buckets = 4,
+ .hash_tbl_entries = 16384,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_OUTER_TUNNEL_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 4,
+ .key_num_bytes = 32,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE",
+ .result_num_entries = 512,
+ .result_num_bytes = 8,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE",
+ .result_num_entries = 512,
+ .result_num_bytes = 8,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE",
+ .result_num_entries = 1024,
+ .result_num_bytes = 10,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE",
+ .result_num_entries = 1024,
+ .result_num_bytes = 10,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL",
+ .result_num_entries = 256,
+ .result_num_bytes = 8,
+ .key_num_bytes = 3,
+ .num_buckets = 4,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL",
+ .result_num_entries = 0,
+ .result_num_bytes = 8,
+ .key_num_bytes = 3,
+ .num_buckets = 0,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_CHAIN_ID_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 4,
+ .key_num_bytes = 4,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_CHAIN_ID_CACHE",
+ .result_num_entries = 64,
+ .result_num_bytes = 4,
+ .key_num_bytes = 4,
+ .num_buckets = 4,
+ .hash_tbl_entries = 256,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -281,8 +459,15 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xfffffff000000000,
.byte_count_shift = 0,
.packet_count_shift = 36,
- .dynamic_pad_en = 0,
+ .wc_dynamic_pad_en = 1,
+ .em_dynamic_pad_en = 0,
.dynamic_sram_en = 0,
+ .wc_slice_width = 80,
+ .wc_max_slices = 4,
+ .wc_mode_list = {0x00000000, 0x00000002,
+ 0x00000003, 0x00000003},
+ .wc_mod_list_max_size = 4,
+ .wc_ctl_size_bits = 16,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -306,13 +491,15 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xfffffff800000000,
.byte_count_shift = 0,
.packet_count_shift = 35,
- .dynamic_pad_en = 1,
+ .wc_dynamic_pad_en = 1,
+ .em_dynamic_pad_en = 1,
.dynamic_sram_en = 1,
- .dyn_encap_list_size = 4,
+ .dyn_encap_list_size = 5,
.dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
{128, TF_TBL_TYPE_ACT_ENCAP_16B},
{256, TF_TBL_TYPE_ACT_ENCAP_32B},
- {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B},
+ {1024, TF_TBL_TYPE_ACT_ENCAP_128B}},
.dyn_modify_list_size = 4,
.dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
{128, TF_TBL_TYPE_ACT_MODIFY_16B},
@@ -348,55 +535,75 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = 0
+ .flags = 0,
+ .vxlan_port = 4789,
+ .vxlan_ip_port = 0
},
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .flags = 0
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_SRV6,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_SRV6,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 3,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
.app_id = 4,
@@ -404,576 +611,617 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY |
- BNXT_ULP_APP_CAP_SOCKET_DIRECT
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 3,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
+ BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_HA_DYNAMIC,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 1,
+ .ha_pool_id = 4,
+ .ha_reg_cnt = 9,
+ .ha_reg_state = 10
},
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY |
- BNXT_ULP_APP_CAP_SOCKET_DIRECT
- }
-};
-
-/* List of unnamed app tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = {
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT |
+ BNXT_ULP_APP_CAP_HA_DYNAMIC,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 1,
+ .ha_pool_id = 4,
+ .ha_reg_cnt = 9,
+ .ha_reg_state = 10
+ },
{
- .app_id = 1,
+ .app_id = 6,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ },
+ {
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 1024
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 250
},
{
- .app_id = 2,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 1024
+ .flags = BNXT_ULP_APP_CAP_BC_MC_SUPPORT |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN |
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 5,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN |
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 5,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
- .app_id = 4,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ }
+};
+
+/* List of unnamed app tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = {
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 4,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 6648
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 1792
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 896
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 5,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
},
{
- .app_id = 5,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 6648
- }
-};
-
-/* List of global app tf resources required to be reserved per app/device */
-struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
+ .count = 6860
+ },
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
.app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .count = 1792
},
{
.app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 896
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
},
{
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4096
},
{
.app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 64
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
+ .app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 392
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 1024
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 704
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 704
+ }
+};
+
+/* List of global app tf resources required to be reserved per app/device */
+struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 2,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_RX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -982,6 +1230,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -990,6 +1239,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -998,6 +1248,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1006,6 +1257,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1014,6 +1266,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1022,6 +1275,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1030,6 +1284,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1038,6 +1293,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1046,6 +1302,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1054,6 +1311,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1062,6 +1320,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1070,6 +1329,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1078,6 +1338,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1086,6 +1347,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1094,6 +1356,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1102,6 +1365,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1110,6 +1374,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1118,6 +1383,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1126,6 +1392,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1134,6 +1401,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1142,6 +1410,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1150,6 +1419,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1158,6 +1428,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1166,6 +1437,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1174,6 +1446,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1182,6 +1455,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1190,6 +1464,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1198,6 +1473,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1206,6 +1482,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1214,6 +1491,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1222,6 +1500,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1230,6 +1509,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1238,6 +1518,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1246,6 +1527,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1254,6 +1536,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1262,6 +1545,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1270,6 +1554,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1278,6 +1563,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
@@ -1286,6 +1572,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
@@ -1294,6 +1581,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
@@ -1302,6 +1590,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
@@ -1310,6 +1599,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3,
@@ -1318,6 +1608,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4,
@@ -1326,6 +1617,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1334,6 +1626,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1342,6 +1635,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1350,6 +1644,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1358,6 +1653,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1366,6 +1662,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1374,6 +1671,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1382,6 +1680,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1390,6 +1689,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1398,6 +1698,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1406,6 +1707,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1414,6 +1716,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1422,6 +1725,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1430,6 +1734,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1438,6 +1743,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1446,6 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1454,6 +1761,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1462,6 +1770,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1470,6 +1779,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1478,6 +1788,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1486,6 +1797,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1494,6 +1806,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1502,6 +1815,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1510,6 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1518,6 +1833,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1526,6 +1842,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1534,6 +1851,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1542,6 +1860,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1550,6 +1869,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1558,6 +1878,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1566,6 +1887,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1574,6 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1582,6 +1905,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1590,6 +1914,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1598,6 +1923,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1606,6 +1932,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1614,6 +1941,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1622,6 +1950,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1630,6 +1959,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1638,6 +1968,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1646,6 +1977,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
@@ -1654,6 +1986,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
@@ -1662,6 +1995,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
@@ -1670,6 +2004,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
@@ -1678,6 +2013,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3,
@@ -1686,6 +2022,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4,
@@ -1694,6 +2031,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1702,4346 +2040,14401 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
- }
-};
-
-/* List of global tf resources required to be reserved per app/device */
-struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ },
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of global tf resources required to be reserved per app/device */
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
.direction = TF_DIR_TX
},
{
- .app_id = 3,
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
.direction = TF_DIR_TX
},
{
- .app_id = 3,
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_9,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_9,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
+ .count = 256
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 256
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 24
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 256
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 256
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 4
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 256
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 4
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 24
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 26624
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4096
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 2048
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 6144
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 48
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 12
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 3576
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 3576
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 12
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 192
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 192
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 26624
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4096
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 2048
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 6144
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
- .direction = TF_DIR_RX
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .count = 63
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 272
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 8192
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 2048
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 272
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4096
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 16384
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 272
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 8192
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 2048
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 272
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4096
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 16384
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 588
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 6912
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 6912
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 31
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 64
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 16384
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 16384
},
{
- .app_id = 3,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 422
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 191
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.count = 1023
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.count = 15
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
.count = 255
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 422
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 960
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 88
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 13168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 292
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 148
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 191
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.count = 1023
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.count = 223
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.count = 255
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 488
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 292
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 144
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 960
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 928
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 15232
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 26624
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 4096
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 2048
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 6144
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 62
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4080
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 4080
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 1024
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 191
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 3340
+ .count = 8192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 3340
+ .count = 6912
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 88
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 6912
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 5,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 1024
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 1024
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1000
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1000
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 100
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2032
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_METER_PROF,
+ .count = 256
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .count = 1023
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 16384
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 16384
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
}
};
@@ -6138,787 +16531,1095 @@ uint32_t ulp_act_prop_map_table[] = {
BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN,
[BNXT_ULP_ACT_PROP_IDX_RSS_KEY] =
BNXT_ULP_ACT_PROP_SZ_RSS_KEY,
+ [BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE] =
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE,
+ [BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX] =
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBND,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBND,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBSM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBSM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CF,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ID] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL,
+ [BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID] =
+ BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID,
[BNXT_ULP_ACT_PROP_IDX_LAST] =
BNXT_ULP_ACT_PROP_SZ_LAST
};
uint8_t ulp_glb_field_tbl[] = {
- [2048] = 0,
- [2049] = 1,
- [2050] = 2,
- [2052] = 3,
- [2054] = 4,
- [2088] = 5,
- [2090] = 6,
- [2092] = 7,
- [2094] = 8,
- [2096] = 9,
- [2098] = 10,
- [2100] = 11,
- [2102] = 12,
- [2176] = 0,
- [2177] = 1,
- [2178] = 2,
- [2180] = 3,
- [2182] = 4,
- [2196] = 5,
- [2198] = 6,
- [2200] = 7,
- [2202] = 8,
- [2204] = 9,
- [2206] = 10,
- [2208] = 11,
- [2210] = 12,
- [2212] = 13,
- [2214] = 14,
- [2304] = 0,
- [2305] = 1,
- [2306] = 2,
- [2308] = 3,
- [2310] = 4,
- [2344] = 8,
- [2346] = 9,
- [2348] = 10,
- [2350] = 11,
- [2352] = 12,
- [2354] = 13,
- [2356] = 14,
- [2358] = 15,
- [2386] = 5,
- [2390] = 6,
- [2394] = 7,
- [2432] = 0,
- [2433] = 1,
- [2434] = 2,
- [2436] = 3,
- [2438] = 4,
- [2452] = 8,
- [2454] = 9,
- [2456] = 10,
- [2458] = 11,
- [2460] = 12,
- [2462] = 13,
- [2464] = 14,
- [2466] = 15,
- [2468] = 16,
- [2470] = 17,
- [2514] = 5,
- [2518] = 6,
- [2522] = 7,
- [2560] = 0,
- [2561] = 1,
- [2562] = 2,
- [2564] = 3,
- [2566] = 4,
- [2600] = 5,
- [2602] = 6,
- [2604] = 7,
- [2606] = 8,
- [2608] = 9,
- [2610] = 10,
- [2612] = 11,
- [2614] = 12,
- [2616] = 13,
- [2618] = 14,
- [2620] = 15,
- [2622] = 16,
- [2624] = 17,
- [2626] = 18,
- [2628] = 19,
- [2630] = 20,
- [2632] = 21,
- [2688] = 0,
- [2689] = 1,
- [2690] = 2,
- [2692] = 3,
- [2694] = 4,
- [2708] = 5,
- [2710] = 6,
- [2712] = 7,
- [2714] = 8,
- [2716] = 9,
- [2718] = 10,
- [2720] = 11,
- [2722] = 12,
- [2724] = 13,
- [2726] = 14,
- [2744] = 15,
- [2746] = 16,
- [2748] = 17,
- [2750] = 18,
- [2752] = 19,
- [2754] = 20,
- [2756] = 21,
- [2758] = 22,
- [2760] = 23,
- [2816] = 0,
- [2817] = 1,
- [2818] = 2,
- [2820] = 3,
- [2822] = 4,
- [2856] = 5,
- [2858] = 6,
- [2860] = 7,
- [2862] = 8,
- [2864] = 9,
- [2866] = 10,
- [2868] = 11,
- [2870] = 12,
- [2890] = 13,
- [2892] = 14,
- [2894] = 15,
- [2896] = 16,
- [2944] = 0,
- [2945] = 1,
- [2946] = 2,
- [2948] = 3,
- [2950] = 4,
- [2964] = 5,
- [2966] = 6,
- [2968] = 7,
- [2970] = 8,
- [2972] = 9,
- [2974] = 10,
- [2976] = 11,
- [2978] = 12,
- [2980] = 13,
- [2982] = 14,
- [3018] = 15,
- [3020] = 16,
- [3022] = 17,
- [3024] = 18,
- [3072] = 0,
- [3073] = 1,
- [3074] = 2,
- [3076] = 3,
- [3078] = 4,
- [3112] = 8,
- [3114] = 9,
- [3116] = 10,
- [3118] = 11,
- [3120] = 12,
- [3122] = 13,
- [3124] = 14,
- [3126] = 15,
- [3128] = 16,
- [3130] = 17,
- [3132] = 18,
- [3134] = 19,
- [3136] = 20,
- [3138] = 21,
- [3140] = 22,
- [3142] = 23,
- [3144] = 24,
- [3154] = 5,
- [3158] = 6,
- [3162] = 7,
- [3200] = 0,
- [3201] = 1,
- [3202] = 2,
- [3204] = 3,
- [3206] = 4,
- [3220] = 8,
- [3222] = 9,
- [3224] = 10,
- [3226] = 11,
- [3228] = 12,
- [3230] = 13,
- [3232] = 14,
- [3234] = 15,
- [3236] = 16,
- [3238] = 17,
- [3256] = 18,
- [3258] = 19,
- [3260] = 20,
- [3262] = 21,
- [3264] = 22,
- [3266] = 23,
- [3268] = 24,
- [3270] = 25,
- [3272] = 26,
- [3282] = 5,
- [3286] = 6,
- [3290] = 7,
- [3328] = 0,
- [3329] = 1,
- [3330] = 2,
- [3332] = 3,
- [3334] = 4,
- [3368] = 8,
- [3370] = 9,
- [3372] = 10,
- [3374] = 11,
- [3376] = 12,
- [3378] = 13,
- [3380] = 14,
- [3382] = 15,
- [3402] = 16,
- [3404] = 17,
- [3406] = 18,
- [3408] = 19,
- [3410] = 5,
- [3414] = 6,
- [3418] = 7,
- [3456] = 0,
- [3457] = 1,
- [3458] = 2,
- [3460] = 3,
- [3462] = 4,
- [3476] = 8,
- [3478] = 9,
- [3480] = 10,
- [3482] = 11,
- [3484] = 12,
- [3486] = 13,
- [3488] = 14,
- [3490] = 15,
- [3492] = 16,
- [3494] = 17,
- [3530] = 18,
- [3532] = 19,
- [3534] = 20,
- [3536] = 21,
- [3538] = 5,
- [3542] = 6,
- [3546] = 7,
- [3584] = 0,
- [3585] = 1,
- [3586] = 2,
- [3588] = 3,
- [3590] = 4,
- [3604] = 5,
- [3606] = 6,
- [3608] = 7,
- [3610] = 8,
- [3612] = 9,
- [3614] = 10,
- [3616] = 11,
- [3618] = 12,
- [3620] = 13,
- [3622] = 14,
- [3658] = 15,
- [3660] = 16,
- [3662] = 17,
- [3664] = 18,
- [3678] = 19,
- [3679] = 20,
- [3680] = 21,
- [3681] = 22,
[4096] = 0,
[4097] = 1,
- [4098] = 2,
- [4100] = 3,
- [4102] = 4,
- [4116] = 5,
- [4118] = 6,
- [4120] = 7,
- [4122] = 8,
- [4124] = 9,
- [4126] = 10,
- [4128] = 11,
- [4130] = 12,
- [4132] = 13,
- [4134] = 14,
- [4170] = 15,
- [4172] = 16,
- [4174] = 17,
- [4176] = 18,
- [4190] = 19,
- [4191] = 20,
- [4192] = 21,
- [4193] = 22,
+ [4102] = 2,
+ [4104] = 3,
+ [4106] = 4,
+ [4140] = 5,
+ [4142] = 6,
+ [4144] = 7,
+ [4146] = 8,
+ [4148] = 9,
+ [4150] = 10,
+ [4152] = 11,
+ [4154] = 12,
[4224] = 0,
[4225] = 1,
- [4227] = 20,
- [4229] = 21,
- [4231] = 22,
- [4244] = 2,
- [4246] = 3,
- [4248] = 4,
- [4250] = 5,
- [4252] = 6,
- [4254] = 7,
- [4256] = 8,
- [4258] = 9,
- [4260] = 10,
- [4262] = 11,
- [4265] = 23,
- [4267] = 24,
- [4269] = 25,
- [4271] = 26,
- [4273] = 27,
- [4275] = 28,
- [4277] = 29,
- [4279] = 30,
- [4298] = 12,
- [4300] = 13,
- [4302] = 14,
- [4304] = 15,
- [4318] = 16,
- [4319] = 17,
- [4320] = 18,
- [4321] = 19,
+ [4230] = 2,
+ [4232] = 3,
+ [4234] = 4,
+ [4248] = 5,
+ [4250] = 6,
+ [4252] = 7,
+ [4254] = 8,
+ [4256] = 9,
+ [4258] = 10,
+ [4260] = 11,
+ [4262] = 12,
+ [4264] = 13,
+ [4266] = 14,
[4352] = 0,
[4353] = 1,
- [4355] = 20,
- [4357] = 21,
- [4359] = 22,
- [4372] = 2,
- [4373] = 23,
- [4374] = 3,
- [4375] = 24,
- [4376] = 4,
- [4377] = 25,
- [4378] = 5,
- [4379] = 26,
- [4380] = 6,
- [4381] = 27,
- [4382] = 7,
- [4383] = 28,
- [4384] = 8,
- [4385] = 29,
- [4386] = 9,
- [4387] = 30,
- [4388] = 10,
- [4389] = 31,
- [4390] = 11,
- [4391] = 32,
- [4426] = 12,
- [4428] = 13,
- [4430] = 14,
- [4432] = 15,
- [4446] = 16,
- [4447] = 17,
- [4448] = 18,
- [4449] = 19,
+ [4358] = 2,
+ [4360] = 3,
+ [4362] = 4,
+ [4396] = 8,
+ [4398] = 9,
+ [4400] = 10,
+ [4402] = 11,
+ [4404] = 12,
+ [4406] = 13,
+ [4408] = 14,
+ [4410] = 15,
+ [4452] = 5,
+ [4456] = 6,
+ [4460] = 7,
[4480] = 0,
[4481] = 1,
- [4483] = 20,
- [4485] = 21,
- [4487] = 22,
- [4500] = 2,
- [4502] = 3,
- [4504] = 4,
- [4506] = 5,
- [4508] = 6,
- [4510] = 7,
- [4512] = 8,
- [4514] = 9,
- [4516] = 10,
- [4518] = 11,
- [4521] = 23,
- [4523] = 24,
- [4525] = 25,
- [4527] = 26,
- [4529] = 27,
- [4531] = 28,
- [4533] = 29,
- [4535] = 30,
- [4537] = 31,
- [4539] = 32,
- [4541] = 33,
- [4543] = 34,
- [4545] = 35,
- [4547] = 36,
- [4549] = 37,
- [4551] = 38,
- [4553] = 39,
- [4554] = 12,
- [4556] = 13,
- [4558] = 14,
- [4560] = 15,
- [4574] = 16,
- [4575] = 17,
- [4576] = 18,
- [4577] = 19,
+ [4486] = 2,
+ [4488] = 3,
+ [4490] = 4,
+ [4504] = 8,
+ [4506] = 9,
+ [4508] = 10,
+ [4510] = 11,
+ [4512] = 12,
+ [4514] = 13,
+ [4516] = 14,
+ [4518] = 15,
+ [4520] = 16,
+ [4522] = 17,
+ [4580] = 5,
+ [4584] = 6,
+ [4588] = 7,
[4608] = 0,
[4609] = 1,
- [4611] = 20,
- [4613] = 21,
- [4615] = 22,
- [4628] = 2,
- [4629] = 23,
- [4630] = 3,
- [4631] = 24,
- [4632] = 4,
- [4633] = 25,
- [4634] = 5,
- [4635] = 26,
- [4636] = 6,
- [4637] = 27,
- [4638] = 7,
- [4639] = 28,
- [4640] = 8,
- [4641] = 29,
- [4642] = 9,
- [4643] = 30,
- [4644] = 10,
- [4645] = 31,
- [4646] = 11,
- [4647] = 32,
- [4665] = 33,
- [4667] = 34,
- [4669] = 35,
- [4671] = 36,
- [4673] = 37,
- [4675] = 38,
- [4677] = 39,
- [4679] = 40,
- [4681] = 41,
- [4682] = 12,
- [4684] = 13,
- [4686] = 14,
- [4688] = 15,
- [4702] = 16,
- [4703] = 17,
- [4704] = 18,
- [4705] = 19,
+ [4614] = 2,
+ [4616] = 3,
+ [4618] = 4,
+ [4652] = 5,
+ [4654] = 6,
+ [4656] = 7,
+ [4658] = 8,
+ [4660] = 9,
+ [4662] = 10,
+ [4664] = 11,
+ [4666] = 12,
+ [4682] = 13,
+ [4684] = 14,
+ [4686] = 15,
+ [4688] = 16,
+ [4690] = 17,
+ [4692] = 18,
+ [4694] = 19,
+ [4696] = 20,
+ [4698] = 21,
[4736] = 0,
[4737] = 1,
- [4739] = 20,
- [4741] = 21,
- [4743] = 22,
- [4756] = 2,
- [4758] = 3,
- [4760] = 4,
- [4762] = 5,
- [4764] = 6,
- [4766] = 7,
- [4768] = 8,
- [4770] = 9,
- [4772] = 10,
- [4774] = 11,
- [4777] = 23,
- [4779] = 24,
- [4781] = 25,
- [4783] = 26,
- [4785] = 27,
- [4787] = 28,
- [4789] = 29,
- [4791] = 30,
- [4810] = 12,
- [4811] = 31,
- [4812] = 13,
- [4813] = 32,
- [4814] = 14,
- [4815] = 33,
- [4816] = 15,
- [4817] = 34,
- [4830] = 16,
- [4831] = 17,
- [4832] = 18,
- [4833] = 19,
+ [4742] = 2,
+ [4744] = 3,
+ [4746] = 4,
+ [4760] = 5,
+ [4762] = 6,
+ [4764] = 7,
+ [4766] = 8,
+ [4768] = 9,
+ [4770] = 10,
+ [4772] = 11,
+ [4774] = 12,
+ [4776] = 13,
+ [4778] = 14,
+ [4810] = 15,
+ [4812] = 16,
+ [4814] = 17,
+ [4816] = 18,
+ [4818] = 19,
+ [4820] = 20,
+ [4822] = 21,
+ [4824] = 22,
+ [4826] = 23,
[4864] = 0,
[4865] = 1,
- [4867] = 20,
- [4869] = 21,
- [4871] = 22,
- [4884] = 2,
- [4885] = 23,
- [4886] = 3,
- [4887] = 24,
- [4888] = 4,
- [4889] = 25,
- [4890] = 5,
- [4891] = 26,
- [4892] = 6,
- [4893] = 27,
- [4894] = 7,
- [4895] = 28,
- [4896] = 8,
- [4897] = 29,
- [4898] = 9,
- [4899] = 30,
- [4900] = 10,
- [4901] = 31,
- [4902] = 11,
- [4903] = 32,
- [4938] = 12,
- [4939] = 33,
- [4940] = 13,
- [4941] = 34,
- [4942] = 14,
- [4943] = 35,
- [4944] = 15,
- [4945] = 36,
- [4958] = 16,
- [4959] = 17,
- [4960] = 18,
- [4961] = 19,
+ [4870] = 2,
+ [4872] = 3,
+ [4874] = 4,
+ [4908] = 5,
+ [4910] = 6,
+ [4912] = 7,
+ [4914] = 8,
+ [4916] = 9,
+ [4918] = 10,
+ [4920] = 11,
+ [4922] = 12,
+ [4956] = 13,
+ [4958] = 14,
+ [4960] = 15,
+ [4962] = 16,
[4992] = 0,
[4993] = 1,
- [4995] = 20,
- [4997] = 21,
- [4999] = 22,
- [5003] = 33,
- [5005] = 34,
- [5007] = 35,
- [5009] = 36,
- [5011] = 37,
- [5012] = 2,
- [5013] = 23,
- [5014] = 3,
- [5015] = 24,
- [5016] = 4,
- [5017] = 25,
- [5018] = 5,
- [5019] = 26,
- [5020] = 6,
- [5021] = 27,
- [5022] = 7,
- [5023] = 28,
- [5024] = 8,
- [5025] = 29,
- [5026] = 9,
- [5027] = 30,
- [5028] = 10,
- [5029] = 31,
- [5030] = 11,
- [5031] = 32,
- [5066] = 12,
- [5068] = 13,
- [5070] = 14,
- [5072] = 15,
+ [4998] = 2,
+ [5000] = 3,
+ [5002] = 4,
+ [5016] = 5,
+ [5018] = 6,
+ [5020] = 7,
+ [5022] = 8,
+ [5024] = 9,
+ [5026] = 10,
+ [5028] = 11,
+ [5030] = 12,
+ [5032] = 13,
+ [5034] = 14,
+ [5084] = 15,
[5086] = 16,
- [5087] = 17,
- [5088] = 18,
- [5089] = 19,
- [6144] = 0,
- [6145] = 1,
- [6146] = 2,
- [6148] = 3,
- [6150] = 4,
- [6184] = 5,
- [6186] = 6,
- [6188] = 7,
- [6190] = 8,
- [6192] = 9,
- [6194] = 10,
- [6196] = 11,
- [6198] = 12,
- [6272] = 0,
- [6273] = 1,
- [6274] = 2,
- [6276] = 3,
- [6278] = 4,
- [6292] = 5,
- [6294] = 6,
- [6296] = 7,
- [6298] = 8,
- [6300] = 9,
- [6302] = 10,
- [6304] = 11,
- [6306] = 12,
- [6308] = 13,
- [6310] = 14,
- [6400] = 0,
- [6401] = 1,
- [6402] = 2,
- [6404] = 3,
- [6406] = 4,
- [6440] = 8,
- [6442] = 9,
- [6444] = 10,
- [6446] = 11,
- [6448] = 12,
- [6450] = 13,
- [6452] = 14,
- [6454] = 15,
- [6482] = 5,
- [6486] = 6,
- [6490] = 7,
- [6528] = 0,
- [6529] = 1,
- [6530] = 2,
- [6532] = 3,
- [6534] = 4,
- [6548] = 8,
- [6550] = 9,
- [6552] = 10,
- [6554] = 11,
- [6556] = 12,
- [6558] = 13,
- [6560] = 14,
- [6562] = 15,
- [6564] = 16,
- [6566] = 17,
- [6610] = 5,
- [6614] = 6,
- [6618] = 7,
- [6656] = 0,
- [6657] = 1,
- [6658] = 2,
- [6660] = 3,
- [6662] = 4,
- [6696] = 5,
- [6698] = 6,
- [6700] = 7,
- [6702] = 8,
- [6704] = 9,
- [6706] = 10,
- [6708] = 11,
- [6710] = 12,
- [6712] = 13,
- [6714] = 14,
- [6716] = 15,
- [6718] = 16,
- [6720] = 17,
- [6722] = 18,
- [6724] = 19,
- [6726] = 20,
- [6728] = 21,
- [6784] = 0,
- [6785] = 1,
- [6786] = 2,
- [6788] = 3,
- [6790] = 4,
- [6804] = 5,
- [6806] = 6,
- [6808] = 7,
- [6810] = 8,
- [6812] = 9,
- [6814] = 10,
- [6816] = 11,
- [6818] = 12,
- [6820] = 13,
- [6822] = 14,
- [6840] = 15,
- [6842] = 16,
- [6844] = 17,
- [6846] = 18,
- [6848] = 19,
- [6850] = 20,
- [6852] = 21,
- [6854] = 22,
- [6856] = 23,
- [6912] = 0,
- [6913] = 1,
- [6914] = 2,
- [6916] = 3,
- [6918] = 4,
- [6952] = 5,
- [6954] = 6,
- [6956] = 7,
- [6958] = 8,
- [6960] = 9,
- [6962] = 10,
- [6964] = 11,
- [6966] = 12,
- [6986] = 13,
- [6988] = 14,
- [6990] = 15,
- [6992] = 16,
- [7040] = 0,
- [7041] = 1,
- [7042] = 2,
- [7044] = 3,
- [7046] = 4,
- [7060] = 5,
- [7062] = 6,
- [7064] = 7,
- [7066] = 8,
- [7068] = 9,
- [7070] = 10,
- [7072] = 11,
- [7074] = 12,
- [7076] = 13,
- [7078] = 14,
- [7114] = 15,
- [7116] = 16,
- [7118] = 17,
- [7120] = 18,
- [7168] = 0,
- [7169] = 1,
- [7170] = 2,
- [7172] = 3,
- [7174] = 4,
- [7208] = 8,
- [7210] = 9,
- [7212] = 10,
- [7214] = 11,
- [7216] = 12,
- [7218] = 13,
- [7220] = 14,
- [7222] = 15,
- [7224] = 16,
- [7226] = 17,
- [7228] = 18,
- [7230] = 19,
- [7232] = 20,
- [7234] = 21,
- [7236] = 22,
- [7238] = 23,
- [7240] = 24,
- [7250] = 5,
- [7254] = 6,
- [7258] = 7,
- [7296] = 0,
- [7297] = 1,
- [7298] = 2,
- [7300] = 3,
- [7302] = 4,
- [7316] = 8,
- [7318] = 9,
- [7320] = 10,
- [7322] = 11,
- [7324] = 12,
- [7326] = 13,
- [7328] = 14,
- [7330] = 15,
- [7332] = 16,
- [7334] = 17,
- [7352] = 18,
- [7354] = 19,
- [7356] = 20,
- [7358] = 21,
- [7360] = 22,
- [7362] = 23,
- [7364] = 24,
- [7366] = 25,
- [7368] = 26,
- [7378] = 5,
- [7382] = 6,
- [7386] = 7,
- [7424] = 0,
- [7425] = 1,
- [7426] = 2,
- [7428] = 3,
- [7430] = 4,
- [7464] = 8,
- [7466] = 9,
- [7468] = 10,
- [7470] = 11,
- [7472] = 12,
- [7474] = 13,
- [7476] = 14,
- [7478] = 15,
- [7498] = 16,
- [7500] = 17,
- [7502] = 18,
- [7504] = 19,
- [7506] = 5,
- [7510] = 6,
- [7514] = 7,
- [7552] = 0,
- [7553] = 1,
- [7554] = 2,
- [7556] = 3,
- [7558] = 4,
- [7572] = 8,
- [7574] = 9,
- [7576] = 10,
- [7578] = 11,
- [7580] = 12,
- [7582] = 13,
- [7584] = 14,
- [7586] = 15,
- [7588] = 16,
- [7590] = 17,
- [7626] = 18,
- [7628] = 19,
- [7630] = 20,
- [7632] = 21,
- [7634] = 5,
- [7638] = 6,
- [7642] = 7
+ [5088] = 17,
+ [5090] = 18,
+ [5120] = 0,
+ [5121] = 1,
+ [5126] = 2,
+ [5128] = 3,
+ [5130] = 4,
+ [5164] = 8,
+ [5166] = 9,
+ [5168] = 10,
+ [5170] = 11,
+ [5172] = 12,
+ [5174] = 13,
+ [5176] = 14,
+ [5178] = 15,
+ [5194] = 16,
+ [5196] = 17,
+ [5198] = 18,
+ [5200] = 19,
+ [5202] = 20,
+ [5204] = 21,
+ [5206] = 22,
+ [5208] = 23,
+ [5210] = 24,
+ [5220] = 5,
+ [5224] = 6,
+ [5228] = 7,
+ [5248] = 0,
+ [5249] = 1,
+ [5254] = 2,
+ [5256] = 3,
+ [5258] = 4,
+ [5272] = 8,
+ [5274] = 9,
+ [5276] = 10,
+ [5278] = 11,
+ [5280] = 12,
+ [5282] = 13,
+ [5284] = 14,
+ [5286] = 15,
+ [5288] = 16,
+ [5290] = 17,
+ [5322] = 18,
+ [5324] = 19,
+ [5326] = 20,
+ [5328] = 21,
+ [5330] = 22,
+ [5332] = 23,
+ [5334] = 24,
+ [5336] = 25,
+ [5338] = 26,
+ [5348] = 5,
+ [5352] = 6,
+ [5356] = 7,
+ [5376] = 0,
+ [5377] = 1,
+ [5382] = 2,
+ [5384] = 3,
+ [5386] = 4,
+ [5420] = 8,
+ [5422] = 9,
+ [5424] = 10,
+ [5426] = 11,
+ [5428] = 12,
+ [5430] = 13,
+ [5432] = 14,
+ [5434] = 15,
+ [5468] = 16,
+ [5470] = 17,
+ [5472] = 18,
+ [5474] = 19,
+ [5476] = 5,
+ [5480] = 6,
+ [5484] = 7,
+ [5504] = 0,
+ [5505] = 1,
+ [5510] = 2,
+ [5512] = 3,
+ [5514] = 4,
+ [5528] = 8,
+ [5530] = 9,
+ [5532] = 10,
+ [5534] = 11,
+ [5536] = 12,
+ [5538] = 13,
+ [5540] = 14,
+ [5542] = 15,
+ [5544] = 16,
+ [5546] = 17,
+ [5596] = 18,
+ [5598] = 19,
+ [5600] = 20,
+ [5602] = 21,
+ [5604] = 5,
+ [5608] = 6,
+ [5612] = 7,
+ [5632] = 0,
+ [5633] = 1,
+ [5638] = 2,
+ [5640] = 3,
+ [5642] = 4,
+ [5656] = 5,
+ [5658] = 6,
+ [5660] = 7,
+ [5662] = 8,
+ [5664] = 9,
+ [5666] = 10,
+ [5668] = 11,
+ [5670] = 12,
+ [5672] = 13,
+ [5674] = 14,
+ [5724] = 15,
+ [5726] = 16,
+ [5728] = 17,
+ [5730] = 18,
+ [5744] = 19,
+ [5745] = 20,
+ [5746] = 21,
+ [5747] = 22,
+ [8192] = 0,
+ [8193] = 1,
+ [8198] = 2,
+ [8200] = 3,
+ [8202] = 4,
+ [8236] = 5,
+ [8238] = 6,
+ [8240] = 7,
+ [8242] = 8,
+ [8244] = 9,
+ [8246] = 10,
+ [8248] = 11,
+ [8250] = 12,
+ [8284] = 13,
+ [8286] = 14,
+ [8288] = 15,
+ [8290] = 16,
+ [8304] = 17,
+ [8305] = 18,
+ [8306] = 19,
+ [8307] = 20,
+ [8320] = 0,
+ [8321] = 1,
+ [8326] = 2,
+ [8328] = 3,
+ [8330] = 4,
+ [8344] = 5,
+ [8346] = 6,
+ [8348] = 7,
+ [8350] = 8,
+ [8352] = 9,
+ [8354] = 10,
+ [8356] = 11,
+ [8358] = 12,
+ [8360] = 13,
+ [8362] = 14,
+ [8412] = 15,
+ [8414] = 16,
+ [8416] = 17,
+ [8418] = 18,
+ [8432] = 19,
+ [8433] = 20,
+ [8434] = 21,
+ [8435] = 22,
+ [8448] = 0,
+ [8449] = 1,
+ [8455] = 18,
+ [8457] = 19,
+ [8459] = 20,
+ [8492] = 2,
+ [8493] = 21,
+ [8494] = 3,
+ [8495] = 22,
+ [8496] = 4,
+ [8497] = 23,
+ [8498] = 5,
+ [8499] = 24,
+ [8500] = 6,
+ [8501] = 25,
+ [8502] = 7,
+ [8503] = 26,
+ [8504] = 8,
+ [8505] = 27,
+ [8506] = 9,
+ [8507] = 28,
+ [8540] = 10,
+ [8542] = 11,
+ [8544] = 12,
+ [8546] = 13,
+ [8560] = 14,
+ [8561] = 15,
+ [8562] = 16,
+ [8563] = 17,
+ [8576] = 0,
+ [8577] = 1,
+ [8583] = 20,
+ [8585] = 21,
+ [8587] = 22,
+ [8600] = 2,
+ [8602] = 3,
+ [8604] = 4,
+ [8606] = 5,
+ [8608] = 6,
+ [8610] = 7,
+ [8612] = 8,
+ [8614] = 9,
+ [8616] = 10,
+ [8618] = 11,
+ [8621] = 23,
+ [8623] = 24,
+ [8625] = 25,
+ [8627] = 26,
+ [8629] = 27,
+ [8631] = 28,
+ [8633] = 29,
+ [8635] = 30,
+ [8668] = 12,
+ [8670] = 13,
+ [8672] = 14,
+ [8674] = 15,
+ [8688] = 16,
+ [8689] = 17,
+ [8690] = 18,
+ [8691] = 19,
+ [8704] = 0,
+ [8705] = 1,
+ [8711] = 18,
+ [8713] = 19,
+ [8715] = 20,
+ [8729] = 21,
+ [8731] = 22,
+ [8733] = 23,
+ [8735] = 24,
+ [8737] = 25,
+ [8739] = 26,
+ [8741] = 27,
+ [8743] = 28,
+ [8745] = 29,
+ [8747] = 30,
+ [8748] = 2,
+ [8750] = 3,
+ [8752] = 4,
+ [8754] = 5,
+ [8756] = 6,
+ [8758] = 7,
+ [8760] = 8,
+ [8762] = 9,
+ [8796] = 10,
+ [8798] = 11,
+ [8800] = 12,
+ [8802] = 13,
+ [8816] = 14,
+ [8817] = 15,
+ [8818] = 16,
+ [8819] = 17,
+ [8832] = 0,
+ [8833] = 1,
+ [8839] = 20,
+ [8841] = 21,
+ [8843] = 22,
+ [8856] = 2,
+ [8857] = 23,
+ [8858] = 3,
+ [8859] = 24,
+ [8860] = 4,
+ [8861] = 25,
+ [8862] = 5,
+ [8863] = 26,
+ [8864] = 6,
+ [8865] = 27,
+ [8866] = 7,
+ [8867] = 28,
+ [8868] = 8,
+ [8869] = 29,
+ [8870] = 9,
+ [8871] = 30,
+ [8872] = 10,
+ [8873] = 31,
+ [8874] = 11,
+ [8875] = 32,
+ [8924] = 12,
+ [8926] = 13,
+ [8928] = 14,
+ [8930] = 15,
+ [8944] = 16,
+ [8945] = 17,
+ [8946] = 18,
+ [8947] = 19,
+ [8960] = 0,
+ [8961] = 1,
+ [8967] = 18,
+ [8969] = 19,
+ [8971] = 20,
+ [9004] = 2,
+ [9005] = 21,
+ [9006] = 3,
+ [9007] = 22,
+ [9008] = 4,
+ [9009] = 23,
+ [9010] = 5,
+ [9011] = 24,
+ [9012] = 6,
+ [9013] = 25,
+ [9014] = 7,
+ [9015] = 26,
+ [9016] = 8,
+ [9017] = 27,
+ [9018] = 9,
+ [9019] = 28,
+ [9035] = 29,
+ [9037] = 30,
+ [9039] = 31,
+ [9041] = 32,
+ [9043] = 33,
+ [9045] = 34,
+ [9047] = 35,
+ [9049] = 36,
+ [9051] = 37,
+ [9052] = 10,
+ [9054] = 11,
+ [9056] = 12,
+ [9058] = 13,
+ [9072] = 14,
+ [9073] = 15,
+ [9074] = 16,
+ [9075] = 17,
+ [9088] = 0,
+ [9089] = 1,
+ [9095] = 20,
+ [9097] = 21,
+ [9099] = 22,
+ [9112] = 2,
+ [9114] = 3,
+ [9116] = 4,
+ [9118] = 5,
+ [9120] = 6,
+ [9122] = 7,
+ [9124] = 8,
+ [9126] = 9,
+ [9128] = 10,
+ [9130] = 11,
+ [9133] = 23,
+ [9135] = 24,
+ [9137] = 25,
+ [9139] = 26,
+ [9141] = 27,
+ [9143] = 28,
+ [9145] = 29,
+ [9147] = 30,
+ [9163] = 31,
+ [9165] = 32,
+ [9167] = 33,
+ [9169] = 34,
+ [9171] = 35,
+ [9173] = 36,
+ [9175] = 37,
+ [9177] = 38,
+ [9179] = 39,
+ [9180] = 12,
+ [9182] = 13,
+ [9184] = 14,
+ [9186] = 15,
+ [9200] = 16,
+ [9201] = 17,
+ [9202] = 18,
+ [9203] = 19,
+ [9216] = 0,
+ [9217] = 1,
+ [9223] = 18,
+ [9225] = 19,
+ [9227] = 20,
+ [9241] = 21,
+ [9243] = 22,
+ [9245] = 23,
+ [9247] = 24,
+ [9249] = 25,
+ [9251] = 26,
+ [9253] = 27,
+ [9255] = 28,
+ [9257] = 29,
+ [9259] = 30,
+ [9260] = 2,
+ [9262] = 3,
+ [9264] = 4,
+ [9266] = 5,
+ [9268] = 6,
+ [9270] = 7,
+ [9272] = 8,
+ [9274] = 9,
+ [9291] = 31,
+ [9293] = 32,
+ [9295] = 33,
+ [9297] = 34,
+ [9299] = 35,
+ [9301] = 36,
+ [9303] = 37,
+ [9305] = 38,
+ [9307] = 39,
+ [9308] = 10,
+ [9310] = 11,
+ [9312] = 12,
+ [9314] = 13,
+ [9328] = 14,
+ [9329] = 15,
+ [9330] = 16,
+ [9331] = 17,
+ [9344] = 0,
+ [9345] = 1,
+ [9351] = 20,
+ [9353] = 21,
+ [9355] = 22,
+ [9368] = 2,
+ [9369] = 23,
+ [9370] = 3,
+ [9371] = 24,
+ [9372] = 4,
+ [9373] = 25,
+ [9374] = 5,
+ [9375] = 26,
+ [9376] = 6,
+ [9377] = 27,
+ [9378] = 7,
+ [9379] = 28,
+ [9380] = 8,
+ [9381] = 29,
+ [9382] = 9,
+ [9383] = 30,
+ [9384] = 10,
+ [9385] = 31,
+ [9386] = 11,
+ [9387] = 32,
+ [9419] = 33,
+ [9421] = 34,
+ [9423] = 35,
+ [9425] = 36,
+ [9427] = 37,
+ [9429] = 38,
+ [9431] = 39,
+ [9433] = 40,
+ [9435] = 41,
+ [9436] = 12,
+ [9438] = 13,
+ [9440] = 14,
+ [9442] = 15,
+ [9456] = 16,
+ [9457] = 17,
+ [9458] = 18,
+ [9459] = 19,
+ [9472] = 0,
+ [9473] = 1,
+ [9479] = 18,
+ [9481] = 19,
+ [9483] = 20,
+ [9516] = 2,
+ [9517] = 21,
+ [9518] = 3,
+ [9519] = 22,
+ [9520] = 4,
+ [9521] = 23,
+ [9522] = 5,
+ [9523] = 24,
+ [9524] = 6,
+ [9525] = 25,
+ [9526] = 7,
+ [9527] = 26,
+ [9528] = 8,
+ [9529] = 27,
+ [9530] = 9,
+ [9531] = 28,
+ [9564] = 10,
+ [9565] = 29,
+ [9566] = 11,
+ [9567] = 30,
+ [9568] = 12,
+ [9569] = 31,
+ [9570] = 13,
+ [9571] = 32,
+ [9584] = 14,
+ [9585] = 15,
+ [9586] = 16,
+ [9587] = 17,
+ [9600] = 0,
+ [9601] = 1,
+ [9607] = 20,
+ [9609] = 21,
+ [9611] = 22,
+ [9624] = 2,
+ [9626] = 3,
+ [9628] = 4,
+ [9630] = 5,
+ [9632] = 6,
+ [9634] = 7,
+ [9636] = 8,
+ [9638] = 9,
+ [9640] = 10,
+ [9642] = 11,
+ [9645] = 23,
+ [9647] = 24,
+ [9649] = 25,
+ [9651] = 26,
+ [9653] = 27,
+ [9655] = 28,
+ [9657] = 29,
+ [9659] = 30,
+ [9692] = 12,
+ [9693] = 31,
+ [9694] = 13,
+ [9695] = 32,
+ [9696] = 14,
+ [9697] = 33,
+ [9698] = 15,
+ [9699] = 34,
+ [9712] = 16,
+ [9713] = 17,
+ [9714] = 18,
+ [9715] = 19,
+ [9728] = 0,
+ [9729] = 1,
+ [9735] = 18,
+ [9737] = 19,
+ [9739] = 20,
+ [9753] = 21,
+ [9755] = 22,
+ [9757] = 23,
+ [9759] = 24,
+ [9761] = 25,
+ [9763] = 26,
+ [9765] = 27,
+ [9767] = 28,
+ [9769] = 29,
+ [9771] = 30,
+ [9772] = 2,
+ [9774] = 3,
+ [9776] = 4,
+ [9778] = 5,
+ [9780] = 6,
+ [9782] = 7,
+ [9784] = 8,
+ [9786] = 9,
+ [9820] = 10,
+ [9821] = 31,
+ [9822] = 11,
+ [9823] = 32,
+ [9824] = 12,
+ [9825] = 33,
+ [9826] = 13,
+ [9827] = 34,
+ [9840] = 14,
+ [9841] = 15,
+ [9842] = 16,
+ [9843] = 17,
+ [9856] = 0,
+ [9857] = 1,
+ [9863] = 20,
+ [9865] = 21,
+ [9867] = 22,
+ [9880] = 2,
+ [9881] = 23,
+ [9882] = 3,
+ [9883] = 24,
+ [9884] = 4,
+ [9885] = 25,
+ [9886] = 5,
+ [9887] = 26,
+ [9888] = 6,
+ [9889] = 27,
+ [9890] = 7,
+ [9891] = 28,
+ [9892] = 8,
+ [9893] = 29,
+ [9894] = 9,
+ [9895] = 30,
+ [9896] = 10,
+ [9897] = 31,
+ [9898] = 11,
+ [9899] = 32,
+ [9948] = 12,
+ [9949] = 33,
+ [9950] = 13,
+ [9951] = 34,
+ [9952] = 14,
+ [9953] = 35,
+ [9954] = 15,
+ [9955] = 36,
+ [9968] = 16,
+ [9969] = 17,
+ [9970] = 18,
+ [9971] = 19,
+ [9984] = 0,
+ [9985] = 1,
+ [9991] = 18,
+ [9993] = 19,
+ [9995] = 20,
+ [9999] = 31,
+ [10001] = 32,
+ [10003] = 33,
+ [10005] = 34,
+ [10007] = 35,
+ [10009] = 21,
+ [10011] = 22,
+ [10013] = 23,
+ [10015] = 24,
+ [10017] = 25,
+ [10019] = 26,
+ [10021] = 27,
+ [10023] = 28,
+ [10025] = 29,
+ [10027] = 30,
+ [10028] = 2,
+ [10030] = 3,
+ [10032] = 4,
+ [10034] = 5,
+ [10036] = 6,
+ [10038] = 7,
+ [10040] = 8,
+ [10042] = 9,
+ [10076] = 10,
+ [10078] = 11,
+ [10080] = 12,
+ [10082] = 13,
+ [10096] = 14,
+ [10097] = 15,
+ [10098] = 16,
+ [10099] = 17,
+ [10112] = 0,
+ [10113] = 1,
+ [10119] = 20,
+ [10121] = 21,
+ [10123] = 22,
+ [10127] = 33,
+ [10129] = 34,
+ [10131] = 35,
+ [10133] = 36,
+ [10135] = 37,
+ [10136] = 2,
+ [10137] = 23,
+ [10138] = 3,
+ [10139] = 24,
+ [10140] = 4,
+ [10141] = 25,
+ [10142] = 5,
+ [10143] = 26,
+ [10144] = 6,
+ [10145] = 27,
+ [10146] = 7,
+ [10147] = 28,
+ [10148] = 8,
+ [10149] = 29,
+ [10150] = 9,
+ [10151] = 30,
+ [10152] = 10,
+ [10153] = 31,
+ [10154] = 11,
+ [10155] = 32,
+ [10204] = 12,
+ [10206] = 13,
+ [10208] = 14,
+ [10210] = 15,
+ [10224] = 16,
+ [10225] = 17,
+ [10226] = 18,
+ [10227] = 19,
+ [12288] = 0,
+ [12289] = 1,
+ [12294] = 2,
+ [12296] = 3,
+ [12298] = 4,
+ [12332] = 5,
+ [12334] = 6,
+ [12336] = 7,
+ [12338] = 8,
+ [12340] = 9,
+ [12342] = 10,
+ [12344] = 11,
+ [12346] = 12,
+ [12416] = 0,
+ [12417] = 1,
+ [12422] = 2,
+ [12424] = 3,
+ [12426] = 4,
+ [12440] = 5,
+ [12442] = 6,
+ [12444] = 7,
+ [12446] = 8,
+ [12448] = 9,
+ [12450] = 10,
+ [12452] = 11,
+ [12454] = 12,
+ [12456] = 13,
+ [12458] = 14,
+ [12544] = 0,
+ [12545] = 1,
+ [12550] = 2,
+ [12552] = 3,
+ [12554] = 4,
+ [12588] = 8,
+ [12590] = 9,
+ [12592] = 10,
+ [12594] = 11,
+ [12596] = 12,
+ [12598] = 13,
+ [12600] = 14,
+ [12602] = 15,
+ [12644] = 5,
+ [12648] = 6,
+ [12652] = 7,
+ [12672] = 0,
+ [12673] = 1,
+ [12678] = 2,
+ [12680] = 3,
+ [12682] = 4,
+ [12696] = 8,
+ [12698] = 9,
+ [12700] = 10,
+ [12702] = 11,
+ [12704] = 12,
+ [12706] = 13,
+ [12708] = 14,
+ [12710] = 15,
+ [12712] = 16,
+ [12714] = 17,
+ [12772] = 5,
+ [12776] = 6,
+ [12780] = 7,
+ [12800] = 0,
+ [12801] = 1,
+ [12806] = 2,
+ [12808] = 3,
+ [12810] = 4,
+ [12844] = 5,
+ [12846] = 6,
+ [12848] = 7,
+ [12850] = 8,
+ [12852] = 9,
+ [12854] = 10,
+ [12856] = 11,
+ [12858] = 12,
+ [12874] = 13,
+ [12876] = 14,
+ [12878] = 15,
+ [12880] = 16,
+ [12882] = 17,
+ [12884] = 18,
+ [12886] = 19,
+ [12888] = 20,
+ [12890] = 21,
+ [12928] = 0,
+ [12929] = 1,
+ [12934] = 2,
+ [12936] = 3,
+ [12938] = 4,
+ [12952] = 5,
+ [12954] = 6,
+ [12956] = 7,
+ [12958] = 8,
+ [12960] = 9,
+ [12962] = 10,
+ [12964] = 11,
+ [12966] = 12,
+ [12968] = 13,
+ [12970] = 14,
+ [13002] = 15,
+ [13004] = 16,
+ [13006] = 17,
+ [13008] = 18,
+ [13010] = 19,
+ [13012] = 20,
+ [13014] = 21,
+ [13016] = 22,
+ [13018] = 23,
+ [13056] = 0,
+ [13057] = 1,
+ [13062] = 2,
+ [13064] = 3,
+ [13066] = 4,
+ [13100] = 5,
+ [13102] = 6,
+ [13104] = 7,
+ [13106] = 8,
+ [13108] = 9,
+ [13110] = 10,
+ [13112] = 11,
+ [13114] = 12,
+ [13148] = 13,
+ [13150] = 14,
+ [13152] = 15,
+ [13154] = 16,
+ [13184] = 0,
+ [13185] = 1,
+ [13190] = 2,
+ [13192] = 3,
+ [13194] = 4,
+ [13208] = 5,
+ [13210] = 6,
+ [13212] = 7,
+ [13214] = 8,
+ [13216] = 9,
+ [13218] = 10,
+ [13220] = 11,
+ [13222] = 12,
+ [13224] = 13,
+ [13226] = 14,
+ [13276] = 15,
+ [13278] = 16,
+ [13280] = 17,
+ [13282] = 18,
+ [13312] = 0,
+ [13313] = 1,
+ [13318] = 2,
+ [13320] = 3,
+ [13322] = 4,
+ [13356] = 8,
+ [13358] = 9,
+ [13360] = 10,
+ [13362] = 11,
+ [13364] = 12,
+ [13366] = 13,
+ [13368] = 14,
+ [13370] = 15,
+ [13386] = 16,
+ [13388] = 17,
+ [13390] = 18,
+ [13392] = 19,
+ [13394] = 20,
+ [13396] = 21,
+ [13398] = 22,
+ [13400] = 23,
+ [13402] = 24,
+ [13412] = 5,
+ [13416] = 6,
+ [13420] = 7,
+ [13440] = 0,
+ [13441] = 1,
+ [13446] = 2,
+ [13448] = 3,
+ [13450] = 4,
+ [13464] = 8,
+ [13466] = 9,
+ [13468] = 10,
+ [13470] = 11,
+ [13472] = 12,
+ [13474] = 13,
+ [13476] = 14,
+ [13478] = 15,
+ [13480] = 16,
+ [13482] = 17,
+ [13514] = 18,
+ [13516] = 19,
+ [13518] = 20,
+ [13520] = 21,
+ [13522] = 22,
+ [13524] = 23,
+ [13526] = 24,
+ [13528] = 25,
+ [13530] = 26,
+ [13540] = 5,
+ [13544] = 6,
+ [13548] = 7,
+ [13568] = 0,
+ [13569] = 1,
+ [13574] = 2,
+ [13576] = 3,
+ [13578] = 4,
+ [13612] = 8,
+ [13614] = 9,
+ [13616] = 10,
+ [13618] = 11,
+ [13620] = 12,
+ [13622] = 13,
+ [13624] = 14,
+ [13626] = 15,
+ [13660] = 16,
+ [13662] = 17,
+ [13664] = 18,
+ [13666] = 19,
+ [13668] = 5,
+ [13672] = 6,
+ [13676] = 7,
+ [13696] = 0,
+ [13697] = 1,
+ [13702] = 2,
+ [13704] = 3,
+ [13706] = 4,
+ [13720] = 8,
+ [13722] = 9,
+ [13724] = 10,
+ [13726] = 11,
+ [13728] = 12,
+ [13730] = 13,
+ [13732] = 14,
+ [13734] = 15,
+ [13736] = 16,
+ [13738] = 17,
+ [13788] = 18,
+ [13790] = 19,
+ [13792] = 20,
+ [13794] = 21,
+ [13796] = 5,
+ [13800] = 6,
+ [13804] = 7
};
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 8869ab1c33..9d4ea8b422 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -15,7 +13,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 5,
+ .num_tbls = 9,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -25,56 +23,128 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 5,
+ .num_tbls = 10,
+ .start_tbl_idx = 9,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 }
},
/* act_tid: 3, ingress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 11,
+ .num_tbls = 6,
+ .start_tbl_idx = 19,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 }
},
- /* act_tid: 4, egress */
+ /* act_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 5,
- .start_tbl_idx = 15,
+ .num_tbls = 7,
+ .start_tbl_idx = 25,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 7,
+ .cond_start_idx = 18,
.cond_nums = 0 }
},
- /* act_tid: 5, egress */
+ /* act_tid: 5, ingress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 20,
+ .num_tbls = 20,
+ .start_tbl_idx = 32,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 12,
+ .cond_start_idx = 25,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
- .start_tbl_idx = 24,
+ .num_tbls = 7,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 15,
+ .cond_start_idx = 40,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 7, egress */
+ [7] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 59,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 8, egress */
+ [8] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 15,
+ .start_tbl_idx = 65,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 9, egress */
+ [9] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 5,
+ .start_tbl_idx = 80,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 68,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 10, egress */
+ [10] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 11,
+ .start_tbl_idx = 85,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 71,
.cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
+ { /* act_tid: 1, , table: control.meter_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 1,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 1, , table: shared_mirror_record.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
@@ -83,20 +153,31 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 0,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 0,
- .blob_key_bit_size = 1,
- .key_bit_size = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
.key_num_fields = 1,
- .ident_start_idx = 0,
+ .ident_start_idx = 1,
.ident_nums = 1
},
+ { /* act_tid: 1, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -107,7 +188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 1,
+ .cond_start_idx = 4,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -124,10 +205,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 2,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
@@ -137,6 +218,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 47
},
+ { /* act_tid: 1, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 6,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 48,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
@@ -147,13 +248,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 48,
+ .result_start_idx = 95,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -167,24 +268,88 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 112,
.result_bit_size = 64,
.result_num_fields = 13
},
- { /* act_tid: 2, , table: control.0 */
+ { /* act_tid: 2, , table: control.delete_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 2, , table: control.mirror_del_exist_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 2, , table: control.mirror_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 2, , table: control.create */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -199,14 +364,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 12,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 78,
+ .result_start_idx = 125,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -220,14 +385,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 3,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 83,
+ .result_start_idx = 130,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -241,14 +406,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 84,
+ .result_start_idx = 131,
.result_bit_size = 64,
.result_num_fields = 13,
.encap_num_fields = 0
@@ -263,13 +428,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 97,
+ .result_start_idx = 144,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -283,19 +448,54 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1,
- .blob_key_bit_size = 1,
- .key_bit_size = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC,
+ .key_start_idx = 3,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
.key_num_fields = 1,
- .result_start_idx = 102,
+ .result_start_idx = 149,
.result_bit_size = 36,
.result_num_fields = 2
},
+ { /* act_tid: 3, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 3,
+ .ident_nums = 1
+ },
+ { /* act_tid: 3, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -306,12 +506,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 104,
+ .result_start_idx = 151,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -325,12 +525,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 105,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -345,12 +545,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 152,
+ .result_start_idx = 199,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -365,386 +565,564 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 199,
+ .result_start_idx = 246,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 5,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 4,
+ .ident_nums = 1
+ },
+ { /* act_tid: 4, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 19,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
+ .cond_start_idx = 20,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 216,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 263,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 4, , table: int_vtag_encap_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ { /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
+ .cond_start_idx = 21,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 217,
+ .result_start_idx = 264,
.result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .result_num_fields = 0
},
- { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ { /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 22,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 228,
+ .result_start_idx = 264,
.result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .result_num_fields = 0
},
- { /* act_tid: 4, , table: int_full_act_record.0 */
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
- .cond_start_idx = 10,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 275,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 264,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0
},
- { /* act_tid: 4, , table: int_compact_act_record.0 */
+ { /* act_tid: 4, , table: int_compact_act_record.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 25,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 292,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 277,
.result_bit_size = 64,
- .result_num_fields = 13
+ .result_num_fields = 13,
+ .encap_num_fields = 0
},
- { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ { /* act_tid: 5, , table: control.create_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 11,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 27,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 305,
- .result_bit_size = 64,
- .result_num_fields = 1
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
+ .ident_nums = 0
},
- { /* act_tid: 5, , table: mod_record.ing_ttl */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ { /* act_tid: 5, , table: control.shared_meter_profile_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 28,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 306,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ { /* act_tid: 5, , table: meter_profile_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 353,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 290,
+ .result_bit_size = 65,
+ .result_num_fields = 11
},
- { /* act_tid: 5, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 400,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 7,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .result_start_idx = 301,
+ .result_bit_size = 42,
+ .result_num_fields = 2
},
- { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 29,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 417,
- .result_bit_size = 64,
- .result_num_fields = 1
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 8,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
+ .ident_nums = 0
+ },
+ { /* act_tid: 5, , table: control.meter_created_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* act_tid: 6, , table: source_property_cache.rd */
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 31,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2,
- .blob_key_bit_size = 80,
- .key_bit_size = 80,
- .key_num_fields = 2,
- .ident_start_idx = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 9,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
.ident_nums = 1
},
- { /* act_tid: 6, , table: control.0 */
+ { /* act_tid: 5, , table: control.shared_meter_profile_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 17,
+ .cond_start_idx = 31,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ { /* act_tid: 5, , table: meter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_type = TF_TBL_TYPE_METER_INST,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 32,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .record_size = 16,
- .result_start_idx = 418,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 3
+ .result_start_idx = 303,
+ .result_bit_size = 64,
+ .result_num_fields = 5
},
- { /* act_tid: 6, , table: source_property_cache.wr */
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 19,
+ .cond_start_idx = 32,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 4,
- .blob_key_bit_size = 80,
- .key_bit_size = 80,
- .key_num_fields = 2,
- .result_start_idx = 421,
- .result_bit_size = 48,
- .result_num_fields = 2
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 10,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .result_start_idx = 308,
+ .result_bit_size = 74,
+ .result_num_fields = 3
},
- { /* act_tid: 6, , table: sp_smac_ipv6.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ { /* act_tid: 5, , table: control.delete_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 19,
+ .cond_start_idx = 32,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 32,
- .result_start_idx = 423,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 3
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 20,
- .cond_nums = 2 },
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 6,
- .blob_key_bit_size = 136,
- .key_bit_size = 136,
- .key_num_fields = 5,
- .ident_start_idx = 2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 6,
.ident_nums = 1
},
- { /* act_tid: 6, , table: control.0 */
+ { /* act_tid: 5, , table: control.mtr_prof_ref_cnt_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 22,
+ .cond_start_idx = 34,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
- },
- { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 23,
- .cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 426,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 30
- },
- { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 25,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 11,
- .blob_key_bit_size = 136,
- .key_bit_size = 136,
- .key_num_fields = 5,
- .result_start_idx = 456,
- .result_bit_size = 48,
- .result_num_fields = 2
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 12,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 7,
+ .ident_nums = 1
+ },
+ { /* act_tid: 5, , table: control.shared_mtr_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 5, , table: control.update_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 13,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 8,
+ .ident_nums = 1
},
- { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ { /* act_tid: 5, , table: meter_tbl.update_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ident_start_idx = 9,
+ .ident_nums = 3,
+ .result_bit_size = 64
+ },
+ { /* act_tid: 5, , table: meter_tbl.update_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 40,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 311,
+ .result_bit_size = 64,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 6, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 14,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 12,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 316,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
@@ -752,15 +1130,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 25,
- .cond_nums = 2 },
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 458,
+ .result_start_idx = 317,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 30
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 6, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 328,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -770,516 +1168,4512 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
- .cond_nums = 0 },
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 488,
+ .result_start_idx = 375,
.result_bit_size = 128,
.result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_execute: act_tid: 1, shared_mirror_record.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
- },
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- },
- /* cond_execute: act_tid: 1, mod_record.ing_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
- /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 6, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 392,
+ .result_bit_size = 64,
+ .result_num_fields = 13
},
- /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 7, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 15,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 1
},
- /* cond_execute: act_tid: 3, mod_record.ing_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ { /* act_tid: 7, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ { /* act_tid: 7, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 405,
+ .result_bit_size = 64,
+ .result_num_fields = 1
},
- /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 7, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 406,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
- /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ { /* act_tid: 7, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 453,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 7, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 500,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 8, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 16,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 14,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 8, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 517,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 8, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 55,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 17,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 15,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 56,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 8, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 57,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .record_size = 16,
+ .result_start_idx = 518,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 8, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 58,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 19,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 521,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 8, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 58,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 523,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 59,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 21,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: mod_record.ing_l2write */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 61,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 526,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 8, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 63,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 64,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 573,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 66,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 26,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 603,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 66,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 605,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 8, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 68,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 635,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 9, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 68,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 31,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 17,
+ .ident_nums = 1
+ },
+ { /* act_tid: 9, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 69,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 70,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 652,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 9, , table: mod_record.vf_2_vf */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 71,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 653,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 9, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 71,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 700,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 10, , table: control.delete_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 71,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 72,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 32,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 18,
+ .ident_nums = 1
+ },
+ { /* act_tid: 10, , table: control.mirror_del_exist_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 72,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 10, , table: control.mirror_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 73,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 10, , table: control.create */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 74,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 10, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 74,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 717,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 10, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 74,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 722,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 10, , table: mod_record.vf_2_vf */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 723,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 10, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 770,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 10, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 787,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 10, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC,
+ .key_start_idx = 33,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .result_start_idx = 792,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_meter_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER
+ },
+ /* cond_execute: act_tid: 1, control.meter_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ /* cond_execute: act_tid: 2, control.delete_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 2, control.mirror_del_exist_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 2, control.mirror_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 3, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 4, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_rss_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_queue_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ /* cond_execute: act_tid: 4, int_compact_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 5, control.create_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_UPDATE
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 5, meter_profile_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE
+ },
+ /* cond_execute: act_tid: 5, control.shared_meter_profile_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, control.meter_created_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, control.shared_meter_profile_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, control.delete_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 5, meter_profile_tbl_cache.del_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE
+ },
+ /* cond_execute: act_tid: 5, control.mtr_prof_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.del_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, control.shared_mtr_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd_update */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, meter_tbl.update_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE
+ },
+ /* cond_execute: act_tid: 6, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 6, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 6, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 7, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 7, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 7, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 7, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 7, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 8, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 8, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 8, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 8, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 8, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 8, mod_record.ing_l2write */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ /* cond_execute: act_tid: 8, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 8, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 9, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 9, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 9, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 10, control.delete_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 10, control.mirror_del_exist_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 10, control.mirror_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 10, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER & 0xff}
+ }
+ },
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ },
+ /* act_tid: 3, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 4, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 7, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 9, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 10, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_METER & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_METER & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RSS_VNIC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RSS_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
- /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 4, int_full_act_record.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, mod_record.ing_ttl */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ /* act_tid: 4, , table: int_compact_act_record.1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, source_property_cache.rd */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
- /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
- /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
- /* cond_execute: act_tid: 6, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
- /* act_tid: 1, , table: shared_mirror_record.rd */
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: meter_profile_tbl.0 */
{
- .field_info_mask = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
- }
+ .description = "cf",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF & 0xff}
+ },
+ {
+ .description = "pm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM & 0xff}
+ },
+ {
+ .description = "rfc2698",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 & 0xff}
+ },
+ {
+ .description = "cbsm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM & 0xff}
+ },
+ {
+ .description = "ebsm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM & 0xff}
+ },
+ {
+ .description = "cbnd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND & 0xff}
+ },
+ {
+ .description = "ebnd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND & 0xff}
+ },
+ {
+ .description = "cbs",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS & 0xff}
+ },
+ {
+ .description = "ebs",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS & 0xff}
+ },
+ {
+ .description = "cir",
+ .field_bit_size = 17,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR & 0xff}
+ },
+ {
+ .description = "eir",
+ .field_bit_size = 17,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR & 0xff}
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "meter_profile_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
+ },
+ /* act_tid: 5, , table: meter_tbl.0 */
+ {
+ .description = "bkt_c",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
+ },
+ {
+ .description = "bkt_e",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
+ },
+ {
+ .description = "mtr_val",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL & 0xff}
+ },
+ {
+ .description = "ecn_rmp_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN & 0xff}
+ },
+ {
+ .description = "meter_profile",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "meter_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff}
},
- /* act_tid: 2, , table: shared_mirror_record.wr */
{
- .field_info_mask = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
- }
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
},
- /* act_tid: 6, , table: source_property_cache.rd */
+ /* act_tid: 5, , table: meter_tbl.update_wr */
{
- .field_info_mask = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- }
+ .description = "bkt_c",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
},
{
- .field_info_mask = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- }
+ .description = "bkt_e",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
},
- /* act_tid: 6, , table: source_property_cache.wr */
{
- .field_info_mask = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- }
+ .description = "mtr_val",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr3 = {
+ (BNXT_ULP_RF_IDX_RF_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RF_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- }
+ .description = "ecn_rmp_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr3 = {
+ (BNXT_ULP_RF_IDX_RF_1 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RF_1 & 0xff}
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
{
- .field_info_mask = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
- }
+ .description = "meter_profile",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
},
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
{
- .field_info_mask = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
- }
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: int_vtag_encap_record.0 */
{
- .field_info_mask = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
- }
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- }
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- }
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
{
- .field_info_mask = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
- }
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
- }
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
- }
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- }
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .field_info_mask = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "vtag_de",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 6, , table: mod_record.dec_ttl_egr */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -1462,8 +5856,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
},
{
.description = "ttl_il3_dec",
@@ -1471,8 +5865,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
},
{
.description = "ttl_tl3_rdir",
@@ -1521,211 +5915,63 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- {
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- /* act_tid: 1, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "decap_func",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_DECAP_FUNC_NONE}
- },
- {
- .description = "meter",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "stats_op",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "use_default",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "mirror",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr2 = {
- (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
- .description = "drop",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
- .description = "hit",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* act_tid: 1, , table: int_compact_act_record.0 */
- {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1734,23 +5980,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "decap_func",
.field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_DECAP_FUNC_NONE}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "meter",
@@ -1781,8 +6012,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -1819,21 +6050,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "vlan_del_rpt",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "drop",
@@ -1860,49 +6078,11 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: mirror_tbl.alloc */
- {
- .description = "act_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "reserved",
- .field_bit_size = 13,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ignore_drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "copy_ing_or_egr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "enable",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* act_tid: 2, , table: int_flow_counter_tbl.0 */
- {
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: int_compact_act_record.0 */
+ /* act_tid: 6, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1944,8 +6124,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -1956,109 +6136,70 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "mirror",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "cond_copy",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: mirror_tbl.wr */
- {
- .description = "act_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 13,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ignore_drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "copy_ing_or_egr",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enable",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- 1}
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
- /* act_tid: 2, , table: shared_mirror_record.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror_id",
- .field_bit_size = 4,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 7, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 3, , table: mod_record.ing_ttl */
+ /* act_tid: 7, , table: mod_record.ing_ttl */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -2112,14 +6253,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -2340,12 +6507,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -2437,7 +6634,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ /* act_tid: 7, , table: mod_record.ing_no_ttl */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -2489,14 +6686,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -2704,12 +6927,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -2801,7 +7054,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 3, , table: int_full_act_record.0 */
+ /* act_tid: 7, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -2851,9 +7104,16 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- 1}
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
},
{
.description = "stats_ptr",
@@ -2870,8 +7130,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -2883,7 +7143,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "mirror",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
{
.description = "cond_copy",
@@ -2917,94 +7180,83 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
- /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 8, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ /* act_tid: 8, , table: sp_smac_ipv4.0 */
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
- },
- {
- .description = "ecv_custom_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "ecv_l2_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ecv_l3_type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "reserved",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 8, , table: source_property_cache.wr */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "vtag_tpid",
+ .description = "sp_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
},
+ /* act_tid: 8, , table: sp_smac_ipv6.0 */
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
- .description = "vtag_de",
- .field_bit_size = 1,
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "reserved",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ /* act_tid: 8, , table: mod_record.ing_l2write */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -3039,9 +7291,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tun_md_en",
@@ -3058,14 +7308,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -3166,50 +7442,37 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "alt_pfid",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "alt_vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_rsvd",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ttl_tl3_dec",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_il3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "tun_new_prot",
@@ -3234,12 +7497,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -3271,622 +7564,730 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 4, , table: int_full_act_record.0 */
+ /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
.field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
},
{
- .description = "mod_rec_ptr",
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .description = "rsvd1",
+ .description = "enc_ipv4_frag",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .description = "rsvd0",
+ .description = "enc_ipv4_ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "stats_op",
- .field_bit_size = 1,
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
},
{
- .description = "stats_ptr",
+ .description = "enc_udp_dport",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
},
{
- .description = "use_default",
- .field_bit_size = 1,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "drop",
- .field_bit_size = 1,
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
+ /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */
{
- .description = "hit",
+ .description = "ecv_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- /* act_tid: 4, , table: int_compact_act_record.0 */
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_THOR_SYM_ECV_VALID_YES}
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
- .description = "stats_op",
+ .description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ ULP_THOR_SYM_ECV_L2_EN_YES}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "use_default",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 5, , table: mod_record.ing_ttl */
{
- .description = "metadata_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rem_ovlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rem_ivlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rep_add_ivlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rep_add_ovlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "ttl_update",
- .field_bit_size = 1,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
},
{
- .description = "tun_md_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
},
{
- .description = "l2_dmac_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
},
{
- .description = "l2_smac_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
},
{
- .description = "l3_sip_ipv6_en",
- .field_bit_size = 1,
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
},
{
- .description = "l3_dip_ipv6_en",
- .field_bit_size = 1,
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
},
{
- .description = "l3_sip_ipv4_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
},
{
- .description = "l3_dip_ipv4_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
},
{
- .description = "l4_sport_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
},
{
- .description = "l4_dport_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 8, , table: int_full_act_record.0 */
{
- .description = "metadata_data",
+ .description = "sp_rec_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_rsvd",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_op",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_prof",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
},
{
- .description = "ivlan_tpid",
+ .description = "encap_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_de",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
- .description = "ovlan_tpid",
+ .description = "mod_rec_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_de",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
- .description = "alt_pfid",
- .field_bit_size = 4,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_vid",
- .field_bit_size = 12,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_rsvd",
- .field_bit_size = 12,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_dec",
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ 1}
},
{
- .description = "ttl_il3_dec",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
- .description = "ttl_tl3_rdir",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
- .description = "ttl_il3_rdir",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_new_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "tun_ex_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "tun_mv",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "reserved",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
{
- .description = "l3_sip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ 1}
},
+ /* act_tid: 9, , table: int_flow_counter_tbl.0 */
{
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ /* act_tid: 9, , table: mod_record.vf_2_vf */
{
.description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "rem_ovlan",
@@ -3957,98 +8358,55 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l3_sip_ipv4_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_ipv4_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_sport_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dport_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_data",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
.description = "metadata_rsvd",
.field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_op",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_prof",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ivlan_tpid",
@@ -4168,84 +8526,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l3_sip_ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l3_dip_ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l4_sport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l4_dport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 5, , table: int_full_act_record.0 */
+ /* act_tid: 9, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -4270,788 +8568,435 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "rsvd1",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "decap_func",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meter",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "stats_op",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
- },
- {
- .description = "vnic_or_vport",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
- },
- {
- .description = "use_default",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mirror",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "cond_copy",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* act_tid: 6, , table: int_flow_counter_tbl.0 */
- {
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: sp_smac_ipv4.0 */
- {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- },
- {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: source_property_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
- },
- /* act_tid: 6, , table: sp_smac_ipv6.0 */
- {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- },
- {
- .description = "ipv6_src_addr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
- {
- .description = "ecv_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VALID_YES}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "enc_eth_dmac",
- .field_bit_size = 48,
+ .description = "use_default",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_tag",
- .field_bit_size = 16,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
.field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_i_vlan_tag",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_i_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_ihl",
- .field_bit_size = 8,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_tos",
- .field_bit_size = 8,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
+ 1}
},
+ /* act_tid: 10, , table: mirror_tbl.alloc */
{
- .description = "enc_ipv4_pkt_id",
+ .description = "act_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_frag",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 13,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_ttl",
- .field_bit_size = 8,
+ .description = "ignore_drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_proto",
- .field_bit_size = 8,
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_daddr",
- .field_bit_size = 32,
+ .description = "enable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ 1}
},
+ /* act_tid: 10, , table: int_flow_counter_tbl.0 */
{
- .description = "enc_ipv6_vtc",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 10, , table: mod_record.vf_2_vf */
{
- .description = "enc_ipv6_zero",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "enc_ipv6_proto",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv6_ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv6_daddr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_udp_dport",
- .field_bit_size = 16,
+ .description = "ttl_update",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_flags",
- .field_bit_size = 8,
+ .description = "tun_md_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_rsvd0",
- .field_bit_size = 24,
+ .description = "reserved_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_vni",
- .field_bit_size = 24,
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_rsvd1",
- .field_bit_size = 8,
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
- .description = "ecv_valid",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_eth_dmac",
- .field_bit_size = 48,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_tag",
+ .description = "ivlan_tpid",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_o_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_i_vlan_tag",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_i_vlan_type",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_ihl",
- .field_bit_size = 8,
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_tos",
- .field_bit_size = 8,
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_pkt_id",
+ .description = "tun_ex_prot",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_frag",
+ .description = "tun_mv",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_ttl",
- .field_bit_size = 8,
+ .description = "reserved",
+ .field_bit_size = 0,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_proto",
- .field_bit_size = 8,
+ .description = "l2_dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_daddr",
- .field_bit_size = 32,
+ .description = "l2_smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_vtc",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
- },
- {
- .description = "enc_ipv6_zero",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_proto",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_daddr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_udp_sport",
+ .description = "l4_sport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_udp_dport",
+ .description = "l4_dport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- },
- {
- .description = "enc_vxlan_flags",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
- },
- {
- .description = "enc_vxlan_rsvd0",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
- },
- {
- .description = "enc_vxlan_vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- },
- {
- .description = "enc_vxlan_rsvd1",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 6, , table: int_full_act_record.0 */
+ /* act_tid: 10, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
.description = "rsvd1",
@@ -5098,10 +9043,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
.description = "use_default",
@@ -5146,10 +9091,74 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* act_tid: 10, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 10, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
};
struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ {
+ .description = "meter_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* act_tid: 1, , table: shared_mirror_record.rd */
{
.description = "mirror_id",
@@ -5157,18 +9166,121 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.ident_bit_size = 4,
.ident_bit_pos = 32
},
- /* act_tid: 6, , table: source_property_cache.rd */
+ /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 3, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 4, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
+ {
+ .description = "meter_profile_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ {
+ .description = "meter_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_tbl.update_rd */
+ {
+ .description = "ecn_rmp_en",
+ .regfile_idx = BNXT_ULP_RF_IDX_RF_1,
+ .ident_bit_size = 1,
+ .ident_bit_pos = 55
+ },
+ {
+ .description = "meter_profile",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 56
+ },
+ {
+ .description = "mtr_val",
+ .regfile_idx = BNXT_ULP_RF_IDX_RF_0,
+ .ident_bit_size = 1,
+ .ident_bit_pos = 54
+ },
+ /* act_tid: 6, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 7, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 8, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 8, , table: source_property_cache.rd */
{
.description = "sp_rec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.ident_bit_size = 16,
.ident_bit_pos = 32
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
{
.description = "enc_rec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.ident_bit_size = 16,
.ident_bit_pos = 32
+ },
+ /* act_tid: 9, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 46c0d624dc..9da14b0878 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -55,7 +53,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 25,
+ .num_tbls = 33,
.start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -123,9 +121,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.key_start_idx = 2,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.ident_start_idx = 4,
.ident_nums = 1
},
@@ -157,7 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 7,
+ .key_start_idx = 8,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -181,10 +179,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 28,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 29,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.result_start_idx = 6,
.result_bit_size = 62,
.result_num_fields = 4
@@ -214,7 +212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 33,
+ .key_start_idx = 35,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -287,7 +285,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 36,
+ .key_start_idx = 38,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -312,7 +310,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 79,
+ .key_start_idx = 81,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -332,7 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 82,
+ .key_start_idx = 84,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -354,7 +352,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
+ .key_start_idx = 198,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -425,7 +423,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 199,
+ .key_start_idx = 201,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -453,7 +451,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 242,
+ .key_start_idx = 244,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -478,7 +476,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 285,
+ .key_start_idx = 287,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -503,7 +501,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 288,
+ .key_start_idx = 290,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -528,7 +526,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 402,
+ .key_start_idx = 404,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -553,7 +551,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 516,
+ .key_start_idx = 518,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -578,7 +576,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 630,
+ .key_start_idx = 632,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -603,7 +601,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 744,
+ .key_start_idx = 746,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -628,7 +626,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 858,
+ .key_start_idx = 860,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -653,7 +651,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 972,
+ .key_start_idx = 974,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -675,7 +673,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1086,
+ .key_start_idx = 1088,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
@@ -696,7 +694,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1087,
+ .key_start_idx = 1089,
.blob_key_bit_size = 19,
.key_bit_size = 19,
.key_num_fields = 2,
@@ -731,7 +729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 1089,
+ .key_start_idx = 1091,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -755,7 +753,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1110,
+ .key_start_idx = 1112,
.blob_key_bit_size = 19,
.key_bit_size = 19,
.key_num_fields = 2,
@@ -788,10 +786,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1112,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 1114,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.ident_start_idx = 18,
.ident_nums = 1
},
@@ -823,7 +821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 1117,
+ .key_start_idx = 1120,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -847,10 +845,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1138,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 1141,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.result_start_idx = 422,
.result_bit_size = 62,
.result_num_fields = 4
@@ -880,7 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1143,
+ .key_start_idx = 1147,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -953,7 +951,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1146,
+ .key_start_idx = 1150,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -978,7 +976,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1189,
+ .key_start_idx = 1193,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -998,7 +996,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1192,
+ .key_start_idx = 1196,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1021,7 +1019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1306,
+ .key_start_idx = 1310,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1075,7 +1073,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1309,
+ .key_start_idx = 1313,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1098,7 +1096,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1352,
+ .key_start_idx = 1356,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1123,7 +1121,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1355,
+ .key_start_idx = 1359,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1145,7 +1143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1469,
+ .key_start_idx = 1473,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1177,7 +1175,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1470,
+ .key_start_idx = 1474,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1250,7 +1248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1473,
+ .key_start_idx = 1477,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1275,7 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1516,
+ .key_start_idx = 1520,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1295,7 +1293,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1519,
+ .key_start_idx = 1523,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1317,7 +1315,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1633,
+ .key_start_idx = 1637,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1371,7 +1369,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1636,
+ .key_start_idx = 1640,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1399,7 +1397,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1679,
+ .key_start_idx = 1683,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1424,7 +1422,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1722,
+ .key_start_idx = 1726,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1449,7 +1447,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1725,
+ .key_start_idx = 1729,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1474,7 +1472,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1839,
+ .key_start_idx = 1843,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1499,7 +1497,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1953,
+ .key_start_idx = 1957,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1541,13 +1539,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2067,
+ .key_start_idx = 2071,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
.result_start_idx = 967,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .result_bit_size = 153,
+ .result_num_fields = 6
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -1563,7 +1561,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2068,
+ .key_start_idx = 2072,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1600,11 +1598,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2069,
+ .key_start_idx = 2073,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 972,
+ .result_start_idx = 973,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1624,11 +1622,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2090,
+ .key_start_idx = 2094,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 978,
+ .result_start_idx = 979,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1645,7 +1643,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 982,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1662,7 +1660,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 983,
+ .result_start_idx = 984,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1682,7 +1680,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 985,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1701,13 +1699,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2091,
+ .key_start_idx = 2095,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 1001,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .result_start_idx = 1002,
+ .result_bit_size = 153,
+ .result_num_fields = 6
},
{ /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1734,7 +1732,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2092,
+ .key_start_idx = 2096,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1767,7 +1765,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 1006,
+ .result_start_idx = 1008,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1785,11 +1783,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2093,
+ .key_start_idx = 2097,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1014,
+ .result_start_idx = 1016,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1807,7 +1805,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2094,
+ .key_start_idx = 2098,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1842,11 +1840,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2095,
+ .key_start_idx = 2099,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1018,
+ .result_start_idx = 1020,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1866,11 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2116,
+ .key_start_idx = 2120,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1024,
+ .result_start_idx = 1026,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1887,7 +1885,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1028,
+ .result_start_idx = 1030,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1904,57 +1902,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1029,
+ .result_start_idx = 1031,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 51,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1030,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
- },
- { /* class_tid: 5, , table: port_table.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 51,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2117,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 1047,
- .result_bit_size = 152,
- .result_num_fields = 5
- },
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -1965,28 +1921,30 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2118,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
+ .key_start_idx = 2121,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
.ident_start_idx = 37,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.vf_0 */
+ { /* class_tid: 5, , table: control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 6,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 51,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ { /* class_tid: 5, , table: mod_record.vf_2_vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -1994,26 +1952,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 2119,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 1052,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 37,
- .ident_nums = 1
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -2021,16 +1972,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2140,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
- .result_start_idx = 1058,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1079,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
},
{ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
@@ -2044,8 +1993,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1062,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1096,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2061,52 +2011,37 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1063,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1097,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 52,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 1064,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
- },
- { /* class_tid: 5, , table: ilt_tbl.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_ILT,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1081,
- .result_bit_size = 64,
- .result_num_fields = 8
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 1098,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
@@ -2119,14 +2054,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2141,
+ .key_start_idx = 2127,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .ident_start_idx = 38,
+ .ident_start_idx = 37,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.0 */
+ { /* class_tid: 5, , table: control.vf_2_vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
@@ -2138,9 +2073,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_ILT,
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -2148,15 +2083,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 53,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 1089,
- .result_bit_size = 64,
- .result_num_fields = 8
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2128,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1105,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -2170,59 +2113,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2142,
+ .key_start_idx = 2149,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1097,
+ .result_start_idx = 1111,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 5, , table: metadata_record.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 53,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1101,
- .result_bit_size = 16,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: mod_record.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 53,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1102,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
- },
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -2232,15 +2136,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1149,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 1115,
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -2251,26 +2156,75 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2143,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
+ .key_start_idx = 2150,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
.ident_start_idx = 38,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.ing_rd_vfr */
+ { /* class_tid: 5, , table: control.prof_tcam_cache.vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 5,
+ .cond_false_goto = 10,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 53,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.drop_action */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1132,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2153,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1149,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
@@ -2288,11 +2242,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2144,
+ .key_start_idx = 2174,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1166,
+ .result_start_idx = 1155,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2311,11 +2265,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1172,
+ .result_start_idx = 1161,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: fkb_select.vf_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1267,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ { /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -2333,18 +2304,45 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2165,
+ .key_start_idx = 2195,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1278,
+ .result_start_idx = 1373,
.result_bit_size = 33,
.result_num_fields = 8
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ { /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2238,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1381,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -2355,15 +2353,183 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2208,
+ .key_start_idx = 2281,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 1389,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1396,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: em.vf_2_vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2284,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1404,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2398,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1286,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1410,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2399,
+ .blob_key_bit_size = 11,
+ .key_bit_size = 11,
+ .key_num_fields = 1,
+ .result_start_idx = 1418,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: ilt_tbl.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1422,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_2_vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1430,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1477,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_2_vf.ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -2373,17 +2539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 54,
+ .cond_start_idx = 55,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1290,
+ .result_start_idx = 1494,
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 5, , table: em.vfr.0 */
+ { /* class_tid: 5, , table: em.vfr_2_vf.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
@@ -2391,15 +2557,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 54,
+ .cond_start_idx = 55,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2209,
+ .key_start_idx = 2400,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1307,
+ .result_start_idx = 1511,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2585,7 +2751,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
/* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4
},
/* cond_execute: class_tid: 3, control.ipv6_check */
{
@@ -2651,17 +2817,22 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.0 */
+ /* cond_execute: class_tid: 5, control.vf_2_vfr.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -2798,6 +2969,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -3198,6 +3383,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
@@ -3472,30 +3671,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5809,25 +5991,22 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ (BNXT_ULP_CF_IDX_O_HAS_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_HAS_VTAG & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
@@ -6795,30 +6974,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -17936,6 +18098,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -18336,6 +18512,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
@@ -18863,8 +19053,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -21143,8 +21348,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -21432,9 +21652,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
@@ -23231,30 +23465,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -25548,30 +25765,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -26210,30 +26410,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31940,25 +32123,108 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: port_table.egr_wr */
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
@@ -32308,70 +32574,57 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
{
.field_info_mask = {
.description = "etype",
@@ -32559,13 +32812,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "metadata",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_MASK >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK & 0xff}
},
.field_info_spec = {
.description = "metadata",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
}
},
{
@@ -32573,19 +32832,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -32680,7 +32933,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_MASK >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK & 0xff}
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VF_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VF_META_VAL & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -33214,8 +33776,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
{
@@ -33292,1474 +33854,4308 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: em.vfr.0 */
- {
- .field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
+ .description = "agg_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
+ .description = "agg_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl3.df",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
+ /* class_tid: 5, , table: em.vf_2_vfr.0 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr_2_vf.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_META_FID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34770,27 +38166,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35163,10 +38630,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -35225,22 +38691,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -35264,10 +38718,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -35279,10 +38732,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -35300,10 +38752,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -35387,19 +38838,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -35461,166 +38910,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35747,7 +39037,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35771,7 +39063,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35783,7 +39077,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35801,7 +39097,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35885,13 +39183,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -36055,9 +39357,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -36081,9 +39381,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -36095,9 +39393,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -36115,9 +39411,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -36201,17 +39495,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -36256,1160 +39546,1334 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "tid.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tctxts.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tqos.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dt.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl4_opt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tqos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "l2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -37420,103 +40884,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ /* class_tid: 2, , table: fkb_select.f2_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -37841,10 +41300,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
+ 1}
},
{
.description = "tid.en",
@@ -37886,19 +41344,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ 1}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -37982,10 +41438,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37997,10 +41452,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -38018,10 +41472,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -38105,19 +41558,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -38179,24 +41630,46 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "em_key_type",
@@ -38208,27 +41681,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "pl_byp_lkup_en",
@@ -38236,7 +41701,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -38259,19 +41724,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
@@ -38294,31 +41753,18 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "opcode",
@@ -38327,18 +41773,23 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 2, , table: fkb_select.f2_wm */
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -38663,9 +42114,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tid.en",
@@ -38707,17 +42156,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38776,8 +42227,22 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -38801,9 +42266,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
.description = "l3_sip_selcmp.en",
@@ -38815,9 +42281,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
{
.description = "l3_dip_selcmp.en",
@@ -38835,9 +42302,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -38921,17 +42389,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
.description = "l4_flags.en",
@@ -38993,46 +42463,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_type",
@@ -39044,19 +42492,27 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "pl_byp_lkup_en",
@@ -39064,7 +42520,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -39087,13 +42543,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
.description = "wc_profile_id",
@@ -39116,24 +42578,22 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
.description = "data",
@@ -39145,14 +42605,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -39519,19 +42989,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 1}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -39590,22 +43058,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -39629,10 +43085,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -39644,10 +43099,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -39665,10 +43119,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -39752,19 +43205,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -39826,24 +43277,32 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "em_key_type",
@@ -39855,35 +43314,84 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
{
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
.description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -39906,19 +43414,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
@@ -39941,14 +43443,33 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "strength",
@@ -39956,7 +43477,26 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 3}
+ 1}
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "data",
@@ -39968,8 +43508,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -39980,384 +43529,625 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "phy_port",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
+ .description = "port_is_pf",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ },
+ {
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_prot.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "phy_port",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_dest.en",
+ .description = "port_is_pf",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tl3_df.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl4_l4type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: mod_record.vf_2_vfr_egr */
{
- .description = "l2_smac.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -40365,317 +44155,403 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l2_dt.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
},
{
- .description = "l3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_qos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_esp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_auth.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_dest.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_frag.en",
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_rthdr.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_hop.en",
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_df.en",
+ .description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_l3err.en",
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_loopback */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR & 0xff}
},
{
- .description = "l4_dst.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ },
+ {
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -40686,75 +44562,80 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
.description = "wc_key_id",
- .field_bit_size = 6,
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
- /* class_tid: 3, , table: profile_tcam_cache.wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -40765,156 +44646,140 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_ing */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "use_default",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: int_full_act_record.0 */
+ /* class_tid: 5, , table: int_full_act_record.drop_action */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -40975,10 +44840,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "use_default",
@@ -41008,7 +44870,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "hit",
@@ -41024,49 +44888,66 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: port_table.ing_wr_0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
},
{
.description = "ctxt_meta_prof",
@@ -41078,10 +44959,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "def_ctxt_data",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -41097,8 +44978,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 & 0xff}
},
{
.description = "parif",
@@ -41106,2052 +44987,2064 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 5, , table: fkb_select.vfr_em */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ 1}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tuntype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tflags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "terr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: port_table.egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_LOOPBACK_PARIF}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
+ /* class_tid: 5, , table: fkb_select.vf_em */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "prof_meta_mask",
- .field_bit_size = 16,
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "metadata_en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rem_ovlan",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rem_ivlan",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rep_add_ivlan",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rep_add_ovlan",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_update",
+ .description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_md_en",
+ .description = "tl4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac_en",
+ .description = "tl4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac_en",
+ .description = "tl4_opt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv6_en",
+ .description = "tl4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4_en",
+ .description = "tflags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport_en",
+ .description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dport_en",
+ .description = "tid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_data",
- .field_bit_size = 16,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_rsvd",
- .field_bit_size = 10,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_op",
- .field_bit_size = 2,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_prof",
- .field_bit_size = 4,
+ .description = "terr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
- },
- {
- .description = "ivlan_tpid",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ivlan_de",
+ .description = "l2_l2type.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_tpid",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_de",
+ .description = "l2_smac.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_pfid",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_rsvd",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_dec",
+ .description = "l2_ovd.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_il3_dec",
+ .description = "l2_ovv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_rdir",
+ .description = "l2_ovt.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_il3_rdir",
+ .description = "l2_ivp.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_new_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_ex_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_mv",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vfr_egr */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: fkb_select.vfr_em */
{
- .description = "l2_cntxt_id.en",
+ .description = "l4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "loopback.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl2_l2type.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 & 0xff}
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 & 0xff}
},
{
- .description = "tl2_ovd.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl2_ovv.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_ing */
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW}
},
{
- .description = "tl3_dip.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: em.vf_2_vfr.0 */
{
- .description = "tl3_qos.en",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tl3_df.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl4_l4type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vf_egr */
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW}
},
{
- .description = "tflags.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tid.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: mod_record.vfr_2_vf_egr */
{
- .description = "tqos.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "terr.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dt.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_dip_selcmp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ttl.en",
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_prot.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_fid.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_qos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_esp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_auth.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_dest.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_frag.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_hop.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_df.en",
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_dst.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
- /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
+ .description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
+ 1}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_2_vf.ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -43261,7 +47154,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 5, , table: em.vfr.0 */
+ /* class_tid: 5, , table: em.vfr_2_vf.0 */
{
.description = "valid",
.field_bit_size = 1,
@@ -43313,7 +47206,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.description = "default_arec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.ident_bit_size = 16,
- .ident_bit_pos = 136
+ .ident_bit_pos = 137
},
{
.description = "drv_func.parent.mac",
@@ -43402,7 +47295,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.description = "default_arec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.ident_bit_size = 16,
- .ident_bit_pos = 136
+ .ident_bit_pos = 137
},
{
.description = "drv_func.parent.mac",
@@ -43574,3 +47467,4 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.ident_bit_pos = 29
}
};
+
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index 16a921e6c8..2a499c0ba2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -20,7 +18,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 0,
- .cond_nums = 9 }
+ .cond_nums = 12 }
},
/* act_tid: 2, ingress */
[2] = {
@@ -29,7 +27,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 }
},
/* act_tid: 3, ingress */
@@ -38,39 +36,69 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.num_tbls = 7,
.start_tbl_idx = 12,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 15,
- .cond_nums = 0 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 18,
+ .cond_nums = 3 }
},
- /* act_tid: 4, egress */
+ /* act_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
.start_tbl_idx = 19,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 21,
- .cond_nums = 0 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 29,
+ .cond_nums = 1 }
},
- /* act_tid: 5, egress */
+ /* act_tid: 5, ingress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 7,
+ .num_tbls = 1,
.start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 29,
+ .cond_start_idx = 35,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 6,
- .start_tbl_idx = 31,
+ .num_tbls = 5,
+ .start_tbl_idx = 25,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 35,
.cond_nums = 0 }
+ },
+ /* act_tid: 7, egress */
+ [7] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 7,
+ .start_tbl_idx = 30,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 43,
+ .cond_nums = 3 }
+ },
+ /* act_tid: 8, egress */
+ [8] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 6,
+ .start_tbl_idx = 37,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 54,
+ .cond_nums = 3 }
+ },
+ /* act_tid: 9, egress */
+ [9] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 3,
+ .start_tbl_idx = 43,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 63,
+ .cond_nums = 0 }
}
};
@@ -85,7 +113,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -107,7 +135,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -127,7 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@@ -149,7 +177,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -170,7 +198,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -188,7 +216,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -203,7 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
@@ -224,7 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -245,7 +273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -267,7 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -289,7 +317,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
@@ -309,7 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -329,8 +357,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
- .cond_nums = 1 },
+ .cond_start_idx = 21,
+ .cond_nums = 3 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
@@ -343,7 +371,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 24,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -362,7 +390,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 17,
+ .cond_start_idx = 25,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@@ -381,7 +409,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 26,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@@ -390,7 +418,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 3, , table: int_encap_mac_record.0 */
+ { /* act_tid: 3, , table: int_encap_vlan_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -400,7 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 19,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -421,7 +449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 19,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -440,7 +468,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 20,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -455,21 +483,130 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 21,
+ .cond_start_idx = 30,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ { /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 231,
+ .result_bit_size = 0,
+ .result_num_fields = 0
+ },
+ { /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 231,
+ .result_bit_size = 0,
+ .result_num_fields = 0
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 33,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 231,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 4, , table: int_full_act_record.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 35,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 257,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 35,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -479,18 +616,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 22,
+ .cond_start_idx = 36,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 8,
- .result_start_idx = 231,
+ .result_start_idx = 284,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* act_tid: 4, , table: int_full_act_record.0 */
+ { /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -500,16 +637,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 24,
+ .cond_start_idx = 38,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 242,
+ .result_start_idx = 295,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 4, , table: ext_full_act_record.no_tag */
+ { /* act_tid: 6, , table: ext_full_act_record.no_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -519,17 +656,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 25,
+ .cond_start_idx = 39,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 268,
+ .result_start_idx = 321,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 4, , table: ext_full_act_record.one_tag */
+ { /* act_tid: 6, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -539,28 +676,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 41,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 305,
+ .result_start_idx = 358,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 5, , table: control.0 */
+ { /* act_tid: 7, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
+ .cond_start_idx = 46,
+ .cond_nums = 3 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ { /* act_tid: 7, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
@@ -570,16 +707,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
+ .cond_start_idx = 49,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 342,
+ .result_start_idx = 395,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: act_modify_ipv4_src.0 */
+ { /* act_tid: 7, , table: act_modify_ipv4_src.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.resource_sub_type =
@@ -589,16 +726,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 31,
+ .cond_start_idx = 50,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 343,
+ .result_start_idx = 396,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: act_modify_ipv4_dst.0 */
+ { /* act_tid: 7, , table: act_modify_ipv4_dst.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.resource_sub_type =
@@ -608,16 +745,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 51,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 344,
+ .result_start_idx = 397,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: int_encap_mac_record.dummy */
+ { /* act_tid: 7, , table: int_encap_vlan_record.dummy */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -627,18 +764,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 33,
+ .cond_start_idx = 52,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.record_size = 16,
- .result_start_idx = 345,
+ .result_start_idx = 398,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* act_tid: 5, , table: int_full_act_record.0 */
+ { /* act_tid: 7, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -648,16 +785,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 52,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 356,
+ .result_start_idx = 409,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 5, , table: ext_full_act_record.0 */
+ { /* act_tid: 7, , table: ext_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -667,17 +804,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 53,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 382,
+ .result_start_idx = 435,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ { /* act_tid: 8, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
@@ -687,16 +824,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 57,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 419,
+ .result_start_idx = 472,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ { /* act_tid: 8, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.resource_sub_type =
@@ -706,18 +843,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 58,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 16,
- .result_start_idx = 420,
+ .result_start_idx = 473,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 2
},
- { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ { /* act_tid: 8, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
.resource_sub_type =
@@ -727,18 +864,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 59,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 24,
- .result_start_idx = 422,
+ .result_start_idx = 475,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 2
},
- { /* act_tid: 6, , table: int_tun_encap_record.0 */
+ { /* act_tid: 8, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.resource_sub_type =
@@ -748,18 +885,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 60,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 64,
- .result_start_idx = 424,
+ .result_start_idx = 477,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
- { /* act_tid: 6, , table: int_full_act_record.0 */
+ { /* act_tid: 8, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -769,16 +906,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 61,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 454,
+ .result_start_idx = 507,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */
+ { /* act_tid: 8, , table: ext_full_act_record_vxlan.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -788,15 +925,64 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 62,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 480,
+ .result_start_idx = 533,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 30
+ },
+ { /* act_tid: 9, , table: control.reject */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 63,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 63,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 589,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 9, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 64,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 590,
+ .result_bit_size = 128,
+ .result_num_fields = 26
}
};
@@ -838,6 +1024,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP
},
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER
+ },
/* cond_execute: act_tid: 1, shared_mirror_record.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -866,10 +1064,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_reject: wh_plus, act_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
/* cond_execute: act_tid: 3, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
},
/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
{
@@ -894,12 +1113,41 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
- /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ /* cond_reject: wh_plus, act_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_rss_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_queue_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
},
- /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, int_vtag_encap_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -907,11 +1155,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ /* cond_execute: act_tid: 6, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 4, ext_full_act_record.no_tag */
+ /* cond_execute: act_tid: 6, ext_full_act_record.no_tag */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -919,7 +1167,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 4, ext_full_act_record.one_tag */
+ /* cond_execute: act_tid: 6, ext_full_act_record.one_tag */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -927,60 +1175,103 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 5, control.0 */
+ /* cond_reject: wh_plus, act_tid: 7 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 7, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
},
- /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ /* cond_execute: act_tid: 7, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
- /* cond_execute: act_tid: 5, act_modify_ipv4_src.0 */
+ /* cond_execute: act_tid: 7, act_modify_ipv4_src.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
},
- /* cond_execute: act_tid: 5, act_modify_ipv4_dst.0 */
+ /* cond_execute: act_tid: 7, act_modify_ipv4_dst.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
},
- /* cond_execute: act_tid: 5, int_full_act_record.0 */
+ /* cond_execute: act_tid: 7, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 5, ext_full_act_record.0 */
+ /* cond_execute: act_tid: 7, ext_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
- /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ /* cond_reject: wh_plus, act_tid: 8 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 8, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
- /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ /* cond_execute: act_tid: 8, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
},
- /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ /* cond_execute: act_tid: 8, sp_smac_ipv6.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.0 */
+ /* cond_execute: act_tid: 8, int_tun_encap_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 6, int_full_act_record.0 */
+ /* cond_execute: act_tid: 8, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 6, ext_full_act_record_vxlan.0 */
+ /* cond_execute: act_tid: 8, ext_full_act_record_vxlan.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
+ },
+ /* cond_execute: act_tid: 9, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 9, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
}
};
@@ -2252,7 +2543,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
},
- /* act_tid: 3, , table: int_encap_mac_record.0 */
+ /* act_tid: 3, , table: int_encap_vlan_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -2753,114 +3044,467 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_DECAP_FUNC_THRU_L2}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 12,
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RSS_VNIC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RSS_VNIC & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_full_act_record.1 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pop_vlan",
- .field_bit_size = 1,
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 1,
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 2,
+ .description = "meter_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_rdir",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
+ .description = "tl3_rdir",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
+ .description = "l3_ttl_dec",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "pop_vlan",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "meter",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "mirror",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_de",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "type",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ /* act_tid: 6, , table: int_vtag_encap_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -2940,7 +3584,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
- /* act_tid: 4, , table: int_full_act_record.0 */
+ /* act_tid: 6, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3130,7 +3774,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: ext_full_act_record.no_tag */
+ /* act_tid: 6, , table: ext_full_act_record.no_tag */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3385,7 +4029,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: ext_full_act_record.one_tag */
+ /* act_tid: 6, , table: ext_full_act_record.one_tag */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3660,14 +4304,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
- /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 7, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: act_modify_ipv4_src.0 */
+ /* act_tid: 7, , table: act_modify_ipv4_src.0 */
{
.description = "ipv4_addr",
.field_bit_size = 32,
@@ -3677,7 +4321,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}
},
- /* act_tid: 5, , table: act_modify_ipv4_dst.0 */
+ /* act_tid: 7, , table: act_modify_ipv4_dst.0 */
{
.description = "ipv4_addr",
.field_bit_size = 32,
@@ -3687,7 +4331,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
},
- /* act_tid: 5, , table: int_encap_mac_record.dummy */
+ /* act_tid: 7, , table: int_encap_vlan_record.dummy */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -3758,7 +4402,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: int_full_act_record.0 */
+ /* act_tid: 7, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3988,7 +4632,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: ext_full_act_record.0 */
+ /* act_tid: 7, , table: ext_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -4288,14 +4932,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 8, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ /* act_tid: 8, , table: sp_smac_ipv4.0 */
{
.description = "smac",
.field_bit_size = 48,
@@ -4314,7 +4958,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
- /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ /* act_tid: 8, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
@@ -4333,7 +4977,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
- /* act_tid: 6, , table: int_tun_encap_record.0 */
+ /* act_tid: 8, , table: int_tun_encap_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -4836,7 +5480,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 6, , table: int_full_act_record.0 */
+ /* act_tid: 8, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -5011,7 +5655,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */
+ /* act_tid: 8, , table: ext_full_act_record_vxlan.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -5684,6 +6328,185 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 9, , table: int_full_act_record.0 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index d1c3ebe065..f92253bb58 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -102,9 +100,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.key_start_idx = 1,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 1,
.ident_nums = 1
},
@@ -136,7 +134,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 6,
+ .key_start_idx = 7,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -160,10 +158,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 19,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 20,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 13,
.result_bit_size = 62,
.result_num_fields = 4
@@ -183,7 +181,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 24,
+ .key_start_idx = 26,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -236,7 +234,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 27,
+ .key_start_idx = 29,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -262,7 +260,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 70,
+ .key_start_idx = 72,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -288,7 +286,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 113,
+ .key_start_idx = 115,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -313,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 156,
+ .key_start_idx = 158,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -334,7 +332,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 159,
+ .key_start_idx = 161,
.blob_key_bit_size = 176,
.key_bit_size = 176,
.key_num_fields = 10,
@@ -355,7 +353,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 169,
+ .key_start_idx = 171,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 10,
@@ -376,7 +374,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 179,
+ .key_start_idx = 181,
.blob_key_bit_size = 416,
.key_bit_size = 416,
.key_num_fields = 11,
@@ -397,7 +395,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 190,
+ .key_start_idx = 192,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -418,7 +416,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 201,
+ .key_start_idx = 203,
.blob_key_bit_size = 200,
.key_bit_size = 200,
.key_num_fields = 11,
@@ -439,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 212,
+ .key_start_idx = 214,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -461,9 +459,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 223,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 19,
+ .key_bit_size = 19,
.key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
@@ -496,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 225,
+ .key_start_idx = 227,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -520,9 +518,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 238,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
+ .key_start_idx = 240,
+ .blob_key_bit_size = 19,
+ .key_bit_size = 19,
.key_num_fields = 2,
.result_start_idx = 140,
.result_bit_size = 52,
@@ -553,10 +551,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 240,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 242,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 11,
.ident_nums = 1
},
@@ -588,7 +586,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 245,
+ .key_start_idx = 248,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -612,10 +610,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 258,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 261,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
@@ -635,7 +633,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 263,
+ .key_start_idx = 267,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -672,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 266,
+ .key_start_idx = 270,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -695,7 +693,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 309,
+ .key_start_idx = 313,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -716,7 +714,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 312,
+ .key_start_idx = 316,
.blob_key_bit_size = 112,
.key_bit_size = 112,
.key_num_fields = 8,
@@ -737,7 +735,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 320,
+ .key_start_idx = 324,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 8,
@@ -759,7 +757,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 328,
+ .key_start_idx = 332,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -780,10 +778,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 329,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 333,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 16,
.ident_nums = 1
},
@@ -815,7 +813,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 334,
+ .key_start_idx = 339,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -839,10 +837,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 347,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 352,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
@@ -861,7 +859,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 352,
+ .key_start_idx = 358,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -914,7 +912,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 355,
+ .key_start_idx = 361,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -940,7 +938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 398,
+ .key_start_idx = 404,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -964,7 +962,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 441,
+ .key_start_idx = 447,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -985,7 +983,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 444,
+ .key_start_idx = 450,
.blob_key_bit_size = 176,
.key_bit_size = 176,
.key_num_fields = 10,
@@ -1006,7 +1004,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 454,
+ .key_start_idx = 460,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 10,
@@ -1027,7 +1025,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 464,
+ .key_start_idx = 470,
.blob_key_bit_size = 416,
.key_bit_size = 416,
.key_num_fields = 11,
@@ -1048,7 +1046,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 475,
+ .key_start_idx = 481,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -1090,7 +1088,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 486,
+ .key_start_idx = 492,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1127,7 +1125,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 487,
+ .key_start_idx = 493,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1151,7 +1149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 500,
+ .key_start_idx = 506,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1256,7 +1254,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 501,
+ .key_start_idx = 507,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1291,7 +1289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 502,
+ .key_start_idx = 508,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1315,7 +1313,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 515,
+ .key_start_idx = 521,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1337,7 +1335,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 516,
+ .key_start_idx = 522,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1372,7 +1370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 517,
+ .key_start_idx = 523,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1396,7 +1394,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 530,
+ .key_start_idx = 536,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1511,7 +1509,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 531,
+ .key_start_idx = 537,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1546,7 +1544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 532,
+ .key_start_idx = 538,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1570,7 +1568,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 545,
+ .key_start_idx = 551,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1667,7 +1665,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 546,
+ .key_start_idx = 552,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1691,7 +1689,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 559,
+ .key_start_idx = 565,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1726,7 +1724,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 560,
+ .key_start_idx = 566,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1750,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 573,
+ .key_start_idx = 579,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1837,7 +1835,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 574,
+ .key_start_idx = 580,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1864,7 +1862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 587,
+ .key_start_idx = 593,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -2243,6 +2241,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -2595,6 +2607,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
@@ -5933,7 +5959,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
{
.field_info_mask = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -5942,7 +5968,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
.field_info_spec = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6160,7 +6186,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
{
.field_info_mask = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6169,7 +6195,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
.field_info_spec = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6281,6 +6307,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -6455,7 +6495,9 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "key_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
},
.field_info_spec = {
.description = "key_type",
@@ -6567,6 +6609,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
@@ -6736,14 +6792,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_WP_SYM_L3_HDR_TYPE_IPV4},
@@ -7052,8 +7108,23 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -7759,6 +7830,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -8111,6 +8196,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
@@ -16767,3 +16866,4 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
.ident_bit_pos = 0
}
};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 8790d7ac0d..fe1f65deb9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -296,6 +296,7 @@ int32_t
ulp_default_flow_create(struct rte_eth_dev *eth_dev,
struct ulp_tlv_param *param_list,
uint32_t ulp_class_tid,
+ uint16_t port_id,
uint32_t *flow_id)
{
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
@@ -355,12 +356,16 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
/* Get the function id */
if (ulp_port_db_port_func_id_get(ulp_ctx,
- eth_dev->data->port_id,
+ port_id,
&mapper_params.func_id)) {
BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
goto err1;
}
+ /* update the VF meta function id */
+ ULP_COMP_FLD_IDX_WR(&mapper_params, BNXT_ULP_CF_IDX_VF_META_FID,
+ BNXT_ULP_META_VF_FLAG | mapper_params.func_id);
+
BNXT_TF_DBG(DEBUG, "Creating default flow with template id: %u\n",
ulp_class_tid);
@@ -498,7 +503,7 @@ bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
return 0;
}
return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
- flow_id);
+ port_id, flow_id);
}
int32_t
@@ -526,8 +531,10 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
info->def_port_flow_id,
&bp->tx_cfa_action);
- if (rc)
+
+ if (rc || BNXT_TESTPMD_EN(bp))
bp->tx_cfa_action = 0;
+
info->valid = true;
return 0;
}
@@ -551,6 +558,7 @@ bnxt_create_port_vfr_default_rule(struct bnxt *bp,
}
};
return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
+ vfr_port_id,
flow_id);
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 85c9cbb7f2..dee2c04b24 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -311,7 +311,8 @@ ulp_fc_tf_flow_stat_get(struct bnxt_ulp_context *ctxt,
uint32_t dev_id = 0;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_flow_db_shared_session_get(res));
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
return -EINVAL;
@@ -437,8 +438,8 @@ void
ulp_fc_mgr_alarm_cb(void *arg)
{
int rc = 0;
- unsigned int j;
- enum tf_dir i;
+ unsigned int j = 0;
+ enum tf_dir i = 0;
struct bnxt_ulp_context *ctxt;
struct bnxt_ulp_fc_info *ulp_fc_info;
struct bnxt_ulp_device_params *dparms;
@@ -472,7 +473,8 @@ ulp_fc_mgr_alarm_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_fc_info->sw_acc_tbl[i][j].session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
bnxt_ulp_cntxt_entry_release();
@@ -512,6 +514,15 @@ ulp_fc_mgr_alarm_cb(void *arg)
if (!ulp_fc_info->sw_acc_tbl[i][j].valid)
continue;
hw_cntr_id = ulp_fc_info->sw_acc_tbl[i][j].hw_cntr_id;
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_fc_info->sw_acc_tbl[i][j].session_type);
+ if (!tfp) {
+ BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
+ pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+ bnxt_ulp_cntxt_entry_release();
+ return;
+ }
+
rc = ulp_get_single_flow_stat(ctxt, tfp, ulp_fc_info, i,
hw_cntr_id, dparms);
if (rc)
@@ -603,7 +614,8 @@ int32_t ulp_fc_mgr_start_idx_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
*
*/
int32_t ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
- uint32_t hw_cntr_id)
+ uint32_t hw_cntr_id,
+ enum bnxt_ulp_session_type session_type)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -619,6 +631,7 @@ int32_t ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = true;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = hw_cntr_id;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].session_type = session_type;
ulp_fc_info->num_entries++;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 9df5ae51a3..14836e0dd2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -29,6 +29,7 @@ struct sw_acc_counter {
bool valid;
uint32_t hw_cntr_id;
uint32_t pc_flow_idx;
+ enum bnxt_ulp_session_type session_type;
};
struct hw_fc_mem_info {
@@ -118,7 +119,9 @@ int ulp_fc_mgr_start_idx_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
*
*/
int ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
- uint32_t hw_cntr_id);
+ uint32_t hw_cntr_id,
+ enum bnxt_ulp_session_type session_type);
+
/*
* Reset the corresponding SW accumulator table entry based on
* the difference between this counter ID and the starting
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 9968311c44..2e6ea43ac1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -653,7 +653,8 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
ulp_fc_mgr_cntr_set(ulp_ctxt, params->direction,
- params->resource_hndl);
+ params->resource_hndl,
+ ulp_flow_db_shared_session_get(params));
if (!ulp_fc_mgr_thread_isstarted(ulp_ctxt))
ulp_fc_mgr_thread_start(ulp_ctxt);
@@ -1824,8 +1825,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
* returns none
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
- enum bnxt_ulp_shared_session shared)
+ enum bnxt_ulp_session_type s_type)
{
- if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
+ if (res && (s_type & BNXT_ULP_SESSION_TYPE_SHARED))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
+ else if (res && (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ res->fdb_flags |= ULP_FDB_FLAG_SHARED_WC_SESSION;
+}
+
+/*
+ * Get the shared bit for the flow db entry
+ *
+ * res [out] shared session type
+ */
+enum bnxt_ulp_session_type
+ulp_flow_db_shared_session_get(struct ulp_flow_db_res_params *res)
+{
+ enum bnxt_ulp_session_type stype = BNXT_ULP_SESSION_TYPE_DEFAULT;
+
+ if (res && (res->fdb_flags & ULP_FDB_FLAG_SHARED_SESSION))
+ stype = BNXT_ULP_SESSION_TYPE_SHARED;
+ else if (res && (res->fdb_flags & ULP_FDB_FLAG_SHARED_WC_SESSION))
+ stype = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+
+ return stype;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index ada34c0e6c..13a957fcff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -15,6 +15,7 @@
/* Defines for the fdb flag */
#define ULP_FDB_FLAG_SHARED_SESSION 0x1
+#define ULP_FDB_FLAG_SHARED_WC_SESSION 0x2
/*
* Structure for the flow database resource information
@@ -404,10 +405,18 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
* Set the shared bit for the flow db entry
*
* res [in] Ptr to fdb entry
- * shared [in] shared flag
+ * s_type [in] session flag
*
* returns none
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
- enum bnxt_ulp_shared_session shared);
+ enum bnxt_ulp_session_type s_type);
+
+/*
+ * Get the shared bit for the flow db entry
+ *
+ * res [out] Shared session type
+ */
+enum bnxt_ulp_session_type
+ulp_flow_db_shared_session_get(struct ulp_flow_db_res_params *res);
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 0030a487f5..42482b596f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -54,7 +54,7 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
@@ -88,7 +88,7 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in client num get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
@@ -176,7 +176,7 @@ ulp_ha_mgr_timer_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_YES);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
goto cb_restart;
@@ -399,7 +399,7 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7774a5537a..1f459c52a4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -115,7 +115,8 @@ ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data,
static int32_t
ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data,
- struct bnxt_ulp_glb_resource_info *glb_res)
+ struct bnxt_ulp_glb_resource_info *glb_res,
+ bool shared)
{
struct tf_alloc_identifier_parms iparms = { 0 };
struct tf_free_identifier_parms fparms;
@@ -123,7 +124,9 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
struct tf *tfp;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, shared ?
+ BNXT_ULP_SESSION_TYPE_SHARED :
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -167,7 +170,8 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
static int32_t
ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data,
- struct bnxt_ulp_glb_resource_info *glb_res)
+ struct bnxt_ulp_glb_resource_info *glb_res,
+ bool shared)
{
struct tf_alloc_tbl_entry_parms aparms = { 0 };
struct tf_free_tbl_entry_parms free_parms = { 0 };
@@ -176,7 +180,9 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_scope_id;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, shared ?
+ BNXT_ULP_SESSION_TYPE_SHARED :
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -728,6 +734,12 @@ ulp_mapper_priority_opc_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_PRI_OPC_APP_PRI:
*priority = parms->app_priority;
break;
+ case BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST:
+ if (parms->app_priority)
+ *priority = parms->app_priority;
+ else
+ *priority = tbl->pri_operand;
+ break;
default:
BNXT_TF_DBG(ERR, "Priority opcode not supported %d\n",
tbl->pri_opcode);
@@ -815,7 +827,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
struct tf *tfp;
int rc;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get tf pointer\n");
return -EINVAL;
@@ -853,7 +865,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = ident->ident_type;
fid_parms.resource_hndl = iparms.id;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -900,7 +912,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
int rc;
/* Get the tfp from ulp context */
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get tf pointer\n");
return -EINVAL;
@@ -950,7 +962,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = ident->ident_type;
fid_parms.resource_hndl = sparms.search_id;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -1682,7 +1694,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = gfid;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1730,7 +1742,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = act_idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1778,7 +1790,7 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = act_idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1846,7 +1858,7 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
uint16_t tmplen;
int32_t rc;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n");
return -EINVAL;
@@ -2026,7 +2038,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return 0;
}
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n");
return -EINVAL;
@@ -2088,7 +2100,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* For wild card tcam perform the post process to swap the blob */
if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
- if (dparms->dynamic_pad_en) {
+ if (dparms->wc_dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
key, mask,
@@ -2204,7 +2216,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = tbl->resource_type;
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_hndl = idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -2245,7 +2257,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t pad = 0;
enum bnxt_ulp_byte_order key_order, res_order;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to get the mem type for EM\n");
@@ -2281,7 +2293,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* if dynamic padding is enabled then add padding to result data */
- if (dparms->dynamic_pad_en) {
+ if (dparms->em_dynamic_pad_en) {
/* add padding to make sure key is at byte boundary */
ulp_blob_pad_align(&key, ULP_BUFFER_ALIGN_8_BITS);
@@ -2300,7 +2312,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
- if (dparms->dynamic_pad_en) {
+ if (dparms->em_dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
/* when dynamic padding is enabled merge result + key */
@@ -2423,7 +2435,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool shared = false;
enum tf_tbl_type tbl_type = tbl->resource_type;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
/* compute the blob size */
bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
@@ -2637,7 +2649,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
if (shared)
- tfp = bnxt_ulp_cntxt_shared_tfp_get(parms->ulp_ctx);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx,
+ tbl->session_type);
+
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR,
@@ -2671,7 +2685,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -2721,7 +2735,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
enum bnxt_ulp_if_tbl_opc if_opc = tbl->tbl_opcode;
uint32_t res_size;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
parms->device_params->result_byte_order)) {
@@ -3013,7 +3027,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = key_index;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -3077,12 +3091,14 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER:
rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
mapper_data,
- &glb_res[idx]);
+ &glb_res[idx],
+ false);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
mapper_data,
- &glb_res[idx]);
+ &glb_res[idx],
+ false);
break;
default:
BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
@@ -3104,108 +3120,57 @@ static int32_t
ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data)
{
- struct tf_get_shared_tbl_increment_parms iparms;
struct bnxt_ulp_glb_resource_info *glb_res;
- struct tf_get_session_info_parms sparms;
- uint32_t num_entries, i, dev_id, res;
- struct tf_resource_info *res_info;
- uint32_t addend;
- uint64_t regval;
- enum tf_dir dir;
- int32_t rc = 0;
- struct tf *tfp;
+ uint32_t num_glb_res_ids, idx, dev_id;
uint8_t app_id;
+ uint32_t rc = 0;
- memset(&sparms, 0, sizeof(sparms));
- glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_entries);
- if (!glb_res || !num_entries) {
+ glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_glb_res_ids);
+ if (!glb_res || !num_glb_res_ids) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_shared_tfp_get(ulp_ctx);
- if (!tfp) {
- BNXT_TF_DBG(ERR, "Failed to get tfp for app global init");
- return -EINVAL;
- }
- /*
- * Retrieve the resources that were assigned during the shared session
- * creation.
- */
- rc = tf_get_session_info(tfp, &sparms);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get session info (%d)\n", rc);
- return rc;
- }
-
- rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
+ rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get the app id in glb init (%d).\n",
+ BNXT_TF_DBG(ERR, "Failed to get device_id for glb init (%d)\n",
rc);
- return rc;
+ return -EINVAL;
}
- rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
+ rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get dev id for app glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get app_id for glb init (%d)\n",
rc);
- return rc;
+ return -EINVAL;
}
- /* Store all the app global resources */
- for (i = 0; i < num_entries; i++) {
- if (dev_id != glb_res[i].device_id ||
- app_id != glb_res[i].app_id)
+ /* Iterate the global resources and process each one */
+ for (idx = 0; idx < num_glb_res_ids; idx++) {
+ if (dev_id != glb_res[idx].device_id ||
+ glb_res[idx].app_id != app_id)
continue;
- dir = glb_res[i].direction;
- res = glb_res[i].resource_type;
- addend = 1;
-
- switch (glb_res[i].resource_func) {
+ switch (glb_res[idx].resource_func) {
case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER:
- res_info = &sparms.session_info.ident[dir].info[res];
+ rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
+ mapper_data,
+ &glb_res[idx],
+ false);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
- /*
- * Tables may have various strides for the allocations.
- * Need to account.
- */
- memset(&iparms, 0, sizeof(iparms));
- iparms.dir = dir;
- iparms.type = res;
- rc = tf_get_shared_tbl_increment(tfp, &iparms);
- if (rc) {
- BNXT_TF_DBG(ERR,
- "Failed to get addend for %s[%s] rc=(%d)\n",
- tf_tbl_type_2_str(res),
- tf_dir_2_str(dir), rc);
- return rc;
- }
- addend = iparms.increment_cnt;
- res_info = &sparms.session_info.tbl[dir].info[res];
- break;
- case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE:
- res_info = &sparms.session_info.tcam[dir].info[res];
- break;
- case BNXT_ULP_RESOURCE_FUNC_EM_TABLE:
- res_info = &sparms.session_info.em[dir].info[res];
+ rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
+ mapper_data,
+ &glb_res[idx],
+ false);
break;
default:
- BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n",
- glb_res[i].resource_func);
- continue;
+ BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
+ glb_res[idx].resource_func);
+ rc = -EINVAL;
+ break;
}
- regval = tfp_cpu_to_be_64((uint64_t)res_info->start);
- res_info->start += addend;
- /*
- * All resources written to the global regfile are shared for
- * this function.
- */
- rc = ulp_mapper_glb_resource_write(mapper_data, &glb_res[i],
- regval, true);
if (rc)
return rc;
}
-
return rc;
}
@@ -3216,69 +3181,76 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
static int32_t
ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
enum bnxt_ulp_cond_opc opc,
- uint32_t operand,
+ uint64_t operand,
int32_t *res)
{
enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT;
+ uint32_t field_size = 0;
int32_t rc = 0;
- uint8_t bit;
- uint64_t regval;
+ uint8_t bit, tmp;
+ uint64_t regval, result = 0;
switch (opc) {
case BNXT_ULP_COND_OPC_CF_IS_SET:
if (operand < BNXT_ULP_CF_IDX_LAST) {
- *res = ULP_COMP_FLD_IDX_RD(parms, operand);
+ result = ULP_COMP_FLD_IDX_RD(parms, operand);
} else {
- BNXT_TF_DBG(ERR, "comp field out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "comp field out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_CF_NOT_SET:
if (operand < BNXT_ULP_CF_IDX_LAST) {
- *res = !ULP_COMP_FLD_IDX_RD(parms, operand);
+ result = !ULP_COMP_FLD_IDX_RD(parms, operand);
} else {
- BNXT_TF_DBG(ERR, "comp field out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "comp field out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ACT_BIT_IS_SET:
if (operand < BNXT_ULP_ACT_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->act_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "action bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "action bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET:
if (operand < BNXT_ULP_ACT_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "action bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "action bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_HDR_BIT_IS_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
@@ -3286,80 +3258,110 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET:
rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit);
if (rc) {
- BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+ BNXT_TF_DBG(ERR,
+ "invalid ulp_glb_field_tbl idx %" PRIu64 "\n",
operand);
return -EINVAL;
}
- *res = ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
+ result = ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
break;
case BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET:
rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit);
if (rc) {
- BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+ BNXT_TF_DBG(ERR,
+ "invalid ulp_glb_field_tbl idx %" PRIu64 "\n",
operand);
return -EINVAL;
}
- *res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
+ result = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
break;
case BNXT_ULP_COND_OPC_RF_IS_SET:
if (!ulp_regfile_read(parms->regfile, operand, ®val)) {
- BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
+ BNXT_TF_DBG(ERR,
+ "regfile[%" PRIu64 "] read oob\n",
+ operand);
return -EINVAL;
}
- *res = regval != 0;
+ result = regval != 0;
break;
case BNXT_ULP_COND_OPC_RF_NOT_SET:
if (!ulp_regfile_read(parms->regfile, operand, ®val)) {
- BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
+ BNXT_TF_DBG(ERR,
+ "regfile[%" PRIu64 "] read oob\n", operand);
return -EINVAL;
}
- *res = regval == 0;
+ result = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- *res = parms->flow_pattern_id == operand;
+ result = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- *res = parms->act_pattern_id == operand;
+ result = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
BNXT_TF_DBG(ERR, "Failed to get the mem type\n");
return -EINVAL;
}
- *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 0 : 1;
+ result = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 0 : 1;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
BNXT_TF_DBG(ERR, "Failed to get the mem type\n");
return -EINVAL;
}
- *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
+ result = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
+ case BNXT_ULP_COND_OPC_ACT_PROP_IS_SET:
+ case BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET:
+ /* only supporting 1-byte action properties for now */
+ if (operand >= BNXT_ULP_ACT_PROP_IDX_LAST) {
+ BNXT_TF_DBG(ERR,
+ "act_prop[%" PRIu64 "] oob\n", operand);
+ return -EINVAL;
+ }
+ field_size = ulp_mapper_act_prop_size_get(operand);
+ if (sizeof(tmp) != field_size) {
+ BNXT_TF_DBG(ERR,
+ "act_prop[%" PRIu64 "] field mismatch %u\n",
+ operand, field_size);
+ return -EINVAL;
+ }
+ tmp = parms->act_prop->act_details[operand];
+ if (opc == BNXT_ULP_COND_OPC_ACT_PROP_IS_SET)
+ result = (int32_t)(tmp);
+ else
+ result = (int32_t)(!tmp);
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
break;
}
+
+ *res = !!result;
return (rc);
}
@@ -3797,10 +3799,7 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp,
BNXT_TF_DBG(ERR, "Unable to free resource\n ");
return -EINVAL;
}
- if (res->fdb_flags & ULP_FDB_FLAG_SHARED_SESSION)
- tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_YES);
- else
- tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp, ulp_flow_db_shared_session_get(res));
if (!tfp) {
BNXT_TF_DBG(ERR, "Unable to free resource failed to get tfp\n");
return -EINVAL;
@@ -4065,7 +4064,7 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
if (!ulp_ctx)
return -EINVAL;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -4136,7 +4135,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to acquire tfp.\n");
/* Free the mapper data regardless of errors. */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index f8ffb567b5..57c9e7d175 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -118,8 +118,8 @@ int32_t ulp_port_db_deinit(struct bnxt_ulp_context *ulp_ctxt)
*
* Returns 0 on success or negative number on failure.
*/
-int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
- struct rte_eth_dev *eth_dev)
+int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
+ struct rte_eth_dev *eth_dev)
{
uint32_t port_id = eth_dev->data->port_id;
struct ulp_phy_port_info *port_data;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index f575a3c2e2..784b93f8b3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -11,6 +11,7 @@
#define BNXT_PORT_DB_MAX_INTF_LIST 256
#define BNXT_PORT_DB_MAX_FUNC 2048
#define BNXT_ULP_FREE_PARIF_BASE 11
+#define BNXT_ULP_META_VF_FLAG 0x1000
enum bnxt_ulp_svif_type {
BNXT_ULP_DRV_FUNC_SVIF = 0,
@@ -51,6 +52,7 @@ struct ulp_func_if_info {
uint8_t func_parent_mac[RTE_ETHER_ADDR_LEN];
uint16_t phy_port_id;
uint16_t ifindex;
+ uint16_t vf_meta_data;
};
/* Structure for the Port database resource information. */
@@ -58,6 +60,7 @@ struct ulp_interface_info {
enum bnxt_ulp_intf_type type;
uint16_t drv_func_id;
uint16_t vf_func_id;
+ uint8_t type_is_pf;
};
struct ulp_phy_port_info {
@@ -109,8 +112,8 @@ int32_t ulp_port_db_deinit(struct bnxt_ulp_context *ulp_ctxt);
*
* Returns 0 on success or negative number on failure.
*/
-int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
- struct rte_eth_dev *eth_dev);
+int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
+ struct rte_eth_dev *eth_dev);
/*
* Api to get the ulp ifindex for a given device port.
@@ -167,7 +170,6 @@ int32_t
ulp_port_db_spif_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t ifindex, uint32_t dir, uint16_t *spif);
-
/*
* Api to get the parif for a given ulp ifindex.
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 80869b79c3..3566f3000b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -131,10 +131,6 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
params->field_idx = BNXT_ULP_PROTO_HDR_SVIF_NUM;
- /* Set the computed flags for no vlan tags before parsing */
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 1);
-
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
if (item->type >= (typeof(item->type))
@@ -515,8 +511,8 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
enum bnxt_ulp_direction_type item_dir;
uint16_t ethdev_id;
uint16_t mask = 0;
- int32_t rc = BNXT_TF_RC_PARSE_ERR;
uint32_t ifindex;
+ int32_t rc = BNXT_TF_RC_PARSE_ERR;
if (!item->spec) {
BNXT_TF_DBG(ERR, "ParseErr:Port spec is not valid\n");
@@ -535,6 +531,11 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
item_dir = BNXT_ULP_DIR_INVALID;
ethdev_id = port_spec->id;
mask = port_mask->id;
+
+ if (!port_mask->id) {
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE);
+ mask = 0xff;
+ }
break;
}
case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: {
@@ -778,7 +779,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
outer_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_HAS_VTAG, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
@@ -808,7 +809,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
inner_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_HAS_VTAG, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 3dcc6dbc0c..fb6fb3553b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -171,7 +171,7 @@ extern struct bnxt_ulp_act_match_info ulp_act_match_list[];
/* Device Specific Tables for mapper */
struct bnxt_ulp_mapper_cond_info {
enum bnxt_ulp_cond_opc cond_opcode;
- uint32_t cond_operand;
+ uint64_t cond_operand;
};
struct bnxt_ulp_mapper_cond_list_info {
@@ -233,10 +233,11 @@ struct bnxt_ulp_device_params {
uint64_t packet_count_mask;
uint32_t byte_count_shift;
uint32_t packet_count_shift;
- uint32_t dynamic_pad_en;
+ uint32_t wc_dynamic_pad_en;
+ uint32_t em_dynamic_pad_en;
uint32_t dynamic_sram_en;
uint32_t dyn_encap_list_size;
- struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[5];
uint32_t dyn_modify_list_size;
struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
@@ -305,8 +306,11 @@ struct bnxt_ulp_mapper_tbl_info {
enum bnxt_ulp_fdb_opc fdb_opcode;
uint32_t fdb_operand;
+ /* Manage ref_cnt via opcode for generic tables */
+ enum bnxt_ulp_ref_cnt_opc ref_cnt_opcode;
+
/* Shared session */
- enum bnxt_ulp_shared_session shared_session;
+ enum bnxt_ulp_session_type session_type;
};
struct bnxt_ulp_mapper_field_info {
@@ -340,6 +344,7 @@ struct bnxt_ulp_glb_resource_info {
uint8_t app_id;
enum bnxt_ulp_device_id device_id;
enum tf_dir direction;
+ enum bnxt_ulp_session_type session_type;
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
enum bnxt_ulp_glb_rf_idx glb_regfile_index;
@@ -349,6 +354,7 @@ struct bnxt_ulp_resource_resv_info {
uint8_t app_id;
enum bnxt_ulp_device_id device_id;
enum tf_dir direction;
+ enum bnxt_ulp_session_type session_type;
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
uint32_t count;
@@ -356,7 +362,13 @@ struct bnxt_ulp_resource_resv_info {
struct bnxt_ulp_app_capabilities_info {
uint8_t app_id;
+ uint32_t vxlan_port;
+ uint32_t vxlan_ip_port;
enum bnxt_ulp_device_id device_id;
+ uint32_t upgrade_fw_update;
+ uint8_t ha_pool_id;
+ uint8_t ha_reg_state;
+ uint8_t ha_reg_cnt;
uint32_t flags;
};
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 06/11] net/bnxt: add RSS and Queue action in TruFLow
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (4 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 07/11] net/bnxt: add support for rte meter Ajit Khaparde
` (5 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Kishore Padmanabha, Mike Baucom, Shuanglin Wang
[-- Attachment #1: Type: text/plain, Size: 186983 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Update ULP layer to support RSS/Queue action
- Modify VNIC handling driver to support RSS action
- Modify VNIC handling driver to support Queue action
This should allow to enable TruFlow path for all RTE_FLOW
by default in future.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/nics/features/bnxt.ini | 1 +
drivers/net/bnxt/bnxt.h | 39 +-
drivers/net/bnxt/bnxt_ethdev.c | 154 +--
drivers/net/bnxt/bnxt_filter.h | 6 +-
drivers/net/bnxt/bnxt_flow.c | 75 +-
drivers/net/bnxt/bnxt_hwrm.c | 187 +++-
drivers/net/bnxt/bnxt_hwrm.h | 30 +-
drivers/net/bnxt/bnxt_ring.c | 4 +-
drivers/net/bnxt/bnxt_rxq.c | 159 +--
drivers/net/bnxt/bnxt_rxr.c | 9 +-
drivers/net/bnxt/bnxt_txq.c | 2 +-
drivers/net/bnxt/bnxt_txr.c | 2 +-
drivers/net/bnxt/bnxt_txr.h | 2 +-
drivers/net/bnxt/bnxt_vnic.c | 969 +++++++++++++++++-
drivers/net/bnxt/bnxt_vnic.h | 80 +-
drivers/net/bnxt/meson.build | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 248 ++++-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 35 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 258 ++++-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 280 ++++-
drivers/net/bnxt/tf_ulp/meson.build | 25 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 13 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 37 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 4 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 121 ++-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 5 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 449 +++++++-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 58 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 26 +
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 22 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 338 +++++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 37 +-
35 files changed, 3279 insertions(+), 417 deletions(-)
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index 50a0b5bfa6..9c456fa863 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -84,6 +84,7 @@ of_set_vlan_vid = Y
pf = Y
port_id = Y
port_representor = Y
+queue = Y
represented_port = Y
rss = Y
sample = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index bb2e7fe003..6dd3c8b87c 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -24,6 +24,7 @@
#include "tf_core.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_vnic.h"
/* Vendor ID */
#define PCI_VENDOR_ID_BROADCOM 0x14E4
@@ -163,6 +164,8 @@
#define BNXT_HWRM_CMD_TO_FORWARD(cmd) \
(bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32)))
+#define BNXT_NTOHS rte_be_to_cpu_16
+
struct bnxt_led_info {
uint8_t num_leds;
uint8_t led_id;
@@ -238,11 +241,11 @@ struct bnxt_parent_info {
struct bnxt_pf_info {
#define BNXT_FIRST_PF_FID 1
#define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs)
-#define BNXT_MAX_VF_REPS_WH 64
-#define BNXT_MAX_VF_REPS_TH 256
+#define BNXT_MAX_VF_REPS_P4 64
+#define BNXT_MAX_VF_REPS_P5 256
#define BNXT_MAX_VF_REPS(bp) \
- (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \
- BNXT_MAX_VF_REPS_WH)
+ (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_P5 : \
+ BNXT_MAX_VF_REPS_P4)
#define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs)
#define BNXT_FIRST_VF_FID 128
#define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
@@ -366,7 +369,7 @@ struct bnxt_ptp_cfg {
uint32_t tx_regs[BNXT_PTP_TX_REGS];
uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
- /* On Thor, the Rx timestamp is present in the Rx completion record */
+ /* On P5, the Rx timestamp is present in the Rx completion record */
uint64_t rx_timestamp;
uint64_t current_time;
};
@@ -679,8 +682,8 @@ struct bnxt {
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
-#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
-#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
+#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
+#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
#define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
#define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
#define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
@@ -689,7 +692,7 @@ struct bnxt {
#define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp)
#define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp))
#define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
-#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
+#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
uint32_t flags2;
@@ -697,8 +700,8 @@ struct bnxt {
#define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1)
#define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \
((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
-#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
-#define BNXT_TESTPMD_EN(bp) \
+#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
+#define BNXT_TESTPMD_EN(bp) \
((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
uint16_t chip_num;
@@ -719,7 +722,8 @@ struct bnxt {
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
-#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
+#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\
+ (bp)->app_id != 0xFF)
pthread_mutex_t flow_lock;
@@ -729,6 +733,7 @@ struct bnxt {
#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
#define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3)
#define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
+#define BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF BIT(4)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
@@ -758,7 +763,6 @@ struct bnxt {
uint16_t nr_vnics;
-#define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
struct bnxt_vnic_info *vnic_info;
STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
@@ -873,6 +877,7 @@ struct bnxt {
uint16_t tx_cfa_action;
struct bnxt_ring_stats *prev_rx_ring_stats;
struct bnxt_ring_stats *prev_tx_ring_stats;
+ struct bnxt_vnic_queue_db vnic_queue_db;
#define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr)
struct rte_ether_addr *mcast_addr_list;
@@ -905,7 +910,7 @@ inline uint16_t bnxt_max_rings(struct bnxt *bp)
}
/*
- * RSS table size in Thor is 512.
+ * RSS table size in P5 is 512.
* Cap max Rx rings to the same value for RSS.
*/
if (BNXT_CHIP_P5(bp))
@@ -997,9 +1002,16 @@ void bnxt_schedule_fw_health_check(struct bnxt *bp);
bool is_bnxt_supported(struct rte_eth_dev *dev);
bool bnxt_stratus_device(struct bnxt *bp);
void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
+uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
int wait_to_complete);
+int
+bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
+int
+bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
extern const struct rte_flow_ops bnxt_flow_ops;
@@ -1053,5 +1065,6 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp);
struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bcde44bb14..4d84aaee0c 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -202,7 +202,7 @@ int is_bnxt_in_error(struct bnxt *bp)
* High level utility functions
*/
-static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
+uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
{
unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
BNXT_RSS_TBL_SIZE_P5);
@@ -421,6 +421,10 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
vnic_id, vnic, vnic->fw_grp_ids);
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc)
goto err_out;
@@ -429,7 +433,7 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
int j, nr_ctxs = bnxt_rss_ctxts(bp);
- /* RSS table size in Thor is 512.
+ /* RSS table size in P5 is 512.
* Cap max Rx rings to same value
*/
if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
@@ -479,9 +483,7 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
j, rxq->vnic, rxq->vnic->fw_grp_ids);
if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
- rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
- else
- vnic->rx_queue_cnt++;
+ vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
}
PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
@@ -755,12 +757,18 @@ static int bnxt_start_nic(struct bnxt *bp)
else
bp->flags &= ~BNXT_FLAG_JUMBO;
- /* THOR does not support ring groups.
+ /* P5 does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
if (BNXT_CHIP_P5(bp))
bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
+ rc = bnxt_vnic_queue_db_init(bp);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "could not allocate vnic db\n");
+ goto err_out;
+ }
+
rc = bnxt_alloc_hwrm_rings(bp);
if (rc) {
PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
@@ -808,6 +816,9 @@ static int bnxt_start_nic(struct bnxt *bp)
}
}
+ /* setup the default vnic details*/
+ bnxt_vnic_queue_db_update_dlft_vnic(bp);
+
/* VNIC configuration */
for (i = 0; i < bp->nr_vnics; i++) {
rc = bnxt_setup_one_vnic(bp, i);
@@ -901,6 +912,7 @@ static int bnxt_shutdown_nic(struct bnxt *bp)
bnxt_free_all_hwrm_resources(bp);
bnxt_free_all_filters(bp);
bnxt_free_all_vnics(bp);
+ bnxt_vnic_queue_db_deinit(bp);
return 0;
}
@@ -1431,7 +1443,6 @@ static void bnxt_ptp_get_current_time(void *arg)
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
-
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
if (rc != 0) {
PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
@@ -1450,6 +1461,7 @@ static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
return rc;
}
@@ -1891,7 +1903,7 @@ static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_PROMISC;
@@ -1920,7 +1932,7 @@ static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
@@ -1949,7 +1961,7 @@ static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
@@ -1978,7 +1990,7 @@ static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
@@ -2026,7 +2038,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
uint16_t idx, sft;
int i, rc;
@@ -2048,6 +2060,10 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
return -EINVAL;
}
+ if (bnxt_vnic_reta_config_update(bp, vnic, reta_conf, reta_size)) {
+ PMD_DRV_LOG(ERR, "Error in setting the reta config\n");
+ return -EINVAL;
+ }
for (i = 0; i < reta_size; i++) {
struct bnxt_rx_queue *rxq;
@@ -2058,11 +2074,6 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
continue;
rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
- if (!rxq) {
- PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
- return -EINVAL;
- }
-
if (BNXT_CHIP_P5(bp)) {
vnic->rss_table[i * 2] =
rxq->rx_ring->rx_ring_struct->fw_ring_id;
@@ -2073,7 +2084,6 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
}
-
rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return rc;
}
@@ -2083,7 +2093,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
uint16_t reta_size)
{
struct bnxt *bp = eth_dev->data->dev_private;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
uint16_t idx, sft, i;
int rc;
@@ -2153,7 +2163,7 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
}
/* Update the default RSS VNIC(s) */
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
vnic->hash_mode =
bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
@@ -2189,7 +2199,7 @@ static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_conf *rss_conf)
{
struct bnxt *bp = eth_dev->data->dev_private;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int len, rc;
uint32_t hash_types;
@@ -2348,7 +2358,7 @@ static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
}
/* Add UDP tunneling port */
-static int
+int
bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel)
{
@@ -2410,7 +2420,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
return rc;
}
-static int
+int
bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel)
{
@@ -2474,7 +2484,7 @@ static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
int rc = 0;
uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
filter = STAILQ_FIRST(&vnic->filter);
while (filter) {
/* Search for this matching MAC+VLAN filter */
@@ -2513,7 +2523,7 @@ static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
* then the HWRM shall only create an l2 context id.
*/
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
filter = STAILQ_FIRST(&vnic->filter);
/* Check if the VLAN has already been added */
while (filter) {
@@ -2618,7 +2628,7 @@ bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
unsigned int i;
int rc;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
/* Remove any VLAN filters programmed */
for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
@@ -2677,16 +2687,18 @@ static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
static int
bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
{
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int rc;
/* Destroy, recreate and reconfigure the default vnic */
- rc = bnxt_free_one_vnic(bp, 0);
+ rc = bnxt_free_one_vnic(bp, bp->vnic_queue_db.dflt_vnic_id);
if (rc)
return rc;
- /* default vnic 0 */
- rc = bnxt_setup_one_vnic(bp, 0);
+ /* setup the default vnic details*/
+ bnxt_vnic_queue_db_update_dlft_vnic(bp);
+
+ rc = bnxt_setup_one_vnic(bp, bp->vnic_queue_db.dflt_vnic_id);
if (rc)
return rc;
@@ -2817,7 +2829,7 @@ bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
{
struct bnxt *bp = dev->data->dev_private;
/* Default Filter is tied to VNIC 0 */
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int rc;
rc = is_bnxt_in_error(bp);
@@ -2867,7 +2879,7 @@ bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
if (rc)
return rc;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
bp->nb_mc_addr = nb_mc_addr;
@@ -3029,8 +3041,7 @@ bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
- uint32_t rc;
- uint32_t i;
+ uint32_t rc = 0;
rc = is_bnxt_in_error(bp);
if (rc)
@@ -3048,30 +3059,17 @@ int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
/* Is there a change in mtu setting? */
if (eth_dev->data->mtu == new_mtu)
- return 0;
+ return rc;
if (new_mtu > RTE_ETHER_MTU)
bp->flags |= BNXT_FLAG_JUMBO;
else
bp->flags &= ~BNXT_FLAG_JUMBO;
- for (i = 0; i < bp->nr_vnics; i++) {
- struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
- uint16_t size = 0;
-
- vnic->mru = BNXT_VNIC_MRU(new_mtu);
- rc = bnxt_hwrm_vnic_cfg(bp, vnic);
- if (rc)
- break;
-
- size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
- size -= RTE_PKTMBUF_HEADROOM;
-
- if (size < new_mtu) {
- rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
- if (rc)
- return rc;
- }
+ rc = bnxt_vnic_mru_config(bp, new_mtu);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "failed to update mtu in vnic context\n");
+ return rc;
}
if (bnxt_hwrm_config_host_mtu(bp))
@@ -5312,9 +5310,11 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
{
int rc = 0;
- rc = bnxt_get_config(bp);
- if (rc)
- return rc;
+ if (reconfig_dev) {
+ rc = bnxt_get_config(bp);
+ if (rc)
+ return rc;
+ }
rc = bnxt_alloc_switch_domain(bp);
if (rc)
@@ -5756,7 +5756,7 @@ static int
bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
{
struct rte_kvargs *kvlist;
- int ret;
+ int ret = 0;
if (devargs == NULL)
return 0;
@@ -5825,22 +5825,6 @@ static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
bp->flags |= BNXT_FLAG_STINGRAY;
- if (BNXT_TRUFLOW_EN(bp)) {
- /* extra mbuf field is required to store CFA code from mark */
- static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
- .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
- .size = sizeof(bnxt_cfa_code_dynfield_t),
- .align = __alignof__(bnxt_cfa_code_dynfield_t),
- };
- bnxt_cfa_code_dynfield_offset =
- rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
- if (bnxt_cfa_code_dynfield_offset < 0) {
- PMD_DRV_LOG(ERR,
- "Failed to register mbuf field for TruFlow mark\n");
- return -rte_errno;
- }
- }
-
rc = bnxt_map_pci_bars(eth_dev);
if (rc) {
PMD_DRV_LOG(ERR,
@@ -5878,6 +5862,26 @@ static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
if (rc)
return rc;
+ rc = bnxt_get_config(bp);
+ if (rc)
+ return rc;
+
+ if (BNXT_TRUFLOW_EN(bp)) {
+ /* extra mbuf field is required to store CFA code from mark */
+ static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
+ .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
+ .size = sizeof(bnxt_cfa_code_dynfield_t),
+ .align = __alignof__(bnxt_cfa_code_dynfield_t),
+ };
+ bnxt_cfa_code_dynfield_offset =
+ rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
+ if (bnxt_cfa_code_dynfield_offset < 0) {
+ PMD_DRV_LOG(ERR,
+ "Failed to register mbuf field for TruFlow mark\n");
+ return -rte_errno;
+ }
+ }
+
return rc;
}
@@ -5912,6 +5916,9 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
bp = eth_dev->data->dev_private;
+ /* set the default app id */
+ bp->app_id = bnxt_ulp_default_app_id_get();
+
/* Parse dev arguments passed on when starting the DPDK application. */
rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
if (rc)
@@ -5948,7 +5955,8 @@ static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
if (!ctx)
return;
- rte_free(ctx->va);
+ if (ctx->va)
+ rte_free(ctx->va);
ctx->va = NULL;
ctx->dma = RTE_BAD_IOVA;
diff --git a/drivers/net/bnxt/bnxt_filter.h b/drivers/net/bnxt/bnxt_filter.h
index 587932c96f..57d704d90b 100644
--- a/drivers/net/bnxt/bnxt_filter.h
+++ b/drivers/net/bnxt/bnxt_filter.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -173,4 +173,8 @@ struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS
#define L2_FILTER_ALLOC_INPUT_EN_NUM_VLANS \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS
+#define CFA_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
+#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE
#endif
diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 4a107e81e9..28dd5ae6cb 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -677,7 +677,6 @@ bnxt_validate_and_parse_flow_type(const struct rte_flow_attr *attr,
break;
}
break;
-
default:
break;
}
@@ -728,7 +727,7 @@ bnxt_find_matching_l2_filter(struct bnxt *bp, struct bnxt_filter_info *nf)
struct bnxt_vnic_info *vnic0;
int i;
- vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic0 = bnxt_get_default_vnic(bp);
f0 = STAILQ_FIRST(&vnic0->filter);
/* This flow has same DST MAC as the port/l2 filter. */
@@ -905,6 +904,10 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct bnxt_vnic_info *vnic,
act,
"Failed to alloc VNIC group");
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc) {
rte_flow_error_set(error, -rc,
@@ -1345,7 +1348,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
* The user specified redirect queue will be set while creating
* the ntuple filter in hardware.
*/
- vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic0 = bnxt_get_default_vnic(bp);
if (use_ntuple)
filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
else
@@ -1964,7 +1967,37 @@ bnxt_flow_create(struct rte_eth_dev *dev,
* in such a case.
*/
if (filter->filter_type == HWRM_CFA_TUNNEL_REDIRECT_FILTER &&
- filter->enables == filter->tunnel_type) {
+ (filter->enables == filter->tunnel_type ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE)) {
+ if (filter->enables & NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT) {
+ struct rte_eth_udp_tunnel tunnel = {0};
+
+ /* hwrm_tunnel_dst_port_alloc converts to Big Endian */
+ tunnel.udp_port = BNXT_NTOHS(filter->dst_port);
+ if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_VXLAN;
+ } else if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_GENEVE;
+ } else {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Invalid tunnel type");
+ ret = -EINVAL;
+ goto free_filter;
+ }
+ ret = bnxt_udp_tunnel_port_add_op(bp->eth_dev, &tunnel);
+ if (ret != 0) {
+ rte_flow_error_set(error, -ret,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Fail to add tunnel port");
+ goto free_filter;
+ }
+ }
ret = bnxt_hwrm_tunnel_redirect_query(bp, &tun_type);
if (ret) {
rte_flow_error_set(error, -ret,
@@ -2147,8 +2180,38 @@ _bnxt_flow_destroy(struct bnxt *bp,
filter = flow->filter;
vnic = flow->vnic;
+ /* If tunnel redirection to a VF/PF is specified then only tunnel_type
+ * is set and enable is set to the tunnel type. Issue hwrm cmd directly
+ * in such a case.
+ */
if (filter->filter_type == HWRM_CFA_TUNNEL_REDIRECT_FILTER &&
- filter->enables == filter->tunnel_type) {
+ (filter->enables == filter->tunnel_type ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE)) {
+ if (filter->enables & NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT) {
+ struct rte_eth_udp_tunnel tunnel = {0};
+
+ /* hwrm_tunnel_dst_port_free converts to Big Endian */
+ tunnel.udp_port = BNXT_NTOHS(filter->dst_port);
+ if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_VXLAN;
+ } else if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_GENEVE;
+ } else {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Invalid tunnel type");
+ return ret;
+ }
+
+ ret = bnxt_udp_tunnel_port_del_op(bp->eth_dev,
+ &tunnel);
+ if (ret)
+ return ret;
+ }
ret = bnxt_handle_tunnel_redirect_destroy(bp, filter, error);
if (!ret)
goto done;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 3f273df6f3..77588bdf49 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -668,6 +668,7 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
else
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
+
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
@@ -858,9 +859,11 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
- if (BNXT_PF(bp)) {
+ if (BNXT_PF(bp))
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
- if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
+
+ if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
+ if (BNXT_CHIP_P5(bp) || BNXT_PF(bp)) {
bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
HWRM_UNLOCK();
@@ -894,6 +897,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
if (bp->tunnel_disable_flag)
PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
bp->tunnel_disable_flag);
+
unlock:
HWRM_UNLOCK();
@@ -951,6 +955,11 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP) {
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF;
+ PMD_DRV_LOG(DEBUG, "Trusted VF's outer RSS capability is enabled\n");
+ }
+
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
@@ -1097,7 +1106,16 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
bp->tx_nr_rings +
BNXT_NUM_ASYNC_CPR(bp));
- req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
+ if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
+ req.num_vnics = rte_cpu_to_le_16(RTE_MIN(BNXT_VNIC_MAX_SUPPORTED_ID,
+ bp->max_vnics));
+ enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
+ req.num_rsscos_ctxs = rte_cpu_to_le_16(RTE_MIN(BNXT_VNIC_MAX_SUPPORTED_ID,
+ bp->max_rsscos_ctx));
+ } else {
+ req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
+ }
+
if (bp->vf_resv_strategy ==
HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
@@ -1936,25 +1954,10 @@ static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cp
int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
- int rc = 0, i, j;
+ int rc = 0;
struct hwrm_vnic_alloc_input req = { 0 };
struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
- if (!BNXT_HAS_RING_GRPS(bp))
- goto skip_ring_grps;
-
- /* map ring groups to this vnic */
- PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
- vnic->start_grp_id, vnic->end_grp_id);
- for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
- vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
-
- vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
- vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
- vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
- vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
-
-skip_ring_grps:
vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
@@ -2068,7 +2071,8 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
*/
for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
rxq = bp->eth_dev->data->rx_queues[i];
- if (rxq->rx_started) {
+ if (rxq->rx_started &&
+ bnxt_vnic_queue_id_is_valid(vnic, i)) {
dflt_rxq = i;
break;
}
@@ -2298,14 +2302,22 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
- req.hash_mode_flags = vnic->hash_mode;
+ /* When the vnic_id in the request field is a valid
+ * one, the hash_mode_flags in the request field must
+ * be set to DEFAULT. And any request to change the
+ * default behavior must be done in a separate call
+ * to HWRM_VNIC_RSS_CFG by exclusively setting hash
+ * mode and vnic_id, rss_ctx_idx to INVALID.
+ */
+ req.hash_mode_flags = BNXT_HASH_MODE_DEFAULT;
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.ring_grp_tbl_addr =
rte_cpu_to_le_64(vnic->rss_table_dma_addr +
- i * HW_HASH_INDEX_SIZE);
+ i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
+ 2 * sizeof(uint16_t));
req.ring_table_pair_index = i;
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
@@ -2314,23 +2326,74 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
+ PMD_DRV_LOG(DEBUG, "RSS CFG: Hash level %d\n", req.hash_mode_flags);
}
return rc;
}
-int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
- struct bnxt_vnic_info *vnic)
+static int
+bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
- int rc = 0;
- struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
+ int rc = 0;
- if (!vnic->rss_table)
+ /* The reason we are returning success here is that this
+ * call is in the context of user/stack RSS configuration.
+ * Even though OUTER RSS is not supported, the normal RSS
+ * configuration should continue to work.
+ */
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)))
return 0;
- if (BNXT_CHIP_P5(bp))
- return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
+ /* Don't call RSS hash level configuration if the current
+ * hash level is the same as the hash level that is requested.
+ */
+ if (vnic->prev_hash_mode == vnic->hash_mode)
+ return 0;
+
+ HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
+
+ /* For FW, hash_mode == DEFAULT means that
+ * the FW is capable of doing INNER & OUTER RSS as well.
+ * DEFAULT doesn't mean that the FW is
+ * going to change the hash_mode to INNER. However, for
+ * the USER, DEFAULT means, change the hash mode to the
+ * NIC's DEFAULT hash mode which is INNER.
+ *
+ * Hence, driver should make the translation of hash_mode
+ * to INNERMOST when hash_mode from the dpdk stack is
+ * DEFAULT.
+ */
+ if (vnic->hash_mode == BNXT_HASH_MODE_DEFAULT)
+ req.hash_mode_flags = BNXT_HASH_MODE_INNERMOST;
+ else
+ req.hash_mode_flags = vnic->hash_mode;
+ req.vnic_id = rte_cpu_to_le_16(BNXT_DFLT_VNIC_ID_INVALID);
+ req.rss_ctx_idx = rte_cpu_to_le_16(BNXT_RSS_CTX_IDX_INVALID);
+
+ PMD_DRV_LOG(DEBUG, "RSS CFG: Hash level %d\n", req.hash_mode_flags);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
+ BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ /* Store the programmed hash_mode in prev_hash_mode so that
+ * it can checked against the next user requested hash mode.
+ */
+ if (!rc)
+ vnic->prev_hash_mode = vnic->hash_mode;
+ HWRM_UNLOCK();
+ return rc;
+}
+
+static int
+bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
+ struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc = 0;
HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
@@ -2352,6 +2415,39 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
return rc;
}
+int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ int rc = 0;
+
+ if (!vnic->rss_table)
+ return 0;
+
+ if (BNXT_CHIP_P5(bp)) {
+ rc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
+ if (rc)
+ return rc;
+ /* Configuring the hash mode has to be done in a
+ * different VNIC_RSS_CFG HWRM command by setting
+ * vnic_id & rss_ctx_id to INVALID. The only
+ * exception to this is if the USER doesn't want
+ * to change the default behavior. So, ideally
+ * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 should be
+ * called when user is explicitly changing the hash
+ * mode. However, this logic will unconditionally
+ * call bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 to
+ * simplify the logic as there is no harm in calling
+ * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 even when
+ * user is not setting it explicitly. Because, this
+ * routine will convert the default value to inner
+ * which is our adapter's default behavior.
+ */
+ return bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(bp, vnic);
+ }
+
+ return bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic);
+}
+
int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
struct bnxt_vnic_info *vnic)
{
@@ -2893,6 +2989,7 @@ void bnxt_free_all_hwrm_resources(struct bnxt *bp)
bnxt_hwrm_vnic_free(bp, vnic);
rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
}
/* Ring resources */
bnxt_free_all_hwrm_rings(bp);
@@ -3977,6 +4074,36 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
return rc;
}
+int bnxt_hwrm_tunnel_upar_id_get(struct bnxt *bp, uint8_t *upar_id,
+ uint8_t tunnel_type)
+{
+ struct hwrm_tunnel_dst_port_query_input req = {0};
+ struct hwrm_tunnel_dst_port_query_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc = 0;
+
+ HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_QUERY, BNXT_USE_CHIMP_MB);
+ req.tunnel_type = tunnel_type;
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+
+ switch (tunnel_type) {
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI:
+ *upar_id = resp->upar_in_use;
+ break;
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6:
+ *upar_id = resp->upar_in_use;
+ break;
+ default:
+ /* INVALID UPAR Id if another tunnel type tries to retrieve */
+ *upar_id = 0xff;
+ break;
+ }
+
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type)
{
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index f9d9fe0ef2..68384bc757 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -109,7 +109,31 @@ struct bnxt_pf_resource_info {
uint32_t num_hw_ring_grps;
};
-#define BNXT_CTX_VAL_INVAL 0xFFFF
+#define BNXT_CTX_VAL_INVAL 0xFFFF
+#define BNXT_RSS_CTX_IDX_INVALID 0xFFFF
+
+#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
+#define BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP))
+
+/*
+ * If the device supports VXLAN, GRE, IPIP and GENEVE tunnel parsing, then report
+ * RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM and
+ * RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM in the Rx/Tx offload capabilities of the device.
+ */
+#define BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp) \
+ (BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+
+#define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ
+#define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) \
(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
@@ -227,6 +251,8 @@ int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf);
int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type);
+int bnxt_hwrm_tunnel_upar_id_get(struct bnxt *bp, uint8_t *upar_id,
+ uint8_t tunnel_type);
int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type);
int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf);
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 4cdbb177d9..686c3af4da 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -54,7 +54,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp)
return -EBUSY;
}
- /* THOR does not support ring groups.
+ /* P5 does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
if (BNXT_CHIP_P5(bp)) {
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index 99758dd304..0d0b5e28e4 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -400,7 +400,7 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
rxq->rx_deferred_start = rx_conf->rx_deferred_start;
rxq->rx_started = rxq->rx_deferred_start ? false : true;
- rxq->vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ rxq->vnic = bnxt_get_default_vnic(bp);
return 0;
err:
@@ -460,6 +460,8 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_rx_queue *rxq = bp->rx_queues[rx_queue_id];
struct bnxt_vnic_info *vnic = NULL;
+ uint16_t vnic_idx = 0;
+ uint16_t fw_grp_id = 0;
int rc = 0;
rc = is_bnxt_in_error(bp);
@@ -471,6 +473,13 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return -EINVAL;
}
+ vnic = bnxt_vnic_queue_id_get_next(bp, rx_queue_id, &vnic_idx);
+ if (vnic == NULL) {
+ PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n",
+ rx_queue_id);
+ return -EINVAL;
+ }
+
/* reset the previous stats for the rx_queue since the counters
* will be cleared when the queue is started.
*/
@@ -490,29 +499,37 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return rc;
if (BNXT_HAS_RING_GRPS(bp))
- rxq->vnic->dflt_ring_grp = bp->grp_info[rx_queue_id].fw_grp_id;
- /* Reconfigure default receive ring and MRU. */
- bnxt_hwrm_vnic_cfg(bp, rxq->vnic);
-
- PMD_DRV_LOG(INFO, "Rx queue started %d\n", rx_queue_id);
+ fw_grp_id = bp->grp_info[rx_queue_id].fw_grp_id;
- if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
- vnic = rxq->vnic;
+ do {
+ if (BNXT_HAS_RING_GRPS(bp))
+ vnic->dflt_ring_grp = fw_grp_id;
+ /* Reconfigure default receive ring and MRU. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+
+ PMD_DRV_LOG(INFO, "Rx queue started %d\n", rx_queue_id);
+
+ if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
+ if (BNXT_HAS_RING_GRPS(bp)) {
+ if (vnic->fw_grp_ids[rx_queue_id] !=
+ INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "invalid ring id %d\n",
+ rx_queue_id);
+ return 0;
+ }
- if (BNXT_HAS_RING_GRPS(bp)) {
- if (vnic->fw_grp_ids[rx_queue_id] != INVALID_HW_RING_ID)
- return 0;
+ vnic->fw_grp_ids[rx_queue_id] = fw_grp_id;
+ PMD_DRV_LOG(DEBUG, "vnic = %p fw_grp_id = %d\n",
+ vnic, fw_grp_id);
+ }
- vnic->fw_grp_ids[rx_queue_id] =
- bp->grp_info[rx_queue_id].fw_grp_id;
- PMD_DRV_LOG(DEBUG,
- "vnic = %p fw_grp_id = %d\n",
- vnic, bp->grp_info[rx_queue_id].fw_grp_id);
+ PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n",
+ vnic->rx_queue_cnt);
+ rc += bnxt_vnic_rss_queue_status_update(bp, vnic);
}
-
- PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
- rc = bnxt_vnic_rss_configure(bp, vnic);
- }
+ vnic_idx++;
+ } while ((vnic = bnxt_vnic_queue_id_get_next(bp, rx_queue_id,
+ &vnic_idx)) != NULL);
if (rc != 0) {
dev->data->rx_queue_state[rx_queue_id] =
@@ -535,6 +552,7 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
struct bnxt_vnic_info *vnic = NULL;
struct bnxt_rx_queue *rxq = NULL;
int active_queue_cnt = 0;
+ uint16_t vnic_idx = 0, q_id = rx_queue_id;
int i, rc = 0;
rc = is_bnxt_in_error(bp);
@@ -556,61 +574,64 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return -EINVAL;
}
- vnic = rxq->vnic;
+ vnic = bnxt_vnic_queue_id_get_next(bp, q_id, &vnic_idx);
if (!vnic) {
- PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n",
- rx_queue_id);
+ PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n", q_id);
return -EINVAL;
}
- dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
+ dev->data->rx_queue_state[q_id] = RTE_ETH_QUEUE_STATE_STOPPED;
rxq->rx_started = false;
PMD_DRV_LOG(DEBUG, "Rx queue stopped\n");
- if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
- if (BNXT_HAS_RING_GRPS(bp))
- vnic->fw_grp_ids[rx_queue_id] = INVALID_HW_RING_ID;
-
- PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
- rc = bnxt_vnic_rss_configure(bp, vnic);
- }
-
- /* Compute current number of active receive queues. */
- for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
- if (bp->rx_queues[i]->rx_started)
- active_queue_cnt++;
+ do {
+ active_queue_cnt = 0;
+ if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
+ if (BNXT_HAS_RING_GRPS(bp))
+ vnic->fw_grp_ids[q_id] = INVALID_HW_RING_ID;
- if (BNXT_CHIP_P5(bp)) {
- /*
- * For Thor, we need to ensure that the VNIC default receive
- * ring corresponds to an active receive queue. When no queue
- * is active, we need to temporarily set the MRU to zero so
- * that packets are dropped early in the receive pipeline in
- * order to prevent the VNIC default receive ring from being
- * accessed.
- */
- if (active_queue_cnt == 0) {
- uint16_t saved_mru = vnic->mru;
-
- /* clear RSS setting on vnic. */
- bnxt_vnic_rss_clear_p5(bp, vnic);
-
- vnic->mru = 0;
- /* Reconfigure default receive ring and MRU. */
- bnxt_hwrm_vnic_cfg(bp, vnic);
- vnic->mru = saved_mru;
- } else {
- /* Reconfigure default receive ring. */
- bnxt_hwrm_vnic_cfg(bp, vnic);
+ PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n",
+ vnic->rx_queue_cnt);
+ rc = bnxt_vnic_rss_queue_status_update(bp, vnic);
}
- } else if (active_queue_cnt) {
- /*
- * If the queue being stopped is the current default queue and
- * there are other active queues, pick one of them as the
- * default and reconfigure the vnic.
- */
- if (vnic->dflt_ring_grp == bp->grp_info[rx_queue_id].fw_grp_id) {
- for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
+
+ /* Compute current number of active receive queues. */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
+ if (bp->rx_queues[i]->rx_started)
+ active_queue_cnt++;
+
+ if (BNXT_CHIP_P5(bp)) {
+ /*
+ * For P5, we need to ensure that the VNIC default
+ * receive ring corresponds to an active receive queue.
+ * When no queue is active, we need to temporarily set
+ * the MRU to zero so that packets are dropped early in
+ * the receive pipeline in order to prevent the VNIC
+ * default receive ring from being accessed.
+ */
+ if (active_queue_cnt == 0) {
+ uint16_t saved_mru = vnic->mru;
+
+ /* clear RSS setting on vnic. */
+ bnxt_vnic_rss_clear_p5(bp, vnic);
+
+ vnic->mru = 0;
+ /* Reconfigure default receive ring and MRU. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+ vnic->mru = saved_mru;
+ } else {
+ /* Reconfigure default receive ring. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+ }
+ } else if (active_queue_cnt && vnic->dflt_ring_grp ==
+ bp->grp_info[q_id].fw_grp_id) {
+ /*
+ * If the queue being stopped is the current default
+ * queue and there are other active queues, pick one of
+ * them as the default and reconfigure the vnic.
+ */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id;
+ i++) {
if (bp->rx_queues[i]->rx_started) {
vnic->dflt_ring_grp =
bp->grp_info[i].fw_grp_id;
@@ -619,7 +640,9 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
}
}
}
- }
+ vnic_idx++;
+ } while ((vnic = bnxt_vnic_queue_id_get_next(bp, q_id,
+ &vnic_idx)) != NULL);
if (rc == 0)
bnxt_rx_queue_release_mbufs(rxq);
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index a067278dca..1ab0ef2f5d 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -691,7 +691,7 @@ static void
bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
{
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
- uint64_t last_hwrm_time;
+ uint64_t last_hwrm_time = 0;
uint64_t pkt_time = 0;
if (!BNXT_CHIP_P5(bp) || !ptp)
@@ -705,7 +705,6 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
* from the HWRM response with the lower 32 bits in the
* Rx completion to produce the 48 bit timestamp for the Rx packet
*/
- last_hwrm_time = ptp->current_time;
pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
/* timer has rolled over */
@@ -923,7 +922,7 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
- RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
+ RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
@@ -1089,6 +1088,7 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
break;
}
+ cpr->cp_raw_cons = raw_cons;
if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
/*
* For PMD, there is no need to keep on pushing to REARM
@@ -1097,7 +1097,6 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
goto done;
}
- cpr->cp_raw_cons = raw_cons;
/* Ring the completion queue doorbell. */
bnxt_db_cq(cpr);
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index c8745add5e..d1d1fe8f1f 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 21c2217092..10b716a00b 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 75456df5bd..b9b8a9b1a2 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c
index b3c03a2af5..be9c127b64 100644
--- a/drivers/net/bnxt/bnxt_vnic.c
+++ b/drivers/net/bnxt/bnxt_vnic.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -9,8 +9,26 @@
#include <rte_malloc.h>
#include "bnxt.h"
+#include "bnxt_rxq.h"
+#include "bnxt_rxr.h"
+#include "bnxt_ring.h"
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
+#include "bnxt_hwrm.h"
+
+/* Macros to manipulate vnic bitmaps*/
+#define BNXT_VNIC_BITMAP_SIZE 64
+#define BNXT_VNIC_BITMAP_SET(b, i) ((b[(i) / BNXT_VNIC_BITMAP_SIZE]) |= \
+ (1UL << ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE))))
+
+#define BNXT_VNIC_BITMAP_RESET(b, i) ((b[(i) / BNXT_VNIC_BITMAP_SIZE]) &= \
+ (~(1UL << ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE)))))
+
+#define BNXT_VNIC_BITMAP_GET(b, i) (((b[(i) / BNXT_VNIC_BITMAP_SIZE]) >> \
+ ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE))) & 1)
/*
* VNIC Functions
@@ -51,6 +69,8 @@ static void bnxt_init_vnics(struct bnxt *bp)
vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
vnic->hash_mode =
HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
+ vnic->prev_hash_mode =
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
vnic->rx_queue_cnt = 0;
STAILQ_INIT(&vnic->filter);
@@ -84,6 +104,11 @@ void bnxt_free_all_vnics(struct bnxt *bp)
for (i = 0; i < bp->max_vnics; i++) {
vnic = &bp->vnic_info[i];
STAILQ_INSERT_TAIL(&bp->free_vnic_list, vnic, next);
+ if (vnic->ref_cnt) {
+ /* clean up the default vnic details */
+ bnxt_vnic_rss_action_free(bp, i);
+ }
+
vnic->rx_queue_cnt = 0;
}
}
@@ -212,6 +237,7 @@ int bnxt_alloc_vnic_mem(struct bnxt *bp)
int bnxt_vnic_grp_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
+ uint32_t i;
vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
if (!vnic->fw_grp_ids) {
@@ -220,7 +246,10 @@ int bnxt_vnic_grp_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
size);
return -ENOMEM;
}
- memset(vnic->fw_grp_ids, -1, size);
+
+ /* Initialize to invalid ring id */
+ for (i = 0; i < bp->max_ring_grps; i++)
+ vnic->fw_grp_ids[i] = INVALID_HW_RING_ID;
return 0;
}
@@ -259,30 +288,27 @@ int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl)
/* If FW has not advertised capability to configure outer/inner
* RSS hashing , just log a message. HW will work in default RSS mode.
*/
- if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)) {
- PMD_DRV_LOG(ERR, "RSS hash level cannot be configured\n");
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS))) {
+ if (lvl)
+ PMD_DRV_LOG(INFO,
+ "Given RSS level is unsupported, using default RSS level\n");
return mode;
}
switch (lvl) {
case BNXT_RSS_LEVEL_INNERMOST:
- if (l3_and_l4 || l4)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4;
- else if (l3_only)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2;
+ /* Irrespective of what RTE says, FW always does 4 tuple */
+ if (l3_and_l4 || l4 || l3_only)
+ mode = BNXT_HASH_MODE_INNERMOST;
break;
case BNXT_RSS_LEVEL_OUTERMOST:
- if (l3_and_l4 || l4)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4;
- else if (l3_only)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2;
+ /* Irrespective of what RTE says, FW always does 4 tuple */
+ if (l3_and_l4 || l4 || l3_only)
+ mode = BNXT_HASH_MODE_OUTERMOST;
break;
default:
- mode = HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
+ mode = BNXT_HASH_MODE_DEFAULT;
break;
}
@@ -296,7 +322,8 @@ uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode)
/* If FW has not advertised capability to configure inner/outer RSS
* return default hash mode.
*/
- if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS))
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)))
return RTE_ETH_RSS_LEVEL_PMD_DEFAULT;
if (mode == HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 ||
@@ -310,3 +337,909 @@ uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode)
return rss_level;
}
+
+static
+int32_t bnxt_vnic_populate_rss_table_p5(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ uint32_t ctx_idx = 0, rss_idx = 0, cnt = 0;
+ uint32_t q_id = -1;
+ struct bnxt_rx_queue *rxq;
+ uint16_t *ring_tbl = vnic->rss_table;
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ uint16_t ring_id;
+
+ /* For P5 platform */
+ for (ctx_idx = 0; ctx_idx < vnic->num_lb_ctxts; ctx_idx++) {
+ for (rss_idx = 0; rss_idx < BNXT_RSS_ENTRIES_PER_CTX_P5;
+ rss_idx++) {
+ /* Find next active ring. */
+ for (cnt = 0; cnt < BNXT_VNIC_MAX_QUEUE_SIZE; cnt++) {
+ if (++q_id == bp->rx_nr_rings)
+ q_id = 0; /* reset the q_id */
+ if (BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ q_id) &&
+ rx_queue_state[q_id] !=
+ RTE_ETH_QUEUE_STATE_STOPPED)
+ break;
+ }
+
+ /* no active queues exit */
+ if (cnt == BNXT_VNIC_MAX_QUEUE_SIZE)
+ return 0;
+
+ rxq = bp->rx_queues[q_id];
+ ring_id = rxq->rx_ring->rx_ring_struct->fw_ring_id;
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ ring_id = rxq->cp_ring->cp_ring_struct->fw_ring_id;
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ }
+ }
+ return 0;
+}
+
+static
+int32_t bnxt_vnic_populate_rss_table_p4(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ uint32_t rss_idx = 0, cnt = 0;
+ uint32_t q_id = -1;
+ uint16_t *ring_tbl = vnic->rss_table;
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ uint16_t ring_id;
+
+ /* For Wh+ platform */
+ for (rss_idx = 0; rss_idx < bnxt_rss_hash_tbl_size(bp); rss_idx++) {
+ /* Find next active ring. */
+ for (cnt = 0; cnt < BNXT_VNIC_MAX_QUEUE_SIZE; cnt++) {
+ if (++q_id == bp->rx_nr_rings)
+ q_id = 0; /* reset the q_id */
+ if (BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ q_id) &&
+ rx_queue_state[q_id] !=
+ RTE_ETH_QUEUE_STATE_STOPPED)
+ break;
+ }
+
+ /* no active queues exit */
+ if (cnt == BNXT_VNIC_MAX_QUEUE_SIZE)
+ return 0;
+
+ ring_id = vnic->fw_grp_ids[q_id];
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ }
+ return 0;
+}
+
+static
+int32_t bnxt_vnic_populate_rss_table(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ /* RSS table population is different for p4 and p5 platforms */
+ if (BNXT_CHIP_P5(bp))
+ return bnxt_vnic_populate_rss_table_p5(bp, vnic);
+
+ return bnxt_vnic_populate_rss_table_p4(bp, vnic);
+}
+
+static void
+bnxt_vnic_queue_delete(struct bnxt *bp, uint16_t vnic_idx)
+{
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_idx];
+
+ if (bnxt_hwrm_vnic_free(bp, vnic))
+ PMD_DRV_LOG(ERR, "Failed to delete queue\n");
+
+ if (vnic->fw_grp_ids) {
+ rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
+ }
+
+ vnic->rx_queue_cnt = 0;
+ if (bp->nr_vnics)
+ bp->nr_vnics--;
+
+ /* reset the queue_bitmap */
+ memset(vnic->queue_bitmap, 0, sizeof(vnic->queue_bitmap));
+}
+
+static struct bnxt_vnic_info*
+bnxt_vnic_queue_create(struct bnxt *bp, int32_t vnic_id, uint16_t q_index)
+{
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ struct bnxt_vnic_info *vnic;
+ struct bnxt_rx_queue *rxq = NULL;
+ int32_t rc = -EINVAL;
+ uint16_t saved_mru = 0;
+
+ vnic = &bp->vnic_info[vnic_id];
+ if (vnic->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "invalid queue configuration %d\n", vnic_id);
+ return NULL;
+ }
+
+ /* set the queue_bitmap */
+ BNXT_VNIC_BITMAP_SET(vnic->queue_bitmap, q_index);
+
+ rxq = bp->rx_queues[q_index];
+ if (rx_queue_state[q_index] == RTE_ETH_QUEUE_STATE_STOPPED)
+ rxq->rx_started = 0;
+ else
+ rxq->rx_started = 1;
+
+ vnic->rx_queue_cnt++;
+ vnic->start_grp_id = q_index;
+ vnic->end_grp_id = q_index + 1;
+ vnic->func_default = 0; /* This is not a default VNIC. */
+ bp->nr_vnics++;
+
+ /* Allocate vnic group for p4 platform */
+ rc = bnxt_vnic_grp_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to allocate vnic groups\n");
+ goto cleanup;
+ }
+
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
+ rc = bnxt_hwrm_vnic_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to allocate vnic %d\n", q_index);
+ goto cleanup;
+ }
+
+ /* store the mru so we can set it to zero in hw */
+ if (rxq->rx_started == 0) {
+ saved_mru = vnic->mru;
+ vnic->mru = 0;
+ }
+
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ if (rxq->rx_started == 0)
+ vnic->mru = saved_mru;
+
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to configure vnic %d\n", q_index);
+ goto cleanup;
+ }
+
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to configure vnic plcmode %d\n",
+ q_index);
+ goto cleanup;
+ }
+
+ vnic->ref_cnt++;
+ return vnic;
+
+cleanup:
+ bnxt_vnic_queue_delete(bp, vnic_id);
+ return NULL;
+}
+
+static inline int32_t
+bnxt_vnic_queue_db_lookup(struct bnxt *bp, uint64_t *q_list)
+{
+ /* lookup in the database to check if it is in use */
+ return rte_hash_lookup(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+}
+
+static inline int32_t
+bnxt_vnic_queue_db_del(struct bnxt *bp, uint64_t *q_list)
+{
+ return rte_hash_del_key(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+}
+
+static int32_t
+bnxt_vnic_queue_db_add(struct bnxt *bp, uint64_t *q_list)
+{
+ struct bnxt_vnic_info *vnic_info;
+ int32_t vnic_id, rc = -1;
+
+ vnic_id = rte_hash_add_key(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+
+ if (vnic_id < 0 || vnic_id >= bp->max_vnics) {
+ PMD_DRV_LOG(DEBUG, "unable to assign vnic index %d\n",
+ vnic_id);
+ return rc;
+ }
+
+ vnic_info = &bp->vnic_info[vnic_id];
+ if (vnic_info->fw_vnic_id != INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(DEBUG, "Invalid ring id for %d.\n", vnic_id);
+ return rc;
+ }
+ return vnic_id;
+}
+
+/* Function to validate the incoming rss configuration */
+static
+int32_t bnxt_vnic_queue_db_rss_validate(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ int32_t *vnic_idx)
+{
+ struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
+ int32_t rc = -EINVAL;
+ uint32_t idx = 0;
+ int32_t out_idx;
+
+ if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS)) {
+ PMD_DRV_LOG(ERR, "Error Rss is not supported on this port\n");
+ return rc;
+ }
+
+ /* rss queue is zero then use the default vnic */
+ if (rss_info->queue_num == 0) {
+ *vnic_idx = 0;
+ return 0;
+ }
+
+ /* Check to see if the queues id are in supported range */
+ if (rss_info->queue_num > bp->rx_nr_rings) {
+ PMD_DRV_LOG(ERR, "Error unsupported queue num.\n");
+ return rc;
+ }
+
+ /* validate the queue ids are in correct range */
+ for (idx = 0; idx < BNXT_VNIC_MAX_QUEUE_SIZE; idx++) {
+ if (BNXT_VNIC_BITMAP_GET(rss_info->queue_list, idx)) {
+ if (idx >= bp->rx_nr_rings) {
+ PMD_DRV_LOG(ERR,
+ "Error %d beyond support size %u\n",
+ idx, bp->rx_nr_rings);
+ return rc;
+ }
+ }
+ }
+
+ /* check if the vnic already exist */
+ out_idx = bnxt_vnic_queue_db_lookup(bp, rss_info->queue_list);
+ if (out_idx < 0 || out_idx >= bp->max_vnics)
+ return -ENOENT; /* entry not found */
+
+ /* found an entry */
+ *vnic_idx = out_idx;
+ return 0;
+}
+
+static void
+bnxt_vnic_rss_delete(struct bnxt *bp, uint16_t q_index)
+{
+ struct bnxt_vnic_info *vnic;
+
+ vnic = &bp->vnic_info[q_index];
+ if (vnic->rx_queue_cnt >= 1)
+ bnxt_hwrm_vnic_ctx_free(bp, vnic);
+
+ if (vnic->fw_vnic_id != INVALID_HW_RING_ID)
+ bnxt_hwrm_vnic_free(bp, vnic);
+
+ if (vnic->fw_grp_ids) {
+ rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
+ }
+
+ /* Update the vnic details for all the rx queues */
+ vnic->rx_queue_cnt = 0;
+ memset(vnic->queue_bitmap, 0, sizeof(vnic->queue_bitmap));
+
+ if (bp->nr_vnics)
+ bp->nr_vnics--;
+}
+
+/* The validation of the rss_info should be done before calling this function*/
+
+static struct bnxt_vnic_info *
+bnxt_vnic_rss_create(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t vnic_id)
+{
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ struct bnxt_vnic_info *vnic;
+ struct bnxt_rx_queue *rxq = NULL;
+ uint32_t idx, nr_ctxs, config_rss = 0;
+ uint16_t saved_mru = 0;
+ uint16_t active_q_cnt = 0;
+ int16_t first_q = -1;
+ int16_t end_q = -1;
+ int32_t rc = 0;
+
+ /* Assign the vnic to be used for this rss configuration */
+ vnic = &bp->vnic_info[vnic_id];
+
+ /* Update the vnic details for all the rx queues */
+ for (idx = 0; idx < BNXT_VNIC_MAX_QUEUE_SIZE; idx++) {
+ if (BNXT_VNIC_BITMAP_GET(rss_info->queue_list, idx)) {
+ rxq = bp->rx_queues[idx];
+ if (rx_queue_state[idx] ==
+ RTE_ETH_QUEUE_STATE_STOPPED) {
+ rxq->rx_started = 0;
+ } else {
+ rxq->rx_started = 1;
+ active_q_cnt++;
+ }
+ vnic->rx_queue_cnt++;
+
+ /* Update the queue list */
+ BNXT_VNIC_BITMAP_SET(vnic->queue_bitmap, idx);
+ if (first_q == -1)
+ first_q = idx;
+ end_q = idx;
+ }
+ }
+ vnic->start_grp_id = first_q;
+ vnic->end_grp_id = end_q + 1;
+ vnic->func_default = 0; /* This is not a default VNIC. */
+ bp->nr_vnics++;
+
+ /* Allocate vnic group for p4 platform */
+ rc = bnxt_vnic_grp_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to allocate vnic groups\n");
+ goto fail_cleanup;
+ }
+
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
+ /* Allocate the vnic in the firmware */
+ rc = bnxt_hwrm_vnic_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to allocate vnic %d\n", idx);
+ goto fail_cleanup;
+ }
+
+ /* Allocate the vnic rss context */
+ /* RSS table size in P5 is 512. Cap max Rx rings to same value */
+ nr_ctxs = bnxt_rss_ctxts(bp);
+ for (idx = 0; idx < nr_ctxs; idx++) {
+ rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, idx);
+ if (rc)
+ break;
+ }
+ if (rc) {
+ PMD_DRV_LOG(ERR,
+ "HWRM ctx %d alloc failure rc: %x\n", idx, rc);
+ goto fail_cleanup;
+ }
+ vnic->num_lb_ctxts = nr_ctxs;
+
+ saved_mru = vnic->mru;
+ if (!active_q_cnt)
+ vnic->mru = 0;
+
+ /* configure the vnic details in firmware */
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ vnic->mru = saved_mru;
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to configure vnic %d\n", idx);
+ goto fail_cleanup;
+ }
+
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to configure vnic plcmode %d\n",
+ idx);
+ goto fail_cleanup;
+ }
+
+ /* hwrm_type conversion */
+ vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_info->rss_types);
+ vnic->hash_mode = bnxt_rte_to_hwrm_hash_level(bp, rss_info->rss_types,
+ rss_info->rss_level);
+
+ /* configure the key */
+ if (!rss_info->key_len)
+ /* If hash key has not been specified, use random hash key.*/
+ bnxt_prandom_bytes(vnic->rss_hash_key, HW_HASH_KEY_SIZE);
+ else
+ memcpy(vnic->rss_hash_key, rss_info->key, rss_info->key_len);
+
+ /* Prepare the indirection table */
+ bnxt_vnic_populate_rss_table(bp, vnic);
+
+ /* check to see if there is at least one queue that is active */
+ for (idx = vnic->start_grp_id; idx < vnic->end_grp_id; idx++) {
+ if (bnxt_vnic_queue_id_is_valid(vnic, idx) &&
+ bp->rx_queues[idx]->rx_started) {
+ config_rss = 1;
+ break;
+ }
+ }
+
+ /* configure the rss table */
+ if (config_rss) {
+ rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+ if (rc) {
+ memset(vnic->rss_hash_key, 0, HW_HASH_KEY_SIZE);
+ PMD_DRV_LOG(ERR,
+ "Failed to configure vnic rss details %d\n",
+ idx);
+ goto fail_cleanup;
+ }
+ }
+
+ vnic->ref_cnt++;
+ return vnic;
+
+fail_cleanup:
+ bnxt_vnic_rss_delete(bp, idx);
+ return NULL;
+}
+
+int32_t
+bnxt_vnic_rss_queue_status_update(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
+ return 0;
+
+ if (!(vnic->rss_table && vnic->hash_type))
+ return 0;
+
+ /* Prepare the indirection table */
+ bnxt_vnic_populate_rss_table(bp, vnic);
+
+ /* configure the rss table */
+ if (bnxt_hwrm_vnic_rss_cfg(bp, vnic)) {
+ PMD_DRV_LOG(DEBUG, "Failed to update vnic rss details\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int32_t
+bnxt_vnic_rss_hash_algo_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic,
+ struct bnxt_vnic_rss_info *rss_info)
+{
+ uint8_t old_rss_hash_key[HW_HASH_KEY_SIZE] = { 0 };
+ uint16_t hash_type;
+ uint8_t hash_mode;
+ uint32_t apply = 0;
+
+ /* validate key length */
+ if (rss_info->key_len != 0 && rss_info->key_len != HW_HASH_KEY_SIZE) {
+ PMD_DRV_LOG(ERR,
+ "Invalid hashkey length, should be %d bytes\n",
+ HW_HASH_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ /* hwrm_type conversion */
+ hash_type = bnxt_rte_to_hwrm_hash_types(rss_info->rss_types);
+ hash_mode = bnxt_rte_to_hwrm_hash_level(bp, rss_info->rss_types,
+ rss_info->rss_level);
+ if (vnic->hash_mode != hash_mode ||
+ vnic->hash_type != hash_type) {
+ apply = 1;
+ vnic->hash_mode = hash_mode;
+ vnic->hash_type = hash_type;
+ }
+ /* Store the old hash key before programming the new one. It will
+ * be used to restore the old hash key when HWRM_VNIC_RSS_CFG
+ * fails.
+ */
+ memcpy(old_rss_hash_key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
+ if (rss_info->key_len != 0 && memcmp(rss_info->key, vnic->rss_hash_key,
+ HW_HASH_KEY_SIZE)) {
+ apply = 1;
+ memcpy(vnic->rss_hash_key, rss_info->key, HW_HASH_KEY_SIZE);
+ }
+
+ if (apply) {
+ if (bnxt_hwrm_vnic_rss_cfg(bp, vnic)) {
+ memcpy(vnic->rss_hash_key, old_rss_hash_key, HW_HASH_KEY_SIZE);
+ BNXT_TF_DBG(ERR, "Error configuring vnic RSS config\n");
+ return -EINVAL;
+ }
+ BNXT_TF_DBG(INFO, "Rss config successfully applied\n");
+ }
+ return 0;
+}
+
+int32_t bnxt_vnic_queue_db_deinit(struct bnxt *bp)
+{
+ if (bp->vnic_queue_db.rss_q_db != NULL)
+ rte_hash_free(bp->vnic_queue_db.rss_q_db);
+ return 0;
+}
+
+int32_t bnxt_vnic_queue_db_init(struct bnxt *bp)
+{
+ struct rte_hash_parameters hash_tbl_params = {0};
+ char hash_tbl_name[64] = {0};
+
+ /* choose the least supported value */
+ if (bp->rx_nr_rings > BNXT_VNIC_MAX_QUEUE_SIZE)
+ bp->vnic_queue_db.num_queues = BNXT_VNIC_MAX_QUEUE_SIZE;
+ else
+ bp->vnic_queue_db.num_queues = bp->rx_nr_rings;
+
+ /* create the hash table for the rss hash entries */
+ snprintf(hash_tbl_name, sizeof(hash_tbl_name),
+ "bnxt_rss_hash_%d", bp->eth_dev->data->port_id);
+ hash_tbl_params.name = hash_tbl_name;
+ hash_tbl_params.entries = (bp->max_vnics > BNXT_VNIC_MAX_SUPPORTED_ID) ?
+ BNXT_VNIC_MAX_SUPPORTED_ID : bp->max_vnics;
+ hash_tbl_params.key_len = BNXT_VNIC_MAX_QUEUE_SZ_IN_8BITS;
+ hash_tbl_params.socket_id = rte_socket_id();
+ bp->vnic_queue_db.rss_q_db = rte_hash_create(&hash_tbl_params);
+ if (bp->vnic_queue_db.rss_q_db == NULL) {
+ PMD_DRV_LOG(ERR, "Failed to create rss hash tbl\n");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+void bnxt_vnic_queue_db_update_dlft_vnic(struct bnxt *bp)
+{
+ struct bnxt_vnic_info *dflt_vnic;
+ uint64_t bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+ uint32_t idx;
+ int32_t vnic_id;
+
+ /* populate all the queue ids in the default vnic */
+ memset(bitmap, 0, sizeof(bitmap));
+ for (idx = 0; idx < bp->vnic_queue_db.num_queues; idx++)
+ BNXT_VNIC_BITMAP_SET(bitmap, idx);
+
+ vnic_id = bnxt_vnic_queue_db_add(bp, bitmap);
+ if (vnic_id < 0) {
+ PMD_DRV_LOG(ERR, "Unable to alloc vnic for default rss\n");
+ return;
+ }
+
+ dflt_vnic = bnxt_vnic_queue_db_get_vnic(bp, vnic_id);
+ if (dflt_vnic == NULL) {
+ PMD_DRV_LOG(ERR, "Invalid vnic for default rss %d\n", vnic_id);
+ return;
+ }
+ /* Update the default vnic structure */
+ bp->vnic_queue_db.dflt_vnic_id = vnic_id;
+ memcpy(dflt_vnic->queue_bitmap, bitmap, sizeof(bitmap));
+ dflt_vnic->rx_queue_cnt = bp->vnic_queue_db.num_queues;
+ dflt_vnic->ref_cnt++;
+}
+
+int32_t bnxt_vnic_queue_action_alloc(struct bnxt *bp,
+ uint16_t q_index,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid)
+{
+ uint64_t queue_list[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS] = {0};
+ struct bnxt_vnic_info *vnic_info;
+ int32_t idx;
+ int32_t rc = -EINVAL;
+
+ /* validate the given queue id */
+ if (q_index >= bp->rx_nr_rings || q_index >= BNXT_VNIC_MAX_QUEUE_SIZE) {
+ PMD_DRV_LOG(ERR, "invalid queue id should be less than %d\n",
+ bp->rx_nr_rings);
+ return rc;
+ }
+
+ /* Populate the queue list */
+ BNXT_VNIC_BITMAP_SET(queue_list, q_index);
+
+ /* check to see if the q_index is already in use */
+ idx = bnxt_vnic_queue_db_lookup(bp, queue_list);
+ if (idx < 0) {
+ /* Assign the vnic slot */
+ idx = bnxt_vnic_queue_db_add(bp, queue_list);
+ if (idx < 0) {
+ PMD_DRV_LOG(DEBUG, "Unable to alloc vnic for queue\n");
+ return rc;
+ }
+
+ /* Allocate a new one */
+ vnic_info = bnxt_vnic_queue_create(bp, idx, q_index);
+ if (!vnic_info) {
+ PMD_DRV_LOG(ERR, "failed to create vnic - %d\n",
+ q_index);
+ bnxt_vnic_queue_db_del(bp, queue_list);
+ return rc; /* failed */
+ }
+ } else {
+ vnic_info = bnxt_vnic_queue_db_get_vnic(bp, idx);
+ if (vnic_info == NULL) {
+ PMD_DRV_LOG(ERR, "Unable to lookup vnic for queue %d\n",
+ q_index);
+ return rc;
+ }
+ /* increment the reference count and return the vnic id */
+ vnic_info->ref_cnt++;
+ }
+ *vnic_idx = (uint16_t)idx;
+ *vnicid = vnic_info->fw_vnic_id;
+ return 0;
+}
+
+int32_t
+bnxt_vnic_queue_action_free(struct bnxt *bp, uint16_t vnic_id)
+{
+ struct bnxt_vnic_info *vnic_info;
+ int32_t rc = -EINVAL;
+ int32_t vnic_idx = vnic_id, idx;
+
+ /* validate the given vnic idx */
+ if (vnic_idx >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic idx %d\n", vnic_idx);
+ return rc;
+ }
+
+ /* validate the vnic info */
+ vnic_info = &bp->vnic_info[vnic_idx];
+ if (!vnic_info->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "Invalid vnic idx, no queues being used\n");
+ return rc;
+ }
+ if (vnic_info->ref_cnt) {
+ vnic_info->ref_cnt--;
+ if (!vnic_info->ref_cnt) {
+ idx = bnxt_vnic_queue_db_del(bp,
+ vnic_info->queue_bitmap);
+ /* Check to ensure there is no corruption */
+ if (idx != vnic_idx)
+ PMD_DRV_LOG(ERR, "bad vnic idx %d\n", vnic_idx);
+
+ bnxt_vnic_queue_delete(bp, vnic_idx);
+ }
+ }
+ return 0;
+}
+
+int32_t
+bnxt_vnic_rss_action_alloc(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid)
+{
+ struct bnxt_vnic_info *vnic_info = NULL;
+ int32_t rc = -EINVAL;
+ int32_t idx;
+
+ /* validate the given parameters */
+ rc = bnxt_vnic_queue_db_rss_validate(bp, rss_info, &idx);
+ if (rc == -EINVAL) {
+ PMD_DRV_LOG(ERR, "Failed to apply the rss action.\n");
+ return rc;
+ } else if (rc == -ENOENT) {
+ /* Allocate a new entry */
+ idx = bnxt_vnic_queue_db_add(bp, rss_info->queue_list);
+ if (idx < 0) {
+ PMD_DRV_LOG(DEBUG, "Unable to alloc vnic for rss\n");
+ return rc;
+ }
+ /* create the rss vnic */
+ vnic_info = bnxt_vnic_rss_create(bp, rss_info, idx);
+ if (!vnic_info) {
+ PMD_DRV_LOG(ERR, "Failed to create rss action.\n");
+ bnxt_vnic_queue_db_del(bp, rss_info->queue_list);
+ return rc;
+ }
+ } else {
+ vnic_info = bnxt_vnic_queue_db_get_vnic(bp, idx);
+ if (vnic_info == NULL) {
+ PMD_DRV_LOG(ERR, "Unable to lookup vnic for idx %d\n",
+ idx);
+ return rc;
+ }
+ /* increment the reference count and return the vnic id */
+ vnic_info->ref_cnt++;
+
+ /* check configuration has changed then update hash details */
+ rc = bnxt_vnic_rss_hash_algo_update(bp, vnic_info, rss_info);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to update the rss action.\n");
+ return rc;
+ }
+ }
+ *vnic_idx = idx;
+ *vnicid = vnic_info->fw_vnic_id;
+ return 0;
+}
+
+/* Delete the vnic associated with the given rss action index */
+int32_t
+bnxt_vnic_rss_action_free(struct bnxt *bp, uint16_t vnic_id)
+{
+ uint64_t bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+ struct bnxt_vnic_info *vnic_info;
+ int32_t rc = -EINVAL;
+ uint64_t *q_list;
+ int32_t idx = 0;
+
+ /* validate the given vnic id */
+ if (vnic_id >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic id %d\n", vnic_id);
+ return rc;
+ }
+
+ /* validate vnic info */
+ vnic_info = &bp->vnic_info[vnic_id];
+ if (!vnic_info->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "Invalid vnic id, not using any queues\n");
+ return rc;
+ }
+
+ if (vnic_info->ref_cnt) {
+ vnic_info->ref_cnt--;
+ if (!vnic_info->ref_cnt) {
+ if (bp->vnic_queue_db.dflt_vnic_id == vnic_id) {
+ /* in case of default queue, list can be
+ * changed by reta config so need a list
+ * with all queues populated.
+ */
+ memset(bitmap, 0, sizeof(bitmap));
+ for (idx = 0;
+ idx < bp->vnic_queue_db.num_queues;
+ idx++)
+ BNXT_VNIC_BITMAP_SET(bitmap, idx);
+ q_list = bitmap;
+ } else {
+ q_list = vnic_info->queue_bitmap;
+ }
+ idx = bnxt_vnic_queue_db_del(bp, q_list);
+
+ /* check to ensure there is no corruption */
+ if (idx != vnic_id)
+ PMD_DRV_LOG(ERR, "bad vnic idx %d\n", vnic_id);
+ bnxt_vnic_rss_delete(bp, vnic_id);
+ }
+ }
+ return 0;
+}
+
+int32_t
+bnxt_vnic_reta_config_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic_info,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ uint64_t l_bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS] = {0};
+ uint16_t i, sft, idx;
+ uint16_t q_id;
+
+ for (i = 0; i < reta_size; i++) {
+ idx = i / RTE_ETH_RETA_GROUP_SIZE;
+ sft = i % RTE_ETH_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ q_id = reta_conf[idx].reta[sft];
+ if (q_id >= bp->vnic_queue_db.num_queues ||
+ !bp->eth_dev->data->rx_queues[q_id]) {
+ PMD_DRV_LOG(ERR, "Queue id %d is invalid\n", q_id);
+ return -EINVAL;
+ }
+ BNXT_VNIC_BITMAP_SET(l_bitmap, q_id);
+ }
+ /* update the queue bitmap after the validation */
+ memcpy(vnic_info->queue_bitmap, l_bitmap, sizeof(l_bitmap));
+ return 0;
+}
+
+int32_t
+bnxt_vnic_queue_id_is_valid(struct bnxt_vnic_info *vnic_info,
+ uint16_t queue_id)
+{
+ if (BNXT_VNIC_BITMAP_GET(vnic_info->queue_bitmap, queue_id))
+ return 1;
+ return 0;
+}
+
+void
+bnxt_vnic_ring_grp_populate(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ uint32_t i;
+
+ /* check if ring group is supported */
+ if (!BNXT_HAS_RING_GRPS(bp))
+ return;
+
+ /* map ring groups to this vnic */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
+ if (bnxt_vnic_queue_id_is_valid(vnic, i) &&
+ bp->rx_queues[i]->rx_started)
+ vnic->fw_grp_ids[i] = bp->grp_info[i].fw_grp_id;
+
+ vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
+}
+
+void
+bnxt_vnic_rules_init(struct bnxt_vnic_info *vnic)
+{
+ vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
+ vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
+ vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
+}
+
+int32_t
+bnxt_vnic_mru_config(struct bnxt *bp, uint16_t new_mtu)
+{
+ struct bnxt_vnic_info *vnic;
+ uint16_t size = 0;
+ int32_t rc = 0;
+ uint32_t i;
+
+ for (i = 0; i < bp->max_vnics; i++) {
+ vnic = &bp->vnic_info[i];
+ if (vnic->fw_vnic_id == INVALID_VNIC_ID)
+ continue;
+
+ vnic->mru = BNXT_VNIC_MRU(new_mtu);
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ if (rc)
+ break;
+
+ size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
+ size -= RTE_PKTMBUF_HEADROOM;
+
+ if (size < new_mtu) {
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc)
+ break;
+ }
+ }
+ return rc;
+}
+
+struct bnxt_vnic_info *
+bnxt_vnic_queue_db_get_vnic(struct bnxt *bp, uint16_t vnic_idx)
+{
+ struct bnxt_vnic_info *vnic_info;
+
+ if (vnic_idx >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic index %u\n", vnic_idx);
+ return NULL;
+ }
+ vnic_info = &bp->vnic_info[vnic_idx];
+ return vnic_info;
+}
+
+struct bnxt_vnic_info *
+bnxt_vnic_queue_id_get_next(struct bnxt *bp, uint16_t queue_id,
+ uint16_t *vnic_idx)
+{
+ struct bnxt_vnic_info *vnic = NULL;
+ uint16_t i = *vnic_idx;
+
+ while (i < bp->max_vnics) {
+ vnic = &bp->vnic_info[i];
+ if (vnic->ref_cnt && BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ queue_id)) {
+ /* found a vnic that has the queue id */
+ *vnic_idx = i;
+ return vnic;
+ }
+ i++;
+ }
+ return NULL;
+}
+
+void
+bnxt_vnic_tpa_cfg(struct bnxt *bp, uint16_t queue_id, bool flag)
+{
+ struct bnxt_vnic_info *vnic = NULL;
+ uint16_t vnic_idx = 0;
+
+ while ((vnic = bnxt_vnic_queue_id_get_next(bp, queue_id,
+ &vnic_idx)) != NULL) {
+ bnxt_hwrm_vnic_tpa_cfg(bp, vnic, flag);
+ vnic_idx++;
+ }
+}
+
+inline struct bnxt_vnic_info *
+bnxt_get_default_vnic(struct bnxt *bp)
+{
+ return &bp->vnic_info[bp->vnic_queue_db.dflt_vnic_id];
+}
diff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h
index 9055b93c4b..4396d95bda 100644
--- a/drivers/net/bnxt/bnxt_vnic.h
+++ b/drivers/net/bnxt/bnxt_vnic.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -8,11 +8,29 @@
#include <sys/queue.h>
#include <stdbool.h>
+#include <rte_hash.h>
-#define INVALID_VNIC_ID ((uint16_t)-1)
+#define INVALID_VNIC_ID ((uint16_t)-1)
+#define BNXT_RSS_LEVEL_INNERMOST 0x2
+#define BNXT_RSS_LEVEL_OUTERMOST 0x1
+#define BNXT_VNIC_MAX_QUEUE_SIZE 256
+#define BNXT_VNIC_MAX_QUEUE_SZ_IN_8BITS (BNXT_VNIC_MAX_QUEUE_SIZE / 8)
+#define BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS (BNXT_VNIC_MAX_QUEUE_SIZE / 64)
+/* Limit the number of vnic creations*/
+#define BNXT_VNIC_MAX_SUPPORTED_ID 64
-#define BNXT_RSS_LEVEL_INNERMOST 0x2
-#define BNXT_RSS_LEVEL_OUTERMOST 0x1
+#define BNXT_HASH_MODE_DEFAULT HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT
+#define BNXT_HASH_MODE_INNERMOST \
+ (HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 | \
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2)
+#define BNXT_HASH_MODE_OUTERMOST \
+ (HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 | \
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2)
+#define BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp) \
+ ((BNXT_PF(bp) && !((bp)->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)) || \
+ (BNXT_VF(bp) && BNXT_VF_IS_TRUSTED(bp) && \
+ !((bp)->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF)) || \
+ (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)))
struct bnxt_vnic_info {
STAILQ_ENTRY(bnxt_vnic_info) next;
@@ -28,6 +46,7 @@ struct bnxt_vnic_info {
uint16_t mru;
uint16_t hash_type;
uint8_t hash_mode;
+ uint8_t prev_hash_mode;
const struct rte_memzone *rss_mz;
rte_iova_t rss_table_dma_addr;
uint16_t *rss_table;
@@ -50,11 +69,29 @@ struct bnxt_vnic_info {
bool func_default;
bool bd_stall;
bool rss_dflt_cr;
+ uint16_t ref_cnt;
+ uint64_t queue_bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
STAILQ_HEAD(, bnxt_filter_info) filter;
STAILQ_HEAD(, rte_flow) flow_list;
};
+struct bnxt_vnic_queue_db {
+ uint16_t num_queues;
+ uint16_t dflt_vnic_id;
+ struct rte_hash *rss_q_db;
+};
+
+/* RSS structure to pass values as an structure argument*/
+struct bnxt_vnic_rss_info {
+ uint32_t rss_level;
+ uint64_t rss_types;
+ uint32_t key_len; /**< Hash key length in bytes. */
+ const uint8_t *key; /**< Hash key. */
+ uint32_t queue_num; /**< Number of entries in @p queue. */
+ uint64_t queue_list[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+};
+
struct bnxt;
int bnxt_free_vnic(struct bnxt *bp, struct bnxt_vnic_info *vnic,
int pool);
@@ -69,4 +106,39 @@ void bnxt_prandom_bytes(void *dest_ptr, size_t len);
uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type);
int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl);
uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode);
+
+int32_t bnxt_vnic_queue_db_init(struct bnxt *bp);
+int32_t bnxt_vnic_queue_db_deinit(struct bnxt *bp);
+
+void bnxt_vnic_queue_db_update_dlft_vnic(struct bnxt *bp);
+int32_t
+bnxt_vnic_rss_queue_status_update(struct bnxt *bp, struct bnxt_vnic_info *vnic);
+
+int32_t bnxt_vnic_queue_action_alloc(struct bnxt *bp, uint16_t q_index,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid);
+int32_t bnxt_vnic_queue_action_free(struct bnxt *bp, uint16_t q_index);
+
+int32_t bnxt_vnic_rss_action_alloc(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t *queue_id,
+ uint16_t *vnicid);
+int32_t bnxt_vnic_rss_action_free(struct bnxt *bp, uint16_t q_index);
+
+int32_t bnxt_vnic_reta_config_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic_info,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+int32_t bnxt_vnic_queue_id_is_valid(struct bnxt_vnic_info *vnic_info,
+ uint16_t queue_id);
+void bnxt_vnic_ring_grp_populate(struct bnxt *bp, struct bnxt_vnic_info *vnic);
+void bnxt_vnic_rules_init(struct bnxt_vnic_info *vnic);
+int32_t bnxt_vnic_mru_config(struct bnxt *bp, uint16_t new_mtu);
+struct bnxt_vnic_info *bnxt_vnic_queue_db_get_vnic(struct bnxt *bp,
+ uint16_t vnic_idx);
+struct bnxt_vnic_info *
+bnxt_vnic_queue_id_get_next(struct bnxt *bp, uint16_t queue_id,
+ uint16_t *vnic_idx);
+void bnxt_vnic_tpa_cfg(struct bnxt *bp, uint16_t queue_id, bool flag);
+
#endif
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index ead03a5ea3..c7a0d5f6c9 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -25,6 +25,8 @@ endforeach
headers = files('rte_pmd_bnxt.h')
+deps += ['hash']
+
sources = files(
'bnxt_cpr.c',
'bnxt_ethdev.c',
@@ -41,7 +43,6 @@ sources = files(
'bnxt_util.c',
'bnxt_vnic.c',
'bnxt_reps.c',
-
'rte_pmd_bnxt.c',
)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
index b09cccedf5..474854d59b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2021-2021 Broadcom
+ * Copyright(c) 2021-2023 Broadcom
* All rights reserved.
*/
@@ -17,6 +17,36 @@
#include "bnxt_tf_common.h"
#include "bnxt_tf_pmd_shim.h"
+int
+bnxt_tunnel_dst_port_free(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type)
+{
+ return bnxt_hwrm_tunnel_dst_port_free(bp,
+ port,
+ type);
+}
+
+int
+bnxt_tunnel_dst_port_alloc(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type)
+{
+ return bnxt_hwrm_tunnel_dst_port_alloc(bp,
+ port,
+ type);
+}
+
+int
+bnxt_tunnel_upar_id_get(struct bnxt *bp,
+ uint8_t type,
+ uint8_t *upar_id)
+{
+ return bnxt_hwrm_tunnel_upar_id_get(bp,
+ upar_id,
+ type);
+}
+
struct bnxt *
bnxt_pmd_get_bp(uint16_t port)
{
@@ -59,7 +89,7 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms)
BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
return rc;
}
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
if (vnic == NULL) {
BNXT_TF_DBG(ERR, "default vnic not available for %u\n",
parms->port_id);
@@ -108,7 +138,6 @@ static int32_t glob_error_fn(const char *epath, int32_t eerrno)
return 0;
}
-
static int32_t ulp_pmd_get_mac_by_pci(const char *pci_name, uint8_t *mac)
{
char path[ULP_FILE_PATH_SIZE], dev_str[ULP_FILE_PATH_SIZE];
@@ -244,7 +273,7 @@ bnxt_pmd_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
bp = eth_dev->data->dev_private;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
return vnic->fw_vnic_id;
}
@@ -343,7 +372,6 @@ bnxt_pmd_get_vport(uint16_t port_id)
return (1 << bnxt_pmd_get_phy_port_id(port_id));
}
-
int32_t
bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
{
@@ -363,7 +391,7 @@ bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_UCAST;
@@ -376,3 +404,211 @@ bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
return rc;
}
+
+int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id)
+{
+ struct bnxt *bp = NULL;
+ uint16_t q_index;
+ struct ulp_rte_act_prop *ap = parms->act_prop;
+
+ bp = bnxt_pmd_get_bp(parms->port_id);
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
+ return -EINVAL;
+ }
+
+ memcpy(&q_index, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX],
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX);
+
+ return bnxt_vnic_queue_action_alloc(bp, q_index, vnic_idx, vnic_id);
+}
+
+int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx)
+{
+ struct bnxt *bp = NULL;
+
+ bp = tfp->bp;
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp\n");
+ return -EINVAL;
+ }
+ return bnxt_vnic_queue_action_free(bp, vnic_idx);
+}
+
+int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id)
+{
+ struct bnxt *bp = NULL;
+ struct bnxt_vnic_rss_info rss_info = {0};
+ struct ulp_rte_act_prop *ap = parms->act_prop;
+
+ bp = bnxt_pmd_get_bp(parms->port_id);
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
+ return -EINVAL;
+ }
+
+ /* get the details */
+ memset(&rss_info, 0, sizeof(rss_info));
+ memcpy(&rss_info.rss_types,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES],
+ BNXT_ULP_ACT_PROP_SZ_RSS_TYPES);
+ memcpy(&rss_info.rss_level,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL],
+ BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL);
+ memcpy(&rss_info.key_len,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN],
+ BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN);
+ if (rss_info.key_len)
+ rss_info.key = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY];
+ memcpy(&rss_info.queue_num,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM],
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM);
+
+ /* Validate the size of the queue list */
+ if (sizeof(rss_info.queue_list) < BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE) {
+ BNXT_TF_DBG(ERR, "Mismatch of RSS queue size in template\n");
+ return -EINVAL;
+ }
+ memcpy(rss_info.queue_list,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE],
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE);
+
+ return bnxt_vnic_rss_action_alloc(bp, &rss_info, vnic_idx, vnic_id);
+}
+
+int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx)
+{
+ struct bnxt *bp = tfp->bp;
+
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp\n");
+ return -EINVAL;
+ }
+ return bnxt_vnic_rss_action_free(bp, vnic_idx);
+}
+
+#define ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT 16
+#define ULP_GLOBAL_TUNNEL_PORT_ID_MASK ((uint16_t)0xffff)
+#define ULP_GLOBAL_TUNNEL_UPARID_SHIFT 8
+#define ULP_GLOBAL_TUNNEL_UPARID_MASK ((uint16_t)0xff)
+#define ULP_GLOBAL_TUNNEL_TYPE_SHIFT 0
+#define ULP_GLOBAL_TUNNEL_TYPE_MASK ((uint16_t)0xffff)
+
+/* Extracts the dpdk port id and tunnel type from the handle */
+static void
+bnxt_pmd_global_reg_hndl_to_data(uint32_t handle, uint16_t *port,
+ uint8_t *upar_id, uint8_t *type)
+{
+ *type = (handle >> ULP_GLOBAL_TUNNEL_TYPE_SHIFT) &
+ ULP_GLOBAL_TUNNEL_TYPE_MASK;
+ *upar_id = (handle >> ULP_GLOBAL_TUNNEL_UPARID_SHIFT) &
+ ULP_GLOBAL_TUNNEL_UPARID_MASK;
+ *port = (handle >> ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT) &
+ ULP_GLOBAL_TUNNEL_PORT_ID_MASK;
+}
+
+/* Packs the dpdk port id and tunnel type in the handle */
+static void
+bnxt_pmd_global_reg_data_to_hndl(uint16_t port_id, uint8_t upar_id,
+ uint8_t type, uint32_t *handle)
+{
+ *handle = (port_id & ULP_GLOBAL_TUNNEL_PORT_ID_MASK) <<
+ ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT;
+ *handle |= (upar_id & ULP_GLOBAL_TUNNEL_UPARID_MASK) <<
+ ULP_GLOBAL_TUNNEL_UPARID_SHIFT;
+ *handle |= (type & ULP_GLOBAL_TUNNEL_TYPE_MASK) <<
+ ULP_GLOBAL_TUNNEL_TYPE_SHIFT;
+}
+
+static struct bnxt_global_tunnel_info
+ ulp_global_tunnel_db[BNXT_GLOBAL_REGISTER_TUNNEL_MAX] = {{0}};
+/* Sets or resets the tunnel ports.
+ * If dport == 0, then the port_id and type are retrieved from the handle.
+ * otherwise, the incoming port_id, type, and dport are used.
+ * The type is enum ulp_mapper_ulp_global_tunnel_type
+ */
+int32_t
+bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
+ uint16_t udp_port, uint32_t *handle)
+{
+ uint16_t lport_id, ldport;
+ uint8_t hwtype, ltype, lupar_id;
+ struct bnxt *bp;
+ int32_t rc = 0;
+
+ /* convert to HWRM type */
+ switch (type) {
+ case BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN:
+ hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Tunnel Type (%d) invalid\n", type);
+ return -EINVAL;
+ }
+
+ if (!udp_port) {
+ /* Free based on the handle */
+ if (!handle) {
+ BNXT_TF_DBG(ERR, "Free with invalid handle\n");
+ return -EINVAL;
+ }
+ bnxt_pmd_global_reg_hndl_to_data(*handle, &lport_id,
+ &lupar_id, <ype);
+
+ bp = bnxt_pmd_get_bp(lport_id);
+ if (!bp) {
+ BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n",
+ lport_id);
+ return -EINVAL;
+ }
+
+ if (!ulp_global_tunnel_db[ltype].ref_cnt)
+ return 0;
+ ldport = ulp_global_tunnel_db[ltype].dport;
+ rc = bnxt_hwrm_tunnel_dst_port_free(bp, ldport, hwtype);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Unable to free tunnel dst port (%d)\n",
+ ldport);
+ return rc;
+ }
+ ulp_global_tunnel_db[ltype].ref_cnt--;
+ if (ulp_global_tunnel_db[ltype].ref_cnt == 0)
+ ulp_global_tunnel_db[ltype].dport = 0;
+ } else {
+ bp = bnxt_pmd_get_bp(port_id);
+ if (!bp) {
+ BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n",
+ port_id);
+ return -EINVAL;
+ }
+
+ rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_port, hwtype);
+ if (!rc) {
+ ulp_global_tunnel_db[type].ref_cnt++;
+ ulp_global_tunnel_db[type].dport = udp_port;
+ bnxt_pmd_global_reg_data_to_hndl(port_id, 0,
+ type, handle);
+ }
+ }
+ return rc;
+}
+
+#define BNXT_ULP_HOT_UP_DYNAMIC_ENV_VAR "BNXT_ULP_T_HA_SUPPORT"
+/* This function queries the linux shell variable to determine
+ * whether Hot upgrade should be disabled or not.
+ * If BNXT_ULP_T_HA_SUPPORT is set to zero explicitly then
+ * hotupgrade is disabled.
+ */
+int32_t bnxt_pmd_get_hot_upgrade_env(void)
+{
+ char *env;
+ int32_t hot_up = 1;
+
+ env = getenv(BNXT_ULP_HOT_UP_DYNAMIC_ENV_VAR);
+ if (env && strcmp(env, "0") == 0)
+ hot_up = 0;
+ return hot_up;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index d6d7a1f0af..b76e4b849d 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2021-2021 Broadcom
+ * Copyright(c) 2021-2023 Broadcom
* All rights reserved.
*/
@@ -9,6 +9,19 @@
#include "bnxt_tf_common.h"
#include "ulp_mapper.h"
+/* Simple structure to manage the custom global tunnel */
+struct bnxt_global_tunnel_info {
+ uint16_t dport;
+ uint16_t ref_cnt;
+};
+
+/* Internal Tunnel type, */
+enum bnxt_global_register_tunnel_type {
+ BNXT_GLOBAL_REGISTER_TUNNEL_UNUSED = 0,
+ BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN,
+ BNXT_GLOBAL_REGISTER_TUNNEL_MAX
+};
+
int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms);
int32_t bnxt_pmd_get_parent_mac_addr(struct bnxt_ulp_mapper_parms *parms,
uint8_t *mac);
@@ -25,4 +38,24 @@ uint16_t bnxt_pmd_get_phy_port_id(uint16_t port);
uint16_t bnxt_pmd_get_vport(uint16_t port);
enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port);
int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev);
+int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id);
+int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx);
+int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id);
+int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx);
+int32_t bnxt_tunnel_dst_port_free(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type);
+int32_t bnxt_tunnel_dst_port_alloc(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type);
+int32_t
+bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
+ uint16_t udp_port, uint32_t *handle);
+int32_t
+bnxt_tunnel_upar_id_get(struct bnxt *bp,
+ uint8_t type,
+ uint8_t *upar_id);
+int32_t bnxt_pmd_get_hot_upgrade_env(void);
#endif /* _BNXT_TF_PMD_ABSTRACT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 109bd0652a..08eb0c6063 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -78,7 +78,7 @@ bnxt_ulp_devid_get(struct bnxt *bp,
if (BNXT_STINGRAY(bp))
*ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY;
else
- /* Assuming Whitney */
+ /* Assuming P4 */
*ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS;
return 0;
@@ -340,12 +340,62 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+/* Function to set the hot upgrade support into the context */
+static int
+bnxt_ulp_multi_shared_session_support_set(struct bnxt *bp,
+ enum bnxt_ulp_device_id devid,
+ uint32_t fw_hu_update)
+{
+ struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
+ struct tf_get_version_parms v_params = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+ int32_t new_fw = 0;
+
+ v_params.device_type = bnxt_ulp_cntxt_convert_dev_id(devid);
+ v_params.bp = bp;
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_version(tfp, &v_params);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get tf version.\n");
+ return rc;
+ }
+
+ if (v_params.major == 1 && v_params.minor == 0 &&
+ v_params.update == 1) {
+ new_fw = 1;
+ }
+ /* if the version update is greater than 0 then set support for
+ * multiple version
+ */
+ if (new_fw) {
+ ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_MULTI_SHARED_SUPPORT;
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED;
+ }
+ if (!new_fw && fw_hu_update) {
+ ulp_ctx->cfg_data->ulp_flags &= ~BNXT_ULP_HIGH_AVAIL_ENABLED;
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED |
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC;
+ }
+
+ if (!new_fw && !fw_hu_update) {
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED |
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC;
+ }
+
+ return rc;
+}
+
int32_t
bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
uint8_t app_id, uint32_t dev_id)
{
struct bnxt_ulp_app_capabilities_info *info;
- uint32_t num = 0;
+ uint32_t num = 0, fw = 0;
uint16_t i;
bool found = false;
struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
@@ -375,15 +425,49 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY)
ulp_ctx->cfg_data->ulp_flags |=
BNXT_ULP_APP_UNICAST_ONLY;
+ if (info[i].flags & BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT)
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_TOS_PROTO_SUPPORT;
+ if (info[i].flags & BNXT_ULP_APP_CAP_BC_MC_SUPPORT)
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_BC_MC_SUPPORT;
if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) {
/* Enable socket direction only if MR is enabled in fw*/
if (BNXT_MULTIROOT_EN(bp)) {
ulp_ctx->cfg_data->ulp_flags |=
BNXT_ULP_APP_SOCKET_DIRECT;
- BNXT_TF_DBG(DEBUG,
- "Socket Direct feature is enabled");
+ BNXT_TF_DBG(INFO,
+ "Socket Direct feature is enabled\n");
}
}
+ if (info[i].flags & BNXT_ULP_APP_CAP_HA_DYNAMIC) {
+ /* Read the environment variable to determine hot up */
+ if (!bnxt_pmd_get_hot_upgrade_env()) {
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_HA_DYNAMIC;
+ /* reset Hot upgrade, dynamically disabled */
+ ulp_ctx->cfg_data->ulp_flags &=
+ ~BNXT_ULP_HIGH_AVAIL_ENABLED;
+ ulp_ctx->cfg_data->def_session_type =
+ BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA;
+ BNXT_TF_DBG(INFO, "Hot upgrade disabled.\n");
+ }
+ }
+
+ bnxt_ulp_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port);
+ bnxt_ulp_vxlan_port_set(ulp_ctx, info[i].vxlan_port);
+
+ /* set the shared session support from firmware */
+ fw = info[i].upgrade_fw_update;
+ if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags) &&
+ bnxt_ulp_multi_shared_session_support_set(bp, dev_id, fw)) {
+ BNXT_TF_DBG(ERR,
+ "Unable to get shared session support\n");
+ return -EINVAL;
+ }
+ bnxt_ulp_ha_reg_set(ulp_ctx, info[i].ha_reg_state,
+ info[i].ha_reg_cnt);
+ ulp_ctx->cfg_data->ha_pool_id = info[i].ha_pool_id;
}
if (!found) {
BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",
@@ -1027,6 +1111,11 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ if (BNXT_TESTPMD_EN(bp)) {
+ ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
+ BNXT_TF_DBG(ERR, "Enabled Testpmd forward mode\n");
+ }
+
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -1055,7 +1144,6 @@ ulp_ctx_init(struct bnxt *bp,
}
bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
-
/* Open the ulp session. */
rc = ulp_ctx_session_open(bp, session);
if (rc)
@@ -1181,7 +1269,7 @@ ulp_ctx_attach(struct bnxt *bp,
tfp->session = NULL;
return rc;
}
-
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
}
@@ -1427,7 +1515,8 @@ bnxt_ulp_deinit(struct bnxt *bp,
return;
ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx);
- if (ha_enabled && session->session_opened) {
+ if (ha_enabled &&
+ bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) {
int32_t rc = ulp_ha_mgr_close(bp->ulp_ctx);
if (rc)
BNXT_TF_DBG(ERR, "Failed to close HA (%d)\n", rc);
@@ -1490,6 +1579,7 @@ bnxt_ulp_init(struct bnxt *bp,
struct bnxt_ulp_session_state *session)
{
int rc;
+ uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
/* Allocate and Initialize the ulp context. */
rc = ulp_ctx_init(bp, session);
@@ -1584,6 +1674,13 @@ bnxt_ulp_init(struct bnxt *bp,
goto jump_to_error;
}
}
+
+ rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
+ return rc;
+ }
+
BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
return rc;
@@ -1592,6 +1689,30 @@ bnxt_ulp_init(struct bnxt *bp,
return rc;
}
+static int
+ulp_cust_vxlan_alloc(struct bnxt *bp)
+{
+ int rc = 0;
+
+ if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_alloc(bp,
+ bp->ulp_ctx->cfg_data->vxlan_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to set global vxlan port\n");
+ }
+
+ if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_alloc(bp,
+ bp->ulp_ctx->cfg_data->vxlan_ip_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to set global custom vxlan_ip port\n");
+ }
+
+ return rc;
+}
+
/*
* When a port is initialized by dpdk. This functions sets up
* the port specific details.
@@ -1686,6 +1807,7 @@ bnxt_ulp_port_init(struct bnxt *bp)
BNXT_TF_DBG(ERR, "Failed to update port database\n");
goto jump_to_error;
}
+
/* create the default rules */
rc = bnxt_ulp_create_df_rules(bp);
if (rc) {
@@ -1711,6 +1833,10 @@ bnxt_ulp_port_init(struct bnxt *bp)
}
}
+ rc = ulp_cust_vxlan_alloc(bp);
+ if (rc)
+ goto jump_to_error;
+
return rc;
jump_to_error:
@@ -1718,6 +1844,28 @@ bnxt_ulp_port_init(struct bnxt *bp)
return rc;
}
+static void
+ulp_cust_vxlan_free(struct bnxt *bp)
+{
+ int rc;
+
+ if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_free(bp,
+ bp->ulp_ctx->cfg_data->vxlan_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to clear global vxlan port\n");
+ }
+
+ if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_free(bp,
+ bp->ulp_ctx->cfg_data->vxlan_ip_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to clear global custom vxlan port\n");
+ }
+}
+
/*
* When a port is de-initialized by dpdk. This functions clears up
* the port specific details.
@@ -1770,6 +1918,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
if (bp->ulp_ctx->cfg_data && bp->ulp_ctx->cfg_data->ref_cnt) {
bp->ulp_ctx->cfg_data->ref_cnt--;
if (bp->ulp_ctx->cfg_data->ref_cnt) {
+ /* Free tunnel configurations */
+ ulp_cust_vxlan_free(bp);
+
/* free the port details */
/* Free the default flow rule associated to this port */
bnxt_ulp_destroy_df_rules(bp, false);
@@ -2201,6 +2352,45 @@ bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx)
pthread_mutex_unlock(&ulp_ctx->cfg_data->flow_db_lock);
}
+/* Function to extract the action type from the shared action handle. */
+int32_t
+bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle,
+ uint32_t *action_handle_type)
+{
+ if (!action_handle_type)
+ return -EINVAL;
+
+ *action_handle_type = (uint32_t)(((uint64_t)handle >> 32) & 0xffffffff);
+ if (*action_handle_type >= BNXT_ULP_GEN_TBL_MAX_SZ)
+ return -EINVAL;
+
+ return 0;
+}
+
+/* Function to extract the direction from the shared action handle. */
+int32_t
+bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle,
+ uint32_t *dir)
+{
+ uint32_t shared_type;
+ int32_t ret = 0;
+
+ ret = bnxt_get_action_handle_type(handle, &shared_type);
+ if (ret)
+ return ret;
+
+ *dir = shared_type & 0x1 ? BNXT_ULP_DIR_EGRESS : BNXT_ULP_DIR_INGRESS;
+
+ return ret;
+}
+
+/* Function to extract the action index from the shared action handle. */
+uint32_t
+bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle)
+{
+ return (uint32_t)((uint64_t)handle & 0xffffffff);
+}
+
/* Function to set the ha info into the context */
int32_t
bnxt_ulp_cntxt_ptr2_ha_info_set(struct bnxt_ulp_context *ulp_ctx,
@@ -2306,6 +2496,13 @@ bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
return ulp->cfg_data->app_tun;
}
+/* Function to get the truflow app id. This defined in the build file */
+uint32_t
+bnxt_ulp_default_app_id_get(void)
+{
+ return BNXT_TF_APP_ID;
+}
+
/* Function to convert ulp dev id to regular dev id. */
uint32_t
bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
@@ -2329,6 +2526,53 @@ bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
return type;
}
+/* This function sets the IF table index for the
+ * Application to poll to get the hot upgrade state and count details from
+ * the firmware.
+ */
+int32_t
+bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx,
+ uint8_t state, uint8_t cnt)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx)) {
+ ulp_ctx->cfg_data->hu_reg_state = state;
+ ulp_ctx->cfg_data->hu_reg_cnt = cnt;
+ } else {
+ ulp_ctx->cfg_data->hu_reg_state = ULP_HA_IF_TBL_IDX;
+ ulp_ctx->cfg_data->hu_reg_cnt = ULP_HA_CLIENT_CNT_IF_TBL_IDX;
+ }
+ return 0;
+}
+
+/* This function gets the IF table index for the
+ * application to poll to get the application hot upgrade state from
+ * the firmware.
+ */
+uint32_t
+bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (uint32_t)ulp_ctx->cfg_data->hu_reg_state;
+}
+
+/* This function gets the IF table index for the
+ * Application to poll to get the application count from
+ * the firmware.
+ */
+uint32_t
+bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (uint32_t)ulp_ctx->cfg_data->hu_reg_cnt;
+}
+
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type)
{
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 9b30851b13..53d76e1465 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -386,4 +386,5 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 55885d1b8c..ad04644db4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -14,6 +14,8 @@
#include "ulp_ha_mgr.h"
#include "ulp_tun.h"
#include <rte_malloc.h>
+#include "ulp_template_db_tbl.h"
+#include "tfp.h"
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -78,6 +80,17 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
#endif
}
+static inline void
+bnxt_ulp_init_parser_cf_defaults(struct ulp_rte_parser_params *params,
+ uint16_t port_id)
+{
+ /* Set up defaults for Comp field */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_INCOMING_IF, port_id);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_DEV_PORT_ID, port_id);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG,
+ BNXT_ULP_INVALID_SVIF_VAL);
+}
+
void
bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
struct ulp_rte_parser_params *params,
@@ -130,6 +143,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG,
1);
+ } else {
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED,
+ 1);
}
/* Update the socket direct flag */
@@ -197,13 +214,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
/* Set the flow attributes */
bnxt_ulp_set_dir_attributes(¶ms, attr);
- /* copy the device port id and direction for further processing */
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_INCOMING_IF,
- dev->data->port_id);
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DEV_PORT_ID,
- dev->data->port_id);
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_SVIF_FLAG,
- BNXT_ULP_INVALID_SVIF_VAL);
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
/* Get the function id */
if (ulp_port_db_port_func_id_get(ulp_ctx,
@@ -320,6 +331,7 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
/* Set the flow attributes */
bnxt_ulp_set_dir_attributes(¶ms, attr);
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
/* Parse the rte flow pattern */
ret = bnxt_ulp_rte_parser_hdr_parse(pattern, ¶ms);
@@ -494,6 +506,256 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+static int32_t
+bnxt_ulp_action_handle_chk_args(const struct rte_flow_action *action,
+ const struct rte_flow_indir_action_conf *conf)
+{
+ if (!action || !conf)
+ return BNXT_TF_RC_ERROR;
+ /* shared action only allowed to have one direction */
+ if (conf->ingress == 1 && conf->egress == 1)
+ return BNXT_TF_RC_ERROR;
+ /* shared action must have at least one direction */
+ if (conf->ingress == 0 && conf->egress == 0)
+ return BNXT_TF_RC_ERROR;
+ return BNXT_TF_RC_SUCCESS;
+}
+
+static inline void
+bnxt_ulp_set_action_handle_dir_attr(struct ulp_rte_parser_params *params,
+ const struct rte_flow_indir_action_conf *conf)
+{
+ if (conf->ingress == 1)
+ params->dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+ else if (conf->egress == 1)
+ params->dir_attr |= BNXT_ULP_FLOW_ATTR_EGRESS;
+}
+
+static struct rte_flow_action_handle *
+bnxt_ulp_action_handle_create(struct rte_eth_dev *dev,
+ const struct rte_flow_indir_action_conf *conf,
+ const struct rte_flow_action *action,
+ struct rte_flow_error *error)
+{
+ enum bnxt_ulp_intf_type port_type = BNXT_ULP_INTF_TYPE_INVALID;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ struct ulp_rte_parser_params params;
+ struct bnxt_ulp_context *ulp_ctx;
+ uint32_t act_tid;
+ uint16_t func_id;
+ uint32_t ifindex;
+ int ret = BNXT_TF_RC_ERROR;
+ const struct rte_flow_action actions[2] = {
+ {
+ .type = action->type,
+ .conf = action->conf
+ },
+ {
+ .type = RTE_FLOW_ACTION_TYPE_END
+ }
+ };
+
+ if (bnxt_ulp_action_handle_chk_args(action, conf) != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ goto parse_error;
+ }
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+
+ ULP_BITMAP_SET(params.act_bitmap.bits, BNXT_ULP_ACT_BIT_SHARED);
+
+ /* Set the shared action direction attribute */
+ bnxt_ulp_set_action_handle_dir_attr(¶ms, conf);
+
+ /* perform the conversion from dpdk port to bnxt ifindex */
+ if (ulp_port_db_dev_port_to_ulp_index(ulp_ctx,
+ dev->data->port_id,
+ &ifindex)) {
+ BNXT_TF_DBG(ERR, "Port id is not valid\n");
+ goto parse_error;
+ }
+ port_type = ulp_port_db_port_type_get(ulp_ctx, ifindex);
+ if (port_type == BNXT_ULP_INTF_TYPE_INVALID) {
+ BNXT_TF_DBG(ERR, "Port type is not valid\n");
+ goto parse_error;
+ }
+
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
+
+ /* Emulating the match port for direction processing */
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_MATCH_PORT_TYPE,
+ port_type);
+
+ if ((params.dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS) &&
+ port_type == BNXT_ULP_INTF_TYPE_VF_REP) {
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ } else {
+ /* Assign the input direction */
+ if (params.dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS)
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_INGRESS);
+ else
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ }
+
+ /* Parse the shared action */
+ ret = bnxt_ulp_rte_parser_act_parse(actions, ¶ms);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ /* Perform the rte flow post process */
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
+ if (ret == BNXT_TF_RC_ERROR)
+ goto parse_error;
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ return (struct rte_flow_action_handle *)((uintptr_t)mparms.shared_hndl);
+
+parse_error:
+ rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "Failed to create shared action.");
+ return NULL;
+}
+
+static int
+bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev,
+ struct rte_flow_action_handle *shared_hndl,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ struct bnxt_ulp_shared_act_info *act_info;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop;
+ struct bnxt_ulp_context *ulp_ctx;
+ enum bnxt_ulp_direction_type dir;
+ uint32_t act_tid, act_info_entries;
+ int ret = BNXT_TF_RC_ERROR;
+ uint32_t shared_action_type;
+ uint64_t tmp64;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ goto parse_error;
+ }
+
+ if (!shared_hndl) {
+ BNXT_TF_DBG(ERR, "Invalid argument of shared handle\n");
+ goto parse_error;
+ }
+
+ act_prop = ¶ms.act_prop;
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+
+ if (bnxt_ulp_cntxt_app_id_get(ulp_ctx, ¶ms.app_id)) {
+ BNXT_TF_DBG(ERR, "failed to get the app id\n");
+ goto parse_error;
+ }
+ /* The template will delete the entry if there are no references */
+ if (bnxt_get_action_handle_type(shared_hndl, &shared_action_type)) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ goto parse_error;
+ }
+
+ act_info_entries = 0;
+ act_info = bnxt_ulp_shared_act_info_get(&act_info_entries);
+ if (shared_action_type >= act_info_entries || !act_info) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ goto parse_error;
+ }
+
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ act_info[shared_action_type].act_bitmask);
+ ULP_BITMAP_SET(params.act_bitmap.bits, BNXT_ULP_ACT_BIT_DELETE);
+
+ ret = bnxt_get_action_handle_direction(shared_hndl, &dir);
+ if (ret) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle dir\n");
+ goto parse_error;
+ }
+
+ if (dir == BNXT_ULP_DIR_EGRESS) {
+ params.dir_attr = BNXT_ULP_FLOW_ATTR_EGRESS;
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+ } else {
+ params.dir_attr = BNXT_ULP_FLOW_ATTR_INGRESS;
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_ING);
+ }
+
+ tmp64 = tfp_cpu_to_be_64((uint64_t)
+ bnxt_get_action_handle_index(shared_hndl));
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE],
+ &tmp64, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE);
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+ if (ret)
+ goto parse_error;
+
+ return 0;
+
+parse_error:
+ rte_flow_error_set(error, BNXT_TF_RC_ERROR,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "Failed to destroy shared action.");
+ return -EINVAL;
+}
+
/* Tunnel offload Apis */
#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
@@ -685,6 +947,8 @@ const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
.isolate = NULL,
+ .action_handle_create = bnxt_ulp_action_handle_create,
+ .action_handle_destroy = bnxt_ulp_action_handle_destroy,
/* Tunnel offload callbacks */
.tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
.tunnel_match = bnxt_ulp_tunnel_match,
diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build
index 71094b9974..c7df7e42f1 100644
--- a/drivers/net/bnxt/tf_ulp/meson.build
+++ b/drivers/net/bnxt/tf_ulp/meson.build
@@ -1,28 +1,29 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2021 Broadcom
+# Copyright(c) 2023 Broadcom
#Include the folder for headers
includes += include_directories('.')
+cflags += '-DBNXT_TF_APP_ID=0'
#Add the source files
sources += files(
+ 'bnxt_tf_pmd_shim.c',
'bnxt_ulp.c',
- 'ulp_mark_mgr.c',
- 'ulp_flow_db.c',
- 'ulp_utils.c',
- 'ulp_mapper.c',
- 'ulp_matcher.c',
- 'ulp_rte_parser.c',
'bnxt_ulp_flow.c',
- 'ulp_port_db.c',
'ulp_def_rules.c',
'ulp_fc_mgr.c',
- 'ulp_tun.c',
- 'bnxt_tf_pmd_shim.c',
- 'ulp_gen_tbl.c',
+ 'ulp_flow_db.c',
'ulp_gen_hash.c',
+ 'ulp_gen_tbl.c',
'ulp_ha_mgr.c',
- 'ulp_rte_handler_tbl.c')
+ 'ulp_mapper.c',
+ 'ulp_mark_mgr.c',
+ 'ulp_matcher.c',
+ 'ulp_port_db.c',
+ 'ulp_rte_handler_tbl.c',
+ 'ulp_rte_parser.c',
+ 'ulp_tun.c',
+ 'ulp_utils.c')
subdir('generic_templates')
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index dee2c04b24..c39cde39aa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -438,8 +438,8 @@ void
ulp_fc_mgr_alarm_cb(void *arg)
{
int rc = 0;
- unsigned int j = 0;
- enum tf_dir i = 0;
+ unsigned int j;
+ enum tf_dir i;
struct bnxt_ulp_context *ctxt;
struct bnxt_ulp_fc_info *ulp_fc_info;
struct bnxt_ulp_device_params *dparms;
@@ -473,14 +473,6 @@ ulp_fc_mgr_alarm_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
- ulp_fc_info->sw_acc_tbl[i][j].session_type);
- if (!tfp) {
- BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
- bnxt_ulp_cntxt_entry_release();
- return;
- }
-
/*
* Take the fc_lock to ensure no flow is destroyed
* during the bulk get
@@ -667,6 +659,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = false;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].session_type = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 5279beb764..ebf32d6702 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -259,23 +259,26 @@ ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_idx, uint32_t ckey)
{
struct ulp_flow_db_res_params res;
+ uint32_t fid = 0; /* not using for this case */
res.direction = tbl_idx & 0x1;
res.resource_sub_type = tbl_idx >> 1;
res.resource_hndl = ckey;
- return ulp_mapper_gen_tbl_res_free(ulp_ctx, &res);
+ return ulp_mapper_gen_tbl_res_free(ulp_ctx, fid, &res);
}
/* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
+ * fid [in] - The fid the generic table is associated with
* res [in] - Pointer to flow db resource entry
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t fid,
struct ulp_flow_db_res_params *res)
{
struct bnxt_ulp_mapper_data *mapper_data;
@@ -283,7 +286,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
struct ulp_mapper_gen_tbl_entry entry;
struct ulp_gen_hash_entry_params hash_entry;
int32_t tbl_idx;
- uint32_t fid = 0;
+ uint32_t rid = 0;
uint32_t key_idx;
/* Extract the resource sub type and direction */
@@ -326,9 +329,10 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
/* Decrement the reference count */
if (!ULP_GEN_TBL_REF_CNT(&entry)) {
- BNXT_TF_DBG(ERR, "generic table corrupt %x:%" PRIX64 "\n",
+ BNXT_TF_DBG(DEBUG,
+ "generic table entry already free %x:%" PRIX64 "\n",
tbl_idx, res->resource_hndl);
- return -EINVAL;
+ return 0;
}
ULP_GEN_TBL_REF_CNT_DEC(&entry);
@@ -336,24 +340,27 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
if (ULP_GEN_TBL_REF_CNT(&entry))
return 0;
- /* Delete the generic table entry. First extract the fid */
+ /* Delete the generic table entry. First extract the rid */
if (ulp_mapper_gen_tbl_entry_data_get(&entry, ULP_GEN_TBL_FID_OFFSET,
ULP_GEN_TBL_FID_SIZE_BITS,
- (uint8_t *)&fid,
- sizeof(fid))) {
- BNXT_TF_DBG(ERR, "Unable to get fid %x:%" PRIX64 "\n",
+ (uint8_t *)&rid,
+ sizeof(rid))) {
+ BNXT_TF_DBG(ERR, "Unable to get rid %x:%" PRIX64 "\n",
tbl_idx, res->resource_hndl);
return -EINVAL;
}
- fid = tfp_be_to_cpu_32(fid);
- /* no need to del if fid is 0 since there is no associated resource */
- if (fid) {
+ rid = tfp_be_to_cpu_32(rid);
+ /* no need to del if rid is 0 since there is no associated resource
+ * if rid from the entry is equal to the incoming fid, then we have a
+ * recursive delete, so don't follow the rid.
+ */
+ if (rid && rid != fid) {
/* Destroy the flow associated with the shared flow id */
if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID,
- fid))
+ rid))
BNXT_TF_DBG(ERR,
- "Error in deleting shared flow id %x\n",
- fid);
+ "Error in deleting shared resource id %x\n",
+ rid);
}
/* Delete the entry from the hash table */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
index 3060072967..4c5a6e176f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -134,12 +134,14 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry,
* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
+ * fid [in] - The fid the generic table is associated with
* res [in] - Pointer to flow db resource entry
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t fid,
struct ulp_flow_db_res_params *res);
/* Free the generic table list entry
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 42482b596f..f3f5bda890 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -23,8 +23,6 @@
#define ULP_HA_IF_TBL_DIR TF_DIR_RX
#define ULP_HA_IF_TBL_TYPE TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR
-#define ULP_HA_IF_TBL_IDX 10
-#define ULP_HA_CLIENT_CNT_IF_TBL_IDX 9
static void ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx);
static int32_t ulp_ha_mgr_timer_start(void *arg);
@@ -42,8 +40,8 @@ static int32_t
ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *cnt);
static int32_t
-ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
- enum ulp_ha_mgr_state state)
+ulp_ha_mgr_state_set_v1(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
{
struct tf_set_if_tbl_entry_parms set_parms = { 0 };
struct tf *tfp;
@@ -66,7 +64,7 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
set_parms.type = ULP_HA_IF_TBL_TYPE;
set_parms.data = (uint8_t *)&val;
set_parms.data_sz_in_bytes = sizeof(val);
- set_parms.idx = ULP_HA_IF_TBL_IDX;
+ set_parms.idx = bnxt_ulp_ha_reg_state_get(ulp_ctx);
rc = tf_set_if_tbl_entry(tfp, &set_parms);
if (rc)
@@ -76,8 +74,82 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
}
static int32_t
-ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
- uint32_t *cnt)
+ulp_ha_mgr_state_set_v2(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
+{
+ struct tf_set_session_hotup_state_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
+ return -EINVAL;
+ }
+
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp == NULL) {
+ BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
+ return -EINVAL;
+ }
+
+ parms.state = (uint16_t)state;
+ rc = tf_set_session_hotup_state(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to write the HA state\n");
+ return rc;
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_state_set_v2(ulp_ctx, state);
+ else
+ return ulp_ha_mgr_state_set_v1(ulp_ctx, state);
+}
+
+static int32_t
+ulp_ha_mgr_tf_state_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *state,
+ uint32_t *cnt)
+{
+ struct tf_get_session_hotup_state_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid parms in client num get.\n");
+ return -EINVAL;
+ }
+
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp == NULL) {
+ BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
+ return -EINVAL;
+ }
+
+ rc = tf_get_session_hotup_state(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to read the HA state\n");
+ return rc;
+ }
+
+ if (state)
+ *state = parms.state;
+
+ if (cnt)
+ *cnt = parms.ref_cnt;
+
+ return rc;
+}
+
+static int32_t
+ulp_ha_mgr_tf_client_num_get_v1(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *cnt)
{
struct tf_get_if_tbl_entry_parms get_parms = { 0 };
struct tf *tfp;
@@ -96,7 +168,7 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
get_parms.dir = ULP_HA_IF_TBL_DIR;
get_parms.type = ULP_HA_IF_TBL_TYPE;
- get_parms.idx = ULP_HA_CLIENT_CNT_IF_TBL_IDX;
+ get_parms.idx = bnxt_ulp_ha_reg_cnt_get(ulp_ctx);
get_parms.data = (uint8_t *)&val;
get_parms.data_sz_in_bytes = sizeof(val);
@@ -108,6 +180,16 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+static int32_t
+ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *cnt)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_tf_state_get(ulp_ctx, NULL, cnt);
+ else
+ return ulp_ha_mgr_tf_client_num_get_v1(ulp_ctx, cnt);
+}
+
static int32_t
ulp_ha_mgr_region_set(struct bnxt_ulp_context *ulp_ctx,
enum ulp_ha_mgr_region region)
@@ -386,9 +468,9 @@ ulp_ha_mgr_app_type_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
-int32_t
-ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
- enum ulp_ha_mgr_state *state)
+static int32_t
+ulp_ha_mgr_state_get_v1(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state *state)
{
struct tf_get_if_tbl_entry_parms get_parms = { 0 };
struct tf *tfp;
@@ -407,7 +489,7 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
get_parms.dir = ULP_HA_IF_TBL_DIR;
get_parms.type = ULP_HA_IF_TBL_TYPE;
- get_parms.idx = ULP_HA_IF_TBL_IDX;
+ get_parms.idx = bnxt_ulp_ha_reg_state_get(ulp_ctx);
get_parms.data = (uint8_t *)&val;
get_parms.data_sz_in_bytes = sizeof(val);
@@ -419,6 +501,16 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+int32_t
+ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state *state)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_tf_state_get(ulp_ctx, state, NULL);
+ else
+ return ulp_ha_mgr_state_get_v1(ulp_ctx, state);
+}
+
int32_t
ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx)
{
@@ -607,10 +699,9 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx)
BNXT_TF_DBG(INFO,
"On Close: SEC[COPY] => [INIT] after %d ms\n",
ULP_HA_WAIT_TIMEOUT - timeout);
- } else {
- BNXT_TF_DBG(ERR, "On Close: Invalid type/state %d/%d\n",
- curr_state, app_type);
}
+ /* else do nothing just return*/
+
cleanup:
return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
index ded967a0af..c39a1371d9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -8,6 +8,9 @@
#include "bnxt_ulp.h"
+#define ULP_HA_IF_TBL_IDX 10
+#define ULP_HA_CLIENT_CNT_IF_TBL_IDX 9
+
enum ulp_ha_mgr_state {
ULP_HA_STATE_INIT,
ULP_HA_STATE_PRIM_RUN,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 1f459c52a4..e5f1d266d7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -149,7 +149,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
* Shared resources are never allocated through this method, so the
* shared flag is always false.
*/
- rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false);
+ rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, shared);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write to global resource id\n");
/* Free the identifier when update failed */
@@ -212,7 +212,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
* Shared resources are never allocated through this method, so the
* shared flag is always false.
*/
- rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false);
+ rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, shared);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write to global resource id\n");
/* Free the identifier when update failed */
@@ -442,6 +442,7 @@ ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
size_map = d_params->dyn_encap_sizes;
for (i = 0; i < d_params->dyn_encap_list_size; i++) {
if (blob_len <= size_map[i].slab_size) {
@@ -534,6 +535,41 @@ ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
return tf_free_tcam_entry(tfp, &fparms);
}
+static int32_t
+ulp_mapper_clear_full_action_record(struct tf *tfp,
+ struct bnxt_ulp_context *ulp_ctx,
+ struct tf_free_tbl_entry_parms *fparms)
+{
+ struct tf_set_tbl_entry_parms sparms = { 0 };
+ uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ int32_t rc = 0;
+
+ rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n");
+ return rc;
+ }
+
+ if (dev_id == BNXT_ULP_DEVICE_ID_THOR) {
+ sparms.dir = fparms->dir;
+ sparms.data = mapper_fld_zeros;
+ sparms.type = fparms->type;
+ sparms.data_sz_in_bytes = 16; /* FULL ACT REC SIZE - THOR */
+ sparms.idx = fparms->idx;
+ sparms.tbl_scope_id = fparms->tbl_scope_id;
+ rc = tf_set_tbl_entry(tfp, &sparms);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Index table[%s][%s][%x] write fail rc=%d\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir),
+ sparms.idx, rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
static inline int32_t
ulp_mapper_index_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -551,6 +587,9 @@ ulp_mapper_index_entry_free(struct bnxt_ulp_context *ulp,
*/
(void)bnxt_ulp_cntxt_tbl_scope_id_get(ulp, &fparms.tbl_scope_id);
+ if (fparms.type == TF_TBL_TYPE_FULL_ACT_RECORD)
+ (void)ulp_mapper_clear_full_action_record(tfp, ulp, &fparms);
+
return tf_free_tbl_entry(tfp, &fparms);
}
@@ -665,6 +704,10 @@ ulp_mapper_fdb_opc_alloc_rid(struct bnxt_ulp_mapper_parms *parms,
BNXT_ULP_FDB_TYPE_RID, rid);
return -EINVAL;
}
+ /* save the rid into the parms in case a flow fails before pushing the
+ * rid into the fid
+ */
+ parms->rid = rid;
return 0;
}
@@ -845,7 +888,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
- BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ BNXT_TF_DBG(DEBUG, "Alloc ident %s:%s.success.\n",
tf_dir_2_str(iparms.dir),
tf_ident_2_str(iparms.ident_type));
@@ -941,9 +984,9 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
- BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ BNXT_TF_DBG(DEBUG, "Search ident %s:%s:%x.success.\n",
tf_dir_2_str(sparms.dir),
- tf_tbl_type_2_str(sparms.ident_type),
+ tf_ident_2_str(sparms.ident_type),
sparms.search_id);
/* Write it to the regfile */
@@ -1016,6 +1059,20 @@ ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
+ case BNXT_ULP_PORT_TABLE_PORT_IS_PF:
+ if (ulp_port_db_port_is_pf_get(parms->ulp_ctx, port_id,
+ val)) {
+ BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
+ return -EINVAL;
+ }
+ break;
+ case BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA:
+ if (ulp_port_db_port_meta_data_get(parms->ulp_ctx, port_id,
+ val)) {
+ BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
+ return -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid port_data %d\n", port_data);
return -EINVAL;
@@ -1042,6 +1099,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
uint8_t *buffer;
uint64_t lregval;
bool shared;
+ uint8_t i = 0;
*val_len = bitlen;
*value = 0;
@@ -1111,6 +1169,11 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
*val = &buffer[field_size - bytelen];
+ if (sizeof(*value) >= field_size) {
+ *value = buffer[0];
+ for (i = 1; i < field_size; i++)
+ *value = (*value << 8) | buffer[i];
+ }
break;
case BNXT_ULP_FIELD_SRC_ACT_PROP_SZ:
if (!ulp_operand_read(field_opr,
@@ -1254,11 +1317,22 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
}
break;
case BNXT_ULP_FIELD_SRC_PORT_TABLE:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "CF operand read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
+ bytelen);
+ return -EINVAL;
+ }
+
/* The port id is present in the comp field list */
- port_id = ULP_COMP_FLD_IDX_RD(parms,
- BNXT_ULP_CF_IDX_DEV_PORT_ID);
+ port_id = ULP_COMP_FLD_IDX_RD(parms, idx);
/* get the port table enum */
- if (!ulp_operand_read(field_opr,
+ if (!ulp_operand_read(field_opr + sizeof(uint16_t),
(uint8_t *)&idx, sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "Port table enum read failed\n");
return -EINVAL;
@@ -1557,9 +1631,8 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- if (!rc) {
+ if (!rc)
return rc;
- }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1878,7 +1951,7 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
- BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ BNXT_TF_DBG(DEBUG, "tcam[%s][%s][%x] write success.\n",
tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
tf_dir_2_str(sparms.dir), sparms.idx);
@@ -2168,7 +2241,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
rc = tf_search_tcam_entry(tfp, &searchparms);
if (rc) {
- BNXT_TF_DBG(ERR, "tcam search failed rc=%d\n", rc);
+ BNXT_TF_DBG(ERR, "entry priority process failed\n");
return rc;
}
@@ -2546,7 +2619,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2651,7 +2724,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (shared)
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx,
tbl->session_type);
-
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR,
@@ -2661,7 +2733,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
- BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ BNXT_TF_DBG(DEBUG, "Index table[%s][%s][%x] write successful\n",
tf_tbl_type_2_str(sparms.type),
tf_dir_2_str(sparms.dir), sparms.idx);
@@ -2832,6 +2904,61 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+static int32_t
+ulp_mapper_gen_tbl_ref_cnt_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_mapper_gen_tbl_entry *entry)
+{
+ int32_t rc = 0;
+ uint64_t val64;
+
+ /* Allow the template to manage the reference count */
+ switch (tbl->ref_cnt_opcode) {
+ case BNXT_ULP_REF_CNT_OPC_INC:
+ ULP_GEN_TBL_REF_CNT_INC(entry);
+ break;
+ case BNXT_ULP_REF_CNT_OPC_DEC:
+ /* writes never decrement the ref count */
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_WRITE)
+ return -EINVAL;
+
+ ULP_GEN_TBL_REF_CNT_DEC(entry);
+ break;
+ case BNXT_ULP_REF_CNT_OPC_NOP:
+ /* Nothing to be done, generally used when
+ * template gets the ref_cnt to make a decision
+ */
+ break;
+ case BNXT_ULP_REF_CNT_OPC_DEFAULT:
+ /* This is the default case and is backward
+ * compatible with older templates
+ */
+ if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP)
+ ULP_GEN_TBL_REF_CNT_INC(entry);
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid REF_CNT_OPC %d\n",
+ tbl->ref_cnt_opcode);
+ return -EINVAL;
+ }
+
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_READ) {
+ /* Add ref_cnt to the regfile for template to use. */
+ val64 = (uint32_t)ULP_GEN_TBL_REF_CNT(entry);
+ val64 = tfp_cpu_to_be_64(val64);
+ rc = ulp_regfile_write(parms->regfile,
+ BNXT_ULP_RF_IDX_REF_CNT,
+ val64);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Failed to write regfile[ref_cnt]\n");
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
static int32_t
ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -2886,6 +3013,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -2949,10 +3077,6 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
"Failed to scan ident list\n");
return -EINVAL;
}
- if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {
- /* increment the reference count */
- ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
- }
/* it is a hit */
gen_tbl_miss = 0;
@@ -2969,8 +3093,13 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* store the hash index in the fdb */
key_index = hash_entry.hash_index;
}
- /* check the reference count */
- if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) {
+
+ /* check the reference count and ignore ref_cnt if NOP.
+ * NOP allows a write as an update.
+ */
+
+ if (tbl->ref_cnt_opcode != BNXT_ULP_REF_CNT_OPC_NOP &&
+ ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) {
/* a hit then error */
BNXT_TF_DBG(ERR, "generic entry already present\n");
return -EINVAL; /* success */
@@ -2999,8 +3128,6 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* increment the reference count */
- ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
fdb_write = 1;
parms->shared_hndl = (uint64_t)tbl_idx << 32 | key_index;
break;
@@ -3030,9 +3157,24 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
- if (rc)
+ if (rc) {
BNXT_TF_DBG(ERR, "Fail to add gen ent flowdb %d\n", rc);
+ return rc;
+ }
+
+ /* Reset the in-flight RID when generic table is written and the
+ * rid has been pushed into a handle (rid or fid). Once it has
+ * been written, we have persistent accounting of the resources.
+ */
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_WRITE &&
+ (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE ||
+ tbl->fdb_opcode == BNXT_ULP_FDB_OPC_PUSH_FID))
+ parms->rid = 0;
+
+ rc = ulp_mapper_gen_tbl_ref_cnt_process(parms, tbl,
+ &gen_tbl_ent);
}
+
return rc;
}
@@ -3041,6 +3183,8 @@ ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
{
int32_t rc = 0;
+ uint64_t val64 = 0;
+ uint32_t rid;
/* process the fdb opcode for alloc push */
if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE) {
@@ -3049,7 +3193,204 @@ ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n");
return rc;
}
+ } else if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE) {
+ rc = ulp_regfile_read(parms->regfile, tbl->fdb_operand, &val64);
+ if (!rc) {
+ BNXT_TF_DBG(ERR, "Failed to get RID from regfile\n");
+ return rc;
+ }
+ rid = (uint32_t)tfp_be_to_cpu_64(val64);
+ rc = ulp_mapper_resources_free(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_RID,
+ rid);
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_mapper_vnic_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms;
+ uint16_t vnic_idx = 0, vnic_id = 0;
+ int32_t rc = 0;
+
+ switch (tbl->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS:
+ if (tbl->tbl_opcode != BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE) {
+ BNXT_TF_DBG(ERR, "Invalid vnic table opcode\n");
+ return -EINVAL;
+ }
+ rc = bnxt_pmd_rss_action_create(parms, &vnic_idx, &vnic_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed create rss action\n");
+ return rc;
+ }
+ break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE:
+ if (tbl->tbl_opcode != BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE) {
+ BNXT_TF_DBG(ERR, "Invalid vnic table opcode\n");
+ return -EINVAL;
+ }
+ rc = bnxt_pmd_queue_action_create(parms, &vnic_idx, &vnic_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed create queue action\n");
+ return rc;
+ }
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid vnic table sub type\n");
+ return -EINVAL;
+ }
+
+ /* Link the created vnic to the flow in the flow db */
+ memset(&fid_parms, 0, sizeof(fid_parms));
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = tbl->resource_func;
+ fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_sub_type = tbl->resource_sub_type;
+ fid_parms.resource_hndl = vnic_idx;
+ fid_parms.critical_resource = tbl->critical_resource;
+ rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
+ rc);
+ return rc;
+ }
+ rc = ulp_regfile_write(parms->regfile, tbl->tbl_operand,
+ (uint64_t)tfp_cpu_to_be_64(vnic_id));
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n",
+ tbl->tbl_operand, rc);
+
+ return rc;
+}
+
+/* Free the vnic resource */
+static int32_t
+ulp_mapper_vnic_tbl_res_free(struct bnxt_ulp_context *ulp __rte_unused,
+ struct tf *tfp,
+ struct ulp_flow_db_res_params *res)
+{
+ uint16_t vnic_idx = res->resource_hndl;
+
+ if (res->resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE)
+ return bnxt_pmd_queue_action_delete(tfp, vnic_idx);
+ else
+ return bnxt_pmd_rss_action_delete(tfp, vnic_idx);
+}
+
+static int32_t
+ulp_mapper_global_res_free(struct bnxt_ulp_context *ulp __rte_unused,
+ struct tf *tfp __rte_unused,
+ struct ulp_flow_db_res_params *res)
+{
+ uint16_t port_id = 0, dport = 0; /* Not needed for free */
+ int32_t rc = 0;
+ uint8_t ttype;
+ uint32_t handle = res->resource_hndl;
+
+ switch (res->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN:
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN;
+ rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
+ &handle);
+ break;
+ default:
+ rc = -EINVAL;
+ BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
+ res->resource_sub_type);
+ break;
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_mapper_global_register_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms = { 0 };
+ struct ulp_blob data;
+ uint16_t data_len = 0;
+ uint8_t *tmp_data;
+ uint16_t udp_port;
+ uint32_t handle;
+ int32_t rc = 0, write_reg = 0;
+ uint8_t ttype;
+
+ /* Initialize the blob data */
+ if (!ulp_blob_init(&data, tbl->result_bit_size,
+ BNXT_ULP_BYTE_ORDER_BE)) {
+ BNXT_TF_DBG(ERR, "Failed initial ulp_global table blob\n");
+ return -EINVAL;
+ }
+
+ /* read the arguments from the result table */
+ rc = ulp_mapper_tbl_result_build(parms, tbl, &data,
+ "ULP Global Result");
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
+ return rc;
+ }
+
+ switch (tbl->tbl_opcode) {
+ case BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_WR_REGFILE:
+ write_reg = 1;
+ break;
+ case BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_NOT_USED:
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid global table opcode %d\n",
+ tbl->tbl_opcode);
+ return -EINVAL;
+ }
+
+ switch (tbl->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN:
+ tmp_data = ulp_blob_data_get(&data, &data_len);
+ udp_port = *((uint16_t *)tmp_data);
+ udp_port = tfp_be_to_cpu_16(udp_port);
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN;
+
+ rc = bnxt_pmd_global_tunnel_set(parms->port_id, ttype,
+ udp_port, &handle);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to set VXLAN UDP port\n");
+ return rc;
+ }
+ break;
+ default:
+ rc = -EINVAL;
+ BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
+ tbl->resource_sub_type);
+ return rc;
}
+
+ /* Set the common pieces of fid parms */
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = tbl->resource_func;
+ fid_parms.resource_sub_type = tbl->resource_sub_type;
+ fid_parms.critical_resource = tbl->critical_resource;
+ fid_parms.resource_hndl = handle;
+
+ rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
+
+ if (rc)
+ return rc;
+
+ /* write to the regfile if opcode is set */
+ if (write_reg) {
+ rc = ulp_regfile_write(parms->regfile,
+ tbl->tbl_operand,
+ (uint64_t)tfp_cpu_to_be_64(handle));
+ if (rc)
+ BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n",
+ tbl->tbl_operand);
+ }
+
return rc;
}
@@ -3112,36 +3453,33 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
-/*
- * Iterate over the shared resources assigned during tf_open_session and store
- * them in the global regfile with the shared flag.
- */
static int32_t
ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
- struct bnxt_ulp_mapper_data *mapper_data)
+ struct bnxt_ulp_mapper_data *mapper_data)
{
struct bnxt_ulp_glb_resource_info *glb_res;
uint32_t num_glb_res_ids, idx, dev_id;
uint8_t app_id;
- uint32_t rc = 0;
+ int32_t rc = 0;
glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_glb_res_ids);
if (!glb_res || !num_glb_res_ids) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return -EINVAL;
}
+
rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get device_id for glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get device id for glb init (%d)\n",
rc);
- return -EINVAL;
+ return rc;
}
rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get app_id for glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get app id for glb init (%d)\n",
rc);
- return -EINVAL;
+ return rc;
}
/* Iterate the global resources and process each one */
@@ -3154,13 +3492,13 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
mapper_data,
&glb_res[idx],
- false);
+ true);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
mapper_data,
&glb_res[idx],
- false);
+ true);
break;
default:
BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
@@ -3726,6 +4064,12 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
case BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE:
rc = ulp_mapper_ctrl_tbl_process(parms, tbl);
break;
+ case BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE:
+ rc = ulp_mapper_vnic_tbl_process(parms, tbl);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE:
+ rc = ulp_mapper_global_register_tbl_process(parms, tbl);
+ break;
case BNXT_ULP_RESOURCE_FUNC_INVALID:
rc = 0;
break;
@@ -3781,7 +4125,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
return rc;
error:
- BNXT_TF_DBG(ERR, "%s tables failed creation for %d:%d\n",
+ BNXT_TF_DBG(ERR, "%s tables failed operation for %d:%d\n",
ulp_mapper_tmpl_name_str(parms->tmpl_type),
parms->dev_id, tid);
return rc;
@@ -3828,7 +4172,13 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp,
rc = ulp_mapper_child_flow_free(ulp, fid, res);
break;
case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE:
- rc = ulp_mapper_gen_tbl_res_free(ulp, res);
+ rc = ulp_mapper_gen_tbl_res_free(ulp, fid, res);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE:
+ rc = ulp_mapper_vnic_tbl_res_free(ulp, tfp, res);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE:
+ rc = ulp_mapper_global_res_free(ulp, tfp, res);
break;
default:
break;
@@ -4045,11 +4395,26 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
return rc;
flow_error:
+ if (parms.rid) {
+ /* An RID was in-flight but not pushed, free the resources */
+ trc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID,
+ parms.rid);
+ if (trc)
+ BNXT_TF_DBG(ERR,
+ "Failed to free resources rid=0x%08x rc=%d\n",
+ parms.rid, trc);
+ parms.rid = 0;
+ }
+
/* Free all resources that were allocated during flow creation */
- trc = ulp_mapper_flow_destroy(ulp_ctx, parms.flow_type,
- parms.fid);
- if (trc)
- BNXT_TF_DBG(ERR, "Failed to free all resources rc=%d\n", trc);
+ if (parms.fid) {
+ trc = ulp_mapper_flow_destroy(ulp_ctx, parms.flow_type,
+ parms.fid);
+ if (trc)
+ BNXT_TF_DBG(ERR,
+ "Failed to free resources fid=0x%08x rc=%d\n",
+ parms.fid, trc);
+ }
return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index b7e6f3ada2..225a14ccfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -52,6 +52,7 @@ struct bnxt_ulp_mapper_parms {
struct ulp_regfile *regfile;
struct bnxt_ulp_context *ulp_ctx;
uint32_t fid;
+ uint32_t rid;
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..8c90998a7d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -29,8 +29,8 @@ ulp_matcher_action_hash_calculate(uint64_t hi_sig, uint64_t app_id)
hi_sig |= ((hi_sig % BNXT_ULP_ACT_HID_HIGH_PRIME) <<
BNXT_ULP_ACT_HID_SHFTL);
- app_id |= ((app_id % BNXT_ULP_CLASS_HID_LOW_PRIME) <<
- (BNXT_ULP_CLASS_HID_SHFTL + 2));
+ app_id |= ((app_id % BNXT_ULP_ACT_HID_LOW_PRIME) <<
+ (BNXT_ULP_ACT_HID_SHFTL + 2));
hash = hi_sig ^ app_id;
hash = (hash >> BNXT_ULP_ACT_HID_SHFTR) & BNXT_ULP_ACT_HID_MASK;
return (uint32_t)hash;
@@ -46,12 +46,8 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
{
struct bnxt_ulp_class_match_info *class_match;
uint32_t class_hid;
- uint8_t vf_to_vf;
uint16_t tmpl_id;
- /* Get vf to vf flow */
- vf_to_vf = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_VF_TO_VF);
-
/* calculate the hash of the given flow */
class_hid = ulp_matcher_class_hash_calculate((params->hdr_bitmap.bits ^
params->app_id),
@@ -81,10 +77,6 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
goto error;
}
- if (vf_to_vf != class_match->act_vnic) {
- BNXT_TF_DBG(DEBUG, "Vnic Match failed\n");
- goto error;
- }
BNXT_TF_DBG(DEBUG, "Found matching pattern template %d\n",
class_match->class_tid);
*class_id = class_match->class_tid;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 57c9e7d175..ba1f966ec3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -150,6 +150,11 @@ int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
intf = &port_db->ulp_intf_list[ifindex];
intf->type = bnxt_pmd_get_interface_type(port_id);
+ if (intf->type == BNXT_ULP_INTF_TYPE_PF)
+ intf->type_is_pf = 1;
+ else
+ intf->type_is_pf = 0;
+
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
BNXT_ULP_INTF_TYPE_INVALID);
@@ -182,6 +187,9 @@ int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
bnxt_pmd_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP);
func->phy_port_id = bnxt_pmd_get_phy_port_id(port_id);
func->ifindex = ifindex;
+ func->func_valid = true;
+ func->vf_meta_data = tfp_cpu_to_be_16(BNXT_ULP_META_VF_FLAG |
+ intf->vf_func_id);
}
/* When there is no match, the default action is to send the packet to
@@ -702,3 +710,53 @@ ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
}
return -EINVAL;
}
+
+/*
+ * Api to get the port type for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * type [out] type if pf or not
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_is_pf_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint8_t **type)
+{
+ struct ulp_func_if_info *info;
+ struct bnxt_ulp_port_db *port_db;
+ uint16_t pid;
+
+ port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt);
+ info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
+ if (info) {
+ pid = info->ifindex;
+ *type = &port_db->ulp_intf_list[pid].type_is_pf;
+ return 0;
+ }
+ return -EINVAL;
+}
+
+/*
+ * Api to get the meta data for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * meta data [out] the meta data of the given port
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_meta_data_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint16_t port_id, uint8_t **meta_data)
+{
+ struct ulp_func_if_info *info;
+
+ info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
+ if (info) {
+ *meta_data = (uint8_t *)&info->vf_meta_data;
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index 784b93f8b3..d4efe0a3d5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -328,4 +328,30 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
int32_t
ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint16_t *phy_port);
+
+/*
+ * Api to get the port type for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * type [out] type if pf or not
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_is_pf_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint8_t **type);
+
+/*
+ * Api to get the meta data for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * meta data [out] the meta data of the given port
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_meta_data_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint16_t port_id, uint8_t **meta_data);
#endif /* _ULP_PORT_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 9cf1ebfe1d..1fbfe18db3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -38,8 +38,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_QUEUE] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_queue_act_handler
},
[RTE_FLOW_ACTION_TYPE_DROP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
@@ -162,12 +162,12 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_set_mac_src_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_set_mac_dst_act_handler
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
@@ -197,6 +197,14 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_port_act_handler
},
+ [RTE_FLOW_ACTION_TYPE_INDIRECT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_action_hdlr_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_INDIRECT + 1] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
};
struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 3566f3000b..d7450b92ff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -24,6 +24,7 @@
#define ULP_VLAN_PRIORITY_MASK 0x700
#define ULP_VLAN_TAG_MASK 0xFFF /* Last 12 bits*/
#define ULP_UDP_PORT_VXLAN 4789
+#define ULP_UDP_PORT_VXLAN_MASK 0XFFFF
/* Utility function to skip the void items. */
static inline int32_t
@@ -190,7 +191,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
hdr_info = &ulp_vendor_act_info[action_item->type -
BNXT_RTE_FLOW_ACTION_TYPE_END];
} else {
- if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_INDIRECT)
goto act_parser_error;
/* get the header information from the act info table */
hdr_info = &ulp_act_info[action_item->type];
@@ -227,7 +228,7 @@ static void
bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
{
uint32_t ifindex;
- uint16_t port_id, parif;
+ uint16_t port_id, parif, svif;
uint32_t mtype;
enum bnxt_ulp_direction_type dir;
@@ -252,6 +253,14 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
}
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
parif);
+ /* Set port SVIF */
+ if (ulp_port_db_svif_get(params->ulp_ctx, ifindex,
+ BNXT_ULP_PHY_PORT_SVIF, &svif)) {
+ BNXT_TF_DBG(ERR, "ParseErr:ifindex is not valid\n");
+ return;
+ }
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_PHY_PORT_SVIF,
+ svif);
} else {
/* Get the match port type */
mtype = ULP_COMP_FLD_IDX_RD(params,
@@ -317,10 +326,11 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
BNXT_ULP_FLOW_DIR_BITMASK_EGR);
}
- /* calculate the VF to VF flag */
+ /* Evaluate the VF to VF flag */
if (act_port_set && act_port_type == BNXT_ULP_INTF_TYPE_VF_REP &&
match_port_type == BNXT_ULP_INTF_TYPE_VF_REP)
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_VF_TO_VF, 1);
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VF_TO_VF);
/* Update the decrement ttl computational fields */
if (ULP_BITMAP_ISSET(params->act_bitmap.bits,
@@ -438,8 +448,7 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
else
svif_type = BNXT_ULP_DRV_FUNC_SVIF;
}
- ulp_port_db_svif_get(params->ulp_ctx, ifindex, svif_type,
- &svif);
+ ulp_port_db_svif_get(params->ulp_ctx, ifindex, svif_type, &svif);
svif = rte_cpu_to_be_16(svif);
hdr_field = ¶ms->hdr_field[BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX];
memcpy(hdr_field->spec, &svif, sizeof(svif));
@@ -575,8 +584,11 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t type, uint32_t in_flag)
+ uint16_t type, uint32_t in_flag,
+ uint32_t has_vlan, uint32_t has_vlan_mask)
{
+#define ULP_RTE_ETHER_TYPE_ROE 0xfc3d
+
if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV4)) {
if (in_flag) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
@@ -587,7 +599,7 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1);
}
- } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV6)) {
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV6)) {
if (in_flag) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_I_IPV6);
@@ -597,6 +609,29 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1);
}
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
+ has_vlan_mask = 1;
+ has_vlan = 1;
+ } else if (type == tfp_cpu_to_be_16(ULP_RTE_ETHER_TYPE_ROE)) {
+ /* Update the hdr_bitmap with RoE */
+ ULP_BITMAP_SET(param->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_O_ROE);
+ }
+
+ if (has_vlan_mask) {
+ if (in_flag) {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_HAS_VTAG,
+ has_vlan);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE,
+ 1);
+ } else {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_HAS_VTAG,
+ has_vlan);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE,
+ 1);
+ }
}
}
@@ -624,17 +659,25 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
+ uint32_t has_vlan = 0, has_vlan_mask = 0;
/* Perform validations */
if (eth_spec) {
- /* Todo: work around to avoid multicast and broadcast addr */
- if (ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.dst_addr))
+ /* Avoid multicast and broadcast addr */
+ if (!ULP_APP_BC_MC_SUPPORT(params->ulp_ctx) &&
+ ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.dst_addr))
return BNXT_TF_RC_PARSE_ERR;
- if (ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.src_addr))
+ if (!ULP_APP_BC_MC_SUPPORT(params->ulp_ctx) &&
+ ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.src_addr))
return BNXT_TF_RC_PARSE_ERR;
eth_type = eth_spec->hdr.ether_type;
+ has_vlan = eth_spec->has_vlan;
+ }
+ if (eth_mask) {
+ eth_type &= eth_mask->hdr.ether_type;
+ has_vlan_mask = eth_mask->has_vlan;
}
if (ulp_rte_prsr_fld_size_validate(params, &idx,
@@ -663,7 +706,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, hdr.ether_type),
ulp_deference_struct(eth_mask, hdr.ether_type),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
/* Update the protocol hdr bitmap */
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
@@ -684,7 +728,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
dmac_idx);
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
+ ulp_rte_l2_proto_type_update(params, eth_type, inner_flag,
+ has_vlan, has_vlan_mask);
return BNXT_TF_RC_SUCCESS;
}
@@ -837,7 +882,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
+ ulp_rte_l2_proto_type_update(params, eth_type, inner_flag, 1, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -876,22 +921,21 @@ ulp_rte_l3_proto_type_update(struct ulp_rte_parser_params *param,
ULP_BITMAP_SET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_O_ICMP);
}
- if (proto) {
- if (in_flag) {
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- proto);
- } else {
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- proto);
- }
+
+ if (in_flag) {
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ proto);
+ } else {
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ proto);
}
}
@@ -906,6 +950,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
+ uint8_t proto_mask = 0;
uint32_t inner_flag = 0;
uint32_t cnt;
@@ -934,8 +979,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
/*
* The tos field is ignored since OVS is setting it as wild card
- * match and it is not supported. This is a work around and
- * shall be addressed in the future.
+ * match and it is not supported. An application can enable tos support.
*/
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.type_of_service);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -943,7 +987,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
hdr.type_of_service),
ulp_deference_struct(ipv4_mask,
hdr.type_of_service),
- ULP_PRSR_ACT_MASK_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MASK_IGNORE);
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.total_length);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -978,7 +1023,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
hdr.next_proto_id),
ulp_deference_struct(ipv4_mask,
hdr.next_proto_id),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
+
if (ipv4_spec)
proto = ipv4_spec->hdr.next_proto_id;
@@ -1020,11 +1067,14 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
* in the IPv4 spec but don't set the mask. So, consider
* the mask in the proto value calculation.
*/
- if (ipv4_mask)
+ if (ipv4_mask) {
proto &= ipv4_mask->hdr.next_proto_id;
+ proto_mask = ipv4_mask->hdr.next_proto_id;
+ }
/* Update the field protocol hdr bitmap */
- ulp_rte_l3_proto_type_update(params, proto, inner_flag);
+ if (proto_mask)
+ ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1038,11 +1088,12 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0, dip_idx = 0;
- uint32_t size;
+ uint32_t size, vtc_flow;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
uint32_t lab_spec = 0, lab_mask = 0;
uint8_t proto = 0;
+ uint8_t proto_mask = 0;
uint32_t inner_flag = 0;
uint32_t cnt;
@@ -1064,22 +1115,25 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
* header fields
*/
if (ipv6_spec) {
- ver_spec = BNXT_ULP_GET_IPV6_VER(ipv6_spec->hdr.vtc_flow);
- tc_spec = BNXT_ULP_GET_IPV6_TC(ipv6_spec->hdr.vtc_flow);
- lab_spec = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_spec->hdr.vtc_flow);
+ vtc_flow = ntohl(ipv6_spec->hdr.vtc_flow);
+ ver_spec = htonl(BNXT_ULP_GET_IPV6_VER(vtc_flow));
+ tc_spec = htonl(BNXT_ULP_GET_IPV6_TC(vtc_flow));
+ lab_spec = htonl(BNXT_ULP_GET_IPV6_FLOWLABEL(vtc_flow));
proto = ipv6_spec->hdr.proto;
}
if (ipv6_mask) {
- ver_mask = BNXT_ULP_GET_IPV6_VER(ipv6_mask->hdr.vtc_flow);
- tc_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow);
- lab_mask = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow);
+ vtc_flow = ntohl(ipv6_mask->hdr.vtc_flow);
+ ver_mask = htonl(BNXT_ULP_GET_IPV6_VER(vtc_flow));
+ tc_mask = htonl(BNXT_ULP_GET_IPV6_TC(vtc_flow));
+ lab_mask = htonl(BNXT_ULP_GET_IPV6_FLOWLABEL(vtc_flow));
/* Some of the PMD applications may set the protocol field
* in the IPv6 spec but don't set the mask. So, consider
* the mask in proto value calculation.
*/
proto &= ipv6_mask->hdr.proto;
+ proto_mask = ipv6_mask->hdr.proto;
}
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.vtc_flow);
@@ -1092,7 +1146,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
* shall be addressed in the future.
*/
ulp_rte_prsr_fld_mask(params, &idx, size, &tc_spec, &tc_mask,
- ULP_PRSR_ACT_MASK_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size, &lab_spec, &lab_mask,
ULP_PRSR_ACT_MASK_IGNORE);
@@ -1107,7 +1162,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.proto),
ulp_deference_struct(ipv6_mask, hdr.proto),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.hop_limits);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -1144,7 +1200,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l3_proto_type_update(params, proto, inner_flag);
+ if (proto_mask)
+ ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
@@ -1280,7 +1337,8 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP) ||
+ ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN))
out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
@@ -1385,7 +1443,8 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP) ||
+ ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN))
out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
@@ -1403,6 +1462,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_vxlan *vxlan_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
+ uint16_t dport;
uint32_t size;
if (ulp_rte_prsr_fld_size_validate(params, &idx,
@@ -1442,6 +1502,15 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+
+ dport = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT);
+ if (!dport) {
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ ULP_UDP_PORT_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ ULP_UDP_PORT_VXLAN_MASK);
+ }
+
return BNXT_TF_RC_SUCCESS;
}
@@ -1637,6 +1706,8 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_rss *rss;
struct ulp_rte_act_prop *ap = ¶m->act_prop;
+ uint64_t queue_list[BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE / sizeof(uint64_t)];
+ uint32_t idx = 0, id;
if (action_item == NULL || action_item->conf == NULL) {
BNXT_TF_DBG(ERR, "Parse Err: invalid rss configuration\n");
@@ -1652,12 +1723,50 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN],
&rss->key_len, BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN);
- if (rss->key_len > BNXT_ULP_ACT_PROP_SZ_RSS_KEY) {
- BNXT_TF_DBG(ERR, "Parse Err: RSS key too big\n");
+ if (rss->key_len != 0 && rss->key_len != BNXT_ULP_ACT_PROP_SZ_RSS_KEY) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS key length must be 40 bytes\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ /* User may specify only key length. In that case, rss->key will be NULL.
+ * So, reject the flow if key_length is valid but rss->key is NULL.
+ * Also, copy the RSS hash key only when rss->key is valid.
+ */
+ if (rss->key_len != 0 && rss->key == NULL) {
+ BNXT_TF_DBG(ERR,
+ "Parse Err: A valid RSS key must be provided with a valid key len.\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ if (rss->key)
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY], rss->key, rss->key_len);
+
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM],
+ &rss->queue_num, BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM);
+
+ if (rss->queue_num >= ULP_BYTE_2_BITS(BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE)) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS queue num too big\n");
return BNXT_TF_RC_ERROR;
}
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY], rss->key,
- rss->key_len);
+
+ /* Queues converted into a bitmap format */
+ memset(queue_list, 0, sizeof(queue_list));
+ for (idx = 0; idx < rss->queue_num; idx++) {
+ id = rss->queue[idx];
+ if (id >= ULP_BYTE_2_BITS(BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE)) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS queue id too big\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ if ((queue_list[id / ULP_INDEX_BITMAP_SIZE] >>
+ ((ULP_INDEX_BITMAP_SIZE - 1) -
+ (id % ULP_INDEX_BITMAP_SIZE)) & 1)) {
+ BNXT_TF_DBG(ERR, "Parse Err: duplicate queue ids\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ queue_list[id / ULP_INDEX_BITMAP_SIZE] |= (1UL <<
+ ((ULP_INDEX_BITMAP_SIZE - 1) - (id % ULP_INDEX_BITMAP_SIZE)));
+ }
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE],
+ (uint8_t *)queue_list, BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE);
/* set the RSS action header bit */
ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS);
@@ -2253,6 +2362,8 @@ ulp_rte_port_act_handler(const struct rte_flow_action *act_item,
/* Set the action port */
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_ACT_PORT_TYPE, intf_type);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID,
+ ethdev_id);
return ulp_rte_parser_act_port_set(param, ifindex, act_dir);
}
@@ -2484,6 +2595,63 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+int32_t
+ulp_rte_action_hdlr_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_handle *handle;
+ struct bnxt_ulp_shared_act_info *act_info;
+ uint64_t action_bitmask;
+ uint32_t shared_action_type;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+ uint64_t tmp64;
+ enum bnxt_ulp_direction_type dir, handle_dir;
+ uint32_t act_info_entries = 0;
+ int32_t ret;
+
+ handle = action_item->conf;
+
+ /* Have to use the computed direction since the params->dir_attr
+ * can be different (transfer, ingress, egress)
+ */
+ dir = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_DIRECTION);
+
+ /* direction of shared action must match direction of flow */
+ ret = bnxt_get_action_handle_direction(handle, &handle_dir);
+ if (ret || dir != handle_dir) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle or direction\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ if (bnxt_get_action_handle_type(handle, &shared_action_type)) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ act_info = bnxt_ulp_shared_act_info_get(&act_info_entries);
+ if (shared_action_type >= act_info_entries || !act_info) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ action_bitmask = act_info[shared_action_type].act_bitmask;
+
+ /* shared actions of the same type cannot be repeated */
+ if (params->act_bitmap.bits & action_bitmask) {
+ BNXT_TF_DBG(ERR, "indirect actions cannot be repeated\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ tmp64 = tfp_cpu_to_be_64((uint64_t)bnxt_get_action_handle_index(handle));
+
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE],
+ &tmp64, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE);
+
+ ULP_BITMAP_SET(params->act_bitmap.bits, action_bitmask);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
int32_t
ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
@@ -2504,3 +2672,69 @@ ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
return ulp_rte_vxlan_decap_act_handler(NULL, params);
}
+
+/* Function to handle the parsing of RTE Flow action queue. */
+int32_t
+ulp_rte_queue_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *param)
+{
+ const struct rte_flow_action_queue *q_info;
+ struct ulp_rte_act_prop *ap = ¶m->act_prop;
+
+ if (action_item == NULL || action_item->conf == NULL) {
+ BNXT_TF_DBG(ERR, "Parse Err: invalid queue configuration\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ q_info = action_item->conf;
+ /* Copy the queue into the specific action properties */
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX],
+ &q_info->index, BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX);
+
+ /* set the queue action header bit */
+ ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_QUEUE);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_set_mac *set_mac;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+
+ set_mac = action_item->conf;
+ if (set_mac) {
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC],
+ set_mac->mac_addr, BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC);
+ /* Update the hdr_bitmap with set mac src */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC);
+ return BNXT_TF_RC_SUCCESS;
+ }
+ BNXT_TF_DBG(ERR, "Parse Error: set mac src arg is invalid\n");
+ return BNXT_TF_RC_ERROR;
+}
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_set_mac *set_mac;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+
+ set_mac = action_item->conf;
+ if (set_mac) {
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST],
+ set_mac->mac_addr, BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST);
+ /* Update the hdr_bitmap with set ipv4 dst */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_SET_MAC_DST);
+ return BNXT_TF_RC_SUCCESS;
+ }
+ BNXT_TF_DBG(ERR, "Parse Error: set mac dst arg is invalid\n");
+ return BNXT_TF_RC_ERROR;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index b0b2b4f33f..401ce4885d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -80,6 +80,16 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow item PF Header. */
+int32_t
+ulp_rte_pf_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow item VF Header. */
+int32_t
+ulp_rte_vf_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
/* Parse items PORT_ID, PORT_REPRESENTOR and REPRESENTED_PORT. */
int32_t
ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
@@ -238,6 +248,15 @@ ulp_rte_set_tp_dst_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow action JUMP .*/
int32_t
@@ -249,7 +268,7 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
-ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
+ulp_rte_action_hdlr_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
@@ -259,4 +278,18 @@ ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_queue_act_handler(const struct rte_flow_action *act_item,
+ struct ulp_rte_parser_params *param);
+
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
#endif /* _ULP_RTE_PARSER_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 07/11] net/bnxt: add support for rte meter
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (5 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
` (4 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Jay Ding
[-- Attachment #1: Type: text/plain, Size: 32690 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Add RTE meter support into the ULP layer.
Currently:
- Chaining of meters is not supported
- Meter can be shared by multiple flows
- srtcm_rfc2697 type is supported
- Stats are not supported in the implementation yet
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/nics/features/bnxt.ini | 1 +
drivers/net/bnxt/bnxt.h | 2 +
drivers/net/bnxt/bnxt_ethdev.c | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 3 +
drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 ++++++++++++++++++
drivers/net/bnxt/tf_ulp/meson.build | 1 +
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 29 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
10 files changed, 961 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index 9c456fa863..2809beb629 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -77,6 +77,7 @@ dec_ttl = Y
drop = Y
jump = Y
mark = Y
+meter = Y
of_pop_vlan = Y
of_push_vlan = Y
of_set_vlan_pcp = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 6dd3c8b87c..7d508c7c23 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1014,6 +1014,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel);
extern const struct rte_flow_ops bnxt_flow_ops;
+extern const struct rte_flow_ops bnxt_flow_meter_ops;
#define bnxt_acquire_flow_lock(bp) \
pthread_mutex_lock(&(bp)->flow_lock)
@@ -1065,6 +1066,7 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+int bnxt_flow_meter_ops_get(struct rte_eth_dev *eth_dev, void *arg);
struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp);
struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 4d84aaee0c..7bceb0524a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4091,6 +4091,7 @@ static const struct eth_dev_ops bnxt_dev_ops = {
.timesync_adjust_time = bnxt_timesync_adjust_time,
.timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
+ .mtr_ops_get = bnxt_flow_meter_ops_get,
};
static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 08eb0c6063..3459140f18 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1681,6 +1681,14 @@ bnxt_ulp_init(struct bnxt *bp,
return rc;
}
+ if (ulp_dev_id == BNXT_ULP_DEVICE_ID_THOR) {
+ rc = bnxt_flow_meter_init(bp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to config meter\n");
+ goto jump_to_error;
+ }
+ }
+
BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
return rc;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 53d76e1465..a6ad5c1eaa 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -371,6 +371,9 @@ bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
unsigned int
bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+int32_t
+bnxt_flow_meter_init(struct bnxt *bp);
+
uint32_t
bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
new file mode 100644
index 0000000000..2461c46f90
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
@@ -0,0 +1,909 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <math.h>
+#include <sys/queue.h>
+
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_flow.h>
+#include <rte_flow_driver.h>
+#include <rte_tailq.h>
+#include <rte_alarm.h>
+#include <rte_cycles.h>
+#include <rte_mtr.h>
+#include <rte_mtr_driver.h>
+
+#include "bnxt.h"
+#include "bnxt_filter.h"
+#include "bnxt_hwrm.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxq.h"
+#include "bnxt_rxr.h"
+#include "bnxt_vnic.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "tfp.h"
+#include "bnxt_tf_common.h"
+#include "ulp_rte_parser.h"
+#include "ulp_matcher.h"
+#include "ulp_flow_db.h"
+#include "ulp_mapper.h"
+#include "ulp_fc_mgr.h"
+#include "ulp_port_db.h"
+#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
+#include <rte_malloc.h>
+
+/**
+ * Meter init status
+ */
+int bnxt_meter_initialized;
+
+/**
+ * Internal api to config global config.
+ * returns 0 on success.
+ */
+static int32_t
+bnxt_meter_global_cfg_update(struct bnxt *bp,
+ enum tf_dir dir,
+ enum tf_global_config_type type,
+ uint32_t offset,
+ uint32_t value,
+ uint32_t set_flag)
+{
+ uint32_t global_cfg = 0;
+ struct tf_global_cfg_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ parms.dir = dir,
+ parms.type = type,
+ parms.offset = offset,
+ parms.config = (uint8_t *)&global_cfg,
+ parms.config_sz_in_bytes = sizeof(global_cfg);
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_global_cfg(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n",
+ type, rc);
+ return rc;
+ }
+
+ if (set_flag)
+ global_cfg |= value;
+ else
+ global_cfg &= ~value;
+
+ rc = tf_set_global_cfg(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n",
+ type, rc);
+ return rc;
+ }
+ return rc;
+}
+
+/**
+ * When a port is initialized by dpdk. This functions is called
+ * to enable the meter and initializes the meter global configurations.
+ */
+#define BNXT_THOR_FMTCR_NUM_MET_MET_1K (0x7UL << 20)
+#define BNXT_THOR_FMTCR_CNTRS_ENABLE (0x1UL << 25)
+#define BNXT_THOR_FMTCR_INTERVAL_1K (1024)
+int32_t
+bnxt_flow_meter_init(struct bnxt *bp)
+{
+ int rc = 0;
+
+ /*
+ * Enable metering. Set the meter global configuration register.
+ * Set number of meter to 1K. Disable the drop counter for now.
+ */
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_RX, TF_METER_CFG,
+ 0,
+ BNXT_THOR_FMTCR_NUM_MET_MET_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set rx meter configuration\n");
+ goto jump_to_error;
+ }
+
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_TX, TF_METER_CFG,
+ 0,
+ BNXT_THOR_FMTCR_NUM_MET_MET_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set tx meter configuration\n");
+ goto jump_to_error;
+ }
+
+ /*
+ * Set meter refresh rate to 1024 clock cycle. This value works for
+ * most bit rates especially for high rates.
+ */
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_RX, TF_METER_INTERVAL_CFG,
+ 0,
+ BNXT_THOR_FMTCR_INTERVAL_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set rx meter interval\n");
+ goto jump_to_error;
+ }
+
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_TX, TF_METER_INTERVAL_CFG,
+ 0,
+ BNXT_THOR_FMTCR_INTERVAL_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set tx meter interval\n");
+ goto jump_to_error;
+ }
+
+ bnxt_meter_initialized = 1;
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter has been initialized\n");
+ return rc;
+
+jump_to_error:
+ return rc;
+}
+
+/**
+ * Get meter capabilities.
+ */
+#define MAX_FLOW_PER_METER 1024
+#define MAX_METER_RATE_100GBPS ((1ULL << 30) * 100 / 8)
+static int
+bnxt_flow_mtr_cap_get(struct rte_eth_dev *dev,
+ struct rte_mtr_capabilities *cap,
+ struct rte_mtr_error *error)
+{
+ struct bnxt *bp = dev->data->dev_private;
+ uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ struct tf_get_session_info_parms iparms;
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
+ if (rc)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Unable to get device id from ulp");
+
+ /* Get number of meter reserved for this session */
+ memset(&iparms, 0, sizeof(iparms));
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_session_info(tfp, &iparms);
+ if (rc != 0)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to get session resource info");
+
+ memset(cap, 0, sizeof(struct rte_mtr_capabilities));
+
+ cap->n_max = iparms.session_info.tbl[TF_DIR_RX].info[TF_TBL_TYPE_METER_INST].stride;
+ if (!cap->n_max)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL,
+ "Meter is not supported");
+
+ cap->srtcm_rfc2697_byte_mode_supported = 1;
+ cap->n_shared_max = cap->n_max;
+ /* No meter is identical */
+ cap->identical = 1;
+ cap->shared_identical = 1;
+ cap->shared_n_flows_per_mtr_max = MAX_FLOW_PER_METER;
+ cap->chaining_n_mtrs_per_flow_max = 1; /* Chaining is not supported. */
+ cap->meter_srtcm_rfc2697_n_max = cap->n_max;
+ cap->meter_rate_max = MAX_METER_RATE_100GBPS;
+ /* No stats supported now */
+ cap->stats_mask = 0;
+
+ return 0;
+}
+
+/**
+ * Calculate mantissa and exponent for cir / eir reg.
+ */
+#define BNXT_CPU_CLOCK 800
+#define MEGA 1000000
+#define NUM_BIT_PER_BYTE 8
+static inline void
+bnxt_ulp_flow_meter_xir_calc(int64_t xir, uint32_t *reg)
+{
+ int64_t temp;
+ uint16_t m = 0;
+ uint16_t e = 0;
+ uint8_t *swap = 0;
+
+ /* Special case xir == 0 ? both exp and matissa are 0. */
+ if (xir == 0) {
+ *reg = 0;
+ return;
+ }
+
+ /*
+ * e = floor(log2(cir)) + 27
+ * a (MBps) = xir (bps) / MEGA
+ * b (MBpc) = a (MBps) / CPU_CLOCK (Mcps)
+ * e = floor(log2(b)) + 27
+ */
+ temp = xir * (1 << 24) / (BNXT_CPU_CLOCK >> 3) / MEGA;
+ e = log2(temp);
+
+ /*
+ * m = round(b/2^(e-27) - 1) * 2048
+ * = round(b*2^(27-e) - 1) * 2^11
+ * = round(b*2^(38-e) - 2^11)
+ *
+ */
+ m = xir * (1 << (38 - e)) / BNXT_CPU_CLOCK / MEGA - (1 << 11);
+ *reg = ((m & 0x7FF) << 6) | (e & 0x3F);
+ swap = (uint8_t *)reg;
+ *reg = swap[0] << 16 | swap[1] << 8 | swap[2];
+}
+
+/**
+ * Calculate mantissa and exponent for cbs / ebs reg.
+ */
+static inline void
+bnxt_ulp_flow_meter_xbs_calc(int64_t xbs, uint16_t *reg)
+{
+ uint16_t m = 0;
+ uint16_t e = 0;
+
+ if (xbs == 0) {
+ *reg = 0;
+ return;
+ }
+
+ /*
+ * e = floor(log2(xbs)) + 1
+ */
+ e = log2(xbs) + 1;
+
+ /*
+ * m = round(xbs/2^(e-1) - 1) * 128
+ * = round(xbs*2^(1-e) - 1) * 2^7
+ * = round(xbs*2^(8-e) - 2^7)
+ *
+ */
+ m = xbs / (1 << (e - 8)) - (1 << 7);
+ *reg = ((m & 0x7F) << 5) | (e & 0x1F);
+ *reg = rte_cpu_to_be_16(*reg);
+}
+
+/**
+ * Parse the meter profile.
+ */
+static inline int
+bnxt_ulp_meter_profile_parse(struct ulp_rte_act_prop *act_prop,
+ const struct rte_mtr_meter_profile *profile,
+ struct rte_mtr_error *error)
+{
+ uint64_t cir, cbs, eir, ebs;
+ uint32_t cir_reg, eir_reg;
+ uint16_t cbs_reg, ebs_reg;
+ bool alg_rfc2698 = false;
+ bool pm = false;
+
+ /* Profile must not be NULL. */
+ if (profile == NULL)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL, "Meter profile is null.");
+
+ if (profile->packet_mode)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "Metering packet_mode is not supported");
+
+ switch (profile->alg) {
+ case RTE_MTR_SRTCM_RFC2697:
+ cir = profile->srtcm_rfc2697.cir;
+ cbs = profile->srtcm_rfc2697.cbs;
+ eir = 0;
+ ebs = profile->srtcm_rfc2697.ebs;
+ break;
+ case RTE_MTR_TRTCM_RFC2698:
+ cir = profile->trtcm_rfc2698.cir;
+ cbs = profile->trtcm_rfc2698.cbs;
+ eir = profile->trtcm_rfc2698.pir;
+ ebs = profile->trtcm_rfc2698.pbs;
+ alg_rfc2698 = true;
+ break;
+ case RTE_MTR_TRTCM_RFC4115:
+ cir = profile->trtcm_rfc4115.cir;
+ cbs = profile->trtcm_rfc4115.cbs;
+ eir = profile->trtcm_rfc4115.eir;
+ ebs = profile->trtcm_rfc4115.ebs;
+ alg_rfc2698 = true;
+ break;
+ default:
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "Metering algorithm type is invalid");
+ }
+
+ /* The CBS and EBS must be configured so that at least one
+ * of them is larger than 0. It is recommended that when
+ * the value of the CBS or the EBS is larger than 0, it
+ * is larger than or equal to the size of the largest possible
+ * IP packet in the stream.
+ */
+ if (cbs == 0 && ebs == 0)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "CBS & EBS cannot both be 0. One of"
+ " them should be larger than the MTU");
+
+ if (alg_rfc2698 && eir < cir)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "PIR must be equal to or greater than CIR");
+
+ bnxt_ulp_flow_meter_xir_calc(cir, &cir_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR],
+ &cir_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR);
+
+ bnxt_ulp_flow_meter_xir_calc(eir, &eir_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR],
+ &eir_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR);
+
+ bnxt_ulp_flow_meter_xbs_calc(cbs, &cbs_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS],
+ &cbs_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS);
+
+ bnxt_ulp_flow_meter_xbs_calc(ebs, &ebs_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS],
+ &ebs_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698],
+ &alg_rfc2698,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM],
+ &pm,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM);
+
+ return 0;
+}
+
+/**
+ * Add MTR profile.
+ */
+static int
+bnxt_flow_meter_profile_add(struct rte_eth_dev *dev,
+ uint32_t meter_profile_id,
+ struct rte_mtr_meter_profile *profile,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop = ¶ms.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+ params.act_bitmap.bits = BNXT_ULP_ACT_BIT_METER_PROFILE;
+ /* not direction from rte_mtr. Set ingress by default */
+ params.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_profile_id = tfp_cpu_to_be_32(meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ ret = bnxt_ulp_meter_profile_parse(act_prop, profile, error);
+ if (ret)
+ goto parse_error;
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto act_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto act_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto act_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto act_error;
+
+ return 0;
+parse_error:
+ return ret;
+act_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to add meter profile.");
+}
+
+/**
+ * Delete meter profile.
+ */
+static int
+bnxt_flow_meter_profile_delete(struct rte_eth_dev *dev,
+ uint32_t meter_profile_id,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop = ¶ms.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+ params.act_bitmap.bits = BNXT_ULP_ACT_BIT_METER_PROFILE;
+ params.act_bitmap.bits |= BNXT_ULP_ACT_BIT_DELETE;
+ /* not direction from rte_mtr. Set ingress by default */
+ params.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_profile_id = tfp_cpu_to_be_32(meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter profile %d deleted\n",
+ meter_profile_id);
+
+ return 0;
+
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to delete meter profile.");
+}
+
+/**
+ * Create meter.
+ */
+static int
+bnxt_flow_meter_create(struct rte_eth_dev *dev, uint32_t meter_id,
+ struct rte_mtr_params *params, int shared __rte_unused,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ bool meter_en = params->meter_enable ? true : false;
+ int ret;
+ uint32_t tmp_meter_id, tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+
+ tmp_profile_id = tfp_cpu_to_be_32(params->meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL],
+ &meter_en,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL);
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is created\n", meter_id);
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to add meter.");
+}
+
+/**
+ * Destroy meter.
+ */
+static int
+bnxt_flow_meter_destroy(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_meter_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ pparams.act_bitmap.bits |= BNXT_ULP_ACT_BIT_DELETE;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is deleted\n", meter_id);
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to delete meter.");
+}
+
+/**
+ * Set meter valid/invalid.
+ */
+static int
+bnxt_flow_meter_enable_set(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ uint8_t val,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_meter_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ pparams.act_bitmap.bits |= BNXT_ULP_ACT_BIT_UPDATE;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+ act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE] = 1;
+ act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL] = val;
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is %s\n",
+ meter_id, val ? "enabled" : "disabled");
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to enable/disable meter.");
+}
+
+/**
+ * Enable flow meter.
+ */
+static int
+bnxt_flow_meter_enable(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ return bnxt_flow_meter_enable_set(dev, meter_id, 1, error);
+}
+
+/**
+ * Disable flow meter.
+ */
+static int
+bnxt_flow_meter_disable(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ return bnxt_flow_meter_enable_set(dev, meter_id, 0, error);
+}
+
+/**
+ * Update meter profile.
+ */
+static int
+bnxt_flow_meter_profile_update(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ uint32_t meter_profile_id __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_profile_update not supported");
+}
+
+/**
+ * Udate meter stats mask.
+ */
+static int
+bnxt_flow_meter_stats_update(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ uint64_t stats_mask __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_stats_update not supported");
+}
+
+/**
+ * Read meter statistics.
+ */
+static int
+bnxt_flow_meter_stats_read(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ struct rte_mtr_stats *stats __rte_unused,
+ uint64_t *stats_mask __rte_unused,
+ int clear __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_stats_read not supported yet");
+}
+
+static const struct rte_mtr_ops bnxt_flow_mtr_ops = {
+ .capabilities_get = bnxt_flow_mtr_cap_get,
+ .meter_profile_add = bnxt_flow_meter_profile_add,
+ .meter_profile_delete = bnxt_flow_meter_profile_delete,
+ .meter_policy_validate = NULL,
+ .meter_policy_add = NULL,
+ .meter_policy_delete = NULL,
+ .create = bnxt_flow_meter_create,
+ .destroy = bnxt_flow_meter_destroy,
+ .meter_enable = bnxt_flow_meter_enable,
+ .meter_disable = bnxt_flow_meter_disable,
+ .meter_profile_update = bnxt_flow_meter_profile_update,
+ .meter_dscp_table_update = NULL,
+ .stats_update = bnxt_flow_meter_stats_update,
+ .stats_read = bnxt_flow_meter_stats_read,
+};
+
+/**
+ * Get meter operations.
+ */
+int
+bnxt_flow_meter_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg)
+{
+ *(const struct rte_mtr_ops **)arg = &bnxt_flow_mtr_ops;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build
index c7df7e42f1..53a34b4413 100644
--- a/drivers/net/bnxt/tf_ulp/meson.build
+++ b/drivers/net/bnxt/tf_ulp/meson.build
@@ -11,6 +11,7 @@ sources += files(
'bnxt_tf_pmd_shim.c',
'bnxt_ulp.c',
'bnxt_ulp_flow.c',
+ 'bnxt_ulp_meter.c',
'ulp_def_rules.c',
'ulp_fc_mgr.c',
'ulp_flow_db.c',
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 1fbfe18db3..af02f857d3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -66,8 +66,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = ulp_rte_port_act_handler
},
[RTE_FLOW_ACTION_TYPE_METER] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_meter_act_handler
},
[RTE_FLOW_ACTION_TYPE_SECURITY] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index d7450b92ff..d64c9e4968 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -2697,6 +2697,35 @@ ulp_rte_queue_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow action meter. */
+int32_t
+ulp_rte_meter_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_meter *meter;
+ struct ulp_rte_act_prop *act_prop = ¶ms->act_prop;
+ uint32_t tmp_meter_id;
+
+ if (action_item == NULL || action_item->conf == NULL) {
+ BNXT_TF_DBG(ERR, "Parse Err: invalid meter configuration\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ meter = action_item->conf;
+ if (meter) {
+ /* validate the mtr_id and update the reference counter */
+ tmp_meter_id = tfp_cpu_to_be_32(meter->mtr_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER);
+ }
+
+ /* set the meter action header bit */
+ ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_METER);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of RTE Flow action set mac src.*/
int32_t
ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 401ce4885d..74c7170a45 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -292,4 +292,9 @@ ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action meter. */
+int32_t
+ulp_rte_meter_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
#endif /* _ULP_RTE_PARSER_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 08/11] net/bnxt: update PTP support on Thor
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (6 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 07/11] net/bnxt: add support for rte meter Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
` (3 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Somnath Kotur, Randy Schacher, Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 10819 bytes --]
From: Somnath Kotur <somnath.kotur@broadcom.com>
add locking and time stamp checks to ptp feature
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 5 ++++
drivers/net/bnxt/bnxt_ethdev.c | 11 +++++++++
drivers/net/bnxt/bnxt_hwrm.c | 11 ++++++++-
drivers/net/bnxt/bnxt_ring.c | 3 +++
drivers/net/bnxt/bnxt_rxr.c | 8 ++++--
drivers/net/bnxt/bnxt_txq.c | 1 +
drivers/net/bnxt/bnxt_txr.c | 45 +++++++++++++++++++++++++++++++---
drivers/net/bnxt/bnxt_txr.h | 1 +
8 files changed, 79 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 7d508c7c23..dadd0bd95a 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -349,6 +349,7 @@ struct bnxt_ptp_cfg {
BNXT_PTP_MSG_PDELAY_RESP)
uint8_t tx_tstamp_en:1;
int rx_filter;
+ uint8_t filter_all;
#define BNXT_PTP_RX_TS_L 0
#define BNXT_PTP_RX_TS_H 1
@@ -372,6 +373,8 @@ struct bnxt_ptp_cfg {
/* On P5, the Rx timestamp is present in the Rx completion record */
uint64_t rx_timestamp;
uint64_t current_time;
+ uint64_t old_time;
+ rte_spinlock_t ptp_lock;
};
struct bnxt_coal {
@@ -722,6 +725,7 @@ struct bnxt {
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
+#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(10)
#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\
(bp)->app_id != 0xFF)
@@ -849,6 +853,7 @@ struct bnxt {
struct bnxt_led_info *leds;
uint8_t ieee_1588;
struct bnxt_ptp_cfg *ptp_cfg;
+ uint8_t ptp_all_rx_tstamp;
uint16_t vf_resv_strategy;
struct bnxt_ctx_mem_info *ctx;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 7bceb0524a..ea817e1fdd 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1441,8 +1441,11 @@ static void bnxt_ptp_get_current_time(void *arg)
if (!ptp)
return;
+ rte_spinlock_lock(&ptp->ptp_lock);
+ ptp->old_time = ptp->current_time;
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
if (rc != 0) {
PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
@@ -1458,8 +1461,11 @@ static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
return 0;
+ rte_spinlock_lock(&ptp->ptp_lock);
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ ptp->old_time = ptp->current_time;
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
@@ -3611,12 +3617,15 @@ bnxt_timesync_enable(struct rte_eth_dev *dev)
ptp->rx_filter = 1;
ptp->tx_tstamp_en = 1;
+ ptp->filter_all = 1;
ptp->rxctl = BNXT_PTP_MSG_EVENTS;
rc = bnxt_hwrm_ptp_cfg(bp);
if (rc)
return rc;
+ rte_spinlock_init(&ptp->ptp_lock);
+ bp->ptp_all_rx_tstamp = 1;
memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
@@ -3653,9 +3662,11 @@ bnxt_timesync_disable(struct rte_eth_dev *dev)
ptp->rx_filter = 0;
ptp->tx_tstamp_en = 0;
ptp->rxctl = 0;
+ ptp->filter_all = 0;
bnxt_hwrm_ptp_cfg(bp);
+ bp->ptp_all_rx_tstamp = 0;
if (!BNXT_CHIP_P5(bp))
bnxt_unmap_ptp_regs(bp);
else
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 77588bdf49..82679d1b32 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -669,6 +669,11 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
+ if (ptp->filter_all)
+ flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
+ else if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
+ flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
+
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
@@ -810,7 +815,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
struct hwrm_func_qcaps_input req = {.req_type = 0 };
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
uint16_t new_max_vfs;
- uint32_t flags;
+ uint32_t flags, flags_ext2;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
@@ -898,6 +903,10 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
bp->tunnel_disable_flag);
+ flags_ext2 = rte_le_to_cpu_32(resp->flags_ext2);
+ if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
+ bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
+
unlock:
HWRM_UNLOCK();
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 686c3af4da..34b2510d54 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -227,6 +227,9 @@ int bnxt_alloc_rings(struct bnxt *bp, unsigned int socket_id, uint16_t qidx,
tx_ring->bd_dma = mz_phys_addr + tx_ring_start;
tx_ring_info->tx_desc_mapping = tx_ring->bd_dma;
tx_ring->mem_zone = (const void *)mz;
+ tx_ring_info->nr_bds = rte_zmalloc("bnxt_nr_bds",
+ sizeof(unsigned short) *
+ tx_ring->ring_size, 0);
if (!tx_ring->bd)
return -ENOMEM;
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 1ab0ef2f5d..0cabfb583c 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -697,7 +697,7 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
if (!BNXT_CHIP_P5(bp) || !ptp)
return;
- /* On Thor, Rx timestamps are provided directly in the
+ /* On P5, Rx timestamps are provided directly in the
* Rx completion records to the driver. Only 32 bits of
* the timestamp is present in the completion. Driver needs
* to read the current 48 bit free running timer using the
@@ -705,6 +705,9 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
* from the HWRM response with the lower 32 bits in the
* Rx completion to produce the 48 bit timestamp for the Rx packet
*/
+ rte_spinlock_lock(&ptp->ptp_lock);
+ last_hwrm_time = ptp->old_time;
+ rte_spinlock_unlock(&ptp->ptp_lock);
pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
/* timer has rolled over */
@@ -922,7 +925,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
- RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
+ RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP) ||
+ bp->ptp_all_rx_tstamp)
bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index d1d1fe8f1f..4df4604975 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -96,6 +96,7 @@ void bnxt_tx_queue_release_op(struct rte_eth_dev *dev, uint16_t queue_idx)
if (txq->tx_ring) {
bnxt_free_ring(txq->tx_ring->tx_ring_struct);
rte_free(txq->tx_ring->tx_ring_struct);
+ rte_free(txq->tx_ring->nr_bds);
rte_free(txq->tx_ring);
}
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 10b716a00b..6a11f5c8dc 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -143,6 +143,41 @@ bnxt_zero_data_len_tso_segsz(struct rte_mbuf *tx_pkt, uint8_t data_len_chk)
return false;
}
+static bool
+bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
+{
+ const struct rte_ether_hdr *eth_hdr;
+ struct rte_ether_hdr _eth_hdr;
+ uint16_t eth_type, proto;
+ uint32_t off = 0;
+
+ eth_hdr = rte_pktmbuf_read(m, off, sizeof(_eth_hdr), &_eth_hdr);
+ eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
+ off += sizeof(*eth_hdr);
+ /* Check for single tagged and double tagged VLANs */
+ if (eth_type == RTE_ETHER_TYPE_VLAN) {
+ const struct rte_vlan_hdr *vh;
+ struct rte_vlan_hdr vh_copy;
+
+ vh = rte_pktmbuf_read(m, off, sizeof(*vh), &vh_copy);
+ if (unlikely(vh == NULL))
+ return false;
+ off += sizeof(*vh);
+ proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_VLAN) {
+ const struct rte_vlan_hdr *vh;
+ struct rte_vlan_hdr vh_copy;
+
+ vh = rte_pktmbuf_read(m, off, sizeof(*vh), &vh_copy);
+ if (unlikely(vh == NULL))
+ return false;
+ off += sizeof(*vh);
+ proto = rte_be_to_cpu_16(vh->eth_proto);
+ }
+ }
+ return false;
+}
+
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
@@ -157,6 +192,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
bool long_bd = false;
unsigned short nr_bds;
uint16_t prod;
+ bool pkt_needs_ts = 0;
struct rte_mbuf *m_seg;
struct rte_mbuf **tx_buf;
static const uint32_t lhint_arr[4] = {
@@ -202,9 +238,13 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
if (unlikely(bnxt_zero_data_len_tso_segsz(tx_pkt, 1)))
return -EIO;
+ if (unlikely(txq->bp->ptp_cfg != NULL && txq->bp->ptp_all_rx_tstamp == 1))
+ pkt_needs_ts = bnxt_check_pkt_needs_ts(tx_pkt);
+
prod = RING_IDX(ring, txr->tx_raw_prod);
tx_buf = &txr->tx_buf_ring[prod];
*tx_buf = tx_pkt;
+ txr->nr_bds[prod] = nr_bds;
txbd = &txr->tx_desc_ring[prod];
txbd->opaque = *coal_pkts;
@@ -341,7 +381,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
/* IP CSO */
txbd1->lflags |= TX_BD_LONG_LFLAGS_T_IP_CHKSUM;
} else if ((tx_pkt->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) ==
- RTE_MBUF_F_TX_IEEE1588_TMST) {
+ RTE_MBUF_F_TX_IEEE1588_TMST || pkt_needs_ts) {
/* PTP */
txbd1->lflags |= TX_BD_LONG_LFLAGS_STAMP;
}
@@ -427,8 +467,7 @@ static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nr_pkts)
unsigned short nr_bds;
tx_buf = &txr->tx_buf_ring[RING_IDX(ring, raw_cons)];
- nr_bds = (*tx_buf)->nb_segs +
- bnxt_xmit_need_long_bd(*tx_buf, txq);
+ nr_bds = txr->nr_bds[RING_IDX(ring, raw_cons)];
for (j = 0; j < nr_bds; j++) {
mbuf = *tx_buf;
*tx_buf = NULL;
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index b9b8a9b1a2..8e391ee58a 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -24,6 +24,7 @@ struct bnxt_tx_ring_info {
rte_iova_t tx_desc_mapping;
+ unsigned short *nr_bds;
struct bnxt_ring *tx_ring_struct;
};
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 09/11] net/bnxt: fix multi-root card support
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (7 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
` (2 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Kishore Padmanabha, stable, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 4012 bytes --]
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Changed the logic to use device serial number to identify that
different ports belong to same physical card instead of the PCI
domain address.
Fixes: 34a7ff5a920e ("net/bnxt: support multi root capability")
Cc: stable@dpdk.org
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 +++
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 ++++++++---
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 ++
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index dadd0bd95a..08791b8a17 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -138,6 +138,7 @@
#define BNXT_NUM_CMPL_DMA_AGGR 36
#define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
#define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
+#define BNXT_DEVICE_SERIAL_NUM_SIZE 8
#define BNXT_DEFAULT_VNIC_STATE_MASK \
HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
@@ -863,6 +864,8 @@ struct bnxt {
uint16_t num_reps;
struct bnxt_rep_info *rep_info;
uint16_t *cfa_code_map;
+ /* Device Serial Number */
+ uint8_t dsn[BNXT_DEVICE_SERIAL_NUM_SIZE];
/* Struct to hold adapter error recovery related info */
struct bnxt_error_recovery_info *recovery_info;
#define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 82679d1b32..edad84c262 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -863,6 +863,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
+ memcpy(bp->dsn, resp->device_serial_number, sizeof(bp->dsn));
if (BNXT_PF(bp))
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 3459140f18..500c177039 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1318,9 +1318,13 @@ ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr)
/* if multi root capability is enabled, then ignore the pci bus id */
STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) {
- if (session->pci_info.domain == pci_addr->domain &&
- (BNXT_MULTIROOT_EN(bp) ||
- session->pci_info.bus == pci_addr->bus)) {
+ if (BNXT_MULTIROOT_EN(bp)) {
+ if (!memcmp(bp->dsn, session->dsn,
+ sizeof(session->dsn))) {
+ return session;
+ }
+ } else if (session->pci_info.domain == pci_addr->domain &&
+ session->pci_info.bus == pci_addr->bus) {
return session;
}
}
@@ -1364,6 +1368,7 @@ ulp_session_init(struct bnxt *bp,
/* Add it to the queue */
session->pci_info.domain = pci_addr->domain;
session->pci_info.bus = pci_addr->bus;
+ memcpy(session->dsn, bp->dsn, sizeof(session->dsn));
rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
if (rc) {
BNXT_TF_DBG(ERR, "mutex create failed\n");
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index a6ad5c1eaa..92db7751fe 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -131,11 +131,13 @@ struct bnxt_ulp_pci_info {
uint8_t bus;
};
+#define BNXT_ULP_DEVICE_SERIAL_NUM_SIZE 8
struct bnxt_ulp_session_state {
STAILQ_ENTRY(bnxt_ulp_session_state) next;
bool bnxt_ulp_init;
pthread_mutex_t bnxt_ulp_mutex;
struct bnxt_ulp_pci_info pci_info;
+ uint8_t dsn[BNXT_ULP_DEVICE_SERIAL_NUM_SIZE];
struct bnxt_ulp_data *cfg_data;
struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
uint32_t session_opened[BNXT_ULP_SESSION_MAX];
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 10/11] net/bnxt: add support for eCPRI packet parsing
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (8 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
2023-05-10 17:16 ` [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Randy Schacher, Shahaji Bhosle, Manish Kurup
[-- Attachment #1: Type: text/plain, Size: 21024 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Add eCPRI parsing and offload support in the TruFlow ULP layer.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Manish Kurup <manish.kurup@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.mailmap | 1 +
doc/guides/nics/features/bnxt.ini | 1 +
drivers/net/bnxt/bnxt.h | 4 +
drivers/net/bnxt/bnxt_ethdev.c | 35 +++++
drivers/net/bnxt/bnxt_hwrm.c | 17 +++
drivers/net/bnxt/bnxt_txr.c | 10 +-
drivers/net/bnxt/bnxt_vnic.c | 5 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 7 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 18 +++
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 120 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +
16 files changed, 256 insertions(+), 7 deletions(-)
diff --git a/.mailmap b/.mailmap
index aded19d181..cc22746f36 100644
--- a/.mailmap
+++ b/.mailmap
@@ -813,6 +813,7 @@ Malvika Gupta <malvika.gupta@arm.com>
Mandal Purna Chandra <purna.chandra.mandal@intel.com>
Mandeep Rohilla <mrohilla@brocade.com>
Manish Chopra <manishc@marvell.com>
+Manish Kurup <manish.kurup@broadcom.com>
Manish Tomar <manish.tomar@nxp.com>
Mao Jiang <maox.jiang@intel.com>
Mao YingMing <maoyingming@baidu.com>
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index 2809beb629..7b3030a58c 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -57,6 +57,7 @@ Perf doc = Y
[rte_flow items]
any = Y
+ecpri = Y
eth = P
ipv4 = Y
ipv6 = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 08791b8a17..ed21ba7f29 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -844,10 +844,14 @@ struct bnxt {
uint8_t port_cnt;
uint8_t vxlan_port_cnt;
uint8_t geneve_port_cnt;
+ uint8_t ecpri_port_cnt;
uint16_t vxlan_port;
uint16_t geneve_port;
+ uint16_t ecpri_port;
uint16_t vxlan_fw_dst_port_id;
uint16_t geneve_fw_dst_port_id;
+ uint16_t ecpri_fw_dst_port_id;
+ uint16_t ecpri_upar_in_use;
uint32_t fw_ver;
uint32_t hwrm_spec_code;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ea817e1fdd..ee1552452a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -2405,6 +2405,20 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
tunnel_type =
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
+ udp_tunnel->udp_port);
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Only one port allowed\n");
+ return -ENOSPC;
+ }
+ bp->ecpri_port_cnt++;
+ return 0;
+ }
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
@@ -2423,6 +2437,10 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
bp->geneve_port_cnt++;
+ if (tunnel_type ==
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI)
+ bp->ecpri_port_cnt++;
+
return rc;
}
@@ -2474,6 +2492,23 @@ bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
port = bp->geneve_fw_dst_port_id;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (!bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
+ return -EINVAL;
+ }
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
+ udp_tunnel->udp_port, bp->ecpri_port);
+ return -EINVAL;
+ }
+ if (--bp->ecpri_port_cnt)
+ return 0;
+
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI;
+ port = bp->ecpri_fw_dst_port_id;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index edad84c262..b944547656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -2969,6 +2969,10 @@ bnxt_free_tunnel_ports(struct bnxt *bp)
if (bp->geneve_port_cnt)
bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
+
+ if (bp->ecpri_port_cnt)
+ bnxt_hwrm_tunnel_dst_port_free(bp, bp->ecpri_fw_dst_port_id,
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI);
}
void bnxt_free_all_hwrm_resources(struct bnxt *bp)
@@ -4075,6 +4079,12 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
rte_le_to_cpu_16(resp->tunnel_dst_port_id);
bp->geneve_port = port;
break;
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI:
+ bp->ecpri_fw_dst_port_id =
+ rte_le_to_cpu_16(resp->tunnel_dst_port_id);
+ bp->ecpri_port = port;
+ bp->ecpri_upar_in_use = resp->upar_in_use;
+ break;
default:
break;
}
@@ -4142,6 +4152,13 @@ int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
bp->geneve_port_cnt = 0;
}
+ if (tunnel_type ==
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI) {
+ bp->ecpri_port = 0;
+ bp->ecpri_upar_in_use = 0;
+ bp->ecpri_port_cnt = 0;
+ }
+
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 6a11f5c8dc..899986764f 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -150,10 +150,14 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
struct rte_ether_hdr _eth_hdr;
uint16_t eth_type, proto;
uint32_t off = 0;
-
+ /*
+ * Check that the received packet is a eCPRI packet
+ */
eth_hdr = rte_pktmbuf_read(m, off, sizeof(_eth_hdr), &_eth_hdr);
eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
off += sizeof(*eth_hdr);
+ if (eth_type == RTE_ETHER_TYPE_ECPRI)
+ return true;
/* Check for single tagged and double tagged VLANs */
if (eth_type == RTE_ETHER_TYPE_VLAN) {
const struct rte_vlan_hdr *vh;
@@ -164,6 +168,8 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
return false;
off += sizeof(*vh);
proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_ECPRI)
+ return true;
if (proto == RTE_ETHER_TYPE_VLAN) {
const struct rte_vlan_hdr *vh;
struct rte_vlan_hdr vh_copy;
@@ -173,6 +179,8 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
return false;
off += sizeof(*vh);
proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_ECPRI)
+ return true;
}
}
return false;
diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c
index be9c127b64..2be456956d 100644
--- a/drivers/net/bnxt/bnxt_vnic.c
+++ b/drivers/net/bnxt/bnxt_vnic.c
@@ -258,7 +258,8 @@ uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)
{
uint16_t hwrm_type = 0;
- if (rte_type & RTE_ETH_RSS_IPV4)
+ if ((rte_type & RTE_ETH_RSS_IPV4) ||
+ (rte_type & RTE_ETH_RSS_ECPRI))
hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
if (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
@@ -277,7 +278,7 @@ uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)
int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl)
{
uint32_t mode = HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
- bool l3 = (hash_f & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6));
+ bool l3 = (hash_f & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_ECPRI));
bool l4 = (hash_f & (RTE_ETH_RSS_NONFRAG_IPV4_UDP |
RTE_ETH_RSS_NONFRAG_IPV6_UDP |
RTE_ETH_RSS_NONFRAG_IPV4_TCP |
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
index 474854d59b..239191e14e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
@@ -543,12 +543,15 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
case BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN:
hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
break;
+ case BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI:
+ hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI;
+ break;
default:
BNXT_TF_DBG(ERR, "Tunnel Type (%d) invalid\n", type);
return -EINVAL;
}
- if (!udp_port) {
+ if (!udp_port && type != BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI) {
/* Free based on the handle */
if (!handle) {
BNXT_TF_DBG(ERR, "Free with invalid handle\n");
@@ -589,7 +592,7 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
if (!rc) {
ulp_global_tunnel_db[type].ref_cnt++;
ulp_global_tunnel_db[type].dport = udp_port;
- bnxt_pmd_global_reg_data_to_hndl(port_id, 0,
+ bnxt_pmd_global_reg_data_to_hndl(port_id, bp->ecpri_upar_in_use,
type, handle);
}
}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index b76e4b849d..18feab6cac 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -19,6 +19,7 @@ struct bnxt_global_tunnel_info {
enum bnxt_global_register_tunnel_type {
BNXT_GLOBAL_REGISTER_TUNNEL_UNUSED = 0,
BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN,
+ BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI,
BNXT_GLOBAL_REGISTER_TUNNEL_MAX
};
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 500c177039..b696b6dc3e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -456,6 +456,7 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
bnxt_ulp_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port);
bnxt_ulp_vxlan_port_set(ulp_ctx, info[i].vxlan_port);
+ bnxt_ulp_ecpri_udp_port_set(ulp_ctx, info[i].ecpri_udp_port);
/* set the shared session support from firmware */
fw = info[i].upgrade_fw_update;
@@ -479,6 +480,29 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
return 0;
}
+/* Function to retrieve the vxlan_ip (ecpri) port from the context. */
+int
+bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t ecpri_udp_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->ecpri_udp_port = ecpri_udp_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan_ip (ecpri) port from the context. */
+unsigned int
+bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->ecpri_udp_port;
+}
+
/* Function to set the number for vxlan_ip (custom vxlan) port into the context */
int
bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 92db7751fe..258801f633 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -113,6 +113,7 @@ struct bnxt_ulp_data {
struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
uint32_t vxlan_port;
uint32_t vxlan_ip_port;
+ uint32_t ecpri_udp_port;
uint8_t hu_reg_state;
uint8_t hu_reg_cnt;
uint32_t hu_session_type;
@@ -367,12 +368,19 @@ bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
uint32_t vxlan_port);
unsigned int
bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx);
+
int
bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
uint32_t vxlan_ip_port);
unsigned int
bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t ecpri_udp_port);
+unsigned int
+bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx);
+
int32_t
bnxt_flow_meter_init(struct bnxt *bp);
@@ -391,5 +399,4 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
-
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index e5f1d266d7..6d345e12c7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -3298,6 +3298,11 @@ ulp_mapper_global_res_free(struct bnxt_ulp_context *ulp __rte_unused,
rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
&handle);
break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI:
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI;
+ rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
+ &handle);
+ break;
default:
rc = -EINVAL;
BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
@@ -3362,6 +3367,19 @@ ulp_mapper_global_register_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI:
+ tmp_data = ulp_blob_data_get(&data, &data_len);
+ udp_port = *((uint16_t *)tmp_data);
+ udp_port = tfp_be_to_cpu_16(udp_port);
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI;
+
+ rc = bnxt_pmd_global_tunnel_set(parms->port_id, ttype,
+ udp_port, &handle);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to set eCPRI UDP port\n");
+ return rc;
+ }
+ break;
default:
rc = -EINVAL;
BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index af02f857d3..51b2e98103 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -408,6 +408,10 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
+ [RTE_FLOW_ITEM_TYPE_ECPRI] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ecpri_hdr_handler
+ },
[RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_port_hdr_handler
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index d64c9e4968..0937d0dbe4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -143,7 +143,7 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
hdr_info = &ulp_vendor_hdr_info[item->type -
BNXT_RTE_FLOW_ITEM_TYPE_END];
} else {
- if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ if (item->type > RTE_FLOW_ITEM_TYPE_ECPRI)
goto hdr_parser_error;
hdr_info = &ulp_hdr_info[item->type];
}
@@ -612,6 +612,10 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
} else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
has_vlan_mask = 1;
has_vlan = 1;
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_ECPRI)) {
+ /* Update the hdr_bitmap with eCPRI */
+ ULP_BITMAP_SET(param->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_O_ECPRI);
} else if (type == tfp_cpu_to_be_16(ULP_RTE_ETHER_TYPE_ROE)) {
/* Update the hdr_bitmap with RoE */
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
@@ -1660,6 +1664,120 @@ ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item ECPRI Header. */
+int32_t
+ulp_rte_ecpri_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_item_ecpri *ecpri_spec = item->spec;
+ const struct rte_flow_item_ecpri *ecpri_mask = item->mask;
+ struct rte_flow_item_ecpri l_ecpri_spec, l_ecpri_mask;
+ struct rte_flow_item_ecpri *p_ecpri_spec = &l_ecpri_spec;
+ struct rte_flow_item_ecpri *p_ecpri_mask = &l_ecpri_mask;
+ struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
+ uint32_t idx = 0, cnt;
+ uint32_t size;
+
+ if (ulp_rte_prsr_fld_size_validate(params, &idx,
+ BNXT_ULP_PROTO_HDR_ECPRI_NUM)) {
+ BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ /* Figure out if eCPRI is within L4(UDP), unsupported, for now */
+ cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
+ if (cnt >= 1) {
+ BNXT_TF_DBG(ERR, "Parse Err: L4 header stack >= 2 not supported\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ if (!ecpri_spec || !ecpri_mask)
+ goto parser_set_ecpri_hdr_bit;
+
+ memcpy(p_ecpri_spec, ecpri_spec, sizeof(*ecpri_spec));
+ memcpy(p_ecpri_mask, ecpri_mask, sizeof(*ecpri_mask));
+
+ p_ecpri_spec->hdr.common.u32 = rte_be_to_cpu_32(p_ecpri_spec->hdr.common.u32);
+ p_ecpri_mask->hdr.common.u32 = rte_be_to_cpu_32(p_ecpri_mask->hdr.common.u32);
+
+ /*
+ * Init eCPRI spec+mask to correct defaults, also clear masks of fields
+ * we ignore in the TCAM.
+ */
+
+ l_ecpri_spec.hdr.common.size = 0;
+ l_ecpri_spec.hdr.common.c = 0;
+ l_ecpri_spec.hdr.common.res = 0;
+ l_ecpri_spec.hdr.common.revision = 1;
+ l_ecpri_mask.hdr.common.size = 0;
+ l_ecpri_mask.hdr.common.c = 1;
+ l_ecpri_mask.hdr.common.res = 0;
+ l_ecpri_mask.hdr.common.revision = 0xf;
+
+ switch (p_ecpri_spec->hdr.common.type) {
+ case RTE_ECPRI_MSG_TYPE_IQ_DATA:
+ l_ecpri_mask.hdr.type0.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_BIT_SEQ:
+ l_ecpri_mask.hdr.type1.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
+ l_ecpri_mask.hdr.type2.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_GEN_DATA:
+ l_ecpri_mask.hdr.type3.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RM_ACC:
+ l_ecpri_mask.hdr.type4.rr = 0;
+ l_ecpri_mask.hdr.type4.rw = 0;
+ l_ecpri_mask.hdr.type4.rma_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_DLY_MSR:
+ l_ecpri_spec.hdr.type5.act_type = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RMT_RST:
+ l_ecpri_spec.hdr.type6.rst_op = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_EVT_IND:
+ l_ecpri_spec.hdr.type7.evt_type = 0;
+ l_ecpri_spec.hdr.type7.seq = 0;
+ l_ecpri_spec.hdr.type7.number = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ p_ecpri_spec->hdr.common.u32 = rte_cpu_to_be_32(p_ecpri_spec->hdr.common.u32);
+ p_ecpri_mask->hdr.common.u32 = rte_cpu_to_be_32(p_ecpri_mask->hdr.common.u32);
+
+ /* Type */
+ size = sizeof(((struct rte_flow_item_ecpri *)NULL)->hdr.common.u32);
+ ulp_rte_prsr_fld_mask(params, &idx, size,
+ ulp_deference_struct(p_ecpri_spec, hdr.common.u32),
+ ulp_deference_struct(p_ecpri_mask, hdr.common.u32),
+ ULP_PRSR_ACT_DEFAULT);
+
+ /* PC/RTC/MSR_ID */
+ size = sizeof(((struct rte_flow_item_ecpri *)NULL)->hdr.dummy[0]);
+ ulp_rte_prsr_fld_mask(params, &idx, size,
+ ulp_deference_struct(p_ecpri_spec, hdr.dummy),
+ ulp_deference_struct(p_ecpri_mask, hdr.dummy),
+ ULP_PRSR_ACT_DEFAULT);
+
+parser_set_ecpri_hdr_bit:
+ /* Update the hdr_bitmap with eCPRI */
+ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ECPRI);
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of RTE Flow item void Header */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 74c7170a45..9dd7ebcb76 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -149,6 +149,11 @@ int32_t
ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow item ECPRI Header. */
+int32_t
+ulp_rte_ecpri_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
/* Function to handle the parsing of RTE Flow item void Header. */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index fb6fb3553b..9e11b3e305 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -29,6 +29,7 @@
#define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4
#define BNXT_ULP_PROTO_HDR_GRE_NUM 2
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
+#define BNXT_ULP_PROTO_HDR_ECPRI_NUM 2
#define BNXT_ULP_PROTO_HDR_MAX 128
#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
@@ -364,6 +365,7 @@ struct bnxt_ulp_app_capabilities_info {
uint8_t app_id;
uint32_t vxlan_port;
uint32_t vxlan_ip_port;
+ uint32_t ecpri_udp_port;
enum bnxt_ulp_device_id device_id;
uint32_t upgrade_fw_update;
uint8_t ha_pool_id;
--
2.39.2 (Apple Git-143)
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 11/11] net/bnxt: set RSS config based on RSS mode
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (9 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
@ 2023-05-04 17:36 ` Ajit Khaparde
2023-05-10 17:16 ` [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-04 17:36 UTC (permalink / raw)
To: dev; +Cc: Shuanglin Wang, Kishore Padmanabha, Mike Baucom
[-- Attachment #1: Type: text/plain, Size: 1200 bytes --]
From: Shuanglin Wang <shuanglin.wang@broadcom.com>
Avoid submitting hwrm RSS request when rss mode disabled.
On WH+, if rss mode isn't enabled, then there is no rss context.
Submitting HWRM_VNIC_RSS_CFG request to firmware would hit a failure.
The fix is to check the rss context. If no rss context, then don't
submit the hwrm request.
Signed-off-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index b944547656..06f196760f 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -2405,6 +2405,9 @@ bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
int rc = 0;
+ if (vnic->num_lb_ctxts == 0)
+ return rc;
+
HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/11] sync Truflow support with latest release
2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
` (10 preceding siblings ...)
2023-05-04 17:36 ` [PATCH v3 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
@ 2023-05-10 17:16 ` Ajit Khaparde
11 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-05-10 17:16 UTC (permalink / raw)
To: dev; +Cc: Ferruh Yigit
[-- Attachment #1: Type: text/plain, Size: 12644 bytes --]
On Thu, May 4, 2023 at 10:36 AM Ajit Khaparde
<ajit.khaparde@broadcom.com> wrote:
>
> Update Truflow support to latest release, deprecating code, updating
> the copyright date and hsi structure, syncing the truflow core,
> adding ULP shared session support, RSS action support, Queue
> action support, rte meter support, and more.
>
> Please apply.
>
> v2->v3:
> - update some commit messages
> - removed some empty lines in the patches
> - removed some dead and unnecessary code
> - fixed some checkpatch errors
>
> Version 2 fixes:
> - misspellings
> - whitespace issues
> - signed off issues
Patchset applied to dpdk-next-net-brcm for-next-net branch.
Thanks.
>
>
> Kishore Padmanabha (1):
> net/bnxt: fix multi-root card support
>
> Randy Schacher (8):
> net/bnxt: remove deprecated features
> net/bnxt: update bnxt hsi structure
> net/bnxt: update copyright date and cleanup whitespace
> net/bnxt: update Truflow core
> net/bnxt: update ULP shared session support
> net/bnxt: add RSS and Queue action in TruFLow
> net/bnxt: add support for rte meter
> net/bnxt: add support for eCPRI packet parsing
>
> Shuanglin Wang (1):
> net/bnxt: set RSS config based on RSS mode
>
> Somnath Kotur (1):
> net/bnxt: update PTP support on Thor
>
> .mailmap | 1 +
> doc/guides/nics/features/bnxt.ini | 3 +
> drivers/net/bnxt/bnxt.h | 66 +-
> drivers/net/bnxt/bnxt_cpr.c | 2 +-
> drivers/net/bnxt/bnxt_cpr.h | 2 +-
> drivers/net/bnxt/bnxt_ethdev.c | 209 +-
> drivers/net/bnxt/bnxt_filter.c | 2 +-
> drivers/net/bnxt/bnxt_filter.h | 6 +-
> drivers/net/bnxt/bnxt_flow.c | 75 +-
> drivers/net/bnxt/bnxt_hwrm.c | 272 +-
> drivers/net/bnxt/bnxt_hwrm.h | 40 +-
> drivers/net/bnxt/bnxt_irq.c | 2 +-
> drivers/net/bnxt/bnxt_irq.h | 3 +-
> drivers/net/bnxt/bnxt_nvm_defs.h | 3 +-
> drivers/net/bnxt/bnxt_reps.c | 4 +-
> drivers/net/bnxt/bnxt_reps.h | 2 +-
> drivers/net/bnxt/bnxt_ring.c | 7 +-
> drivers/net/bnxt/bnxt_ring.h | 3 +-
> drivers/net/bnxt/bnxt_rxq.c | 159 +-
> drivers/net/bnxt/bnxt_rxq.h | 2 +-
> drivers/net/bnxt/bnxt_rxr.c | 15 +-
> drivers/net/bnxt/bnxt_rxr.h | 3 +-
> drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +-
> drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +-
> drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +-
> drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +-
> drivers/net/bnxt/bnxt_stats.c | 2 +-
> drivers/net/bnxt/bnxt_stats.h | 2 +-
> drivers/net/bnxt/bnxt_txq.c | 3 +-
> drivers/net/bnxt/bnxt_txq.h | 2 +-
> drivers/net/bnxt/bnxt_txr.c | 55 +-
> drivers/net/bnxt/bnxt_txr.h | 4 +-
> drivers/net/bnxt/bnxt_util.c | 2 +-
> drivers/net/bnxt/bnxt_util.h | 3 +-
> drivers/net/bnxt/bnxt_vnic.c | 974 +-
> drivers/net/bnxt/bnxt_vnic.h | 80 +-
> drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 ++-
> drivers/net/bnxt/meson.build | 5 +-
> drivers/net/bnxt/rte_pmd_bnxt.c | 2 +-
> drivers/net/bnxt/rte_pmd_bnxt.h | 2 +-
> drivers/net/bnxt/tf_core/bitalloc.c | 3 +-
> drivers/net/bnxt/tf_core/bitalloc.h | 3 +-
> drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
> drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 +
> .../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 +
> .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 +
> .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 +
> drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 +
> .../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +
> .../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 +
> drivers/net/bnxt/tf_core/dpool.c | 3 +-
> drivers/net/bnxt/tf_core/dpool.h | 3 +-
> drivers/net/bnxt/tf_core/ll.c | 2 +-
> drivers/net/bnxt/tf_core/ll.h | 2 +-
> drivers/net/bnxt/tf_core/lookup3.h | 1 -
> drivers/net/bnxt/tf_core/meson.build | 38 +-
> drivers/net/bnxt/tf_core/rand.c | 2 +-
> drivers/net/bnxt/tf_core/rand.h | 3 +-
> drivers/net/bnxt/tf_core/stack.c | 2 +-
> drivers/net/bnxt/tf_core/stack.h | 3 +-
> drivers/net/bnxt/tf_core/tf_common.h | 3 +-
> drivers/net/bnxt/tf_core/tf_core.c | 56 +-
> drivers/net/bnxt/tf_core/tf_core.h | 189 +-
> drivers/net/bnxt/tf_core/tf_device.c | 53 +-
> drivers/net/bnxt/tf_core/tf_device.h | 9 +-
> drivers/net/bnxt/tf_core/tf_device_p4.c | 24 +-
> drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +-
> drivers/net/bnxt/tf_core/tf_device_p58.c | 94 +-
> drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +-
> drivers/net/bnxt/tf_core/tf_em.h | 3 +-
> drivers/net/bnxt/tf_core/tf_em_common.c | 10 +-
> drivers/net/bnxt/tf_core/tf_em_common.h | 4 +-
> .../net/bnxt/tf_core/tf_em_hash_internal.c | 2 +-
> drivers/net/bnxt/tf_core/tf_em_host.c | 3 +-
> drivers/net/bnxt/tf_core/tf_em_internal.c | 13 +-
> drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +-
> drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +-
> drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +-
> drivers/net/bnxt/tf_core/tf_hash.c | 2 +-
> drivers/net/bnxt/tf_core/tf_hash.h | 3 +-
> drivers/net/bnxt/tf_core/tf_identifier.c | 111 +-
> drivers/net/bnxt/tf_core/tf_identifier.h | 7 +-
> drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +-
> drivers/net/bnxt/tf_core/tf_if_tbl.h | 11 +-
> drivers/net/bnxt/tf_core/tf_msg.c | 217 +-
> drivers/net/bnxt/tf_core/tf_msg.h | 38 +-
> drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +-
> drivers/net/bnxt/tf_core/tf_project.h | 3 +-
> drivers/net/bnxt/tf_core/tf_resources.h | 3 +-
> drivers/net/bnxt/tf_core/tf_rm.c | 135 +-
> drivers/net/bnxt/tf_core/tf_rm.h | 6 +-
> drivers/net/bnxt/tf_core/tf_session.c | 121 +-
> drivers/net/bnxt/tf_core/tf_session.h | 80 +-
> .../net/bnxt/tf_core/tf_shadow_identifier.c | 190 -
> .../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -
> drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 -
> drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 -
> drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +-
> drivers/net/bnxt/tf_core/tf_sram_mgr.h | 23 +-
> drivers/net/bnxt/tf_core/tf_tbl.c | 8 +-
> drivers/net/bnxt/tf_core/tf_tbl.h | 4 +-
> drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +-
> drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +-
> drivers/net/bnxt/tf_core/tf_tcam.c | 451 +-
> drivers/net/bnxt/tf_core/tf_tcam.h | 41 +-
> drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +
> drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 +
> drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +-
> drivers/net/bnxt/tf_core/tf_tcam_shared.h | 4 +-
> drivers/net/bnxt/tf_core/tf_util.c | 5 +-
> drivers/net/bnxt/tf_core/tf_util.h | 3 +-
> drivers/net/bnxt/tf_core/tfp.c | 2 +-
> drivers/net/bnxt/tf_core/tfp.h | 4 +-
> drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +-
> drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 251 +-
> drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 37 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 850 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 121 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 280 +-
> drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 +
> .../bnxt/tf_ulp/generic_templates/meson.build | 18 +-
> .../generic_templates/ulp_template_db_act.c | 7000 +++-
> .../generic_templates/ulp_template_db_class.c | 33556 +++++++++++-----
> .../generic_templates/ulp_template_db_enum.h | 4366 +-
> .../generic_templates/ulp_template_db_field.h | 689 +-
> .../generic_templates/ulp_template_db_tbl.c | 16055 ++++++--
> .../ulp_template_db_thor_act.c | 8714 ++--
> .../ulp_template_db_thor_class.c | 10746 +++--
> .../ulp_template_db_wh_plus_act.c | 1157 +-
> .../ulp_template_db_wh_plus_class.c | 288 +-
> drivers/net/bnxt/tf_ulp/meson.build | 26 +-
> drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 26 +-
> drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +-
> drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 14 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 37 +-
> drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 5 +-
> drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 131 +-
> drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 6 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.c | 726 +-
> drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +-
> drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
> drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +-
> drivers/net/bnxt/tf_ulp/ulp_matcher.c | 14 +-
> drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +-
> drivers/net/bnxt/tf_ulp/ulp_port_db.c | 64 +-
> drivers/net/bnxt/tf_ulp/ulp_port_db.h | 35 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 30 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 504 +-
> drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 46 +-
> drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 25 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +-
> drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +-
> drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +-
> 163 files changed, 79517 insertions(+), 25424 deletions(-)
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
> create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
> delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
> delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
> delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
> delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
> create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
> create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
> create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
>
> --
> 2.39.2 (Apple Git-143)
>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/11] net/bnxt: update Truflow core
2023-05-04 17:36 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
@ 2023-06-10 18:32 ` Thomas Monjalon
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
2023-06-28 16:35 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
0 siblings, 2 replies; 30+ messages in thread
From: Thomas Monjalon @ 2023-06-10 18:32 UTC (permalink / raw)
To: Randy Schacher, Farah Smith, Shahaji Bhosle, Ajit Khaparde
Cc: dev, david.marchand
04/05/2023 19:36, Ajit Khaparde:
> From: Randy Schacher <stuart.schacher@broadcom.com>
>
> Update TruFlow core code to:
> - Add shared session management
> - Add SRAM session management
> - Add dynamic TCAM management
> - Add shared TCAM session management
> - Add Hot Upgrade support
> - Update copyright year
I suppose you can update the date in the previous patch
for the whole driver.
Also this patch is removing some blank lines out of Truflow.
And I don't understand the need for removing the blank lines
before the last #ifdef of the file.
More important, you are doing huge update of many different things
in one patch.
It looks like you don't want the community to follow what you are doing.
For info, there are other things to fix in this patchset:
Error: Incorrect indent at drivers/net/bnxt/tf_ulp/generic_templates/meson.build
rte_flow doc out of sync for bnxt
action set_mac_dst
action set_mac_src
You can run the following script to catch these issues:
devtools/check-meson.py
devtools/check-doc-vs-code.sh
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 00/11] sync Truflow support with latest release
2023-06-10 18:32 ` Thomas Monjalon
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 01/11] net/bnxt: remove deprecated features Ajit Khaparde
` (10 more replies)
2023-06-28 16:35 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
1 sibling, 11 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas
[-- Attachment #1: Type: text/plain, Size: 12168 bytes --]
Update Truflow support to latest release, deprecating code, updating
the copyright date and hsi structure, syncing the truflow core,
adding ULP shared session support, RSS action support, Queue
action support, rte meter support, and more.
Please apply.
v3->v4:
- Rebased against the latest 23.07-rc2 code base.
- Address review comments.
- Updated bnxt rte_flow doc for action and item support
- Fixed indentation in meson files
- Removed some blank line changes, most of these changes were from
automated scripts.
- Other cleanup and comments.
v2->v3:
- update some commit messages
- removed some empty lines in the patches
- removed some dead and unnecessary code
- fixed some checkpatch errors
Version 2 fixes:
- misspellings
- whitespace issues
- signed off issues
Kishore Padmanabha (1):
net/bnxt: fix multi-root card support
Randy Schacher (8):
net/bnxt: remove deprecated features
net/bnxt: update bnxt hsi structure
net/bnxt: update copyright date and cleanup whitespace
net/bnxt: update Truflow core
net/bnxt: update ULP shared session support
net/bnxt: add RSS and Queue action in TruFLow
net/bnxt: add support for rte meter
net/bnxt: add support for eCPRI packet parsing
Shuanglin Wang (1):
net/bnxt: set RSS config based on RSS mode
Somnath Kotur (1):
net/bnxt: update PTP support on Thor
.mailmap | 1 +
doc/guides/nics/features/bnxt.ini | 5 +
drivers/net/bnxt/bnxt.h | 66 +-
drivers/net/bnxt/bnxt_cpr.c | 2 +-
drivers/net/bnxt/bnxt_cpr.h | 2 +-
drivers/net/bnxt/bnxt_ethdev.c | 209 +-
drivers/net/bnxt/bnxt_filter.c | 2 +-
drivers/net/bnxt/bnxt_filter.h | 6 +-
drivers/net/bnxt/bnxt_flow.c | 75 +-
drivers/net/bnxt/bnxt_hwrm.c | 272 +-
drivers/net/bnxt/bnxt_hwrm.h | 40 +-
drivers/net/bnxt/bnxt_irq.c | 2 +-
drivers/net/bnxt/bnxt_irq.h | 3 +-
drivers/net/bnxt/bnxt_nvm_defs.h | 3 +-
drivers/net/bnxt/bnxt_reps.c | 4 +-
drivers/net/bnxt/bnxt_reps.h | 2 +-
drivers/net/bnxt/bnxt_ring.c | 7 +-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 159 +-
drivers/net/bnxt/bnxt_rxq.h | 2 +-
drivers/net/bnxt/bnxt_rxr.c | 15 +-
drivers/net/bnxt/bnxt_rxr.h | 3 +-
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +-
drivers/net/bnxt/bnxt_stats.c | 2 +-
drivers/net/bnxt/bnxt_stats.h | 2 +-
drivers/net/bnxt/bnxt_txq.c | 3 +-
drivers/net/bnxt/bnxt_txq.h | 2 +-
drivers/net/bnxt/bnxt_txr.c | 55 +-
drivers/net/bnxt/bnxt_txr.h | 4 +-
drivers/net/bnxt/bnxt_util.c | 2 +-
drivers/net/bnxt/bnxt_util.h | 3 +-
drivers/net/bnxt/bnxt_vnic.c | 974 +-
drivers/net/bnxt/bnxt_vnic.h | 80 +-
drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 ++-
drivers/net/bnxt/meson.build | 5 +-
drivers/net/bnxt/rte_pmd_bnxt.c | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.h | 2 +-
drivers/net/bnxt/tf_core/bitalloc.c | 3 +-
drivers/net/bnxt/tf_core/bitalloc.h | 3 +-
drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +-
drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 +
.../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 +
drivers/net/bnxt/tf_core/dpool.c | 3 +-
drivers/net/bnxt/tf_core/dpool.h | 3 +-
drivers/net/bnxt/tf_core/ll.c | 2 +-
drivers/net/bnxt/tf_core/ll.h | 2 +-
drivers/net/bnxt/tf_core/lookup3.h | 1 -
drivers/net/bnxt/tf_core/meson.build | 38 +-
drivers/net/bnxt/tf_core/rand.c | 2 +-
drivers/net/bnxt/tf_core/rand.h | 3 +-
drivers/net/bnxt/tf_core/stack.c | 2 +-
drivers/net/bnxt/tf_core/stack.h | 3 +-
drivers/net/bnxt/tf_core/tf_common.h | 3 +-
drivers/net/bnxt/tf_core/tf_core.c | 56 +-
drivers/net/bnxt/tf_core/tf_core.h | 189 +-
drivers/net/bnxt/tf_core/tf_device.c | 53 +-
drivers/net/bnxt/tf_core/tf_device.h | 9 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 24 +-
drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 94 +-
drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +-
drivers/net/bnxt/tf_core/tf_em.h | 3 +-
drivers/net/bnxt/tf_core/tf_em_common.c | 10 +-
drivers/net/bnxt/tf_core/tf_em_common.h | 4 +-
.../net/bnxt/tf_core/tf_em_hash_internal.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_host.c | 3 +-
drivers/net/bnxt/tf_core/tf_em_internal.c | 13 +-
drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +-
drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +-
drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +-
drivers/net/bnxt/tf_core/tf_hash.c | 2 +-
drivers/net/bnxt/tf_core/tf_hash.h | 3 +-
drivers/net/bnxt/tf_core/tf_identifier.c | 111 +-
drivers/net/bnxt/tf_core/tf_identifier.h | 7 +-
drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +-
drivers/net/bnxt/tf_core/tf_if_tbl.h | 11 +-
drivers/net/bnxt/tf_core/tf_msg.c | 217 +-
drivers/net/bnxt/tf_core/tf_msg.h | 38 +-
drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +-
drivers/net/bnxt/tf_core/tf_project.h | 3 +-
drivers/net/bnxt/tf_core/tf_resources.h | 3 +-
drivers/net/bnxt/tf_core/tf_rm.c | 135 +-
drivers/net/bnxt/tf_core/tf_rm.h | 6 +-
drivers/net/bnxt/tf_core/tf_session.c | 121 +-
drivers/net/bnxt/tf_core/tf_session.h | 80 +-
.../net/bnxt/tf_core/tf_shadow_identifier.c | 190 -
.../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -
drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 -
drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 -
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 23 +-
drivers/net/bnxt/tf_core/tf_tbl.c | 8 +-
drivers/net/bnxt/tf_core/tf_tbl.h | 4 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +-
drivers/net/bnxt/tf_core/tf_tcam.c | 451 +-
drivers/net/bnxt/tf_core/tf_tcam.h | 41 +-
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +-
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 4 +-
drivers/net/bnxt/tf_core/tf_util.c | 5 +-
drivers/net/bnxt/tf_core/tf_util.h | 3 +-
drivers/net/bnxt/tf_core/tfp.c | 2 +-
drivers/net/bnxt/tf_core/tfp.h | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 251 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 37 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 850 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 121 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 280 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 +
.../bnxt/tf_ulp/generic_templates/meson.build | 3 -
.../generic_templates/ulp_template_db_act.c | 6999 +++-
.../generic_templates/ulp_template_db_class.c | 33541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 4365 +-
.../generic_templates/ulp_template_db_field.h | 689 +-
.../generic_templates/ulp_template_db_tbl.c | 16056 ++++++--
.../ulp_template_db_thor_act.c | 8714 ++--
.../ulp_template_db_thor_class.c | 10737 +++--
.../ulp_template_db_wh_plus_act.c | 1157 +-
.../ulp_template_db_wh_plus_class.c | 287 +-
drivers/net/bnxt/tf_ulp/meson.build | 26 +-
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 26 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 14 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 37 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 5 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 131 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 6 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 726 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 4 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 64 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 35 +-
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 30 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 504 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 46 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 25 +-
drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +-
163 files changed, 79495 insertions(+), 25407 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 01/11] net/bnxt: remove deprecated features
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
` (9 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev
Cc: ferruh.yigit, thomas, Randy Schacher, Kishore Padmanabha,
Peter Spreadborough
[-- Attachment #1: Type: text/plain, Size: 81234 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Deprecate shadow identifier
- Deprecate shadow TCAM
- Remove files which are not needed anymore.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 53 --
drivers/net/bnxt/bnxt_hwrm.h | 10 -
drivers/net/bnxt/tf_core/meson.build | 2 -
drivers/net/bnxt/tf_core/tf_core.c | 2 -
drivers/net/bnxt/tf_core/tf_core.h | 91 +-
drivers/net/bnxt/tf_core/tf_device.c | 35 -
drivers/net/bnxt/tf_core/tf_device.h | 6 -
drivers/net/bnxt/tf_core/tf_device_p4.c | 10 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 10 -
drivers/net/bnxt/tf_core/tf_identifier.c | 108 ---
drivers/net/bnxt/tf_core/tf_identifier.h | 4 -
drivers/net/bnxt/tf_core/tf_if_tbl.h | 8 -
drivers/net/bnxt/tf_core/tf_session.c | 9 +-
drivers/net/bnxt/tf_core/tf_session.h | 18 +-
.../net/bnxt/tf_core/tf_shadow_identifier.c | 190 ----
.../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -----
drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 ------------------
drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195 ----
drivers/net/bnxt/tf_core/tf_tcam.c | 243 -----
drivers/net/bnxt/tf_core/tf_tcam.h | 38 +-
drivers/net/bnxt/tf_core/tf_util.c | 2 -
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 3 -
22 files changed, 8 insertions(+), 2095 deletions(-)
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index d86ac73293..3f273df6f3 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -407,59 +407,6 @@ int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
return rc;
}
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len)
-{
- int rc = 0;
- struct hwrm_cfa_tflib_input req = { .req_type = 0 };
- struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
- bool mailbox = BNXT_USE_CHIMP_MB;
-
- if (msg_len > sizeof(req.tf_req))
- return -ENOMEM;
-
- if (use_kong_mb)
- mailbox = BNXT_USE_KONG(bp);
-
- HWRM_PREP(&req, HWRM_TF, mailbox);
- /* Build request using the user supplied request payload.
- * TLV request size is checked at build time against HWRM
- * request max size, thus no checking required.
- */
- req.tf_type = tf_type;
- req.tf_subtype = tf_subtype;
- memcpy(req.tf_req, msg, msg_len);
-
- rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
- HWRM_CHECK_RESULT();
-
- /* Copy the resp to user provided response buffer */
- if (response != NULL)
- /* Post process response data. We need to copy only
- * the 'payload' as the HWRM data structure really is
- * HWRM header + msg header + payload and the TFLIB
- * only provided a payload place holder.
- */
- if (response_len != 0) {
- memcpy(response,
- resp->tf_resp,
- response_len);
- }
-
- /* Extract the internal tflib response code */
- *tf_response_code = resp->tf_resp_code;
- HWRM_UNLOCK();
-
- return rc;
-}
-
int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
int rc = 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index a82d9fb3ef..f9d9fe0ef2 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -79,16 +79,6 @@ struct hwrm_func_qstats_output;
bp->rx_cos_queue[x].profile = \
resp->queue_id##x##_service_profile
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len);
-
int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
bool use_kong_mb,
uint16_t msg_type,
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index 206935d18a..f812e471d1 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -30,9 +30,7 @@ sources += files(
'tf_identifier.c',
'tf_if_tbl.c',
'tf_session.c',
- 'tf_shadow_tcam.c',
'tf_tcam.c',
'tf_tcam_shared.c',
- 'tf_shadow_identifier.c',
'tf_hash.c',
'tf_device_p58.c')
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 90ff93946b..038e439101 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -917,7 +917,6 @@ tf_free_tcam_entry(struct tf *tfp,
return 0;
}
-#ifdef TF_TCAM_SHARED
int
tf_move_tcam_shared_entries(struct tf *tfp,
struct tf_move_tcam_shared_entries_parms *parms)
@@ -1019,7 +1018,6 @@ tf_clear_tcam_shared_entries(struct tf *tfp,
return 0;
}
-#endif /* TF_TCAM_SHARED */
int
tf_alloc_tbl_entry(struct tf *tfp,
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index f891d7a48f..814eff68da 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -337,41 +337,6 @@ enum tf_tbl_type {
TF_TBL_TYPE_MAX
};
-/** Enable Shared TCAM Management
- *
- * This feature allows for management of high and low pools within
- * the WC TCAM. These pools are only valid when this feature is enabled.
- *
- * For normal OVS-DPDK operation, this feature is not required and can
- * be disabled by commenting out TF_TCAM_SHARED in this header file.
- *
- * Operation:
- *
- * When a shared session is created with WC TCAM entries allocated during
- * tf_open_session(), the TF_TCAM_TBL_TYPE_WC_TCAM pool entries will be divided
- * into 2 equal pools - TF_TCAM_TBL_TYPE_WC_TCAM_HIGH and
- * TF_TCAM_TBL_TYPE_WC_TCAM_LOW.
- *
- * The user will allocate and free entries from either of these pools to obtain
- * WC_TCAM entry offsets. For the WC_TCAM_HI/LO management, alloc/free is done
- * using the tf_alloc_tcam_entry()/tf_free_tcam_entry() APIs for the shared
- * session.
- *
- * The use case for this feature is so that applications can have a shared
- * session and use the TF core to allocate/set/free entries within a given
- * region of the WC_TCAM within the shared session. Application A only writes
- * to the LOW region for example and Application B only writes to the HIGH
- * region during normal operation. After Application A goes down, Application
- * B may decide to overwrite the LOW region with the HIGH region's entries
- * and switch to the low region.
- *
- * For other TCAM types in the shared session, no alloc/free operations are
- * permitted. Only set should be used for other TCAM table types after getting
- * the range as provided by the tf_get_resource_info() API.
- *
- */
-#define TF_TCAM_SHARED 1
-
/**
* TCAM table type
*/
@@ -390,12 +355,10 @@ enum tf_tcam_tbl_type {
TF_TCAM_TBL_TYPE_CT_RULE_TCAM,
/** Virtual Edge Bridge TCAM */
TF_TCAM_TBL_TYPE_VEB_TCAM,
-#ifdef TF_TCAM_SHARED
/** Wildcard TCAM HI Priority */
TF_TCAM_TBL_TYPE_WC_TCAM_HIGH,
/** Wildcard TCAM Low Priority */
TF_TCAM_TBL_TYPE_WC_TCAM_LOW,
-#endif /* TF_TCAM_SHARED */
TF_TCAM_TBL_TYPE_MAX
};
@@ -626,20 +589,6 @@ struct tf_open_session_parms {
* 0000:02:00.0. The name for shared session is 0000:02:00.0-tf_shared.
*/
char ctrl_chan_name[TF_SESSION_NAME_MAX];
- /**
- * [in] shadow_copy
- *
- * Boolean controlling the use and availability of shadow
- * copy. Shadow copy will allow the TruFlow to keep track of
- * resource content on the firmware side without having to
- * query firmware. Additional private session core_data will
- * be allocated if this boolean is set to 'true', default
- * 'false'.
- *
- * Size of memory depends on the NVM Resource settings for the
- * control channel.
- */
- bool shadow_copy;
/**
* [in/out] session_id
*
@@ -1045,9 +994,6 @@ struct tf_search_identifier_parms {
* TruFlow core will allocate a free id from the per identifier resource type
* pool reserved for the session during tf_open(). No firmware is involved.
*
- * If shadow copy is enabled, the internal ref_cnt is set to 1 in the
- * shadow table for a newly allocated resource.
- *
* Returns success or failure code.
*/
int tf_alloc_identifier(struct tf *tfp,
@@ -1061,8 +1007,7 @@ int tf_alloc_identifier(struct tf *tfp,
* complete pool is returned to the firmware.
*
* additional operation (experimental)
- * Decrement reference count. Only release resource once refcnt goes to 0 if
- * shadow copy is enabled.
+ * Decrement reference count.
*
* Returns success or failure code.
*/
@@ -1072,19 +1017,6 @@ int tf_free_identifier(struct tf *tfp,
/**
* Search identifier resource (experimental)
*
- * If the shadow copy is enabled search_id is used to search for a matching
- * entry in the shadow table. The shadow table consists of an array of
- * reference counts indexed by identifier. If a matching entry is found hit is
- * set to TRUE, refcnt is increased by 1 and returned. Otherwise, hit is
- * set to false and refcnt is set to 0.
- *
- * TODO: we may need a per table internal shadow copy enable flag to stage
- * the shadow table implementation. We do not need the shadow table for other
- * tables at this time so we may only want to enable the identifier shadow.
- *
- * TODO: remove this pseudocode below added to show that if search fails
- * we shouldn't allocate a new entry but return.
- *
* identifier alloc (search_en=1)
* if (ident is allocated and ref_cnt >=1)
* return ident - hit is set, incr refcnt
@@ -1262,11 +1194,9 @@ int tf_free_tbl_scope(struct tf *tfp,
*
* @ref tf_free_tcam_entry
*
-#ifdef TF_TCAM_SHARED
* @ref tf_move_tcam_shared_entries
*
* @ref tf_clear_tcam_shared_entries
-#endif
*/
/**
@@ -1332,14 +1262,9 @@ struct tf_search_tcam_entry_parms {
*
* Search for a TCAM entry
*
- * This function searches the shadow copy of the TCAM table for a matching
- * entry. Key and mask must match for hit to be set. Only TruFlow core data
- * is accessed. If shadow_copy is not enabled, an error is returned.
- *
* Implementation:
*
- * A hash is performed on the key/mask data and mapped to a shadow copy entry
- * where the full key/mask is populated. If the full key/mask matches the
+ * If the full key/mask matches the
* entry, hit is set, ref_cnt is incremented, and search_status indicates what
* action the caller can take regarding setting the entry.
*
@@ -1416,8 +1341,7 @@ struct tf_alloc_tcam_entry_parms {
*
* This function allocates a TCAM table record. This function
* will attempt to allocate a TCAM table entry from the session
- * owned TCAM entries or search a shadow copy of the TCAM table for a
- * matching entry if search is enabled. Key, mask and result must match for
+ * owned TCAM entries. Key, mask and result must match for
* hit to be set. Only TruFlow core data is accessed.
* A hash table to entry mapping is maintained for search purposes. If
* search is not enabled, the first available free entry is returned based
@@ -1568,7 +1492,6 @@ struct tf_free_tcam_entry_parms {
int tf_free_tcam_entry(struct tf *tfp,
struct tf_free_tcam_entry_parms *parms);
-#ifdef TF_TCAM_SHARED
/**
* tf_move_tcam_shared_entries parameter definition
*/
@@ -1633,7 +1556,6 @@ struct tf_clear_tcam_shared_entries_parms {
int tf_clear_tcam_shared_entries(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-#endif /* TF_TCAM_SHARED */
/**
* @page table Table Access
*
@@ -1854,9 +1776,6 @@ struct tf_get_tbl_entry_parms {
*
* Used to retrieve a previous set index table entry.
*
- * Reads and compares with the shadow table copy (if enabled) (only
- * for internal objects).
- *
* Returns success or failure code. Failure will be returned if the
* provided data buffer is too small for the data type requested.
*/
@@ -2165,9 +2084,7 @@ int tf_delete_em_entry(struct tf *tfp,
* succeeds, a pointer to the matching entry and the result record associated
* with the matching entry will be provided.
*
- * If flow_handle is set, search shadow copy.
- *
- * Otherwise, query the fw with key to get result.
+ * Query the fw with key to get result.
*
* External:
*
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index a35d22841c..1c97218b5b 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -9,10 +9,8 @@
#include "tfp.h"
#include "tf_em.h"
#include "tf_rm.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
#include "tf_tbl_sram.h"
-#endif /* TF_TCAM_SHARED */
struct tf;
@@ -67,9 +65,6 @@ tf_dev_reservation_check(uint16_t count,
* [in] tfp
* Pointer to TF handle
*
- * [in] shadow_copy
- * Flag controlling shadow copy DB creation
- *
* [in] resources
* Pointer to resource allocation information
*
@@ -82,7 +77,6 @@ tf_dev_reservation_check(uint16_t count,
*/
static int
tf_dev_bind_p4(struct tf *tfp,
- bool shadow_copy,
struct tf_session_resources *resources,
struct tf_dev_info *dev_handle,
enum tf_wc_num_slice wc_num_slices)
@@ -115,7 +109,6 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
ident_cfg.num_elements = TF_IDENT_TYPE_MAX;
ident_cfg.cfg = tf_ident_p4;
- ident_cfg.shadow_copy = shadow_copy;
ident_cfg.resources = resources;
rc = tf_ident_bind(tfp, &ident_cfg);
if (rc) {
@@ -150,14 +143,9 @@ tf_dev_bind_p4(struct tf *tfp,
if (rsv_cnt) {
tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX;
tcam_cfg.cfg = tf_tcam_p4;
- tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
tcam_cfg.wc_num_slices = wc_num_slices;
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_bind(tfp, &tcam_cfg);
-#endif
if (rc) {
TFP_DRV_LOG(ERR,
"TCAM initialization failure\n");
@@ -223,7 +211,6 @@ tf_dev_bind_p4(struct tf *tfp,
*/
if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX;
if_tbl_cfg.cfg = tf_if_tbl_p4;
- if_tbl_cfg.shadow_copy = shadow_copy;
rc = tf_if_tbl_bind(tfp, &if_tbl_cfg);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -287,11 +274,7 @@ tf_dev_unbind_p4(struct tf *tfp)
* In case of residuals TCAMs are cleaned up first as to
* invalidate the pipeline in a clean manner.
*/
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_unbind(tfp);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_unbind(tfp);
-#endif /* TF_TCAM_SHARED */
if (rc) {
TFP_DRV_LOG(INFO,
"Device unbind failed, TCAM\n");
@@ -354,9 +337,6 @@ tf_dev_unbind_p4(struct tf *tfp)
* [in] tfp
* Pointer to TF handle
*
- * [in] shadow_copy
- * Flag controlling shadow copy DB creation
- *
* [in] resources
* Pointer to resource allocation information
*
@@ -369,7 +349,6 @@ tf_dev_unbind_p4(struct tf *tfp)
*/
static int
tf_dev_bind_p58(struct tf *tfp,
- bool shadow_copy,
struct tf_session_resources *resources,
struct tf_dev_info *dev_handle,
enum tf_wc_num_slice wc_num_slices)
@@ -400,7 +379,6 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
ident_cfg.num_elements = TF_IDENT_TYPE_MAX;
ident_cfg.cfg = tf_ident_p58;
- ident_cfg.shadow_copy = shadow_copy;
ident_cfg.resources = resources;
rc = tf_ident_bind(tfp, &ident_cfg);
if (rc) {
@@ -443,14 +421,9 @@ tf_dev_bind_p58(struct tf *tfp,
if (rsv_cnt) {
tcam_cfg.num_elements = TF_TCAM_TBL_TYPE_MAX;
tcam_cfg.cfg = tf_tcam_p58;
- tcam_cfg.shadow_copy = shadow_copy;
tcam_cfg.resources = resources;
tcam_cfg.wc_num_slices = wc_num_slices;
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_bind(tfp, &tcam_cfg);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_bind(tfp, &tcam_cfg);
-#endif
if (rc) {
TFP_DRV_LOG(ERR,
"TCAM initialization failure\n");
@@ -495,7 +468,6 @@ tf_dev_bind_p58(struct tf *tfp,
*/
if_tbl_cfg.num_elements = TF_IF_TBL_TYPE_MAX;
if_tbl_cfg.cfg = tf_if_tbl_p58;
- if_tbl_cfg.shadow_copy = shadow_copy;
rc = tf_if_tbl_bind(tfp, &if_tbl_cfg);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -560,11 +532,7 @@ tf_dev_unbind_p58(struct tf *tfp)
* In case of residuals TCAMs are cleaned up first as to
* invalidate the pipeline in a clean manner.
*/
-#ifdef TF_TCAM_SHARED
rc = tf_tcam_shared_unbind(tfp);
-#else /* !TF_TCAM_SHARED */
- rc = tf_tcam_unbind(tfp);
-#endif /* TF_TCAM_SHARED */
if (rc) {
TFP_DRV_LOG(INFO,
"Device unbind failed, TCAM\n");
@@ -629,7 +597,6 @@ tf_dev_unbind_p58(struct tf *tfp)
int
tf_dev_bind(struct tf *tfp __rte_unused,
enum tf_device_type type,
- bool shadow_copy,
struct tf_session_resources *resources,
uint16_t wc_num_slices,
struct tf_dev_info *dev_handle)
@@ -639,14 +606,12 @@ tf_dev_bind(struct tf *tfp __rte_unused,
case TF_DEVICE_TYPE_SR:
dev_handle->type = type;
return tf_dev_bind_p4(tfp,
- shadow_copy,
resources,
dev_handle,
wc_num_slices);
case TF_DEVICE_TYPE_THOR:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
- shadow_copy,
resources,
dev_handle,
wc_num_slices);
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index bfb5de4370..bc6de60423 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -11,9 +11,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
@@ -86,7 +84,6 @@ struct tf_hcapi_resource_map {
*/
int tf_dev_bind(struct tf *tfp,
enum tf_device_type type,
- bool shadow_copy,
struct tf_session_resources *resources,
uint16_t wc_num_slices,
struct tf_dev_info *dev_handle);
@@ -705,7 +702,6 @@ struct tf_dev_ops {
int (*tf_dev_get_tcam)(struct tf *tfp,
struct tf_tcam_get_parms *parms);
-#ifdef TF_TCAM_SHARED
/**
* Move TCAM shared entries
*
@@ -738,8 +734,6 @@ struct tf_dev_ops {
int (*tf_dev_clear_tcam)(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-#endif /* TF_TCAM_SHARED */
-
/**
* Retrieves the tcam resource info.
*
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index b8b3dcbb3f..72c6b1cde8 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -10,9 +10,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif /* TF_TCAM_SHARED */
#include "tf_em.h"
#include "tf_if_tbl.h"
#include "tfp.h"
@@ -540,20 +538,12 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
.tf_dev_get_bulk_sram_tbl = NULL,
.tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
-#ifdef TF_TCAM_SHARED
.tf_dev_alloc_tcam = tf_tcam_shared_alloc,
.tf_dev_free_tcam = tf_tcam_shared_free,
.tf_dev_set_tcam = tf_tcam_shared_set,
.tf_dev_get_tcam = tf_tcam_shared_get,
.tf_dev_move_tcam = tf_tcam_shared_move_p4,
.tf_dev_clear_tcam = tf_tcam_shared_clear,
-#else /* !TF_TCAM_SHARED */
- .tf_dev_alloc_tcam = tf_tcam_alloc,
- .tf_dev_free_tcam = tf_tcam_free,
- .tf_dev_set_tcam = tf_tcam_set,
- .tf_dev_get_tcam = tf_tcam_get,
-#endif
- .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_delete_int_entry,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index 8179287e46..f8b424ebc9 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -10,9 +10,7 @@
#include "tf_identifier.h"
#include "tf_tbl.h"
#include "tf_tcam.h"
-#ifdef TF_TCAM_SHARED
#include "tf_tcam_shared.h"
-#endif /* TF_TCAM_SHARED */
#include "tf_em.h"
#include "tf_if_tbl.h"
#include "tfp.h"
@@ -848,20 +846,12 @@ const struct tf_dev_ops tf_dev_ops_p58 = {
.tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
.tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
.tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
-#ifdef TF_TCAM_SHARED
.tf_dev_alloc_tcam = tf_tcam_shared_alloc,
.tf_dev_free_tcam = tf_tcam_shared_free,
.tf_dev_set_tcam = tf_tcam_shared_set,
.tf_dev_get_tcam = tf_tcam_shared_get,
.tf_dev_move_tcam = tf_tcam_shared_move_p58,
.tf_dev_clear_tcam = tf_tcam_shared_clear,
-#else /* !TF_TCAM_SHARED */
- .tf_dev_alloc_tcam = tf_tcam_alloc,
- .tf_dev_free_tcam = tf_tcam_free,
- .tf_dev_set_tcam = tf_tcam_set,
- .tf_dev_get_tcam = tf_tcam_get,
-#endif
- .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
.tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
.tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
.tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index c491f77a2b..8131d8754d 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -6,7 +6,6 @@
#include <rte_common.h>
#include "tf_identifier.h"
-#include "tf_shadow_identifier.h"
#include "tf_common.h"
#include "tf_rm.h"
#include "tf_util.h"
@@ -15,16 +14,6 @@
struct tf;
-/**
- * Identifier shadow DBs.
- */
-static void *ident_shadow_db[TF_DIR_MAX];
-
-/**
- * Shadow DB Init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
-
int
tf_ident_bind(struct tf *tfp,
struct tf_ident_cfg_parms *parms)
@@ -33,8 +22,6 @@ tf_ident_bind(struct tf *tfp,
int db_rc[TF_DIR_MAX] = { 0 };
int i;
struct tf_rm_create_db_parms db_cfg = { 0 };
- struct tf_shadow_ident_cfg_parms shadow_cfg = { 0 };
- struct tf_shadow_ident_create_db_parms shadow_cdb = { 0 };
struct ident_rm_db *ident_db;
struct tfp_calloc_parms cparms;
struct tf_session *tfs;
@@ -74,23 +61,6 @@ tf_ident_bind(struct tf *tfp,
db_rc[i] = tf_rm_create_db_no_reservation(tfp, &db_cfg);
else
db_rc[i] = tf_rm_create_db(tfp, &db_cfg);
-
- if (parms->shadow_copy) {
- shadow_cfg.alloc_cnt =
- parms->resources->ident_cnt[i].cnt;
- shadow_cdb.num_elements = parms->num_elements;
- shadow_cdb.tf_shadow_ident_db = &ident_shadow_db[i];
- shadow_cdb.cfg = &shadow_cfg;
- rc = tf_shadow_ident_create_db(&shadow_cdb);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Ident shadow DB creation failed\n",
- tf_dir_2_str(i));
-
- return rc;
- }
- shadow_init = 1;
- }
}
/* No db created */
@@ -111,7 +81,6 @@ tf_ident_unbind(struct tf *tfp)
int rc = 0;
int i;
struct tf_rm_free_db_parms fparms = { 0 };
- struct tf_shadow_ident_free_db_parms sparms = { 0 };
struct ident_rm_db *ident_db;
void *ident_db_ptr = NULL;
@@ -132,22 +101,8 @@ tf_ident_unbind(struct tf *tfp)
TFP_DRV_LOG(ERR,
"rm free failed on unbind\n");
}
- if (shadow_init) {
- sparms.tf_shadow_ident_db = ident_shadow_db[i];
- rc = tf_shadow_ident_free_db(&sparms);
- if (rc) {
- /* TODO: If there are failures on unbind we
- * really just have to try until all DBs are
- * attempted to be cleared.
- */
- }
- ident_shadow_db[i] = NULL;
- }
ident_db->ident_db[i] = NULL;
}
-
- shadow_init = 0;
-
return 0;
}
@@ -159,7 +114,6 @@ tf_ident_alloc(struct tf *tfp __rte_unused,
uint32_t id;
uint32_t base_id;
struct tf_rm_allocate_parms aparms = { 0 };
- struct tf_shadow_ident_insert_parms iparms = { 0 };
struct ident_rm_db *ident_db;
void *ident_db_ptr = NULL;
@@ -187,23 +141,7 @@ tf_ident_alloc(struct tf *tfp __rte_unused,
return rc;
}
- if (shadow_init) {
- iparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- iparms.type = parms->type;
- iparms.id = base_id;
-
- rc = tf_shadow_ident_insert(&iparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed insert shadow DB, type:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
- }
-
*parms->id = id;
-
return 0;
}
@@ -214,7 +152,6 @@ tf_ident_free(struct tf *tfp __rte_unused,
int rc;
struct tf_rm_is_allocated_parms aparms = { 0 };
struct tf_rm_free_parms fparms = { 0 };
- struct tf_shadow_ident_remove_parms rparms = { 0 };
int allocated = 0;
uint32_t base_id;
struct ident_rm_db *ident_db;
@@ -250,27 +187,6 @@ tf_ident_free(struct tf *tfp __rte_unused,
return -EINVAL;
}
- if (shadow_init) {
- rparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- rparms.type = parms->type;
- rparms.id = base_id;
- rparms.ref_cnt = parms->ref_cnt;
-
- rc = tf_shadow_ident_remove(&rparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: ref_cnt was 0 in shadow DB,"
- " type:%d, index:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->id);
- return rc;
- }
-
- if (*rparms.ref_cnt > 0)
- return 0;
- }
-
/* Free requested element */
fparms.rm_db = ident_db->ident_db[parms->dir];
fparms.subtype = parms->type;
@@ -294,7 +210,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
{
int rc;
struct tf_rm_is_allocated_parms aparms = { 0 };
- struct tf_shadow_ident_search_parms sparms = { 0 };
int allocated = 0;
uint32_t base_id;
struct ident_rm_db *ident_db;
@@ -302,13 +217,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
TF_CHECK_PARMS2(tfp, parms);
- if (!shadow_init) {
- TFP_DRV_LOG(ERR,
- "%s: Identifier Shadow copy is not enabled\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -336,22 +244,6 @@ tf_ident_search(struct tf *tfp __rte_unused,
parms->search_id);
return -EINVAL;
}
-
- sparms.tf_shadow_ident_db = ident_shadow_db[parms->dir];
- sparms.type = parms->type;
- sparms.search_id = base_id;
- sparms.hit = parms->hit;
- sparms.ref_cnt = parms->ref_cnt;
-
- rc = tf_shadow_ident_search(&sparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Failed search shadow DB, type:%d\n",
- tf_dir_2_str(parms->dir),
- parms->type);
- return rc;
- }
-
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h
index 55c093802e..285ff11ce2 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.h
+++ b/drivers/net/bnxt/tf_core/tf_identifier.h
@@ -22,10 +22,6 @@ struct tf_ident_cfg_parms {
* [in] Identifier configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * [in] Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* [in] Session resource allocations
*/
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h
index 9f081c8196..bea2f07324 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h
@@ -84,14 +84,6 @@ struct tf_if_tbl_cfg_parms {
* Table Type element configuration array
*/
struct tf_if_tbl_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_if_tbl_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
};
/**
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index c30c0e7029..d0a0916c6a 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -141,8 +141,6 @@ tf_session_create(struct tf *tfp,
/* Return the allocated session id */
session_id->id = session->session_id.id;
- session->shadow_copy = parms->open_cfg->shadow_copy;
-
/* Init session client list */
ll_init(&session->client_ll);
@@ -200,7 +198,6 @@ tf_session_create(struct tf *tfp,
rc = tf_dev_bind(tfp,
parms->open_cfg->device_type,
- session->shadow_copy,
&parms->open_cfg->resources,
parms->open_cfg->wc_num_slices,
&session->dev);
@@ -360,7 +357,7 @@ tf_session_client_create(struct tf *tfp,
* - (-EINVAL) on failure.
* - (-ENOTFOUND) error, client not owned by the session.
* - (-ENOTSUPP) error, unable to destroy client as its the last
- * client. Please use the tf_session_close().
+ * client. Please use the tf_session_close().
*/
static int
tf_session_client_destroy(struct tf *tfp,
@@ -992,8 +989,6 @@ tf_session_set_db(struct tf *tfp,
return rc;
}
-#ifdef TF_TCAM_SHARED
-
int
tf_session_get_tcam_shared_db(struct tf *tfp,
void **tcam_shared_db_handle)
@@ -1070,8 +1065,6 @@ tf_session_set_sram_db(struct tf *tfp,
return rc;
}
-#endif /* TF_TCAM_SHARED */
-
int
tf_session_get_global_db(struct tf *tfp,
void **global_handle)
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index 19a96c28b1..a6716dfff4 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -48,8 +48,7 @@
*
* Shared memory containing private TruFlow session information.
* Through this structure the session can keep track of resource
- * allocations and (if so configured) any shadow copy of flow
- * information. It also holds info about Session Clients.
+ * allocations. It also holds info about Session Clients.
*
* Memory is assigned to the Truflow instance by way of
* tf_open_session. Memory is allocated and owned by i.e. ULP.
@@ -86,19 +85,6 @@ struct tf_session {
*/
bool shared_session_creator;
- /**
- * Boolean controlling the use and availability of shadow
- * copy. Shadow copy will allow the TruFlow Core to keep track
- * of resource content on the firmware side without having to
- * query firmware. Additional private session core_data will
- * be allocated if this boolean is set to 'true', default
- * 'false'.
- *
- * Size of memory depends on the NVM Resource settings for the
- * control channel.
- */
- bool shadow_copy;
-
/**
* Session Reference Count. To keep track of functions per
* session the ref_count is updated. There is also a
@@ -159,12 +145,10 @@ struct tf_session {
*/
void *em_pool[TF_DIR_MAX];
-#ifdef TF_TCAM_SHARED
/**
* tcam db reference for the session
*/
void *tcam_shared_db_handle;
-#endif /* TF_TCAM_SHARED */
/**
* SRAM db reference for the session
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c b/drivers/net/bnxt/tf_core/tf_shadow_identifier.c
deleted file mode 100644
index dc9606712c..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#include <rte_common.h>
-
-#include "tf_shadow_identifier.h"
-#include "tf_common.h"
-#include "tf_util.h"
-#include "tfp.h"
-
-/**
- * Shadow identifier DB element
- */
-struct tf_shadow_ident_element {
- /**
- * Identifier
- */
- uint32_t *id;
-
- /**
- * Reference count, array of number of identifier type entries
- */
- uint32_t *ref_count;
-};
-
-/**
- * Shadow identifier DB definition
- */
-struct tf_shadow_ident_db {
- /**
- * Number of elements in the DB
- */
- uint16_t num_entries;
-
- /**
- * The DB consists of an array of elements
- */
- struct tf_shadow_ident_element *db;
-};
-
-int
-tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms)
-{
- int rc;
- int i;
- struct tfp_calloc_parms cparms;
- struct tf_shadow_ident_db *shadow_db;
- struct tf_shadow_ident_element *db;
-
- TF_CHECK_PARMS1(parms);
-
- /* Build the shadow DB per the request */
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_ident_db);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db = (void *)cparms.mem_va;
-
- /* Build the DB within shadow DB */
- cparms.nitems = parms->num_elements;
- cparms.size = sizeof(struct tf_shadow_ident_element);
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db->db = (struct tf_shadow_ident_element *)cparms.mem_va;
- shadow_db->num_entries = parms->num_elements;
-
- db = shadow_db->db;
- for (i = 0; i < parms->num_elements; i++) {
- /* If the element didn't request an allocation no need
- * to create a pool nor verify if we got a reservation.
- */
- if (parms->cfg->alloc_cnt[i] == 0)
- continue;
-
- /* Create array */
- cparms.nitems = parms->cfg->alloc_cnt[i];
- cparms.size = sizeof(uint32_t);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Array alloc failed, type:%d\n",
- tf_dir_2_str(parms->dir),
- i);
- goto fail;
- }
- db[i].ref_count = (uint32_t *)cparms.mem_va;
- }
-
- *parms->tf_shadow_ident_db = (void *)shadow_db;
-
- return 0;
-fail:
- tfp_free((void *)db->ref_count);
- tfp_free((void *)db);
- tfp_free((void *)shadow_db);
- parms->tf_shadow_ident_db = NULL;
-
- return -EINVAL;
-}
-
-int
-tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms)
-{
- int i;
- struct tf_shadow_ident_db *shadow_db;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- for (i = 0; i < shadow_db->num_entries; i++)
- tfp_free((void *)shadow_db->db[i].ref_count);
-
- tfp_free((void *)shadow_db->db);
- tfp_free((void *)parms->tf_shadow_ident_db);
-
- return 0;
-}
-
-int
-tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
- uint32_t ref_cnt = 0;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- ref_cnt = shadow_db->db[parms->type].ref_count[parms->search_id];
- if (ref_cnt > 0) {
- *parms->hit = 1;
- *parms->ref_cnt = ++ref_cnt;
- shadow_db->db[parms->type].ref_count[parms->search_id] =
- ref_cnt;
- } else {
- *parms->hit = 0;
- *parms->ref_cnt = 0;
- }
-
-
- return 0;
-}
-
-#define ID_REF_CNT_MAX 0xffffffff
-int
-tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
-
- /* In case of overflow, ref count keeps the max value */
- if (shadow_db->db[parms->type].ref_count[parms->id] < ID_REF_CNT_MAX)
- shadow_db->db[parms->type].ref_count[parms->id]++;
- else
- TFP_DRV_LOG(ERR,
- "Identifier %d in type %d reaches the max ref_cnt\n",
- parms->type,
- parms->id);
-
- parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
-
- return 0;
-}
-
-int
-tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms)
-{
- struct tf_shadow_ident_db *shadow_db;
- uint32_t ref_cnt = 0;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_ident_db *)parms->tf_shadow_ident_db;
- ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
- if (ref_cnt > 0)
- shadow_db->db[parms->type].ref_count[parms->id]--;
- else
- return -EINVAL;
-
- *parms->ref_cnt = shadow_db->db[parms->type].ref_count[parms->id];
-
- return 0;
-}
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h b/drivers/net/bnxt/tf_core/tf_shadow_identifier.h
deleted file mode 100644
index ff41eaad9f..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_identifier.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#ifndef _TF_SHADOW_IDENTIFIER_H_
-#define _TF_SHADOW_IDENTIFIER_H_
-
-#include "tf_core.h"
-
-struct tf;
-
-/**
- * The Shadow Identifier module provides shadow DB handling for identifier based
- * TF types. A shadow DB provides the capability that allows for reuse
- * of TF resources.
- *
- * A Shadow identifier DB is intended to be used by the Identifier Type module
- * only.
- */
-
-/**
- * Shadow DB configuration information for a single identifier type.
- *
- * It is used in an array of identifier types. The array must be ordered
- * by the TF type is represents.
- */
-struct tf_shadow_ident_cfg_parms {
- /**
- * TF Identifier type
- */
- enum tf_identifier_type type;
-
- /**
- * Number of entries the Shadow DB needs to hold
- */
- int num_entries;
-
- /**
- * Resource allocation count array. This array content
- * originates from the tf_session_resources that is passed in
- * on session open.
- * Array size is num_elements.
- */
- uint16_t *alloc_cnt;
-};
-
-/**
- * Shadow identifier DB creation parameters
- */
-struct tf_shadow_ident_create_db_parms {
- /**
- * [in] Receive or transmit direction.
- */
- enum tf_dir dir;
- /**
- * [in] Configuration information for the shadow db
- */
- struct tf_shadow_ident_cfg_parms *cfg;
- /**
- * [in] Number of elements in the parms structure
- */
- uint16_t num_elements;
- /**
- * [out] Shadow identifier DB handle
- */
- void **tf_shadow_ident_db;
-};
-
-/**
- * Shadow identifier DB free parameters
- */
-struct tf_shadow_ident_free_db_parms {
- /**
- * Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
-};
-
-/**
- * Shadow identifier search parameters
- */
-struct tf_shadow_ident_search_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Identifier type
- */
- enum tf_identifier_type type;
- /**
- * [in] id to search
- */
- uint16_t search_id;
- /**
- * [out] Index of the found element returned if hit
- */
- bool *hit;
- /**
- * [out] Reference count incremented if hit
- */
- uint32_t *ref_cnt;
-};
-
-/**
- * Shadow identifier insert parameters
- */
-struct tf_shadow_ident_insert_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Tbl type
- */
- enum tf_identifier_type type;
- /**
- * [in] Entry to update
- */
- uint16_t id;
- /**
- * [out] Reference count after insert
- */
- uint32_t ref_cnt;
-};
-
-/**
- * Shadow identifier remove parameters
- */
-struct tf_shadow_ident_remove_parms {
- /**
- * [in] Shadow identifier DB handle
- */
- void *tf_shadow_ident_db;
- /**
- * [in] Tbl type
- */
- enum tf_identifier_type type;
- /**
- * [in] Entry to update
- */
- uint16_t id;
- /**
- * [out] Reference count after removal
- */
- uint32_t *ref_cnt;
-};
-
-/**
- * @page shadow_ident Shadow identifier DB
- *
- * @ref tf_shadow_ident_create_db
- *
- * @ref tf_shadow_ident_free_db
- *
- * @reg tf_shadow_ident_search
- *
- * @reg tf_shadow_ident_insert
- *
- * @reg tf_shadow_ident_remove
- */
-
-/**
- * Creates and fills a Shadow identifier DB. The DB is indexed per the
- * parms structure.
- *
- * [in] parms
- * Pointer to create db parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_create_db(struct tf_shadow_ident_create_db_parms *parms);
-
-/**
- * Closes the Shadow identifier DB and frees all allocated
- * resources per the associated database.
- *
- * [in] parms
- * Pointer to the free DB parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_free_db(struct tf_shadow_ident_free_db_parms *parms);
-
-/**
- * Search Shadow identifier db for matching result
- *
- * [in] parms
- * Pointer to the search parameters
- *
- * Returns
- * - (0) if successful, element was found.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_search(struct tf_shadow_ident_search_parms *parms);
-
-/**
- * Inserts an element into the Shadow identifier DB. Ref_count after insert
- * will be incremented.
- *
- * [in] parms
- * Pointer to insert parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_insert(struct tf_shadow_ident_insert_parms *parms);
-
-/**
- * Removes an element from the Shadow identifier DB. Will fail if the
- * elements ref_count is 0. Ref_count after removal will be
- * decremented.
- *
- * [in] parms
- * Pointer to remove parameter
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_shadow_ident_remove(struct tf_shadow_ident_remove_parms *parms);
-
-#endif /* _TF_SHADOW_IDENTIFIER_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c b/drivers/net/bnxt/tf_core/tf_shadow_tcam.c
deleted file mode 100644
index 5fcd1f9107..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#include "tf_common.h"
-#include "tf_util.h"
-#include "tfp.h"
-#include "tf_tcam.h"
-#include "tf_shadow_tcam.h"
-#include "tf_hash.h"
-
-/**
- * The implementation includes 3 tables per tcam table type.
- * - hash table
- * - sized so that a minimum of 4 slots per shadow entry are available to
- * minimize the likelihood of collisions.
- * - shadow key table
- * - sized to the number of entries requested and is directly indexed
- * - the index is zero based and is the tcam index - the base address
- * - the key and mask are stored in the key table.
- * - The stored key is the AND of the key/mask in order to eliminate the need
- * to compare both the key and mask.
- * - shadow result table
- * - the result table is stored separately since it only needs to be accessed
- * when the key matches.
- * - the result has a back pointer to the hash table via the hb handle. The
- * hb handle is a 32 bit representation of the hash with a valid bit, bucket
- * element index, and the hash index. It is necessary to store the hb handle
- * with the result since subsequent removes only provide the tcam index.
- *
- * - Max entries is limited in the current implementation since bit 15 is the
- * valid bit in the hash table.
- * - A 16bit hash is calculated and masked based on the number of entries
- * - 64b wide bucket is used and broken into 4x16bit elements.
- * This decision is based on quicker bucket scanning to determine if any
- * elements are in use.
- * - bit 15 of each bucket element is the valid, this is done to prevent having
- * to read the larger key/result data for determining VALID. It also aids
- * in the more efficient scanning of the bucket for slot usage.
- */
-
-/*
- * The maximum number of shadow entries supported. The value also doubles as
- * the maximum number of hash buckets. There are only 15 bits of data per
- * bucket to point to the shadow tables.
- */
-#define TF_SHADOW_TCAM_ENTRIES_MAX (1 << 15)
-
-/* The number of elements(BE) per hash bucket (HB) */
-#define TF_SHADOW_TCAM_HB_NUM_ELEM (4)
-#define TF_SHADOW_TCAM_BE_VALID (1 << 15)
-#define TF_SHADOW_TCAM_BE_IS_VALID(be) (((be) & TF_SHADOW_TCAM_BE_VALID) != 0)
-
-/**
- * The hash bucket handle is 32b
- * - bit 31, the Valid bit
- * - bit 29-30, the element
- * - bits 0-15, the hash idx (is masked based on the allocated size)
- */
-#define TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hndl) (((hndl) & (1 << 31)) != 0)
-#define TF_SHADOW_TCAM_HB_HANDLE_CREATE(idx, be) ((1 << 31) | \
- ((be) << 29) | (idx))
-
-#define TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hdl) (((hdl) >> 29) & \
- (TF_SHADOW_TCAM_HB_NUM_ELEM - 1))
-
-#define TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hdl)((hdl) & \
- (ctxt)->hash_ctxt.hid_mask)
-
-/**
- * The idx provided by the caller is within a region, so currently the base is
- * either added or subtracted from the idx to ensure it can be used as a
- * compressed index
- */
-
-/* Convert the tcam index to a shadow index */
-#define TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, idx) ((idx) - \
- (ctxt)->shadow_ctxt.base_addr)
-
-/* Convert the shadow index to a tcam index */
-#define TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt, idx) ((idx) + \
- (ctxt)->shadow_ctxt.base_addr)
-
-/* Simple helper masks for clearing en element from the bucket */
-#define TF_SHADOW_TCAM_BE0_MASK_CLEAR(hb) ((hb) & 0xffffffffffff0000ull)
-#define TF_SHADOW_TCAM_BE1_MASK_CLEAR(hb) ((hb) & 0xffffffff0000ffffull)
-#define TF_SHADOW_TCAM_BE2_MASK_CLEAR(hb) ((hb) & 0xffff0000ffffffffull)
-#define TF_SHADOW_TCAM_BE3_MASK_CLEAR(hb) ((hb) & 0x0000ffffffffffffull)
-
-/**
- * This should be coming from external, but for now it is assumed that no key
- * is greater than 1K bits and no result is bigger than 128 bits. This makes
- * allocation of the hash table easier without having to allocate on the fly.
- */
-#define TF_SHADOW_TCAM_MAX_KEY_SZ 128
-#define TF_SHADOW_TCAM_MAX_RESULT_SZ 16
-
-/*
- * Local only defines for the internal data.
- */
-
-/**
- * tf_shadow_tcam_shadow_key_entry is the key/mask entry of the key table.
- * The key stored in the table is the masked version of the key. This is done
- * to eliminate the need of comparing both the key and mask.
- */
-struct tf_shadow_tcam_shadow_key_entry {
- uint8_t key[TF_SHADOW_TCAM_MAX_KEY_SZ];
- uint8_t mask[TF_SHADOW_TCAM_MAX_KEY_SZ];
-};
-
-/**
- * tf_shadow_tcam_shadow_result_entry is the result table entry.
- * The result table writes are broken into two phases:
- * - The search phase, which stores the hb_handle and key size and
- * - The set phase, which writes the result, refcnt, and result size
- */
-struct tf_shadow_tcam_shadow_result_entry {
- uint8_t result[TF_SHADOW_TCAM_MAX_RESULT_SZ];
- uint16_t result_size;
- uint16_t key_size;
- uint32_t refcnt;
- uint32_t hb_handle;
-};
-
-/**
- * tf_shadow_tcam_shadow_ctxt holds all information for accessing the key and
- * result tables.
- */
-struct tf_shadow_tcam_shadow_ctxt {
- struct tf_shadow_tcam_shadow_key_entry *sh_key_tbl;
- struct tf_shadow_tcam_shadow_result_entry *sh_res_tbl;
- uint32_t base_addr;
- uint16_t num_entries;
- uint16_t alloc_idx;
-};
-
-/**
- * tf_shadow_tcam_hash_ctxt holds all information related to accessing the hash
- * table.
- */
-struct tf_shadow_tcam_hash_ctxt {
- uint64_t *hashtbl;
- uint16_t hid_mask;
- uint16_t hash_entries;
-};
-
-/**
- * tf_shadow_tcam_ctxt holds the hash and shadow tables for the current shadow
- * tcam db. This structure is per tcam table type as each tcam table has it's
- * own shadow and hash table.
- */
-struct tf_shadow_tcam_ctxt {
- struct tf_shadow_tcam_shadow_ctxt shadow_ctxt;
- struct tf_shadow_tcam_hash_ctxt hash_ctxt;
-};
-
-/**
- * tf_shadow_tcam_db is the allocated db structure returned as an opaque
- * void * pointer to the caller during create db. It holds the pointers for
- * each tcam associated with the db.
- */
-struct tf_shadow_tcam_db {
- /* Each context holds the shadow and hash table information */
- struct tf_shadow_tcam_ctxt *ctxt[TF_TCAM_TBL_TYPE_MAX];
-};
-
-/**
- * Returns the number of entries in the contexts shadow table.
- */
-static inline uint16_t
-tf_shadow_tcam_sh_num_entries_get(struct tf_shadow_tcam_ctxt *ctxt)
-{
- return ctxt->shadow_ctxt.num_entries;
-}
-
-/**
- * Compare the give key with the key in the shadow table.
- *
- * Returns 0 if the keys match
- */
-static int
-tf_shadow_tcam_key_cmp(struct tf_shadow_tcam_ctxt *ctxt,
- uint8_t *key,
- uint8_t *mask,
- uint16_t sh_idx,
- uint16_t size)
-{
- if (size != ctxt->shadow_ctxt.sh_res_tbl[sh_idx].key_size ||
- sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !key || !mask)
- return -1;
-
- return memcmp(key, ctxt->shadow_ctxt.sh_key_tbl[sh_idx].key, size);
-}
-
-/**
- * Copies the shadow result to the result.
- *
- * Returns 0 on failure
- */
-static void *
-tf_shadow_tcam_res_cpy(struct tf_shadow_tcam_ctxt *ctxt,
- uint8_t *result,
- uint16_t sh_idx,
- uint16_t size)
-{
- if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) || !result)
- return 0;
-
- if (ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result_size != size)
- return 0;
-
- return memcpy(result,
- ctxt->shadow_ctxt.sh_res_tbl[sh_idx].result,
- size);
-}
-
-/**
- * Using a software based CRC function for now, but will look into using hw
- * assisted in the future.
- */
-static uint32_t
-tf_shadow_tcam_crc32_calc(uint8_t *key, uint32_t len)
-{
- return tf_hash_calc_crc32(key, len);
-}
-
-/**
- * Free the memory associated with the context.
- */
-static void
-tf_shadow_tcam_ctxt_delete(struct tf_shadow_tcam_ctxt *ctxt)
-{
- if (!ctxt)
- return;
-
- tfp_free(ctxt->hash_ctxt.hashtbl);
- tfp_free(ctxt->shadow_ctxt.sh_key_tbl);
- tfp_free(ctxt->shadow_ctxt.sh_res_tbl);
-}
-
-/**
- * The TF Shadow TCAM context is per TCAM and holds all information relating to
- * managing the shadow and search capability. This routine allocated data that
- * needs to be deallocated by the tf_shadow_tcam_ctxt_delete prior when deleting
- * the shadow db.
- */
-static int
-tf_shadow_tcam_ctxt_create(struct tf_shadow_tcam_ctxt *ctxt,
- uint16_t num_entries,
- uint16_t base_addr)
-{
- struct tfp_calloc_parms cparms;
- uint16_t hash_size = 1;
- uint16_t hash_mask;
- int rc;
-
- /* Hash table is a power of two that holds the number of entries */
- if (num_entries > TF_SHADOW_TCAM_ENTRIES_MAX) {
- TFP_DRV_LOG(ERR, "Too many entries for shadow %d > %d\n",
- num_entries,
- TF_SHADOW_TCAM_ENTRIES_MAX);
- return -ENOMEM;
- }
-
- while (hash_size < num_entries)
- hash_size = hash_size << 1;
-
- hash_mask = hash_size - 1;
-
- /* Allocate the hash table */
- cparms.nitems = hash_size;
- cparms.size = sizeof(uint64_t);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->hash_ctxt.hashtbl = cparms.mem_va;
- ctxt->hash_ctxt.hid_mask = hash_mask;
- ctxt->hash_ctxt.hash_entries = hash_size;
-
- /* allocate the shadow tables */
- /* allocate the shadow key table */
- cparms.nitems = num_entries;
- cparms.size = sizeof(struct tf_shadow_tcam_shadow_key_entry);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->shadow_ctxt.sh_key_tbl = cparms.mem_va;
-
- /* allocate the shadow result table */
- cparms.nitems = num_entries;
- cparms.size = sizeof(struct tf_shadow_tcam_shadow_result_entry);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
- ctxt->shadow_ctxt.sh_res_tbl = cparms.mem_va;
-
- ctxt->shadow_ctxt.num_entries = num_entries;
- ctxt->shadow_ctxt.base_addr = base_addr;
-
- return 0;
-error:
- tf_shadow_tcam_ctxt_delete(ctxt);
-
- return -ENOMEM;
-}
-
-/**
- * Get a shadow TCAM context given the db and the TCAM type
- */
-static struct tf_shadow_tcam_ctxt *
-tf_shadow_tcam_ctxt_get(struct tf_shadow_tcam_db *shadow_db,
- enum tf_tcam_tbl_type type)
-{
- if (type >= TF_TCAM_TBL_TYPE_MAX ||
- !shadow_db ||
- !shadow_db->ctxt[type])
- return NULL;
-
- return shadow_db->ctxt[type];
-}
-
-/**
- * Sets the hash entry into the table given the TCAM context, hash bucket
- * handle, and shadow index.
- */
-static inline int
-tf_shadow_tcam_set_hash_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint32_t hb_handle,
- uint16_t sh_idx)
-{
- uint16_t hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle);
- uint16_t be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle);
- uint64_t entry = sh_idx | TF_SHADOW_TCAM_BE_VALID;
-
- if (hid >= ctxt->hash_ctxt.hash_entries)
- return -EINVAL;
-
- ctxt->hash_ctxt.hashtbl[hid] |= entry << (be * 16);
- return 0;
-}
-
-/**
- * Clears the hash entry given the TCAM context and hash bucket handle.
- */
-static inline void
-tf_shadow_tcam_clear_hash_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint32_t hb_handle)
-{
- uint16_t hid, be;
- uint64_t *bucket;
-
- if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(hb_handle))
- return;
-
- hid = TF_SHADOW_TCAM_HB_HANDLE_HASH_GET(ctxt, hb_handle);
- be = TF_SHADOW_TCAM_HB_HANDLE_BE_GET(hb_handle);
- bucket = &ctxt->hash_ctxt.hashtbl[hid];
-
- switch (be) {
- case 0:
- *bucket = TF_SHADOW_TCAM_BE0_MASK_CLEAR(*bucket);
- break;
- case 1:
- *bucket = TF_SHADOW_TCAM_BE1_MASK_CLEAR(*bucket);
- break;
- case 2:
- *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket);
- break;
- case 3:
- *bucket = TF_SHADOW_TCAM_BE2_MASK_CLEAR(*bucket);
- break;
- default:
- /*
- * Since the BE_GET masks non-inclusive bits, this will not
- * happen.
- */
- break;
- }
-}
-
-/**
- * Clears the shadow key and result entries given the TCAM context and
- * shadow index.
- */
-static void
-tf_shadow_tcam_clear_sh_entry(struct tf_shadow_tcam_ctxt *ctxt,
- uint16_t sh_idx)
-{
- struct tf_shadow_tcam_shadow_key_entry *sk_entry;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (sh_idx >= tf_shadow_tcam_sh_num_entries_get(ctxt))
- return;
-
- sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[sh_idx];
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[sh_idx];
-
- /*
- * memset key/result to zero for now, possibly leave the data alone
- * in the future and rely on the valid bit in the hash table.
- */
- memset(sk_entry, 0, sizeof(struct tf_shadow_tcam_shadow_key_entry));
- memset(sr_entry, 0, sizeof(struct tf_shadow_tcam_shadow_result_entry));
-}
-
-/**
- * Binds the allocated tcam index with the hash and shadow tables.
- * The entry will be incomplete until the set has happened with the result
- * data.
- */
-int
-tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms)
-{
- int rc;
- int i;
- uint16_t idx, klen;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_shadow_tcam_shadow_key_entry *sk_entry;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
- uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ];
-
- if (!parms || !TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(parms->hb_handle) ||
- !parms->key || !parms->mask) {
- TFP_DRV_LOG(ERR, "Invalid parms\n");
- return -EINVAL;
- }
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, parms->type);
- if (!ctxt) {
- TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n",
- tf_tcam_tbl_2_str(parms->type));
- return -EINVAL;
- }
-
- memset(tkey, 0, sizeof(tkey));
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, parms->idx);
- klen = parms->key_size;
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt) ||
- klen > TF_SHADOW_TCAM_MAX_KEY_SZ) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid len (%d) > %d || oob idx %d\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- klen,
- TF_SHADOW_TCAM_MAX_KEY_SZ, idx);
-
- return -EINVAL;
- }
-
- rc = tf_shadow_tcam_set_hash_entry(ctxt, parms->hb_handle, idx);
- if (rc)
- return -EINVAL;
-
- sk_entry = &ctxt->shadow_ctxt.sh_key_tbl[idx];
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
-
- /*
- * Write the masked key to the table for more efficient comparisons
- * later.
- */
- for (i = 0; i < klen; i++)
- tkey[i] = parms->key[i] & parms->mask[i];
-
- memcpy(sk_entry->key, tkey, klen);
- memcpy(sk_entry->mask, parms->mask, klen);
-
- /* Write the result table */
- sr_entry->key_size = parms->key_size;
- sr_entry->hb_handle = parms->hb_handle;
- sr_entry->refcnt = 1;
-
- return 0;
-}
-
-/**
- * Deletes hash/shadow information if no more references.
- *
- * Returns 0 - The caller should delete the tcam entry in hardware.
- * Returns non-zero - The number of references to the entry
- */
-int
-tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms)
-{
- uint16_t idx;
- uint32_t hb_handle;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_tcam_free_parms *fparms;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (!parms || !parms->fparms) {
- TFP_DRV_LOG(ERR, "Invalid parms\n");
- return -EINVAL;
- }
-
- fparms = parms->fparms;
-
- /*
- * Initialize the reference count to zero. It will only be changed if
- * non-zero.
- */
- fparms->ref_cnt = 0;
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, fparms->type);
- if (!ctxt) {
- TFP_DRV_LOG(DEBUG, "%s no ctxt for table\n",
- tf_tcam_tbl_2_str(fparms->type));
- return 0;
- }
-
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, fparms->idx);
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) {
- TFP_DRV_LOG(DEBUG, "%s %d >= %d\n",
- tf_tcam_tbl_2_str(fparms->type),
- fparms->idx,
- tf_shadow_tcam_sh_num_entries_get(ctxt));
- return 0;
- }
-
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
- if (sr_entry->refcnt <= 1) {
- hb_handle = sr_entry->hb_handle;
- tf_shadow_tcam_clear_hash_entry(ctxt, hb_handle);
- tf_shadow_tcam_clear_sh_entry(ctxt, idx);
- } else {
- sr_entry->refcnt--;
- fparms->ref_cnt = sr_entry->refcnt;
- }
-
- return 0;
-}
-
-int
-tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms)
-{
- uint16_t len;
- uint8_t rcopy;
- uint64_t bucket;
- uint32_t i, hid32;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_shadow_tcam_db *shadow_db;
- uint16_t hid16, hb_idx, hid_mask, shtbl_idx, shtbl_key, be_valid;
- struct tf_tcam_alloc_search_parms *sparms;
- uint8_t tkey[TF_SHADOW_TCAM_MAX_KEY_SZ];
- uint32_t be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM;
-
- if (!parms || !parms->sparms) {
- TFP_DRV_LOG(ERR, "tcam search with invalid parms\n");
- return -EINVAL;
- }
-
- memset(tkey, 0, sizeof(tkey));
- sparms = parms->sparms;
-
- /* Initialize return values to invalid */
- sparms->hit = 0;
- sparms->search_status = REJECT;
- parms->hb_handle = 0;
- sparms->ref_cnt = 0;
- /* see if caller wanted the result */
- rcopy = sparms->result && sparms->result_size;
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type);
- if (!ctxt) {
- TFP_DRV_LOG(ERR, "%s Unable to get tcam mgr context\n",
- tf_tcam_tbl_2_str(sparms->type));
- return -EINVAL;
- }
-
- hid_mask = ctxt->hash_ctxt.hid_mask;
-
- len = sparms->key_size;
-
- if (len > TF_SHADOW_TCAM_MAX_KEY_SZ ||
- !sparms->key || !sparms->mask || !len) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid parms %d : %p : %p\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- len,
- sparms->key,
- sparms->mask);
- return -EINVAL;
- }
-
- /* Combine the key and mask */
- for (i = 0; i < len; i++)
- tkey[i] = sparms->key[i] & sparms->mask[i];
-
- /*
- * Calculate the crc32
- * Fold it to create a 16b value
- * Reduce it to fit the table
- */
- hid32 = tf_shadow_tcam_crc32_calc(tkey, len);
- hid16 = (uint16_t)(((hid32 >> 16) & 0xffff) ^ (hid32 & 0xffff));
- hb_idx = hid16 & hid_mask;
-
- bucket = ctxt->hash_ctxt.hashtbl[hb_idx];
-
- if (!bucket) {
- /* empty bucket means a miss and available entry */
- sparms->search_status = MISS;
- parms->hb_handle = TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, 0);
- sparms->idx = 0;
- return 0;
- }
-
- /* Set the avail to max so we can detect when there is an avail entry */
- be_avail = TF_SHADOW_TCAM_HB_NUM_ELEM;
- for (i = 0; i < TF_SHADOW_TCAM_HB_NUM_ELEM; i++) {
- shtbl_idx = (uint16_t)((bucket >> (i * 16)) & 0xffff);
- be_valid = TF_SHADOW_TCAM_BE_IS_VALID(shtbl_idx);
- if (!be_valid) {
- /* The element is avail, keep going */
- be_avail = i;
- continue;
- }
- /* There is a valid entry, compare it */
- shtbl_key = shtbl_idx & ~TF_SHADOW_TCAM_BE_VALID;
- if (!tf_shadow_tcam_key_cmp(ctxt,
- sparms->key,
- sparms->mask,
- shtbl_key,
- sparms->key_size)) {
- /*
- * It matches, increment the ref count if the caller
- * requested allocation and return the info
- */
- if (sparms->alloc)
- ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt++;
-
- sparms->hit = 1;
- sparms->search_status = HIT;
- parms->hb_handle =
- TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, i);
- sparms->idx = TF_SHADOW_TCAM_SHIDX_TO_IDX(ctxt,
- shtbl_key);
- sparms->ref_cnt =
- ctxt->shadow_ctxt.sh_res_tbl[shtbl_key].refcnt;
-
- /* copy the result, if caller wanted it. */
- if (rcopy &&
- !tf_shadow_tcam_res_cpy(ctxt,
- sparms->result,
- shtbl_key,
- sparms->result_size)) {
- /*
- * Should never get here, possible memory
- * corruption or something unexpected.
- */
- TFP_DRV_LOG(ERR, "Error copying result\n");
- return -EINVAL;
- }
-
- return 0;
- }
- }
-
- /* No hits, return avail entry if exists */
- if (be_avail < TF_SHADOW_TCAM_HB_NUM_ELEM) {
- parms->hb_handle =
- TF_SHADOW_TCAM_HB_HANDLE_CREATE(hb_idx, be_avail);
- sparms->search_status = MISS;
- sparms->hit = 0;
- sparms->idx = 0;
- } else {
- sparms->search_status = REJECT;
- }
-
- return 0;
-}
-
-int
-tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms)
-{
- uint16_t idx;
- struct tf_shadow_tcam_ctxt *ctxt;
- struct tf_tcam_set_parms *sparms;
- struct tf_shadow_tcam_db *shadow_db;
- struct tf_shadow_tcam_shadow_result_entry *sr_entry;
-
- if (!parms || !parms->sparms) {
- TFP_DRV_LOG(ERR, "Null parms\n");
- return -EINVAL;
- }
-
- sparms = parms->sparms;
- if (!sparms->result || !sparms->result_size) {
- TFP_DRV_LOG(ERR, "%s:%s No result to set.\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type));
- return -EINVAL;
- }
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- ctxt = tf_shadow_tcam_ctxt_get(shadow_db, sparms->type);
- if (!ctxt) {
- /* We aren't tracking this table, so return success */
- TFP_DRV_LOG(DEBUG, "%s Unable to get tcam mgr context\n",
- tf_tcam_tbl_2_str(sparms->type));
- return 0;
- }
-
- idx = TF_SHADOW_TCAM_IDX_TO_SHIDX(ctxt, sparms->idx);
- if (idx >= tf_shadow_tcam_sh_num_entries_get(ctxt)) {
- TFP_DRV_LOG(ERR, "%s:%s Invalid idx(0x%x)\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- sparms->idx);
- return -EINVAL;
- }
-
- /* Write the result table, the key/hash has been written already */
- sr_entry = &ctxt->shadow_ctxt.sh_res_tbl[idx];
-
- /*
- * If the handle is not valid, the bind was never called. We aren't
- * tracking this entry.
- */
- if (!TF_SHADOW_TCAM_HB_HANDLE_IS_VALID(sr_entry->hb_handle))
- return 0;
-
- if (sparms->result_size > TF_SHADOW_TCAM_MAX_RESULT_SZ) {
- TFP_DRV_LOG(ERR, "%s:%s Result length %d > %d\n",
- tf_dir_2_str(sparms->dir),
- tf_tcam_tbl_2_str(sparms->type),
- sparms->result_size,
- TF_SHADOW_TCAM_MAX_RESULT_SZ);
- return -EINVAL;
- }
-
- memcpy(sr_entry->result, sparms->result, sparms->result_size);
- sr_entry->result_size = sparms->result_size;
-
- return 0;
-}
-
-int
-tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms)
-{
- struct tf_shadow_tcam_db *shadow_db;
- int i;
-
- TF_CHECK_PARMS1(parms);
-
- shadow_db = (struct tf_shadow_tcam_db *)parms->shadow_db;
- if (!shadow_db) {
- TFP_DRV_LOG(DEBUG, "Shadow db is NULL cannot be freed\n");
- return -EINVAL;
- }
-
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- if (shadow_db->ctxt[i]) {
- tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]);
- tfp_free(shadow_db->ctxt[i]);
- }
- }
-
- tfp_free(shadow_db);
-
- return 0;
-}
-
-/**
- * Allocate the TCAM resources for search and allocate
- *
- */
-int tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms)
-{
- int rc;
- int i;
- uint16_t base;
- struct tfp_calloc_parms cparms;
- struct tf_shadow_tcam_db *shadow_db = NULL;
-
- TF_CHECK_PARMS1(parms);
-
- /* Build the shadow DB per the request */
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_tcam_db);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- return rc;
- shadow_db = (void *)cparms.mem_va;
-
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- /* If the element didn't request an allocation no need
- * to create a pool nor verify if we got a reservation.
- */
- if (!parms->cfg->alloc_cnt[i]) {
- shadow_db->ctxt[i] = NULL;
- continue;
- }
-
- cparms.nitems = 1;
- cparms.size = sizeof(struct tf_shadow_tcam_ctxt);
- cparms.alignment = 0;
- rc = tfp_calloc(&cparms);
- if (rc)
- goto error;
-
- shadow_db->ctxt[i] = cparms.mem_va;
- base = parms->cfg->base_addr[i];
- rc = tf_shadow_tcam_ctxt_create(shadow_db->ctxt[i],
- parms->cfg->alloc_cnt[i],
- base);
- if (rc)
- goto error;
- }
-
- *parms->shadow_db = (void *)shadow_db;
-
- TFP_DRV_LOG(INFO,
- "TF SHADOW TCAM - initialized\n");
-
- return 0;
-error:
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- if (shadow_db->ctxt[i]) {
- tf_shadow_tcam_ctxt_delete(shadow_db->ctxt[i]);
- tfp_free(shadow_db->ctxt[i]);
- }
- }
-
- tfp_free(shadow_db);
-
- return -ENOMEM;
-}
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h b/drivers/net/bnxt/tf_core/tf_shadow_tcam.h
deleted file mode 100644
index d6506b219a..0000000000
--- a/drivers/net/bnxt/tf_core/tf_shadow_tcam.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#ifndef _TF_SHADOW_TCAM_H_
-#define _TF_SHADOW_TCAM_H_
-
-#include "tf_core.h"
-
-/**
- * Shadow DB configuration information
- *
- * The shadow configuration is for all tcam table types for a direction
- */
-struct tf_shadow_tcam_cfg_parms {
- /**
- * [in] The number of elements in the alloc_cnt and base_addr
- * For now, it should always be equal to TF_TCAM_TBL_TYPE_MAX
- */
- int num_entries;
- /**
- * [in] Resource allocation count array
- * This array content originates from the tf_session_resources
- * that is passed in on session open
- * Array size is TF_TCAM_TBL_TYPE_MAX
- */
- uint16_t *alloc_cnt;
- /**
- * [in] The base index for each tcam table
- */
- uint16_t base_addr[TF_TCAM_TBL_TYPE_MAX];
-};
-
-/**
- * Shadow TCAM DB creation parameters. The shadow db for this direction
- * is returned
- */
-struct tf_shadow_tcam_create_db_parms {
- /**
- * [in] Receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] Configuration information for the shadow db
- */
- struct tf_shadow_tcam_cfg_parms *cfg;
- /**
- * [out] Shadow tcam DB handle
- */
- void **shadow_db;
-};
-
-/**
- * Create the shadow db for a single direction
- *
- * The returned shadow db must be free using the free db API when no longer
- * needed
- */
-int
-tf_shadow_tcam_create_db(struct tf_shadow_tcam_create_db_parms *parms);
-
-/**
- * Shadow TCAM free parameters
- */
-struct tf_shadow_tcam_free_db_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
-};
-
-/**
- * Free all resources associated with the shadow db
- */
-int
-tf_shadow_tcam_free_db(struct tf_shadow_tcam_free_db_parms *parms);
-
-/**
- * Shadow TCAM bind index parameters
- */
-struct tf_shadow_tcam_bind_index_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in] receive or transmit direction
- */
- enum tf_dir dir;
- /**
- * [in] TCAM table type
- */
- enum tf_tcam_tbl_type type;
- /**
- * [in] index of the entry to program
- */
- uint16_t idx;
- /**
- * [in] struct containing key
- */
- uint8_t *key;
- /**
- * [in] struct containing mask fields
- */
- uint8_t *mask;
- /**
- * [in] key size in bits (if search)
- */
- uint16_t key_size;
- /**
- * [in] The hash bucket handled returned from the search
- */
- uint32_t hb_handle;
-};
-
-/**
- * Binds the allocated tcam index with the hash and shadow tables
- */
-int
-tf_shadow_tcam_bind_index(struct tf_shadow_tcam_bind_index_parms *parms);
-
-/**
- * Shadow TCAM insert parameters
- */
-struct tf_shadow_tcam_insert_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in] The set parms from tf core
- */
- struct tf_tcam_set_parms *sparms;
-};
-
-/**
- * Set the entry into the tcam manager hash and shadow tables
- *
- * The search must have been used prior to setting the entry so that the
- * hash has been calculated and duplicate entries will not be added
- */
-int
-tf_shadow_tcam_insert(struct tf_shadow_tcam_insert_parms *parms);
-
-/**
- * Shadow TCAM remove parameters
- */
-struct tf_shadow_tcam_remove_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in,out] The set parms from tf core
- */
- struct tf_tcam_free_parms *fparms;
-};
-
-/**
- * Remove the entry from the tcam hash and shadow tables
- *
- * The search must have been used prior to setting the entry so that the
- * hash has been calculated and duplicate entries will not be added
- */
-int
-tf_shadow_tcam_remove(struct tf_shadow_tcam_remove_parms *parms);
-
-/**
- * Shadow TCAM search parameters
- */
-struct tf_shadow_tcam_search_parms {
- /**
- * [in] Shadow tcam DB handle
- */
- void *shadow_db;
- /**
- * [in,out] The search parameters from tf core
- */
- struct tf_tcam_alloc_search_parms *sparms;
- /**
- * [out] The hash handle to use for the set
- */
- uint32_t hb_handle;
-};
-
-/**
- * Search for an entry in the tcam hash/shadow tables
- *
- * If there is a miss, but there is room for insertion, the hb_handle returned
- * is used for insertion during the bind index API
- */
-int
-tf_shadow_tcam_search(struct tf_shadow_tcam_search_parms *parms);
-#endif
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 273f20858b..1c42a6adc7 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -14,20 +14,9 @@
#include "tfp.h"
#include "tf_session.h"
#include "tf_msg.h"
-#include "tf_shadow_tcam.h"
struct tf;
-/**
- * TCAM Shadow DBs
- */
-static void *shadow_tcam_db[TF_DIR_MAX];
-
-/**
- * Shadow init flag, set on bind and cleared on unbind
- */
-static uint8_t shadow_init;
-
int
tf_tcam_bind(struct tf *tfp,
struct tf_tcam_cfg_parms *parms)
@@ -40,9 +29,6 @@ tf_tcam_bind(struct tf *tfp,
struct tf_rm_create_db_parms db_cfg;
struct tf_tcam_resources *tcam_cnt;
struct tf_rm_get_alloc_info_parms ainfo;
- struct tf_shadow_tcam_free_db_parms fshadow;
- struct tf_shadow_tcam_cfg_parms shadow_cfg;
- struct tf_shadow_tcam_create_db_parms shadow_cdb;
uint16_t num_slices = parms->wc_num_slices;
struct tf_session *tfs;
struct tf_dev_info *dev;
@@ -144,44 +130,6 @@ tf_tcam_bind(struct tf *tfp,
}
/* Initialize the TCAM manager. */
- if (parms->shadow_copy) {
- for (d = 0; d < TF_DIR_MAX; d++) {
- memset(&shadow_cfg, 0, sizeof(shadow_cfg));
- memset(&shadow_cdb, 0, sizeof(shadow_cdb));
- /* Get the base addresses of the tcams for tcam mgr */
- for (i = 0; i < TF_TCAM_TBL_TYPE_MAX; i++) {
- memset(&info, 0, sizeof(info));
-
- if (!parms->resources->tcam_cnt[d].cnt[i])
- continue;
- ainfo.rm_db = tcam_db->tcam_db[d];
- ainfo.subtype = i;
- ainfo.info = &info;
- rc = tf_rm_get_info(&ainfo);
- if (rc)
- goto error;
-
- shadow_cfg.base_addr[i] = info.entry.start;
- }
-
- /* Create the shadow db */
- shadow_cfg.alloc_cnt =
- parms->resources->tcam_cnt[d].cnt;
- shadow_cfg.num_entries = parms->num_elements;
-
- shadow_cdb.shadow_db = &shadow_tcam_db[d];
- shadow_cdb.cfg = &shadow_cfg;
- rc = tf_shadow_tcam_create_db(&shadow_cdb);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "TCAM MGR DB creation failed "
- "rc=%d\n", rc);
- goto error;
- }
- }
- shadow_init = 1;
- }
-
TFP_DRV_LOG(INFO,
"TCAM - initialized\n");
@@ -193,19 +141,10 @@ tf_tcam_bind(struct tf *tfp,
fparms.rm_db = tcam_db->tcam_db[i];
/* Ignoring return here since we are in the error case */
(void)tf_rm_free_db(tfp, &fparms);
-
- if (parms->shadow_copy) {
- fshadow.shadow_db = shadow_tcam_db[i];
- tf_shadow_tcam_free_db(&fshadow);
- shadow_tcam_db[i] = NULL;
- }
-
tcam_db->tcam_db[i] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL);
}
- shadow_init = 0;
-
return rc;
}
@@ -217,7 +156,6 @@ tf_tcam_unbind(struct tf *tfp)
struct tf_rm_free_db_parms fparms;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
- struct tf_shadow_tcam_free_db_parms fshadow;
TF_CHECK_PARMS1(tfp);
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
@@ -237,18 +175,8 @@ tf_tcam_unbind(struct tf *tfp)
return rc;
tcam_db->tcam_db[i] = NULL;
-
- if (shadow_init) {
- memset(&fshadow, 0, sizeof(fshadow));
-
- fshadow.shadow_db = shadow_tcam_db[i];
- tf_shadow_tcam_free_db(&fshadow);
- shadow_tcam_db[i] = NULL;
- }
}
- shadow_init = 0;
-
return 0;
}
@@ -346,7 +274,6 @@ tf_tcam_free(struct tf *tfp,
struct tf_rm_get_hcapi_parms hparms;
uint16_t num_slices = 1;
int allocated = 0;
- struct tf_shadow_tcam_remove_parms shparms;
int i;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
@@ -416,35 +343,6 @@ tf_tcam_free(struct tf *tfp,
return -EINVAL;
}
- /*
- * The Shadow mgmt, if enabled, determines if the entry needs
- * to be deleted.
- */
- if (shadow_init) {
- shparms.shadow_db = shadow_tcam_db[parms->dir];
- shparms.fparms = parms;
- rc = tf_shadow_tcam_remove(&shparms);
- if (rc) {
- /*
- * Should not get here, log it and let the entry be
- * deleted.
- */
- TFP_DRV_LOG(ERR, "%s: Shadow free fail, "
- "type:%d index:%d deleting the entry.\n",
- tf_dir_2_str(parms->dir),
- parms->type,
- parms->idx);
- } else {
- /*
- * If the entry still has references, just return the
- * ref count to the caller. No need to remove entry
- * from rm or hw
- */
- if (parms->ref_cnt >= 1)
- return rc;
- }
- }
-
for (i = 0; i < num_slices; i++) {
/* Free requested element */
memset(&fparms, 0, sizeof(fparms));
@@ -488,128 +386,6 @@ tf_tcam_free(struct tf *tfp,
return 0;
}
-int
-tf_tcam_alloc_search(struct tf *tfp,
- struct tf_tcam_alloc_search_parms *parms)
-{
- struct tf_shadow_tcam_search_parms sparms;
- struct tf_shadow_tcam_bind_index_parms bparms;
- struct tf_tcam_free_parms fparms;
- struct tf_tcam_alloc_parms aparms;
- uint16_t num_slice_per_row = 1;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int rc;
-
- TF_CHECK_PARMS2(tfp, parms);
-
- if (!shadow_init || !shadow_tcam_db[parms->dir]) {
- TFP_DRV_LOG(ERR, "%s: TCAM Shadow not initialized for %s\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type));
- return -EINVAL;
- }
-
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- /* Need to retrieve row size etc */
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- parms->type,
- parms->key_size,
- &num_slice_per_row);
- if (rc)
- return rc;
-
- /*
- * Prep the shadow search, reusing the parms from original search
- * instead of copying them. Shadow will update output in there.
- */
- memset(&sparms, 0, sizeof(sparms));
- sparms.sparms = parms;
- sparms.shadow_db = shadow_tcam_db[parms->dir];
-
- rc = tf_shadow_tcam_search(&sparms);
- if (rc)
- return rc;
-
- /*
- * The app didn't request us to alloc the entry, so return now.
- * The hit should have been updated in the original search parm.
- */
- if (!parms->alloc || parms->search_status != MISS)
- return rc;
-
- /* Caller desires an allocate on miss */
- if (dev->ops->tf_dev_alloc_tcam == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
- memset(&aparms, 0, sizeof(aparms));
- aparms.dir = parms->dir;
- aparms.type = parms->type;
- aparms.key_size = parms->key_size;
- aparms.priority = parms->priority;
- rc = dev->ops->tf_dev_alloc_tcam(tfp, &aparms);
- if (rc)
- return rc;
-
- /* Successful allocation, attempt to add it to the shadow */
- memset(&bparms, 0, sizeof(bparms));
- bparms.dir = parms->dir;
- bparms.shadow_db = shadow_tcam_db[parms->dir];
- bparms.type = parms->type;
- bparms.key = parms->key;
- bparms.mask = parms->mask;
- bparms.key_size = parms->key_size;
- bparms.idx = aparms.idx;
- bparms.hb_handle = sparms.hb_handle;
- rc = tf_shadow_tcam_bind_index(&bparms);
- if (rc) {
- /* Error binding entry, need to free the allocated idx */
- if (dev->ops->tf_dev_free_tcam == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "%s: Operation not supported, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(-rc));
- return rc;
- }
-
- fparms.dir = parms->dir;
- fparms.type = parms->type;
- fparms.idx = aparms.idx;
- rc = dev->ops->tf_dev_free_tcam(tfp, &fparms);
- if (rc)
- return rc;
- }
-
- /* Add the allocated index to output and done */
- parms->idx = aparms.idx;
-
- return 0;
-}
-
int
tf_tcam_set(struct tf *tfp __rte_unused,
struct tf_tcam_set_parms *parms __rte_unused)
@@ -619,7 +395,6 @@ tf_tcam_set(struct tf *tfp __rte_unused,
struct tf_dev_info *dev;
struct tf_rm_is_allocated_parms aparms;
struct tf_rm_get_hcapi_parms hparms;
- struct tf_shadow_tcam_insert_parms iparms;
uint16_t num_slice_per_row = 1;
int allocated = 0;
struct tcam_rm_db *tcam_db;
@@ -705,24 +480,6 @@ tf_tcam_set(struct tf *tfp __rte_unused,
strerror(-rc));
return rc;
}
-
- /* Successfully added to hw, now for shadow if enabled. */
- if (!shadow_init || !shadow_tcam_db[parms->dir])
- return 0;
-
- iparms.shadow_db = shadow_tcam_db[parms->dir];
- iparms.sparms = parms;
- rc = tf_shadow_tcam_insert(&iparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: %s: Entry %d set failed, rc:%s",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- parms->idx,
- strerror(-rc));
- return rc;
- }
-
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index b1e7a92b0b..0ed2250464 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -27,14 +27,6 @@ struct tf_tcam_cfg_parms {
* TCAM configuration array
*/
struct tf_rm_element_cfg *cfg;
- /**
- * Shadow table type configuration array
- */
- struct tf_shadow_tcam_cfg *shadow_cfg;
- /**
- * Boolean controlling the request shadow copy.
- */
- bool shadow_copy;
/**
* Session resource allocations
*/
@@ -91,11 +83,6 @@ struct tf_tcam_free_parms {
* [in] Index to free
*/
uint16_t idx;
- /**
- * [out] Reference count after free, only valid if session has been
- * created with shadow_copy.
- */
- uint16_t ref_cnt;
};
/**
@@ -322,10 +309,8 @@ int tf_tcam_alloc(struct tf *tfp,
struct tf_tcam_alloc_parms *parms);
/**
- * Free's the requested table type and returns it to the DB. If shadow
- * DB is enabled its searched first and if found the element refcount
- * is decremented. If refcount goes to 0 then its returned to the
- * table type DB.
+ * Free's the requested table type and returns it to the DB.
+ * If refcount goes to 0 then its returned to the table type DB.
*
* [in] tfp
* Pointer to TF handle, used for HCAPI communication
@@ -340,25 +325,6 @@ int tf_tcam_alloc(struct tf *tfp,
int tf_tcam_free(struct tf *tfp,
struct tf_tcam_free_parms *parms);
-/**
- * Supported if Shadow DB is configured. Searches the Shadow DB for
- * any matching element. If found the refcount in the shadow DB is
- * updated accordingly. If not found a new element is allocated and
- * installed into the shadow DB.
- *
- * [in] tfp
- * Pointer to TF handle, used for HCAPI communication
- *
- * [in] parms
- * Pointer to parameters
- *
- * Returns
- * - (0) if successful.
- * - (-EINVAL) on failure.
- */
-int tf_tcam_alloc_search(struct tf *tfp,
- struct tf_tcam_alloc_search_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index c1b9be0755..7d9de7c764 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -59,12 +59,10 @@ tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type)
return "sp_tcam";
case TF_TCAM_TBL_TYPE_CT_RULE_TCAM:
return "ct_rule_tcam";
-#ifdef TF_TCAM_SHARED
case TF_TCAM_TBL_TYPE_WC_TCAM_HIGH:
return "wc_tcam_hi";
case TF_TCAM_TBL_TYPE_WC_TCAM_LOW:
return "wc_tcam_lo";
-#endif
default:
return "Invalid tcam table type";
}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 1ee21fceef..1bb38399e4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -461,7 +461,6 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
return rc;
}
- parms.shadow_copy = true;
parms.bp = bp;
if (app_id == 0)
parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
@@ -550,8 +549,6 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
}
- params.shadow_copy = true;
-
rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n");
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 02/11] net/bnxt: update bnxt hsi structure
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 01/11] net/bnxt: remove deprecated features Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
` (8 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Randy Schacher, Kishore Padmanabha
[-- Attachment #1: Type: text/plain, Size: 271515 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Sync hsi structure to latest revision.
New version is 1.10.2.138
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 +++++++++++++++++++++---
1 file changed, 5128 insertions(+), 595 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 380dec4d3e..9afdd056ce 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2022 Broadcom Inc.
+ * Copyright (c) 2014-2023 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -442,6 +442,8 @@ struct cmd_nums {
#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
#define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
#define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
+ #define HWRM_PORT_CFG UINT32_C(0xdc)
+ #define HWRM_PORT_QCFG UINT32_C(0xdd)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
@@ -480,9 +482,7 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
/* Experimental */
#define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
- /* Experimental */
#define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
- /* Experimental */
#define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
/* Experimental */
#define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
@@ -678,6 +678,17 @@ struct cmd_nums {
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
/* The is the new API to query backing store capabilities. */
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
+ /* To query doorbell pacing NQ id list configuration. */
+ #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)
+ /*
+ * To notify the firmware that recovery cycle has been
+ * completed by host function drivers.
+ */
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)
+ /* Configures SyncE configurations. */
+ #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)
+ /* Queries SyncE configurations. */
+ #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
@@ -747,6 +758,8 @@ struct cmd_nums {
* to run.
*/
#define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
+ /* Queries the generic stats */
+ #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)
/* Experimental */
#define HWRM_TF UINT32_C(0x2bc)
/* Experimental */
@@ -774,6 +787,10 @@ struct cmd_nums {
/* Experimental */
#define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
/* Experimental */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)
+ /* Experimental */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)
+ /* Experimental */
#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
/* Experimental */
#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
@@ -819,6 +836,54 @@ struct cmd_nums {
#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
/* Experimental */
#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
+ /* TruFlow command to check firmware table scope capabilities. */
+ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)
+ /* TruFlow command to allocate a table scope ID and create the pools. */
+ #define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)
+ /* TruFlow command to configure the table scope memory. */
+ #define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)
+ /* TruFlow command to deconfigure a table scope memory. */
+ #define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)
+ /* TruFlow command to add a FID to a table scope. */
+ #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)
+ /* TruFlow command to remove a FID from a table scope. */
+ #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)
+ /* TruFlow command to allocate a table scope pool. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)
+ /* TruFlow command to free a table scope pool. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)
+ /* Experimental */
+ #define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)
+ /* Experimental */
+ #define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)
+ /* Experimental */
+ #define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)
+ /* TruFlow command to allocate an index table entry */
+ #define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)
+ /* TruFlow command to allocate and set an index table entry */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)
+ /* TruFlow command to set an index table entry */
+ #define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)
+ /* TruFlow command to get an index table entry */
+ #define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)
+ /* TruFlow command to free an index table entry */
+ #define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)
+ /* TruFlow command to allocate resources for a global id. */
+ #define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)
+ /* TruFlow command to set TCAM entry. */
+ #define HWRM_TFC_TCAM_SET UINT32_C(0x393)
+ /* TruFlow command to get TCAM entry. */
+ #define HWRM_TFC_TCAM_GET UINT32_C(0x394)
+ /* TruFlow command to allocate a TCAM entry. */
+ #define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)
+ /* TruFlow command allocate and set TCAM entry. */
+ #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)
+ /* TruFlow command to free a TCAM entry. */
+ #define HWRM_TFC_TCAM_FREE UINT32_C(0x397)
/* Experimental */
#define HWRM_SV UINT32_C(0x400)
/* Experimental */
@@ -1089,8 +1154,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 2
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 83
-#define HWRM_VERSION_STR "1.10.2.83"
+#define HWRM_VERSION_RSVD 138
+#define HWRM_VERSION_STR "1.10.2.138"
/****************
* hwrm_ver_get *
@@ -1345,6 +1410,7 @@ struct hwrm_ver_get_output {
* If set to 1, firmware is capable to support flow aging.
* If set to 0, firmware is not capable to support flow aging.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
@@ -1353,6 +1419,7 @@ struct hwrm_ver_get_output {
* Meter drop counters and EEM counters.
* If set to 0, firmware is not capable to support advanced flow counters.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
UINT32_C(0x400)
@@ -1362,6 +1429,7 @@ struct hwrm_ver_get_output {
* If set to 0, firmware is not capable to support the use of the
* CFA EEM feature.
* By default, this flag should be 0 for older version of core firmware.
+ * (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
UINT32_C(0x800)
@@ -1996,7 +2064,7 @@ struct cfa_bds_event_collect_cmd_data_msg {
uint64_t host_address;
} __rte_packed;
-/* ce_bds_add_data_msg (size:512b/64B) */
+/* ce_bds_add_data_msg (size:576b/72B) */
struct ce_bds_add_data_msg {
uint32_t version_algorithm_kid_opcode;
/*
@@ -2050,26 +2118,14 @@ struct ce_bds_add_data_msg {
(UINT32_C(0x1) << 28)
#define CE_BDS_ADD_DATA_MSG__LAST \
CE_BDS_ADD_DATA_MSG__TLS1_3
- uint8_t cmd_type_ctx_kind;
- /*
- * Command Type in the TLS header. HW will provide registers that
- * converts the 3b encoded command type to 8b of actual command
- * type in the TLS Header. This field is initialized/updated by
- * this "KTLS crypto add" mid-path command.
- */
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
- /* Application */
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
- #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
- CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
+ uint8_t ctx_kind;
/* This field selects the context kind for the request. */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8)
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0
/* Crypto key transmit context */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)
/* Crypto key receive context */
- #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3)
+ #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \
CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX
uint8_t unused0[3];
@@ -2083,8 +2139,8 @@ struct ce_bds_add_data_msg {
* is zero padded to 12B and then xor'ed with the 4B of salt to generate
* the 12B of IV. This value is initialized by this mid-path command.
*/
- uint32_t salt;
- uint32_t unused1;
+ uint8_t salt[4];
+ uint8_t unused1[4];
/*
* This field keeps track of the TCP sequence number that is expected as
* the first byte in the next TCP packet. This field is calculated by HW
@@ -2111,16 +2167,21 @@ struct ce_bds_add_data_msg {
* the field after that for every record processed as it parses the TCP
* packet.
*/
- uint32_t record_seq_num[2];
+ uint64_t record_seq_num;
/*
* Key used for encrypting or decrypting TLS records. The Key is
* exchanged during the hand-shake protocol by the client-server and
* provided to HW through this mid-path BD.
*/
- uint32_t session_key[8];
+ uint8_t session_key[32];
+ /*
+ * Additional IV that is exchanged as part of sessions setup between
+ * the two end points. This field is used for TLS1.3 only.
+ */
+ uint8_t addl_iv[8];
} __rte_packed;
-/* ce_bds_delete_data_msg (size:64b/8B) */
+/* ce_bds_delete_data_msg (size:32b/4B) */
struct ce_bds_delete_data_msg {
uint32_t kid_opcode_ctx_kind;
/*
@@ -2160,7 +2221,6 @@ struct ce_bds_delete_data_msg {
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \
CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX
- uint32_t unused0;
} __rte_packed;
/* ce_bds_resync_resp_ack_msg (size:128b/16B) */
@@ -2213,7 +2273,7 @@ struct ce_bds_resync_resp_ack_msg {
* it has found since sending the resync request, update the context and
* resume decrypting records.
*/
- uint32_t resync_record_seq_num[2];
+ uint64_t resync_record_seq_num;
} __rte_packed;
/* ce_bds_resync_resp_nack_msg (size:64b/8B) */
@@ -2288,6 +2348,19 @@ struct crypto_presync_bd_cmd {
*/
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
UINT32_C(0x1)
+ /*
+ * When packet with an authentication TAG is lost in the network,
+ * During retransmission Device driver will post the entire record for
+ * the hardware to recalculate the TAG. Hardware is set to retransmit
+ * only portions of the record, it does so by looking at the Header
+ * TCP Sequence Number and Start TCP Sequence Number. However, there
+ * is a case where the header packet gets dropped in the stack for ex
+ * BPF packet filter and it is impossible for the Hardware to
+ * determine if this is a case of full replay for only the TAG
+ * generation.
+ */
+ #define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN \
+ UINT32_C(0x2)
uint8_t unused0;
uint16_t unused1;
/*
@@ -2331,7 +2404,7 @@ struct crypto_presync_bd_cmd {
* the first TLS header. When subsequent TLS Headers are detected, the
* value is extracted from packet.
*/
- uint32_t explicit_nonce[2];
+ uint8_t explicit_nonce[8];
/*
* This is sequence number for the TLS record in a particular session. In
* TLS1.2, record sequence number is part of the Associated Data (AD) in
@@ -2343,7 +2416,110 @@ struct crypto_presync_bd_cmd {
* delivering more retransmission instruction will also update this
* field.
*/
- uint32_t record_seq_num[2];
+ uint64_t record_seq_num;
+} __rte_packed;
+
+/* ce_bds_quic_add_data_msg (size:832b/104B) */
+struct ce_bds_quic_add_data_msg {
+ uint32_t ver_algo_kid_opcode;
+ /*
+ * This value selects the operation for the mid-path command for the
+ * crypto blocks.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0
+ /*
+ * This is the add command. Using this opcode, Host Driver can add
+ * information required for QUIC processing. The information is
+ * updated in the CFCK context.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD
+ /*
+ * This field is the Crypto Context ID. The KID is used to store
+ * information used by the associated QUIC offloaded connection.
+ */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK \
+ UINT32_C(0xfffff0)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4
+ /* Algorithm used for encryption and decryption. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK \
+ UINT32_C(0xf000000)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24
+ /* AES_GCM_128 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
+ (UINT32_C(0x1) << 24)
+ /* AES_GCM_256 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
+ (UINT32_C(0x2) << 24)
+ /* Chacha20 Algorithm. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 \
+ (UINT32_C(0x3) << 24)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20
+ /* Version number of QUIC connection. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK \
+ UINT32_C(0xf0000000)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28
+ /* TLS1.2 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 \
+ (UINT32_C(0x0) << 28)
+ /* TLS1.3 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 \
+ (UINT32_C(0x1) << 28)
+ /* DTLS1.2 Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 \
+ (UINT32_C(0x2) << 28)
+ /* DTLS1.2 for RoCE Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE \
+ (UINT32_C(0x3) << 28)
+ /* QUIC Version */
+ #define CE_BDS_QUIC_ADD_DATA_MSG__QUIC \
+ (UINT32_C(0x4) << 28)
+ #define CE_BDS_QUIC_ADD_DATA_MSG__LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG__QUIC
+ uint32_t ctx_kind_dcid_width_key_phase;
+ /* Key phase. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)
+ /* Destination connection ID width. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1
+ /* This field selects the context kind for the request. */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6
+ /* QUIC key transmit context */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX \
+ (UINT32_C(0x14) << 6)
+ /* QUIC key receive context */
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX \
+ (UINT32_C(0x15) << 6)
+ #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST \
+ CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX
+ uint32_t unused_0[2];
+ /*
+ * Least-significant 64 bits (of 96) of additional IV that is
+ * exchanged as part of sessions setup between the two end
+ * points for QUIC operations.
+ */
+ uint64_t quic_iv_lo;
+ /*
+ * Most-significant 32 bits (of 96) of additional IV that is
+ * exchanged as part of sessions setup between the two end
+ * points for QUIC operations.
+ */
+ uint32_t quic_iv_hi;
+ uint32_t unused_1;
+ /*
+ * Key used for encrypting or decrypting records. The Key is exchanged
+ * as part of sessions setup between the two end points through this
+ * mid-path BD.
+ */
+ uint32_t session_key[8];
+ /* Header protection key. */
+ uint32_t hp_key[8];
+ /* Packet number associated with the QUIC connection. */
+ uint64_t pkt_number;
} __rte_packed;
/* bd_base (size:64b/8B) */
@@ -3665,7 +3841,7 @@ struct cfa_dma128b_data_msg {
/* ce_cmpls_cmp_data_msg (size:128b/16B) */
struct ce_cmpls_cmp_data_msg {
- uint16_t status_subtype_type;
+ uint16_t client_subtype_type;
/*
* This field indicates the exact type of the completion. By
* convention, the LSB identifies the length of the record in 16B
@@ -3678,82 +3854,82 @@ struct ce_cmpls_cmp_data_msg {
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6
/*
* This value indicates the CE sub-type operation that is being
* completed.
*/
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8
/* Completion Response for a Solicited Command. */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)
/* Error Completion (Unsolicited). */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)
/* Re-Sync Completion (Unsolicited) */
- #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
+ #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
+ /*
+ * This field represents the Mid-Path client that generated the
+ * completion.
+ */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12
+ /* TX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE \
+ (UINT32_C(0x0) << 12)
+ /* RX crypto engine block. */
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE \
+ (UINT32_C(0x1) << 12)
+ #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
+ CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE
+ uint16_t status;
/* This value indicates the status for the command. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0
/* Completed without error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
- (UINT32_C(0x0) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)
/* CFCK load error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
- (UINT32_C(0x1) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)
/* FID check error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
- (UINT32_C(0x2) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)
/* Context kind / MP version mismatch error. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \
- (UINT32_C(0x3) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)
/* Unsupported Destination Connection ID Length. */
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \
- (UINT32_C(0x4) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)
/*
* Invalid MP Command [anything other than ADD or DELETE
* triggers this for QUIC].
*/
- #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \
- (UINT32_C(0x5) << 10)
+ #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR
- uint8_t unused0;
- uint8_t mp_clients;
- #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
- #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
- /*
- * This field represents the Mid-Path client that generated the
- * completion.
- */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
- /* TX crypto engine block. */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
- /* RX crypto engine block. */
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
- #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
- CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4
/*
* This is a copy of the opaque field from the mid path BD of this
* command.
*/
uint32_t opaque;
- /* */
- uint32_t kid_v;
+ uint32_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes will
* write 1. The odd passes will write 0.
*/
- #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1
+ uint32_t kid;
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
- #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
- #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
- uint32_t unused2;
+ #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)
+ #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
+ #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20
} __rte_packed;
/* cmpl_base (size:128b/16B) */
@@ -3783,16 +3959,11 @@ struct cmpl_base {
* Completion of coalesced TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
- /*
- * TX L2 PTP completion:
- * Completion of PTP TX packet. Length = 32B
- */
- #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
/*
* TX L2 Packet Timestamp completion:
* Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
- #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4)
+ #define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
/*
* RX L2 TPA Start V2 Completion:
* Completion of and L2 RX packet. Length = 32B
@@ -4173,47 +4344,79 @@ struct tx_cmpl_coal {
#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
} __rte_packed;
-/* tx_cmpl_ptp (size:128b/16B) */
-struct tx_cmpl_ptp {
- uint16_t flags_type;
+/* tx_cmpl_packet_timestamp (size:128b/16B) */
+struct tx_cmpl_packet_timestamp {
+ uint16_t ts_sub_ns_flags_type;
/*
- * This field indicates the exact type of the completion.
- * By convention, the LSB identifies the length of the
- * record in 16B units. Even values indicate 16B
- * records. Odd values indicate 32B
- * records.
+ * This field indicates the exact type of the completion. By
+ * convention, the LSB identifies the length of the record in 16B
+ * units. Even values indicate 16B records. Odd values indicate
+ * 32B records.
*/
- #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
- #define TX_CMPL_PTP_TYPE_SFT 0
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0
/*
- * TX L2 PTP completion:
- * Completion of TX packet. Length = 32B
+ * TX L2 Packet Timestamp completion:
+ * Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
- #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
- #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
- #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
- #define TX_CMPL_PTP_FLAGS_SFT 6
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
+ #define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6
/*
- * When this bit is '1', it indicates a packet that has an
- * error of some type. Type of error is indicated in
- * error_flags.
+ * When this bit is '1', it indicates a packet that has an error
+ * of some type. Type of error is indicated in error_flags.
*/
- #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)
/*
- * When this bit is '1', it indicates that the packet completed
- * was transmitted using the push acceleration data provided
- * by the driver. When this bit is '0', it indicates that the
- * packet had not push acceleration data written or was executed
- * as a normal packet even though push data was provided.
+ * This field indicates the TX packet timestamp type that is
+ * represented by a TX Packet Timestamp Completion. Note that
+ * this field is invalid if the timestamp_invalid_error flag
+ * is set.
*/
- #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
- /* unused1 is 16 b */
- uint16_t unused_0;
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)
+ /* The packet timestamp came from PM. */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM \
+ (UINT32_C(0x0) << 7)
+ /* The packet timestamp came from PA. */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA \
+ (UINT32_C(0x1) << 7)
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA
+ /*
+ * This flag indicates that the timestamp should have come from PM,
+ * but came instead from PA because all PM timestamp resources were
+ * in use. This can occur in the following circumstances:
+ * 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet
+ * but PA could not request a PM timestamp
+ * 2. The BD specified ts_2cmpl_pm, but PA could not request a PM
+ * timestamp
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)
+ /*
+ * For 2-step PTP timestamps, bits[3:0] of this field represent the
+ * sub-nanosecond portion of the packet timestamp, returned from PM
+ * for 2-step PTP timestamps. For PA timestamps, this field also
+ * represents the sub-nanosecond portion of the packet timestamp;
+ * however, due to synchronization uncertainties, the accuracy of
+ * PA timestamps is limited to approximately +/- 4 ns. Therefore
+ * this field is of dubious value for PA timestamps.
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)
+ #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12
+ /*
+ * This is bits [47:32] of the nanoseconds portion of the packet
+ * timestamp, returned from PM for 2-step PTP timestamps or from
+ * PA for PA timestamps. This field is in units of 2^32 ns.
+ */
+ uint16_t ts_ns_mid;
/*
* This is a copy of the opaque field from the first TX BD of this
- * transmitted packet. Note that, if the packet was described by a short
- * CSO or short CSO inline BD, then the 16-bit opaque field from the
- * short CSO BD will appear in the bottom 16 bits of this field.
+ * transmitted packet. Note that, if the packet was described by a
+ * short CSO or short CSO inline BD, then the 16-bit opaque field
+ * from the short CSO BD will appear in the bottom 16 bits of this
+ * field.
*/
uint32_t opaque;
uint16_t errors_v;
@@ -4222,95 +4425,103 @@ struct tx_cmpl_ptp {
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define TX_CMPL_PTP_V UINT32_C(0x1)
- #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
- #define TX_CMPL_PTP_ERRORS_SFT 1
+ #define TX_CMPL_PACKET_TIMESTAMP_V \
+ UINT32_C(0x1)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1
/*
- * This error indicates that there was some sort of problem
- * with the BDs for the packet.
+ * This field was previously used to indicate fatal errors, which
+ * now result in aborting and bringing down the ring. This field
+ * is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
- /* No error */
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK \
+ UINT32_C(0xe)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1
+ /* No error. */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR \
(UINT32_C(0x0) << 1)
- /*
- * Bad Format:
- * BDs were not formatted correctly.
- */
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
+ /* Deprecated. */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT \
(UINT32_C(0x2) << 1)
- #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
- TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST \
+ TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT
/*
- * When this bit is '1', it indicates that the length of
- * the packet was zero. No packet was transmitted.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
- /*
- * When this bit is '1', it indicates that the packet
- * was longer than the programmed limit in TDI. No
- * packet was transmitted.
- */
- #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT \
+ UINT32_C(0x10)
/*
- * When this bit is '1', it indicates that one or more of the
- * BDs associated with this packet generated a PCI error.
- * This probably means the address was not valid.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH \
+ UINT32_C(0x20)
/*
- * When this bit is '1', it indicates that the packet was longer
- * than indicated by the hint. No packet was transmitted.
+ * When this bit is '1', it indicates that one or more of the BDs
+ * associated with this packet generated a PCI error when accessing
+ * header/payload data from host memory. It most likely indicates
+ * that the address was not valid. Note that this bit has no meaning
+ * for the timestamp completion and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR \
+ UINT32_C(0x40)
/*
- * When this bit is '1', it indicates that the packet was
- * dropped due to Poison TLP error on one or more of the
- * TLPs in the PXP completion.
+ * This error is fatal and results in aborting and bringing down the
+ * ring, thus is deprecated.
*/
- #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT \
+ UINT32_C(0x80)
/*
- * When this bit is '1', it indicates that the packet was dropped due
- * to a transient internal error in TDC. The packet or LSO can be
- * retried and may transmit successfully on a subsequent attempt.
+ * When this bit is '1', it indicates that the packet was dropped
+ * due to Poison TLP error on one or more of the TLPs in one or more
+ * of the associated PXP completion(s) when accessing header/payload
+ * data from host memory. Note that this bit has no meaning for the
+ * timestamp completion, and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR \
+ UINT32_C(0x100)
/*
- * When this bit is '1', it was not possible to collect a a timestamp
- * for a PTP completion, in which case the timestamp_hi and
- * timestamp_lo fields are invalid. When this bit is '0' for a PTP
- * completion, the timestamp_hi and timestamp_lo fields are valid.
- * RJRN will copy the value of this bit into the field of the same
- * name in all TX completions, regardless of whether such
- * completions are PTP completions or other TX completions.
+ * When this bit is '1', it indicates that the packet was dropped
+ * due to a transient internal error in TDC. The packet or LSO can
+ * be retried and may transmit successfully on a subsequent attempt.
+ * Note that this bit has no meaning for the timestamp completion
+ * and will always be '0'.
*/
- #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
- /* unused2 is 16 b */
- uint16_t unused_1;
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR \
+ UINT32_C(0x200)
/*
- * This is timestamp value (lower 32bits) read from PM for the PTP
- * timestamp enabled packet.
- */
- uint32_t timestamp_lo;
-} __rte_packed;
-
-/* tx_cmpl_ptp_hi (size:128b/16B) */
-struct tx_cmpl_ptp_hi {
+ * When this bit is '1', it was not possible to collect a timestamp
+ * for a timestamp completion, in which case the ts_ns and ts_sub_ns
+ * fields are invalid. When this bit is '0' in a timestamp
+ * completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields
+ * are valid. Note that this bit has meaning only for the timestamp
+ * completion. For types other than the timestamp completion, this
+ * bit will always be '0'.
+ */
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR \
+ UINT32_C(0x400)
/*
- * This is timestamp value (lower 32bits) read from PM for the PTP
- * timestamp enabled packet.
+ * When this bit is '1', it indicates that a Timed Transmit
+ * SO-TXTIME packet violated the max_ttx_overtime constraint i.e.,
+ * the time the packet was processed for transmission in TWE was
+ * later than the time given by (TimedTx_BD.tx_time +
+ * max_ttx_overtime) and as result, the packet was dropped.
+ * Note that max_ttx_overtime is a global configuration in TWE.
+ * Note that this bit has no meaning in a timestamp completion,
+ * and will always be '0'.
*/
- uint16_t timestamp_hi[3];
- uint16_t reserved16;
- uint64_t v2;
+ #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR \
+ UINT32_C(0x800)
+ /* unused2 is 16 b */
+ uint16_t unused_2;
/*
- * This value is written by the NIC such that it will be different for
- * each pass through the completion queue.
- * The even passes will write 1.
- * The odd passes will write 0.
+ * This is bits [31:0] of the nanoseconds portion of the packet
+ * timestamp, returned from PM for 2-step PTP timestamp or from
+ * PA for PA timestamps. This field is in units of ns.
*/
- #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
+ uint32_t ts_ns_lo;
} __rte_packed;
/* rx_pkt_cmpl (size:128b/16B) */
@@ -9314,9 +9525,31 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \
UINT32_C(0x46)
+ /*
+ * An event from firmware indicating that the RSS capabilities have
+ * changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE \
+ UINT32_C(0x47)
+ /*
+ * An event from firmware indicating that list of nq ids used for
+ * doorbell pacing DBQ event notification has been updated. The driver
+ * needs to take appropriate action and retrieve the new list when this
+ * event is received from the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \
+ UINT32_C(0x48)
+ /*
+ * An event from firmware indicating that hardware ran into an error
+ * while trying to read the host based doorbell copy region. The driver
+ * needs to take the appropriate action and maintain the corresponding
+ * doorbell copy region.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \
+ UINT32_C(0x49)
/* Maximum Registrable event id. */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
- UINT32_C(0x47)
+ UINT32_C(0x4a)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -11828,6 +12061,195 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold {
uint32_t event_data1;
} __rte_packed;
+/* hwrm_async_event_cmpl_rss_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_rss_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that the RSS capabilities have changed. The driver will need
+ * to query hwrm_vnic_qcaps.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE \
+ UINT32_C(0x47)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */
+struct hwrm_async_event_cmpl_doorbell_pacing_nq_update {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * An event from firmware indicating that list of nq ids used for
+ * doorbell pacing DBQ event notification has been updated. The driver
+ * needs to take appropriate action and retrieve the new list when this
+ * event is received from the firmware.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \
+ UINT32_C(0x48)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __rte_packed;
+
+/* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message is used to inform the driver
+ * that hardware ran into an error while trying to read the host
+ * based doorbell copy region. The driver will take the appropriate
+ * action to maintain the corresponding functions doorbell copy
+ * region in the correct format.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \
+ UINT32_C(0x49)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR
+ /* Event specific data. */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_SFT \
+ 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Indicates that there is an error while reading the doorbell copy
+ * regions.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK \
+ UINT32_C(0xf)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * SQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * RQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * SRQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, indicates that there is an error while reading the
+ * CQ doorbell copy region for this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \
+ UINT32_C(0x8)
+} __rte_packed;
+
/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
struct hwrm_async_event_cmpl_fw_trace_msg {
uint16_t type;
@@ -12385,6 +12807,14 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
UINT32_C(0x4)
#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
+ /*
+ * The epoch value to be sent from firmware to the driver to track
+ * a doorbell recovery cycle.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK \
+ UINT32_C(0xffffff00)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \
+ 8
} __rte_packed;
/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */
@@ -12516,8 +12946,8 @@ struct metadata_base_msg {
#define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
/*
* This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * the state of the receive context, the meta-data will carry
+ * different information.
*/
#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
/*
@@ -12525,12 +12955,21 @@ struct metadata_base_msg {
* record that it is requesting a resync on in the meta data.
*/
#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
+ /* This setting is used for QUIC packets. */
+ #define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3)
+ /*
+ * This setting is used for crypto packets with an unsupported
+ * protocol.
+ */
+ #define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f)
#define METADATA_BASE_MSG_MD_TYPE_LAST \
- METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
+ METADATA_BASE_MSG_MD_TYPE_ILLEGAL
/*
- * This field indicates where the next metadata block starts. It is
- * counted in 16B units. A value of zero indicates that there is no
- * metadata.
+ * This field indicates where the next metadata block starts, relative
+ * to the current metadata block. It is the offset to the next metadata
+ * header, counted in 16B units. A value of zero indicates that there is
+ * no additional metadata, and that the current metadata block is the
+ * last one.
*/
#define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
#define METADATA_BASE_MSG_LINK_SFT 5
@@ -12544,11 +12983,12 @@ struct tls_metadata_base_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT \
+ 0
/*
- * This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * This setting is used when packets are coming in-order. Depending
+ * on the state of the receive context, the meta-data will carry
+ * different information.
*/
#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
UINT32_C(0x1)
@@ -12567,11 +13007,13 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_BASE_MSG_LINK_SFT 5
+ #define TLS_METADATA_BASE_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_BASE_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_BASE_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12584,7 +13026,8 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12610,12 +13053,13 @@ struct tls_metadata_base_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
/*
* This enumeration states that there is at least one tag in the
@@ -12638,13 +13082,61 @@ struct tls_metadata_base_msg {
*/
#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_BASE_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_BASE_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -12661,11 +13153,12 @@ struct tls_metadata_insync_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT \
+ 0
/*
* This setting is used when packets are coming in-order. Depending on
- * the state of the receive context, the meta-data will carry different
- * information.
+ * the state of the receive context, the meta-data will carry
+ * different information.
*/
#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
UINT32_C(0x1)
@@ -12678,11 +13171,13 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
+ #define TLS_METADATA_INSYNC_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12695,7 +13190,8 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12721,12 +13217,13 @@ struct tls_metadata_insync_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
/*
* This enumeration states that there is at least one tag in the
@@ -12749,13 +13246,61 @@ struct tls_metadata_insync_msg {
*/
#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -12764,14 +13309,14 @@ struct tls_metadata_insync_msg {
#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
/*
- * This field is only valid when md_type is set to tls_insync. This field
- * indicates the offset within the current TCP packet where the TLS header
- * starts. If there are multiple TLS headers in the packet, this provides
- * the offset of the last TLS header.
+ * This field is only valid when md_type is set to tls_insync. This
+ * field indicates the offset within the current TCP packet where the
+ * TLS header starts. If there are multiple TLS headers in the packet,
+ * this provides the offset of the last TLS header.
*
- * The field is calculated by subtracting TCP sequence number of the first
- * byte of the TCP payload of the packet from the TCP sequence number of
- * the last TLS header in the packet.
+ * The field is calculated by subtracting TCP sequence number of the
+ * first byte of the TCP payload of the packet from the TCP sequence
+ * number of the last TLS header in the packet.
*/
uint16_t tls_header_offset;
/*
@@ -12787,7 +13332,7 @@ struct tls_metadata_insync_msg {
* not decrypt every packet and authenticate the record. Partial GHASH is
* only sent out with packet having the TAG field.
*/
- uint64_t partial_ghash;
+ uint8_t partial_ghash[8];
} __rte_packed;
/* tls_metadata_resync_msg (size:256b/32B) */
@@ -12796,7 +13341,8 @@ struct tls_metadata_resync_msg {
/* This field classifies the data present in the meta-data. */
#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
UINT32_C(0x1f)
- #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
+ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT \
+ 0
/*
* With this setting HW passes the TCP sequence number of the TLS
* record that it is requesting a resync on in the meta data.
@@ -12812,11 +13358,13 @@ struct tls_metadata_resync_msg {
*/
#define TLS_METADATA_RESYNC_MSG_LINK_MASK \
UINT32_C(0x1e0)
- #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
+ #define TLS_METADATA_RESYNC_MSG_LINK_SFT \
+ 5
/* These are flags present in the metadata. */
#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
UINT32_C(0x1fffe00)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT \
+ 9
/*
* A value of 1 implies that the packet was decrypted by HW. Otherwise
* the packet is passed on as it came in on the wire.
@@ -12829,7 +13377,8 @@ struct tls_metadata_resync_msg {
*/
#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
UINT32_C(0xc00)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT \
+ 10
/*
* This enumeration states that the ghash is not valid in the
* meta-data.
@@ -12841,28 +13390,77 @@ struct tls_metadata_resync_msg {
/* This field indicates the status of tag authentication. */
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
UINT32_C(0x3000)
- #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \
+ 12
/*
- * This enumeration is set when there is no tags present in the
- * packet.
+ * This enumeration is set when HW was not able to authenticate a
+ * TAG.
*/
- #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \
(UINT32_C(0x0) << 12)
#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
- TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
+ TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED
/*
* A value of 1 indicates that this packet contains a record that
* starts in the packet and extends beyond the packet.
*/
#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
UINT32_C(0x4000)
+ /*
+ * A value of 1 indicates that the packet experienced a context load
+ * error. In this case, the packet is sent to the host without the
+ * header or payload decrypted and the context is not updated.
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR \
+ UINT32_C(0x8000)
+ /* This field indicates the packet operation state. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \
+ UINT32_C(0x70000)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \
+ 16
+ /* Packet is in order. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \
+ (UINT32_C(0x0) << 16)
+ /* Packet is out of order, no header loss. */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \
+ (UINT32_C(0x1) << 16)
+ /* Packet is header search (out of order with header loss). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \
+ (UINT32_C(0x2) << 16)
+ /* Packet is resync (resync record ongoing). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \
+ (UINT32_C(0x3) << 16)
+ /*
+ * Packet is resync wait (resync record completes, waiting for
+ * result).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \
+ (UINT32_C(0x4) << 16)
+ /*
+ * Packet is resync wait for partial tag (waiting for resync record
+ * tag).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \
+ (UINT32_C(0x5) << 16)
+ /* Packet is resync success (got resync record success). */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \
+ (UINT32_C(0x6) << 16)
+ /*
+ * Packet is resync success wait (got midpath ACK, waiting for
+ * resync record success).
+ */
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \
+ (UINT32_C(0x7) << 16)
+ #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \
+ TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT
/*
* This value indicates the lower 7-bit of the Crypto Key ID
* associated with this operation.
*/
#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
UINT32_C(0xfe000000)
- #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
+ #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT \
+ 25
uint16_t kid_hi;
/*
* This value indicates the upper 13-bit of the Crypto Key ID
@@ -13221,7 +13819,7 @@ struct hwrm_func_vf_free_output {
********************/
-/* hwrm_func_vf_cfg_input (size:448b/56B) */
+/* hwrm_func_vf_cfg_input (size:512b/64B) */
struct hwrm_func_vf_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13384,7 +13982,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of TX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
@@ -13393,7 +13991,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
@@ -13402,7 +14000,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of CMPL rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
@@ -13411,7 +14009,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RSS ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
@@ -13420,7 +14018,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of ring groups) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
@@ -13429,7 +14027,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of stat ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
@@ -13438,7 +14036,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of VNICs) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
@@ -13447,7 +14045,7 @@ struct hwrm_func_vf_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of L2 ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
@@ -13486,9 +14084,10 @@ struct hwrm_func_vf_cfg_input {
/* The number of HW ring groups requested for the VF. */
uint16_t num_hw_ring_grps;
/* Number of Tx Key Contexts requested. */
- uint16_t num_tx_key_ctxs;
+ uint32_t num_tx_key_ctxs;
/* Number of Rx Key Contexts requested. */
- uint16_t num_rx_key_ctxs;
+ uint32_t num_rx_key_ctxs;
+ uint8_t unused[4];
} __rte_packed;
/* hwrm_func_vf_cfg_output (size:128b/16B) */
@@ -13558,7 +14157,7 @@ struct hwrm_func_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcaps_output (size:768b/96B) */
+/* hwrm_func_qcaps_output (size:896b/112B) */
struct hwrm_func_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -14176,6 +14775,74 @@ struct hwrm_func_qcaps_output {
/* When this bit is '1', it indicates that HW and FW support QUIC. */
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \
UINT32_C(0x2)
+ /*
+ * When this bit is '1', it indicates that KDNet mode is
+ * supported on the port for this function. This bit is
+ * never set for a VF.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When this bit is '1', it indicates the FW is capable of
+ * supporting Enhanced Doorbell Pacing.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED \
+ UINT32_C(0x8)
+ /*
+ * When this bit is '1', it indicates that FW is capable of
+ * supporting software based doorbell drop recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED \
+ UINT32_C(0x10)
+ /*
+ * When this bit is '1', it indicates the FW supports collection
+ * and query of the generic statistics.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', it indicates that the HW is capable of
+ * supporting UDP GSO on the function.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', it indicates that SyncE feature is
+ * supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', it indicates the FW is capable of
+ * supporting doorbell pacing version 0. As doorbell pacing
+ * notification from hardware for Thor2 is completely different
+ * from Thor1, this flag is used to differentiate the doorbell
+ * pacing notification between Thor1 and Thor2. Thor1 uses
+ * dbr_pacing_supported and dbr_pacing_ext_supported flags for
+ * doorbell pacing whereas Thor2 uses dbr_pacing_v0_supported flag.
+ * These flags will never be set at the same time for Thor2.
+ * Based on this flag, host drivers assume doorbell pacing is needed
+ * for Thor2.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', it indicates that the HW supports
+ * two-completion TX packet timestamp feature, a second completion
+ * carrying packet TX timestamp in addition to the standard
+ * completion returned for packets. Host driver should not use
+ * HWRM port timestamp query (HWRM_PORT_TS_QUERY) command for
+ * TX timestamp read when two-completion timestamp feature is
+ * supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', it indicates that the hardware based
+ * link aggregation group (L2 and RoCE) feature is supported.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \
+ UINT32_C(0x400)
uint16_t tunnel_disable_flag;
/*
* When this bit is '1', it indicates that the VXLAN parsing
@@ -14225,7 +14892,16 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \
UINT32_C(0x80)
- uint8_t unused_1;
+ uint8_t unused_1[2];
+ /*
+ * This value uniquely identifies the hardware NIC used by the
+ * function. The value returned will be the same for all functions.
+ * A value of 00-00-00-00-00-00-00-00 indicates no device serial number
+ * is currently configured. This is the same value that is returned by
+ * PCIe Capability Device Serial Number.
+ */
+ uint8_t device_serial_number[8];
+ uint8_t unused_2[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -14283,7 +14959,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_qcfg_output (size:896b/112B) */
+/* hwrm_func_qcfg_output (size:1024b/128B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -14787,7 +15463,36 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
UINT32_C(0x10)
- uint8_t unused_2[3];
+ /*
+ * Configured doorbell page size for this function.
+ * This field is valid for PF only.
+ */
+ uint8_t db_page_size;
+ /* DB page size is 4KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
+ /* DB page size is 8KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
+ /* DB page size is 16KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
+ /* DB page size is 32KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
+ /* DB page size is 64KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
+ /* DB page size is 128KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
+ /* DB page size is 256KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
+ /* DB page size is 512KB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
+ /* DB page size is 1MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
+ /* DB page size is 2MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
+ /* DB page size is 4MB. */
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
+ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB
+ uint8_t unused_2[2];
/*
* Minimum guaranteed bandwidth for the network partition made up
* of the caller physical function and all its child virtual
@@ -14874,11 +15579,36 @@ struct hwrm_func_qcfg_output {
* value is used if ring MTU is not specified.
*/
uint16_t host_mtu;
+ uint8_t unused_3[2];
+ uint8_t unused_4[2];
+ /*
+ * KDNet mode for the port for this function. If a VF, KDNet
+ * mode is always disabled.
+ */
+ uint8_t port_kdnet_mode;
+ /* KDNet mode is not enabled on the port for this function. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
+ /* KDNet mode is enabled on the port for this function. */
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_LAST \
+ HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED
+ /*
+ * If KDNet mode is enabled, the PCI function number of the
+ * KDNet partition.
+ */
+ uint8_t kdnet_pcie_function;
+ /*
+ * Function ID of the KDNET function on this port. If the
+ * KDNET partition does not exist and the FW supports this
+ * feature, 0xffff will be returned.
+ */
+ uint16_t port_kdnet_fid;
+ uint8_t unused_5[2];
/* Number of Tx Key Contexts allocated. */
- uint16_t alloc_tx_key_ctxs;
+ uint32_t alloc_tx_key_ctxs;
/* Number of Rx Key Contexts allocated. */
- uint16_t alloc_rx_key_ctxs;
- uint8_t unused_3[5];
+ uint32_t alloc_rx_key_ctxs;
+ uint8_t unused_6[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -14894,7 +15624,7 @@ struct hwrm_func_qcfg_output {
*****************/
-/* hwrm_func_cfg_input (size:896b/112B) */
+/* hwrm_func_cfg_input (size:1024b/128B) */
struct hwrm_func_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -15002,7 +15732,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of TX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
@@ -15011,7 +15741,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RX rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
@@ -15020,7 +15750,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of CMPL rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
@@ -15029,7 +15759,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of RSS ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
@@ -15038,7 +15768,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of ring groups) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
@@ -15047,7 +15777,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of stat ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
@@ -15056,7 +15786,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of VNICs) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
@@ -15065,7 +15795,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of L2 ctx) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
@@ -15091,7 +15821,7 @@ struct hwrm_func_cfg_input {
* This bit requests that the firmware test to see if all the assets
* requested in this command (i.e. number of NQ rings) are available.
* The firmware will return an error if the requested assets are
- * not available. The firwmare will NOT reserve the assets if they
+ * not available. The firmware will NOT reserve the assets if they
* are available.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
@@ -15158,6 +15888,15 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
UINT32_C(0x40000000)
+ /*
+ * If this bit is set to 1, the driver is requesting FW to see if
+ * all the assets requested in this command (i.e. number of KTLS/
+ * QUIC key contexts) are available. The firmware will return an
+ * error if the requested assets are not available. The firmware
+ * will NOT reserve the assets if they are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \
+ UINT32_C(0x80000000)
uint32_t enables;
/*
* This bit must be '1' for the admin_mtu field to be
@@ -15803,11 +16542,71 @@ struct hwrm_func_cfg_input {
* ring that is assigned to a function has a valid mtu.
*/
uint16_t host_mtu;
+ uint8_t unused_0[4];
+ uint32_t enables2;
+ /*
+ * This bit must be '1' for the kdnet_mode field to be
+ * configured.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the db_page_size field to be
+ * configured. Legacy controller core FW may silently ignore
+ * the db_page_size programming request through this command.
+ */
+ #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)
+ /*
+ * KDNet mode for the port for this function. If NPAR is
+ * also configured on this port, it takes precedence. KDNet
+ * mode is ignored for a VF.
+ */
+ uint8_t port_kdnet_mode;
+ /* KDNet mode is not enabled. */
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
+ /* KDNet mode enabled. */
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
+ #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_LAST \
+ HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED
+ /*
+ * This field can be used by the PF driver to configure the doorbell
+ * page size. L2 driver can use different pages to ring the doorbell
+ * for L2 push operation. The doorbell page size should be configured
+ * to match the native CPU page size for proper RoCE and L2 doorbell
+ * operations. This value supersedes the older method of configuring
+ * the doorbell page size by the RoCE driver using the command queue
+ * method. The default is 4K.
+ */
+ uint8_t db_page_size;
+ /* DB page size is 4KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
+ /* DB page size is 8KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
+ /* DB page size is 16KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
+ /* DB page size is 32KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
+ /* DB page size is 64KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
+ /* DB page size is 128KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
+ /* DB page size is 256KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
+ /* DB page size is 512KB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
+ /* DB page size is 1MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
+ /* DB page size is 2MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
+ /* DB page size is 4MB. */
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
+ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \
+ HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB
+ uint8_t unused_1[2];
/* Number of Tx Key Contexts requested. */
- uint16_t num_tx_key_ctxs;
+ uint32_t num_tx_key_ctxs;
/* Number of Rx Key Contexts requested. */
- uint16_t num_rx_key_ctxs;
- uint8_t unused_0[4];
+ uint32_t num_rx_key_ctxs;
+ uint8_t unused_2[4];
} __rte_packed;
/* hwrm_func_cfg_output (size:128b/16B) */
@@ -15900,24 +16699,27 @@ struct hwrm_func_qstats_input {
* A privileged PF can query for other function's statistics.
*/
uint16_t fid;
- /* This flags indicates the type of statistics request. */
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * flags should be set to 1 when request is for only RoCE statistics.
- * This will be honored only if the caller_fid is a privileged PF.
- * In all other cases FID and caller_fid should be the same.
+ * This bit should be set to 1 when request is for only RoCE
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
*/
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
/*
- * flags should be set to 2 when request is for the counter mask,
+ * This bit should be set to 1 when request is for the counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
- #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
- HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
+ /*
+ * This bit should be set to 1 when request is for only L2
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
+ */
+ #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4)
uint8_t unused_0[5];
} __rte_packed;
@@ -15992,7 +16794,18 @@ struct hwrm_func_qstats_output {
uint64_t rx_agg_events;
/* Number of aborted aggregations on the function. */
uint64_t rx_agg_aborts;
- uint8_t unused_0[7];
+ /*
+ * This field is the sequence of the statistics of a function being
+ * cleared. Firmware starts the sequence from zero. It increments
+ * the sequence number every time the statistics of the function
+ * are cleared, which can be triggered by a clear statistics request
+ * or by freeing all statistics contexts of the function. If a user
+ * is interested in knowing if the statistics have been cleared
+ * since the last query, it can keep track of this sequence number
+ * between queries.
+ */
+ uint8_t clear_seq;
+ uint8_t unused_0[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -16045,24 +16858,20 @@ struct hwrm_func_qstats_ext_input {
* A privileged PF can query for other function's statistics.
*/
uint16_t fid;
- /* This flags indicates the type of statistics request. */
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
- * flags should be set to 1 when request is for only RoCE statistics.
- * This will be honored only if the caller_fid is a privileged PF.
- * In all other cases FID and caller_fid should be the same.
+ * This bit should be set to 1 when request is for only RoCE
+ * statistics. This will be honored only if the caller_fid is
+ * a privileged PF. In all other cases FID and caller_fid should
+ * be the same.
*/
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
+ #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
/*
- * flags should be set to 2 when request is for the counter mask
+ * This bit should be set to 1 when request is for the counter mask
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
- #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
- HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
uint8_t unused_0[1];
uint32_t enables;
/*
@@ -16418,6 +17227,14 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \
UINT32_C(0x200)
+ /*
+ * When this bit is 1, the function's driver is indicating the
+ * support for asymmetric queue configuration, such that queue
+ * ids and service profiles on TX side are not the same as the
+ * corresponding queue configuration on the RX side
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \
+ UINT32_C(0x400)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -16979,7 +17796,7 @@ struct hwrm_func_resource_qcaps_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_resource_qcaps_output (size:512b/64B) */
+/* hwrm_func_resource_qcaps_output (size:576b/72B) */
struct hwrm_func_resource_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -17054,15 +17871,16 @@ struct hwrm_func_resource_qcaps_output {
*/
#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ uint8_t unused_0[2];
/* Minimum guaranteed number of Tx Key Contexts */
- uint16_t min_tx_key_ctxs;
+ uint32_t min_tx_key_ctxs;
/* Maximum non-guaranteed number of Tx Key Contexts */
- uint16_t max_tx_key_ctxs;
+ uint32_t max_tx_key_ctxs;
/* Minimum guaranteed number of Rx Key Contexts */
- uint16_t min_rx_key_ctxs;
+ uint32_t min_rx_key_ctxs;
/* Maximum non-guaranteed number of Rx Key Contexts */
- uint16_t max_rx_key_ctxs;
- uint8_t unused_0[5];
+ uint32_t max_rx_key_ctxs;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -17078,7 +17896,7 @@ struct hwrm_func_resource_qcaps_output {
*****************************/
-/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
+/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */
struct hwrm_func_vf_resource_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -17152,18 +17970,18 @@ struct hwrm_func_vf_resource_cfg_input {
*/
#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
UINT32_C(0x1)
+ uint8_t unused_0[2];
/* Minimum guaranteed number of Tx Key Contexts */
- uint16_t min_tx_key_ctxs;
+ uint32_t min_tx_key_ctxs;
/* Maximum non-guaranteed number of Tx Key Contexts */
- uint16_t max_tx_key_ctxs;
+ uint32_t max_tx_key_ctxs;
/* Minimum guaranteed number of Rx Key Contexts */
- uint16_t min_rx_key_ctxs;
+ uint32_t min_rx_key_ctxs;
/* Maximum non-guaranteed number of Rx Key Contexts */
- uint16_t max_rx_key_ctxs;
- uint8_t unused_0[2];
+ uint32_t max_rx_key_ctxs;
} __rte_packed;
-/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
+/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */
struct hwrm_func_vf_resource_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -17190,10 +18008,10 @@ struct hwrm_func_vf_resource_cfg_output {
/* Reserved number of ring groups */
uint16_t reserved_hw_ring_grps;
/* Actual number of Tx Key Contexts reserved */
- uint16_t reserved_tx_key_ctxs;
+ uint32_t reserved_tx_key_ctxs;
/* Actual number of Rx Key Contexts reserved */
- uint16_t reserved_rx_key_ctxs;
- uint8_t unused_0[3];
+ uint32_t reserved_rx_key_ctxs;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -17479,8 +18297,13 @@ struct hwrm_func_backing_store_qcaps_output {
* function.
*/
uint32_t rkc_max_entries;
+ /*
+ * Additional number of RoCE QP context entries required for this
+ * function to support fast QP destroy feature.
+ */
+ uint16_t fast_qpmd_qp_num_entries;
/* Reserved for future. */
- uint8_t rsvd1[7];
+ uint8_t rsvd1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20638,31 +21461,53 @@ struct hwrm_func_ptp_pin_qcfg_output {
/* Type of function for Pin #2. */
uint8_t pin2_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
/* Type of function for Pin #3. */
uint8_t pin3_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
uint8_t unused_0;
/*
* This field is used in Output records to indicate that the output
@@ -20813,17 +21658,28 @@ struct hwrm_func_ptp_pin_cfg_input {
/* Configure function for TSIO pin#2. */
uint8_t pin2_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
/* Enable or disable functionality of Pin #3. */
uint8_t pin3_state;
/* Disabled */
@@ -20835,17 +21691,28 @@ struct hwrm_func_ptp_pin_cfg_input {
/* Configure function for TSIO pin#3. */
uint8_t pin3_usage;
/* No function is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE \
+ UINT32_C(0x0)
/* PPS IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN \
+ UINT32_C(0x1)
/* PPS OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT \
+ UINT32_C(0x2)
/* SYNC IN is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN \
+ UINT32_C(0x3)
/* SYNC OUT is configured. */
- #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT \
+ UINT32_C(0x4)
+ /* SYNCE primary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \
+ UINT32_C(0x5)
+ /* SYNCE secondary clock OUT is configured. */
+ #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \
+ UINT32_C(0x6)
#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \
- HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT
+ HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
uint8_t unused_0[4];
} __rte_packed;
@@ -21130,12 +21997,25 @@ struct hwrm_func_ptp_ts_query_output {
uint16_t resp_len;
/* Timestamp value of last PPS event latched. */
uint64_t pps_event_ts;
- /* PTM local timestamp value. */
- uint64_t ptm_res_local_ts;
- /* PTM Master timestamp value. */
- uint64_t ptm_pmstr_ts;
- /* PTM Master propagation delay */
- uint32_t ptm_mstr_prop_dly;
+ /*
+ * PHC timestamp value when PTM responseD request is received
+ * at downstream port (t4'). This is a 48 bit timestamp in nanoseconds.
+ */
+ uint64_t ptm_local_ts;
+ /*
+ * PTM System timestamp value corresponding to t4' at
+ * root complex (T4'). Together with ptm_local_ts, these
+ * two timestamps provide the cross-trigger timestamps.
+ * Driver can directly use these values for cross-trigger.
+ * This is a 48 bit timestamp in nanoseconds.
+ */
+ uint64_t ptm_system_ts;
+ /*
+ * PTM Link delay. This is the time taken at root complex (RC)
+ * between receiving PTM request and sending PTM response to
+ * downstream port. This is a 32 bit value in nanoseconds.
+ */
+ uint32_t ptm_link_delay;
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -21463,7 +22343,18 @@ struct hwrm_func_key_ctx_alloc_output {
uint16_t resp_len;
/* Actual number of Key Contexts allocated. */
uint16_t num_key_ctxs_allocated;
- uint8_t unused_0[5];
+ /* Control flags. */
+ uint8_t flags;
+ /*
+ * When set, it indicates that all key contexts allocated by this
+ * command are contiguous. As a result, the driver has to read the
+ * start context ID from the first entry of the DMA data buffer
+ * and figures out the end context ID by “start context ID +
+ * num_key_ctxs_allocated - 1”.
+ */
+ #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \
+ UINT32_C(0x1)
+ uint8_t unused_0[4];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21574,6 +22465,9 @@ struct hwrm_func_backing_store_cfg_v2_input {
* Instance of the backing store type. It is zero-based,
* which means "0" indicates the first instance. For backing
* stores with single instance only, leave this field to 0.
+ * 1. If the backing store type is MPC TQM ring, use the following
+ * instance value to MPC client mapping:
+ * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
*/
uint16_t instance;
/* Control flags. */
@@ -21586,6 +22480,31 @@ struct hwrm_func_backing_store_cfg_v2_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the driver indicates that the backing store type
+ * to be configured in this command is the last one to do for
+ * the associated PF. That means all backing store type
+ * configurations are done for the corresponding PF after this
+ * command. As a result, the firmware has to do the necessary
+ * post configurations.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE \
+ UINT32_C(0x2)
+ /*
+ * When set, the driver indicates extending the size of the specific
+ * backing store type instead of configuring the corresponding PBLs.
+ * The size specified in the command will be the new size to be
+ * configured. The operation is only valid when the specific backing
+ * store has been configured before. Otherwise, the firmware will
+ * return an error. The driver needs to zero out the “entry_size”,
+ * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the
+ * firmware will ignore these inputs. Further, the firmware expects
+ * the “num_entries” and any valid split entries to be no less than
+ * the initial value that has been configured. If not, it will
+ * return an error code.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND \
+ UINT32_C(0x4)
/* Page directory. */
uint64_t page_dir;
/* Number of entries */
@@ -21957,6 +22876,52 @@ struct hwrm_func_backing_store_qcfg_v2_output {
uint8_t valid;
} __rte_packed;
+/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* qpc_split_entries (size:128b/16B) */
+struct qpc_split_entries {
+ /* Number of L2 QP backing store entries. */
+ uint32_t qp_num_l2_entries;
+ /* Number of QP1 entries. */
+ uint32_t qp_num_qp1_entries;
+ uint32_t rsvd[2];
+} __rte_packed;
+
+/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* srq_split_entries (size:128b/16B) */
+struct srq_split_entries {
+ /* Number of L2 SRQ backing store entries. */
+ uint32_t srq_num_l2_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* cq_split_entries (size:128b/16B) */
+struct cq_split_entries {
+ /* Number of L2 CQ backing store entries. */
+ uint32_t cq_num_l2_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* vnic_split_entries (size:128b/16B) */
+struct vnic_split_entries {
+ /* Number of VNIC backing store entries. */
+ uint32_t vnic_num_vnic_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
+/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */
+/* mrav_split_entries (size:128b/16B) */
+struct mrav_split_entries {
+ /* Number of AV backing store entries. */
+ uint32_t mrav_num_av_entries;
+ uint32_t rsvd;
+ uint32_t rsvd2[2];
+} __rte_packed;
+
/************************************
* hwrm_func_backing_store_qcaps_v2 *
************************************/
@@ -22150,6 +23115,9 @@ struct hwrm_func_backing_store_qcaps_v2_output {
/*
* Bit map of the valid instances associated with the
* backing store type.
+ * 1. If the backing store type is MPC TQM ring, use the following
+ * bit to MPC client mapping:
+ * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
*/
uint32_t instance_bit_map;
/*
@@ -22506,7 +23474,7 @@ struct hwrm_func_dbr_pacing_qcfg_output {
uint8_t unused_3[7];
/*
* Specifies primary function’s NQ ID.
- * A value of 0xFFFF indicates NQ ID is invalid.
+ * A value of 0xFFFF FFFF indicates NQ ID is invalid.
*/
uint32_t primary_nq_id;
/*
@@ -22585,13 +23553,13 @@ struct hwrm_func_dbr_pacing_broadcast_event_output {
uint8_t valid;
} __rte_packed;
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/*************************************
+ * hwrm_func_dbr_pacing_nqlist_query *
+ *************************************/
-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
-struct hwrm_func_vlan_qcfg_input {
+/* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */
+struct hwrm_func_dbr_pacing_nqlist_query_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -22620,18 +23588,10 @@ struct hwrm_func_vlan_qcfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /*
- * Function ID of the function that is being
- * configured.
- * If set to 0xFF... (All Fs), then the configuration is
- * for the requesting function.
- */
- uint16_t fid;
- uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
-struct hwrm_func_vlan_qcfg_output {
+/* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */
+struct hwrm_func_dbr_pacing_nqlist_query_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -22640,49 +23600,414 @@ struct hwrm_func_vlan_qcfg_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint64_t unused_0;
- /* S-TAG VLAN identifier configured for the function. */
- uint16_t stag_vid;
- /* S-TAG PCP value configured for the function. */
- uint8_t stag_pcp;
- uint8_t unused_1;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id0;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id1;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id2;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id3;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id4;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id5;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id6;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id7;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id8;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id9;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id10;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id11;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id12;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id13;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id14;
+ /* ID of an NQ ring allocated for DBR pacing notifications. */
+ uint16_t nq_ring_id15;
+ /* Number of consecutive NQ ring IDs populated in the response. */
+ uint32_t num_nqs;
+ uint8_t unused_0[3];
/*
- * S-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t stag_tpid;
- /* C-TAG VLAN identifier configured for the function. */
- uint16_t ctag_vid;
- /* C-TAG PCP value configured for the function. */
- uint8_t ctag_pcp;
- uint8_t unused_2;
+ uint8_t valid;
+} __rte_packed;
+
+/************************************
+ * hwrm_func_dbr_recovery_completed *
+ ************************************/
+
+
+/* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */
+struct hwrm_func_dbr_recovery_completed_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * C-TAG TPID value configured for the function. This field is specified in
- * network byte order.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t ctag_tpid;
- /* Future use. */
- uint32_t rsvd2;
- /* Future use. */
- uint32_t rsvd3;
- uint8_t unused_3[3];
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Specifies the epoch value with the one that was specified by the
+ * firmware in the error_report_doorbell_drop_threshold async event
+ * corresponding to the specific recovery cycle.
+ */
+ uint32_t epoch;
+ /* The epoch value. */
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK \
+ UINT32_C(0xffffff)
+ #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */
+struct hwrm_func_dbr_recovery_completed_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
*/
uint8_t valid;
} __rte_packed;
-/**********************
- * hwrm_func_vlan_cfg *
- **********************/
+/***********************
+ * hwrm_func_synce_cfg *
+ ***********************/
-/* hwrm_func_vlan_cfg_input (size:384b/48B) */
-struct hwrm_func_vlan_cfg_input {
+/* hwrm_func_synce_cfg_input (size:192b/24B) */
+struct hwrm_func_synce_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t enables;
+ /*
+ * This bit must be '1' for the freq_profile field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the primary_clock_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the secondary_clock_state field to be
+ * configured.
+ */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK \
+ UINT32_C(0x4)
+ /* Frequency profile for SyncE recovered clock. */
+ uint8_t freq_profile;
+ /* Invalid frequency profile */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
+ /* 25MHz SyncE clock profile */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ
+ /*
+ * Enable or disable primary clock for PF/port, overriding previous
+ * primary clock setting.
+ */
+ uint8_t primary_clock_state;
+ /* Disable clock */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE \
+ UINT32_C(0x0)
+ /* Enable clock */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE \
+ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE
+ /*
+ * Enable or disable secondary clock for PF/port, overriding previous
+ * secondary clock setting.
+ */
+ uint8_t secondary_clock_state;
+ /* Clock disabled */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE \
+ UINT32_C(0x0)
+ /* Clock enabled */
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE \
+ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \
+ HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE
+ uint8_t unused_0[4];
+} __rte_packed;
+
+/* hwrm_func_synce_cfg_output (size:128b/16B) */
+struct hwrm_func_synce_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_func_synce_qcfg *
+ ************************/
+
+
+/* hwrm_func_synce_qcfg_input (size:192b/24B) */
+struct hwrm_func_synce_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __rte_packed;
+
+/* hwrm_func_synce_qcfg_output (size:128b/16B) */
+struct hwrm_func_synce_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Frequency profile for SyncE recovered clock. */
+ uint8_t freq_profile;
+ /* Invalid frequency profile */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
+ /* 25MHz SyncE clock profile */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_LAST \
+ HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ
+ /* SyncE recovered clock state */
+ uint8_t state;
+ /*
+ * When this bit is '1', primary clock is enabled for this PF/port.
+ * When this bit is '0', primary clock is disabled for this PF/port.
+ */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED \
+ UINT32_C(0x1)
+ /*
+ * When this bit is '1', secondary clock is enabled for this
+ * PF/port.
+ * When this bit is '0', secondary clock is disabled for this
+ * PF/port.
+ */
+ #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED \
+ UINT32_C(0x2)
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
+
+
+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
+struct hwrm_func_vlan_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Function ID of the function that is being
+ * configured.
+ * If set to 0xFF... (All Fs), then the configuration is
+ * for the requesting function.
+ */
+ uint16_t fid;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */
+struct hwrm_func_vlan_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint64_t unused_0;
+ /* S-TAG VLAN identifier configured for the function. */
+ uint16_t stag_vid;
+ /* S-TAG PCP value configured for the function. */
+ uint8_t stag_pcp;
+ uint8_t unused_1;
+ /*
+ * S-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t stag_tpid;
+ /* C-TAG VLAN identifier configured for the function. */
+ uint16_t ctag_vid;
+ /* C-TAG PCP value configured for the function. */
+ uint8_t ctag_pcp;
+ uint8_t unused_2;
+ /*
+ * C-TAG TPID value configured for the function. This field is specified in
+ * network byte order.
+ */
+ uint16_t ctag_tpid;
+ /* Future use. */
+ uint32_t rsvd2;
+ /* Future use. */
+ uint32_t rsvd3;
+ uint8_t unused_3[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_func_vlan_cfg *
+ **********************/
+
+
+/* hwrm_func_vlan_cfg_input (size:384b/48B) */
+struct hwrm_func_vlan_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24576,7 +25901,7 @@ struct hwrm_port_phy_qcfg_input {
uint8_t unused_0[6];
} __rte_packed;
-/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+/* hwrm_port_phy_qcfg_output (size:832b/104B) */
struct hwrm_port_phy_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25601,6 +26926,14 @@ struct hwrm_port_phy_qcfg_output {
/* 200Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
UINT32_C(0x4)
+ /*
+ * This field is used to indicate the reasons for link down.
+ * This field is set to 0, if the link down reason is unknown.
+ */
+ uint8_t link_down_reason;
+ /* Remote fault */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -26934,16 +28267,12 @@ struct hwrm_port_qstats_input {
/* Port ID of port that is being queried. */
uint16_t port_id;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for a counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0[5];
/*
* This is the host address where
@@ -27646,16 +28975,12 @@ struct hwrm_port_qstats_ext_input {
*/
uint16_t rx_stat_size;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for the counter mask,
* representing width of each of the stats counters, rather than
* counters themselves.
*/
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
- HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0;
/*
* This is the host address where
@@ -27903,16 +29228,12 @@ struct hwrm_port_ecn_qstats_input {
*/
uint16_t ecn_stat_buf_size;
uint8_t flags;
- /* This value is not used to avoid backward compatibility issues. */
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
/*
* This bit is set to 1 when request is for a counter mask,
* representing the width of each of the stats counters, rather
* than counters themselves.
*/
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
- #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
- HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
+ #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
uint8_t unused_0[3];
/*
* This is the host address where
@@ -28398,6 +29719,12 @@ struct hwrm_port_phy_qcaps_output {
*/
#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \
UINT32_C(0x2)
+ /*
+ * If set to 1, then this field indicates that
+ * bank based addressing is supported in firmware.
+ */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \
+ UINT32_C(0x4)
/*
* Number of internal ports for this device. This field allows the FW
* to advertise how many internal ports are present. Manufacturing
@@ -29720,6 +31047,14 @@ struct hwrm_port_prbs_test_input {
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
/* PRBS58 */
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* PRBS49 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7)
+ /* PRBS10 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8)
+ /* PRBS20 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9)
+ /* PRBS13 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa)
/* Invalid */
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
#define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
@@ -29749,6 +31084,15 @@ struct hwrm_port_prbs_test_input {
*/
#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
UINT32_C(0x4)
+ /* If set to 1, FEC stat t-code 0-7 registers are enabled. */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 \
+ UINT32_C(0x8)
+ /*
+ * If set to 1, FEC stat t-code 8-15 registers are enabled.
+ * If fec_stat_t0_t7 is set, fec_stat_t8_t15 field will be ignored.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 \
+ UINT32_C(0x10)
/* Duration in seconds to run the PRBS test. */
uint16_t timeout;
/*
@@ -29777,7 +31121,15 @@ struct hwrm_port_prbs_test_output {
uint16_t resp_len;
/* Total length of stored data. */
uint16_t total_data_len;
- uint16_t unused_0;
+ /* This field is used in Output records to indicate the output format */
+ uint8_t ber_format;
+ /* BER_FORMAT_PRBS */
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)
+ /* BER_FORMAT_FEC */
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1)
+ #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_LAST \
+ HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC
+ uint8_t unused_0;
uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
@@ -30800,6 +32152,160 @@ struct hwrm_port_ep_tx_qcfg_output {
uint8_t valid;
} __rte_packed;
+/*****************
+ * hwrm_port_cfg *
+ *****************/
+
+
+/* hwrm_port_cfg_input (size:256b/32B) */
+struct hwrm_port_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tx_rate_limit field to
+ * be configured.
+ */
+ #define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1)
+ /* Port ID of port that is to be configured. */
+ uint16_t port_id;
+ uint16_t unused_0;
+ /*
+ * Requested setting of TX rate limit in Mbps.
+ * tx_rate_limit = 0 will cancel the rate limit if any.
+ * This field is valid only when tx_rate_limit bit in 'enables'
+ * field is '1'.
+ */
+ uint32_t tx_rate_limit;
+} __rte_packed;
+
+/* hwrm_port_cfg_output (size:128b/16B) */
+struct hwrm_port_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************
+ * hwrm_port_qcfg *
+ ******************/
+
+
+/* hwrm_port_qcfg_input (size:192b/24B) */
+struct hwrm_port_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Port ID of port that is to be queried. */
+ uint16_t port_id;
+ uint8_t unused_0[6];
+} __rte_packed;
+
+/* hwrm_port_qcfg_output (size:192b/24B) */
+struct hwrm_port_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t supported;
+ /*
+ * If set to '1', then this bit indicates that TX rate limit
+ * could be configured via hwrm_port_cfg command.
+ */
+ #define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1)
+ uint32_t enabled;
+ /*
+ * If set to '1', then this bit indicates that TX rate limit
+ * is enabled and could be found in tx_rate_limit field.
+ */
+ #define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1)
+ /*
+ * Current setting of TX rate limit in Mbps.
+ * This field is valid only when tx_rate_limit bit in 'enabled'
+ * field is '1'.
+ */
+ uint32_t tx_rate_limit;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -35688,29 +37194,19 @@ struct hwrm_vnic_update_input {
HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
/*
* The metadata format type used in all the RX packet completions
- * going through this VNIC.
+ * going through this VNIC. This value is product specific. Refer to
+ * the L2 HSI completion ring structures for the detailed
+ * descriptions. For Thor and Thor2, it corresponds to “meta_format”
+ * in “rx_pkt_cmpl_hi” and “rx_pkt_v3_cmpl_hi”, respectively.
*/
uint8_t metadata_format_type;
- /* No metadata information. */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
- UINT32_C(0x0)
- /*
- * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
- * vtag[19:0]).
- */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
- UINT32_C(0x1)
- /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
- UINT32_C(0x2)
- /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
- UINT32_C(0x3)
- /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
- #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
- UINT32_C(0x4)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
+ #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
- HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
+ HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4
/*
* The maximum receive unit of the vnic.
* Each vnic is associated with a function.
@@ -35911,6 +37407,12 @@ struct hwrm_vnic_cfg_input {
*/
#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
UINT32_C(0x40)
+ /*
+ * When this bit is '1' it enables ring selection using the incoming
+ * spif and lcos for the packet.
+ */
+ #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the dflt_ring_grp field to be
@@ -36259,6 +37761,9 @@ struct hwrm_vnic_qcfg_output {
*/
#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
UINT32_C(0x80)
+ /* When this bit is '1' it indicates port cos_mapping_mode enabled. */
+ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x100)
/*
* When returned with a valid CoS Queue id, the CoS Queue/VNIC association
* is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
@@ -36315,7 +37820,30 @@ struct hwrm_vnic_qcfg_output {
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \
HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED
- uint8_t unused_1[3];
+ /*
+ * This field conveys the metadata format type that has been
+ * configured. This value is product specific. Refer to the L2 HSI
+ * completion ring structures for the detailed descriptions. For Thor
+ * and Thor2, it corresponds to “meta_format” in “rx_pkt_cmpl_hi” and
+ * “rx_pkt_v3_cmpl_hi”, respectively.
+ */
+ uint8_t metadata_format_type;
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
+ #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST \
+ HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4
+ /* This field conveys the VNIC operation state. */
+ uint8_t vnic_state;
+ /* Normal operation state. */
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
+ /* Drop all packets. */
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1)
+ #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST \
+ HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP
+ uint8_t unused_1;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -36557,6 +38085,53 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \
UINT32_C(0x100000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv4 IPSEC AH SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv4 IPSEC ESP SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP \
+ UINT32_C(0x400000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv6 IPSEC AH SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP \
+ UINT32_C(0x800000)
+ /*
+ * When this bit is '1' HW supports hash calculation
+ * based on IPv6 IPSEC ESP SPI field.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP \
+ UINT32_C(0x1000000)
+ /*
+ * When outermost_rss_cap is '1' and this bit is '1', the outermost
+ * RSS hash mode may be set on a PF or trusted VF.
+ * When outermost_rss_cap is '1' and this bit is '0', the outermost
+ * RSS hash mode may be set on a PF.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP \
+ UINT32_C(0x2000000)
+ /*
+ * When this bit is '1' it indicates HW is capable of enabling ring
+ * selection using the incoming spif and lcos for the packet.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \
+ UINT32_C(0x4000000)
+ /*
+ * When this bit is '1', it indicates controller enabled
+ * RSS profile TCAM mode.
+ */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED \
+ UINT32_C(0x8000000)
+ /* When this bit is '1' FW supports VNIC hash mode. */
+ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \
+ UINT32_C(0x10000000)
/*
* This field advertises the maximum concurrent TPA aggregations
* supported by the VNIC on new devices that support TPA v2 or v3.
@@ -36869,6 +38444,38 @@ struct hwrm_vnic_rss_cfg_input {
*/
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \
UINT32_C(0x40)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv4 packets. Host drivers should set this bit based on
+ * rss_ipsec_ah_spi_ipv4_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv4 packets. Host drivers should set this bit based on
+ * rss_ipsec_esp_spi_ipv4_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv6 packets. Host drivers should set this bit based on
+ * rss_ipsec_ah_spi_ipv6_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv6 packets. Host drivers should set this bit based on
+ * rss_ipsec_esp_spi_ipv6_cap.
+ */
+ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 \
+ UINT32_C(0x400)
/* VNIC ID of VNIC associated with RSS table being configured. */
uint16_t vnic_id;
/*
@@ -36876,11 +38483,25 @@ struct hwrm_vnic_rss_cfg_input {
* Valid values range from 0 to 7.
*/
uint8_t ring_table_pair_index;
- /* Flags to specify different RSS hash modes. */
+ /*
+ * Flags to specify different RSS hash modes. Global RSS hash mode is
+ * indicated when vnic_id and rss_ctx_idx fields are set to value of
+ * 0xffff. Only PF can initiate global RSS hash mode setting changes.
+ * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx,
+ * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based
+ * on first come first serve order. Global RSS hash mode and VNIC RSS
+ * hash modes are mutually exclusive. FW returns invalid error
+ * if FW receives conflicting requests. To change the current hash
+ * mode, the mode associated drivers need to be unloaded and apply
+ * the new configuration.
+ */
uint8_t hash_mode_flags;
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,
+ * innermost_4 and innermost_2 hash modes are used to configure
+ * the tuple mode. When this bit is '1' and FW is not
+ * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash
+ * mode setting configured in the device otherwise.
*/
#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
@@ -37063,9 +38684,17 @@ struct hwrm_vnic_rss_qcfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Index to the rss indirection table. */
+ /*
+ * Index to the rss indirection table. This field is used as a lookup
+ * for chips before Thor - i.e. Cumulus and Whitney.
+ */
uint16_t rss_ctx_idx;
- uint8_t unused_0[6];
+ /*
+ * VNIC ID of VNIC associated with RSS table being queried. This field
+ * is used as a lookup for Thor and later chips.
+ */
+ uint16_t vnic_id;
+ uint8_t unused_0[4];
} __rte_packed;
/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
@@ -37084,45 +38713,104 @@ struct hwrm_vnic_rss_qcfg_output {
* over source and destination IPv4 addresses of IPv4
* packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 \
+ UINT32_C(0x1)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv4 addresses and
* source/destination ports of TCP/IPv4 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 \
+ UINT32_C(0x2)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv4 addresses and
* source/destination ports of UDP/IPv4 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 \
+ UINT32_C(0x4)
/*
* When this bit is '1', the RSS hash shall be computed
* over source and destination IPv6 addresses of IPv6
* packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 \
+ UINT32_C(0x8)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv6 addresses and
* source/destination ports of TCP/IPv6 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 \
+ UINT32_C(0x10)
/*
* When this bit is '1', the RSS hash shall be computed
* over source/destination IPv6 addresses and
* source/destination ports of UDP/IPv6 packets.
*/
- #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 \
+ UINT32_C(0x20)
+ /*
+ * When this bit is '1', the RSS hash shall be computed
+ * over source, destination IPv6 addresses and flow label of IPv6
+ * packets. Hash type ipv6 and ipv6_flow_label are mutually
+ * exclusive. HW does not include the flow_label in hash
+ * calculation for the packets that are matching tcp_ipv6 and
+ * udp_ipv6 hash types. This bit will be '0' if
+ * rss_ipv6_flow_label_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL \
+ UINT32_C(0x40)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap
+ * is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 \
+ UINT32_C(0x80)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv4 packets. This bit will be '0' if
+ * rss_ipsec_esp_spi_ipv4_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 \
+ UINT32_C(0x100)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC
+ * AH/IPv6 packets. This bit will be '0' if
+ * rss_ipsec_ah_spi_ipv6_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 \
+ UINT32_C(0x200)
+ /*
+ * When this bit is '1', the RSS hash shall be computed over
+ * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC
+ * ESP/IPv6 packets. This bit will be '0' if
+ * rss_ipsec_esp_spi_ipv6_cap is '0'.
+ */
+ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 \
+ UINT32_C(0x400)
uint8_t unused_0[4];
/* This is the value of rss hash key */
uint32_t hash_key[10];
- /* Flags to specify different RSS hash modes. */
+ /*
+ * Flags to specify different RSS hash modes. Setting rss_ctx_idx to
+ * the value of 0xffff implies a global RSS configuration query.
+ * hash_mode_flags are only valid for global RSS configuration query.
+ * Only the PF can initiate a global RSS configuration query.
+ * The query request fails if any VNIC is configured with hash mode
+ * and rss_ctx_idx is 0xffff.
+ */
uint8_t hash_mode_flags;
/*
- * When this bit is '1', it indicates using current RSS
- * hash mode setting configured in the device.
+ * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable,
+ * it indicates VNIC's configured RSS hash mode.
+ * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable,
+ * It indicates using current RSS hash mode setting configured in the
+ * device.
*/
#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
UINT32_C(0x1)
@@ -37832,6 +39520,27 @@ struct hwrm_ring_alloc_input {
*/
#define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \
UINT32_C(0x2)
+ /*
+ * Used with enhanced Doorbell Pacing feature, when set to '1'
+ * this flag indicates that the NQ id that's allocated should be
+ * used for DBR pacing notifications.
+ */
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING \
+ UINT32_C(0x4)
+ /*
+ * Host driver should set this flag bit to '1' to enable
+ * two-completion TX packet timestamp feature. By enabling this
+ * per QP flag and enabling stamp bit in TX BD lflags, host drivers
+ * expect two completions, one for regular TX completion and the
+ * other completion with timestamp. For a QP with both completion
+ * coalescing and timestamp completion features enabled, completion
+ * coalescing takes place on regular TX completions. The timestamp
+ * completions are not coalesced and a separate timestamp completion
+ * is generated for each packet with stamp bit set in the TX BD
+ * lflags.
+ */
+ #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE \
+ UINT32_C(0x8)
/*
* This value is a pointer to the page table for the
* Ring.
@@ -38026,7 +39735,7 @@ struct hwrm_ring_alloc_input {
* completion rings are allowed.
*/
uint8_t int_mode;
- /* Legacy INTA */
+ /* Legacy INTA (deprecated) */
#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
/* Reserved */
#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
@@ -40371,6 +42080,9 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41239,6 +42951,9 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
*/
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41507,6 +43222,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41629,6 +43347,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41743,6 +43464,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
*/
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -41978,8 +43702,11 @@ struct hwrm_cfa_encap_record_alloc_input {
*/
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -42309,6 +44036,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* Applies to UDP and TCP traffic.
* 6 - TCP
* 17 - UDP
+ * 1 - ICMP
+ * 58 - ICMPV6
+ * 255 - RSVD
*/
uint8_t ip_protocol;
/* invalid */
@@ -42320,8 +44050,17 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* UDP */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
UINT32_C(0x11)
+ /* ICMP */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP \
+ UINT32_C(0x1)
+ /* ICMPV6 */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 \
+ UINT32_C(0x3a)
+ /* RSVD */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD \
+ UINT32_C(0xff)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD
/*
* If set, this value shall represent the
* Logical VNIC ID of the destination VNIC for the RX
@@ -42388,6 +44127,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -42979,6 +44721,9 @@ struct hwrm_cfa_em_flow_alloc_input {
*/
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -44444,6 +46189,9 @@ struct hwrm_cfa_decap_filter_alloc_input {
*/
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -44929,6 +46677,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -45182,8 +46933,11 @@ struct hwrm_cfa_flow_action_data {
* (IPV6oVXLANGPE)
*/
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
- HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE
uint8_t unused[7];
/* This value is encap data for the associated encap type. */
uint32_t encap_data[20];
@@ -45238,6 +46992,9 @@ struct hwrm_cfa_flow_tunnel_hdr_data {
*/
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
/* Any tunneled traffic */
#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -45377,19 +47134,35 @@ struct hwrm_cfa_flow_info_input {
/* Max flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
UINT32_C(0xfff)
- #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
/* CNP flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
UINT32_C(0x1000)
/* RoCEv1 flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
UINT32_C(0x2000)
+ /* NIC flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX \
+ UINT32_C(0x3000)
/* RoCEv2 flow handle */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
UINT32_C(0x4000)
/* Direction rx = 1 */
#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
UINT32_C(0x8000)
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX \
+ UINT32_C(0x9000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX \
+ UINT32_C(0xa000)
+ /* NIC flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX \
+ UINT32_C(0xb000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX \
+ UINT32_C(0xc000)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST \
+ HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX
uint8_t unused_0[6];
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
@@ -45629,27 +47402,67 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
+ /* Number of valid flows in this command. */
uint16_t num_flows;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_0 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_0;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_1 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_1;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_2 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_2;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_3 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_3;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_4 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_4;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_5 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_5;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_6 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_6;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_7 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_7;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_8 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_8;
- /* Flow handle. */
+ /*
+ * Flow handle.
+ * For a listing of applicable flow_handle_9 values, see enumeration
+ * in hwrm_cfa_flow_info_input.
+ */
uint16_t flow_handle_9;
uint8_t unused_0[2];
/* Flow ID of a flow. */
@@ -45724,7 +47537,16 @@ struct hwrm_cfa_flow_stats_output {
uint64_t byte_8;
/* byte_9 is 64 b */
uint64_t byte_9;
- uint8_t unused_0[7];
+ /*
+ * If a flow has been hit, the bit representing the flow will be 1.
+ * Likewise, if a flow has not, the bit representing the flow
+ * will be 0. Mapping will match flow numbers where bitX is for flowX
+ * (ex: bit 0 is flow0). This only applies for NIC flows. Upon
+ * reading of the flow, the bit will be cleared for the flow and only
+ * set again when traffic is received by the flow.
+ */
+ uint16_t flow_hits;
+ uint8_t unused_0[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -46498,27 +48320,36 @@ struct hwrm_cfa_pair_alloc_input {
* 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
*/
uint16_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
UINT32_C(0x4)
- /* Modify existing rep2fn pair and move pair to new PF. */
+ /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
UINT32_C(0x5)
/*
* Modify existing rep2fn pairs paired with same PF and move pairs
- * to new PF.
+ * to new PF. (deprecated)
*/
#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
UINT32_C(0x6)
@@ -46672,21 +48503,30 @@ struct hwrm_cfa_pair_free_input {
* 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
*/
uint16_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
- /* Modify existing rep2fn pair and move pair to new PF. */
+ /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
/*
* Modify existing rep2fn pairs paired with same PF and move pairs
- * to new PF.
+ * to new PF. (deprecated)
*/
#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
/*
@@ -46808,15 +48648,24 @@ struct hwrm_cfa_pair_info_output {
uint16_t tx_cfa_action_b;
/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
uint8_t pair_mode;
- /* Pair between VF on local host with PF or VF on specified host. */
+ /*
+ * Pair between VF on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
- /* Pair between REP on local host with PF or VF on specified host. */
+ /*
+ * Pair between REP on local host with PF or VF on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
- /* Pair between REP on local host with REP on specified host. */
+ /*
+ * Pair between REP on local host with REP on specified host.
+ * (deprecated)
+ */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
- /* Pair for the proxy interface. */
+ /* Pair for the proxy interface. (deprecated) */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
- /* Pair for the PF interface. */
+ /* Pair for the PF interface. (deprecated) */
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
@@ -47084,6 +48933,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
*/
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
UINT32_C(0x2000)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE \
+ UINT32_C(0x4000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -48272,7 +50124,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* Value of 1 to indicate firmware support flow batch delete
* operation through HWRM_CFA_FLOW_FLUSH command.
* Value of 0 to indicate that the firmware does not support flow
- * batch delete operation.
+ * batch delete operation. (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
UINT32_C(0x4)
@@ -48280,7 +50132,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* Value of 1 to indicate that the firmware support flow reset all
* operation through HWRM_CFA_FLOW_FLUSH command.
* Value of 0 indicates firmware does not support flow reset all
- * operation.
+ * operation. (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
@@ -48295,12 +50147,14 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
/*
* Value of 1 to indicate that firmware supports TX EEM flows.
* Value of 0 indicates firmware does not support TX EEM flows.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
/*
* Value of 1 to indicate that firmware supports RX EEM flows.
* Value of 0 indicates firmware does not support RX EEM flows.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
@@ -48309,6 +50163,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
* allocation of an on-chip flow counter which can be used for EEM
* flows. Value of 0 indicates firmware does not support the dynamic
* allocation of an on-chip flow counter.
+ * (deprecated)
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
UINT32_C(0x80)
@@ -48390,6 +50245,19 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \
UINT32_C(0x40000)
+ /*
+ * If set to 1, firmware is capable returning stats for nic flows
+ * in cfa_flow_stats command where flow_handle value 0xF000.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED \
+ UINT32_C(0x80000)
+ /*
+ * If set to 1, firmware is capable of supporting these additional
+ * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default,
+ * this flag should be 0 for older version of firmware.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \
+ UINT32_C(0x100000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -50172,7 +52040,7 @@ struct hwrm_tf_tbl_type_get_input {
uint32_t index;
} __rte_packed;
-/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
+/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */
struct hwrm_tf_tbl_type_get_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -50189,7 +52057,7 @@ struct hwrm_tf_tbl_type_get_output {
/* unused */
uint16_t unused0;
/* Response data. */
- uint8_t data[128];
+ uint8_t data[256];
/* unused */
uint8_t unused1[7];
/*
@@ -50250,6 +52118,8 @@ struct hwrm_tf_tbl_type_set_input {
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate table data is being sent via DMA. */
+ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
/* unused. */
uint8_t unused0[2];
/*
@@ -52298,133 +54168,2494 @@ struct hwrm_tf_if_tbl_set_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
- uint32_t fw_session_id;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Index of the type to set. */
+ uint32_t index;
+ /* Size of the data to set. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused1[6];
+ /* Data to be set. */
+ uint8_t data[88];
+} __rte_packed;
+
+/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
+struct hwrm_tf_if_tbl_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tf_tbl_type_bulk_get *
+ *****************************/
+
+
+/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
+struct hwrm_tf_tbl_type_bulk_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * When set use the special access register access to clear
+ * the table entries on read.
+ */
+ #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * Type of the resource, defined globally in the
+ * hwrm_tf_resc_type enum.
+ */
+ uint32_t type;
+ /* Starting index of the type to retrieve. */
+ uint32_t start_index;
+ /* Number of entries to retrieve. */
+ uint32_t num_entries;
+ /* Number of entries to retrieve. */
+ uint32_t unused1;
+ /* Host memory where data will be stored. */
+ uint64_t host_addr;
+} __rte_packed;
+
+/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
+struct hwrm_tf_tbl_type_bulk_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Response code. */
+ uint32_t resp_code;
+ /* Response size. */
+ uint16_t size;
+ /* unused */
+ uint8_t unused0;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************************
+ * hwrm_tf_session_hotup_state_set *
+ ***********************************/
+
+
+/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */
+struct hwrm_tf_session_hotup_state_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Shared session state. */
+ uint16_t state;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX
+} __rte_packed;
+
+/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */
+struct hwrm_tf_session_hotup_state_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************************
+ * hwrm_tf_session_hotup_state_get *
+ ***********************************/
+
+
+/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */
+struct hwrm_tf_session_hotup_state_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint32_t fw_session_id;
+ /* Control flags. */
+ uint16_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX
+ /* unused. */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */
+struct hwrm_tf_session_hotup_state_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Shared session HA state. */
+ uint16_t state;
+ /* Shared session HA reference count. */
+ uint16_t ref_cnt;
+ /* unused. */
+ uint8_t unused0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_tbl_scope_qcaps *
+ ****************************/
+
+
+/*
+ * TruFlow command to check if firmware is capable of
+ * supporting table scopes.
+ */
+/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * The maximum number of lookup records that a table scope can support.
+ * This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint32_t max_lkup_rec_cnt;
+ /*
+ * The maximum number of action records that a table scope can support.
+ * This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint32_t max_act_rec_cnt;
+ /* Not zero if firmware capable of table scopes. */
+ uint8_t tbl_scope_capable;
+ /*
+ * log2 of the number of lookup static buckets that a table scope can
+ * support. This field is only valid if tbl_scope_capable is not zero.
+ */
+ uint8_t max_lkup_static_buckets_exp;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_tfc_tbl_scope_id_alloc *
+ *******************************/
+
+
+/*
+ * TruFlow command to allocate a table scope ID and create the pools.
+ *
+ * There is no corresponding free command since a table scope
+ * ID will automatically be freed once the last FID is removed.
+ * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns
+ * a fid_cnt of 0 that also means that the table scope ID has
+ * been freed.
+ */
+/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The maximum number of pools for this table scope. */
+ uint16_t max_pools;
+ /* Non-zero if this table scope is shared. */
+ uint8_t shared;
+ /*
+ * The size of the lookup pools per direction expressed as
+ * log2(max_records/max_pools). That is, size=2^exp.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t lkup_pool_sz_exp[2];
+ /*
+ * The size of the action pools per direction expressed as
+ * log2(max_records/max_pools). That is, size=2^exp.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t act_pool_sz_exp[2];
+ /* unused. */
+ uint8_t unused0;
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The table scope ID that was allocated. */
+ uint8_t tsid;
+ /*
+ * Non-zero if this is the first FID associated with this table scope
+ * ID.
+ */
+ uint8_t first;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tfc_tbl_scope_config *
+ *****************************/
+
+
+/* TruFlow command to configure the table scope memory. */
+/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */
+struct hwrm_tfc_tbl_scope_config_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The base addresses for lookup memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint64_t lkup_base_addr[2];
+ /*
+ * The base addresses for action memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint64_t act_base_addr[2];
+ /*
+ * The number of minimum sized lkup records per direction.
+ * In this usage, records are the minimum lookup memory
+ * allocation unit in a table scope. This value is the total
+ * memory required for buckets and entries.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t lkup_rec_cnt[2];
+ /*
+ * The number of minimum sized action records per direction.
+ * Similar to the lkup_rec_cnt, records are the minimum
+ * action memory allocation unit in a table scope.
+ *
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t act_rec_cnt[2];
+ /*
+ * The number of static lookup buckets in the table scope.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint32_t lkup_static_bucket_cnt[2];
+ /* The page size of the table scope. */
+ uint32_t pbl_page_sz;
+ /*
+ * The PBL level for lookup memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t lkup_pbl_level[2];
+ /*
+ * The PBL level for action memory.
+ * Array is indexed by enum cfa_dir.
+ */
+ uint8_t act_pbl_level[2];
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_config_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*******************************
+ * hwrm_tfc_tbl_scope_deconfig *
+ *******************************/
+
+
+/* TruFlow command to deconfigure the table scope memory. */
+/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_deconfig_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_deconfig_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_tbl_scope_fid_add *
+ ******************************/
+
+
+/* TruFlow command to add a FID to a table scope. */
+/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_fid_add_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_fid_add_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs currently in the table scope ID. */
+ uint8_t fid_cnt;
+ /* unused. */
+ uint8_t unused0[6];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_tbl_scope_fid_rem *
+ ******************************/
+
+
+/* TruFlow command to remove a FID from a table scope. */
+/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_fid_rem_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The table scope ID. */
+ uint8_t tsid;
+ /* unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_fid_rem_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs remaining in the table scope ID. */
+ uint16_t fid_cnt;
+ /* unused. */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************************
+ * hwrm_tfc_tbl_scope_pool_alloc *
+ *********************************/
+
+
+/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_pool_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Table Scope ID */
+ uint8_t tsid;
+ /* Control flags. Direction and type. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX
+ /* Indicates the table type. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE \
+ UINT32_C(0x2)
+ /* Lookup table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP \
+ (UINT32_C(0x0) << 1)
+ /* Action table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION
+ /* Unused */
+ uint8_t unused[6];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_pool_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pool ID */
+ uint16_t pool_id;
+ /* Pool size exponent. An exponent of 0 indicates a failure. */
+ uint8_t pool_sz_exp;
+ /* unused. */
+ uint8_t unused1[4];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/********************************
+ * hwrm_tfc_tbl_scope_pool_free *
+ ********************************/
+
+
+/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */
+struct hwrm_tfc_tbl_scope_pool_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Table Scope ID */
+ uint8_t tsid;
+ /* Control flags. Direction and type. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX
+ /* Indicates the table type. */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE \
+ UINT32_C(0x2)
+ /* Lookup table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP \
+ (UINT32_C(0x0) << 1)
+ /* Action table */
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST \
+ HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION
+ /* Pool ID */
+ uint16_t pool_id;
+ /* Unused */
+ uint8_t unused[4];
+} __rte_packed;
+
+/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */
+struct hwrm_tfc_tbl_scope_pool_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*****************************
+ * hwrm_tfc_session_id_alloc *
+ *****************************/
+
+
+/*
+ * Allocate a TFC session. Requests the firmware to allocate a TFC
+ * session identifier and associate a forwarding function with the
+ * session. Though there's not an explicit matching free for a session
+ * id alloc, dis-associating the last fid from a session id (fid_cnt goes
+ * to 0), will result in this session id being freed automatically.
+ */
+/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */
+struct hwrm_tfc_session_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __rte_packed;
+
+/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_session_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_session_fid_add *
+ ****************************/
+
+
+/*
+ * Associate a TFC session id with a forwarding function. The target_fid
+ * will be associated with the passed in sid.
+ */
+/* hwrm_tfc_session_fid_add_input (size:192b/24B) */
+struct hwrm_tfc_session_fid_add_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[6];
+} __rte_packed;
+
+/* hwrm_tfc_session_fid_add_output (size:128b/16B) */
+struct hwrm_tfc_session_fid_add_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs that share this session. */
+ uint16_t fid_cnt;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_session_fid_rem *
+ ****************************/
+
+
+/*
+ * Dis-associate a TFC session from the target_fid.
+ * Though there's not an explicit matching free for a
+ * session id alloc, dis-associating the last fid from a session id
+ * (fid_cnt goes to 0), will result in this session id being freed
+ * automatically.
+ */
+/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */
+struct hwrm_tfc_session_fid_rem_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware.
+ */
+ uint16_t sid;
+ /* Unused field */
+ uint8_t unused0[6];
+} __rte_packed;
+
+/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */
+struct hwrm_tfc_session_fid_rem_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The number of FIDs that share this session. */
+ uint16_t fid_cnt;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_ident_alloc *
+ ************************/
+
+
+/*
+ * Allocate a TFC identifier. Requests the firmware to
+ * allocate a TFC identifier. The session id and track_type are passed
+ * in. The tracking_id is either the sid or target_fid depends on the
+ * track_type. The resource subtype is passed in, an id corresponding
+ * to all these is allocated and returned in the HWRM response.
+ */
+/* hwrm_tfc_ident_alloc_input (size:192b/24B) */
+struct hwrm_tfc_ident_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware. Will be used to track this identifier.
+ */
+ uint16_t sid;
+ /* Control flags. Direction. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking tag to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused field */
+ uint8_t unused0[3];
+} __rte_packed;
+
+/* hwrm_tfc_ident_alloc_output (size:128b/16B) */
+struct hwrm_tfc_ident_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Resource identifier allocated by the firmware using
+ * parameters above.
+ */
+ uint16_t ident_id;
+ /* Unused field */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_tfc_ident_free *
+ ***********************/
+
+
+/*
+ * Requests the firmware to free a TFC resource identifier.
+ * A resource subtype and session id are passed in.
+ * An identifier (previously allocated) corresponding to all these is
+ * freed, only after various sanity checks are completed.
+ */
+/* hwrm_tfc_ident_free_input (size:192b/24B) */
+struct hwrm_tfc_ident_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session identifier for the session created by the
+ * firmware. Will be used to validate this request.
+ */
+ uint16_t sid;
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Control flags. Direction. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX
+ /* The resource identifier to be freed */
+ uint16_t ident_id;
+ /* Reserved */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_ident_free_output (size:128b/16B) */
+struct hwrm_tfc_ident_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Reserved */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**************************
+ * hwrm_tfc_idx_tbl_alloc *
+ **************************/
+
+
+/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */
+struct hwrm_tfc_idx_tbl_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Reserved */
+ uint8_t unused0[3];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/******************************
+ * hwrm_tfc_idx_tbl_alloc_set *
+ ******************************/
+
+
+/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */
+struct hwrm_tfc_idx_tbl_alloc_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX
+ /*
+ * Indicate device data is being sent via DMA, the device
+ * data packing does not change.
+ */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Reserved */
+ uint8_t unused0;
+ /* The size of the index table entry in bytes. */
+ uint16_t data_size;
+ /* The location of the dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[104];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_alloc_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_idx_tbl_set *
+ ************************/
+
+
+/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */
+struct hwrm_tfc_idx_tbl_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX
+ /*
+ * Indicate device data is being sent via DMA, the device
+ * data packing does not change.
+ */
+ #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /*
+ * Index table index returned during alloc by the
+ * firmware.
+ */
+ uint16_t idx_tbl_id;
+ /* The size of the index table entry in bytes. */
+ uint16_t data_size;
+ /* The location of the dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[104];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/************************
+ * hwrm_tfc_idx_tbl_get *
+ ************************/
+
+
+/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */
+struct hwrm_tfc_idx_tbl_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR \
+ UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX \
+ UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX \
+ UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * When set use the special access register access to clear
+ * the table entry on read.
+ */
+ #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ \
+ UINT32_C(0x2)
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /*
+ * Index table index returned during alloc by the
+ * firmware.
+ */
+ uint16_t idx_tbl_id;
+ /* The size of the index table entry buffer in bytes. */
+ uint16_t buffer_size;
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of the index table buffer returned in device size bytes. */
+ uint16_t data_size;
+ /* unused */
+ uint8_t unused1[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*************************
+ * hwrm_tfc_idx_tbl_free *
+ *************************/
+
+
+/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */
+struct hwrm_tfc_idx_tbl_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX
+ /*
+ * CFA resource subtype. For definitions, please see
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Index table id to be freed by the firmware. */
+ uint16_t idx_tbl_id;
+ /* Reserved */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */
+struct hwrm_tfc_idx_tbl_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Reserved */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* TruFlow resources request for a global id. */
+/* tfc_global_id_hwrm_req (size:64b/8B) */
+struct tfc_global_id_hwrm_req {
+ /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */
+ uint16_t rtype;
+ /* Indicates the flow direction in type of cfa_dir. */
+ uint16_t dir;
+ /* Subtype of the resource type. */
+ uint16_t subtype;
+ /* Number of the type of resources. */
+ uint16_t cnt;
+} __rte_packed;
+
+/* The reserved resources for the global id. */
+/* tfc_global_id_hwrm_rsp (size:64b/8B) */
+struct tfc_global_id_hwrm_rsp {
+ /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */
+ uint16_t rtype;
+ /* Indicates the flow direction in type of cfa_dir. */
+ uint16_t dir;
+ /* Subtype of the resource type. */
+ uint16_t subtype;
+ /* The global id that the resources reserved for. */
+ uint16_t id;
+} __rte_packed;
+
+/****************************
+ * hwrm_tfc_global_id_alloc *
+ ****************************/
+
+
+/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */
+struct hwrm_tfc_global_id_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
+ uint16_t sid;
+ /* Global domain id. */
+ uint16_t global_id;
+ /*
+ * Defines the array size of the provided req_addr and
+ * resv_addr array buffers. Should be set to the number of
+ * request entries.
+ */
+ uint16_t req_cnt;
+ /* unused. */
+ uint8_t unused0[2];
+ /*
+ * This is the DMA address for the request input data array
+ * buffer. Array is of tfc_global_id_hwrm_req type. Size of the
+ * array buffer is provided by the 'req_cnt' field in this
+ * message.
+ */
+ uint64_t req_addr;
+ /*
+ * This is the DMA address for the resc output data array
+ * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array
+ * buffer is provided by the 'req_cnt' field in this
+ * message.
+ */
+ uint64_t resc_addr;
+} __rte_packed;
+
+/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */
+struct hwrm_tfc_global_id_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Size of the returned hwrm_tfc_global_id_req data array. The value
+ * cannot exceed the req_cnt defined by the input msg. The data
+ * array is returned using the resv_addr specified DMA
+ * address also provided by the input msg.
+ */
+ uint16_t rsp_cnt;
+ /* Non-zero if this is the first allocation for the global ID. */
+ uint8_t first;
+ /* unused. */
+ uint8_t unused0[4];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_tfc_tcam_set *
+ *********************/
+
+
+/* hwrm_tfc_tcam_set_input (size:1088b/136B) */
+struct hwrm_tfc_tcam_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Number of bytes in the TCAM result. */
+ uint16_t result_size;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate device data is being sent via DMA. */
+ #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /* unused. */
+ uint8_t unused0[6];
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+ /*
+ * TCAM key located at offset 0, mask located at mask_offset
+ * and result at result_offset for the device.
+ */
+ uint8_t dev_data[96];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_set_output (size:128b/16B) */
+struct hwrm_tfc_tcam_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* unused. */
+ uint8_t unused0[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/*********************
+ * hwrm_tfc_tcam_get *
+ *********************/
+
+
+/* hwrm_tfc_tcam_get_input (size:192b/24B) */
+struct hwrm_tfc_tcam_get_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX
+ /*
+ * Subtype of TCAM resource See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
+ */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* unused. */
+ uint8_t unused0[2];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_get_output (size:2368b/296B) */
+struct hwrm_tfc_tcam_get_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Number of bytes in the TCAM result. */
+ uint16_t result_size;
+ /* unused. */
+ uint8_t unused0[4];
+ /*
+ * TCAM key located at offset 0, mask located at key_size
+ * and result at 2 * key_size for the device.
+ */
+ uint8_t dev_data[272];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the
+ * output is completely written to RAM. This field should be
+ * read as '1' to indicate that the output has been
+ * completely written. When writing a command completion or
+ * response to an internal processor, the order of writes has
+ * to be such that this field is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***********************
+ * hwrm_tfc_tcam_alloc *
+ ***********************/
+
+
+/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */
+struct hwrm_tfc_tcam_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* Entry priority. */
+ uint16_t priority;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused. */
+ uint8_t unused0[7];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */
+struct hwrm_tfc_tcam_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Index table entry allocated by the firmware using the
+ * parameters above.
+ */
+ uint16_t idx;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/***************************
+ * hwrm_tfc_tcam_alloc_set *
+ ***************************/
+
+
+/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */
+struct hwrm_tfc_tcam_alloc_set_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Control flags. */
+ uint8_t flags;
+ /* Indicates the flow direction. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ /* If this bit is set to 1, then it indicates tx flow. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX
+ /* Indicate device data is being sent via DMA. */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
+ /*
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
+ */
+ uint8_t subtype;
+ /*
+ * Unique session id for the session created by the
+ * firmware. Will be used to track this index table entry
+ * only if track type is track_type_sid.
+ */
+ uint16_t sid;
+ /* Number of bytes in the TCAM key. */
+ uint16_t key_size;
+ /* The size of the TCAM table entry in bytes. */
+ uint16_t result_size;
+ /* Entry priority. */
+ uint16_t priority;
+ /* Describes the type of tracking id to be used */
+ uint8_t track_type;
+ /* Invalid track type */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \
+ UINT32_C(0x0)
+ /* Tracked by session id */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \
+ UINT32_C(0x1)
+ /* Tracked by function id */
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \
+ UINT32_C(0x2)
+ #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST \
+ HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID
+ /* Unused */
+ uint8_t unused[5];
+ /* The location of the response dma buffer */
+ uint64_t dma_addr;
+ /*
+ * Index table data located at offset 0. If dma bit is set,
+ * then this field contains the DMA buffer pointer.
+ */
+ uint8_t dev_data[96];
+} __rte_packed;
+
+/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */
+struct hwrm_tfc_tcam_alloc_set_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Reserved */
+ uint8_t unused0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_tfc_tcam_free *
+ **********************/
+
+
+/* hwrm_tfc_tcam_free_input (size:192b/24B) */
+struct hwrm_tfc_tcam_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
/* Control flags. */
- uint16_t flags;
+ uint8_t flags;
/* Indicates the flow direction. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
/* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
/* If this bit is set to 1, then it indicates tx flow. */
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
- #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
- /* unused. */
- uint8_t unused0[2];
- /*
- * Type of the resource, defined globally in the
- * hwrm_tf_resc_type enum.
- */
- uint32_t type;
- /* Index of the type to set. */
- uint32_t index;
- /* Size of the data to set. */
- uint16_t size;
- /* unused */
- uint8_t unused1[6];
- /* Data to be set. */
- uint8_t data[88];
-} __rte_packed;
-
-/* hwrm_tf_if_tbl_set_output (size:128b/16B) */
-struct hwrm_tf_if_tbl_set_output {
- /* The specific error status for the command. */
- uint16_t error_code;
- /* The HWRM command request type. */
- uint16_t req_type;
- /* The sequence ID from the original command. */
- uint16_t seq_id;
- /* The length of the response data in number of bytes. */
- uint16_t resp_len;
- /* unused. */
- uint8_t unused0[7];
- /*
- * This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal
- * processor, the order of writes has to be such that this field
- * is written last.
- */
- uint8_t valid;
-} __rte_packed;
-
-/*****************************
- * hwrm_tf_tbl_type_bulk_get *
- *****************************/
-
-
-/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
-struct hwrm_tf_tbl_type_bulk_get_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
+ #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
+ HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * Subtype of TCAM resource. See
+ * cfa_v3/include/cfa_resources.h.
*/
- uint16_t cmpl_ring;
+ uint8_t subtype;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Session id associated with the firmware. Will be used
+ * for validation if the track type matches.
*/
- uint16_t seq_id;
- /*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
- * * 0xFFFD - Reserved for user-space HWRM interface
- * * 0xFFFF - HWRM
- */
- uint16_t target_id;
- /*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
- uint32_t fw_session_id;
- /* Control flags. */
- uint16_t flags;
- /* Indicates the flow direction. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \
- UINT32_C(0x1)
- /* If this bit set to 0, then it indicates rx flow. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \
- UINT32_C(0x0)
- /* If this bit is set to 1, then it indicates tx flow. */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \
- UINT32_C(0x1)
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
- HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
- /*
- * When set use the special access register access to clear
- * the table entries on read.
- */
- #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \
- UINT32_C(0x2)
- /* unused. */
+ uint16_t sid;
+ /* Logical TCAM ID. */
+ uint16_t tcam_id;
+ /* Reserved */
uint8_t unused0[2];
- /*
- * Type of the resource, defined globally in the
- * hwrm_tf_resc_type enum.
- */
- uint32_t type;
- /* Starting index of the type to retrieve. */
- uint32_t start_index;
- /* Number of entries to retrieve. */
- uint32_t num_entries;
- /* Number of entries to retrieve. */
- uint32_t unused1;
- /* Host memory where data will be stored. */
- uint64_t host_addr;
} __rte_packed;
-/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
-struct hwrm_tf_tbl_type_bulk_get_output {
+/* hwrm_tfc_tcam_free_output (size:128b/16B) */
+struct hwrm_tfc_tcam_free_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -52433,12 +56664,8 @@ struct hwrm_tf_tbl_type_bulk_get_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Response code. */
- uint32_t resp_code;
- /* Response size. */
- uint16_t size;
- /* unused */
- uint8_t unused0;
+ /* Reserved */
+ uint8_t unused0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52505,8 +56732,20 @@ struct hwrm_tunnel_dst_port_query_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0[7];
} __rte_packed;
@@ -52538,7 +56777,38 @@ struct hwrm_tunnel_dst_port_query_output {
* configured.
*/
uint16_t tunnel_dst_port_val;
- uint8_t unused_0[3];
+ /*
+ * This field represents the UPAR usage status.
+ * Available UPARs on wh+ are UPAR0 and UPAR1
+ * Available UPARs on Thor are UPAR0 to UPAR3
+ * Available UPARs on Thor2 are UPAR0 to UPAR7
+ */
+ uint8_t upar_in_use;
+ /* This bit will be '1' when UPAR0 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 \
+ UINT32_C(0x1)
+ /* This bit will be '1' when UPAR1 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 \
+ UINT32_C(0x2)
+ /* This bit will be '1' when UPAR2 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 \
+ UINT32_C(0x4)
+ /* This bit will be '1' when UPAR3 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 \
+ UINT32_C(0x8)
+ /* This bit will be '1' when UPAR4 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 \
+ UINT32_C(0x10)
+ /* This bit will be '1' when UPAR5 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 \
+ UINT32_C(0x20)
+ /* This bit will be '1' when UPAR6 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 \
+ UINT32_C(0x40)
+ /* This bit will be '1' when UPAR7 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \
+ UINT32_C(0x80)
+ uint8_t unused_0[2];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52604,8 +56874,20 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -52636,7 +56918,51 @@ struct hwrm_tunnel_dst_port_alloc_output {
* types that has l4 destination port parameters.
*/
uint16_t tunnel_dst_port_id;
- uint8_t unused_0[5];
+ /* Error information */
+ uint8_t error_info;
+ /* No error */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS \
+ UINT32_C(0x0)
+ /* Tunnel port is already allocated */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED \
+ UINT32_C(0x1)
+ /* Out of resources error */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \
+ UINT32_C(0x2)
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \
+ HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE
+ /*
+ * This field represents the UPAR usage status.
+ * Available UPARs on wh+ are UPAR0 and UPAR1
+ * Available UPARs on Thor are UPAR0 to UPAR3
+ * Available UPARs on Thor2 are UPAR0 to UPAR7
+ */
+ uint8_t upar_in_use;
+ /* This bit will be '1' when UPAR0 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 \
+ UINT32_C(0x1)
+ /* This bit will be '1' when UPAR1 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 \
+ UINT32_C(0x2)
+ /* This bit will be '1' when UPAR2 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 \
+ UINT32_C(0x4)
+ /* This bit will be '1' when UPAR3 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 \
+ UINT32_C(0x8)
+ /* This bit will be '1' when UPAR4 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 \
+ UINT32_C(0x10)
+ /* This bit will be '1' when UPAR5 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 \
+ UINT32_C(0x20)
+ /* This bit will be '1' when UPAR6 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 \
+ UINT32_C(0x40)
+ /* This bit will be '1' when UPAR7 is IN_USE */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 \
+ UINT32_C(0x80)
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -52702,8 +57028,20 @@ struct hwrm_tunnel_dst_port_free_input {
/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
UINT32_C(0xc)
+ /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE \
+ UINT32_C(0xd)
+ /* Enhanced Common Packet Radio Interface (eCPRI) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI \
+ UINT32_C(0xe)
+ /* IPv6 Segment Routing (SRv6) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 \
+ UINT32_C(0xf)
+ /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \
+ UINT32_C(0x10)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -52723,7 +57061,20 @@ struct hwrm_tunnel_dst_port_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_1[7];
+ /* Error information */
+ uint8_t error_info;
+ /* No error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS \
+ UINT32_C(0x0)
+ /* Not owner error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER \
+ UINT32_C(0x1)
+ /* Not allocated error */
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED \
+ UINT32_C(0x2)
+ #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST \
+ HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED
+ uint8_t unused_1[6];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -53534,6 +57885,185 @@ struct pcie_ctx_hw_stats {
uint64_t pcie_recovery_histogram;
} __rte_packed;
+/****************************
+ * hwrm_stat_generic_qstats *
+ ****************************/
+
+
+/* hwrm_stat_generic_qstats_input (size:256b/32B) */
+struct hwrm_stat_generic_qstats_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * The size of the generic statistics buffer passed in the
+ * generic_stat_host_addr in bytes.
+ * Firmware will not exceed this size when it DMAs the
+ * statistics structure to the host. The actual DMA size
+ * will be returned in the response.
+ */
+ uint16_t generic_stat_size;
+ uint8_t flags;
+ /*
+ * The bit should be set to 1 when request is for the counter mask
+ * representing the width of each of the stats counters, rather
+ * than counters themselves.
+ */
+ #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK \
+ UINT32_C(0x1)
+ uint8_t unused_0[5];
+ /*
+ * This is the host address where
+ * generic statistics will be stored
+ */
+ uint64_t generic_stat_host_addr;
+} __rte_packed;
+
+/* hwrm_stat_generic_qstats_output (size:128b/16B) */
+struct hwrm_stat_generic_qstats_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* The size of Generic Statistics block in bytes. */
+ uint16_t generic_stat_size;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field is
+ * written last.
+ */
+ uint8_t valid;
+} __rte_packed;
+
+/* Generic Statistic Format */
+/* generic_sw_hw_stats (size:1408b/176B) */
+struct generic_sw_hw_stats {
+ /*
+ * This is the number of TLP bytes that have been transmitted for
+ * the caller PF.
+ */
+ uint64_t pcie_statistics_tx_tlp;
+ /*
+ * This is the number of TLP bytes that have been received
+ * for the caller PF.
+ */
+ uint64_t pcie_statistics_rx_tlp;
+ /* Posted Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_posted;
+ /* Non-posted Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_nonposted;
+ /* Completion Header Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_hdr_cmpl;
+ /* Posted Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_posted;
+ /* Non-Posted Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_nonposted;
+ /* Completion Data Flow Control credits available for the caller PF. */
+ uint64_t pcie_credit_fc_data_cmpl;
+ /*
+ * Available Non-posted credit for target flow control reads or
+ * config for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_nonposted;
+ /*
+ * Available posted data credit for target flow control writes
+ * for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_data_posted;
+ /*
+ * Available posted header credit for target flow control writes
+ * for the caller PF.
+ */
+ uint64_t pcie_credit_fc_tgt_hdr_posted;
+ /* Available completion flow control header credits for the caller PF. */
+ uint64_t pcie_credit_fc_cmpl_hdr_posted;
+ /* Available completion flow control data credits. */
+ uint64_t pcie_credit_fc_cmpl_data_posted;
+ /*
+ * Displays Time information of the longest completon time from any of
+ * the 4 tags for the caller PF. The unit of time recorded is in
+ * microseconds.
+ */
+ uint64_t pcie_cmpl_longest;
+ /*
+ * Displays Time information of the shortest completon time from any of
+ * the 4 tags for the caller PF. The unit of time recorded is in
+ * microseconds.
+ */
+ uint64_t pcie_cmpl_shortest;
+ /*
+ * This field contains the total number of CFCQ 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcq;
+ /*
+ * This field contains the total number of CFCS 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcs;
+ /*
+ * This field contains the total number of CFCC 'misses' observed for
+ * all the PF's.
+ */
+ uint64_t cache_miss_count_cfcc;
+ /*
+ * This field contains the total number of CFCM 'misses' observed
+ * for all the PF's.
+ */
+ uint64_t cache_miss_count_cfcm;
+ /*
+ * Total number of Doorbell messages dropped from the DB FIFO.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_dbs_dropped;
+ /*
+ * Total number of doorbell drops serviced.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_drops_serviced;
+ /*
+ * Total number of dropped doorbells recovered.
+ * This counter is only applicable for devices that support
+ * the hardware based doorbell drop recovery feature.
+ */
+ uint64_t hw_db_recov_dbs_recovered;
+} __rte_packed;
+
/**********************
* hwrm_exec_fwd_resp *
**********************/
@@ -55174,8 +59704,11 @@ struct hwrm_nvm_install_update_cmd_err {
/* Firmware update failed due to Anti-rollback. */
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \
UINT32_C(0x3)
+ /* Firmware update does not support voltage regulators on the device. */
+ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT \
+ UINT32_C(0x4)
#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
- HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK
+ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT
uint8_t unused_0[7];
} __rte_packed;
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 03/11] net/bnxt: update copyright date and cleanup whitespace
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 01/11] net/bnxt: remove deprecated features Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 04/11] net/bnxt: update Truflow core Ajit Khaparde
` (7 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Randy Schacher, Kishore Padmanabha
[-- Attachment #1: Type: text/plain, Size: 46733 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Update the Copyright to 2023
Clean up extra blank lines
Clean up other whitespace issues
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_cpr.c | 2 +-
drivers/net/bnxt/bnxt_cpr.h | 2 +-
drivers/net/bnxt/bnxt_filter.c | 2 +-
drivers/net/bnxt/bnxt_irq.c | 2 +-
drivers/net/bnxt/bnxt_irq.h | 2 +-
drivers/net/bnxt/bnxt_nvm_defs.h | 2 +-
drivers/net/bnxt/bnxt_reps.h | 2 +-
drivers/net/bnxt/bnxt_ring.h | 2 +-
drivers/net/bnxt/bnxt_rxq.h | 2 +-
drivers/net/bnxt/bnxt_rxr.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +-
drivers/net/bnxt/bnxt_stats.c | 2 +-
drivers/net/bnxt/bnxt_stats.h | 2 +-
drivers/net/bnxt/bnxt_txq.h | 2 +-
drivers/net/bnxt/bnxt_util.c | 2 +-
drivers/net/bnxt/bnxt_util.h | 2 +-
drivers/net/bnxt/meson.build | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.c | 2 +-
drivers/net/bnxt/rte_pmd_bnxt.h | 2 +-
drivers/net/bnxt/tf_core/bitalloc.c | 3 +--
drivers/net/bnxt/tf_core/bitalloc.h | 3 +--
drivers/net/bnxt/tf_core/cfa_resource_types.h | 3 +--
drivers/net/bnxt/tf_core/dpool.c | 3 ++-
drivers/net/bnxt/tf_core/dpool.h | 3 +--
drivers/net/bnxt/tf_core/ll.c | 2 +-
drivers/net/bnxt/tf_core/ll.h | 2 +-
drivers/net/bnxt/tf_core/lookup3.h | 1 -
drivers/net/bnxt/tf_core/rand.c | 2 +-
drivers/net/bnxt/tf_core/rand.h | 3 +--
drivers/net/bnxt/tf_core/stack.c | 2 +-
drivers/net/bnxt/tf_core/stack.h | 3 +--
drivers/net/bnxt/tf_core/tf_common.h | 3 +--
drivers/net/bnxt/tf_core/tf_core.h | 1 -
drivers/net/bnxt/tf_core/tf_device.h | 1 -
drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +--
drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +-
drivers/net/bnxt/tf_core/tf_em.h | 3 +--
drivers/net/bnxt/tf_core/tf_em_common.c | 8 +-------
drivers/net/bnxt/tf_core/tf_em_common.h | 4 +---
drivers/net/bnxt/tf_core/tf_em_hash_internal.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_host.c | 3 +--
drivers/net/bnxt/tf_core/tf_em_internal.c | 3 ++-
drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +---
drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +-
drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +--
drivers/net/bnxt/tf_core/tf_hash.c | 2 +-
drivers/net/bnxt/tf_core/tf_hash.h | 3 +--
drivers/net/bnxt/tf_core/tf_identifier.c | 2 +-
drivers/net/bnxt/tf_core/tf_identifier.h | 3 +--
drivers/net/bnxt/tf_core/tf_if_tbl.h | 3 +--
drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +--
drivers/net/bnxt/tf_core/tf_project.h | 3 +--
drivers/net/bnxt/tf_core/tf_resources.h | 3 +--
drivers/net/bnxt/tf_core/tf_rm.h | 6 +-----
drivers/net/bnxt/tf_core/tf_session.h | 1 -
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 1 -
drivers/net/bnxt/tf_core/tf_tbl.h | 4 +---
drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +-----
drivers/net/bnxt/tf_core/tf_tcam.h | 3 +--
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 1 -
drivers/net/bnxt/tf_core/tf_util.c | 3 +--
drivers/net/bnxt/tf_core/tf_util.h | 3 +--
drivers/net/bnxt/tf_core/tfp.c | 2 +-
drivers/net/bnxt/tf_core/tfp.h | 4 +---
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +--
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 -
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 -
drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +--
drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 3 +--
87 files changed, 73 insertions(+), 135 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c
index 5bb376d4d5..0733cf4df2 100644
--- a/drivers/net/bnxt/bnxt_cpr.c
+++ b/drivers/net/bnxt/bnxt_cpr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index dab6bed2ae..2de154322d 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c
index b0c3bbd1b2..ff563f08bb 100644
--- a/drivers/net/bnxt/bnxt_filter.c
+++ b/drivers/net/bnxt/bnxt_filter.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_irq.c b/drivers/net/bnxt/bnxt_irq.c
index 508abfc844..71d1565e08 100644
--- a/drivers/net/bnxt/bnxt_irq.c
+++ b/drivers/net/bnxt/bnxt_irq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h
index 53d9198858..e498578968 100644
--- a/drivers/net/bnxt/bnxt_irq.h
+++ b/drivers/net/bnxt/bnxt_irq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h
index bb45d7e472..f5ac4e8c84 100644
--- a/drivers/net/bnxt/bnxt_nvm_defs.h
+++ b/drivers/net/bnxt/bnxt_nvm_defs.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h
index 01e57ee5b5..3f2db9d1ae 100644
--- a/drivers/net/bnxt/bnxt_reps.h
+++ b/drivers/net/bnxt/bnxt_reps.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index ef9586e64e..3d747aba54 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index a97037c6e0..b9908be5f4 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index a84f016609..e132166a18 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
index 34bd22edf0..d4e8e8eb87 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_avx2.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_common.h b/drivers/net/bnxt/bnxt_rxtx_vec_common.h
index 0627fd212d..2294f0aa3c 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_common.h
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2020-2021 Broadcom
+ * Copyright(c) 2020-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
index 6a4ece681b..aa1b1ab8bb 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
index ffd560166c..2ad8591b90 100644
--- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2019-2021 Broadcom All rights reserved. */
+/* Copyright(c) 2019-2023 Broadcom All rights reserved. */
#include <inttypes.h>
#include <stdbool.h>
diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c
index 72169e8b35..0e25207fc3 100644
--- a/drivers/net/bnxt/bnxt_stats.c
+++ b/drivers/net/bnxt/bnxt_stats.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_stats.h b/drivers/net/bnxt/bnxt_stats.h
index 1ca9b9c594..e46c05eed3 100644
--- a/drivers/net/bnxt/bnxt_stats.h
+++ b/drivers/net/bnxt/bnxt_stats.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txq.h b/drivers/net/bnxt/bnxt_txq.h
index f3a03812ad..3a483ad5c3 100644
--- a/drivers/net/bnxt/bnxt_txq.h
+++ b/drivers/net/bnxt/bnxt_txq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_util.c b/drivers/net/bnxt/bnxt_util.c
index 3167894789..47dd5fa6ff 100644
--- a/drivers/net/bnxt/bnxt_util.c
+++ b/drivers/net/bnxt/bnxt_util.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h
index b243c21ec2..3437dc75ae 100644
--- a/drivers/net/bnxt/bnxt_util.h
+++ b/drivers/net/bnxt/bnxt_util.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 96fa06a358..ead03a5ea3 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2020 Broadcom
+# Copyright(c) 2023 Broadcom
if is_windows
build = false
diff --git a/drivers/net/bnxt/rte_pmd_bnxt.c b/drivers/net/bnxt/rte_pmd_bnxt.c
index ffa1114046..964a5aeb05 100644
--- a/drivers/net/bnxt/rte_pmd_bnxt.c
+++ b/drivers/net/bnxt/rte_pmd_bnxt.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Broadcom
+ * Copyright(c) 2017-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/rte_pmd_bnxt.h b/drivers/net/bnxt/rte_pmd_bnxt.h
index 174c18a0f3..2077026903 100644
--- a/drivers/net/bnxt/rte_pmd_bnxt.h
+++ b/drivers/net/bnxt/rte_pmd_bnxt.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Broadcom
+ * Copyright(c) 2017-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/bitalloc.c b/drivers/net/bnxt/tf_core/bitalloc.c
index e253cfc3a6..136263b6a4 100644
--- a/drivers/net/bnxt/tf_core/bitalloc.c
+++ b/drivers/net/bnxt/tf_core/bitalloc.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -7,7 +7,6 @@
#define BITALLOC_MAX_LEVELS 6
-
/* Finds the last bit set plus 1, equivalent to gcc __builtin_fls */
static int
ba_fls(bitalloc_word_t v)
diff --git a/drivers/net/bnxt/tf_core/bitalloc.h b/drivers/net/bnxt/tf_core/bitalloc.h
index db8a09abdd..bf15cbc87b 100644
--- a/drivers/net/bnxt/tf_core/bitalloc.h
+++ b/drivers/net/bnxt/tf_core/bitalloc.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -121,5 +121,4 @@ int ba_free_count(struct bitalloc *pool);
* Returns the pool's in use count
*/
int ba_inuse_count(struct bitalloc *pool);
-
#endif /* _BITALLOC_H_ */
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 36a55d4e17..874d7b834f 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -256,5 +256,4 @@
/* Table Scope */
#define CFA_RESOURCE_TYPE_P4_TBL_SCOPE 0x22UL
#define CFA_RESOURCE_TYPE_P4_LAST CFA_RESOURCE_TYPE_P4_TBL_SCOPE
-
#endif /* _CFA_RESOURCE_TYPES_H_ */
diff --git a/drivers/net/bnxt/tf_core/dpool.c b/drivers/net/bnxt/tf_core/dpool.c
index 5c03f775a5..f60c04e949 100644
--- a/drivers/net/bnxt/tf_core/dpool.c
+++ b/drivers/net/bnxt/tf_core/dpool.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <stdio.h>
@@ -55,6 +55,7 @@ static int dpool_move(struct dpool *dpool,
{
uint32_t size;
uint32_t i;
+
if (DP_IS_FREE(dpool->entry[dst_index].flags)) {
size = DP_FLAGS_SIZE(dpool->entry[src_index].flags);
diff --git a/drivers/net/bnxt/tf_core/dpool.h b/drivers/net/bnxt/tf_core/dpool.h
index fb79c7be4b..2e64916bf6 100644
--- a/drivers/net/bnxt/tf_core/dpool.h
+++ b/drivers/net/bnxt/tf_core/dpool.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -305,5 +305,4 @@ void dpool_dump(struct dpool *dpool);
int dpool_defrag(struct dpool *dpool,
uint32_t entry_size,
uint8_t defrag);
-
#endif /* _DPOOL_H_ */
diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c
index f2bdff6b9e..75b096aa08 100644
--- a/drivers/net/bnxt/tf_core/ll.c
+++ b/drivers/net/bnxt/tf_core/ll.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h
index 9cf8f64ec2..89271b7243 100644
--- a/drivers/net/bnxt/tf_core/ll.h
+++ b/drivers/net/bnxt/tf_core/ll.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/lookup3.h b/drivers/net/bnxt/tf_core/lookup3.h
index 743c4d9c4f..a937de4a16 100644
--- a/drivers/net/bnxt/tf_core/lookup3.h
+++ b/drivers/net/bnxt/tf_core/lookup3.h
@@ -157,5 +157,4 @@ static inline uint32_t hashword(const uint32_t *k,
/*------------------------------------------------- report the result */
return c;
}
-
#endif /* _LOOKUP3_H_ */
diff --git a/drivers/net/bnxt/tf_core/rand.c b/drivers/net/bnxt/tf_core/rand.c
index d419d7257b..07d4aff750 100644
--- a/drivers/net/bnxt/tf_core/rand.c
+++ b/drivers/net/bnxt/tf_core/rand.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/rand.h b/drivers/net/bnxt/tf_core/rand.h
index 80b2ab3ecd..656bd58868 100644
--- a/drivers/net/bnxt/tf_core/rand.h
+++ b/drivers/net/bnxt/tf_core/rand.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -32,5 +32,4 @@ uint32_t rand32(void);
*
*/
void rand_init(void);
-
#endif /* __RAND_H__ */
diff --git a/drivers/net/bnxt/tf_core/stack.c b/drivers/net/bnxt/tf_core/stack.c
index db79461db9..d2e200b4f4 100644
--- a/drivers/net/bnxt/tf_core/stack.c
+++ b/drivers/net/bnxt/tf_core/stack.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/stack.h b/drivers/net/bnxt/tf_core/stack.h
index 358233279c..f9a748574c 100644
--- a/drivers/net/bnxt/tf_core/stack.h
+++ b/drivers/net/bnxt/tf_core/stack.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#ifndef _STACK_H_
@@ -113,5 +113,4 @@ int stack_pop(struct stack *st, uint32_t *x);
* none
*/
void stack_dump(struct stack *st);
-
#endif /* _STACK_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_common.h b/drivers/net/bnxt/tf_core/tf_common.h
index abdd390b4f..0bfb7f1f33 100644
--- a/drivers/net/bnxt/tf_core/tf_common.h
+++ b/drivers/net/bnxt/tf_core/tf_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2020-2021 Broadcom
+ * Copyright(c) 2020-2023 Broadcom
* All rights reserved.
*/
@@ -39,5 +39,4 @@
return -EINVAL; \
} \
} while (0)
-
#endif /* _TF_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 814eff68da..f5fe0a9098 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -2481,5 +2481,4 @@ struct tf_get_sram_policy_parms {
*/
int tf_get_sram_policy(struct tf *tfp,
struct tf_get_sram_policy_parms *parms);
-
#endif /* _TF_CORE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index bc6de60423..5a42180719 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -1142,5 +1142,4 @@ extern const struct tf_dev_ops tf_dev_ops_p58;
*/
extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1];
extern const struct tf_hcapi_resource_map tf_hcapi_res_map_p58[CFA_RESOURCE_TYPE_P58_LAST + 1];
-
#endif /* _TF_DEVICE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index 86de525995..20da2f97db 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -181,5 +181,4 @@ const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST
TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE
},
};
-
#endif /* _TF_DEVICE_P4_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 61c856b767..858d975f11 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 074c128651..97cdb48f14 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -8,7 +8,6 @@
#include "tf_core.h"
#include "tf_session.h"
-
#include "tf_em_common.h"
#include "hcapi_cfa_defs.h"
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 3bdfc14e05..b56b7cc188 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -9,7 +9,6 @@
#include <rte_common.h>
#include <rte_errno.h>
#include <rte_log.h>
-
#include "tf_core.h"
#include "tf_util.h"
#include "tf_common.h"
@@ -20,10 +19,8 @@
#include "tf_device.h"
#include "tf_ext_flow_handle.h"
#include "hcapi_cfa.h"
-
#include "bnxt.h"
-
/** Invalid table scope id */
#define TF_TBL_SCOPE_INVALID 0xffffffff
@@ -285,7 +282,6 @@ tf_em_create_key_entry(struct cfa_p4_eem_entry_hdr *result,
memcpy(key_entry->key, in_key, TF_P4_HW_EM_KEY_MAX_SIZE + 4);
}
-
/**
* Return the number of page table pages needed to
* reference the given number of next level pages.
@@ -908,7 +904,6 @@ tf_em_delete_ext_entry(struct tf *tfp,
return tf_delete_eem_entry(tbl_scope_cb, parms);
}
-
int
tf_em_ext_common_bind(struct tf *tfp,
struct tf_em_cfg_parms *parms)
@@ -1204,7 +1199,6 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp,
gcfg_parms.config_mask = (uint8_t *)mask;
gcfg_parms.config_sz_in_bytes = sizeof(uint64_t);
-
rc = tf_msg_set_global_cfg(tfp, &gcfg_parms);
if (rc) {
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h
index 7f215adef2..0ae95f260a 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.h
+++ b/drivers/net/bnxt/tf_core/tf_em_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -178,7 +178,6 @@ int tf_em_validate_num_entries(struct tf_tbl_scope_cb *tbl_scope_cb,
int tf_em_size_table(struct hcapi_cfa_em_table *tbl,
uint32_t page_size);
-
/**
* Look up table scope control block using tbl_scope_id from
* tf_session
@@ -196,5 +195,4 @@ int tf_em_size_table(struct hcapi_cfa_em_table *tbl,
struct tf_tbl_scope_cb *
tf_em_ext_common_tbl_scope_find(struct tf *tfp,
uint32_t tbl_scope_id);
-
#endif /* _TF_EM_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
index 60273a798c..d72ac83295 100644
--- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index 869a78e904..9efffe4ee5 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -376,7 +376,6 @@ tf_em_ext_alloc(struct tf *tfp,
void *ext_ptr = NULL;
uint16_t pf;
-
rc = tf_session_get_session_internal(tfp, &tfs);
if (rc) {
TFP_DRV_LOG(ERR, "Failed to get tf_session, rc:%s\n",
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 67ba011eae..8ea5d93672 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -15,6 +15,7 @@
#include "tf_msg.h"
#include "tfp.h"
#include "tf_ext_flow_handle.h"
+
#include "bnxt.h"
#define TF_EM_DB_EM_REC 0
diff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
index bf6dbcd238..8f967c5c85 100644
--- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
+++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -184,6 +184,4 @@ do { \
type = (((gfid) & TF_HASH_TYPE_GFID_MASK) >> \
TF_HASH_TYPE_GFID_SFT); \
} while (0)
-
-
#endif /* _TF_EXT_FLOW_HANDLE_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.c b/drivers/net/bnxt/tf_core/tf_global_cfg.c
index d83e7db315..3a8030a2fb 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.c
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.h b/drivers/net/bnxt/tf_core/tf_global_cfg.h
index c14e5e9109..f57f3313da 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.h
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -146,5 +146,4 @@ int tf_global_cfg_set(struct tf *tfp,
*/
int tf_global_cfg_get(struct tf *tfp,
struct tf_global_cfg_parms *parms);
-
#endif /* TF_GLOBAL_CFG_H */
diff --git a/drivers/net/bnxt/tf_core/tf_hash.c b/drivers/net/bnxt/tf_core/tf_hash.c
index a722821f05..b402dc8a12 100644
--- a/drivers/net/bnxt/tf_core/tf_hash.c
+++ b/drivers/net/bnxt/tf_core/tf_hash.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_hash.h b/drivers/net/bnxt/tf_core/tf_hash.h
index d128269b54..0c082f5fd6 100644
--- a/drivers/net/bnxt/tf_core/tf_hash.h
+++ b/drivers/net/bnxt/tf_core/tf_hash.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -23,5 +23,4 @@ tf_hash_calc_crc32i(uint32_t init, uint8_t *buf, uint32_t len);
*/
uint32_t
tf_hash_calc_crc32(uint8_t *buf, uint32_t len);
-
#endif
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index 8131d8754d..1846675916 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.h b/drivers/net/bnxt/tf_core/tf_identifier.h
index 285ff11ce2..48ca63a58d 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.h
+++ b/drivers/net/bnxt/tf_core/tf_identifier.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -212,5 +212,4 @@ int tf_ident_search(struct tf *tfp,
*/
int tf_ident_get_resc_info(struct tf *tfp,
struct tf_identifier_resource_info *parms);
-
#endif /* _TF_IDENTIFIER_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.h b/drivers/net/bnxt/tf_core/tf_if_tbl.h
index bea2f07324..bb536c31d1 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -224,5 +224,4 @@ int tf_if_tbl_set(struct tf *tfp,
*/
int tf_if_tbl_get(struct tf *tfp,
struct tf_if_tbl_get_parms *parms);
-
#endif /* TF_IF_TBL_TYPE_H */
diff --git a/drivers/net/bnxt/tf_core/tf_msg_common.h b/drivers/net/bnxt/tf_core/tf_msg_common.h
index 49f334717d..949062a42f 100644
--- a/drivers/net/bnxt/tf_core/tf_msg_common.h
+++ b/drivers/net/bnxt/tf_core/tf_msg_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -40,5 +40,4 @@
parms.resp_size = 0; \
parms.resp_data = NULL; \
} while (0)
-
#endif /* _TF_MSG_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_project.h b/drivers/net/bnxt/tf_core/tf_project.h
index 57285508fb..6357760f16 100644
--- a/drivers/net/bnxt/tf_core/tf_project.h
+++ b/drivers/net/bnxt/tf_core/tf_project.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -20,5 +20,4 @@
#ifndef TF_SHARED
#define TF_SHARED 0
#endif
-
#endif /* _TF_PROJECT_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_resources.h b/drivers/net/bnxt/tf_core/tf_resources.h
index 2c1d738755..8c28d3dc68 100644
--- a/drivers/net/bnxt/tf_core/tf_resources.h
+++ b/drivers/net/bnxt/tf_core/tf_resources.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -7,5 +7,4 @@
#define _TF_RESOURCES_H_
#define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */
-
#endif /* _TF_RESOURCES_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h
index da7d0c7211..a4187891f4 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.h
+++ b/drivers/net/bnxt/tf_core/tf_rm.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -43,7 +43,6 @@ struct tf;
* support module, not called directly.
*/
-
/**
* RM Element configuration enumeration. Used by the Device to
* indicate how the RM elements the DB consists off, are to be
@@ -75,8 +74,6 @@ enum tf_rm_elem_cfg_type {
* HCAPI type. Child accesses the parent db.
*/
TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
-
-
TF_RM_TYPE_MAX
};
@@ -581,5 +578,4 @@ tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms);
*/
int
tf_rm_get_slices(struct tf_rm_get_slices_parms *parms);
-
#endif /* TF_RM_NEW_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index a6716dfff4..5a94b941fa 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -716,5 +716,4 @@ tf_session_set_if_tbl_db(struct tf *tfp,
int
tf_session_get_if_tbl_db(struct tf *tfp,
void **if_tbl_handle);
-
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
index eb2156456a..fc78426130 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -303,5 +303,4 @@ const char
*/
const char
*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id);
-
#endif /* _TF_SRAM_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 2483718e5d..dfa3bcaa14 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -15,7 +15,6 @@ struct tf;
* The Table module provides processing of Internal TF table types.
*/
-
/**
* Table configuration parameters
*/
@@ -327,5 +326,4 @@ int tf_tbl_bulk_get(struct tf *tfp,
int
tf_tbl_get_resc_info(struct tf *tfp,
struct tf_tbl_resource_info *tbl);
-
#endif /* TF_TBL_TYPE_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
index 32001e34a9..c109210ce9 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -9,12 +9,10 @@
#include "tf_core.h"
#include "stack.h"
-
/**
* The SRAM Table module provides processing of managed SRAM types.
*/
-
/**
* @page tblsram SRAM Table
*
@@ -99,7 +97,6 @@ int tf_tbl_sram_alloc(struct tf *tfp,
int tf_tbl_sram_free(struct tf *tfp,
struct tf_tbl_free_parms *parms);
-
/**
* Configures the requested element by sending a firmware request which
* then installs it into the device internal structures.
@@ -150,5 +147,4 @@ int tf_tbl_sram_get(struct tf *tfp,
*/
int tf_tbl_sram_bulk_get(struct tf *tfp,
struct tf_tbl_get_bulk_parms *parms);
-
#endif /* TF_TBL_SRAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h
index 0ed2250464..1807edd092 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -374,5 +374,4 @@ int tf_tcam_get(struct tf *tfp,
*/
int tf_tcam_get_resc_info(struct tf *tfp,
struct tf_tcam_resource_info *parms);
-
#endif /* _TF_TCAM_H */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
index 020763af6b..524631f262 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
@@ -179,5 +179,4 @@ int tf_tcam_shared_move_p58(struct tf *tfp,
*/
int tf_tcam_shared_clear(struct tf *tfp,
struct tf_clear_tcam_shared_entries_parms *parms);
-
#endif /* _TF_TCAM_SHARED_H */
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index 7d9de7c764..8ce8238b4a 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -1,10 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include "tf_util.h"
const char *
diff --git a/drivers/net/bnxt/tf_core/tf_util.h b/drivers/net/bnxt/tf_core/tf_util.h
index 854c51931a..f46480868b 100644
--- a/drivers/net/bnxt/tf_core/tf_util.h
+++ b/drivers/net/bnxt/tf_core/tf_util.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -93,5 +93,4 @@ const char *tf_module_subtype_2_str(enum tf_module_type module,
* Pointer to a char string holding the string for the EM type
*/
const char *tf_module_2_str(enum tf_module_type module);
-
#endif /* _TF_UTIL_H_ */
diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c
index a967a9ccf2..604141b689 100644
--- a/drivers/net/bnxt/tf_core/tfp.c
+++ b/drivers/net/bnxt/tf_core/tfp.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
* see the individual elements.
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h
index 5a99c7a06e..92f76004da 100644
--- a/drivers/net/bnxt/tf_core/tfp.h
+++ b/drivers/net/bnxt/tf_core/tfp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -185,7 +185,6 @@ void tfp_spinlock_unlock(struct tfp_spinlock_parms *slock);
*/
int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
-
/*
* @ref tfp_cpu_to_le_16
* @ref tfp_le_to_cpu_16
@@ -232,5 +231,4 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
*
*/
int tfp_get_pf(struct tf *tfp, uint16_t *pf);
-
#endif /* _TFP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index d006464a75..cd4cd8ac74 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -68,5 +68,4 @@ bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx);
int32_t
bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mark_tbl *mark_tbl);
-
#endif /* _BNXT_TF_COMMON_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index 229e21814b..d6d7a1f0af 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -25,5 +25,4 @@ uint16_t bnxt_pmd_get_phy_port_id(uint16_t port);
uint16_t bnxt_pmd_get_vport(uint16_t port);
enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port);
int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev);
-
#endif /* _BNXT_TF_PMD_ABSTRACT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 05a98b14e6..906d933af5 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -317,5 +317,4 @@ bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
-
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 9825ed2a27..9df5ae51a3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -184,5 +184,4 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
enum tf_dir dir,
uint32_t hw_cntr_id,
uint32_t pc_idx);
-
#endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 2b02836a40..ada34c0e6c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -410,5 +410,4 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
enum bnxt_ulp_shared_session shared);
-
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
index 84c83de35c..d746fbbd4e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
index 543ef79d30..d3f3840cbe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_hash.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -162,5 +162,4 @@ ulp_gen_hash_tbl_list_add(struct ulp_gen_hash_tbl *hash_tbl,
int32_t
ulp_gen_hash_tbl_list_del(struct ulp_gen_hash_tbl *hash_tbl,
struct ulp_gen_hash_entry_params *entry);
-
#endif /* _ULP_GEN_HASH_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
index f245825142..3060072967 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
@@ -167,5 +167,4 @@ int32_t
ulp_mapper_gen_tbl_hash_entry_add(struct ulp_mapper_gen_tbl_list *tbl_list,
struct ulp_gen_hash_entry_params *hash_entry,
struct ulp_mapper_gen_tbl_entry *gen_tbl_ent);
-
#endif /* _ULP_EN_TBL_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
index 793511564a..ded967a0af 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
@@ -63,5 +63,4 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx);
int32_t
ulp_ha_mgr_region_get(struct bnxt_ulp_context *ulp_ctx,
enum ulp_ha_mgr_region *region);
-
#endif /* _ULP_HA_MGR_H_*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 4d6ba0f73a..b7e6f3ada2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -133,5 +133,4 @@ ulp_mapper_get_shared_fid(struct bnxt_ulp_context *ulp,
uint32_t id,
uint16_t key,
uint32_t *fid);
-
#endif /* _ULP_MAPPER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 9dffaef73b..1cfb21782c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
index d9d82d4644..2a1f3ad615 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -112,5 +112,4 @@ int32_t
ulp_mark_db_mark_del(struct bnxt_ulp_context *ctxt,
uint32_t mark_flag,
uint32_t gfid);
-
#endif /* _ULP_MARK_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
index dc2487889c..47a9e8e0eb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -27,5 +27,4 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
int32_t
ulp_matcher_action_match(struct ulp_rte_parser_params *params,
uint32_t *act_id);
-
#endif /* ULP_MATCHER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index b112f1a216..f575a3c2e2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -326,5 +326,4 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
int32_t
ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint16_t *phy_port);
-
#endif /* _ULP_PORT_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index f59b10e88b..b0b2b4f33f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -259,5 +259,4 @@ ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
-
#endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 7d1bc06a3e..3dcc6dbc0c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -441,5 +441,4 @@ extern struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[];
* that could be reused by other templates.
*/
extern uint32_t ulp_glb_template_tbl[];
-
#endif /* _ULP_TEMPLATE_STRUCT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index 7ce6740633..3be3475a83 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 0fc2ac39d1..b60aa1efbe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -57,5 +57,4 @@ ulp_tunnel_offload_entry_clear(struct bnxt_tun_cache_entry *tun_tbl,
int32_t
ulp_tunnel_offload_process(struct ulp_rte_parser_params *params);
-
#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index c60d81d14a..6fb2e3f2ad 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 68a537fa0a..e9ccee7bf4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -522,5 +522,4 @@ uint32_t ulp_bitmap_notzero(const uint8_t *bitmap, int32_t size);
/* returns 0 if input is power of 2 */
int32_t ulp_util_is_power_of_2(uint64_t x);
-
#endif /* _ULP_UTILS_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 04/11] net/bnxt: update Truflow core
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (2 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
` (6 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Randy Schacher, Farah Smith, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 303760 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Update TruFlow core code to:
- Add shared session management
- Add SRAM session management
- Add dynamic TCAM management
- Add shared TCAM session management
- Add Hot Upgrade support
- Update copyright year
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 -
drivers/net/bnxt/bnxt_irq.h | 1 -
drivers/net/bnxt/bnxt_nvm_defs.h | 1 -
drivers/net/bnxt/bnxt_ring.h | 1 -
drivers/net/bnxt/bnxt_rxr.h | 1 -
drivers/net/bnxt/bnxt_txr.h | 1 -
drivers/net/bnxt/bnxt_util.h | 1 -
drivers/net/bnxt/tf_core/cfa_resource_types.h | 2 -
drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 +++++++++++++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 ++++
.../net/bnxt/tf_core/cfa_tcam_mgr_device.h | 101 +
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 ++
.../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h | 28 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c | 921 +++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 ++++++++
drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h | 20 +
drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 +
.../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 +++
.../net/bnxt/tf_core/cfa_tcam_mgr_session.h | 54 +
drivers/net/bnxt/tf_core/meson.build | 36 +-
drivers/net/bnxt/tf_core/tf_core.c | 54 +-
drivers/net/bnxt/tf_core/tf_core.h | 97 +-
drivers/net/bnxt/tf_core/tf_device.c | 18 +-
drivers/net/bnxt/tf_core/tf_device.h | 2 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 14 +-
drivers/net/bnxt/tf_core/tf_device_p58.c | 84 +-
drivers/net/bnxt/tf_core/tf_em_common.c | 2 +-
drivers/net/bnxt/tf_core/tf_em_internal.c | 10 +-
drivers/net/bnxt/tf_core/tf_identifier.c | 1 +
drivers/net/bnxt/tf_core/tf_if_tbl.c | 59 +-
drivers/net/bnxt/tf_core/tf_msg.c | 217 +-
drivers/net/bnxt/tf_core/tf_msg.h | 38 +-
drivers/net/bnxt/tf_core/tf_rm.c | 117 +-
drivers/net/bnxt/tf_core/tf_session.c | 112 +-
drivers/net/bnxt/tf_core/tf_session.h | 65 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.c | 117 +-
drivers/net/bnxt/tf_core/tf_sram_mgr.h | 22 +-
drivers/net/bnxt/tf_core/tf_tbl.c | 8 +-
drivers/net/bnxt/tf_core/tf_tbl_sram.c | 25 +-
drivers/net/bnxt/tf_core/tf_tcam.c | 226 +-
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c | 286 +++
drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h | 49 +
drivers/net/bnxt/tf_core/tf_tcam_shared.c | 1146 +--------
drivers/net/bnxt/tf_core/tf_tcam_shared.h | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 +-
46 files changed, 6686 insertions(+), 1552 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
create mode 100644 drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
create mode 100644 drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 48bd8f2418..2bccdec7e0 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1044,5 +1044,4 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
-
#endif
diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h
index e498578968..e2d61bae7a 100644
--- a/drivers/net/bnxt/bnxt_irq.h
+++ b/drivers/net/bnxt/bnxt_irq.h
@@ -20,5 +20,4 @@ void bnxt_enable_int(struct bnxt *bp);
int bnxt_setup_int(struct bnxt *bp);
int bnxt_request_int(struct bnxt *bp);
void bnxt_int_handler(void *param);
-
#endif
diff --git a/drivers/net/bnxt/bnxt_nvm_defs.h b/drivers/net/bnxt/bnxt_nvm_defs.h
index f5ac4e8c84..57ddefa7a1 100644
--- a/drivers/net/bnxt/bnxt_nvm_defs.h
+++ b/drivers/net/bnxt/bnxt_nvm_defs.h
@@ -66,5 +66,4 @@ enum bnxnvm_pkglog_field_index {
BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
};
-
#endif /* Don't add anything after this line */
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 3d747aba54..baa60b2627 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -142,5 +142,4 @@ static inline void bnxt_db_cq(struct bnxt_cp_ring_info *cpr)
B_CP_DIS_DB(cpr, cp_raw_cons);
}
}
-
#endif
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index e132166a18..8e722b7bf0 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -386,5 +386,4 @@ bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,
mbuf->packet_type = pkt_type;
}
-
#endif /* _BNXT_RXR_H_ */
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index e11343c082..75456df5bd 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -90,5 +90,4 @@ int bnxt_flush_tx_cmp(struct bnxt_cp_ring_info *cpr);
TX_BD_LONG_LFLAGS_IP_CHKSUM)
#define TX_BD_FLG_TIP_TCP_UDP_CHKSUM (TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM | \
TX_BD_LONG_LFLAGS_T_IP_CHKSUM)
-
#endif
diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h
index 3437dc75ae..7f5b4c160e 100644
--- a/drivers/net/bnxt/bnxt_util.h
+++ b/drivers/net/bnxt/bnxt_util.h
@@ -17,5 +17,4 @@
int bnxt_check_zero_bytes(const uint8_t *bytes, int len);
void bnxt_eth_hw_addr_random(uint8_t *mac_addr);
-
#endif /* _BNXT_UTIL_H_ */
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 874d7b834f..8431c778e4 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -63,7 +63,6 @@
#define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x18UL
#define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM
-
/* Meter */
#define CFA_RESOURCE_TYPE_P58_METER 0x0UL
/* SRAM_Bank_0 */
@@ -184,7 +183,6 @@
#define CFA_RESOURCE_TYPE_P45_TBL_SCOPE 0x23UL
#define CFA_RESOURCE_TYPE_P45_LAST CFA_RESOURCE_TYPE_P45_TBL_SCOPE
-
/* Multicast Group */
#define CFA_RESOURCE_TYPE_P4_MCG 0x0UL
/* Encap 8 byte record */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
new file mode 100644
index 0000000000..f26d93e7a9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.c
@@ -0,0 +1,2116 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <inttypes.h>
+#include <signal.h>
+
+#include "hcapi_cfa_defs.h"
+
+#include "tfp.h"
+#include "tf_session.h"
+#include "tf_util.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_hwop_msg.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_session.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+
+#define TF_TCAM_SLICE_INVALID (-1)
+
+/*
+ * The following macros are for setting the entry status in a row entry.
+ * row is (struct cfa_tcam_mgr_table_rows_0 *)
+ */
+#define ROW_ENTRY_INUSE(row, entry) ((row)->entry_inuse & (1U << (entry)))
+#define ROW_ENTRY_SET(row, entry) ((row)->entry_inuse |= (1U << (entry)))
+#define ROW_ENTRY_CLEAR(row, entry) ((row)->entry_inuse &= ~(1U << (entry)))
+#define ROW_INUSE(row) ((row)->entry_inuse != 0)
+
+static struct cfa_tcam_mgr_entry_data *entry_data[TF_TCAM_MAX_SESSIONS];
+
+static int global_data_initialized[TF_TCAM_MAX_SESSIONS];
+int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+static int physical_table_types[CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS] =
+ TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS] =
+ TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_PROF_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_SP_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_CT_RULE_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS] =
+ TF_TCAM_TBL_TYPE_VEB_TCAM,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM_HIGH,
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] =
+ TF_TCAM_TBL_TYPE_WC_TCAM_LOW,
+};
+
+int
+cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type)
+{
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return physical_table_types[type];
+}
+
+const char *
+cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type)
+{
+ switch (tcam_type) {
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM:
+ return "l2_ctxt_tcam_high AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS:
+ return "l2_ctxt_tcam_high Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM:
+ return "l2_ctxt_tcam_low AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS:
+ return "l2_ctxt_tcam_low Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM:
+ return "prof_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS:
+ return "prof_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM:
+ return "wc_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS:
+ return "wc_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM:
+ return "veb_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS:
+ return "veb_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM:
+ return "sp_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS:
+ return "sp_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM:
+ return "ct_rule_tcam AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS:
+ return "ct_rule_tcam Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM:
+ return "wc_tcam_high AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS:
+ return "wc_tcam_high Apps";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM:
+ return "wc_tcam_low AFM";
+ case CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS:
+ return "wc_tcam_low Apps";
+ default:
+ return "Invalid tcam table type";
+ }
+}
+
+/* key_size and slice_width are in bytes */
+static int
+cfa_tcam_mgr_get_num_slices(unsigned int key_size, unsigned int slice_width)
+{
+ int num_slices = 0;
+
+ if (key_size == 0)
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ num_slices = ((key_size - 1U) / slice_width) + 1U;
+ /* Round up to next highest power of 2 */
+ /* This is necessary since, for example, 3 slices is not a valid entry
+ * width.
+ */
+ num_slices--;
+ /* Repeat to maximum number of bits actually used */
+ /* This fills in all the bits. */
+ num_slices |= num_slices >> 1;
+ num_slices |= num_slices >> 2;
+ num_slices |= num_slices >> 4;
+ /*
+ * If the maximum number of slices that are supported by the HW
+ * increases, then additional shifts are needed.
+ */
+ num_slices++;
+ return num_slices;
+}
+
+static struct cfa_tcam_mgr_entry_data *
+cfa_tcam_mgr_entry_get(int sess_idx, uint16_t id)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return NULL;
+
+ return &entry_data[sess_idx][id];
+}
+
+/* Insert an entry into the entry table */
+static int
+cfa_tcam_mgr_entry_insert(int sess_idx, uint16_t id,
+ struct cfa_tcam_mgr_entry_data *entry)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ memcpy(&entry_data[sess_idx][id], entry,
+ sizeof(entry_data[sess_idx][id]));
+
+ return 0;
+}
+
+/* Delete an entry from the entry table */
+static int
+cfa_tcam_mgr_entry_delete(int sess_idx, uint16_t id)
+{
+ if (id > cfa_tcam_mgr_max_entries[sess_idx])
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+
+ memset(&entry_data[sess_idx][id], 0, sizeof(entry_data[sess_idx][id]));
+
+ return 0;
+}
+
+/* Returns the size of the row structure taking into account how many slices a
+ * TCAM supports.
+ */
+static int
+cfa_tcam_mgr_row_size_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ return sizeof(struct cfa_tcam_mgr_table_rows_0) +
+ (cfa_tcam_mgr_tables[sess_idx][dir][type].max_slices *
+ sizeof(((struct cfa_tcam_mgr_table_rows_0 *)0)->entries[0]));
+}
+
+static void *
+cfa_tcam_mgr_row_ptr_get(void *base, int index, int row_size)
+{
+ return (uint8_t *)base + (index * row_size);
+}
+
+/*
+ * Searches a table to find the direction and type of an entry.
+ */
+static int
+cfa_tcam_mgr_entry_find_in_table(int sess_idx, int id, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ int max_slices, row_idx, row_size, slice;
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ if (table_data->max_entries > 0 &&
+ table_data->hcapi_type > 0) {
+ max_slices = table_data->max_slices;
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type);
+ for (row_idx = table_data->start_row;
+ row_idx <= table_data->end_row;
+ row_idx++) {
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows,
+ row_idx, row_size);
+ if (!ROW_INUSE(row))
+ continue;
+ for (slice = 0;
+ slice < (max_slices / row->entry_size);
+ slice++) {
+ if (!ROW_ENTRY_INUSE(row, slice))
+ continue;
+ if (row->entries[slice] == id)
+ return 0;
+ }
+ }
+ }
+
+ return -CFA_TCAM_MGR_ERR_CODE(NOENT);
+}
+
+/*
+ * Searches all the tables to find the direction and type of an entry.
+ */
+static int
+cfa_tcam_mgr_entry_find(int sess_idx, int id, enum tf_dir *tbl_dir,
+ enum cfa_tcam_mgr_tbl_type *tbl_type)
+{
+ enum tf_dir dir;
+ enum cfa_tcam_mgr_tbl_type type;
+ int rc = -CFA_TCAM_MGR_ERR_CODE(NOENT);
+
+ for (dir = TF_DIR_RX; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = CFA_TCAM_MGR_TBL_TYPE_START;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ rc = cfa_tcam_mgr_entry_find_in_table(sess_idx, id, dir, type);
+ if (rc == 0) {
+ *tbl_dir = dir;
+ *tbl_type = type;
+ return rc;
+ }
+ }
+ }
+
+ return rc;
+}
+
+static int
+cfa_tcam_mgr_row_is_entry_free(struct cfa_tcam_mgr_table_rows_0 *row,
+ int max_slices,
+ int key_slices)
+{
+ int j;
+
+ if (ROW_INUSE(row) &&
+ row->entry_size == key_slices) {
+ for (j = 0; j < (max_slices / row->entry_size); j++) {
+ if (!ROW_ENTRY_INUSE(row, j))
+ return j;
+ }
+ }
+ return -1;
+}
+
+static int
+cfa_tcam_mgr_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ int entry_id,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dest_row_index, int dest_row_slice,
+ struct cfa_tcam_mgr_table_rows_0 *dest_row,
+ int source_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *source_row,
+ bool free_source_entry)
+{
+ struct cfa_tcam_mgr_get_parms gparms = { 0 };
+ struct cfa_tcam_mgr_set_parms sparms = { 0 };
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ struct cfa_tcam_mgr_entry_data *entry;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE];
+
+ int j, rc;
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id);
+ if (entry == NULL)
+ return -1;
+
+ gparms.dir = dir;
+ gparms.type = type;
+ gparms.hcapi_type = table_data->hcapi_type;
+ gparms.key = key;
+ gparms.mask = mask;
+ gparms.result = result;
+ gparms.id = source_row->entries[entry->slice];
+ gparms.key_size = sizeof(key);
+ gparms.result_size = sizeof(result);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms,
+ source_row_index,
+ entry->slice * source_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ sparms.dir = dir;
+ sparms.type = type;
+ sparms.hcapi_type = table_data->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = result;
+ sparms.id = gparms.id;
+ sparms.key_size = gparms.key_size;
+ sparms.result_size = gparms.result_size;
+
+ /* Slice in destination row not specified. Find first free slice. */
+ if (dest_row_slice < 0)
+ for (j = 0;
+ j < (table_data->max_slices / dest_row->entry_size);
+ j++) {
+ if (!ROW_ENTRY_INUSE(dest_row, j)) {
+ dest_row_slice = j;
+ break;
+ }
+ }
+
+ /* If no free slice found, return error. */
+ if (dest_row_slice < 0)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms,
+ dest_row_index,
+ dest_row_slice * dest_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ if (free_source_entry) {
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ source_row_index,
+ entry->slice *
+ dest_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ source_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR,
+ dir, type,
+ "Failed to free entry ID %d at"
+ " row %d, slice %d for sess_idx %d. rc: %d.\n",
+ gparms.id,
+ source_row_index,
+ entry->slice,
+ sess_idx,
+ -rc);
+ }
+ }
+
+ ROW_ENTRY_SET(dest_row, dest_row_slice);
+ dest_row->entries[dest_row_slice] = entry_id;
+ ROW_ENTRY_CLEAR(source_row, entry->slice);
+ entry->row = dest_row_index;
+ entry->slice = dest_row_slice;
+
+ return 0;
+}
+
+static int
+cfa_tcam_mgr_row_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dest_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *dest_row,
+ int source_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *source_row)
+{
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ int j, rc;
+
+ dest_row->priority = source_row->priority;
+ dest_row->entry_size = source_row->entry_size;
+ dest_row->entry_inuse = 0;
+
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+
+ for (j = 0;
+ j < (table_data->max_slices / source_row->entry_size);
+ j++) {
+ if (ROW_ENTRY_INUSE(source_row, j)) {
+ cfa_tcam_mgr_entry_move(sess_idx, context, dir, type,
+ source_row->entries[j],
+ table_data,
+ dest_row_index, j, dest_row,
+ source_row_index, source_row,
+ true);
+ } else {
+ /* Slice not in use, write an empty slice. */
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ dest_row_index,
+ j *
+ dest_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ dest_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+/* Install entry into in-memory tables, not into TCAM (yet). */
+static void
+cfa_tcam_mgr_row_entry_install(int sess_idx,
+ struct cfa_tcam_mgr_table_rows_0 *row,
+ struct cfa_tcam_mgr_alloc_parms *parms,
+ struct cfa_tcam_mgr_entry_data *entry,
+ uint16_t id,
+ int key_slices,
+ int row_index, int slice)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return;
+ }
+
+ if (slice == TF_TCAM_SLICE_INVALID) {
+ slice = 0;
+ row->entry_size = key_slices;
+ row->priority = parms->priority;
+ }
+
+ ROW_ENTRY_SET(row, slice);
+ row->entries[slice] = id;
+ entry->row = row_index;
+ entry->slice = slice;
+}
+
+/* Finds an empty row that can be used and reserve for entry. If necessary,
+ * entries will be shuffled in order to make room.
+ */
+static struct cfa_tcam_mgr_table_rows_0 *
+cfa_tcam_mgr_empty_row_alloc(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms,
+ struct cfa_tcam_mgr_entry_data *entry,
+ uint16_t id,
+ int key_slices)
+{
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ struct cfa_tcam_mgr_table_rows_0 *from_row;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int i, max_slices, row_size;
+ int to_row_idx, from_row_idx, slice, start_row, end_row;
+ int empty_row = -1;
+ int target_row = -1;
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ max_slices = table_data->max_slices;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ /*
+ * First check for partially used entries, but only if the key needs
+ * fewer slices than there are in a row.
+ */
+ if (key_slices < max_slices) {
+ for (i = start_row; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ continue;
+ if (row->priority < parms->priority)
+ break;
+ if (row->priority > parms->priority)
+ continue;
+ slice = cfa_tcam_mgr_row_is_entry_free(row,
+ max_slices,
+ key_slices);
+ if (slice >= 0) {
+ cfa_tcam_mgr_row_entry_install(sess_idx, row, parms,
+ entry, id,
+ key_slices,
+ i, slice);
+ return row;
+ }
+ }
+ }
+
+ /* No partially used rows available. Find an empty row, if any. */
+
+ /*
+ * All max priority entries are placed in the beginning of the TCAM. It
+ * should not be necessary to shuffle any of these entries. All other
+ * priorities are placed from the end of the TCAM and may require
+ * shuffling.
+ */
+ if (parms->priority == TF_TCAM_PRIORITY_MAX) {
+ /* Handle max priority first. */
+ for (i = start_row; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row)) {
+ cfa_tcam_mgr_row_entry_install(sess_idx,
+ row, parms,
+ entry,
+ id, key_slices,
+ i,
+ TF_TCAM_SLICE_INVALID);
+ return row;
+ }
+ if (row->priority < parms->priority) {
+ /*
+ * No free entries before priority change, table
+ * is full.
+ */
+ return NULL;
+ }
+ }
+ /* No free entries found, table is full. */
+ return NULL;
+ }
+
+ /* Use the highest available entry */
+ for (i = end_row; i >= start_row; i--) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row)) {
+ empty_row = i;
+ break;
+ }
+
+ if (row->priority > parms->priority &&
+ target_row < 0)
+ target_row = i;
+ }
+
+ if (empty_row < 0) {
+ /* No free entries found, table is full. */
+ return NULL;
+ }
+
+ if (target_row < 0) {
+ /*
+ * Did not find a row with higher priority before unused row so
+ * just install new entry in empty_row.
+ */
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, empty_row, row_size);
+ cfa_tcam_mgr_row_entry_install(sess_idx, row, parms, entry, id,
+ key_slices, empty_row,
+ TF_TCAM_SLICE_INVALID);
+ return row;
+ }
+
+ to_row_idx = empty_row;
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size);
+ while (to_row_idx < target_row) {
+ from_row_idx = to_row_idx + 1;
+ from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx,
+ row_size);
+ /*
+ * Find the highest row with the same priority as the initial
+ * source row (from_row). It's only necessary to copy one row
+ * of each priority.
+ */
+ for (i = from_row_idx + 1; i <= target_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (row->priority != from_row->priority)
+ break;
+ from_row_idx = i;
+ from_row = row;
+ }
+ cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type,
+ table_data, to_row_idx, to_row,
+ from_row_idx, from_row);
+ to_row = from_row;
+ to_row_idx = from_row_idx;
+ }
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, target_row, row_size);
+ memset(to_row, 0, row_size);
+ cfa_tcam_mgr_row_entry_install(sess_idx, to_row, parms, entry, id,
+ key_slices, target_row,
+ TF_TCAM_SLICE_INVALID);
+
+ return row;
+}
+
+/*
+ * This function will combine rows when possible to result in the fewest rows
+ * used necessary for the entries that are installed.
+ */
+static void
+cfa_tcam_mgr_rows_combine(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int changed_row_index)
+{
+ struct cfa_tcam_mgr_table_rows_0 *from_row = NULL;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ int i, j, row_size;
+ int to_row_idx, from_row_idx, start_row, end_row, max_slices;
+ bool entry_moved = false;
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ max_slices = table_data->max_slices;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ from_row_idx = changed_row_index;
+ from_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, from_row_idx, row_size);
+
+ if (ROW_INUSE(from_row)) {
+ /*
+ * Row is still in partial use. See if remaining entry(s) can
+ * be moved to free up a row.
+ */
+ for (i = 0; i < (max_slices / from_row->entry_size); i++) {
+ if (!ROW_ENTRY_INUSE(from_row, i))
+ continue;
+ for (to_row_idx = end_row;
+ to_row_idx >= start_row;
+ to_row_idx--) {
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows,
+ to_row_idx,
+ row_size);
+ if (!ROW_INUSE(to_row))
+ continue;
+ if (to_row->priority > from_row->priority)
+ break;
+ if (to_row->priority != from_row->priority)
+ continue;
+ if (to_row->entry_size != from_row->entry_size)
+ continue;
+ if (to_row_idx == changed_row_index)
+ continue;
+ for (j = 0;
+ j < (max_slices / to_row->entry_size);
+ j++) {
+ if (!ROW_ENTRY_INUSE(to_row, j)) {
+ cfa_tcam_mgr_entry_move
+ (sess_idx,
+ context,
+ parms->dir,
+ parms->type,
+ from_row->entries[i],
+ table_data,
+ to_row_idx,
+ -1, to_row,
+ from_row_idx,
+ from_row,
+ true);
+ entry_moved = true;
+ break;
+ }
+ }
+ if (entry_moved)
+ break;
+ }
+ if (ROW_INUSE(from_row))
+ entry_moved = false;
+ else
+ break;
+ }
+ }
+}
+
+/*
+ * This function will ensure that all rows, except those of the highest
+ * priority, at the end of the table. When this function is finished, all the
+ * empty rows should be between the highest priority rows at the beginning of
+ * the table and the rest of the rows with lower priorities.
+ */
+/*
+ * Will need to free the row left newly empty as a result of moving.
+ *
+ * Return row to free to caller. If new_row_to_free < 0, then no new row to
+ * free.
+ */
+static void
+cfa_tcam_mgr_rows_compact(int sess_idx, struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int *new_row_to_free,
+ int changed_row_index)
+{
+ struct cfa_tcam_mgr_table_rows_0 *from_row = NULL;
+ struct cfa_tcam_mgr_table_rows_0 *to_row;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ int i, row_size, priority;
+ int to_row_idx = 0, from_row_idx = 0, start_row = 0, end_row = 0;
+
+ *new_row_to_free = -1;
+
+ start_row = table_data->start_row;
+ end_row = table_data->end_row;
+ tcam_rows = table_data->tcam_rows;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ /*
+ * The row is no longer in use, so see if rows need to be moved in order
+ * to not leave any gaps.
+ */
+ to_row_idx = changed_row_index;
+ to_row = cfa_tcam_mgr_row_ptr_get(tcam_rows, to_row_idx, row_size);
+
+ priority = to_row->priority;
+ if (priority == TF_TCAM_PRIORITY_MAX) {
+ if (changed_row_index == end_row)
+ /*
+ * Nothing to move - the last row in the TCAM is being
+ * deleted.
+ */
+ return;
+ for (i = changed_row_index + 1; i <= end_row; i++) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ break;
+
+ if (row->priority < priority)
+ break;
+
+ from_row = row;
+ from_row_idx = i;
+ }
+ } else {
+ if (changed_row_index == start_row)
+ /*
+ * Nothing to move - the first row in the TCAM is being
+ * deleted.
+ */
+ return;
+ for (i = changed_row_index - 1; i >= start_row; i--) {
+ row = cfa_tcam_mgr_row_ptr_get(tcam_rows, i, row_size);
+ if (!ROW_INUSE(row))
+ break;
+
+ if (row->priority > priority) {
+ /* Don't move the highest priority rows. */
+ if (row->priority == TF_TCAM_PRIORITY_MAX)
+ break;
+ /*
+ * If from_row is NULL, that means that there
+ * were no rows of the deleted priority.
+ * Nothing to move yet.
+ *
+ * If from_row is not NULL, then it is the last
+ * row with the same priority and must be moved
+ * to fill the newly empty (by free or by move)
+ * row.
+ */
+ if (from_row != NULL) {
+ cfa_tcam_mgr_row_move(sess_idx, context,
+ parms->dir,
+ parms->type,
+ table_data,
+ to_row_idx, to_row,
+ from_row_idx,
+ from_row);
+ *new_row_to_free = from_row_idx;
+ to_row = from_row;
+ to_row_idx = from_row_idx;
+ }
+
+ priority = row->priority;
+ }
+ from_row = row;
+ from_row_idx = i;
+ }
+ }
+
+ if (from_row != NULL) {
+ cfa_tcam_mgr_row_move(sess_idx, context, parms->dir, parms->type,
+ table_data,
+ to_row_idx, to_row,
+ from_row_idx, from_row);
+ *new_row_to_free = from_row_idx;
+ }
+}
+
+/*
+ * This function is to set table limits for the logical TCAM tables.
+ */
+static int
+cfa_tcam_mgr_table_limits_set(int sess_idx, struct cfa_tcam_mgr_init_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ unsigned int dir, type;
+ int start, stride;
+
+ if (parms == NULL)
+ return 0;
+
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++)
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ /*
+ * If num_rows is zero, then TCAM Manager did not
+ * allocate any row storage for that table so cannot
+ * manage it.
+ */
+ if (table_data->num_rows == 0)
+ continue;
+ start = parms->resc[dir][type].start;
+ stride = parms->resc[dir][type].stride;
+ if (start % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Start of resources (%d) for table (%d) "
+ "does not begin on row boundary.\n",
+ start, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Start is %d, number of slices "
+ "is %d.\n",
+ start,
+ table_data->max_slices);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Stride of resources (%d) for table (%d)"
+ " does not end on row boundary.\n",
+ stride, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Stride is %d, number of "
+ "slices is %d.\n",
+ stride,
+ table_data->max_slices);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else {
+ table_data->start_row = start /
+ table_data->max_slices;
+ table_data->end_row = table_data->start_row +
+ (stride / table_data->max_slices) - 1;
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type,
+ struct cfa_tcam_mgr_init_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ unsigned int dir, tbl_type;
+ int rc;
+
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ rc = cfa_tcam_mgr_init_p4(sess_idx, &entry_data[sess_idx]);
+ break;
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ rc = cfa_tcam_mgr_init_p58(sess_idx, &entry_data[sess_idx]);
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d for sess_idx %d\n",
+ type, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+ if (rc < 0)
+ return rc;
+
+ rc = cfa_tcam_mgr_table_limits_set(sess_idx, parms);
+ if (rc < 0)
+ return rc;
+
+ /* Now calculate the max entries per table and global max entries based
+ * on the updated table limits.
+ */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++)
+ for (tbl_type = 0;
+ tbl_type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ tbl_type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type];
+ /*
+ * If num_rows is zero, then TCAM Manager did not
+ * allocate any row storage for that table so cannot
+ * manage it.
+ */
+ if (table_data->num_rows == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else if (table_data->end_row >=
+ table_data->num_rows) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(EMERG, dir, tbl_type,
+ "End row is out of "
+ "range (%d >= %d) for sess_idx %d\n",
+ table_data->end_row,
+ table_data->num_rows,
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(FAULT);
+ } else if (table_data->max_entries == 0 &&
+ table_data->start_row == 0 &&
+ table_data->end_row == 0) {
+ /* Nothing to do */
+ } else {
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ cfa_tcam_mgr_max_entries[sess_idx] += table_data->max_entries;
+ }
+
+ rc = cfa_tcam_mgr_hwops_init(type);
+ if (rc < 0)
+ return rc;
+
+ rc = cfa_tcam_mgr_session_init(sess_idx, type);
+ if (rc < 0)
+ return rc;
+
+ global_data_initialized[sess_idx] = 1;
+
+ if (parms != NULL)
+ parms->max_entries = cfa_tcam_mgr_max_entries[sess_idx];
+
+ CFA_TCAM_MGR_LOG(INFO, "Global TCAM table initialized for sess_idx %d.\n",
+ sess_idx);
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_qcaps_parms *parms)
+{
+ unsigned int type;
+ int rc, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ /*
+ * This code will indicate if TCAM Manager is managing a logical TCAM
+ * table or not. If not, then the physical TCAM will have to be
+ * accessed using the traditional methods.
+ */
+ parms->rx_tcam_supported = 0;
+ parms->tx_tcam_supported = 0;
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].max_entries > 0 &&
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX][type].hcapi_type > 0)
+ parms->rx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type);
+ if (cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].max_entries > 0 &&
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX][type].hcapi_type > 0)
+ parms->tx_tcam_supported |= 1 << cfa_tcam_mgr_get_phys_table_type(type);
+ }
+
+ return 0;
+}
+
+/*
+ * Manipulate the tables to split the WC TCAM into HIGH and LOW ranges
+ * and also update the sizes in the tcam count array
+ */
+static int
+cfa_tcam_mgr_shared_wc_bind(uint32_t sess_idx, bool dual_ha_app,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX])
+{
+ uint16_t start_row, end_row, max_entries, slices;
+ uint16_t num_pools = dual_ha_app ? 4 : 2;
+ enum tf_dir dir;
+ int rc;
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ rc = cfa_tcam_mgr_tables_get(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ &start_row, &end_row, &max_entries, &slices);
+ if (rc)
+ return rc;
+ if (max_entries) {
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ start_row,
+ start_row +
+ ((max_entries / slices) / num_pools) - 1,
+ max_entries / num_pools);
+ if (rc)
+ return rc;
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ start_row +
+ ((max_entries / slices) / num_pools),
+ start_row +
+ (max_entries / slices) - 1,
+ max_entries / num_pools);
+ if (rc)
+ return rc;
+ rc = cfa_tcam_mgr_tables_set(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ 0, 0, 0);
+ if (rc)
+ return rc;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS] =
+ max_entries / num_pools;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS] =
+ max_entries / num_pools;
+ tcam_cnt[dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS] = 0;
+ }
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_cfg_parms *parms)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct tf_dev_info *dev;
+ unsigned int dir;
+ int rc, sess_idx;
+ uint32_t session_id;
+ struct tf_session *tfs;
+ unsigned int type;
+ int prev_max_entries;
+ int start, stride;
+ enum cfa_tcam_mgr_device_type device_type;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ switch (dev->type) {
+ case TF_DEVICE_TYPE_P4:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_P4;
+ break;
+ case TF_DEVICE_TYPE_SR:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_SR;
+ break;
+ case TF_DEVICE_TYPE_P5:
+ device_type = CFA_TCAM_MGR_DEVICE_TYPE_P5;
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", dev->type);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_add(session_id);
+ if (sess_idx < 0)
+ return sess_idx;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ rc = cfa_tcam_mgr_init(sess_idx, device_type, NULL);
+ if (rc < 0)
+ return rc;
+ }
+
+ if (parms->num_elements != ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir])) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "Session element count (%d) differs "
+ "from table count (%zu) for sess_idx %d.\n",
+ parms->num_elements,
+ ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]),
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /*
+ * Only managing one session. resv_res contains the resources allocated
+ * to this session by the resource manager. Update the limits on TCAMs.
+ */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ prev_max_entries = table_data->max_entries;
+ /*
+ * In AFM logical tables, max_entries is initialized to
+ * zero. These logical tables are not used when TCAM
+ * Manager is in the core so skip.
+ */
+ if (prev_max_entries == 0)
+ continue;
+ start = parms->resv_res[dir][type].start;
+ stride = parms->resv_res[dir][type].stride;
+ if (start % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Start of resources (%d) for table(%d) "
+ "does not begin on row boundary.\n",
+ start, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Start is %d, number of slices "
+ "is %d.\n",
+ start,
+ table_data->max_slices);
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride % table_data->max_slices > 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Stride of resources (%d) for table(%d) "
+ "does not end on row boundary.\n",
+ stride, sess_idx);
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Stride is %d, number of "
+ "slices is %d.\n",
+ stride,
+ table_data->max_slices);
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (stride == 0) {
+ table_data->start_row = 0;
+ table_data->end_row = 0;
+ table_data->max_entries = 0;
+ } else {
+ table_data->start_row = start /
+ table_data->max_slices;
+ table_data->end_row = table_data->start_row +
+ (stride / table_data->max_slices) - 1;
+ table_data->max_entries =
+ table_data->max_slices *
+ (table_data->end_row -
+ table_data->start_row + 1);
+ }
+ cfa_tcam_mgr_max_entries[sess_idx] += (table_data->max_entries -
+ prev_max_entries);
+ }
+ }
+
+ if (tf_session_is_shared_hotup_session(tfs)) {
+ rc = cfa_tcam_mgr_shared_wc_bind(sess_idx, false, parms->tcam_cnt);
+ if (rc) {
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return rc;
+ }
+ }
+
+ rc = cfa_tcam_mgr_session_cfg(session_id, parms->tcam_cnt);
+ if (rc < 0) {
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+ return rc;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context)
+{
+ int rc, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS1(context);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ (void)cfa_tcam_mgr_session_free(session_id, context);
+
+ global_data_initialized[sess_idx] = 0;
+ return 0;
+}
+
+int
+cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int dir, tbl_type;
+ int key_slices, rc, sess_idx;
+ int new_entry_id;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ dir = parms->dir;
+ tbl_type = parms->type;
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Invalid direction: %d.\n", dir);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (tbl_type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Invalid table type: %d.\n",
+ tbl_type);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+#if TF_TCAM_PRIORITY_MAX < UINT16_MAX
+ if (parms->priority > TF_TCAM_PRIORITY_MAX) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Priority (%u) out of range (%u -%u).\n",
+ parms->priority,
+ TF_TCAM_PRIORITY_MIN,
+ TF_TCAM_PRIORITY_MAX);
+ }
+#endif
+
+ /* Check for session limits */
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][tbl_type];
+
+ if (parms->key_size == 0 ||
+ parms->key_size > table_data->row_width) {
+ CFA_TCAM_MGR_LOG_DIR(ERR, dir,
+ "Invalid key size:%d (range 1-%d) sess_idx %d.\n",
+ parms->key_size,
+ table_data->row_width,
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /* Check global limits */
+ if (table_data->used_entries >=
+ table_data->max_entries) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, tbl_type,
+ "Table full sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ /* There is room, now increment counts and allocate an entry. */
+ new_entry_id = cfa_tcam_mgr_session_entry_alloc(session_id,
+ parms->dir,
+ parms->type);
+ if (new_entry_id < 0)
+ return new_entry_id;
+
+ memset(&entry, 0, sizeof(entry));
+ entry.ref_cnt++;
+
+ key_slices = cfa_tcam_mgr_get_num_slices(parms->key_size,
+ (table_data->row_width /
+ table_data->max_slices));
+
+ row = cfa_tcam_mgr_empty_row_alloc(sess_idx, context, parms, &entry,
+ new_entry_id, key_slices);
+ if (row == NULL) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Table full (HW) sess_idx %d.\n",
+ sess_idx);
+ (void)cfa_tcam_mgr_session_entry_free(session_id, new_entry_id,
+ parms->dir, parms->type);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ memcpy(&entry_data[sess_idx][new_entry_id],
+ &entry,
+ sizeof(entry_data[sess_idx][new_entry_id]));
+ table_data->used_entries += 1;
+
+ cfa_tcam_mgr_entry_insert(sess_idx, new_entry_id, &entry);
+
+ parms->id = new_entry_id;
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int row_size, rc, sess_idx, new_row_to_free;
+ uint32_t session_id;
+ uint16_t id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ id = parms->id;
+ entry = cfa_tcam_mgr_entry_get(sess_idx, id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(INFO, "Entry %d not found for sess_idx %d.\n",
+ id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (entry->ref_cnt == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not in use for sess_idx %d.\n",
+ id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ /*
+ * If the TCAM type is CFA_TCAM_MGR_TBL_TYPE_MAX, that implies that the
+ * caller does not know the table or direction of the entry and TCAM
+ * Manager must search the tables to find out which table has the entry
+ * installed.
+ *
+ * This would be the case if RM has informed TCAM Mgr that an entry must
+ * be freed. Clients (sessions, AFM) should always know the type and
+ * direction of the table where an entry is installed.
+ */
+ if (parms->type == CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Need to search for the entry in the tables */
+ rc = cfa_tcam_mgr_entry_find(sess_idx, id, &parms->dir, &parms->type);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not in tables for sess_idx %d.\n",
+ id, sess_idx);
+ return rc;
+ }
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ entry->ref_cnt--;
+
+ (void)cfa_tcam_mgr_session_entry_free(session_id, id,
+ parms->dir, parms->type);
+
+ if (entry->ref_cnt == 0) {
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ ROW_ENTRY_CLEAR(row, entry->slice);
+
+ new_row_to_free = entry->row;
+ cfa_tcam_mgr_rows_combine(sess_idx, context, parms, table_data,
+ new_row_to_free);
+
+ if (!ROW_INUSE(row)) {
+ cfa_tcam_mgr_rows_compact(sess_idx, context,
+ parms, table_data,
+ &new_row_to_free,
+ new_row_to_free);
+ if (new_row_to_free >= 0)
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, parms,
+ new_row_to_free, 0,
+ table_data->row_width,
+ table_data->result_size,
+ table_data->max_slices);
+ }
+
+ cfa_tcam_mgr_entry_delete(sess_idx, id);
+ table_data->used_entries -= 1;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int rc;
+ int row_size, sess_idx;
+ int entry_size_in_bytes;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not found for sess_idx %d.\n",
+ parms->id, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ entry_size_in_bytes = table_data->row_width /
+ table_data->max_slices *
+ row->entry_size;
+ if (parms->key_size != entry_size_in_bytes) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "Key size(%d) is different from entry "
+ "size(%d).\n",
+ parms->key_size,
+ entry_size_in_bytes);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->max_slices);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Failed to set TCAM data.\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+int
+cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_get_parms *parms)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ struct cfa_tcam_mgr_table_rows_0 *row;
+ struct cfa_tcam_mgr_table_data *table_data;
+ int rc;
+ int row_size, sess_idx;
+ uint32_t session_id;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, parms->id);
+ if (entry == NULL) {
+ CFA_TCAM_MGR_LOG(ERR, "Entry %d not found.\n", parms->id);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ parms->hcapi_type = table_data->hcapi_type;
+
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, parms->dir, parms->type);
+ row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, entry->row,
+ row_size);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, parms,
+ entry->row,
+ entry->slice * row->entry_size,
+ table_data->max_slices);
+ if (rc < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Failed to read from TCAM.\n");
+ return rc;
+ }
+
+ return 0;
+}
+
+int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_clear_parms *parms)
+{
+ int rc;
+ uint16_t row, slice = 0;
+ int sess_idx;
+ uint32_t session_id;
+ struct cfa_tcam_mgr_free_parms fparms;
+ struct cfa_tcam_mgr_table_data *table_data;
+ uint16_t start_row, end_row, max_entries, max_slices;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][parms->dir][parms->type];
+ fparms.dir = parms->dir;
+ fparms.type = parms->type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ fparms.id = 0;
+
+ rc = cfa_tcam_mgr_tables_get(sess_idx, parms->dir, parms->type,
+ &start_row, &end_row, &max_entries, &max_slices);
+ if (rc)
+ return rc;
+
+ for (row = start_row; row <= end_row; row++) {
+ cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ row,
+ slice,
+ table_data->row_width,
+ table_data->result_size,
+ table_data->max_slices);
+ }
+ return rc;
+}
+
+static void
+cfa_tcam_mgr_mv_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ struct cfa_tcam_mgr_table_data *dst_table_data,
+ struct cfa_tcam_mgr_table_data *src_table_data)
+{
+ dst_table_data->used_entries++;
+ src_table_data->used_entries--;
+
+ cfa_tcam_mgr_mv_session_used_entries_cnt(sess_idx, dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS);
+}
+
+/*
+ * Move HI WC TCAM entries to LOW TCAM region for HA
+ * This happens when secondary is becoming primary
+ */
+static int
+cfa_tcam_mgr_shared_entry_move(int sess_idx, struct cfa_tcam_mgr_context *context,
+ enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type,
+ int entry_id,
+ struct cfa_tcam_mgr_table_data *dst_table_data,
+ struct cfa_tcam_mgr_table_data *table_data,
+ int dst_row_index, int dst_row_slice,
+ struct cfa_tcam_mgr_table_rows_0 *dst_row,
+ int src_row_index,
+ struct cfa_tcam_mgr_table_rows_0 *src_row)
+{
+ struct cfa_tcam_mgr_get_parms gparms = { 0 };
+ struct cfa_tcam_mgr_set_parms sparms = { 0 };
+ struct cfa_tcam_mgr_free_parms fparms = { 0 };
+ struct cfa_tcam_mgr_entry_data *entry;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE];
+ uint8_t result[CFA_TCAM_MGR_MAX_KEY_SIZE];
+
+ int rc;
+
+ entry = cfa_tcam_mgr_entry_get(sess_idx, entry_id);
+ if (entry == NULL)
+ return -1;
+
+ gparms.dir = dir;
+ gparms.type = type;
+ gparms.hcapi_type = table_data->hcapi_type;
+ gparms.key = key;
+ gparms.mask = mask;
+ gparms.result = result;
+ gparms.id = src_row->entries[entry->slice];
+ gparms.key_size = sizeof(key);
+ gparms.result_size = sizeof(result);
+
+ rc = cfa_tcam_mgr_entry_get_msg(sess_idx, context, &gparms,
+ src_row_index,
+ entry->slice * src_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ sparms.dir = dir;
+ sparms.type = CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS;
+ sparms.hcapi_type = table_data->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = result;
+ sparms.id = gparms.id;
+ sparms.key_size = gparms.key_size;
+ sparms.result_size = gparms.result_size;
+
+ rc = cfa_tcam_mgr_entry_set_msg(sess_idx, context, &sparms,
+ dst_row_index,
+ dst_row_slice * dst_row->entry_size,
+ table_data->max_slices);
+ if (rc != 0)
+ return rc;
+
+ fparms.dir = dir;
+ fparms.type = type;
+ fparms.hcapi_type = table_data->hcapi_type;
+ rc = cfa_tcam_mgr_entry_free_msg(sess_idx, context, &fparms,
+ src_row_index,
+ entry->slice *
+ dst_row->entry_size,
+ table_data->row_width /
+ table_data->max_slices *
+ src_row->entry_size,
+ table_data->result_size,
+ table_data->max_slices);
+ if (rc != 0) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR,
+ dir, type,
+ "Failed to free entry ID %d at"
+ " row %d, slice %d for sess_idx %d. rc: %d.\n",
+ gparms.id,
+ src_row_index,
+ entry->slice,
+ sess_idx,
+ -rc);
+ }
+
+#ifdef CFA_TCAM_MGR_TRACING
+ CFA_TCAM_MGR_TRACE(INFO, "Moved entry %d from row %d, slice %d to "
+ "row %d, slice %d.\n",
+ entry_id, src_row_index, entry->slice,
+ dst_row_index, dst_row_slice);
+#endif
+
+ ROW_ENTRY_SET(dst_row, dst_row_slice);
+ dst_row->entries[dst_row_slice] = entry_id;
+ dst_row->entry_size = src_row->entry_size;
+ dst_row->priority = src_row->priority;
+ ROW_ENTRY_CLEAR(src_row, entry->slice);
+ entry->row = dst_row_index;
+ entry->slice = dst_row_slice;
+
+ cfa_tcam_mgr_mv_used_entries_cnt(sess_idx, dir, dst_table_data, table_data);
+
+#ifdef CFA_TCAM_MGR_TRACING
+ cfa_tcam_mgr_rows_dump(sess_idx, dir, type);
+ cfa_tcam_mgr_rows_dump(sess_idx, dir, CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS);
+#endif
+
+ return 0;
+}
+
+int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_move_parms *parms)
+{
+ int rc;
+ int sess_idx;
+ uint32_t session_id;
+ uint16_t src_row, dst_row, row_size, slice;
+ struct cfa_tcam_mgr_table_rows_0 *src_table_row;
+ struct cfa_tcam_mgr_table_rows_0 *dst_table_row;
+ struct cfa_tcam_mgr_table_data *src_table_data;
+ struct cfa_tcam_mgr_table_data *dst_table_data;
+
+ CFA_TCAM_MGR_CHECK_PARMS2(context, parms);
+
+ rc = cfa_tcam_mgr_get_session_from_context(context, &session_id);
+ if (rc < 0)
+ return rc;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG(ERR, "Session 0x%08x not found.\n",
+ session_id);
+ return sess_idx;
+ }
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+ }
+
+ src_table_data =
+ &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS];
+ dst_table_data =
+ &cfa_tcam_mgr_tables[sess_idx][parms->dir][CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS];
+
+ row_size =
+ cfa_tcam_mgr_row_size_get(sess_idx,
+ parms->dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS);
+
+ for (src_row = src_table_data->start_row,
+ dst_row = dst_table_data->start_row;
+ src_row <= src_table_data->end_row;
+ src_row++, dst_row++) {
+ src_table_row = cfa_tcam_mgr_row_ptr_get(src_table_data->tcam_rows,
+ src_row, row_size);
+ dst_table_row = cfa_tcam_mgr_row_ptr_get(dst_table_data->tcam_rows,
+ dst_row, row_size);
+ if (ROW_INUSE(src_table_row)) {
+ for (slice = 0;
+ slice < src_table_data->max_slices / src_table_row->entry_size;
+ slice++) {
+ if (ROW_ENTRY_INUSE(src_table_row, slice)) {
+#ifdef CFA_TCAM_MGR_TRACING
+ CFA_TCAM_MGR_TRACE(INFO, "Move entry id %d "
+ "from src_row %d, slice %d "
+ "to dst_row %d, slice %d.\n",
+ src_table_row->entries[slice],
+ src_row, slice,
+ dst_row, slice);
+#endif
+ rc = cfa_tcam_mgr_shared_entry_move(sess_idx,
+ context,
+ parms->dir,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ src_table_row->entries[slice],
+ dst_table_data,
+ src_table_data,
+ dst_row, slice,
+ dst_table_row,
+ src_row,
+ src_table_row);
+ }
+ }
+ }
+ }
+
+ return rc;
+}
+
+static void
+cfa_tcam_mgr_tbl_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ /* Get start, end and max for tcam type*/
+ *start_row = table_data->start_row;
+ *end_row = table_data->end_row;
+ *max_entries = table_data->max_entries;
+ *slices = table_data->max_slices;
+}
+
+int
+cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices)
+{
+ CFA_TCAM_MGR_CHECK_PARMS3(start_row, end_row, max_entries);
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n",
+ TF_DIR_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ cfa_tcam_mgr_tbl_get(sess_idx, dir,
+ type,
+ start_row,
+ end_row,
+ max_entries,
+ slices);
+ return 0;
+}
+
+static void
+cfa_tcam_mgr_tbl_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ /* Update start, end and max for tcam type*/
+ table_data->start_row = start_row;
+ table_data->end_row = end_row;
+ table_data->max_entries = max_entries;
+}
+
+int
+cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(ERR, "PANIC: TCAM not initialized for sess_idx %d.\n",
+ sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid dir (0-%d) forsess_idx %d.\n",
+ TF_DIR_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ CFA_TCAM_MGR_LOG(ERR, "Must specify valid tbl type (0-%d) forsess_idx %d.\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1, sess_idx);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ cfa_tcam_mgr_tbl_set(sess_idx, dir,
+ type,
+ start_row,
+ end_row,
+ max_entries);
+ return 0;
+}
+
+void
+cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_table_rows_0 *table_row;
+ int i, row, row_size;
+ bool row_found = false;
+ bool empty_row = false;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx);
+ return;
+ }
+
+ if (dir >= TF_DIR_MAX) {
+ printf("Must specify a valid direction (0-%d).\n",
+ TF_DIR_MAX - 1);
+ return;
+ }
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ printf("Must specify a valid type (0-%d).\n",
+ CFA_TCAM_MGR_TBL_TYPE_MAX - 1);
+ return;
+ }
+
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ row_size = cfa_tcam_mgr_row_size_get(sess_idx, dir, type);
+
+ printf("\nTCAM Rows:\n");
+ printf("Rows for direction %s, Logical table type %s\n",
+ tf_dir_2_str(dir), cfa_tcam_mgr_tbl_2_str(type));
+ printf("Managed rows %d-%d for sess_idx %d:\n",
+ table_data->start_row, table_data->end_row, sess_idx);
+
+ printf("Index Pri Size Entry IDs\n");
+ printf(" Sl 0");
+ for (i = 1; i < table_data->max_slices; i++)
+ printf(" Sl %d", i);
+ printf("\n");
+ for (row = table_data->start_row; row <= table_data->end_row; row++) {
+ table_row = cfa_tcam_mgr_row_ptr_get(table_data->tcam_rows, row,
+ row_size);
+ if (ROW_INUSE(table_row)) {
+ empty_row = false;
+ printf("%5u %5u %4u",
+ row,
+ TF_TCAM_PRIORITY_MAX - table_row->priority - 1,
+ table_row->entry_size);
+ for (i = 0;
+ i < table_data->max_slices / table_row->entry_size;
+ i++) {
+ if (ROW_ENTRY_INUSE(table_row, i))
+ printf(" %5u", table_row->entries[i]);
+ else
+ printf(" x");
+ }
+ printf("\n");
+ row_found = true;
+ } else if (!empty_row) {
+ empty_row = true;
+ printf("\n");
+ }
+ }
+
+ if (!row_found)
+ printf("No rows in use.\n");
+}
+
+static void
+cfa_tcam_mgr_table_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ struct cfa_tcam_mgr_table_data *table_data =
+ &cfa_tcam_mgr_tables[sess_idx][dir][type];
+
+ printf("%3s %-22s %5u %5u %5u %5u %6u %7u %2u\n",
+ tf_dir_2_str(dir),
+ cfa_tcam_mgr_tbl_2_str(type),
+ table_data->row_width,
+ table_data->num_rows,
+ table_data->start_row,
+ table_data->end_row,
+ table_data->max_entries,
+ table_data->used_entries,
+ table_data->max_slices);
+}
+
+#define TABLE_DUMP_HEADER \
+ "Dir Table Width Rows Start End " \
+ "MaxEnt UsedEnt Slices\n"
+
+void
+cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ if (global_data_initialized[sess_idx] == 0) {
+ printf("PANIC: TCAM not initialized for sess_idx %d.\n", sess_idx);
+ return;
+ }
+
+ printf("\nTCAM Table(s) for sess_idx %d:\n", sess_idx);
+ printf(TABLE_DUMP_HEADER);
+ if (dir >= TF_DIR_MAX) {
+ /* Iterate over all directions */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Iterate over all types */
+ for (type = 0;
+ type < CFA_TCAM_MGR_TBL_TYPE_MAX;
+ type++) {
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+ } else {
+ /* Display a specific type */
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+ }
+ } else if (type >= CFA_TCAM_MGR_TBL_TYPE_MAX) {
+ /* Iterate over all types for a direction */
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++)
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ } else {
+ /* Display a specific direction and type */
+ cfa_tcam_mgr_table_dump(sess_idx, dir, type);
+ }
+}
+
+#define ENTRY_DUMP_HEADER "Entry RefCnt Row Slice\n"
+
+void
+cfa_tcam_mgr_entries_dump(int sess_idx)
+{
+ struct cfa_tcam_mgr_entry_data *entry;
+ bool entry_found = false;
+ uint16_t id;
+
+ if (global_data_initialized[sess_idx] == 0) {
+ CFA_TCAM_MGR_LOG(INFO, "PANIC: No TCAM data created for sess_idx %d\n",
+ sess_idx);
+ return;
+ }
+
+ printf("\nGlobal Maximum Entries: %d\n\n",
+ cfa_tcam_mgr_max_entries[sess_idx]);
+ printf("TCAM Entry Table:\n");
+ for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) {
+ if (entry_data[sess_idx][id].ref_cnt > 0) {
+ entry = &entry_data[sess_idx][id];
+ if (!entry_found)
+ printf(ENTRY_DUMP_HEADER);
+ printf("%5u %5u %5u %5u",
+ id, entry->ref_cnt,
+ entry->row, entry->slice);
+ printf("\n");
+ entry_found = true;
+ }
+ }
+
+ if (!entry_found)
+ printf("No entries found.\n");
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
new file mode 100644
index 0000000000..40bfe8e225
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr.h
@@ -0,0 +1,523 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _CFA_TCAM_MGR_H_
+#define _CFA_TCAM_MGR_H_
+
+#include <errno.h>
+#include "rte_common.h"
+#include "hsi_struct_def_dpdk.h"
+#include "tf_core.h"
+
+#ifndef __rte_unused
+#define __rte_unused __attribute__((unused))
+#endif
+
+/**
+ * The TCAM module provides processing of Internal TCAM types.
+ */
+
+#ifndef TF_TCAM_MAX_SESSIONS
+#define TF_TCAM_MAX_SESSIONS 16
+#endif
+
+#define ENTRY_ID_INVALID UINT16_MAX
+
+#define TF_TCAM_PRIORITY_MIN 0
+#define TF_TCAM_PRIORITY_MAX UINT16_MAX
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_array) (sizeof(_array) / sizeof(_array[0]))
+#endif
+
+/* Use TFP_DRV_LOG definition in tfp.h */
+#define CFA_TCAM_MGR_LOG(level, fmt, args...) \
+ TFP_DRV_LOG(level, fmt, ## args)
+#define CFA_TCAM_MGR_LOG_DIR(level, dir, fmt, args...) \
+ TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir), ## args)
+#define CFA_TCAM_MGR_LOG_DIR_TYPE(level, dir, type, fmt, args...) \
+ TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \
+ cfa_tcam_mgr_tbl_2_str(type), ## args)
+
+#define CFA_TCAM_MGR_LOG_0(level, fmt) \
+ TFP_DRV_LOG(level, fmt)
+#define CFA_TCAM_MGR_LOG_DIR_0(level, dir, fmt) \
+ TFP_DRV_LOG(level, "%s: " fmt, tf_dir_2_str(dir))
+#define CFA_TCAM_MGR_LOG_DIR_TYPE_0(level, dir, type, fmt) \
+ TFP_DRV_LOG(level, "%s: %s " fmt, tf_dir_2_str(dir), \
+ cfa_tcam_mgr_tbl_2_str(type))
+
+#define CFA_TCAM_MGR_ERR_CODE(type) E ## type
+
+/**
+ * Checks 1 parameter against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS1(parms) do { \
+ if ((parms) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+/**
+ * Checks 2 parameters against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS2(parms1, parms2) do { \
+ if ((parms1) == NULL || (parms2) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+/**
+ * Checks 3 parameters against NULL.
+ */
+#define CFA_TCAM_MGR_CHECK_PARMS3(parms1, parms2, parms3) do { \
+ if ((parms1) == NULL || \
+ (parms2) == NULL || \
+ (parms3) == NULL) { \
+ CFA_TCAM_MGR_LOG_0(ERR, "Invalid Argument(s)\n"); \
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL); \
+ } \
+ } while (0)
+
+enum cfa_tcam_mgr_tbl_type {
+ /* Logical TCAM tables */
+ CFA_TCAM_MGR_TBL_TYPE_START,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM =
+ CFA_TCAM_MGR_TBL_TYPE_START,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM,
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+ CFA_TCAM_MGR_TBL_TYPE_MAX
+};
+
+enum cfa_tcam_mgr_device_type {
+ CFA_TCAM_MGR_DEVICE_TYPE_P4 = 0,
+ CFA_TCAM_MGR_DEVICE_TYPE_SR,
+ CFA_TCAM_MGR_DEVICE_TYPE_P5,
+ CFA_TCAM_MGR_DEVICE_TYPE_MAX
+};
+
+struct cfa_tcam_mgr_context {
+ struct tf *tfp;
+};
+
+/**
+ * TCAM Manager initialization parameters
+ */
+struct cfa_tcam_mgr_init_parms {
+ /**
+ * [in] TCAM resources reserved
+ * type element is not used.
+ */
+ struct tf_rm_resc_entry resc[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ /**
+ * [out] maximum number of entries available.
+ */
+ uint32_t max_entries;
+};
+
+/**
+ * TCAM Manager initialization parameters
+ */
+struct cfa_tcam_mgr_qcaps_parms {
+ /**
+ * [out] Bitmasks. Set if TCAM Manager is managing a logical TCAM.
+ * Each bitmask is indexed by logical TCAM table ID.
+ */
+ uint32_t rx_tcam_supported;
+ uint32_t tx_tcam_supported;
+};
+
+/**
+ * TCAM Manager configuration parameters
+ */
+struct cfa_tcam_mgr_cfg_parms {
+ /**
+ * [in] Number of tcam types in each of the configuration arrays
+ */
+ uint16_t num_elements;
+ /**
+ * [in] Session resource allocations
+ */
+ uint16_t tcam_cnt[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+ /**
+ * [in] TCAM Locations reserved
+ */
+ struct tf_rm_resc_entry (*resv_res)[CFA_TCAM_MGR_TBL_TYPE_MAX];
+};
+
+/**
+ * TCAM Manager allocation parameters
+ */
+struct cfa_tcam_mgr_alloc_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of the allocation
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [in] Priority of entry requested (definition TBD)
+ */
+ uint16_t priority;
+ /**
+ * [out] Id of allocated entry or found entry (if search_enable)
+ */
+ uint16_t id;
+};
+
+/**
+ * TCAM Manager free parameters
+ */
+struct cfa_tcam_mgr_free_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of the allocation
+ * If the type is not known, set the type to CFA_TCAM_MGR_TBL_TYPE_MAX.
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to free
+ */
+ uint16_t id;
+};
+
+/**
+ * TCAM Manager set parameters
+ */
+struct cfa_tcam_mgr_set_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of object to set
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to write to
+ */
+ uint16_t id;
+ /**
+ * [in] array containing key
+ */
+ uint8_t *key;
+ /**
+ * [in] array containing mask fields
+ */
+ uint8_t *mask;
+ /**
+ * [in] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [in] array containing result
+ */
+ uint8_t *result;
+ /**
+ * [in] result size (bytes)
+ */
+ uint16_t result_size;
+};
+
+/**
+ * TCAM Manager get parameters
+ */
+struct cfa_tcam_mgr_get_parms {
+ /**
+ * [in] Receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] Type of object to get
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+ /**
+ * [in] Type of HCAPI
+ */
+ uint16_t hcapi_type;
+ /**
+ * [in] Entry ID to read
+ */
+ uint16_t id;
+ /**
+ * [out] array containing key
+ */
+ uint8_t *key;
+ /**
+ * [out] array containing mask fields
+ */
+ uint8_t *mask;
+ /**
+ * [out] key size (bytes)
+ */
+ uint16_t key_size;
+ /**
+ * [out] array containing result
+ */
+ uint8_t *result;
+ /**
+ * [out] result size (bytes)
+ */
+ uint16_t result_size;
+};
+
+/**
+ * cfa_tcam_mgr_shared_clear_parms parameter definition
+ */
+struct cfa_tcam_mgr_shared_clear_parms {
+ /**
+ * [in] receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] TCAM table type
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+};
+
+/**
+ * cfa_tcam_mgr_shared_move_parms parameter definition
+ */
+struct cfa_tcam_mgr_shared_move_parms {
+ /**
+ * [in] receive or transmit direction
+ */
+ enum tf_dir dir;
+ /**
+ * [in] TCAM table type
+ */
+ enum cfa_tcam_mgr_tbl_type type;
+};
+
+/**
+ * @page tcam TCAM Manager
+ *
+ * @ref cfa_tcam_mgr_init
+ *
+ * @ref cfa_tcam_mgr_get_phys_table_type
+ *
+ * @ref cfa_tcam_mgr_bind
+ *
+ * @ref cfa_tcam_mgr_unbind
+ *
+ * @ref cfa_tcam_mgr_alloc
+ *
+ * @ref cfa_tcam_mgr_free
+ *
+ * @ref cfa_tcam_mgr_set
+ *
+ * @ref cfa_tcam_mgr_get
+ *
+ */
+
+const char *
+cfa_tcam_mgr_tbl_2_str(enum cfa_tcam_mgr_tbl_type tcam_type);
+
+/**
+ * Initializes the TCAM Manager
+ *
+ * [in] type
+ * Device type
+ *
+ * Returns
+ * - (0) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_init(int sess_idx, enum cfa_tcam_mgr_device_type type,
+ struct cfa_tcam_mgr_init_parms *parms);
+
+/**
+ * Returns the physical TCAM table that a logical TCAM table uses.
+ *
+ * [in] type
+ * Logical table type
+ *
+ * Returns
+ * - (tf_tcam_tbl_type) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_get_phys_table_type(enum cfa_tcam_mgr_tbl_type type);
+
+/**
+ * Queries the capabilities of TCAM Manager.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [out] parms
+ * Pointer to parameters to be returned
+ *
+ * Returns
+ * - (0) if successful.
+ * - (<0) on failure.
+ */
+int
+cfa_tcam_mgr_qcaps(struct cfa_tcam_mgr_context *context __rte_unused,
+ struct cfa_tcam_mgr_qcaps_parms *parms);
+
+/**
+ * Initializes the TCAM module with the requested DBs. Must be
+ * invoked as the first thing before any of the access functions.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_bind(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_cfg_parms *parms);
+
+/**
+ * Cleans up the private DBs and releases all the data.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_unbind(struct cfa_tcam_mgr_context *context);
+
+/**
+ * Allocates the requested tcam type from the internal RM DB.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_alloc(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_alloc_parms *parms);
+
+/**
+ * Free's the requested table type and returns it to the DB.
+ * If refcount goes to 0 then it is returned to the table type DB.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_free(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms);
+
+/**
+ * Configures the requested element by sending a firmware request which
+ * then installs it into the device internal structures.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_set(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms);
+
+/**
+ * Retrieves the requested element by sending a firmware request to get
+ * the element.
+ *
+ * [in] context
+ * Pointer to context information
+ *
+ * [in] parms
+ * Pointer to parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int cfa_tcam_mgr_get(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_get_parms *parms);
+
+int
+cfa_tcam_mgr_tables_get(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t *start_row,
+ uint16_t *end_row,
+ uint16_t *max_entries,
+ uint16_t *slices);
+int
+cfa_tcam_mgr_tables_set(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type,
+ uint16_t start_row,
+ uint16_t end_row,
+ uint16_t max_entries);
+
+int cfa_tcam_mgr_shared_clear(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_clear_parms *parms);
+
+int cfa_tcam_mgr_shared_move(struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_shared_move_parms *parms);
+
+void cfa_tcam_mgr_rows_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type);
+void cfa_tcam_mgr_tables_dump(int sess_idx, enum tf_dir dir, enum cfa_tcam_mgr_tbl_type type);
+void cfa_tcam_mgr_entries_dump(int sess_idx);
+#endif /* _CFA_TCAM_MGR_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
new file mode 100644
index 0000000000..6ab9b5e118
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_device.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_DEVICE_H
+#define CFA_TCAM_MGR_DEVICE_H
+
+#include <inttypes.h>
+#include "cfa_tcam_mgr.h"
+
+/*
+ * This identifier is to be used for one-off variable sizes. Do not use it for
+ * sizing keys in an array.
+ */
+#define CFA_TCAM_MGR_MAX_KEY_SIZE 96
+
+/* Note that this macro's arguments are not macro expanded due to
+ * concatenation.
+ */
+#define TF_TCAM_TABLE_ROWS_DEF(_slices) \
+ struct cfa_tcam_mgr_table_rows_ ## _slices { \
+ uint16_t priority; \
+ uint8_t entry_size; /* Slices per entry */ \
+ uint8_t entry_inuse; /* bit[entry] set if in use */ \
+ uint16_t entries[_slices]; \
+ }
+
+/*
+ * Have to explicitly declare this struct since some compilers don't accept the
+ * GNU C extension of zero length arrays.
+ */
+struct cfa_tcam_mgr_table_rows_0 {
+ uint16_t priority;
+ uint8_t entry_size; /* Slices per entry */
+ uint8_t entry_inuse; /* bit[entry] set if in use */
+ uint16_t entries[];
+};
+
+TF_TCAM_TABLE_ROWS_DEF(1);
+TF_TCAM_TABLE_ROWS_DEF(2);
+TF_TCAM_TABLE_ROWS_DEF(4);
+TF_TCAM_TABLE_ROWS_DEF(8);
+
+#define TF_TCAM_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_ENTRIES + \
+ L2_CTXT_TCAM_TX_MAX_ENTRIES + \
+ PROF_TCAM_RX_MAX_ENTRIES + \
+ PROF_TCAM_TX_MAX_ENTRIES + \
+ WC_TCAM_RX_MAX_ENTRIES + \
+ WC_TCAM_TX_MAX_ENTRIES + \
+ SP_TCAM_RX_MAX_ENTRIES + \
+ SP_TCAM_TX_MAX_ENTRIES + \
+ CT_RULE_TCAM_RX_MAX_ENTRIES + \
+ CT_RULE_TCAM_TX_MAX_ENTRIES + \
+ VEB_TCAM_RX_MAX_ENTRIES + \
+ VEB_TCAM_TX_MAX_ENTRIES)
+
+struct cfa_tcam_mgr_entry_data {
+ uint16_t row;
+ uint8_t slice;
+ uint8_t ref_cnt;
+};
+
+struct cfa_tcam_mgr_table_data {
+ struct cfa_tcam_mgr_table_rows_0 *tcam_rows;
+ uint16_t hcapi_type;
+ uint16_t num_rows; /* Rows in physical TCAM */
+ uint16_t start_row; /* Where the logical TCAM starts */
+ uint16_t end_row; /* Where the logical TCAM ends */
+ uint16_t max_entries;
+ uint16_t used_entries;
+ uint8_t row_width; /* bytes */
+ uint8_t result_size; /* bytes */
+ uint8_t max_slices;
+};
+
+extern int cfa_tcam_mgr_max_entries[TF_TCAM_MAX_SESSIONS];
+
+extern struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables[TF_TCAM_MAX_SESSIONS][TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+
+/* HW OP definitions begin here */
+typedef int (*cfa_tcam_mgr_hwop_set_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_set_parms
+ *parms, int row, int slice,
+ int max_slices);
+typedef int (*cfa_tcam_mgr_hwop_get_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_get_parms
+ *parms, int row, int slice,
+ int max_slices);
+typedef int (*cfa_tcam_mgr_hwop_free_func_t)(int sess_idx,
+ struct cfa_tcam_mgr_free_parms
+ *parms, int row, int slice,
+ int max_slices);
+
+struct cfa_tcam_mgr_hwops_funcs {
+ cfa_tcam_mgr_hwop_set_func_t set;
+ cfa_tcam_mgr_hwop_get_func_t get;
+ cfa_tcam_mgr_hwop_free_func_t free;
+};
+#endif /* CFA_TCAM_MGR_DEVICE_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
new file mode 100644
index 0000000000..0fb5563cc3
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+/*
+ * This file will "do the right thing" for each of the primitives set, get and
+ * free. The TCAM manager is running in the core, so the tables will be cached.
+ * Set and free messages will also be sent to the firmware. Instead of sending
+ * get messages, the entry will be read from the cached copy thus saving a
+ * firmware message.
+ */
+
+#include "tf_tcam.h"
+#include "hcapi_cfa_defs.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_hwop_msg.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+#include "tf_session.h"
+#include "tf_msg.h"
+#include "tfp.h"
+#include "tf_util.h"
+
+/*
+ * The free hwop will free more than a single slice so cannot be used.
+ */
+struct cfa_tcam_mgr_hwops_funcs hwop_funcs;
+
+int
+cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type)
+{
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ return cfa_tcam_mgr_hwops_get_funcs_p4(&hwop_funcs);
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ return cfa_tcam_mgr_hwops_get_funcs_p58(&hwop_funcs);
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+}
+
+/*
+ * This is the glue between the TCAM manager and the firmware HW operations. It
+ * is intended to abstract out the location of the TCAM manager so that the TCAM
+ * manager code will be the same whether or not it is actually using the
+ * firmware.
+ */
+
+int
+cfa_tcam_mgr_entry_set_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_set_parms *parms,
+ int row, int slice,
+ int max_slices __rte_unused)
+{
+ cfa_tcam_mgr_hwop_set_func_t set_func;
+
+ set_func = hwop_funcs.set;
+ if (set_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ struct tf_tcam_set_parms sparms;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ int rc;
+ enum tf_tcam_tbl_type type =
+ cfa_tcam_mgr_get_phys_table_type(parms->type);
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ memset(&sparms, 0, sizeof(sparms));
+ sparms.dir = parms->dir;
+ sparms.type = type;
+ sparms.hcapi_type = parms->hcapi_type;
+ sparms.idx = (row * max_slices) + slice;
+ sparms.key = parms->key;
+ sparms.mask = parms->mask;
+ sparms.key_size = parms->key_size;
+ sparms.result = parms->result;
+ sparms.result_size = parms->result_size;
+
+ rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms);
+ if (rc) {
+ /* Log error */
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d set failed, rc:%d\n",
+ parms->id, -rc);
+ return rc;
+ }
+
+ return set_func(sess_idx, parms, row, slice, max_slices);
+}
+
+int
+cfa_tcam_mgr_entry_get_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_get_parms *parms,
+ int row, int slice,
+ int max_slices __rte_unused)
+{
+ cfa_tcam_mgr_hwop_get_func_t get_func;
+
+ get_func = hwop_funcs.get;
+ if (get_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ return get_func(sess_idx, parms, row, slice, max_slices);
+}
+
+int
+cfa_tcam_mgr_entry_free_msg(int sess_idx, struct cfa_tcam_mgr_context *context
+ __rte_unused,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice,
+ int key_size,
+ int result_size,
+ int max_slices)
+{
+ cfa_tcam_mgr_hwop_free_func_t free_func;
+
+ free_func = hwop_funcs.free;
+ if (free_func == NULL)
+ return -CFA_TCAM_MGR_ERR_CODE(PERM);
+
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+ int rc;
+ enum tf_tcam_tbl_type type =
+ cfa_tcam_mgr_get_phys_table_type(parms->type);
+
+ /* Free will clear an entire row. */
+ /* Use set message to clear an individual entry */
+ struct tf_tcam_set_parms sparms;
+ uint8_t key[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 };
+ uint8_t mask[CFA_TCAM_MGR_MAX_KEY_SIZE] = { 0 };
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(context->tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ if (key_size > CFA_TCAM_MGR_MAX_KEY_SIZE) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d key size is %d greater than:%d\n",
+ parms->id, key_size,
+ CFA_TCAM_MGR_MAX_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ if (result_size > CFA_TCAM_MGR_MAX_KEY_SIZE) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Entry %d result size is %d greater than:%d\n",
+ parms->id, result_size,
+ CFA_TCAM_MGR_MAX_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ memset(&sparms, 0, sizeof(sparms));
+ memset(&key, 0, sizeof(key));
+ memset(&mask, 0xff, sizeof(mask));
+
+ sparms.dir = parms->dir;
+ sparms.type = type;
+ sparms.hcapi_type = parms->hcapi_type;
+ sparms.key = key;
+ sparms.mask = mask;
+ sparms.result = key;
+ sparms.idx = (row * max_slices) + slice;
+ sparms.key_size = key_size;
+ sparms.result_size = result_size;
+
+ rc = tf_msg_tcam_entry_set(context->tfp, dev, &sparms);
+ if (rc) {
+ /* Log error */
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, parms->dir, parms->type,
+ "Row %d, slice %d set failed, "
+ "rc:%d.\n",
+ row,
+ slice,
+ rc);
+ return rc;
+ }
+ return free_func(sess_idx, parms, row, slice, max_slices);
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
new file mode 100644
index 0000000000..f7ba625c07
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_HWOP_MSG_H
+#define CFA_TCAM_MGR_HWOP_MSG_H
+
+int
+cfa_tcam_mgr_hwops_init(enum cfa_tcam_mgr_device_type type);
+
+int
+cfa_tcam_mgr_entry_set_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_set_parms *parms,
+ int row, int slice, int max_slices);
+int
+cfa_tcam_mgr_entry_get_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_get_parms *parms,
+ int row, int slice, int max_slices);
+int
+cfa_tcam_mgr_entry_free_msg(int sess_idx,
+ struct cfa_tcam_mgr_context *context,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int key_size,
+ int result_size, int max_slices);
+#endif /* CFA_TCAM_MGR_HWOP_MSG_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
new file mode 100644
index 0000000000..63c84c5938
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c
@@ -0,0 +1,921 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include "hcapi_cfa_defs.h"
+
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_p4.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_resource_types.h"
+#include "tfp.h"
+#include "assert.h"
+#include "tf_util.h"
+
+/*
+ * Sizings of the TCAMs on P4
+ */
+
+#define MAX_ROW_WIDTH 48
+#define MAX_RESULT_SIZE 8
+
+#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#endif
+
+/*
+ * TCAM definitions
+ *
+ * These define the TCAMs in HW.
+ *
+ * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported
+ * by HW or not supported by TCAM Manager.
+ */
+
+/** L2 Context TCAM */
+#define L2_CTXT_TCAM_RX_MAX_SLICES 1
+#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(167)
+#define L2_CTXT_TCAM_RX_NUM_ROWS 1024
+#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \
+ L2_CTXT_TCAM_RX_NUM_ROWS)
+#define L2_CTXT_TCAM_RX_RESULT_SIZE 8
+
+#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES
+#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH
+#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS
+#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES
+#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE
+
+/** Profile TCAM */
+#define PROF_TCAM_RX_MAX_SLICES 1
+#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(81)
+#define PROF_TCAM_RX_NUM_ROWS 1024
+#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \
+ PROF_TCAM_RX_NUM_ROWS)
+#define PROF_TCAM_RX_RESULT_SIZE 8
+
+#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES
+#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH
+#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS
+#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES
+#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE
+
+/** Wildcard TCAM */
+#define WC_TCAM_RX_MAX_SLICES 4
+/* 82 bits per slice */
+#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_WORD_ALIGN(82) * \
+ WC_TCAM_RX_MAX_SLICES)
+#define WC_TCAM_RX_NUM_ROWS 256
+#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define WC_TCAM_RX_RESULT_SIZE 4
+
+#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES
+#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH
+#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS
+#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES
+#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE
+
+/** Source Properties TCAM */
+#define SP_TCAM_RX_MAX_SLICES 1
+#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(89)
+#define SP_TCAM_RX_NUM_ROWS 512
+#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define SP_TCAM_RX_RESULT_SIZE 8
+
+#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES
+#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH
+#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS
+#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES
+#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE
+
+/** Connection Tracking Rule TCAM */
+#define CT_RULE_TCAM_RX_MAX_SLICES 1
+#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(16)
+#define CT_RULE_TCAM_RX_NUM_ROWS 0
+#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \
+ CT_RULE_TCAM_RX_NUM_ROWS)
+#define CT_RULE_TCAM_RX_RESULT_SIZE 8
+
+#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES
+#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH
+#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS
+#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES
+#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE
+
+/** Virtual Edge Bridge TCAM */
+#define VEB_TCAM_RX_MAX_SLICES 1
+#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(78)
+/* Tx only */
+#define VEB_TCAM_RX_NUM_ROWS 0
+#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+#define VEB_TCAM_RX_RESULT_SIZE 8
+
+#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES
+#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH
+#define VEB_TCAM_TX_NUM_ROWS 1024
+#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE
+
+/* Declare the table rows for each table here. If new tables are added to the
+ * enum tf_tcam_tbl_type, then new declarations will be needed here.
+ *
+ * The numeric suffix of the structure type indicates how many slices a
+ * particular TCAM supports.
+ *
+ * Array sizes have 1 added to avoid zero length arrays.
+ */
+
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables_p4[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ { /* RX */
+ { /* High AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* High APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* Low AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* Low APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_RX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_RX_MAX_ENTRIES,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_RX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if VEB_TCAM_RX_NUM_ROWS > 0
+ .end_row = VEB_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = VEB_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = VEB_TCAM_RX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ },
+ { /* TX */
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH,
+ },
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_TX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_TX_MAX_ENTRIES,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_SP_TCAM,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_TX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = VEB_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = VEB_TCAM_TX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P4_WC_TCAM,
+ },
+ },
+};
+
+static struct cfa_tcam_mgr_entry_data entry_data_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+static struct sbmp session_bmp_p4[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+int
+cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp)
+{
+ *session_bmp = session_bmp_p4[sess_idx];
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data)
+{
+ int max_row_width = 0;
+ int max_result_size = 0;
+ int dir, type;
+
+ *global_entry_data = entry_data_p4[sess_idx];
+
+ memcpy(&cfa_tcam_mgr_tables[sess_idx],
+ &cfa_tcam_mgr_tables_p4,
+ sizeof(cfa_tcam_mgr_tables[sess_idx]));
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width >
+ max_row_width)
+ max_row_width =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].row_width;
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size >
+ max_result_size)
+ max_result_size =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].result_size;
+ }
+ }
+
+ if (max_row_width != MAX_ROW_WIDTH) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_ROW_WIDTH (%d) does not match actual "
+ "value (%d).\n",
+ MAX_ROW_WIDTH,
+ max_row_width);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (max_result_size != MAX_RESULT_SIZE) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_RESULT_SIZE (%d) does not match actual "
+ "value (%d).\n",
+ MAX_RESULT_SIZE,
+ max_result_size);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ return 0;
+}
+
+/* HW OP declarations begin here */
+struct cfa_tcam_mgr_TCAM_row_data {
+ int key_size;
+ int result_size;
+ uint8_t key[MAX_ROW_WIDTH];
+ uint8_t mask[MAX_ROW_WIDTH];
+ uint8_t result[MAX_RESULT_SIZE];
+};
+
+/* These macros are only needed to avoid exceeding 80 columns */
+#define L2_CTXT_RX_MAX_ROWS \
+ (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS)
+#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS)
+#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define CT_RULE_RX_MAX_ROWS \
+ (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS)
+#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+
+#define L2_CTXT_TX_MAX_ROWS \
+ (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS)
+#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS)
+#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS)
+#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS)
+#define CT_RULE_TX_MAX_ROWS \
+ (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS)
+#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+
+static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = {
+ L2_CTXT_RX_MAX_ROWS,
+ L2_CTXT_RX_MAX_ROWS,
+ PROF_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ SP_RX_MAX_ROWS,
+ CT_RULE_RX_MAX_ROWS,
+ VEB_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS
+};
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data *
+row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = {
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ },
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ }
+};
+
+static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type)
+{
+ if (type >= TF_TCAM_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return cfa_tcam_mgr_max_rows[type];
+}
+
+static int cfa_tcam_mgr_hwop_set(int sess_idx,
+ struct cfa_tcam_mgr_set_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ this_row->key_size = parms->key_size;
+ memcpy(&this_row->key, parms->key, parms->key_size);
+ memcpy(&this_row->mask, parms->mask, parms->key_size);
+ this_row->result_size = parms->result_size;
+ if (parms->result != ((void *)0))
+ memcpy(&this_row->result, parms->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_get(int sess_idx,
+ struct cfa_tcam_mgr_get_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ parms->key_size = this_row->key_size;
+ parms->result_size = this_row->result_size;
+ if (parms->key != ((void *)0))
+ memcpy(parms->key, &this_row->key, parms->key_size);
+ if (parms->mask != ((void *)0))
+ memcpy(parms->mask, &this_row->mask, parms->key_size);
+ if (parms->result != ((void *)0))
+ memcpy(parms->result, &this_row->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_free(int sess_idx,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ memset(&this_row->key, 0, sizeof(this_row->key));
+ memset(&this_row->mask, 0, sizeof(this_row->mask));
+ memset(&this_row->result, 0, sizeof(this_row->result));
+ this_row->key_size = 0;
+ this_row->result_size = 0;
+ return 0;
+};
+
+int cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs)
+{
+ hwop_funcs->set = cfa_tcam_mgr_hwop_set;
+ hwop_funcs->get = cfa_tcam_mgr_hwop_get;
+ hwop_funcs->free = cfa_tcam_mgr_hwop_free;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
new file mode 100644
index 0000000000..3ca59b2aeb
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_P4_H
+#define CFA_TCAM_MGR_P4_H
+
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_sbmp.h"
+
+int
+cfa_tcam_mgr_init_p4(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data);
+
+int
+cfa_tcam_mgr_sess_table_get_p4(int sess_idx, struct sbmp **session_bmp);
+
+int
+cfa_tcam_mgr_hwops_get_funcs_p4(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs);
+#endif /* CFA_TCAM_MGR_P4_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
new file mode 100644
index 0000000000..c9a04dc4e9
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c
@@ -0,0 +1,926 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include "hcapi_cfa_defs.h"
+
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_resource_types.h"
+#include "tfp.h"
+#include "assert.h"
+#include "tf_util.h"
+
+/*
+ * Sizings of the TCAMs on P5
+ */
+
+#define MAX_ROW_WIDTH 96
+#define MAX_RESULT_SIZE 8
+
+#if MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#error MAX_ROW_WIDTH > CFA_TCAM_MGR_MAX_KEY_SIZE
+#endif
+
+/*
+ * TCAM definitions
+ *
+ * These define the TCAMs in HW.
+ *
+ * Note: Set xxx_TCAM_[R|T]X_NUM_ROWS to zero if a TCAM is either not supported
+ * by HW or not supported by TCAM Manager.
+ */
+
+/** L2 Context TCAM */
+#define L2_CTXT_TCAM_RX_MAX_SLICES 1
+#define L2_CTXT_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(214)
+#define L2_CTXT_TCAM_RX_NUM_ROWS 1024
+#define L2_CTXT_TCAM_RX_MAX_ENTRIES (L2_CTXT_TCAM_RX_MAX_SLICES * \
+ L2_CTXT_TCAM_RX_NUM_ROWS)
+#define L2_CTXT_TCAM_RX_RESULT_SIZE 8
+
+#define L2_CTXT_TCAM_TX_MAX_SLICES L2_CTXT_TCAM_RX_MAX_SLICES
+#define L2_CTXT_TCAM_TX_ROW_WIDTH L2_CTXT_TCAM_RX_ROW_WIDTH
+#define L2_CTXT_TCAM_TX_NUM_ROWS L2_CTXT_TCAM_RX_NUM_ROWS
+#define L2_CTXT_TCAM_TX_MAX_ENTRIES L2_CTXT_TCAM_RX_MAX_ENTRIES
+#define L2_CTXT_TCAM_TX_RESULT_SIZE L2_CTXT_TCAM_RX_RESULT_SIZE
+
+/** Profile TCAM */
+#define PROF_TCAM_RX_MAX_SLICES 1
+#define PROF_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(94)
+#define PROF_TCAM_RX_NUM_ROWS 256
+#define PROF_TCAM_RX_MAX_ENTRIES (PROF_TCAM_RX_MAX_SLICES * \
+ PROF_TCAM_RX_NUM_ROWS)
+#define PROF_TCAM_RX_RESULT_SIZE 8
+
+#define PROF_TCAM_TX_MAX_SLICES PROF_TCAM_RX_MAX_SLICES
+#define PROF_TCAM_TX_ROW_WIDTH PROF_TCAM_RX_ROW_WIDTH
+#define PROF_TCAM_TX_NUM_ROWS PROF_TCAM_RX_NUM_ROWS
+#define PROF_TCAM_TX_MAX_ENTRIES PROF_TCAM_RX_MAX_ENTRIES
+#define PROF_TCAM_TX_RESULT_SIZE PROF_TCAM_RX_RESULT_SIZE
+
+/** Wildcard TCAM */
+#define WC_TCAM_RX_MAX_SLICES 4
+/* 162 bits per slice */
+#define WC_TCAM_RX_ROW_WIDTH (TF_BITS2BYTES_64B_WORD_ALIGN(162) * \
+ WC_TCAM_RX_MAX_SLICES)
+#define WC_TCAM_RX_NUM_ROWS 2048
+#define WC_TCAM_RX_MAX_ENTRIES (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define WC_TCAM_RX_RESULT_SIZE 8
+
+#define WC_TCAM_TX_MAX_SLICES WC_TCAM_RX_MAX_SLICES
+#define WC_TCAM_TX_ROW_WIDTH WC_TCAM_RX_ROW_WIDTH
+#define WC_TCAM_TX_NUM_ROWS WC_TCAM_RX_NUM_ROWS
+#define WC_TCAM_TX_MAX_ENTRIES WC_TCAM_RX_MAX_ENTRIES
+#define WC_TCAM_TX_RESULT_SIZE WC_TCAM_RX_RESULT_SIZE
+
+/** Source Properties TCAM */
+#define SP_TCAM_RX_MAX_SLICES 1
+#define SP_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(89)
+#define SP_TCAM_RX_NUM_ROWS 0
+#define SP_TCAM_RX_MAX_ENTRIES (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define SP_TCAM_RX_RESULT_SIZE 8
+
+#define SP_TCAM_TX_MAX_SLICES SP_TCAM_RX_MAX_SLICES
+#define SP_TCAM_TX_ROW_WIDTH SP_TCAM_RX_ROW_WIDTH
+#define SP_TCAM_TX_NUM_ROWS SP_TCAM_RX_NUM_ROWS
+#define SP_TCAM_TX_MAX_ENTRIES SP_TCAM_RX_MAX_ENTRIES
+#define SP_TCAM_TX_RESULT_SIZE SP_TCAM_RX_RESULT_SIZE
+
+/** Connection Tracking Rule TCAM */
+#define CT_RULE_TCAM_RX_MAX_SLICES 1
+#define CT_RULE_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_64B_WORD_ALIGN(16)
+#define CT_RULE_TCAM_RX_NUM_ROWS 0
+#define CT_RULE_TCAM_RX_MAX_ENTRIES (CT_RULE_TCAM_RX_MAX_SLICES * \
+ CT_RULE_TCAM_RX_NUM_ROWS)
+#define CT_RULE_TCAM_RX_RESULT_SIZE 8
+
+#define CT_RULE_TCAM_TX_MAX_SLICES CT_RULE_TCAM_RX_MAX_SLICES
+#define CT_RULE_TCAM_TX_ROW_WIDTH CT_RULE_TCAM_RX_ROW_WIDTH
+#define CT_RULE_TCAM_TX_NUM_ROWS CT_RULE_TCAM_RX_NUM_ROWS
+#define CT_RULE_TCAM_TX_MAX_ENTRIES CT_RULE_TCAM_RX_MAX_ENTRIES
+#define CT_RULE_TCAM_TX_RESULT_SIZE CT_RULE_TCAM_RX_RESULT_SIZE
+
+/** Virtual Edge Bridge TCAM */
+#define VEB_TCAM_RX_MAX_SLICES 1
+#define VEB_TCAM_RX_ROW_WIDTH TF_BITS2BYTES_WORD_ALIGN(79)
+/* Tx only */
+#define VEB_TCAM_RX_NUM_ROWS 0
+#define VEB_TCAM_RX_MAX_ENTRIES (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+#define VEB_TCAM_RX_RESULT_SIZE 8
+
+#define VEB_TCAM_TX_MAX_SLICES VEB_TCAM_RX_MAX_SLICES
+#define VEB_TCAM_TX_ROW_WIDTH VEB_TCAM_RX_ROW_WIDTH
+#define VEB_TCAM_TX_NUM_ROWS 1024
+#define VEB_TCAM_TX_MAX_ENTRIES (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+#define VEB_TCAM_TX_RESULT_SIZE VEB_TCAM_RX_RESULT_SIZE
+
+/* Declare the table rows for each table here. If new tables are added to the
+ * enum tf_tcam_tbl_type, then new declarations will be needed here.
+ *
+ * The numeric suffix of the structure type indicates how many slices a
+ * particular TCAM supports.
+ *
+ * Array sizes have 1 added to avoid zero length arrays.
+ */
+
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[TF_TCAM_MAX_SESSIONS][L2_CTXT_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_RX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_PROF_TCAM_TX[TF_TCAM_MAX_SESSIONS][PROF_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_RX[TF_TCAM_MAX_SESSIONS][SP_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_SP_TCAM_TX[TF_TCAM_MAX_SESSIONS][SP_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[TF_TCAM_MAX_SESSIONS][CT_RULE_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_RX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_1
+ cfa_tcam_mgr_table_rows_VEB_TCAM_TX[TF_TCAM_MAX_SESSIONS][VEB_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_RX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+static struct cfa_tcam_mgr_table_rows_4
+ cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[TF_TCAM_MAX_SESSIONS][WC_TCAM_TX_NUM_ROWS + 1];
+
+struct cfa_tcam_mgr_table_data
+cfa_tcam_mgr_tables_p58[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX] = {
+ { /* RX */
+ { /* High AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* High APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* Low AFM */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* Low APPS */
+ .max_slices = L2_CTXT_TCAM_RX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_RX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_RX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_RX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_RX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_RX_MAX_SLICES,
+ .row_width = PROF_TCAM_RX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_RX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = 0,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_RX_MAX_SLICES,
+ .row_width = SP_TCAM_RX_ROW_WIDTH,
+ .num_rows = SP_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_RX_MAX_ENTRIES,
+ .result_size = SP_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_RX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_RX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_RX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_RX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_RX_MAX_SLICES,
+ .row_width = VEB_TCAM_RX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+#if VEB_TCAM_RX_NUM_ROWS > 0
+ .end_row = VEB_TCAM_RX_NUM_ROWS - 1,
+#else
+ .end_row = VEB_TCAM_RX_NUM_ROWS,
+#endif
+ .max_entries = VEB_TCAM_RX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_RX_MAX_SLICES,
+ .row_width = WC_TCAM_RX_ROW_WIDTH,
+ .num_rows = WC_TCAM_RX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_RX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_RX_MAX_ENTRIES,
+ .result_size = WC_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ },
+ { /* TX */
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2) - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
+ },
+ { /* AFM */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* APPS */
+ .max_slices = L2_CTXT_TCAM_TX_MAX_SLICES,
+ .row_width = L2_CTXT_TCAM_TX_ROW_WIDTH,
+ .num_rows = L2_CTXT_TCAM_TX_NUM_ROWS,
+ .start_row = (L2_CTXT_TCAM_TX_NUM_ROWS / 2),
+ .end_row = L2_CTXT_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = (L2_CTXT_TCAM_TX_MAX_ENTRIES / 2),
+ .result_size = L2_CTXT_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
+ },
+ { /* AFM */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* APPS */
+ .max_slices = PROF_TCAM_TX_MAX_SLICES,
+ .row_width = PROF_TCAM_TX_ROW_WIDTH,
+ .num_rows = PROF_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = PROF_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = PROF_TCAM_TX_MAX_ENTRIES,
+ .result_size = PROF_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_PROF_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = SP_TCAM_TX_MAX_SLICES,
+ .row_width = SP_TCAM_TX_ROW_WIDTH,
+ .num_rows = SP_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = SP_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = SP_TCAM_TX_MAX_ENTRIES,
+ .result_size = SP_TCAM_TX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* APPS */
+ .max_slices = CT_RULE_TCAM_TX_MAX_SLICES,
+ .row_width = CT_RULE_TCAM_TX_ROW_WIDTH,
+ .num_rows = CT_RULE_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+#if CT_RULE_TCAM_TX_NUM_ROWS > 0
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS - 1,
+#else
+ .end_row = CT_RULE_TCAM_TX_NUM_ROWS,
+#endif
+ .max_entries = CT_RULE_TCAM_TX_MAX_ENTRIES,
+ .result_size = CT_RULE_TCAM_RX_RESULT_SIZE,
+ },
+ { /* AFM */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* APPS */
+ .max_slices = VEB_TCAM_TX_MAX_SLICES,
+ .row_width = VEB_TCAM_TX_ROW_WIDTH,
+ .num_rows = VEB_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = VEB_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = VEB_TCAM_TX_MAX_ENTRIES,
+ .result_size = VEB_TCAM_RX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_VEB_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* AFM */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = 0,
+ .max_entries = 0,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ { /* APPS */
+ .max_slices = WC_TCAM_TX_MAX_SLICES,
+ .row_width = WC_TCAM_TX_ROW_WIDTH,
+ .num_rows = WC_TCAM_TX_NUM_ROWS,
+ .start_row = 0,
+ .end_row = WC_TCAM_TX_NUM_ROWS - 1,
+ .max_entries = WC_TCAM_TX_MAX_ENTRIES,
+ .result_size = WC_TCAM_TX_RESULT_SIZE,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_WC_TCAM,
+ },
+ },
+};
+
+static struct cfa_tcam_mgr_entry_data entry_data_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+static struct sbmp session_bmp_p58[TF_TCAM_MAX_SESSIONS][TF_TCAM_MAX_ENTRIES];
+
+int
+cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp)
+{
+ *session_bmp = session_bmp_p58[sess_idx];
+ return 0;
+}
+
+int
+cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data)
+{
+ int max_row_width = 0;
+ int max_result_size = 0;
+ int dir, type;
+
+ *global_entry_data = entry_data_p58[sess_idx];
+
+ memcpy(&cfa_tcam_mgr_tables[sess_idx],
+ &cfa_tcam_mgr_tables_p58,
+ sizeof(cfa_tcam_mgr_tables[sess_idx]));
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_L2_CTXT_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_PROF_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_SP_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_CT_RULE_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_RX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_VEB_TCAM_TX[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_HIGH[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_RX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_RX_LOW[sess_idx];
+
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_AFM].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+ cfa_tcam_mgr_tables[sess_idx][TF_DIR_TX]
+ [CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS].tcam_rows =
+ (struct cfa_tcam_mgr_table_rows_0 *)
+ &cfa_tcam_mgr_table_rows_WC_TCAM_TX_LOW[sess_idx];
+
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < CFA_TCAM_MGR_TBL_TYPE_MAX; type++) {
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].row_width >
+ max_row_width)
+ max_row_width =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].row_width;
+ if (cfa_tcam_mgr_tables[sess_idx][dir][type].result_size >
+ max_result_size)
+ max_result_size =
+ cfa_tcam_mgr_tables[sess_idx][dir][type].result_size;
+ }
+ }
+
+ if (max_row_width != MAX_ROW_WIDTH) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_ROW_WIDTH (%d) does not match actual "
+ "value (%d).\n",
+ MAX_ROW_WIDTH,
+ max_row_width);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ if (max_result_size != MAX_RESULT_SIZE) {
+ CFA_TCAM_MGR_LOG(ERR,
+ "MAX_RESULT_SIZE (%d) does not match actual "
+ "value (%d).\n",
+ MAX_RESULT_SIZE,
+ max_result_size);
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+ return 0;
+}
+
+/* HW OP declarations begin here */
+
+struct cfa_tcam_mgr_TCAM_row_data {
+ int key_size;
+ int result_size;
+ uint8_t key[MAX_ROW_WIDTH];
+ uint8_t mask[MAX_ROW_WIDTH];
+ uint8_t result[MAX_RESULT_SIZE];
+};
+
+/* These macros are only needed to avoid exceeding 80 columns */
+#define L2_CTXT_RX_MAX_ROWS \
+ (L2_CTXT_TCAM_RX_MAX_SLICES * L2_CTXT_TCAM_RX_NUM_ROWS)
+#define PROF_RX_MAX_ROWS (PROF_TCAM_RX_MAX_SLICES * PROF_TCAM_RX_NUM_ROWS)
+#define WC_RX_MAX_ROWS (WC_TCAM_RX_MAX_SLICES * WC_TCAM_RX_NUM_ROWS)
+#define SP_RX_MAX_ROWS (SP_TCAM_RX_MAX_SLICES * SP_TCAM_RX_NUM_ROWS)
+#define CT_RULE_RX_MAX_ROWS \
+ (CT_RULE_TCAM_RX_MAX_SLICES * CT_RULE_TCAM_RX_NUM_ROWS)
+#define VEB_RX_MAX_ROWS (VEB_TCAM_RX_MAX_SLICES * VEB_TCAM_RX_NUM_ROWS)
+
+#define L2_CTXT_TX_MAX_ROWS \
+ (L2_CTXT_TCAM_TX_MAX_SLICES * L2_CTXT_TCAM_TX_NUM_ROWS)
+#define PROF_TX_MAX_ROWS (PROF_TCAM_TX_MAX_SLICES * PROF_TCAM_TX_NUM_ROWS)
+#define WC_TX_MAX_ROWS (WC_TCAM_TX_MAX_SLICES * WC_TCAM_TX_NUM_ROWS)
+#define SP_TX_MAX_ROWS (SP_TCAM_TX_MAX_SLICES * SP_TCAM_TX_NUM_ROWS)
+#define CT_RULE_TX_MAX_ROWS \
+ (CT_RULE_TCAM_TX_MAX_SLICES * CT_RULE_TCAM_TX_NUM_ROWS)
+#define VEB_TX_MAX_ROWS (VEB_TCAM_TX_MAX_SLICES * VEB_TCAM_TX_NUM_ROWS)
+
+static int cfa_tcam_mgr_max_rows[TF_TCAM_TBL_TYPE_MAX] = {
+ L2_CTXT_RX_MAX_ROWS,
+ L2_CTXT_RX_MAX_ROWS,
+ PROF_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ SP_RX_MAX_ROWS,
+ CT_RULE_RX_MAX_ROWS,
+ VEB_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS,
+ WC_RX_MAX_ROWS
+};
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][PROF_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][SP_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][VEB_RX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[TF_TCAM_MAX_SESSIONS][WC_RX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][L2_CTXT_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][PROF_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][SP_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][CT_RULE_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][VEB_TX_MAX_ROWS];
+static struct cfa_tcam_mgr_TCAM_row_data
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[TF_TCAM_MAX_SESSIONS][WC_TX_MAX_ROWS];
+
+static struct cfa_tcam_mgr_TCAM_row_data *
+row_tables[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX] = {
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_RX_row_data[0],
+ },
+ {
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_L2_CTXT_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_PROF_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_SP_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_CT_RULE_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_VEB_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ cfa_tcam_mgr_WC_TCAM_TX_row_data[0],
+ }
+};
+
+static int cfa_tcam_mgr_get_max_rows(enum tf_tcam_tbl_type type)
+{
+ if (type >= TF_TCAM_TBL_TYPE_MAX)
+ assert(0);
+ else
+ return cfa_tcam_mgr_max_rows[type];
+}
+
+static int cfa_tcam_mgr_hwop_set(int sess_idx,
+ struct cfa_tcam_mgr_set_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ this_row->key_size = parms->key_size;
+ memcpy(&this_row->key, parms->key, parms->key_size);
+ memcpy(&this_row->mask, parms->mask, parms->key_size);
+ this_row->result_size = parms->result_size;
+ if (parms->result != ((void *)0))
+ memcpy(&this_row->result, parms->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_get(int sess_idx,
+ struct cfa_tcam_mgr_get_parms *parms, int row,
+ int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ parms->key_size = this_row->key_size;
+ parms->result_size = this_row->result_size;
+ if (parms->key != ((void *)0))
+ memcpy(parms->key, &this_row->key, parms->key_size);
+ if (parms->mask != ((void *)0))
+ memcpy(parms->mask, &this_row->mask, parms->key_size);
+ if (parms->result != ((void *)0))
+ memcpy(parms->result, &this_row->result, parms->result_size);
+ return 0;
+};
+
+static int cfa_tcam_mgr_hwop_free(int sess_idx,
+ struct cfa_tcam_mgr_free_parms *parms,
+ int row, int slice, int max_slices)
+{
+ struct cfa_tcam_mgr_TCAM_row_data *this_table;
+ struct cfa_tcam_mgr_TCAM_row_data *this_row;
+ this_table = row_tables[parms->dir]
+ [cfa_tcam_mgr_get_phys_table_type(parms->type)];
+ this_table += (sess_idx *
+ cfa_tcam_mgr_get_max_rows(cfa_tcam_mgr_get_phys_table_type(parms->type)));
+ this_row = &this_table[row * max_slices + slice];
+ memset(&this_row->key, 0, sizeof(this_row->key));
+ memset(&this_row->mask, 0, sizeof(this_row->mask));
+ memset(&this_row->result, 0, sizeof(this_row->result));
+ this_row->key_size = 0;
+ this_row->result_size = 0;
+ return 0;
+};
+
+int cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs
+ *hwop_funcs)
+{
+ hwop_funcs->set = cfa_tcam_mgr_hwop_set;
+ hwop_funcs->get = cfa_tcam_mgr_hwop_get;
+ hwop_funcs->free = cfa_tcam_mgr_hwop_free;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
new file mode 100644
index 0000000000..7640f91911
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_P58_H
+#define CFA_TCAM_MGR_P58_H
+
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_sbmp.h"
+
+int
+cfa_tcam_mgr_init_p58(int sess_idx, struct cfa_tcam_mgr_entry_data **global_entry_data);
+
+int
+cfa_tcam_mgr_sess_table_get_p58(int sess_idx, struct sbmp **session_bmp);
+
+int
+cfa_tcam_mgr_hwops_get_funcs_p58(struct cfa_tcam_mgr_hwops_funcs *hwop_funcs);
+#endif /* CFA_TCAM_MGR_P58_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
new file mode 100644
index 0000000000..6ad158abe8
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_SBMP_H
+#define CFA_TCAM_MGR_SBMP_H
+
+#include <inttypes.h>
+
+#include "cfa_tcam_mgr.h"
+
+#define SBMP_SESSION_MAX TF_TCAM_MAX_SESSIONS
+#if SBMP_SESSION_MAX <= 16
+#define SBMP_WORD_WIDTH 16
+#else
+#define SBMP_WORD_WIDTH 32
+#endif
+
+#define SBMP_WIDTH (((SBMP_SESSION_MAX + SBMP_WORD_WIDTH - 1) / \
+ SBMP_WORD_WIDTH) * SBMP_WORD_WIDTH)
+#define SBMP_WORD_MAX ((SBMP_WIDTH + SBMP_WORD_WIDTH - 1) / SBMP_WORD_WIDTH)
+
+struct sbmp {
+#if SBMP_WORD_WIDTH == 16
+ uint16_t bits[SBMP_WORD_MAX];
+#elif SBMP_WORD_WIDTH == 32
+ uint32_t bits[SBMP_WORD_MAX];
+#else
+ uint64_t bits[SBMP_WORD_MAX];
+#endif
+};
+
+#define SBMP_WORD_GET(bm, word) ((bm).bits[(word)])
+
+#if SBMP_WORD_MAX == 1
+#define SBMP_WENT(session) (0)
+#define SBMP_WBIT(session) (1U << (session))
+#define SBMP_CLEAR(bm) (SBMP_WORD_GET(bm, 0) = 0)
+#define SBMP_IS_NULL(bm) (SBMP_WORD_GET(bm, 0) == 0)
+#define SBMP_COUNT(bm, count) \
+ (count = __builtin_popcount(SBMP_WORD_GET(bm, 0)))
+#elif SBMP_WORD_MAX == 2
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = 0; \
+ } while (0)
+#define SBMP_IS_NULL(bm) \
+ (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0)
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 1))); \
+ } while (0)
+#elif SBMP_WORD_MAX == 3
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ SBMP_WORD_GET(*_bm, 0) = SBMP_WORD_GET(*_bm, 1) = \
+ SBMP_WORD_GET(*_bm, 2) = 0; \
+ } while (0)
+#define SBMP_IS_NULL(bm) \
+ (SBMP_WORD_GET(bm, 0) == 0 && SBMP_WORD_GET(bm, 1) == 0 && \
+ SBMP_WORD_GET(bm, 2) == 0)
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ count = __builtin_popcount(SBMP_WORD_GET(*_bm, 0)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 1)) + \
+ __builtin_popcount(SBMP_WORD_GET(*_bm, 2)); \
+ } while (0)
+#else /* SBMP_WORD_MAX > 3 */
+#define SBMP_WENT(session) ((session) / SBMP_WORD_WIDTH)
+#define SBMP_WBIT(session) (1U << ((session) % SBMP_WORD_WIDTH))
+#define SBMP_CLEAR(bm) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ int _w; \
+ for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \
+ SBMP_WORD_GET(*_bm, _w) = 0; \
+ } \
+ } while (0)
+#define SBMP_IS_NULL(bm) (sbmp_bmnull(&(bm)))
+#define SBMP_COUNT(bm, count) \
+ do { \
+ typeof(bm) *_bm = &(bm); \
+ int _count, _w; \
+ _count = 0; \
+ for (_w = 0; _w < SBMP_WORD_MAX; _w++) { \
+ _count += __builtin_popcount(SBMP_WORD_GET(*_bm, _w)); \
+ } \
+ count = _count; \
+ } while (0)
+
+/* Only needed if SBMP_WORD_MAX > 3 */
+static int
+sbmp_bmnull(struct ebmp *bmp)
+{
+ int i;
+
+ for (i = 0; i < SBMP_WORD_MAX; i++) {
+ if (SBMP_WORD_GET(*bmp, i) != 0)
+ return 0;
+ }
+ return 1;
+}
+#endif
+
+/* generics that use the previously defined helpers */
+#define SBMP_NOT_NULL(bm) (!SBMP_IS_NULL(bm))
+
+#define SBMP_ENTRY(bm, session) \
+ (SBMP_WORD_GET(bm, SBMP_WENT(session)))
+#define SBMP_MEMBER(bm, session) \
+ ((SBMP_ENTRY(bm, session) & SBMP_WBIT(session)) != 0)
+#define SBMP_SESSION_ADD(bm, session) \
+ (SBMP_ENTRY(bm, session) |= SBMP_WBIT(session))
+#define SBMP_SESSION_REMOVE(bm, session) \
+ (SBMP_ENTRY(bm, session) &= ~SBMP_WBIT(session))
+#endif /* CFA_TCAM_MGR_SBMP_H */
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
new file mode 100644
index 0000000000..3d085bc69e
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.c
@@ -0,0 +1,377 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <inttypes.h>
+#include "hcapi_cfa_defs.h"
+#include "tf_util.h"
+#include "cfa_tcam_mgr.h"
+#include "cfa_tcam_mgr_device.h"
+#include "cfa_tcam_mgr_session.h"
+#include "cfa_tcam_mgr_sbmp.h"
+#include "tfp.h"
+#include "cfa_tcam_mgr_p58.h"
+#include "cfa_tcam_mgr_p4.h"
+
+struct cfa_tcam_mgr_session_data {
+ uint32_t session_id;
+ /* The following are per-session values */
+ uint16_t max_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ uint16_t used_entries[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+};
+
+static struct cfa_tcam_mgr_session_data session_data[TF_TCAM_MAX_SESSIONS];
+
+static uint16_t last_entry_id;
+
+static struct sbmp *session_bmp[TF_TCAM_MAX_SESSIONS];
+
+int
+cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type)
+{
+ int rc;
+
+ switch (type) {
+ case CFA_TCAM_MGR_DEVICE_TYPE_P4:
+ case CFA_TCAM_MGR_DEVICE_TYPE_SR:
+ rc = cfa_tcam_mgr_sess_table_get_p4(sess_idx, &session_bmp[sess_idx]);
+ break;
+ case CFA_TCAM_MGR_DEVICE_TYPE_P5:
+ rc = cfa_tcam_mgr_sess_table_get_p58(sess_idx, &session_bmp[sess_idx]);
+ break;
+ default:
+ CFA_TCAM_MGR_LOG(ERR, "No such device %d\n", type);
+ rc = -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ return rc;
+}
+
+int
+cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context,
+ uint32_t *session_id)
+{
+ if (context == NULL) {
+ CFA_TCAM_MGR_LOG_0(ERR, "context passed as NULL pointer.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+ }
+
+ *session_id = context->tfp->session->session_id.id;
+ return 0;
+}
+
+int
+cfa_tcam_mgr_session_find(unsigned int session_id)
+{
+ unsigned int sess_idx;
+
+ for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) {
+ if (session_data[sess_idx].session_id == session_id)
+ return sess_idx;
+ }
+
+ return -CFA_TCAM_MGR_ERR_CODE(INVAL);
+}
+
+int
+cfa_tcam_mgr_session_add(unsigned int session_id)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx >= 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session is already bound.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(BUSY);
+ }
+
+ /* Session not found in table, find first empty entry. */
+ for (sess_idx = 0;
+ sess_idx < (signed int)ARRAY_SIZE(session_data);
+ sess_idx++) {
+ if (session_data[sess_idx].session_id == 0)
+ break;
+ }
+
+ if (sess_idx >= (signed int)ARRAY_SIZE(session_data)) {
+ /* No room in the session table */
+ CFA_TCAM_MGR_LOG_0(ERR, "Session table is full.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NOMEM);
+ }
+
+ session_data[sess_idx].session_id = session_id;
+
+ return sess_idx;
+}
+
+int
+cfa_tcam_mgr_session_free(unsigned int session_id,
+ struct cfa_tcam_mgr_context *context)
+{
+ struct cfa_tcam_mgr_free_parms free_parms;
+ int entry_id;
+ int sess_idx = cfa_tcam_mgr_session_find(session_id);
+
+ if (sess_idx < 0)
+ return sess_idx;
+
+ memset(&free_parms, 0, sizeof(free_parms));
+ /* Since we are freeing all pending TCAM entries (which is typically
+ * done during tcam_unbind), we don't know the type of each entry.
+ * So we set the type to MAX as a hint to cfa_tcam_mgr_free() to
+ * figure out the actual type. We need to set it through each
+ * iteration in the loop below; otherwise, the type determined for
+ * the first entry would be used for subsequent entries that may or
+ * may not be of the same type, resulting in errors.
+ */
+ for (entry_id = 0; entry_id < cfa_tcam_mgr_max_entries[sess_idx]; entry_id++) {
+ if (SBMP_MEMBER(session_bmp[sess_idx][entry_id], sess_idx)) {
+ SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx);
+
+ free_parms.id = entry_id;
+ free_parms.type = CFA_TCAM_MGR_TBL_TYPE_MAX;
+ cfa_tcam_mgr_free(context, &free_parms);
+ }
+ }
+
+ memset(&session_data[sess_idx], 0, sizeof(session_data[sess_idx]));
+ return 0;
+}
+
+int
+cfa_tcam_mgr_session_cfg(unsigned int session_id,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX])
+{
+ struct cfa_tcam_mgr_table_data *table_data;
+ struct cfa_tcam_mgr_session_data *session_entry;
+ unsigned int dir, type;
+ int sess_idx = cfa_tcam_mgr_session_find(session_id);
+ uint16_t requested_cnt;
+
+ if (sess_idx < 0)
+ return sess_idx;
+
+ session_entry = &session_data[sess_idx];
+
+ /* Validate session request */
+ for (dir = 0; dir < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx]); dir++) {
+ for (type = 0;
+ type < ARRAY_SIZE(cfa_tcam_mgr_tables[sess_idx][dir]);
+ type++) {
+ table_data = &cfa_tcam_mgr_tables[sess_idx][dir][type];
+ requested_cnt = tcam_cnt[dir][type];
+ /*
+ * Only check if table supported (max_entries > 0).
+ */
+ if (table_data->max_entries > 0 &&
+ requested_cnt > table_data->max_entries) {
+ CFA_TCAM_MGR_LOG_DIR_TYPE(ERR, dir, type,
+ "Requested %d, available %d.\n",
+ requested_cnt,
+ table_data->max_entries);
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+ }
+ }
+
+ memcpy(session_entry->max_entries, tcam_cnt,
+ sizeof(session_entry->max_entries));
+ return 0;
+}
+
+void
+cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type dst_type,
+ enum cfa_tcam_mgr_tbl_type src_type)
+{
+ session_data[sess_idx].used_entries[dir][dst_type]++;
+ session_data[sess_idx].used_entries[dir][src_type]--;
+}
+
+int
+cfa_tcam_mgr_session_entry_alloc(unsigned int session_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ if (session_data[sess_idx].used_entries[dir][type] >=
+ session_data[sess_idx].max_entries[dir][type]) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Table full (session).\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NOSPC);
+ }
+
+ do {
+ last_entry_id++;
+ if (cfa_tcam_mgr_max_entries[sess_idx] <= last_entry_id)
+ last_entry_id = 0;
+ } while (!SBMP_IS_NULL(session_bmp[sess_idx][last_entry_id]));
+
+ SBMP_SESSION_ADD(session_bmp[sess_idx][last_entry_id], sess_idx);
+
+ session_data[sess_idx].used_entries[dir][type] += 1;
+
+ return last_entry_id;
+}
+
+int
+cfa_tcam_mgr_session_entry_free(unsigned int session_id,
+ unsigned int entry_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type)
+{
+ int sess_idx;
+
+ sess_idx = cfa_tcam_mgr_session_find(session_id);
+ if (sess_idx < 0) {
+ CFA_TCAM_MGR_LOG_0(ERR, "Session not found.\n");
+ return -CFA_TCAM_MGR_ERR_CODE(NODEV);
+ }
+
+ SBMP_SESSION_REMOVE(session_bmp[sess_idx][entry_id], sess_idx);
+ session_data[sess_idx].used_entries[dir][type] -= 1;
+
+ return 0;
+}
+
+#if SBMP_WORD_WIDTH == 16
+#define SBMP_FORMAT PRIX16
+#define SBMP_PRECISION "4"
+#elif SBMP_WORD_WIDTH == 32
+#define SBMP_FORMAT PRIX32
+#define SBMP_PRECISION "8"
+#elif SBMP_WORD_WIDTH == 64
+#define SBMP_FORMAT PRIX64
+#define SBMP_PRECISION "16"
+#else
+#error "Invalid value for SBMP_WORD_WIDTH."
+#endif
+
+static void
+cfa_tcam_mgr_session_bitmap_print(struct sbmp *session_bmp)
+{
+ unsigned int i;
+
+ printf("0x");
+ for (i = 0;
+ i < ARRAY_SIZE(session_bmp->bits);
+ i++) {
+ printf("%0" SBMP_PRECISION SBMP_FORMAT,
+ session_bmp->bits[i]);
+ }
+}
+
+#define SESSION_DUMP_HEADER_1 " RX TX\n"
+#define SESSION_DUMP_HEADER_2 \
+ " Max Used Max Used\n"
+
+static void
+cfa_tcam_mgr_session_printf(struct cfa_tcam_mgr_session_data *session,
+ enum cfa_tcam_mgr_tbl_type tbl_type)
+{
+ printf("%-22s: %5u %5u %5u %5u\n",
+ cfa_tcam_mgr_tbl_2_str(tbl_type),
+ session->max_entries[TF_DIR_RX][tbl_type],
+ session->used_entries[TF_DIR_RX][tbl_type],
+ session->max_entries[TF_DIR_TX][tbl_type],
+ session->used_entries[TF_DIR_TX][tbl_type]);
+}
+
+void
+cfa_tcam_mgr_sessions_dump(void)
+{
+ struct cfa_tcam_mgr_session_data *session;
+ unsigned int sess_idx;
+ bool sess_found = false;
+ enum cfa_tcam_mgr_tbl_type tbl_type;
+
+ printf("\nTCAM Sessions Table:\n");
+ for (sess_idx = 0; sess_idx < ARRAY_SIZE(session_data); sess_idx++) {
+ if (session_data[sess_idx].session_id != 0) {
+ session = &session_data[sess_idx];
+ if (!sess_found) {
+ printf(SESSION_DUMP_HEADER_1);
+ printf(SESSION_DUMP_HEADER_2);
+ }
+ printf("Session 0x%08x:\n",
+ session->session_id);
+ for (tbl_type = CFA_TCAM_MGR_TBL_TYPE_START;
+ tbl_type < CFA_TCAM_MGR_TBL_TYPE_MAX;
+ tbl_type++) {
+ cfa_tcam_mgr_session_printf(session, tbl_type);
+ }
+ sess_found = true;
+ }
+ }
+
+ if (!sess_found)
+ printf("No sessions found.\n");
+}
+
+/* This dumps all the sessions using an entry */
+void
+cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id)
+{
+ bool session_found = false;
+
+ if (id >= cfa_tcam_mgr_max_entries[sess_idx]) {
+ printf("Entry ID %u out of range for sess_idx %d. Max ID %u.\n",
+ id, sess_idx, cfa_tcam_mgr_max_entries[sess_idx] - 1);
+ return;
+ }
+
+ if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) {
+ printf("Sessions using entry ID %u:\n", id);
+ for (sess_idx = 0; sess_idx < SBMP_SESSION_MAX; sess_idx++)
+ if (SBMP_MEMBER(session_bmp[sess_idx][id], (sess_idx))) {
+ if (session_data[sess_idx].session_id != 0) {
+ printf("0x%08x (index %d)\n",
+ session_data[sess_idx].session_id,
+ sess_idx);
+ session_found = true;
+ } else {
+ printf("Error! Entry ID %u used by "
+ "session index %d which is not "
+ "in use.\n",
+ id, sess_idx);
+ }
+ }
+ if (!session_found)
+ printf("No sessions using entry ID %u.\n", id);
+ } else {
+ printf("Entry ID %u not in use.\n",
+ id);
+ return;
+ }
+}
+
+/* This dumps all the entries in use by any session */
+void
+cfa_tcam_mgr_session_entries_dump(int sess_idx)
+{
+ bool entry_found = false;
+ uint16_t id;
+
+ printf("\nGlobal Maximum Entries for sess_idx %d: %d\n\n",
+ sess_idx, cfa_tcam_mgr_max_entries[sess_idx]);
+ printf("TCAM Session Entry Table:\n");
+ for (id = 0; id < cfa_tcam_mgr_max_entries[sess_idx]; id++) {
+ if (!SBMP_IS_NULL(session_bmp[sess_idx][id])) {
+ if (!entry_found)
+ printf(" EID Session bitmap\n");
+ printf("%5u ", id);
+ cfa_tcam_mgr_session_bitmap_print(&session_bmp[sess_idx][id]);
+ printf("\n");
+ entry_found = true;
+ }
+ }
+
+ if (!entry_found)
+ printf("No entries found.\n");
+}
diff --git a/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
new file mode 100644
index 0000000000..69311b7e1d
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/cfa_tcam_mgr_session.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef CFA_TCAM_MGR_SESSION_H
+#define CFA_TCAM_MGR_SESSION_H
+
+#include <inttypes.h>
+#include "cfa_tcam_mgr.h"
+
+int
+cfa_tcam_mgr_session_init(int sess_idx, enum cfa_tcam_mgr_device_type type);
+
+int
+cfa_tcam_mgr_get_session_from_context(struct cfa_tcam_mgr_context *context,
+ uint32_t *session_id);
+
+int
+cfa_tcam_mgr_session_find(unsigned int session_id);
+
+int
+cfa_tcam_mgr_session_add(unsigned int session_id);
+
+int
+cfa_tcam_mgr_session_free(unsigned int session_id,
+ struct cfa_tcam_mgr_context *context);
+
+int
+cfa_tcam_mgr_session_cfg(unsigned int session_id,
+ uint16_t tcam_cnt[][CFA_TCAM_MGR_TBL_TYPE_MAX]);
+
+int
+cfa_tcam_mgr_session_entry_alloc(unsigned int session_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type);
+int
+cfa_tcam_mgr_session_entry_free(unsigned int session_id,
+ unsigned int entry_id,
+ enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type type);
+
+void
+cfa_tcam_mgr_sessions_dump(void);
+void
+cfa_tcam_mgr_entry_sessions_dump(int sess_idx, uint16_t id);
+void
+cfa_tcam_mgr_session_entries_dump(int sess_idx);
+
+void
+cfa_tcam_mgr_mv_session_used_entries_cnt(int sess_idx, enum tf_dir dir,
+ enum cfa_tcam_mgr_tbl_type dst_type,
+ enum cfa_tcam_mgr_tbl_type src_type);
+#endif /* CFA_TCAM_MGR_SESSION_H */
diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build
index f812e471d1..ae44aa34cf 100644
--- a/drivers/net/bnxt/tf_core/meson.build
+++ b/drivers/net/bnxt/tf_core/meson.build
@@ -1,36 +1,42 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2021 Broadcom
+# Copyright(c) 2023 Broadcom
#Include the folder for headers
includes += include_directories('.')
#Add the source files
sources += files(
- 'tf_core.c',
'bitalloc.c',
- 'tf_msg.c',
- 'll.c',
+ 'cfa_tcam_mgr.c',
+ 'cfa_tcam_mgr_hwop_msg.c',
+ 'cfa_tcam_mgr_p4.c',
+ 'cfa_tcam_mgr_p58.c',
+ 'cfa_tcam_mgr_session.c',
'dpool.c',
+ 'll.c',
'rand.c',
'stack.c',
- 'tf_rm.c',
- 'tf_tbl.c',
- 'tf_tbl_sram.c',
- 'tf_sram_mgr.c',
+ 'tf_core.c',
+ 'tf_device.c',
+ 'tf_device_p4.c',
+ 'tf_device_p58.c',
'tf_em_common.c',
+ 'tf_em_hash_internal.c',
'tf_em_host.c',
'tf_em_internal.c',
- 'tf_em_hash_internal.c',
- 'tfp.c',
- 'tf_util.c',
- 'tf_device.c',
- 'tf_device_p4.c',
'tf_global_cfg.c',
+ 'tf_hash.c',
'tf_identifier.c',
'tf_if_tbl.c',
+ 'tf_msg.c',
+ 'tfp.c',
+ 'tf_rm.c',
'tf_session.c',
+ 'tf_sram_mgr.c',
+ 'tf_tbl.c',
+ 'tf_tbl_sram.c',
'tf_tcam.c',
+ 'tf_tcam_mgr_msg.c',
'tf_tcam_shared.c',
- 'tf_hash.c',
- 'tf_device_p58.c')
+ 'tf_util.c')
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 038e439101..3a812bee3a 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -34,8 +34,8 @@ tf_open_session(struct tf *tfp,
* side. It is assumed that the Firmware will be supported if
* firmware open session succeeds.
*/
- if (parms->device_type != TF_DEVICE_TYPE_WH &&
- parms->device_type != TF_DEVICE_TYPE_THOR &&
+ if (parms->device_type != TF_DEVICE_TYPE_P4 &&
+ parms->device_type != TF_DEVICE_TYPE_P5 &&
parms->device_type != TF_DEVICE_TYPE_SR) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
@@ -83,7 +83,7 @@ tf_open_session(struct tf *tfp,
return rc;
TFP_DRV_LOG(INFO,
- "domain:%d, bus:%d, device:%u\n",
+ "domain:%x, bus:%x, device:%u\n",
parms->session_id.internal.domain,
parms->session_id.internal.bus,
parms->session_id.internal.device);
@@ -176,7 +176,7 @@ tf_close_session(struct tf *tfp)
return rc;
TFP_DRV_LOG(INFO,
- "domain:%d, bus:%d, device:%d\n",
+ "domain:%d, bus:%x, device:%d\n",
cparms.session_id->internal.domain,
cparms.session_id->internal.bus,
cparms.session_id->internal.device);
@@ -742,7 +742,6 @@ tf_set_tcam_entry(struct tf *tfp,
memset(&sparms, 0, sizeof(struct tf_tcam_set_parms));
-
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -790,6 +789,10 @@ tf_set_tcam_entry(struct tf *tfp,
strerror(-rc));
return rc;
}
+ TFP_DRV_LOG(DEBUG,
+ "%s: TCAM type %d set idx:%d key size %d result size %d\n",
+ tf_dir_2_str(parms->dir), sparms.type,
+ sparms.idx, sparms.key_size, sparms.result_size);
return 0;
}
@@ -807,7 +810,6 @@ tf_get_tcam_entry(struct tf *tfp __rte_unused,
memset(&gparms, 0, sizeof(struct tf_tcam_get_parms));
-
/* Retrieve the session information */
rc = tf_session_get_session(tfp, &tfs);
if (rc) {
@@ -1812,8 +1814,8 @@ int tf_get_version(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_WH &&
- parms->device_type != TF_DEVICE_TYPE_THOR &&
+ if (parms->device_type != TF_DEVICE_TYPE_P4 &&
+ parms->device_type != TF_DEVICE_TYPE_P5 &&
parms->device_type != TF_DEVICE_TYPE_SR) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
@@ -1845,7 +1847,7 @@ int tf_query_sram_resources(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1927,7 +1929,7 @@ int tf_set_sram_policy(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1968,7 +1970,7 @@ int tf_get_sram_policy(struct tf *tfp,
/* This function can be called before open session, filter
* out any non-supported device types on the Core side.
*/
- if (parms->device_type != TF_DEVICE_TYPE_THOR) {
+ if (parms->device_type != TF_DEVICE_TYPE_P5) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
@@ -1997,3 +1999,31 @@ int tf_get_sram_policy(struct tf *tfp,
return rc;
}
+
+int tf_set_session_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_set_hotup_state(tfp, parms);
+ if (rc)
+ return rc;
+
+ return rc;
+}
+
+int tf_get_session_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+
+ TF_CHECK_PARMS1(tfp);
+
+ rc = tf_session_get_hotup_state(tfp, parms);
+ if (rc)
+ return rc;
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index f5fe0a9098..3da1d2a5ca 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -112,6 +112,10 @@ enum tf_sram_bank_id {
* @ref tf_attach_session
*
* @ref tf_close_session
+ *
+ * @ref tf_get_session_info
+ *
+ * @ref tf_get_session_info
*/
/**
@@ -188,10 +192,10 @@ struct tf_session_version {
* Session supported device types
*/
enum tf_device_type {
- TF_DEVICE_TYPE_WH = 0, /**< Whitney+ */
- TF_DEVICE_TYPE_SR, /**< Stingray */
- TF_DEVICE_TYPE_THOR, /**< Thor */
- TF_DEVICE_TYPE_MAX /**< Maximum */
+ TF_DEVICE_TYPE_P4 = 0,
+ TF_DEVICE_TYPE_SR,
+ TF_DEVICE_TYPE_P5,
+ TF_DEVICE_TYPE_MAX
};
/**
@@ -286,6 +290,8 @@ enum tf_tbl_type {
TF_TBL_TYPE_ACT_ENCAP_32B,
/** Wh+/SR/TH Action Encap 64 Bytes */
TF_TBL_TYPE_ACT_ENCAP_64B,
+ /* TH Action Encap 128 Bytes */
+ TF_TBL_TYPE_ACT_ENCAP_128B,
/** WH+/SR/TH Action Source Properties SMAC */
TF_TBL_TYPE_ACT_SP_SMAC,
/** Wh+/SR/TH Action Source Properties SMAC IPv4 */
@@ -331,7 +337,7 @@ enum tf_tbl_type {
* External table type - initially 1 poolsize entries.
* All External table types are associated with a table
* scope. Internal types are not. Currently this is
- * a pool of 64B entries.
+ * a pool of 128B entries.
*/
TF_TBL_TYPE_EXT,
TF_TBL_TYPE_MAX
@@ -914,6 +920,71 @@ int tf_attach_session(struct tf *tfp,
*/
int tf_close_session(struct tf *tfp);
+/**
+ * tf_set_session_hotup_state parameter definition.
+ */
+struct tf_set_session_hotup_state_parms {
+ /**
+ * [in] the structure is used to set the state of
+ * the hotup shared session.
+ *
+ */
+ uint16_t state;
+};
+
+/**
+ * set hot upgrade shared session state
+ *
+ * This API is used to set the state of the shared session.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to set hotup state parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_set_session_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms);
+
+/**
+ * tf_get_session_hotup_state parameter definition.
+ */
+struct tf_get_session_hotup_state_parms {
+ /**
+ * [out] the structure is used to get the state of
+ * the hotup shared session.
+ *
+ */
+ uint16_t state;
+ /**
+ * [out] get the ref_cnt of the hotup shared session.
+ *
+ */
+ uint16_t ref_cnt;
+};
+
+/**
+ * get hot upgrade shared session state
+ *
+ * This API is used to set the state of the shared session.
+ *
+ * [in] tfp
+ * Pointer to TF handle
+ *
+ * [in] parms
+ * Pointer to get hotup state parameters
+ *
+ * Returns
+ * - (0) if successful.
+ * - (-EINVAL) on failure.
+ */
+int tf_get_session_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms);
+
/**
* @page ident Identity Management
*
@@ -1192,8 +1263,6 @@ int tf_free_tbl_scope(struct tf *tfp,
*
* @ref tf_get_tcam_entry
*
- * @ref tf_free_tcam_entry
- *
* @ref tf_move_tcam_shared_entries
*
* @ref tf_clear_tcam_shared_entries
@@ -1258,7 +1327,7 @@ struct tf_search_tcam_entry_parms {
};
/**
- * search TCAM entry (experimental)
+ * search TCAM entry
*
* Search for a TCAM entry
*
@@ -1732,7 +1801,7 @@ struct tf_get_shared_tbl_increment_parms {
* tf_get_shared_tbl_increment
*
* This API is currently only required for use in the shared
- * session for Thor (p58) actions. An increment count is returned per
+ * session for P5 actions. An increment count is returned per
* type to indicate how much to increment the start by for each
* entry (see tf_resource_info)
*
@@ -1898,6 +1967,7 @@ struct tf_insert_em_entry_parms {
*/
uint64_t flow_id;
};
+
/**
* tf_delete_em_entry parameter definition
*/
@@ -1927,6 +1997,7 @@ struct tf_delete_em_entry_parms {
*/
uint64_t flow_handle;
};
+
/**
* tf_move_em_entry parameter definition
*/
@@ -1969,6 +2040,7 @@ struct tf_move_em_entry_parms {
*/
uint64_t flow_handle;
};
+
/**
* tf_search_em_entry parameter definition (Future)
*/
@@ -2108,6 +2180,7 @@ int tf_search_em_entry(struct tf *tfp,
*
* @ref tf_get_global_cfg
*/
+
/**
* Tunnel Encapsulation Offsets
*/
@@ -2121,6 +2194,7 @@ enum tf_tunnel_encap_offsets {
TF_TUNNEL_ENCAP_GRE,
TF_TUNNEL_ENCAP_FULL_GENERIC
};
+
/**
* Global Configuration Table Types
*/
@@ -2193,9 +2267,8 @@ int tf_set_global_cfg(struct tf *tfp,
* @ref tf_set_if_tbl_entry
*
* @ref tf_get_if_tbl_entry
- *
- * @ref tf_restore_if_tbl_entry
*/
+
/**
* Enumeration of TruFlow interface table types.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 1c97218b5b..02a9ebd7b2 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -332,7 +332,7 @@ tf_dev_unbind_p4(struct tf *tfp)
}
/**
- * Device specific bind function, THOR
+ * Device specific bind function, P5
*
* [in] tfp
* Pointer to TF handle
@@ -504,7 +504,7 @@ tf_dev_bind_p58(struct tf *tfp,
}
/**
- * Device specific unbind function, THOR
+ * Device specific unbind function, P5
*
* [in] tfp
* Pointer to TF handle
@@ -602,14 +602,14 @@ tf_dev_bind(struct tf *tfp __rte_unused,
struct tf_dev_info *dev_handle)
{
switch (type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
dev_handle->type = type;
return tf_dev_bind_p4(tfp,
resources,
dev_handle,
wc_num_slices);
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
dev_handle->type = type;
return tf_dev_bind_p58(tfp,
resources,
@@ -627,11 +627,11 @@ tf_dev_bind_ops(enum tf_device_type type,
struct tf_dev_info *dev_handle)
{
switch (type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
dev_handle->ops = &tf_dev_ops_p4_init;
break;
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
dev_handle->ops = &tf_dev_ops_p58_init;
break;
default:
@@ -648,10 +648,10 @@ tf_dev_unbind(struct tf *tfp,
struct tf_dev_info *dev_handle)
{
switch (dev_handle->type) {
- case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_P4:
case TF_DEVICE_TYPE_SR:
return tf_dev_unbind_p4(tfp);
- case TF_DEVICE_TYPE_THOR:
+ case TF_DEVICE_TYPE_P5:
return tf_dev_unbind_p58(tfp);
default:
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index 5a42180719..06c17a7212 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 72c6b1cde8..911ea92471 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -296,11 +296,15 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp,
return rc;
/* Single slice support */
-#define CFA_P4_WC_TCAM_SLICE_SIZE 12
-
+#define CFA_P4_WC_TCAM_SLICE_SIZE (12)
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = tfs->wc_num_slices_per_row;
- if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
+ if (key_sz <= 1 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+ else if (key_sz <= 2 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else if (key_sz <= 4 * CFA_P4_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW;
+ else
return -ENOTSUP;
} else { /* for other type of tcam */
*num_slices_per_row = 1;
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index f8b424ebc9..6916c50fdc 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -16,6 +16,7 @@
#include "tfp.h"
#include "tf_msg_common.h"
#include "tf_tbl_sram.h"
+#include "tf_util.h"
#define TF_DEV_P58_PARIF_MAX 16
#define TF_DEV_P58_PF_MASK 0xfUL
@@ -79,33 +80,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
[TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 8,
+ .slices = 16,
},
/* Policy - Encaps in bank 2 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_128B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
@@ -116,49 +123,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
/* Policy - SP in bank 0 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 2,
+ .slices = 4,
},
/* Policy - Stats in bank 3 */
[TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
@@ -192,33 +199,39 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
[TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
- .slices = 8,
+ .slices = 16,
},
/* Policy - Encaps in bank 2 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
+ .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
+ .slices = 2,
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_128B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
@@ -229,49 +242,49 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 2,
+ .slices = 4,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
- .slices = 1,
+ .slices = 2,
},
/* Policy - SP in bank 0 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 8,
+ .slices = 16,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 4,
+ .slices = 8,
},
[TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
.parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
- .slices = 2,
+ .slices = 4,
},
/* Policy - Stats in bank 3 */
[TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
.cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
.hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
- .slices = 8,
+ .slices = 16,
},
};
@@ -406,10 +419,15 @@ tf_dev_p58_get_tcam_slice_info(struct tf *tfp,
if (rc)
return rc;
-#define CFA_P58_WC_TCAM_SLICE_SIZE 24
+#define CFA_P58_WC_TCAM_SLICE_SIZE (24)
if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
- *num_slices_per_row = tfs->wc_num_slices_per_row;
- if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
+ if (key_sz <= 1 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW;
+ else if (key_sz <= 2 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW;
+ else if (key_sz <= 4 * CFA_P58_WC_TCAM_SLICE_SIZE)
+ *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW;
+ else
return -ENOTSUP;
} else { /* for other type of tcam */
*num_slices_per_row = 1;
@@ -452,6 +470,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
case TF_TBL_TYPE_ACT_SP_SMAC:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
@@ -461,7 +480,7 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_MODIFY_16B:
case TF_TBL_TYPE_ACT_MODIFY_32B:
case TF_TBL_TYPE_ACT_MODIFY_64B:
- parms->increment_cnt = 8;
+ parms->increment_cnt = 16;
break;
default:
parms->increment_cnt = 1;
@@ -493,6 +512,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
case TF_TBL_TYPE_ACT_SP_SMAC:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
@@ -527,7 +547,7 @@ static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
*
* [in/out] shift
* Pointer to the factor to be used as a multiplier to translate
- * between the RM units to the user address. SRAM manages 64B entries
+ * between the RM units to the user address. SRAM manages 128B entries
* Addresses must be shifted to an 8B address.
*
* Returns
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index b56b7cc188..c518150d1f 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1000,8 +1000,8 @@ tf_em_ext_common_unbind(struct tf *tfp)
strerror(-rc));
return rc;
}
- ext_db = (struct em_ext_db *)ext_ptr;
+ ext_db = (struct em_ext_db *)ext_ptr;
if (ext_db != NULL) {
entry = ext_db->tbl_scope_ll.head;
while (entry != NULL) {
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 8ea5d93672..46de63a9da 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -7,7 +7,6 @@
#include <rte_common.h>
#include <rte_errno.h>
#include <rte_log.h>
-
#include "tf_core.h"
#include "tf_util.h"
#include "tf_common.h"
@@ -63,7 +62,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return -1;
}
-
rptr_index = index;
rc = tf_msg_insert_em_internal_entry(tfp,
parms,
@@ -75,6 +73,7 @@ tf_em_insert_int_entry(struct tf *tfp,
dpool_free(pool, index);
return -1;
}
+
TF_SET_GFID(gfid,
((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) |
rptr_entry),
@@ -95,7 +94,6 @@ tf_em_insert_int_entry(struct tf *tfp,
return 0;
}
-
/** Delete EM internal entry API
*
* returns:
@@ -253,7 +251,6 @@ tf_em_int_bind(struct tf *tfp,
return db_rc[TF_DIR_RX];
}
-
if (!tf_session_is_shared_session(tfs)) {
for (i = 0; i < TF_DIR_MAX; i++) {
iparms.rm_db = em_db->em_db[i];
@@ -335,11 +332,10 @@ tf_em_int_unbind(struct tf *tfp)
}
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr);
- if (rc) {
+ if (rc)
return 0;
- }
- em_db = (struct em_rm_db *)em_db_ptr;
+ em_db = (struct em_rm_db *)em_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
if (em_db->em_db[i] == NULL)
continue;
diff --git a/drivers/net/bnxt/tf_core/tf_identifier.c b/drivers/net/bnxt/tf_core/tf_identifier.c
index 1846675916..7d9d9595dd 100644
--- a/drivers/net/bnxt/tf_core/tf_identifier.c
+++ b/drivers/net/bnxt/tf_core/tf_identifier.c
@@ -89,6 +89,7 @@ tf_ident_unbind(struct tf *tfp)
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_IDENTIFIER, &ident_db_ptr);
if (rc)
return 0;
+
ident_db = (struct ident_rm_db *)ident_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
diff --git a/drivers/net/bnxt/tf_core/tf_if_tbl.c b/drivers/net/bnxt/tf_core/tf_if_tbl.c
index e667d6fa6d..578d361417 100644
--- a/drivers/net/bnxt/tf_core/tf_if_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_if_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -21,12 +21,6 @@ struct tf_if_tbl_db {
struct tf_if_tbl_cfg *if_tbl_cfg_db[TF_DIR_MAX];
};
-/**
- * Init flag, set on bind and cleared on unbind
- * TODO: Store this data in session db
- */
-static uint8_t init;
-
/**
* Convert if_tbl_type to hwrm type.
*
@@ -80,8 +74,6 @@ tf_if_tbl_bind(struct tf *tfp,
if_tbl_db->if_tbl_cfg_db[TF_DIR_TX] = parms->cfg;
tf_session_set_if_tbl_db(tfp, (void *)if_tbl_db);
- init = 1;
-
TFP_DRV_LOG(INFO,
"Table Type - initialized\n");
@@ -92,14 +84,7 @@ int
tf_if_tbl_unbind(struct tf *tfp)
{
int rc;
- struct tf_if_tbl_db *if_tbl_db_ptr;
-
- /* Bail if nothing has been initialized */
- if (!init) {
- TFP_DRV_LOG(INFO,
- "No Table DBs created\n");
- return 0;
- }
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
TF_CHECK_PARMS1(tfp);
@@ -108,9 +93,15 @@ tf_if_tbl_unbind(struct tf *tfp)
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ /* Bail if nothing has been initialized */
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(INFO,
+ "No Table DBs created\n");
+ return 0;
+ }
tfp_free((void *)if_tbl_db_ptr);
- init = 0;
+ tf_session_set_if_tbl_db(tfp, NULL);
return 0;
}
@@ -120,24 +111,24 @@ tf_if_tbl_set(struct tf *tfp,
struct tf_if_tbl_set_parms *parms)
{
int rc;
- struct tf_if_tbl_db *if_tbl_db_ptr;
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
struct tf_if_tbl_get_hcapi_parms hparms;
TF_CHECK_PARMS3(tfp, parms, parms->data);
- if (!init) {
- TFP_DRV_LOG(ERR,
- "%s: No Table DBs created\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(ERR,
+ "%s: No Table DBs created\n",
+ tf_dir_2_str(parms->dir));
+ return -EINVAL;
+ }
+
/* Convert TF type to HCAPI type */
hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir];
hparms.db_index = parms->type;
@@ -163,24 +154,24 @@ tf_if_tbl_get(struct tf *tfp,
struct tf_if_tbl_get_parms *parms)
{
int rc = 0;
- struct tf_if_tbl_db *if_tbl_db_ptr;
+ struct tf_if_tbl_db *if_tbl_db_ptr = NULL;
struct tf_if_tbl_get_hcapi_parms hparms;
TF_CHECK_PARMS3(tfp, parms, parms->data);
- if (!init) {
- TFP_DRV_LOG(ERR,
- "%s: No Table DBs created\n",
- tf_dir_2_str(parms->dir));
- return -EINVAL;
- }
-
rc = tf_session_get_if_tbl_db(tfp, (void **)&if_tbl_db_ptr);
if (rc) {
TFP_DRV_LOG(INFO, "No IF Table DBs initialized\n");
return 0;
}
+ if (!if_tbl_db_ptr) {
+ TFP_DRV_LOG(ERR,
+ "%s: No Table DBs created\n",
+ tf_dir_2_str(parms->dir));
+ return -EINVAL;
+ }
+
/* Convert TF type to HCAPI type */
hparms.tbl_db = if_tbl_db_ptr->if_tbl_cfg_db[parms->dir];
hparms.db_index = parms->type;
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index fbc96d374c..1c66c7e01a 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -47,7 +47,6 @@ static_assert(sizeof(struct hwrm_tf_global_cfg_set_input) ==
static_assert(sizeof(struct hwrm_tf_em_insert_input) ==
TF_MSG_SIZE_HWRM_TF_EM_INSERT,
"HWRM message size changed: hwrm_tf_em_insert_input");
-
#define TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET 128
static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) ==
TF_MSG_SIZE_HWRM_TF_TBL_TYPE_SET,
@@ -61,13 +60,18 @@ static_assert(sizeof(struct hwrm_tf_tbl_type_set_input) ==
/**
* This is the length of shared session name "tf_share"
*/
-#define TF_SHARED_SESSION_NAME_LEN 8
+#define TF_SHARED_SESSION_NAME_LEN 9
/**
* This is the length of tcam shared session name "tf_shared-wc_tcam"
*/
#define TF_TCAM_SHARED_SESSION_NAME_LEN 17
+/**
+ * This is the length of tcam shared session name "tf_shared-poolx"
+ */
+#define TF_POOL_SHARED_SESSION_NAME_LEN 16
+
/**
* If data bigger than TF_PCI_BUF_SIZE_MAX then use DMA method
*/
@@ -135,18 +139,30 @@ tf_msg_session_open(struct bnxt *bp,
struct hwrm_tf_session_open_input req = { 0 };
struct hwrm_tf_session_open_output resp = { 0 };
struct tfp_send_msg_parms parms = { 0 };
- int name_len;
char *session_name;
char *tcam_session_name;
+ char *pool_session_name;
- /* Populate the request */
- name_len = strnlen(ctrl_chan_name, TF_SESSION_NAME_MAX);
- session_name = &ctrl_chan_name[name_len - strlen("tf_shared")];
- tcam_session_name = &ctrl_chan_name[name_len - strlen("tf_shared-wc_tcam")];
- if (!strncmp(tcam_session_name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam")))
- tfp_memcpy(&req.session_name, tcam_session_name, TF_TCAM_SHARED_SESSION_NAME_LEN);
- else if (!strncmp(session_name, "tf_shared", strlen("tf_shared")))
- tfp_memcpy(&req.session_name, session_name, TF_SHARED_SESSION_NAME_LEN);
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ * "tf_shared" is used by both verions.
+ */
+ tcam_session_name = strstr(ctrl_chan_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(ctrl_chan_name, "tf_shared-pool");
+ session_name = strstr(ctrl_chan_name, "tf_shared");
+ if (tcam_session_name)
+ tfp_memcpy(&req.session_name,
+ tcam_session_name,
+ TF_TCAM_SHARED_SESSION_NAME_LEN);
+ else if (pool_session_name)
+ tfp_memcpy(&req.session_name,
+ pool_session_name,
+ TF_POOL_SHARED_SESSION_NAME_LEN);
+ else if (session_name)
+ tfp_memcpy(&req.session_name,
+ session_name,
+ TF_SHARED_SESSION_NAME_LEN);
else
tfp_memcpy(&req.session_name, ctrl_chan_name, TF_SESSION_NAME_MAX);
@@ -191,9 +207,9 @@ tf_msg_session_client_register(struct tf *tfp,
struct tfp_send_msg_parms parms = { 0 };
uint8_t fw_session_id;
struct tf_dev_info *dev;
- int name_len;
char *session_name;
char *tcam_session_name;
+ char *pool_session_name;
/* Retrieve the device information */
rc = tf_session_get_device(tfs, &dev);
@@ -214,24 +230,31 @@ tf_msg_session_client_register(struct tf *tfp,
/* Populate the request */
req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
- name_len = strnlen(ctrl_channel_name, TF_SESSION_NAME_MAX);
- session_name = &ctrl_channel_name[name_len - strlen("tf_shared")];
- tcam_session_name = &ctrl_channel_name[name_len -
- strlen("tf_shared-wc_tcam")];
- if (!strncmp(tcam_session_name,
- "tf_shared-wc_tcam",
- strlen("tf_shared-wc_tcam")))
+
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ * "tf_shared" is used by both verions.
+ */
+ tcam_session_name = strstr(ctrl_channel_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(ctrl_channel_name, "tf_shared-pool");
+ session_name = strstr(ctrl_channel_name, "tf_shared");
+ if (tcam_session_name)
+ tfp_memcpy(&req.session_client_name,
+ tcam_session_name,
+ TF_TCAM_SHARED_SESSION_NAME_LEN);
+ else if (pool_session_name)
tfp_memcpy(&req.session_client_name,
- tcam_session_name,
- TF_TCAM_SHARED_SESSION_NAME_LEN);
- else if (!strncmp(session_name, "tf_shared", strlen("tf_shared")))
+ pool_session_name,
+ TF_POOL_SHARED_SESSION_NAME_LEN);
+ else if (session_name)
tfp_memcpy(&req.session_client_name,
- session_name,
- TF_SHARED_SESSION_NAME_LEN);
+ session_name,
+ TF_SHARED_SESSION_NAME_LEN);
else
tfp_memcpy(&req.session_client_name,
- ctrl_channel_name,
- TF_SESSION_NAME_MAX);
+ ctrl_channel_name,
+ TF_SESSION_NAME_MAX);
parms.tf_type = HWRM_TF_SESSION_REGISTER;
parms.req_data = (uint32_t *)&req;
@@ -431,7 +454,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp,
/* Post process the response */
data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr;
-
for (i = 0; i < resp.size; i++) {
query[i].type = tfp_le_to_cpu_32(data[i].type);
query[i].min = tfp_le_to_cpu_16(data[i].min);
@@ -1757,6 +1779,7 @@ tf_msg_set_tbl_entry(struct tf *tfp,
struct hwrm_tf_tbl_type_set_input req = { 0 };
struct hwrm_tf_tbl_type_set_output resp = { 0 };
struct tfp_send_msg_parms parms = { 0 };
+ struct tf_msg_dma_buf buf = { 0 };
uint8_t fw_session_id;
struct tf_dev_info *dev;
struct tf_session *tfs;
@@ -1802,18 +1825,19 @@ tf_msg_set_tbl_entry(struct tf *tfp,
/* Check for data size conformity */
if (size > TF_MSG_TBL_TYPE_SET_DATA_SIZE) {
- rc = -EINVAL;
- TFP_DRV_LOG(ERR,
- "%s: Invalid parameters for msg type, rc:%s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
+ /* use dma buffer */
+ req.flags |= HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA;
+ rc = tf_msg_alloc_dma_buf(&buf, size);
+ if (rc)
+ goto cleanup;
+ tfp_memcpy(buf.va_addr, data, size);
+ tfp_memcpy(&req.data[0],
+ &buf.pa_addr,
+ sizeof(buf.pa_addr));
+ } else {
+ tfp_memcpy(&req.data, data, size);
}
- tfp_memcpy(&req.data,
- data,
- size);
-
parms.tf_type = HWRM_TF_TBL_TYPE_SET;
parms.req_data = (uint32_t *)&req;
parms.req_size = sizeof(req);
@@ -1823,10 +1847,10 @@ tf_msg_set_tbl_entry(struct tf *tfp,
rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
&parms);
- if (rc)
- return rc;
+cleanup:
+ tf_msg_free_dma_buf(&buf);
- return 0;
+ return rc;
}
int
@@ -2325,3 +2349,114 @@ tf_msg_get_version(struct bnxt *bp,
return rc;
}
+
+int
+tf_msg_session_set_hotup_state(struct tf *tfp, uint16_t state)
+{
+ int rc;
+ struct hwrm_tf_session_hotup_state_set_input req = { 0 };
+ struct hwrm_tf_session_hotup_state_set_output resp = { 0 };
+ struct tfp_send_msg_parms parms = { 0 };
+ uint8_t fw_session_id;
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup device, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_session_get_fw_session_id(tfp, &fw_session_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Unable to lookup FW id, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Populate the request */
+ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
+ req.state = tfp_cpu_to_le_16(state);
+
+ parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_SET;
+ parms.req_data = (uint32_t *)&req;
+ parms.req_size = sizeof(req);
+ parms.resp_data = (uint32_t *)&resp;
+ parms.resp_size = sizeof(resp);
+ parms.mailbox = dev->ops->tf_dev_get_mailbox();
+
+ rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
+ &parms);
+ return rc;
+}
+
+int
+tf_msg_session_get_hotup_state(struct tf *tfp,
+ uint16_t *state,
+ uint16_t *ref_cnt)
+{
+ int rc;
+ struct hwrm_tf_session_hotup_state_get_input req = { 0 };
+ struct hwrm_tf_session_hotup_state_get_output resp = { 0 };
+ struct tfp_send_msg_parms parms = { 0 };
+ uint8_t fw_session_id;
+ struct tf_dev_info *dev;
+ struct tf_session *tfs;
+
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup session, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Failed to lookup device, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_session_get_fw_session_id(tfp, &fw_session_id);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Unable to lookup FW id, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ /* Populate the request */
+ req.fw_session_id = tfp_cpu_to_le_32(fw_session_id);
+
+ parms.tf_type = HWRM_TF_SESSION_HOTUP_STATE_GET;
+ parms.req_data = (uint32_t *)&req;
+ parms.req_size = sizeof(req);
+ parms.resp_data = (uint32_t *)&resp;
+ parms.resp_size = sizeof(resp);
+ parms.mailbox = dev->ops->tf_dev_get_mailbox();
+
+ rc = tfp_send_msg_direct(tf_session_get_bp(tfp),
+ &parms);
+
+ *state = tfp_le_to_cpu_16(resp.state);
+ *ref_cnt = tfp_le_to_cpu_16(resp.ref_cnt);
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h
index 188b361d71..24d0ae5f43 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.h
+++ b/drivers/net/bnxt/tf_core/tf_msg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -761,4 +761,40 @@ int
tf_msg_get_version(struct bnxt *bp,
struct tf_dev_info *dev,
struct tf_get_version_parms *parms);
+
+/**
+ * Send set hot upgrade state request to the firmware.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [in] state
+ * Hot upgrade session state
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_msg_session_set_hotup_state(struct tf *tfp,
+ uint16_t state);
+
+/**
+ * Send get hot upgrade state request to the firmware.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [out] state
+ * Pointer to hot upgrade session state
+ *
+ * [out] ref_cnt
+ * Pointer to hot upgrade session reference count
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_msg_session_get_hotup_state(struct tf *tfp,
+ uint16_t *state,
+ uint16_t *ref_cnt);
#endif /* _TF_MSG_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index d2045921b9..1fccb698d0 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -1,15 +1,12 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include <rte_common.h>
#include <rte_debug.h>
-
#include <cfa_resource_types.h>
-
#include "tf_rm.h"
#include "tf_common.h"
#include "tf_util.h"
@@ -18,9 +15,6 @@
#include "tfp.h"
#include "tf_msg.h"
-/* Logging defines */
-#define TF_RM_DEBUG 0
-
/**
* Generic RM Element data type that an RM DB is build upon.
*/
@@ -210,45 +204,6 @@ tf_rm_adjust_index(struct tf_rm_element *db,
return rc;
}
-/**
- * Logs an array of found residual entries to the console.
- *
- * [in] dir
- * Receive or transmit direction
- *
- * [in] module
- * Type of Device Module
- *
- * [in] count
- * Number of entries in the residual array
- *
- * [in] residuals
- * Pointer to an array of residual entries. Array is index same as
- * the DB in which this function is used. Each entry holds residual
- * value for that entry.
- */
-#if (TF_RM_DEBUG == 1)
-static void
-tf_rm_log_residuals(enum tf_dir dir,
- enum tf_module_type module,
- uint16_t count,
- uint16_t *residuals)
-{
- int i;
-
- /* Walk the residual array and log the types that wasn't
- * cleaned up to the console.
- */
- for (i = 0; i < count; i++) {
- if (residuals[i] != 0)
- TFP_DRV_LOG(INFO,
- "%s, %s was not cleaned up, %d outstanding\n",
- tf_dir_2_str(dir),
- tf_module_subtype_2_str(module, i),
- residuals[i]);
- }
-}
-#endif /* TF_RM_DEBUG == 1 */
/**
* Performs a check of the passed in DB for any lingering elements. If
* a resource type was found to not have been cleaned up by the caller
@@ -364,12 +319,6 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db,
*resv_size = found;
}
-#if (TF_RM_DEBUG == 1)
- tf_rm_log_residuals(rm_db->dir,
- rm_db->module,
- rm_db->num_entries,
- residuals);
-#endif
tfp_free((void *)residuals);
*resv = local_resv;
@@ -419,7 +368,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
bool shared_session)
{
int parent, child;
- const char *type_str;
+ const char *type_str = NULL;
/* Search through all the elements */
for (parent = 0; parent < num_elements; parent++) {
@@ -444,11 +393,6 @@ tf_rm_update_parent_reservations(struct tf *tfp,
dev->ops->tf_dev_get_resource_str(tfp,
cfg[parent].hcapi_type,
&type_str);
-#if (TF_RM_DEBUG == 1)
- printf("%s:%s cnt(%d) slices(%d)\n",
- type_str, tf_tbl_type_2_str(parent),
- alloc_cnt[parent], p_slices);
-#endif /* (TF_RM_DEBUG == 1) */
}
/* Search again through all the elements */
@@ -469,13 +413,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
dev->ops->tf_dev_get_resource_str(tfp,
cfg[child].hcapi_type,
&type_str);
-#if (TF_RM_DEBUG == 1)
- printf("%s:%s cnt(%d) slices(%d)\n",
- type_str,
- tf_tbl_type_2_str(child),
- alloc_cnt[child],
- c_slices);
-#endif /* (TF_RM_DEBUG == 1) */
+
/* Increment the parents combined count
* with each child's count adjusted for
* number of slices per RM alloc item.
@@ -492,10 +430,6 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
/* Save the parent count to be requested */
req_cnt[parent] = combined_cnt;
-#if (TF_RM_DEBUG == 1)
- printf("%s calculated total:%d\n\n",
- type_str, req_cnt[parent]);
-#endif /* (TF_RM_DEBUG == 1) */
}
}
return 0;
@@ -595,12 +529,6 @@ tf_rm_create_db(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
-#if (TF_RM_DEBUG == 1)
- TFP_DRV_LOG(INFO,
- "%s: module: %s Empty RM DB create request\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -746,7 +674,7 @@ tf_rm_create_db(struct tf *tfp,
rc = ba_init(db[i].pool,
resv[j].stride,
- !tf_session_is_shared_session(tfs));
+ true);
if (rc) {
TFP_DRV_LOG(ERR,
"%s: Pool init failed, type:%d:%s\n",
@@ -773,13 +701,6 @@ tf_rm_create_db(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
-#if (TF_RM_DEBUG == 1)
-
- printf("%s: module:%s\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif /* (TF_RM_DEBUG == 1) */
-
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -812,6 +733,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
+ bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -841,6 +763,16 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
+ shared_session = tf_session_is_shared_session(tfs);
+
+ /* Update the req_cnt based upon the element configuration
+ */
+ tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
+ parms->alloc_cnt,
+ parms->num_elements,
+ req_cnt,
+ shared_session);
+
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
* req msg content by removing those out of the request yet
@@ -855,11 +787,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
&hcapi_items);
if (hcapi_items == 0) {
- TFP_DRV_LOG(ERR,
- "%s: module:%s Empty RM DB create request\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-
parms->rm_db = NULL;
return -ENOMEM;
}
@@ -938,6 +865,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
db[i].cfg_type = cfg->cfg_type;
db[i].hcapi_type = cfg->hcapi_type;
+ db[i].slices = cfg->slices;
/* Save the parent subtype for later use to find the pool
*/
@@ -986,7 +914,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rc = ba_init(db[i].pool,
resv[j].stride,
- !tf_session_is_shared_session(tfs));
+ true);
if (rc) {
TFP_DRV_LOG(ERR,
"%s: Pool init failed, type:%d:%s\n",
@@ -1013,13 +941,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
rm_db->module = parms->module;
*parms->rm_db = (void *)rm_db;
-#if (TF_RM_DEBUG == 1)
-
- printf("%s: module:%s\n",
- tf_dir_2_str(parms->dir),
- tf_module_2_str(parms->module));
-#endif /* (TF_RM_DEBUG == 1) */
-
tfp_free((void *)req);
tfp_free((void *)resv);
tfp_free((void *)req_cnt);
@@ -1036,6 +957,7 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
return -EINVAL;
}
+
int
tf_rm_free_db(struct tf *tfp,
struct tf_rm_free_db_parms *parms)
@@ -1110,6 +1032,7 @@ tf_rm_free_db(struct tf *tfp,
return rc;
}
+
/**
* Get the bit allocator pool associated with the subtype and the db
*
@@ -1388,6 +1311,7 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms)
return 0;
}
+
int
tf_rm_get_slices(struct tf_rm_get_slices_parms *parms)
{
@@ -1440,6 +1364,7 @@ tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms)
return rc;
}
+
/* Only used for table bulk get at this time
*/
int
diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c
index d0a0916c6a..253d716572 100644
--- a/drivers/net/bnxt/tf_core/tf_session.c
+++ b/drivers/net/bnxt/tf_core/tf_session.c
@@ -1,12 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
-
#include <rte_common.h>
-
#include "tf_session.h"
#include "tf_common.h"
#include "tf_msg.h"
@@ -59,8 +57,9 @@ tf_session_create(struct tf *tfp,
union tf_session_id *session_id;
struct tf_dev_info dev;
bool shared_session_creator;
- int name_len;
- char *name;
+ char *shared_name;
+ char *tcam_session_name;
+ char *pool_session_name;
TF_CHECK_PARMS2(tfp, parms);
@@ -180,16 +179,18 @@ tf_session_create(struct tf *tfp,
session->em_ext_db_handle = NULL;
/* Populate the request */
- name_len = strnlen(parms->open_cfg->ctrl_chan_name,
- TF_SESSION_NAME_MAX);
- name = &parms->open_cfg->ctrl_chan_name[name_len - strlen("tf_shared")];
- if (!strncmp(name, "tf_shared", strlen("tf_shared")))
- session->shared_session = true;
-
- name = &parms->open_cfg->ctrl_chan_name[name_len -
- strlen("tf_shared-wc_tcam")];
- if (!strncmp(name, "tf_shared-wc_tcam", strlen("tf_shared-wc_tcam")))
+ shared_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared");
+ if (shared_name) {
session->shared_session = true;
+ /*
+ * "tf_shared-wc_tcam" is defined for tf_fw version 1.0.0.
+ * "tf_shared-pool" is defined for version 1.0.1.
+ */
+ tcam_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-wc_tcam");
+ pool_session_name = strstr(parms->open_cfg->ctrl_chan_name, "tf_shared-pool");
+ if (tcam_session_name || pool_session_name)
+ session->shared_session_hotup = true;
+ }
if (session->shared_session && shared_session_creator) {
session->shared_session_creator = true;
@@ -342,7 +343,6 @@ tf_session_client_create(struct tf *tfp,
return rc;
}
-
/**
* Destroys a Session Client on an existing Session.
*
@@ -441,7 +441,7 @@ tf_session_open_session(struct tf *tfp,
TFP_DRV_LOG(INFO,
"Session created, session_client_id:%d,"
- "session_id:0x%08x, fw_session_id:%d\n",
+ " session_id:0x%08x, fw_session_id:%d\n",
parms->open_cfg->session_client_id.id,
parms->open_cfg->session_id.id,
parms->open_cfg->session_id.internal.fw_session_id);
@@ -462,7 +462,7 @@ tf_session_open_session(struct tf *tfp,
}
TFP_DRV_LOG(INFO,
- "Session Client:%d registered on session:0x%8x\n",
+ "Session Client:%d registered on session:0x%08x\n",
scparms.session_client_id->internal.fw_session_client_id,
tfp->session->session_id.id);
}
@@ -535,6 +535,11 @@ tf_session_close_session(struct tf *tfp,
return rc;
}
+ /* Record the session we're closing so the caller knows the
+ * details.
+ */
+ *parms->session_id = tfs->session_id;
+
/* In case multiple clients we chose to close those first */
if (tfs->ref_count > 1) {
/* Linaro gcc can't static init this structure */
@@ -567,11 +572,6 @@ tf_session_close_session(struct tf *tfp,
return 0;
}
- /* Record the session we're closing so the caller knows the
- * details.
- */
- *parms->session_id = tfs->session_id;
-
rc = tf_session_get_device(tfs, &tfd);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -1140,3 +1140,71 @@ tf_session_set_if_tbl_db(struct tf *tfp,
tfs->if_tbl_db_handle = if_tbl_handle;
return rc;
}
+
+int
+tf_session_set_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+ struct tf_session *tfs = NULL;
+
+ rc = tf_session_get_session(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Session lookup failed, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ if (!tf_session_is_shared_session(tfs)) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR,
+ "Only shared session able to set state, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_session_set_hotup_state(tfp, parms->state);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Set session hot upgrade state failed, rc:%s\n",
+ strerror(-rc));
+ }
+
+ return rc;
+}
+
+int
+tf_session_get_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms)
+{
+ int rc = 0;
+ struct tf_session *tfs = NULL;
+
+ rc = tf_session_get_session(tfp, &tfs);
+ if (rc) {
+ TFP_DRV_LOG(ERR,
+ "Session lookup failed, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ if (!tf_session_is_shared_session(tfs)) {
+ rc = -EINVAL;
+ TFP_DRV_LOG(ERR,
+ "Only shared session able to get state, rc:%s\n",
+ strerror(-rc));
+ return rc;
+ }
+
+ rc = tf_msg_session_get_hotup_state(tfp, &parms->state, &parms->ref_cnt);
+ if (rc) {
+ /* Log error */
+ TFP_DRV_LOG(ERR,
+ "Get session hot upgrade state failed, rc:%s\n",
+ strerror(-rc));
+ }
+
+ return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index 5a94b941fa..9bbbccf125 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -8,7 +8,6 @@
#include <stdint.h>
#include <stdlib.h>
-
#include "bitalloc.h"
#include "tf_core.h"
#include "tf_device.h"
@@ -48,7 +47,7 @@
*
* Shared memory containing private TruFlow session information.
* Through this structure the session can keep track of resource
- * allocations. It also holds info about Session Clients.
+ * allocations. It also holds info about Session Clients.
*
* Memory is assigned to the Truflow instance by way of
* tf_open_session. Memory is allocated and owned by i.e. ULP.
@@ -78,6 +77,11 @@ struct tf_session {
*/
bool shared_session;
+ /**
+ * Boolean controlling the split of hardware resources for hotupgrade.
+ */
+ bool shared_session_hotup;
+
/**
* This flag indicates the shared session on firmware side is created
* by this session. Some privileges may be assigned to this session.
@@ -169,6 +173,12 @@ struct tf_session {
* Number of slices per row for WC TCAM
*/
uint16_t wc_num_slices_per_row;
+
+ /**
+ * Indicates if TCAM is controlled by TCAM Manager
+ */
+ int tcam_mgr_control[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX];
+
};
/**
@@ -276,11 +286,9 @@ struct tf_session_close_session_parms {
*
* @ref tf_session_is_shared_session
*
- * #define TF_SHARED
* @ref tf_session_get_tcam_shared_db
*
* @ref tf_session_set_tcam_shared_db
- * #endif
*
* @ref tf_session_get_sram_db
*
@@ -588,6 +596,21 @@ tf_session_is_shared_session(struct tf_session *tfs)
return tfs->shared_session;
}
+/**
+ * Check if the session is shared session for hot upgrade.
+ *
+ * [in] session, pointer to the session
+ *
+ * Returns:
+ * - true if it is shared session for hot upgrade
+ * - false if it is not shared session for hot upgrade
+ */
+static inline bool
+tf_session_is_shared_hotup_session(struct tf_session *tfs)
+{
+ return tfs->shared_session_hotup;
+}
+
/**
* Check if the session is the shared session creator
*
@@ -716,4 +739,36 @@ tf_session_set_if_tbl_db(struct tf *tfp,
int
tf_session_get_if_tbl_db(struct tf *tfp,
void **if_tbl_handle);
+
+/**
+ * Set hot upgrade session state.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [in] parms
+ * Hot upgrade session state parms
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_session_set_hotup_state(struct tf *tfp,
+ struct tf_set_session_hotup_state_parms *parms);
+
+/**
+ * Get hot upgrade session state.
+ *
+ * [in] tfp
+ * Pointer to session handle
+ *
+ * [out] parms
+ * Pointer to hot upgrade session state parms
+ *
+ * Returns:
+ * 0 on Success else internal Truflow error
+ */
+int
+tf_session_get_hotup_state(struct tf *tfp,
+ struct tf_get_session_hotup_state_parms *parms);
#endif /* _TF_SESSION_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
index acb3372486..87e8882fed 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.c
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <stdlib.h>
@@ -21,7 +21,7 @@
/**
* TF SRAM block info
*
- * Contains all the information about a particular 64B SRAM
+ * Contains all the information about a particular 128B SRAM
* block and the slices within it.
*/
struct tf_sram_block {
@@ -36,9 +36,9 @@ struct tf_sram_block {
* If a bit is set, it indicates the slice
* in the row is in use.
*/
- uint8_t in_use_mask;
+ uint16_t in_use_mask;
- /** Block id - this is a 64B offset
+ /** Block id - this is a 128B offset
*/
uint16_t block_id;
};
@@ -46,7 +46,7 @@ struct tf_sram_block {
/**
* TF SRAM block list
*
- * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B)
+ * List of 128B SRAM blocks used for fixed size slices (8, 16, 32, 64B, 128B)
*/
struct tf_sram_slice_list {
/** Pointer to head of linked list of blocks.
@@ -70,7 +70,6 @@ struct tf_sram_slice_list {
enum tf_sram_slice_size size;
};
-
/**
* TF SRAM bank info consists of lists of different slice sizes per bank
*/
@@ -111,6 +110,8 @@ const char
return "32B slice";
case TF_SRAM_SLICE_SIZE_64B:
return "64B slice";
+ case TF_SRAM_SLICE_SIZE_128B:
+ return "128B slice";
default:
return "Invalid slice size";
}
@@ -179,8 +180,8 @@ static void
tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset,
uint16_t *block_id, uint16_t *slice_offset)
{
- *slice_offset = offset & 0x7;
- *block_id = ((offset & ~0x7) >> 3) -
+ *slice_offset = offset & 0xf;
+ *block_id = ((offset & ~0xf) >> 3) -
tf_sram_bank_2_base_offset[bank_id];
}
@@ -232,31 +233,37 @@ tf_sram_free_slice(enum tf_sram_slice_size slice_size,
bool *block_is_empty)
{
int rc = 0;
- uint8_t shift;
- uint8_t slice_mask = 0;
+ uint16_t shift;
+ uint16_t slice_mask = 0;
TF_CHECK_PARMS2(block, block_is_empty);
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = slice_offset >> 0;
- assert(shift < 8);
+ assert(shift < 16);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = slice_offset >> 1;
- assert(shift < 4);
+ assert(shift < 8);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = slice_offset >> 2;
- assert(shift < 2);
+ assert(shift < 4);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ shift = slice_offset >> 3;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = slice_offset >> 0;
assert(shift < 1);
@@ -294,27 +301,32 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
bool *block_is_full)
{
int rc, free_id = -1;
- uint8_t shift, max_slices, mask, i, full_mask;
+ uint16_t shift, max_slices, mask, i, full_mask;
TF_CHECK_PARMS3(block, slice_offset, block_is_full);
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = 0;
- max_slices = 8;
- full_mask = 0xff;
+ max_slices = 16;
+ full_mask = 0xffff;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = 1;
- max_slices = 4;
- full_mask = 0xf;
+ max_slices = 8;
+ full_mask = 0xff;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = 2;
+ max_slices = 4;
+ full_mask = 0xf;
+ break;
+ case TF_SRAM_SLICE_SIZE_64B:
+ shift = 3;
max_slices = 2;
full_mask = 0x3;
break;
- case TF_SRAM_SLICE_SIZE_64B:
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = 0;
max_slices = 1;
@@ -338,7 +350,6 @@ tf_sram_get_next_slice_in_block(struct tf_sram_block *block,
else
*block_is_full = false;
-
if (free_id >= 0) {
*slice_offset = free_id << shift;
rc = 0;
@@ -362,8 +373,8 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
bool *is_allocated)
{
int rc = 0;
- uint8_t shift;
- uint8_t slice_mask = 0;
+ uint16_t shift;
+ uint16_t slice_mask = 0;
TF_CHECK_PARMS2(block, is_allocated);
@@ -372,23 +383,29 @@ tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block,
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
shift = slice_offset >> 0;
- assert(shift < 8);
+ assert(shift < 16);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_16B:
shift = slice_offset >> 1;
- assert(shift < 4);
+ assert(shift < 8);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_32B:
shift = slice_offset >> 2;
- assert(shift < 2);
+ assert(shift < 4);
slice_mask = 1 << shift;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ shift = slice_offset >> 3;
+ assert(shift < 2);
+ slice_mask = 1 << shift;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
shift = slice_offset >> 0;
assert(shift < 1);
@@ -416,7 +433,6 @@ tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list)
return slice_list->cnt;
}
-
/**
* Free a block data structure - does not free to the RM
*/
@@ -508,22 +524,26 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
struct tf_sram_block **first_not_full_block)
{
struct tf_sram_block *block = slice_list->head;
- uint8_t slice_mask, mask;
+ uint16_t slice_mask, mask;
switch (slice_size) {
case TF_SRAM_SLICE_SIZE_8B:
- slice_mask = 0xff;
+ slice_mask = 0xffff;
break;
case TF_SRAM_SLICE_SIZE_16B:
- slice_mask = 0xf;
+ slice_mask = 0xff;
break;
case TF_SRAM_SLICE_SIZE_32B:
- slice_mask = 0x3;
+ slice_mask = 0xf;
break;
case TF_SRAM_SLICE_SIZE_64B:
+ slice_mask = 0x3;
+ break;
+
+ case TF_SRAM_SLICE_SIZE_128B:
default:
slice_mask = 0x1;
break;
@@ -543,7 +563,7 @@ tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list,
static void
tf_sram_dump_block(struct tf_sram_block *block)
{
- TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n",
+ TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%04x)\n",
block->block_id,
block->in_use_mask);
}
@@ -631,9 +651,10 @@ int tf_sram_mgr_alloc(void *sram_handle,
struct tf_sram *sram;
struct tf_sram_slice_list *slice_list;
uint16_t block_id, slice_offset = 0;
- uint32_t index;
+ uint32_t index, next_index;
struct tf_sram_block *block;
struct tf_rm_allocate_parms aparms = { 0 };
+ struct tf_rm_free_parms fparms = { 0 };
bool block_is_full;
uint16_t block_offset;
@@ -662,11 +683,34 @@ int tf_sram_mgr_alloc(void *sram_handle,
aparms.subtype = parms->tbl_type;
aparms.rm_db = parms->rm_db;
rc = tf_rm_allocate(&aparms);
+ if (rc)
+ return rc;
+ /* to support 128B block rows, we are allocating
+ * 2 sequential 64B blocks from RM, if they are not next to
+ * each other we are going to have issues
+ */
+ aparms.index = &next_index;
+ rc = tf_rm_allocate(&aparms);
if (rc)
return rc;
+ /* make sure we do get the next 64B block, else free the
+ * allocated indexes and return error
+ */
+ if (unlikely(index + 1 != next_index)) {
+ fparms.index = index;
+ fparms.subtype = parms->tbl_type;
+ fparms.rm_db = parms->rm_db;
+ tf_rm_free(&fparms);
+ fparms.index = next_index;
+ tf_rm_free(&fparms);
+ TFP_DRV_LOG(ERR,
+ "Could not allocate two sequential 64B blocks\n");
+ return -ENOMEM;
+ }
block_id = index;
block = tf_sram_alloc_block(slice_list, block_id);
+
} else {
/* Block exists
*/
@@ -742,7 +786,7 @@ tf_sram_mgr_free(void *sram_handle,
}
#if (STATS_CLEAR_ON_READ_SUPPORT == 0)
/* If this is a counter, clear it. In the future we need to switch to
- * using the special access registers on Thor to automatically clear on
+ * using the special access registers on P5 to automatically clear on
* read.
*/
/* If this is counter table, clear the entry on free */
@@ -794,6 +838,13 @@ tf_sram_mgr_free(void *sram_handle,
TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n",
block_id, strerror(-rc));
}
+ fparms.index = block_id + 1;
+ rc = tf_rm_free(&fparms);
+
+ if (rc) {
+ TFP_DRV_LOG(ERR, "Free next block_id(%d) failed error(%s)\n",
+ block_id + 1, strerror(-rc));
+ }
/* Free local entry regardless */
tf_sram_free_block(slice_list, block);
diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
index fc78426130..878195c404 100644
--- a/drivers/net/bnxt/tf_core/tf_sram_mgr.h
+++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -26,28 +26,28 @@
*/
#define STATS_CLEAR_ON_READ_SUPPORT 0
-#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64
+#define TF_SRAM_MGR_BLOCK_SZ_BYTES 128
#define TF_SRAM_MGR_MIN_SLICE_BYTES 8
/**
* TF slice size.
*
- * A slice is part of a 64B row
+ * A slice is part of a 128B row
*
* Each slice is a multiple of 8B
*/
enum tf_sram_slice_size {
- TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
- TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
+ TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_128B, /**< 128 byte SRAM slice */
+ TF_SRAM_SLICE_SIZE_MAX /**< slice limit */
};
-
/** Initialize the SRAM slice manager
*
- * The SRAM slice manager manages slices within 64B rows. Slices are of size
+ * The SRAM slice manager manages slices within 128B rows. Slices are of size
* tf_sram_slice_size. This function provides a handle to the SRAM manager
* data.
*
@@ -181,7 +181,7 @@ struct tf_sram_mgr_free_parms {
/**
* Free an SRAM Slice
*
- * Free an SRAM slice to the indicated bank. This may result in a 64B row
+ * Free an SRAM slice to the indicated bank. This may result in a 128B row
* being returned to the RM SRAM bank pool.
*
* [in] sram_handle
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c
index f18e4ba346..f5f3889934 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl.c
@@ -1,12 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
/* Truflow Table APIs and supporting code */
#include <rte_common.h>
-
#include "tf_tbl.h"
#include "tf_common.h"
#include "tf_rm.h"
@@ -18,8 +17,8 @@
struct tf;
-#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
- *(new_idx) = (((idx) + (base)) << (shift)); \
+#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \
+ *(new_idx) = (((idx) + (base)) << (shift)); \
}
int
@@ -98,6 +97,7 @@ tf_tbl_unbind(struct tf *tfp)
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr);
if (rc)
return 0;
+
tbl_db = (struct tbl_rm_db *)tbl_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
index 567f912dfa..3a6f1c68c7 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl_sram.c
+++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -73,11 +73,12 @@ const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = {
* Translate HCAPI type to SRAM Manager bank
*/
const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = {
- [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */
- [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */
- [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */
- [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */
- [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */
+ [0] = TF_SRAM_SLICE_SIZE_128B, /* if 0 slices assume 1 128B block */
+ [1] = TF_SRAM_SLICE_SIZE_128B, /* 1 slice per 128B block */
+ [2] = TF_SRAM_SLICE_SIZE_64B, /* 2 slice per 128B block */
+ [4] = TF_SRAM_SLICE_SIZE_32B, /* 4 slices per 128B block */
+ [8] = TF_SRAM_SLICE_SIZE_16B, /* 8 slices per 128B block */
+ [16] = TF_SRAM_SLICE_SIZE_8B /* 16 slices per 128B block */
};
/**
@@ -340,7 +341,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Free of invalid entry:%s idx(%d):(%s)\n",
+ "%s: Free of invalid entry:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -361,7 +362,7 @@ tf_tbl_sram_free(struct tf *tfp __rte_unused,
rc = tf_sram_mgr_free(sram_handle, &fparms);
if (rc) {
TFP_DRV_LOG(ERR,
- "%s: Failed to free entry:%s idx(%d)\n",
+ "%s: Failed to free entry:%s idx(0x%x)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx);
@@ -469,7 +470,7 @@ tf_tbl_sram_set(struct tf *tfp,
if (rallocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
TFP_DRV_LOG(ERR,
- "%s, Invalid or not allocated index, type:%s, idx:%d\n",
+ "%s, Invalid or not allocated index, type:%s, idx:0x%x\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx);
@@ -484,7 +485,7 @@ tf_tbl_sram_set(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -587,7 +588,7 @@ tf_tbl_sram_get(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
parms->idx,
@@ -711,7 +712,7 @@ tf_tbl_sram_bulk_get(struct tf *tfp,
rc = tf_sram_mgr_is_allocated(sram_handle, &aparms);
if (rc || !allocated) {
TFP_DRV_LOG(ERR,
- "%s: Entry not allocated:%s last_idx(%d):(%s)\n",
+ "%s: Entry not allocated:%s last_idx(0x%x):(%s)\n",
tf_dir_2_str(parms->dir),
tf_tbl_type_2_str(parms->type),
idx,
diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c
index 1c42a6adc7..9e0671d47b 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -14,6 +14,7 @@
#include "tfp.h"
#include "tf_session.h"
#include "tf_msg.h"
+#include "tf_tcam_mgr_msg.h"
struct tf;
@@ -23,17 +24,22 @@ tf_tcam_bind(struct tf *tfp,
{
int rc;
int db_rc[TF_DIR_MAX] = { 0 };
- int i, d;
+ int d, t;
struct tf_rm_alloc_info info;
struct tf_rm_free_db_parms fparms;
struct tf_rm_create_db_parms db_cfg;
+ struct tf_tcam_resources local_tcam_cnt[TF_DIR_MAX];
struct tf_tcam_resources *tcam_cnt;
struct tf_rm_get_alloc_info_parms ainfo;
- uint16_t num_slices = parms->wc_num_slices;
+ uint16_t num_slices = 1;
struct tf_session *tfs;
struct tf_dev_info *dev;
struct tcam_rm_db *tcam_db;
struct tfp_calloc_parms cparms;
+ struct tf_resource_info resv_res[TF_DIR_MAX][TF_TCAM_TBL_TYPE_MAX];
+ uint32_t rx_supported;
+ uint32_t tx_supported;
+ bool no_req = true;
TF_CHECK_PARMS2(tfp, parms);
@@ -47,7 +53,7 @@ tf_tcam_bind(struct tf *tfp,
if (rc)
return rc;
- if (dev->ops->tf_dev_set_tcam_slice_info == NULL) {
+ if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
rc = -EOPNOTSUPP;
TFP_DRV_LOG(ERR,
"Operation not supported, rc:%s\n",
@@ -55,18 +61,28 @@ tf_tcam_bind(struct tf *tfp,
return rc;
}
- rc = dev->ops->tf_dev_set_tcam_slice_info(tfp,
- num_slices);
+ tcam_cnt = parms->resources->tcam_cnt;
+
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0,
+ &num_slices);
if (rc)
return rc;
- tcam_cnt = parms->resources->tcam_cnt;
- if ((tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices) ||
- (tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] % num_slices)) {
- TFP_DRV_LOG(ERR,
- "Requested num of WC TCAM entries has to be multiple %d\n",
- num_slices);
- return -EINVAL;
+ if (num_slices == 1)
+ continue;
+
+ if (tcam_cnt[d].cnt[t] % num_slices) {
+ TFP_DRV_LOG(ERR,
+ "%s: Requested num of %s entries "
+ "has to be multiple of %d\n",
+ tf_dir_2_str(d),
+ tf_tcam_tbl_2_str(t),
+ num_slices);
+ return -EINVAL;
+ }
+ }
}
memset(&db_cfg, 0, sizeof(db_cfg));
@@ -80,8 +96,8 @@ tf_tcam_bind(struct tf *tfp,
}
tcam_db = cparms.mem_va;
- for (i = 0; i < TF_DIR_MAX; i++)
- tcam_db->tcam_db[i] = NULL;
+ for (d = 0; d < TF_DIR_MAX; d++)
+ tcam_db->tcam_db[d] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, tcam_db);
db_cfg.module = TF_MODULE_TYPE_TCAM;
@@ -90,7 +106,7 @@ tf_tcam_bind(struct tf *tfp,
for (d = 0; d < TF_DIR_MAX; d++) {
db_cfg.dir = d;
- db_cfg.alloc_cnt = parms->resources->tcam_cnt[d].cnt;
+ db_cfg.alloc_cnt = tcam_cnt[d].cnt;
db_cfg.rm_db = (void *)&tcam_db->tcam_db[d];
if (tf_session_is_shared_session(tfs) &&
(!tf_session_is_shared_session_creator(tfs)))
@@ -98,53 +114,112 @@ tf_tcam_bind(struct tf *tfp,
else
db_rc[d] = tf_rm_create_db(tfp, &db_cfg);
}
-
/* No db created */
if (db_rc[TF_DIR_RX] && db_rc[TF_DIR_TX]) {
TFP_DRV_LOG(ERR, "No TCAM DB created\n");
return db_rc[TF_DIR_RX];
}
- /* check if reserved resource for WC is multiple of num_slices */
+ /* Collect info on which entries were reserved. */
for (d = 0; d < TF_DIR_MAX; d++) {
- if (!tcam_db->tcam_db[d])
- continue;
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ memset(&info, 0, sizeof(info));
+ if (tcam_cnt[d].cnt[t] == 0) {
+ resv_res[d][t].start = 0;
+ resv_res[d][t].stride = 0;
+ continue;
+ }
+ ainfo.rm_db = tcam_db->tcam_db[d];
+ ainfo.subtype = t;
+ ainfo.info = &info;
+ rc = tf_rm_get_info(&ainfo);
+ if (rc)
+ goto error;
+
+ rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, t, 0,
+ &num_slices);
+ if (rc)
+ return rc;
+
+ if (num_slices > 1) {
+ /* check if reserved resource for is multiple of
+ * num_slices
+ */
+ if (info.entry.start % num_slices != 0 ||
+ info.entry.stride % num_slices != 0) {
+ TFP_DRV_LOG(ERR,
+ "%s: %s reserved resource"
+ " is not multiple of %d\n",
+ tf_dir_2_str(d),
+ tf_tcam_tbl_2_str(t),
+ num_slices);
+ rc = -EINVAL;
+ goto error;
+ }
+ }
+
+ resv_res[d][t].start = info.entry.start;
+ resv_res[d][t].stride = info.entry.stride;
+ }
+ }
- memset(&info, 0, sizeof(info));
- ainfo.rm_db = tcam_db->tcam_db[d];
- ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- ainfo.info = &info;
- rc = tf_rm_get_info(&ainfo);
- if (rc)
- goto error;
-
- if (info.entry.start % num_slices != 0 ||
- info.entry.stride % num_slices != 0) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM reserved resource is not multiple of %d\n",
- tf_dir_2_str(d),
- num_slices);
- rc = -EINVAL;
- goto error;
+ rc = tf_tcam_mgr_bind_msg(tfp, dev, parms, resv_res);
+ if (rc)
+ return rc;
+
+ rc = tf_tcam_mgr_qcaps_msg(tfp, dev,
+ &rx_supported, &tx_supported);
+ if (rc)
+ return rc;
+
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ if (rx_supported & 1 << t)
+ tfs->tcam_mgr_control[TF_DIR_RX][t] = 1;
+ if (tx_supported & 1 << t)
+ tfs->tcam_mgr_control[TF_DIR_TX][t] = 1;
+ }
+
+ /*
+ * Make a local copy of tcam_cnt with only resources not managed by TCAM
+ * Manager requested.
+ */
+ memcpy(&local_tcam_cnt, tcam_cnt, sizeof(local_tcam_cnt));
+ tcam_cnt = local_tcam_cnt;
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ for (t = 0; t < TF_TCAM_TBL_TYPE_MAX; t++) {
+ /* If controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[d][t])
+ tcam_cnt[d].cnt[t] = 0;
+ else if (tcam_cnt[d].cnt[t] > 0)
+ no_req = false;
}
}
- /* Initialize the TCAM manager. */
+ /* If no resources left to request */
+ if (no_req)
+ goto finished;
+
+finished:
TFP_DRV_LOG(INFO,
"TCAM - initialized\n");
return 0;
error:
- for (i = 0; i < TF_DIR_MAX; i++) {
- memset(&fparms, 0, sizeof(fparms));
- fparms.dir = i;
- fparms.rm_db = tcam_db->tcam_db[i];
- /* Ignoring return here since we are in the error case */
- (void)tf_rm_free_db(tfp, &fparms);
- tcam_db->tcam_db[i] = NULL;
+ for (d = 0; d < TF_DIR_MAX; d++) {
+ if (tcam_db->tcam_db[d] != NULL) {
+ memset(&fparms, 0, sizeof(fparms));
+ fparms.dir = d;
+ fparms.rm_db = tcam_db->tcam_db[d];
+ /*
+ * Ignoring return here since we are in the error case
+ */
+ (void)tf_rm_free_db(tfp, &fparms);
+
+ tcam_db->tcam_db[d] = NULL;
+ }
+ tcam_db->tcam_db[d] = NULL;
tf_session_set_db(tfp, TF_MODULE_TYPE_TCAM, NULL);
}
-
return rc;
}
@@ -156,27 +231,43 @@ tf_tcam_unbind(struct tf *tfp)
struct tf_rm_free_db_parms fparms;
struct tcam_rm_db *tcam_db;
void *tcam_db_ptr = NULL;
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
TF_CHECK_PARMS1(tfp);
+ /* Retrieve the session information */
+ rc = tf_session_get_session_internal(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc) {
+ if (rc)
return 0;
- }
+
tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
for (i = 0; i < TF_DIR_MAX; i++) {
- if (tcam_db->tcam_db[i] == NULL)
- continue;
- memset(&fparms, 0, sizeof(fparms));
- fparms.dir = i;
- fparms.rm_db = tcam_db->tcam_db[i];
- rc = tf_rm_free_db(tfp, &fparms);
- if (rc)
- return rc;
+ if (tcam_db->tcam_db[i] != NULL) {
+ memset(&fparms, 0, sizeof(fparms));
+ fparms.dir = i;
+ fparms.rm_db = tcam_db->tcam_db[i];
+ rc = tf_rm_free_db(tfp, &fparms);
+ if (rc)
+ return rc;
+
+ tcam_db->tcam_db[i] = NULL;
+ }
- tcam_db->tcam_db[i] = NULL;
}
+ rc = tf_tcam_mgr_unbind_msg(tfp, dev);
+ if (rc)
+ return rc;
+
return 0;
}
@@ -222,6 +313,9 @@ tf_tcam_alloc(struct tf *tfp,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_alloc_msg(tfp, dev, parms);
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -251,12 +345,8 @@ tf_tcam_alloc(struct tf *tfp,
}
/* return the start index of each row */
- if (parms->priority == 0) {
if (i == 0)
parms->idx = index;
- } else {
- parms->idx = index;
- }
}
return 0;
@@ -307,6 +397,14 @@ tf_tcam_free(struct tf *tfp,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ /*
+ * If a session can have multiple references to an entry, check
+ * the reference count here before actually freeing the entry.
+ */
+ return tf_tcam_mgr_free_msg(tfp, dev, parms);
+
if (parms->idx % num_slices) {
TFP_DRV_LOG(ERR,
"%s: TCAM reserved resource is not multiple of %d\n",
@@ -429,6 +527,10 @@ tf_tcam_set(struct tf *tfp __rte_unused,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_set_msg(tfp, dev, parms);
+
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
@@ -508,6 +610,10 @@ tf_tcam_get(struct tf *tfp __rte_unused,
if (rc)
return rc;
+ /* If TCAM controlled by TCAM Manager */
+ if (tfs->tcam_mgr_control[parms->dir][parms->type])
+ return tf_tcam_mgr_get_msg(tfp, dev, parms);
+
rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
if (rc) {
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
new file mode 100644
index 0000000000..c535f4f4f6
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.c
@@ -0,0 +1,286 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <errno.h>
+
+#include "tfp.h"
+#include "tf_tcam.h"
+#include "cfa_tcam_mgr.h"
+#include "tf_tcam_mgr_msg.h"
+
+/*
+ * Table to convert TCAM type to logical TCAM type for applications.
+ * Index is tf_tcam_tbl_type.
+ */
+static enum cfa_tcam_mgr_tbl_type tcam_types[TF_TCAM_TBL_TYPE_MAX] = {
+ [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_HIGH_APPS,
+ [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
+ CFA_TCAM_MGR_TBL_TYPE_L2_CTXT_TCAM_LOW_APPS,
+ [TF_TCAM_TBL_TYPE_PROF_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_PROF_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_SP_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_SP_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_CT_RULE_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_CT_RULE_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_VEB_TCAM] =
+ CFA_TCAM_MGR_TBL_TYPE_VEB_TCAM_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM_HIGH] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_HIGH_APPS,
+ [TF_TCAM_TBL_TYPE_WC_TCAM_LOW] =
+ CFA_TCAM_MGR_TBL_TYPE_WC_TCAM_LOW_APPS,
+};
+
+static uint16_t hcapi_type[TF_TCAM_TBL_TYPE_MAX];
+
+/*
+ * This is the glue between the core tf_tcam and the TCAM manager. It is
+ * intended to abstract out the location of the TCAM manager so that the core
+ * code will be the same if the TCAM manager is in the core or in firmware.
+ *
+ * If the TCAM manager is in the core, then this file will just translate to
+ * TCAM manager APIs. If TCAM manager is in firmware, then this file will cause
+ * messages to be sent (except for bind and unbind).
+ */
+
+int
+tf_tcam_mgr_qcaps_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ uint32_t *rx_tcam_supported,
+ uint32_t *tx_tcam_supported)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_qcaps_parms mgr_parms;
+ int rc;
+
+ context.tfp = tfp;
+ memset(&mgr_parms, 0, sizeof(mgr_parms));
+ rc = cfa_tcam_mgr_qcaps(&context, &mgr_parms);
+ if (rc >= 0) {
+ *rx_tcam_supported = mgr_parms.rx_tcam_supported;
+ *tx_tcam_supported = mgr_parms.tx_tcam_supported;
+ }
+ return rc;
+}
+
+int
+tf_tcam_mgr_bind_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_cfg_parms *parms,
+ struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX]
+ __rte_unused
+ )
+{
+ /* Common Code */
+ int type;
+
+ if (parms->num_elements != TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "Invalid number of elements in bind request.\n");
+ TFP_DRV_LOG(ERR,
+ "Expected %d, received %d.\n",
+ TF_TCAM_TBL_TYPE_MAX,
+ parms->num_elements);
+ return -EINVAL;
+ }
+
+ for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++)
+ hcapi_type[type] = parms->cfg[type].hcapi_type;
+
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_cfg_parms mgr_parms;
+ struct tf_rm_resc_entry
+ mgr_resv_res[TF_DIR_MAX][CFA_TCAM_MGR_TBL_TYPE_MAX];
+ int dir, rc;
+
+ context.tfp = tfp;
+
+ memset(&mgr_parms, 0, sizeof(mgr_parms));
+
+ mgr_parms.num_elements = CFA_TCAM_MGR_TBL_TYPE_MAX;
+
+ /* Convert the data to logical tables */
+ for (dir = 0; dir < TF_DIR_MAX; dir++) {
+ for (type = 0; type < TF_TCAM_TBL_TYPE_MAX; type++) {
+ mgr_parms.tcam_cnt[dir][tcam_types[type]] =
+ parms->resources->tcam_cnt[dir].cnt[type];
+ mgr_resv_res[dir][tcam_types[type]].start =
+ resv_res[dir][type].start;
+ mgr_resv_res[dir][tcam_types[type]].stride =
+ resv_res[dir][type].stride;
+ }
+ }
+ mgr_parms.resv_res = mgr_resv_res;
+
+ rc = cfa_tcam_mgr_bind(&context, &mgr_parms);
+
+ return rc;
+}
+
+int
+tf_tcam_mgr_unbind_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused)
+{
+ struct cfa_tcam_mgr_context context;
+
+ context.tfp = tfp;
+
+ return cfa_tcam_mgr_unbind(&context);
+}
+
+int
+tf_tcam_mgr_alloc_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_alloc_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_alloc_parms mgr_parms;
+ int rc;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.key_size = parms->key_size;
+ if (parms->priority > TF_TCAM_PRIORITY_MAX)
+ mgr_parms.priority = 0;
+ else
+ mgr_parms.priority = TF_TCAM_PRIORITY_MAX - parms->priority - 1;
+
+ rc = cfa_tcam_mgr_alloc(&context, &mgr_parms);
+ if (rc)
+ return rc;
+
+ parms->idx = mgr_parms.id;
+ return 0;
+}
+
+int
+tf_tcam_mgr_free_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_free_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_free_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+
+ return cfa_tcam_mgr_free(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_set_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_set_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_set_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+ mgr_parms.key = parms->key;
+ mgr_parms.mask = parms->mask;
+ mgr_parms.key_size = parms->key_size;
+ mgr_parms.result = parms->result;
+ mgr_parms.result_size = parms->result_size;
+
+ return cfa_tcam_mgr_set(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_get_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ struct tf_tcam_get_parms *parms)
+{
+ int rc;
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_get_parms mgr_parms;
+
+ if (parms->type >= TF_TCAM_TBL_TYPE_MAX) {
+ TFP_DRV_LOG(ERR,
+ "No such TCAM table %d.\n",
+ parms->type);
+ return -EINVAL;
+ }
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->type];
+ mgr_parms.hcapi_type = hcapi_type[parms->type];
+ mgr_parms.id = parms->idx;
+ mgr_parms.key = parms->key;
+ mgr_parms.mask = parms->mask;
+ mgr_parms.key_size = parms->key_size;
+ mgr_parms.result = parms->result;
+ mgr_parms.result_size = parms->result_size;
+
+ rc = cfa_tcam_mgr_get(&context, &mgr_parms);
+ if (rc)
+ return rc;
+
+ parms->key_size = mgr_parms.key_size;
+ parms->result_size = mgr_parms.result_size;
+
+ return rc;
+}
+
+int
+tf_tcam_mgr_shared_clear_msg(struct tf *tfp,
+ struct tf_clear_tcam_shared_entries_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_shared_clear_parms mgr_parms;
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->tcam_tbl_type];
+
+ return cfa_tcam_mgr_shared_clear(&context, &mgr_parms);
+}
+
+int
+tf_tcam_mgr_shared_move_msg(struct tf *tfp,
+ struct tf_move_tcam_shared_entries_parms *parms)
+{
+ struct cfa_tcam_mgr_context context;
+ struct cfa_tcam_mgr_shared_move_parms mgr_parms;
+
+ context.tfp = tfp;
+ mgr_parms.dir = parms->dir;
+ mgr_parms.type = tcam_types[parms->tcam_tbl_type];
+
+ return cfa_tcam_mgr_shared_move(&context, &mgr_parms);
+}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
new file mode 100644
index 0000000000..8a8d136f5e
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_tcam_mgr_msg.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021-2023 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_TCAM_MGR_MSG_H_
+#define _TF_TCAM_MGR_MSG_H_
+
+#include "tf_tcam.h"
+#include "tf_rm.h"
+
+int
+tf_tcam_mgr_qcaps_msg(struct tf *tfp,
+ struct tf_dev_info *dev __rte_unused,
+ uint32_t *rx_tcam_supported,
+ uint32_t *tx_tcam_supported);
+
+int
+tf_tcam_mgr_bind_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_cfg_parms *parms,
+ struct tf_resource_info resv_res[][TF_TCAM_TBL_TYPE_MAX]);
+int
+tf_tcam_mgr_unbind_msg(struct tf *tfp,
+ struct tf_dev_info *dev);
+int
+tf_tcam_mgr_alloc_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_alloc_parms *parms);
+int
+tf_tcam_mgr_free_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_free_parms *parms);
+int
+tf_tcam_mgr_set_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_set_parms *parms);
+int
+tf_tcam_mgr_get_msg(struct tf *tfp,
+ struct tf_dev_info *dev,
+ struct tf_tcam_get_parms *parms);
+int
+tf_tcam_mgr_shared_clear_msg(struct tf *tfp,
+ struct tf_clear_tcam_shared_entries_parms *parms);
+
+int
+tf_tcam_mgr_shared_move_msg(struct tf *tfp,
+ struct tf_move_tcam_shared_entries_parms *parms);
+#endif /* _TF_TCAM_MGR_MSG_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
index c120c6f577..e853f616f9 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c
@@ -1,11 +1,13 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
#include <string.h>
#include <rte_common.h>
+#include "tf_core.h"
+
#include "tf_tcam_shared.h"
#include "tf_tcam.h"
#include "tf_common.h"
@@ -16,229 +18,8 @@
#include "tf_session.h"
#include "tf_msg.h"
#include "bitalloc.h"
-#include "tf_core.h"
-
-/** Shared WC TCAM pool identifiers
- */
-enum tf_tcam_shared_wc_pool_id {
- TF_TCAM_SHARED_WC_POOL_HI = 0,
- TF_TCAM_SHARED_WC_POOL_LO = 1,
- TF_TCAM_SHARED_WC_POOL_MAX = 2
-};
-
-/** Get string representation of a WC TCAM shared pool id
- */
-static const char *
-tf_pool_2_str(enum tf_tcam_shared_wc_pool_id id)
-{
- switch (id) {
- case TF_TCAM_SHARED_WC_POOL_HI:
- return "TCAM_SHARED_WC_POOL_HI";
- case TF_TCAM_SHARED_WC_POOL_LO:
- return "TCAM_SHARED_WC_POOL_LO";
- default:
- return "Invalid TCAM_SHARED_WC_POOL";
- }
-}
-
-/** The WC TCAM shared pool datastructure
- */
-struct tf_tcam_shared_wc_pool {
- /** Start and stride data */
- struct tf_resource_info info;
- /** bitalloc pool */
- struct bitalloc *pool;
-};
-
-struct tf_tcam_shared_wc_pools {
- struct tf_tcam_shared_wc_pool db[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX];
-};
-
-/** The WC TCAM shared pool declarations
- */
-/* struct tf_tcam_shared_wc_pool tcam_shared_wc[TF_DIR_MAX][TF_TCAM_SHARED_WC_POOL_MAX]; */
-
-static int
-tf_tcam_shared_create_db(struct tf_tcam_shared_wc_pools **db)
-{
- struct tfp_calloc_parms cparms;
- int rc = 0;
-
- cparms.nitems = 1;
- cparms.alignment = 0;
- cparms.size = sizeof(struct tf_tcam_shared_wc_pools);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "TCAM shared db allocation failed (%s)\n",
- strerror(-rc));
- return rc;
- }
- *db = cparms.mem_va;
-
- return rc;
-}
-
-/** Create a WC TCAM shared pool
- */
-static int
-tf_tcam_shared_create_wc_pool(int dir,
- enum tf_tcam_shared_wc_pool_id id,
- int start,
- int stride,
- struct tf_tcam_shared_wc_pools *tcam_shared_wc)
-{
- int rc = 0;
- bool free = true;
- struct tfp_calloc_parms cparms;
- uint32_t pool_size;
-
- /* Create pool */
- pool_size = (BITALLOC_SIZEOF(stride) / sizeof(struct bitalloc));
- cparms.nitems = pool_size;
- cparms.alignment = 0;
- cparms.size = sizeof(struct bitalloc);
- rc = tfp_calloc(&cparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: pool memory alloc failed %s:%s\n",
- tf_dir_2_str(dir), tf_pool_2_str(id),
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc->db[dir][id].pool = (struct bitalloc *)cparms.mem_va;
-
- rc = ba_init(tcam_shared_wc->db[dir][id].pool,
- stride,
- free);
-
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: pool bitalloc failed %s\n",
- tf_dir_2_str(dir), tf_pool_2_str(id));
- return rc;
- }
-
- tcam_shared_wc->db[dir][id].info.start = start;
- tcam_shared_wc->db[dir][id].info.stride = stride;
-
- return rc;
-}
-/** Free a WC TCAM shared pool
- */
-static int
-tf_tcam_shared_free_wc_pool(int dir,
- enum tf_tcam_shared_wc_pool_id id,
- struct tf_tcam_shared_wc_pools *tcam_shared_wc)
-{
- int rc = 0;
- TF_CHECK_PARMS1(tcam_shared_wc);
-
- tcam_shared_wc->db[dir][id].info.start = 0;
- tcam_shared_wc->db[dir][id].info.stride = 0;
-
- if (tcam_shared_wc->db[dir][id].pool)
- tfp_free((void *)tcam_shared_wc->db[dir][id].pool);
- return rc;
-}
-
-/** Get the number of WC TCAM slices allocated during 1 allocation/free
- */
-static int
-tf_tcam_shared_get_slices(struct tf *tfp,
- struct tf_dev_info *dev,
- uint16_t *num_slices)
-{
- int rc;
-
- if (dev->ops->tf_dev_get_tcam_slice_info == NULL) {
- rc = -EOPNOTSUPP;
- TFP_DRV_LOG(ERR,
- "Operation not supported, rc:%s\n", strerror(-rc));
- return rc;
- }
- rc = dev->ops->tf_dev_get_tcam_slice_info(tfp,
- TF_TCAM_TBL_TYPE_WC_TCAM,
- 0,
- num_slices);
- return rc;
-}
-
-static bool
-tf_tcam_db_valid(struct tf *tfp,
- enum tf_dir dir)
-{
- struct tcam_rm_db *tcam_db;
- void *tcam_db_ptr = NULL;
- int rc;
-
- TF_CHECK_PARMS1(tfp);
-
- rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc)
- return false;
-
- tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
-
- if (tcam_db->tcam_db[dir])
- return true;
-
- return false;
-}
-
-static int
-tf_tcam_shared_get_rm_info(struct tf *tfp,
- enum tf_dir dir,
- uint16_t *hcapi_type,
- struct tf_rm_alloc_info *info)
-{
- int rc;
- struct tcam_rm_db *tcam_db;
- void *tcam_db_ptr = NULL;
- struct tf_rm_get_alloc_info_parms ainfo;
- struct tf_rm_get_hcapi_parms hparms;
-
- TF_CHECK_PARMS3(tfp, hcapi_type, info);
-
- rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TCAM, &tcam_db_ptr);
- if (rc) {
- TFP_DRV_LOG(INFO,
- "Tcam_db is not initialized, rc:%s\n",
- strerror(-rc));
- return 0;
- }
- tcam_db = (struct tcam_rm_db *)tcam_db_ptr;
-
- /* Convert TF type to HCAPI RM type */
- memset(&hparms, 0, sizeof(hparms));
- hparms.rm_db = tcam_db->tcam_db[dir];
- hparms.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- hparms.hcapi_type = hcapi_type;
-
- rc = tf_rm_get_hcapi_type(&hparms);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Get RM hcapi type failed %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
-
- memset(info, 0, sizeof(struct tf_rm_alloc_info));
- ainfo.rm_db = tcam_db->tcam_db[dir];
- ainfo.subtype = TF_TCAM_TBL_TYPE_WC_TCAM;
- ainfo.info = info;
-
- rc = tf_rm_get_info(&ainfo);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed %s\n",
- tf_dir_2_str(dir),
- strerror(-rc));
- return rc;
- }
- return rc;
-}
+#include "tf_rm.h"
+#include "tf_tcam_mgr_msg.h"
/**
* tf_tcam_shared_bind
@@ -247,92 +28,15 @@ int
tf_tcam_shared_bind(struct tf *tfp,
struct tf_tcam_cfg_parms *parms)
{
- int rc, dir;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- struct tf_rm_alloc_info info;
- uint16_t start, stride;
- uint16_t num_slices;
- uint16_t hcapi_type;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc = NULL;
+ int rc;
TF_CHECK_PARMS2(tfp, parms);
/* Perform normal bind
*/
rc = tf_tcam_bind(tfp, parms);
- if (rc)
- return rc;
-
- /* After the normal TCAM bind, if this is a shared session
- * create all required databases for the WC_HI and WC_LO pools
- */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Session access failure: %s\n", strerror(-rc));
- return rc;
- }
- if (tf_session_is_shared_session(tfs)) {
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- tf_tcam_shared_create_db(&tcam_shared_wc);
-
-
- /* If there are WC TCAM entries, create 2 pools each with 1/2
- * the total number of entries
- */
- for (dir = 0; dir < TF_DIR_MAX; dir++) {
- if (!tf_tcam_db_valid(tfp, dir))
- continue;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(dir));
- goto done;
- }
-
- start = info.entry.start;
- stride = info.entry.stride / 2;
-
- tf_tcam_shared_create_wc_pool(dir,
- TF_TCAM_SHARED_WC_POOL_HI,
- start,
- stride,
- tcam_shared_wc);
-
- start += stride;
- tf_tcam_shared_create_wc_pool(dir,
- TF_TCAM_SHARED_WC_POOL_LO,
- start,
- stride,
- tcam_shared_wc);
-
- tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc);
- }
-
- rc = tf_tcam_shared_get_slices(tfp,
- dev,
- &num_slices);
- if (rc)
- return rc;
-
- if (num_slices > 1) {
- TFP_DRV_LOG(ERR,
- "Only single slice supported\n");
- return -EOPNOTSUPP;
- }
- }
-done:
return rc;
+
}
/**
* tf_tcam_shared_unbind
@@ -340,132 +44,10 @@ tf_tcam_shared_bind(struct tf *tfp,
int
tf_tcam_shared_unbind(struct tf *tfp)
{
- int rc, dir;
- struct tf_dev_info *dev;
- struct tf_session *tfs;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- enum tf_tcam_shared_wc_pool_id pool_id;
- struct tf_tcam_free_parms parms;
- struct bitalloc *pool;
- uint16_t start;
- int log_idx, phy_idx;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- int i, pool_cnt;
+ int rc;
TF_CHECK_PARMS1(tfp);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If not the shared session, call the normal
- * tcam unbind and exit
- */
- if (!tf_session_is_shared_session(tfs)) {
- rc = tf_tcam_unbind(tfp);
- return rc;
- }
-
- /* We must be a shared session, get the database
- */
- rc = tf_session_get_tcam_shared_db(tfp,
- (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db, rc:%s\n",
- strerror(-rc));
- return rc;
- }
-
- tcam_shared_wc =
- (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- /* Get the device
- */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
-
- /* If there are WC TCAM entries allocated, free them
- */
- for (dir = 0; dir < TF_DIR_MAX; dir++) {
- /* If the database is invalid, skip
- */
- if (!tf_tcam_db_valid(tfp, dir))
- continue;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM shared rm info get failed\n",
- tf_dir_2_str(dir));
- return rc;
- }
-
- for (pool_id = TF_TCAM_SHARED_WC_POOL_HI;
- pool_id < TF_TCAM_SHARED_WC_POOL_MAX;
- pool_id++) {
- pool = tcam_shared_wc->db[dir][pool_id].pool;
- start = tcam_shared_wc->db[dir][pool_id].info.start;
- pool_cnt = ba_inuse_count(pool);
-
- if (pool_cnt) {
- TFP_DRV_LOG(INFO,
- "%s: %s: %d residuals found, freeing\n",
- tf_dir_2_str(dir),
- tf_pool_2_str(pool_id),
- pool_cnt);
- }
-
- log_idx = 0;
-
- for (i = 0; i < pool_cnt; i++) {
- log_idx = ba_find_next_inuse(pool, log_idx);
-
- if (log_idx < 0) {
- TFP_DRV_LOG(ERR,
- "Expected a found %s entry %d\n",
- tf_pool_2_str(pool_id),
- i);
- /* attempt normal unbind
- */
- goto done;
- }
- phy_idx = start + log_idx;
-
- parms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- parms.hcapi_type = hcapi_type;
- parms.idx = phy_idx;
- parms.dir = dir;
- rc = tf_msg_tcam_entry_free(tfp, dev, &parms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: %d free failed, rc:%s\n",
- tf_dir_2_str(parms.dir),
- tf_tcam_tbl_2_str(parms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- }
- /* Free the pool once all the entries
- * have been cleared
- */
- tf_tcam_shared_free_wc_pool(dir,
- pool_id,
- tcam_shared_wc);
- }
- }
-done:
rc = tf_tcam_unbind(tfp);
return rc;
}
@@ -478,79 +60,11 @@ tf_tcam_shared_alloc(struct tf *tfp,
struct tf_tcam_alloc_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int log_idx;
- struct bitalloc *pool;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or the type is
- * not one of the special WC TCAM types, call the normal
- * allocation.
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal alloc
- */
- rc = tf_tcam_alloc(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
-
- /*
- * priority 0: allocate from top of the tcam i.e. high
- * priority !0: allocate index from bottom i.e lowest
- */
- if (parms->priority)
- log_idx = ba_alloc_reverse(pool);
- else
- log_idx = ba_alloc(pool);
- if (log_idx == BA_FAIL) {
- TFP_DRV_LOG(ERR,
- "%s: Allocation failed, rc:%s\n",
- tf_dir_2_str(parms->dir),
- strerror(ENOMEM));
- return -ENOMEM;
- }
- parms->idx = log_idx;
- return 0;
+ rc = tf_tcam_alloc(tfp, parms);
+ return rc;
}
int
@@ -558,118 +72,11 @@ tf_tcam_shared_free(struct tf *tfp,
struct tf_tcam_free_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- uint16_t start;
- int phy_idx;
- struct bitalloc *pool;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_free_parms nparms;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or the type is
- * not one of the special WC TCAM types, call the normal
- * allocation.
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal free
- */
- rc = tf_tcam_free(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry already free, type:%d, idx:%d\n",
- tf_dir_2_str(parms->dir), parms->type, parms->idx);
- return -EINVAL;
- }
-
- rc = ba_free(pool, parms->idx);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Free failed, type:%s, idx:%d\n",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(parms->type),
- parms->idx);
- return rc;
- }
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms = *parms;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
- nparms.idx = phy_idx;
-
- rc = tf_msg_tcam_entry_free(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: log%d free failed, rc:%s\n",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- return 0;
+ rc = tf_tcam_free(tfp, parms);
+ return rc;
}
int
@@ -677,109 +84,11 @@ tf_tcam_shared_set(struct tf *tfp __rte_unused,
struct tf_tcam_set_parms *parms __rte_unused)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- int phy_idx, log_idx;
- struct tf_tcam_set_parms nparms;
- struct bitalloc *pool;
- uint16_t start;
- enum tf_tcam_shared_wc_pool_id id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
-
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or one of our
- * special types
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal set and exit
- */
- rc = tf_tcam_set(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- log_idx = parms->idx;
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry is not allocated, type:%d, logid:%d\n",
- tf_dir_2_str(parms->dir), parms->type, log_idx);
- return -EINVAL;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc)
- return rc;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms.hcapi_type = hcapi_type;
- nparms.dir = parms->dir;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.idx = phy_idx;
- nparms.key = parms->key;
- nparms.mask = parms->mask;
- nparms.key_size = parms->key_size;
- nparms.result = parms->result;
- nparms.result_size = parms->result_size;
-
- rc = tf_msg_tcam_entry_set(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phy entry %d set failed, rc:%s",
- tf_dir_2_str(parms->dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- return 0;
+ rc = tf_tcam_set(tfp, parms);
+ return rc;
}
int
@@ -787,226 +96,10 @@ tf_tcam_shared_get(struct tf *tfp __rte_unused,
struct tf_tcam_get_parms *parms)
{
int rc;
- struct tf_session *tfs;
- struct tf_dev_info *dev;
- int allocated = 0;
- int phy_idx, log_idx;
- struct tf_tcam_get_parms nparms;
- struct bitalloc *pool;
- uint16_t start;
- enum tf_tcam_shared_wc_pool_id id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
TF_CHECK_PARMS2(tfp, parms);
- /* Retrieve the session information */
- rc = tf_session_get_session_internal(tfp, &tfs);
- if (rc)
- return rc;
-
- /* If we aren't the shared session or one of our
- * special types
- */
- if (!tf_session_is_shared_session(tfs) ||
- (parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_HIGH &&
- parms->type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW)) {
- /* Perform normal get and exit
- */
- rc = tf_tcam_get(tfp, parms);
- return rc;
- }
-
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
- if (parms->type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- pool = tcam_shared_wc->db[parms->dir][id].pool;
- start = tcam_shared_wc->db[parms->dir][id].info.start;
-
- log_idx = parms->idx;
- phy_idx = parms->idx + start;
- allocated = ba_inuse(pool, parms->idx);
-
- if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) {
- TFP_DRV_LOG(ERR,
- "%s: Entry is not allocated, type:%d, logid:%d\n",
- tf_dir_2_str(parms->dir), parms->type, log_idx);
- return -EINVAL;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc)
- return rc;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms = *parms;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
- nparms.idx = phy_idx;
-
- rc = tf_msg_tcam_entry_get(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: Entry %d set failed, rc:%s",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- nparms.idx,
- strerror(-rc));
- return rc;
- }
- return 0;
-}
-
-/* Normally, device specific code wouldn't reside here, it belongs
- * in a separate device specific function in tf_device_pxx.c.
- * But this code is placed here as it is not a long term solution
- * and we would like to have this code centrally located for easy
- * removal
- */
-#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4 12
-#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P4 4
-#define TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 24
-#define TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 8
-
-/* Temporary builder defines pulled in here and adjusted
- * for max WC TCAM values
- */
-union tf_tmp_field_obj {
- uint32_t words[(TF_TCAM_SHARED_REMAP_SZ_BYTES_P58 + 3) / 4];
- uint8_t bytes[TF_TCAM_SHARED_REMAP_SZ_BYTES_P58];
-};
-
-union tf_tmp_key {
- uint32_t words[(TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58 + 3) / 4];
- uint8_t bytes[TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58];
-};
-
-/** p58 has an enable bit, p4 does not
- */
-#define TF_TCAM_SHARED_ENTRY_ENABLE 0x8
-
-/** Move a WC TCAM entry from the high offset to the same low offset
- */
-static int
-tf_tcam_shared_move_entry(struct tf *tfp,
- struct tf_dev_info *dev,
- uint16_t hcapi_type,
- enum tf_dir dir,
- int sphy_idx,
- int dphy_idx,
- int key_sz_bytes,
- int remap_sz_bytes,
- bool set_enable_bit)
-{
- int rc = 0;
- struct tf_tcam_get_parms gparms;
- struct tf_tcam_set_parms sparms;
- struct tf_tcam_free_parms fparms;
- union tf_tmp_key tcam_key_obj;
- union tf_tmp_key tcam_key_msk_obj;
- union tf_tmp_field_obj tcam_remap_obj;
-
- memset(&tcam_key_obj, 0, sizeof(tcam_key_obj));
- memset(&tcam_key_msk_obj, 0, sizeof(tcam_key_msk_obj));
- memset(&tcam_remap_obj, 0, sizeof(tcam_remap_obj));
- memset(&gparms, 0, sizeof(gparms));
-
- gparms.hcapi_type = hcapi_type;
- gparms.dir = dir;
- gparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- gparms.idx = sphy_idx;
- gparms.key = (uint8_t *)&tcam_key_obj;
- gparms.key_size = key_sz_bytes;
- gparms.mask = (uint8_t *)&tcam_key_msk_obj;
- gparms.result = (uint8_t *)&tcam_remap_obj;
- gparms.result_size = remap_sz_bytes;
-
- rc = tf_msg_tcam_entry_get(tfp, dev, &gparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phyid(%d) get failed, rc:%s\n",
- tf_tcam_tbl_2_str(gparms.type),
- tf_dir_2_str(dir),
- gparms.idx,
- strerror(-rc));
- return rc;
- }
-
- if (set_enable_bit)
- tcam_key_obj.bytes[0] |= TF_TCAM_SHARED_ENTRY_ENABLE;
-
- /* Override HI/LO type with parent WC TCAM type */
- sparms.hcapi_type = hcapi_type;
- sparms.dir = dir;
- sparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- sparms.idx = dphy_idx;
- sparms.key = gparms.key;
- sparms.mask = gparms.mask;
- sparms.key_size = key_sz_bytes;
- sparms.result = gparms.result;
- sparms.result_size = remap_sz_bytes;
-
- rc = tf_msg_tcam_entry_set(tfp, dev, &sparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s phyid(%d/0x%x) set failed, rc:%s\n",
- tf_tcam_tbl_2_str(sparms.type),
- tf_dir_2_str(dir),
- sparms.idx,
- sparms.idx,
- strerror(-rc));
- return rc;
- }
-
- /* Override HI/LO type with parent WC TCAM type */
- fparms.dir = dir;
- fparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- fparms.hcapi_type = hcapi_type;
- fparms.idx = sphy_idx;
-
- rc = tf_msg_tcam_entry_free(tfp, dev, &fparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: phyid(%d/0x%x) free failed, rc:%s\n",
- tf_dir_2_str(dir),
- tf_tcam_tbl_2_str(fparms.type),
- sphy_idx,
- sphy_idx,
- strerror(-rc));
- return rc;
- }
+ rc = tf_tcam_get(tfp, parms);
return rc;
}
@@ -1015,23 +108,10 @@ tf_tcam_shared_move_entry(struct tf *tfp,
*/
static
int tf_tcam_shared_move(struct tf *tfp,
- struct tf_move_tcam_shared_entries_parms *parms,
- int key_sz_bytes,
- int remap_sz_bytes,
- bool set_enable_bit)
+ struct tf_move_tcam_shared_entries_parms *parms)
{
- int rc;
struct tf_session *tfs;
- struct tf_dev_info *dev;
- int log_idx;
- struct bitalloc *hi_pool, *lo_pool;
- uint16_t hi_start, lo_start;
- enum tf_tcam_shared_wc_pool_id hi_id, lo_id;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- int hi_cnt, i;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- void *tcam_shared_db_ptr = NULL;
+ int rc;
TF_CHECK_PARMS2(tfp, parms);
@@ -1052,104 +132,7 @@ int tf_tcam_shared_move(struct tf *tfp,
return -EOPNOTSUPP;
}
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc) {
- /* TODO print amazing error */
- return rc;
- }
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
- hi_id = TF_TCAM_SHARED_WC_POOL_HI;
- hi_pool = tcam_shared_wc->db[parms->dir][hi_id].pool;
- hi_start = tcam_shared_wc->db[parms->dir][hi_id].info.start;
-
- lo_id = TF_TCAM_SHARED_WC_POOL_LO;
- lo_pool = tcam_shared_wc->db[parms->dir][lo_id].pool;
- lo_start = tcam_shared_wc->db[parms->dir][lo_id].info.start;
-
- if (hi_pool == NULL || lo_pool == NULL)
- return -ENOMEM;
-
- /* Get the total count of in use entries in the high pool
- */
- hi_cnt = ba_inuse_count(hi_pool);
-
- /* Copy each valid entry to the same low pool logical offset
- */
- log_idx = 0;
-
- for (i = 0; i < hi_cnt; i++) {
- /* Find next free index starting from where we left off
- */
- log_idx = ba_find_next_inuse(hi_pool, log_idx);
- if (log_idx < 0) {
- TFP_DRV_LOG(ERR,
- "Expected a found %s entry %d\n",
- tf_pool_2_str(hi_id),
- i);
- goto done;
- }
- /* The user should have never allocated from the low
- * pool because the move only happens when switching
- * from the high to the low pool
- */
- if (ba_alloc_index(lo_pool, log_idx) < 0) {
- TFP_DRV_LOG(ERR,
- "Warning %s index %d already allocated\n",
- tf_pool_2_str(lo_id),
- i);
-
- /* Since already allocated, continue with move
- */
- }
-
- rc = tf_tcam_shared_move_entry(tfp, dev,
- hcapi_type,
- parms->dir,
- hi_start + log_idx,
- lo_start + log_idx,
- key_sz_bytes,
- remap_sz_bytes,
- set_enable_bit);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: Move error %s to %s index %d\n",
- tf_dir_2_str(parms->dir),
- tf_pool_2_str(hi_id),
- tf_pool_2_str(lo_id),
- i);
- goto done;
- }
- ba_free(hi_pool, log_idx);
- }
-done:
+ rc = tf_tcam_mgr_shared_move_msg(tfp, parms);
return rc;
}
@@ -1159,24 +142,17 @@ tf_tcam_shared_move_p4(struct tf *tfp,
{
int rc = 0;
rc = tf_tcam_shared_move(tfp,
- parms,
- TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P4,
- TF_TCAM_SHARED_REMAP_SZ_BYTES_P4,
- false); /* no enable bit */
+ parms);
return rc;
}
-
int
tf_tcam_shared_move_p58(struct tf *tfp,
struct tf_move_tcam_shared_entries_parms *parms)
{
int rc = 0;
rc = tf_tcam_shared_move(tfp,
- parms,
- TF_TCAM_SHARED_KEY_SLICE_SZ_BYTES_P58,
- TF_TCAM_SHARED_REMAP_SZ_BYTES_P58,
- true); /* set enable bit */
+ parms);
return rc;
}
@@ -1186,16 +162,6 @@ tf_tcam_shared_clear(struct tf *tfp,
{
int rc = 0;
struct tf_session *tfs;
- struct tf_dev_info *dev;
- uint16_t start;
- int phy_idx;
- enum tf_tcam_shared_wc_pool_id id;
- struct tf_tcam_free_parms nparms;
- uint16_t hcapi_type;
- struct tf_rm_alloc_info info;
- void *tcam_shared_db_ptr = NULL;
- struct tf_tcam_shared_wc_pools *tcam_shared_wc;
- int i, cnt;
TF_CHECK_PARMS2(tfp, parms);
@@ -1209,74 +175,6 @@ tf_tcam_shared_clear(struct tf *tfp,
parms->tcam_tbl_type != TF_TCAM_TBL_TYPE_WC_TCAM_LOW))
return -EOPNOTSUPP;
- if (!tf_tcam_db_valid(tfp, parms->dir)) {
- TFP_DRV_LOG(ERR,
- "%s: tcam shared pool doesn't exist\n",
- tf_dir_2_str(parms->dir));
- return -ENOMEM;
- }
-
- rc = tf_session_get_tcam_shared_db(tfp, (void *)&tcam_shared_db_ptr);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "Failed to get tcam_shared_db from session, rc:%s\n",
- strerror(-rc));
- return rc;
- }
- tcam_shared_wc = (struct tf_tcam_shared_wc_pools *)tcam_shared_db_ptr;
-
-
- if (parms->tcam_tbl_type == TF_TCAM_TBL_TYPE_WC_TCAM_HIGH)
- id = TF_TCAM_SHARED_WC_POOL_HI;
- else
- id = TF_TCAM_SHARED_WC_POOL_LO;
-
-
- /* Retrieve the device information */
- rc = tf_session_get_device(tfs, &dev);
- if (rc)
- return rc;
-
- rc = tf_tcam_shared_get_rm_info(tfp,
- parms->dir,
- &hcapi_type,
- &info);
- if (rc) {
- TFP_DRV_LOG(ERR,
- "%s: TCAM rm info get failed\n",
- tf_dir_2_str(parms->dir));
- return rc;
- }
-
- start = tcam_shared_wc->db[parms->dir][id].info.start;
- cnt = tcam_shared_wc->db[parms->dir][id].info.stride;
-
- /* Override HI/LO type with parent WC TCAM type */
- nparms.dir = parms->dir;
- nparms.type = TF_TCAM_TBL_TYPE_WC_TCAM;
- nparms.hcapi_type = hcapi_type;
-
- for (i = 0; i < cnt; i++) {
- phy_idx = start + i;
- nparms.idx = phy_idx;
-
- /* Clear entry */
- rc = tf_msg_tcam_entry_free(tfp, dev, &nparms);
- if (rc) {
- /* Log error */
- TFP_DRV_LOG(ERR,
- "%s: %s: log%d free failed, rc:%s\n",
- tf_dir_2_str(nparms.dir),
- tf_tcam_tbl_2_str(nparms.type),
- phy_idx,
- strerror(-rc));
- return rc;
- }
- }
-
- TFP_DRV_LOG(DEBUG,
- "%s: TCAM shared clear pool(%s)\n",
- tf_dir_2_str(nparms.dir),
- tf_pool_2_str(id));
- return 0;
+ rc = tf_tcam_mgr_shared_clear_msg(tfp, parms);
+ return rc;
}
diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.h b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
index 524631f262..e25babcd18 100644
--- a/drivers/net/bnxt/tf_core/tf_tcam_shared.h
+++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -129,7 +129,6 @@ int tf_tcam_shared_set(struct tf *tfp,
int tf_tcam_shared_get(struct tf *tfp,
struct tf_tcam_get_parms *parms);
-
/**
* Moves entries from the WC_TCAM_HI to the WC_TCAM_LO shared pools
* for the P4 device.
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 1bb38399e4..8513ee06a9 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -448,13 +448,13 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
switch (ulp_dev_id) {
case BNXT_ULP_DEVICE_ID_WH_PLUS:
- parms.device_type = TF_DEVICE_TYPE_WH;
+ parms.device_type = TF_DEVICE_TYPE_P5;
break;
case BNXT_ULP_DEVICE_ID_STINGRAY:
parms.device_type = TF_DEVICE_TYPE_SR;
break;
case BNXT_ULP_DEVICE_ID_THOR:
- parms.device_type = TF_DEVICE_TYPE_THOR;
+ parms.device_type = TF_DEVICE_TYPE_P4;
break;
default:
BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n");
@@ -563,13 +563,13 @@ ulp_ctx_session_open(struct bnxt *bp,
switch (ulp_dev_id) {
case BNXT_ULP_DEVICE_ID_WH_PLUS:
- params.device_type = TF_DEVICE_TYPE_WH;
+ params.device_type = TF_DEVICE_TYPE_P5;
break;
case BNXT_ULP_DEVICE_ID_STINGRAY:
params.device_type = TF_DEVICE_TYPE_SR;
break;
case BNXT_ULP_DEVICE_ID_THOR:
- params.device_type = TF_DEVICE_TYPE_THOR;
+ params.device_type = TF_DEVICE_TYPE_P4;
break;
default:
BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n");
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 05/11] net/bnxt: update ULP shared session support
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (3 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 04/11] net/bnxt: update Truflow core Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
` (5 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev
Cc: ferruh.yigit, thomas, Randy Schacher, Kishore Padmanabha, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 3548252 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Update ulp generic templates
- Modify code to support shared sessions
This should allow more than one application to share a TruFlow
session.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 16 +-
drivers/net/bnxt/bnxt_ethdev.c | 8 +-
drivers/net/bnxt/bnxt_reps.c | 4 +-
drivers/net/bnxt/tf_core/tf_rm.c | 28 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 548 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 109 +-
.../bnxt/tf_ulp/generic_templates/meson.build | 3 -
.../generic_templates/ulp_template_db_act.c | 6999 +++-
.../generic_templates/ulp_template_db_class.c | 33541 +++++++++++-----
.../generic_templates/ulp_template_db_enum.h | 4365 +-
.../generic_templates/ulp_template_db_field.h | 689 +-
.../generic_templates/ulp_template_db_tbl.c | 16056 ++++++--
.../ulp_template_db_thor_act.c | 8714 ++--
.../ulp_template_db_thor_class.c | 10737 +++--
.../ulp_template_db_wh_plus_act.c | 1157 +-
.../ulp_template_db_wh_plus_class.c | 287 +-
drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 16 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 25 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 7 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 29 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 15 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 10 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 281 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 10 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 17 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 22 +-
27 files changed, 63055 insertions(+), 20644 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 2bccdec7e0..bb2e7fe003 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -633,6 +633,13 @@ struct bnxt_ring_stats {
uint64_t rx_agg_aborts;
};
+enum bnxt_session_type {
+ BNXT_SESSION_TYPE_REGULAR = 0,
+ BNXT_SESSION_TYPE_SHARED_COMMON,
+ BNXT_SESSION_TYPE_SHARED_WC,
+ BNXT_SESSION_TYPE_LAST
+};
+
struct bnxt {
void *bar0;
@@ -690,6 +697,9 @@ struct bnxt {
#define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1)
#define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \
((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
+#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
+#define BNXT_TESTPMD_EN(bp) \
+ ((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
uint16_t chip_num;
#define CHIP_NUM_58818 0xd818
@@ -855,8 +865,7 @@ struct bnxt {
uint16_t func_svif;
uint16_t port_svif;
- struct tf tfp;
- struct tf tfp_shared;
+ struct tf tfp[BNXT_SESSION_TYPE_LAST];
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_stat_info *flow_stat;
uint16_t max_num_kflows;
@@ -1044,4 +1053,5 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ef7b8859d9..bcde44bb14 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -6415,6 +6415,12 @@ bool is_bnxt_supported(struct rte_eth_dev *dev)
return is_device_supported(dev, &bnxt_rte_pmd);
}
+struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type)
+{
+ return (type >= BNXT_SESSION_TYPE_LAST) ?
+ &bp->tfp[BNXT_SESSION_TYPE_REGULAR] : &bp->tfp[type];
+}
+
RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 8a5b777793..78337431af 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -327,7 +327,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
(void)bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
/* Update the ULP portdata base with the new VFR interface */
- rc = ulp_port_db_dev_port_intf_update(parent_bp->ulp_ctx, vfr_ethdev);
+ rc = ulp_port_db_port_update(parent_bp->ulp_ctx, vfr_ethdev);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to update ulp port details vfr:%u\n",
vfr->vf_id);
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 1fccb698d0..9b85f5397d 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -364,8 +364,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
struct tf_rm_element_cfg *cfg,
uint16_t *alloc_cnt,
uint16_t num_elements,
- uint16_t *req_cnt,
- bool shared_session)
+ uint16_t *req_cnt)
{
int parent, child;
const char *type_str = NULL;
@@ -376,11 +375,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
/* If I am a parent */
if (cfg[parent].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_PARENT) {
- uint8_t p_slices = 1;
-
- /* Shared session doesn't support slices */
- if (!shared_session)
- p_slices = cfg[parent].slices;
+ uint8_t p_slices = cfg[parent].slices;
RTE_ASSERT(p_slices);
@@ -402,12 +397,9 @@ tf_rm_update_parent_reservations(struct tf *tfp,
TF_RM_ELEM_CFG_HCAPI_BA_CHILD &&
cfg[child].parent_subtype == parent &&
alloc_cnt[child]) {
- uint8_t c_slices = 1;
+ uint8_t c_slices = cfg[child].slices;
uint16_t cnt = 0;
- if (!shared_session)
- c_slices = cfg[child].slices;
-
RTE_ASSERT(c_slices);
dev->ops->tf_dev_get_resource_str(tfp,
@@ -429,7 +421,7 @@ tf_rm_update_parent_reservations(struct tf *tfp,
}
}
/* Save the parent count to be requested */
- req_cnt[parent] = combined_cnt;
+ req_cnt[parent] = combined_cnt * 2;
}
}
return 0;
@@ -452,7 +444,6 @@ tf_rm_create_db(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
- bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -505,15 +496,12 @@ tf_rm_create_db(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
- shared_session = tf_session_is_shared_session(tfs);
-
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt,
- shared_session);
+ req_cnt);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
@@ -733,7 +721,6 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
struct tf_rm_new_db *rm_db;
struct tf_rm_element *db;
uint32_t pool_size;
- bool shared_session = 0;
TF_CHECK_PARMS2(tfp, parms);
@@ -763,15 +750,12 @@ tf_rm_create_db_no_reservation(struct tf *tfp,
tfp_memcpy(req_cnt, parms->alloc_cnt,
parms->num_elements * sizeof(uint16_t));
- shared_session = tf_session_is_shared_session(tfs);
-
/* Update the req_cnt based upon the element configuration
*/
tf_rm_update_parent_reservations(tfp, dev, parms->cfg,
parms->alloc_cnt,
parms->num_elements,
- req_cnt,
- shared_session);
+ req_cnt);
/* Process capabilities against DB requirements. However, as a
* DB can hold elements that are not HCAPI we can reduce the
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 8513ee06a9..109bd0652a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -13,6 +13,7 @@
#include "bnxt.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "hsi_struct_def_dpdk.h"
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
@@ -26,6 +27,7 @@
#include "ulp_tun.h"
#include "ulp_ha_mgr.h"
#include "bnxt_tf_pmd_shim.h"
+#include "ulp_template_db_tbl.h"
/* Linked list of all TF sessions. */
STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list =
@@ -91,6 +93,17 @@ bnxt_ulp_app_cap_list_get(uint32_t *num_entries)
return ulp_app_cap_info_list;
}
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries)
+{
+ if (!num_entries)
+ return NULL;
+
+ *num_entries = BNXT_ULP_GEN_TBL_MAX_SZ;
+
+ return ulp_shared_act_info;
+}
+
static struct bnxt_ulp_resource_resv_info *
bnxt_ulp_app_resource_resv_list_get(uint32_t *num_entries)
{
@@ -122,6 +135,7 @@ static int32_t
bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_glb_resource_info *info,
uint32_t num,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST, res_type, i;
@@ -149,6 +163,11 @@ bnxt_ulp_named_resources_calc(struct bnxt_ulp_context *ulp_ctx,
for (i = 0; i < num; i++) {
if (dev_id != info[i].device_id || app_id != info[i].app_id)
continue;
+ /* check to see if the session type matches only then include */
+ if ((stype || info[i].session_type) &&
+ !(info[i].session_type & stype))
+ continue;
+
dir = info[i].direction;
res_type = info[i].resource_type;
@@ -179,6 +198,7 @@ static int32_t
bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_resource_resv_info *info,
uint32_t num,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
uint32_t dev_id, res_type, i;
@@ -206,6 +226,12 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
for (i = 0; i < num; i++) {
if (app_id != info[i].app_id || dev_id != info[i].device_id)
continue;
+
+ /* check to see if the session type matches only then include */
+ if ((stype || info[i].session_type) &&
+ !(info[i].session_type & stype))
+ continue;
+
dir = info[i].direction;
res_type = info[i].resource_type;
@@ -231,6 +257,7 @@ bnxt_ulp_unnamed_resources_calc(struct bnxt_ulp_context *ulp_ctx,
static int32_t
bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
struct bnxt_ulp_resource_resv_info *unnamed = NULL;
@@ -242,13 +269,18 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
+ /* use DEFAULT_NON_HA instead of DEFAULT resources if HA is disabled */
+ if (ULP_APP_HA_IS_DYNAMIC(ulp_ctx))
+ stype = ulp_ctx->cfg_data->def_session_type;
+
unnamed = bnxt_ulp_resource_resv_list_get(&unum);
if (unnamed == NULL) {
BNXT_TF_DBG(ERR, "Unable to get resource resv list.\n");
return -EINVAL;
}
- rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+ rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+ res);
if (rc)
BNXT_TF_DBG(ERR, "Unable to calc resources for session.\n");
@@ -257,6 +289,7 @@ bnxt_ulp_tf_resources_get(struct bnxt_ulp_context *ulp_ctx,
static int32_t
bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
+ enum bnxt_ulp_session_type stype,
struct tf_session_resources *res)
{
struct bnxt_ulp_resource_resv_info *unnamed;
@@ -272,6 +305,10 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
/* Make sure the resources are zero before accumulating. */
memset(res, 0, sizeof(struct tf_session_resources));
+ if (bnxt_ulp_cntxt_ha_enabled(ulp_ctx) &&
+ stype == BNXT_ULP_SESSION_TYPE_SHARED)
+ stype = ulp_ctx->cfg_data->hu_session_type;
+
/*
* Shared resources are comprised of both named and unnamed resources.
* First get the unnamed counts, and then add the named to the result.
@@ -282,9 +319,11 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Unable to get shared resource resv list.\n");
return -EINVAL;
}
- rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, res);
+ rc = bnxt_ulp_unnamed_resources_calc(ulp_ctx, unnamed, unum, stype,
+ res);
if (rc) {
- BNXT_TF_DBG(ERR, "Unable to calc resources for shared session.\n");
+ BNXT_TF_DBG(ERR,
+ "Unable to calc resources for shared session.\n");
return -EINVAL;
}
@@ -294,7 +333,7 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Unable to get app global resource list\n");
return -EINVAL;
}
- rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, res);
+ rc = bnxt_ulp_named_resources_calc(ulp_ctx, named, nnum, stype, res);
if (rc)
BNXT_TF_DBG(ERR, "Unable to calc named resources\n");
@@ -356,17 +395,127 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
return 0;
}
+/* Function to set the number for vxlan_ip (custom vxlan) port into the context */
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_ip_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->vxlan_ip_port = vxlan_ip_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan_ip (custom vxlan) port from the context. */
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->vxlan_ip_port;
+}
+
+/* Function to set the number for vxlan port into the context */
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->vxlan_port = vxlan_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan port from the context. */
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->vxlan_port;
+}
+
+static inline uint32_t
+bnxt_ulp_session_idx_get(enum bnxt_ulp_session_type session_type) {
+ if (session_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ return 1;
+ else if (session_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ return 2;
+ return 0;
+}
+
+/* Function to set the tfp session details in session */
+static int32_t
+bnxt_ulp_session_tfp_set(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type,
+ struct tf *tfp)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+ int32_t rc = 0;
+
+ if (!session->session_opened[idx]) {
+ session->g_tfp[idx] = rte_zmalloc("bnxt_ulp_session_tfp",
+ sizeof(struct tf), 0);
+ if (!session->g_tfp[idx]) {
+ BNXT_TF_DBG(DEBUG, "Failed to alloc session tfp\n");
+ return -ENOMEM;
+ }
+ session->g_tfp[idx]->session = tfp->session;
+ session->session_opened[idx] = 1;
+ }
+ return rc;
+}
+
+/* Function to get the tfp session details in session */
+static struct tf_session_info *
+bnxt_ulp_session_tfp_get(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ if (session->session_opened[idx])
+ return session->g_tfp[idx]->session;
+ return NULL;
+}
+
+static uint32_t
+bnxt_ulp_session_is_open(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ return session->session_opened[idx];
+}
+
+/* Function to reset the tfp session details in session */
+static void
+bnxt_ulp_session_tfp_reset(struct bnxt_ulp_session_state *session,
+ enum bnxt_ulp_session_type session_type)
+{
+ uint32_t idx = bnxt_ulp_session_idx_get(session_type);
+
+ if (session->session_opened[idx]) {
+ session->session_opened[idx] = 0;
+ rte_free(session->g_tfp[idx]);
+ session->g_tfp[idx] = NULL;
+ }
+}
+
static void
ulp_ctx_shared_session_close(struct bnxt *bp,
+ enum bnxt_ulp_session_type session_type,
struct bnxt_ulp_session_state *session)
{
struct tf *tfp;
int32_t rc;
- if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
- return;
-
- tfp = bnxt_ulp_cntxt_shared_tfp_get(bp->ulp_ctx);
+ tfp = bnxt_ulp_cntxt_tfp_get(bp->ulp_ctx, session_type);
if (!tfp) {
/*
* Log it under debug since this is likely a case of the
@@ -380,29 +529,26 @@ ulp_ctx_shared_session_close(struct bnxt *bp,
if (rc)
BNXT_TF_DBG(ERR, "Failed to close the shared session rc=%d.\n",
rc);
- (void)bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, NULL);
-
- session->g_shared_tfp.session = NULL;
+ (void)bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, NULL);
+ bnxt_ulp_session_tfp_reset(session, session_type);
}
static int32_t
ulp_ctx_shared_session_open(struct bnxt *bp,
+ enum bnxt_ulp_session_type session_type,
struct bnxt_ulp_session_state *session)
{
struct rte_eth_dev *ethdev = bp->eth_dev;
struct tf_session_resources *resources;
struct tf_open_session_parms parms;
- size_t copy_nbytes;
+ size_t nb;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
int32_t rc = 0;
uint8_t app_id;
-
- /* only perform this if shared session is enabled. */
- if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
- return 0;
+ struct tf *tfp;
+ uint8_t pool_id;
memset(&parms, 0, sizeof(parms));
-
rc = rte_eth_dev_get_name_by_port(ethdev->data->port_id,
parms.ctrl_chan_name);
if (rc) {
@@ -416,21 +562,39 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
* Need to account for size of ctrl_chan_name and 1 extra for Null
* terminator
*/
- copy_nbytes = sizeof(parms.ctrl_chan_name) -
- strlen(parms.ctrl_chan_name) - 1;
+ nb = sizeof(parms.ctrl_chan_name) - strlen(parms.ctrl_chan_name) - 1;
/*
* Build the ctrl_chan_name with shared token.
* When HA is enabled, the WC TCAM needs extra management by the core,
* so add the wc_tcam string to the control channel.
*/
- if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
- strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam",
- copy_nbytes);
- else
- strncat(parms.ctrl_chan_name, "-tf_shared", copy_nbytes);
+ pool_id = bp->ulp_ctx->cfg_data->ha_pool_id;
+ if (!bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ if (bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx))
+ strncat(parms.ctrl_chan_name, "-tf_shared-wc_tcam", nb);
+ else
+ strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+ } else if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ if (session_type == BNXT_ULP_SESSION_TYPE_SHARED) {
+ strncat(parms.ctrl_chan_name, "-tf_shared", nb);
+ } else if (session_type == BNXT_ULP_SESSION_TYPE_SHARED_WC) {
+ char session_pool_name[64];
+
+ sprintf(session_pool_name, "-tf_shared-pool%d",
+ pool_id);
+
+ if (nb >= strlen(session_pool_name)) {
+ strncat(parms.ctrl_chan_name, session_pool_name, nb);
+ } else {
+ BNXT_TF_DBG(ERR, "No space left for session_name\n");
+ return -EINVAL;
+ }
+ }
+ }
- rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, resources);
+ rc = bnxt_ulp_tf_shared_session_resources_get(bp->ulp_ctx, session_type,
+ resources);
if (rc)
return rc;
@@ -446,32 +610,15 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
return rc;
}
- switch (ulp_dev_id) {
- case BNXT_ULP_DEVICE_ID_WH_PLUS:
- parms.device_type = TF_DEVICE_TYPE_P5;
- break;
- case BNXT_ULP_DEVICE_ID_STINGRAY:
- parms.device_type = TF_DEVICE_TYPE_SR;
- break;
- case BNXT_ULP_DEVICE_ID_THOR:
- parms.device_type = TF_DEVICE_TYPE_P4;
- break;
- default:
- BNXT_TF_DBG(ERR, "Unable to determine dev for opening session.\n");
- return rc;
- }
-
+ tfp = bnxt_ulp_bp_tfp_get(bp, session_type);
+ parms.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
parms.bp = bp;
- if (app_id == 0)
- parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
- else
- parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
/*
* Open the session here, but the collect the resources during the
* mapper initialization.
*/
- rc = tf_open_session(&bp->tfp_shared, &parms);
+ rc = tf_open_session(tfp, &parms);
if (rc)
return rc;
@@ -481,40 +628,70 @@ ulp_ctx_shared_session_open(struct bnxt *bp,
BNXT_TF_DBG(DEBUG, "Shared session attached.\n");
/* Save the shared session in global data */
- if (!session->g_shared_tfp.session)
- session->g_shared_tfp.session = bp->tfp_shared.session;
+ rc = bnxt_ulp_session_tfp_set(session, session_type, tfp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add shared tfp to session\n");
+ return rc;
+ }
- rc = bnxt_ulp_cntxt_shared_tfp_set(bp->ulp_ctx, &bp->tfp_shared);
- if (rc)
+ rc = bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, session_type, tfp);
+ if (rc) {
BNXT_TF_DBG(ERR, "Failed to add shared tfp to ulp (%d)\n", rc);
+ return rc;
+ }
return rc;
}
static int32_t
ulp_ctx_shared_session_attach(struct bnxt *bp,
- struct bnxt_ulp_session_state *session)
+ struct bnxt_ulp_session_state *ses)
{
+ enum bnxt_ulp_session_type type;
+ struct tf *tfp;
int32_t rc = 0;
/* Simply return success if shared session not enabled */
if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
- bp->tfp_shared.session = session->g_shared_tfp.session;
- rc = ulp_ctx_shared_session_open(bp, session);
+ type = BNXT_ULP_SESSION_TYPE_SHARED;
+ tfp = bnxt_ulp_bp_tfp_get(bp, type);
+ tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+ rc = ulp_ctx_shared_session_open(bp, type, ses);
+ }
+
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ type = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+ tfp = bnxt_ulp_bp_tfp_get(bp, type);
+ tfp->session = bnxt_ulp_session_tfp_get(ses, type);
+ rc = ulp_ctx_shared_session_open(bp, type, ses);
}
+ if (!rc)
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
return rc;
}
static void
ulp_ctx_shared_session_detach(struct bnxt *bp)
{
+ struct tf *tfp;
+
if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
- if (bp->tfp_shared.session) {
- tf_close_session(&bp->tfp_shared);
- bp->tfp_shared.session = NULL;
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
}
}
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
+ }
+ }
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
}
/*
@@ -538,6 +715,7 @@ ulp_ctx_session_open(struct bnxt *bp,
struct tf_session_resources *resources;
uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
uint8_t app_id;
+ struct tf *tfp;
memset(¶ms, 0, sizeof(params));
@@ -561,43 +739,29 @@ ulp_ctx_session_open(struct bnxt *bp,
return rc;
}
- switch (ulp_dev_id) {
- case BNXT_ULP_DEVICE_ID_WH_PLUS:
- params.device_type = TF_DEVICE_TYPE_P5;
- break;
- case BNXT_ULP_DEVICE_ID_STINGRAY:
- params.device_type = TF_DEVICE_TYPE_SR;
- break;
- case BNXT_ULP_DEVICE_ID_THOR:
- params.device_type = TF_DEVICE_TYPE_P4;
- break;
- default:
- BNXT_TF_DBG(ERR, "Unable to determine device for opening session.\n");
- return rc;
- }
-
+ params.device_type = bnxt_ulp_cntxt_convert_dev_id(ulp_dev_id);
resources = ¶ms.resources;
- rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx, resources);
+ rc = bnxt_ulp_tf_resources_get(bp->ulp_ctx,
+ BNXT_ULP_SESSION_TYPE_DEFAULT,
+ resources);
if (rc)
return rc;
params.bp = bp;
- if (app_id == 0)
- params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW;
- else
- params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW;
- rc = tf_open_session(&bp->tfp, ¶ms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_open_session(tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n",
params.ctrl_chan_name, rc);
return -EINVAL;
}
- if (!session->session_opened) {
- session->session_opened = 1;
- session->g_tfp = rte_zmalloc("bnxt_ulp_session_tfp",
- sizeof(struct tf), 0);
- session->g_tfp->session = bp->tfp.session;
+ rc = bnxt_ulp_session_tfp_set(session,
+ BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set TF session - %s, rc = %d\n",
+ params.ctrl_chan_name, rc);
+ return -EINVAL;
}
return rc;
}
@@ -610,12 +774,14 @@ static void
ulp_ctx_session_close(struct bnxt *bp,
struct bnxt_ulp_session_state *session)
{
+ struct tf *tfp;
+
/* close the session in the hardware */
- if (session->session_opened)
- tf_close_session(&bp->tfp);
- session->session_opened = 0;
- rte_free(session->g_tfp);
- session->g_tfp = NULL;
+ if (bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) {
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ tf_close_session(tfp);
+ }
+ bnxt_ulp_session_tfp_reset(session, BNXT_ULP_SESSION_TYPE_DEFAULT);
}
static void
@@ -678,6 +844,7 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
struct bnxt_ulp_device_params *dparms;
enum bnxt_ulp_flow_mem_type mtype;
uint32_t dev_id;
+ struct tf *tfp;
int rc;
/* Get the dev specific number of flows that needed to be supported. */
@@ -700,12 +867,14 @@ ulp_eem_tbl_scope_init(struct bnxt *bp)
}
bnxt_init_tbl_scope_parms(bp, ¶ms);
- rc = tf_alloc_tbl_scope(&bp->tfp, ¶ms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_alloc_tbl_scope(tfp, ¶ms);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to allocate eem table scope rc = %d\n",
rc);
return rc;
}
+
rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id);
if (rc) {
BNXT_TF_DBG(ERR, "Unable to set table scope id\n");
@@ -729,7 +898,7 @@ ulp_eem_tbl_scope_deinit(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx)
if (!ulp_ctx || !ulp_ctx->cfg_data)
return -EINVAL;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
return -EINVAL;
@@ -777,7 +946,16 @@ ulp_ctx_deinit(struct bnxt *bp,
ulp_ctx_session_close(bp, session);
/* The shared session must be closed last. */
- ulp_ctx_shared_session_close(bp, session);
+ if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx))
+ ulp_ctx_shared_session_close(bp, BNXT_ULP_SESSION_TYPE_SHARED,
+ session);
+
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx))
+ ulp_ctx_shared_session_close(bp,
+ BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ session);
+
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, false);
/* Free the contents */
if (session->cfg_data) {
@@ -796,6 +974,8 @@ ulp_ctx_init(struct bnxt *bp,
struct bnxt_ulp_data *ulp_data;
int32_t rc = 0;
enum bnxt_ulp_device_id devid;
+ enum bnxt_ulp_session_type stype;
+ struct tf *tfp;
/* Initialize the context entries list */
bnxt_ulp_cntxt_list_init();
@@ -851,22 +1031,42 @@ ulp_ctx_init(struct bnxt *bp,
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
*/
- rc = ulp_ctx_shared_session_open(bp, session);
- if (rc) {
- BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n", rc);
- goto error_deinit;
+ if (bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) {
+ rc = ulp_ctx_shared_session_open(bp,
+ BNXT_ULP_SESSION_TYPE_SHARED,
+ session);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to open shared session (%d)\n",
+ rc);
+ goto error_deinit;
+ }
}
+ /* Multiple session support */
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(bp->ulp_ctx)) {
+ stype = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+ rc = ulp_ctx_shared_session_open(bp, stype, session);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Unable to open shared wc session (%d)\n",
+ rc);
+ goto error_deinit;
+ }
+ }
+ bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
+
+
/* Open the ulp session. */
rc = ulp_ctx_session_open(bp, session);
if (rc)
goto error_deinit;
- bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
error_deinit:
- session->session_opened = 1;
+ session->session_opened[BNXT_ULP_SESSION_TYPE_DEFAULT] = 1;
(void)ulp_ctx_deinit(bp, session);
return rc;
}
@@ -932,6 +1132,7 @@ ulp_ctx_attach(struct bnxt *bp,
{
int32_t rc = 0;
uint32_t flags, dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ struct tf *tfp;
uint8_t app_id;
/* Increment the ulp context data reference count usage. */
@@ -939,7 +1140,9 @@ ulp_ctx_attach(struct bnxt *bp,
bp->ulp_ctx->cfg_data->ref_cnt++;
/* update the session details in bnxt tfp */
- bp->tfp.session = session->g_tfp->session;
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ tfp->session = bnxt_ulp_session_tfp_get(session,
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
/* Add the context to the context entries list */
rc = bnxt_ulp_cntxt_list_add(bp->ulp_ctx);
@@ -975,20 +1178,23 @@ ulp_ctx_attach(struct bnxt *bp,
rc = ulp_ctx_session_open(bp, session);
if (rc) {
PMD_DRV_LOG(ERR, "Failed to open ctxt session, rc:%d\n", rc);
- bp->tfp.session = NULL;
+ tfp->session = NULL;
return rc;
}
- bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
+ bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
}
static void
ulp_ctx_detach(struct bnxt *bp)
{
- if (bp->tfp.session) {
- tf_close_session(&bp->tfp);
- bp->tfp.session = NULL;
+ struct tf *tfp;
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ if (tfp->session) {
+ tf_close_session(tfp);
+ tfp->session = NULL;
}
}
@@ -1121,6 +1327,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
uint32_t global_cfg = 0;
int rc;
struct tf_global_cfg_parms parms = { 0 };
+ struct tf *tfp;
/* Initialize the params */
parms.dir = dir,
@@ -1129,7 +1336,8 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
parms.config = (uint8_t *)&global_cfg,
parms.config_sz_in_bytes = sizeof(global_cfg);
- rc = tf_get_global_cfg(&bp->tfp, &parms);
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_global_cfg(tfp, &parms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n",
type, rc);
@@ -1142,7 +1350,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
global_cfg &= ~value;
/* SET the register RE_CFA_REG_ACT_TECT */
- rc = tf_set_global_cfg(&bp->tfp, &parms);
+ rc = tf_set_global_cfg(tfp, &parms);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n",
type, rc);
@@ -1473,7 +1681,7 @@ bnxt_ulp_port_init(struct bnxt *bp)
}
/* update the port database for the given interface */
- rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp->eth_dev);
+ rc = ulp_port_db_port_update(bp->ulp_ctx, bp->eth_dev);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to update port database\n");
goto jump_to_error;
@@ -1624,6 +1832,12 @@ bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
return ULP_SHARED_SESSION_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags);
}
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx)
+{
+ return ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx);
+}
+
int32_t
bnxt_ulp_cntxt_app_id_set(struct bnxt_ulp_context *ulp_ctx, uint8_t app_id)
{
@@ -1721,74 +1935,86 @@ bnxt_ulp_cntxt_tbl_scope_id_set(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
-/* Function to set the shared tfp session details from the ulp context. */
-int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
-{
- if (!ulp) {
- BNXT_TF_DBG(ERR, "Invalid arguments\n");
- return -EINVAL;
- }
-
- if (tfp == NULL) {
- if (ulp->cfg_data->num_shared_clients > 0)
- ulp->cfg_data->num_shared_clients--;
- } else {
- ulp->cfg_data->num_shared_clients++;
- }
-
- ulp->g_shared_tfp = tfp;
- return 0;
-}
-
-/* Function to get the shared tfp session details from the ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp)
+/* Function to get the number of shared clients attached */
+uint8_t
+bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
{
- if (!ulp) {
+ if (ulp == NULL || ulp->cfg_data == NULL) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
- return NULL;
+ return 0;
}
- return ulp->g_shared_tfp;
+ return ulp->cfg_data->num_shared_clients;
}
-/* Function to get the number of shared clients attached */
-uint8_t
-bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp)
+/* Function to set the number of shared clients */
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp, bool incr)
{
if (ulp == NULL || ulp->cfg_data == NULL) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return 0;
}
- return ulp->cfg_data->num_shared_clients;
+ if (incr)
+ ulp->cfg_data->num_shared_clients++;
+ else if (ulp->cfg_data->num_shared_clients)
+ ulp->cfg_data->num_shared_clients--;
+
+ BNXT_TF_DBG(DEBUG, "%d:clients(%d)\n", incr,
+ ulp->cfg_data->num_shared_clients);
+
+ return 0;
}
/* Function to set the tfp session details from the ulp context. */
int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp)
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+ enum bnxt_ulp_session_type s_type,
+ struct tf *tfp)
{
+ uint32_t idx = 0;
+
if (!ulp) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return -EINVAL;
}
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+ if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ idx = 1;
+ else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ idx = 2;
+
+ } else {
+ if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+ (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ idx = 1;
+ }
- ulp->g_tfp = tfp;
+ ulp->g_tfp[idx] = tfp;
return 0;
}
/* Function to get the tfp session details from the ulp context. */
struct tf *
bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
- enum bnxt_ulp_shared_session shared)
+ enum bnxt_ulp_session_type s_type)
{
+ uint32_t idx = 0;
+
if (!ulp) {
BNXT_TF_DBG(ERR, "Invalid arguments\n");
return NULL;
}
- if (shared)
- return ulp->g_shared_tfp;
- else
- return ulp->g_tfp;
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp)) {
+ if (s_type & BNXT_ULP_SESSION_TYPE_SHARED)
+ idx = 1;
+ else if (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ idx = 2;
+ } else {
+ if ((s_type & BNXT_ULP_SESSION_TYPE_SHARED) ||
+ (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ idx = 1;
+ }
+ return ulp->g_tfp[idx];
}
/*
@@ -2079,3 +2305,41 @@ bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
return ulp->cfg_data->app_tun;
}
+
+/* Function to convert ulp dev id to regular dev id. */
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
+{
+ enum tf_device_type type = 0;
+
+ switch (ulp_dev_id) {
+ case BNXT_ULP_DEVICE_ID_WH_PLUS:
+ type = TF_DEVICE_TYPE_P4;
+ break;
+ case BNXT_ULP_DEVICE_ID_STINGRAY:
+ type = TF_DEVICE_TYPE_SR;
+ break;
+ case BNXT_ULP_DEVICE_ID_THOR:
+ type = TF_DEVICE_TYPE_P5;
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid device id\n");
+ break;
+ }
+ return type;
+}
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type)
+{
+ enum bnxt_session_type btype;
+
+ if (type & BNXT_ULP_SESSION_TYPE_SHARED)
+ btype = BNXT_SESSION_TYPE_SHARED_COMMON;
+ else if (type & BNXT_ULP_SESSION_TYPE_SHARED_WC)
+ btype = BNXT_SESSION_TYPE_SHARED_WC;
+ else
+ btype = BNXT_SESSION_TYPE_REGULAR;
+
+ return bnxt_get_tfp_session(bp, btype);
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 906d933af5..9b30851b13 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -35,6 +35,11 @@
#define BNXT_ULP_HIGH_AVAIL_ENABLED 0x8
#define BNXT_ULP_APP_UNICAST_ONLY 0x10
#define BNXT_ULP_APP_SOCKET_DIRECT 0x20
+#define BNXT_ULP_APP_TOS_PROTO_SUPPORT 0x40
+#define BNXT_ULP_APP_BC_MC_SUPPORT 0x80
+#define BNXT_ULP_CUST_VXLAN_SUPPORT 0x100
+#define BNXT_ULP_MULTI_SHARED_SUPPORT 0x200
+#define BNXT_ULP_APP_HA_DYNAMIC 0x400
#define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED)
#define ULP_SHARED_SESSION_IS_ENABLED(flag) ((flag) &\
@@ -43,6 +48,17 @@
BNXT_ULP_APP_DEV_UNSUPPORTED)
#define ULP_HIGH_AVAIL_IS_ENABLED(flag) ((flag) & BNXT_ULP_HIGH_AVAIL_ENABLED)
#define ULP_SOCKET_DIRECT_IS_ENABLED(flag) ((flag) & BNXT_ULP_APP_SOCKET_DIRECT)
+#define ULP_APP_TOS_PROTO_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_TOS_PROTO_SUPPORT)
+#define ULP_APP_BC_MC_SUPPORT(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_BC_MC_SUPPORT)
+#define ULP_MULTI_SHARED_IS_SUPPORTED(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_MULTI_SHARED_SUPPORT)
+#define ULP_APP_HA_IS_DYNAMIC(ctx) ((ctx)->cfg_data->ulp_flags &\
+ BNXT_ULP_APP_HA_DYNAMIC)
+
+#define ULP_APP_CUST_VXLAN_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_port != 0)
+#define ULP_APP_CUST_VXLAN_IP_SUPPORT(ctx) ((ctx)->cfg_data->vxlan_ip_port != 0)
enum bnxt_ulp_flow_mem_type {
BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
@@ -95,12 +111,19 @@ struct bnxt_ulp_data {
uint8_t app_id;
uint8_t num_shared_clients;
struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
+ uint32_t vxlan_port;
+ uint32_t vxlan_ip_port;
+ uint8_t hu_reg_state;
+ uint8_t hu_reg_cnt;
+ uint32_t hu_session_type;
+ uint8_t ha_pool_id;
+ enum bnxt_ulp_session_type def_session_type;
};
+#define BNXT_ULP_SESSION_MAX 3
struct bnxt_ulp_context {
struct bnxt_ulp_data *cfg_data;
- struct tf *g_tfp;
- struct tf *g_shared_tfp;
+ struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
};
struct bnxt_ulp_pci_info {
@@ -110,13 +133,12 @@ struct bnxt_ulp_pci_info {
struct bnxt_ulp_session_state {
STAILQ_ENTRY(bnxt_ulp_session_state) next;
- bool bnxt_ulp_init;
- pthread_mutex_t bnxt_ulp_mutex;
- struct bnxt_ulp_pci_info pci_info;
- struct bnxt_ulp_data *cfg_data;
- struct tf *g_tfp;
- struct tf g_shared_tfp;
- uint32_t session_opened;
+ bool bnxt_ulp_init;
+ pthread_mutex_t bnxt_ulp_mutex;
+ struct bnxt_ulp_pci_info pci_info;
+ struct bnxt_ulp_data *cfg_data;
+ struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
+ uint32_t session_opened[BNXT_ULP_SESSION_MAX];
};
/* ULP flow id structure */
@@ -172,20 +194,14 @@ bnxt_ulp_cntxt_tbl_scope_id_get(struct bnxt_ulp_context *ulp_ctx,
/* Function to set the tfp session details in the ulp context. */
int32_t
-bnxt_ulp_cntxt_shared_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
-
-/* Function to get the tfp session details from ulp context. */
-struct tf *
-bnxt_ulp_cntxt_shared_tfp_get(struct bnxt_ulp_context *ulp);
-
-/* Function to set the tfp session details in the ulp context. */
-int32_t
-bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp, struct tf *tfp);
+bnxt_ulp_cntxt_tfp_set(struct bnxt_ulp_context *ulp,
+ enum bnxt_ulp_session_type s_type,
+ struct tf *tfp);
/* Function to get the tfp session details from ulp context. */
struct tf *
bnxt_ulp_cntxt_tfp_get(struct bnxt_ulp_context *ulp,
- enum bnxt_ulp_shared_session shared);
+ enum bnxt_ulp_session_type s_type);
/* Get the device table entry based on the device id. */
struct bnxt_ulp_device_params *
@@ -238,6 +254,7 @@ int32_t
ulp_default_flow_create(struct rte_eth_dev *eth_dev,
struct ulp_tlv_param *param_list,
uint32_t ulp_class_tid,
+ uint16_t port_id,
uint32_t *flow_id);
/* Function to destroy default flows. */
@@ -274,6 +291,20 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
void
bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx);
+int32_t
+bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle,
+ uint32_t *action_handle_type);
+
+struct bnxt_ulp_shared_act_info *
+bnxt_ulp_shared_act_info_get(uint32_t *num_entries);
+
+int32_t
+bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle,
+ uint32_t *dir);
+
+uint32_t
+bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle);
+
struct bnxt_ulp_glb_resource_info *
bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries);
@@ -286,6 +317,9 @@ bnxt_ulp_cntxt_app_id_get(struct bnxt_ulp_context *ulp_ctx, uint8_t *app_id);
bool
bnxt_ulp_cntxt_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
+bool
+bnxt_ulp_cntxt_multi_shared_session_enabled(struct bnxt_ulp_context *ulp_ctx);
+
struct bnxt_ulp_app_capabilities_info *
bnxt_ulp_app_cap_list_get(uint32_t *num_entries);
@@ -315,6 +349,41 @@ bnxt_ulp_cntxt_entry_release(void);
uint8_t
bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_cntxt_num_shared_clients_set(struct bnxt_ulp_context *ulp_ctx,
+ bool incr);
+
struct bnxt_flow_app_tun_ent *
bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp);
+
+/* Function to get the truflow app id. This defined in the build file */
+uint32_t
+bnxt_ulp_default_app_id_get(void);
+
+int
+bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_port);
+unsigned int
+bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t vxlan_ip_port);
+unsigned int
+bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
+
+int32_t
+bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx,
+ uint8_t state, uint8_t cnt);
+
+uint32_t
+bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx);
+
+uint32_t
+bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
+
+struct tf*
+bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
index 4ace838a3c..b1e7b8cc32 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build
@@ -2,10 +2,7 @@
# Copyright(c) 2018 Intel Corporation
# Copyright(c) 2020 Broadcom
-#Include the folder for headers
includes += include_directories('.')
-
-#Add the source files
sources += files(
'ulp_template_db_class.c',
'ulp_template_db_act.c',
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index ce878d8e02..7f1eba369e 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Aug 25 14:37:06 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -16,98 +14,550 @@
*/
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_0000] = 1,
- [BNXT_ULP_ACT_HID_0001] = 2,
- [BNXT_ULP_ACT_HID_0400] = 3,
- [BNXT_ULP_ACT_HID_01ab] = 4,
- [BNXT_ULP_ACT_HID_0010] = 5,
- [BNXT_ULP_ACT_HID_05ab] = 6,
- [BNXT_ULP_ACT_HID_01bb] = 7,
- [BNXT_ULP_ACT_HID_0002] = 8,
- [BNXT_ULP_ACT_HID_0003] = 9,
- [BNXT_ULP_ACT_HID_0402] = 10,
- [BNXT_ULP_ACT_HID_01ad] = 11,
- [BNXT_ULP_ACT_HID_0012] = 12,
- [BNXT_ULP_ACT_HID_05ad] = 13,
- [BNXT_ULP_ACT_HID_01bd] = 14,
- [BNXT_ULP_ACT_HID_0613] = 15,
- [BNXT_ULP_ACT_HID_02a9] = 16,
- [BNXT_ULP_ACT_HID_0054] = 17,
- [BNXT_ULP_ACT_HID_0622] = 18,
- [BNXT_ULP_ACT_HID_0454] = 19,
- [BNXT_ULP_ACT_HID_0064] = 20,
- [BNXT_ULP_ACT_HID_0614] = 21,
- [BNXT_ULP_ACT_HID_0615] = 22,
- [BNXT_ULP_ACT_HID_02ab] = 23,
- [BNXT_ULP_ACT_HID_0056] = 24,
- [BNXT_ULP_ACT_HID_0624] = 25,
- [BNXT_ULP_ACT_HID_0456] = 26,
- [BNXT_ULP_ACT_HID_0066] = 27,
- [BNXT_ULP_ACT_HID_048d] = 28,
- [BNXT_ULP_ACT_HID_048f] = 29,
- [BNXT_ULP_ACT_HID_04bc] = 30,
- [BNXT_ULP_ACT_HID_00a9] = 31,
- [BNXT_ULP_ACT_HID_020f] = 32,
- [BNXT_ULP_ACT_HID_0153] = 33,
- [BNXT_ULP_ACT_HID_04a9] = 34,
- [BNXT_ULP_ACT_HID_01fc] = 35,
- [BNXT_ULP_ACT_HID_04be] = 36,
- [BNXT_ULP_ACT_HID_00ab] = 37,
- [BNXT_ULP_ACT_HID_0211] = 38,
- [BNXT_ULP_ACT_HID_0155] = 39,
- [BNXT_ULP_ACT_HID_04ab] = 40,
- [BNXT_ULP_ACT_HID_01fe] = 41,
- [BNXT_ULP_ACT_HID_0667] = 42,
- [BNXT_ULP_ACT_HID_0254] = 43,
- [BNXT_ULP_ACT_HID_03ba] = 44,
- [BNXT_ULP_ACT_HID_02fe] = 45,
- [BNXT_ULP_ACT_HID_0654] = 46,
- [BNXT_ULP_ACT_HID_03a7] = 47,
- [BNXT_ULP_ACT_HID_0669] = 48,
- [BNXT_ULP_ACT_HID_0256] = 49,
- [BNXT_ULP_ACT_HID_03bc] = 50,
- [BNXT_ULP_ACT_HID_0300] = 51,
- [BNXT_ULP_ACT_HID_0656] = 52,
- [BNXT_ULP_ACT_HID_03a9] = 53,
- [BNXT_ULP_ACT_HID_021b] = 54,
- [BNXT_ULP_ACT_HID_021c] = 55,
- [BNXT_ULP_ACT_HID_021e] = 56,
- [BNXT_ULP_ACT_HID_063f] = 57,
- [BNXT_ULP_ACT_HID_0510] = 58,
- [BNXT_ULP_ACT_HID_03c6] = 59,
- [BNXT_ULP_ACT_HID_0082] = 60,
- [BNXT_ULP_ACT_HID_06bb] = 61,
- [BNXT_ULP_ACT_HID_021d] = 62,
- [BNXT_ULP_ACT_HID_0641] = 63,
- [BNXT_ULP_ACT_HID_0512] = 64,
- [BNXT_ULP_ACT_HID_03c8] = 65,
- [BNXT_ULP_ACT_HID_0084] = 66,
- [BNXT_ULP_ACT_HID_06bd] = 67,
- [BNXT_ULP_ACT_HID_06d7] = 68,
- [BNXT_ULP_ACT_HID_02c4] = 69,
- [BNXT_ULP_ACT_HID_042a] = 70,
- [BNXT_ULP_ACT_HID_036e] = 71,
- [BNXT_ULP_ACT_HID_06c4] = 72,
- [BNXT_ULP_ACT_HID_0417] = 73,
- [BNXT_ULP_ACT_HID_06d9] = 74,
- [BNXT_ULP_ACT_HID_02c6] = 75,
- [BNXT_ULP_ACT_HID_042c] = 76,
- [BNXT_ULP_ACT_HID_0370] = 77,
- [BNXT_ULP_ACT_HID_06c6] = 78,
- [BNXT_ULP_ACT_HID_0419] = 79,
- [BNXT_ULP_ACT_HID_0119] = 80,
- [BNXT_ULP_ACT_HID_046f] = 81,
- [BNXT_ULP_ACT_HID_05d5] = 82,
- [BNXT_ULP_ACT_HID_0519] = 83,
- [BNXT_ULP_ACT_HID_0106] = 84,
- [BNXT_ULP_ACT_HID_05c2] = 85,
- [BNXT_ULP_ACT_HID_011b] = 86,
- [BNXT_ULP_ACT_HID_0471] = 87,
- [BNXT_ULP_ACT_HID_05d7] = 88,
- [BNXT_ULP_ACT_HID_051b] = 89,
- [BNXT_ULP_ACT_HID_0108] = 90,
- [BNXT_ULP_ACT_HID_05c4] = 91,
- [BNXT_ULP_ACT_HID_00a2] = 92,
- [BNXT_ULP_ACT_HID_00a4] = 93
+ [BNXT_ULP_ACT_HID_0008] = 2,
+ [BNXT_ULP_ACT_HID_2000] = 3,
+ [BNXT_ULP_ACT_HID_1988] = 4,
+ [BNXT_ULP_ACT_HID_0080] = 5,
+ [BNXT_ULP_ACT_HID_3988] = 6,
+ [BNXT_ULP_ACT_HID_1a08] = 7,
+ [BNXT_ULP_ACT_HID_0010] = 8,
+ [BNXT_ULP_ACT_HID_0040] = 9,
+ [BNXT_ULP_ACT_HID_0050] = 10,
+ [BNXT_ULP_ACT_HID_0018] = 11,
+ [BNXT_ULP_ACT_HID_2010] = 12,
+ [BNXT_ULP_ACT_HID_1998] = 13,
+ [BNXT_ULP_ACT_HID_0090] = 14,
+ [BNXT_ULP_ACT_HID_3998] = 15,
+ [BNXT_ULP_ACT_HID_1a18] = 16,
+ [BNXT_ULP_ACT_HID_32ea] = 17,
+ [BNXT_ULP_ACT_HID_32f2] = 18,
+ [BNXT_ULP_ACT_HID_52ea] = 19,
+ [BNXT_ULP_ACT_HID_4c72] = 20,
+ [BNXT_ULP_ACT_HID_336a] = 21,
+ [BNXT_ULP_ACT_HID_6c72] = 22,
+ [BNXT_ULP_ACT_HID_4cf2] = 23,
+ [BNXT_ULP_ACT_HID_32fa] = 24,
+ [BNXT_ULP_ACT_HID_3302] = 25,
+ [BNXT_ULP_ACT_HID_52fa] = 26,
+ [BNXT_ULP_ACT_HID_4c82] = 27,
+ [BNXT_ULP_ACT_HID_337a] = 28,
+ [BNXT_ULP_ACT_HID_6c82] = 29,
+ [BNXT_ULP_ACT_HID_4d02] = 30,
+ [BNXT_ULP_ACT_HID_0808] = 31,
+ [BNXT_ULP_ACT_HID_1008] = 32,
+ [BNXT_ULP_ACT_HID_1808] = 33,
+ [BNXT_ULP_ACT_HID_0818] = 34,
+ [BNXT_ULP_ACT_HID_1018] = 35,
+ [BNXT_ULP_ACT_HID_1818] = 36,
+ [BNXT_ULP_ACT_HID_0880] = 37,
+ [BNXT_ULP_ACT_HID_1080] = 38,
+ [BNXT_ULP_ACT_HID_1880] = 39,
+ [BNXT_ULP_ACT_HID_0890] = 40,
+ [BNXT_ULP_ACT_HID_1090] = 41,
+ [BNXT_ULP_ACT_HID_1890] = 42,
+ [BNXT_ULP_ACT_HID_3af2] = 43,
+ [BNXT_ULP_ACT_HID_42f2] = 44,
+ [BNXT_ULP_ACT_HID_4af2] = 45,
+ [BNXT_ULP_ACT_HID_3b02] = 46,
+ [BNXT_ULP_ACT_HID_4302] = 47,
+ [BNXT_ULP_ACT_HID_4b02] = 48,
+ [BNXT_ULP_ACT_HID_3b6a] = 49,
+ [BNXT_ULP_ACT_HID_436a] = 50,
+ [BNXT_ULP_ACT_HID_4b6a] = 51,
+ [BNXT_ULP_ACT_HID_3b7a] = 52,
+ [BNXT_ULP_ACT_HID_437a] = 53,
+ [BNXT_ULP_ACT_HID_4b7a] = 54,
+ [BNXT_ULP_ACT_HID_640d] = 55,
+ [BNXT_ULP_ACT_HID_641d] = 56,
+ [BNXT_ULP_ACT_HID_071a] = 57,
+ [BNXT_ULP_ACT_HID_0800] = 58,
+ [BNXT_ULP_ACT_HID_1000] = 59,
+ [BNXT_ULP_ACT_HID_1800] = 60,
+ [BNXT_ULP_ACT_HID_0810] = 61,
+ [BNXT_ULP_ACT_HID_1010] = 62,
+ [BNXT_ULP_ACT_HID_1810] = 63,
+ [BNXT_ULP_ACT_HID_1110] = 64,
+ [BNXT_ULP_ACT_HID_4420] = 65,
+ [BNXT_ULP_ACT_HID_2220] = 66,
+ [BNXT_ULP_ACT_HID_0c84] = 67,
+ [BNXT_ULP_ACT_HID_3f94] = 68,
+ [BNXT_ULP_ACT_HID_3330] = 69,
+ [BNXT_ULP_ACT_HID_50a4] = 70,
+ [BNXT_ULP_ACT_HID_1910] = 71,
+ [BNXT_ULP_ACT_HID_4c20] = 72,
+ [BNXT_ULP_ACT_HID_2a20] = 73,
+ [BNXT_ULP_ACT_HID_1484] = 74,
+ [BNXT_ULP_ACT_HID_4794] = 75,
+ [BNXT_ULP_ACT_HID_3b30] = 76,
+ [BNXT_ULP_ACT_HID_58a4] = 77,
+ [BNXT_ULP_ACT_HID_2110] = 78,
+ [BNXT_ULP_ACT_HID_5420] = 79,
+ [BNXT_ULP_ACT_HID_3220] = 80,
+ [BNXT_ULP_ACT_HID_1c84] = 81,
+ [BNXT_ULP_ACT_HID_4f94] = 82,
+ [BNXT_ULP_ACT_HID_4330] = 83,
+ [BNXT_ULP_ACT_HID_60a4] = 84,
+ [BNXT_ULP_ACT_HID_2910] = 85,
+ [BNXT_ULP_ACT_HID_5c20] = 86,
+ [BNXT_ULP_ACT_HID_3a20] = 87,
+ [BNXT_ULP_ACT_HID_2484] = 88,
+ [BNXT_ULP_ACT_HID_5794] = 89,
+ [BNXT_ULP_ACT_HID_4b30] = 90,
+ [BNXT_ULP_ACT_HID_68a4] = 91,
+ [BNXT_ULP_ACT_HID_1120] = 92,
+ [BNXT_ULP_ACT_HID_4430] = 93,
+ [BNXT_ULP_ACT_HID_2230] = 94,
+ [BNXT_ULP_ACT_HID_0c94] = 95,
+ [BNXT_ULP_ACT_HID_3fa4] = 96,
+ [BNXT_ULP_ACT_HID_3340] = 97,
+ [BNXT_ULP_ACT_HID_50b4] = 98,
+ [BNXT_ULP_ACT_HID_1920] = 99,
+ [BNXT_ULP_ACT_HID_4c30] = 100,
+ [BNXT_ULP_ACT_HID_2a30] = 101,
+ [BNXT_ULP_ACT_HID_1494] = 102,
+ [BNXT_ULP_ACT_HID_47a4] = 103,
+ [BNXT_ULP_ACT_HID_3b40] = 104,
+ [BNXT_ULP_ACT_HID_58b4] = 105,
+ [BNXT_ULP_ACT_HID_2120] = 106,
+ [BNXT_ULP_ACT_HID_5430] = 107,
+ [BNXT_ULP_ACT_HID_3230] = 108,
+ [BNXT_ULP_ACT_HID_1c94] = 109,
+ [BNXT_ULP_ACT_HID_4fa4] = 110,
+ [BNXT_ULP_ACT_HID_4340] = 111,
+ [BNXT_ULP_ACT_HID_60b4] = 112,
+ [BNXT_ULP_ACT_HID_2920] = 113,
+ [BNXT_ULP_ACT_HID_5c30] = 114,
+ [BNXT_ULP_ACT_HID_3a30] = 115,
+ [BNXT_ULP_ACT_HID_2494] = 116,
+ [BNXT_ULP_ACT_HID_57a4] = 117,
+ [BNXT_ULP_ACT_HID_4b40] = 118,
+ [BNXT_ULP_ACT_HID_68b4] = 119,
+ [BNXT_ULP_ACT_HID_2a98] = 120,
+ [BNXT_ULP_ACT_HID_5da8] = 121,
+ [BNXT_ULP_ACT_HID_3ba8] = 122,
+ [BNXT_ULP_ACT_HID_260c] = 123,
+ [BNXT_ULP_ACT_HID_591c] = 124,
+ [BNXT_ULP_ACT_HID_6a2c] = 125,
+ [BNXT_ULP_ACT_HID_2aa8] = 126,
+ [BNXT_ULP_ACT_HID_5db8] = 127,
+ [BNXT_ULP_ACT_HID_3bb8] = 128,
+ [BNXT_ULP_ACT_HID_261c] = 129,
+ [BNXT_ULP_ACT_HID_592c] = 130,
+ [BNXT_ULP_ACT_HID_6a3c] = 131,
+ [BNXT_ULP_ACT_HID_3298] = 132,
+ [BNXT_ULP_ACT_HID_65a8] = 133,
+ [BNXT_ULP_ACT_HID_43a8] = 134,
+ [BNXT_ULP_ACT_HID_2e0c] = 135,
+ [BNXT_ULP_ACT_HID_611c] = 136,
+ [BNXT_ULP_ACT_HID_722c] = 137,
+ [BNXT_ULP_ACT_HID_32a8] = 138,
+ [BNXT_ULP_ACT_HID_65b8] = 139,
+ [BNXT_ULP_ACT_HID_43b8] = 140,
+ [BNXT_ULP_ACT_HID_2e1c] = 141,
+ [BNXT_ULP_ACT_HID_612c] = 142,
+ [BNXT_ULP_ACT_HID_723c] = 143,
+ [BNXT_ULP_ACT_HID_3a98] = 144,
+ [BNXT_ULP_ACT_HID_6da8] = 145,
+ [BNXT_ULP_ACT_HID_4ba8] = 146,
+ [BNXT_ULP_ACT_HID_360c] = 147,
+ [BNXT_ULP_ACT_HID_691c] = 148,
+ [BNXT_ULP_ACT_HID_7a2c] = 149,
+ [BNXT_ULP_ACT_HID_3aa8] = 150,
+ [BNXT_ULP_ACT_HID_6db8] = 151,
+ [BNXT_ULP_ACT_HID_4bb8] = 152,
+ [BNXT_ULP_ACT_HID_361c] = 153,
+ [BNXT_ULP_ACT_HID_692c] = 154,
+ [BNXT_ULP_ACT_HID_7a3c] = 155,
+ [BNXT_ULP_ACT_HID_4298] = 156,
+ [BNXT_ULP_ACT_HID_75a8] = 157,
+ [BNXT_ULP_ACT_HID_53a8] = 158,
+ [BNXT_ULP_ACT_HID_3e0c] = 159,
+ [BNXT_ULP_ACT_HID_711c] = 160,
+ [BNXT_ULP_ACT_HID_0670] = 161,
+ [BNXT_ULP_ACT_HID_42a8] = 162,
+ [BNXT_ULP_ACT_HID_75b8] = 163,
+ [BNXT_ULP_ACT_HID_53b8] = 164,
+ [BNXT_ULP_ACT_HID_3e1c] = 165,
+ [BNXT_ULP_ACT_HID_712c] = 166,
+ [BNXT_ULP_ACT_HID_0680] = 167,
+ [BNXT_ULP_ACT_HID_3aea] = 168,
+ [BNXT_ULP_ACT_HID_42ea] = 169,
+ [BNXT_ULP_ACT_HID_4aea] = 170,
+ [BNXT_ULP_ACT_HID_3afa] = 171,
+ [BNXT_ULP_ACT_HID_42fa] = 172,
+ [BNXT_ULP_ACT_HID_4afa] = 173,
+ [BNXT_ULP_ACT_HID_43fa] = 174,
+ [BNXT_ULP_ACT_HID_770a] = 175,
+ [BNXT_ULP_ACT_HID_550a] = 176,
+ [BNXT_ULP_ACT_HID_3f6e] = 177,
+ [BNXT_ULP_ACT_HID_727e] = 178,
+ [BNXT_ULP_ACT_HID_661a] = 179,
+ [BNXT_ULP_ACT_HID_07d2] = 180,
+ [BNXT_ULP_ACT_HID_4bfa] = 181,
+ [BNXT_ULP_ACT_HID_034e] = 182,
+ [BNXT_ULP_ACT_HID_5d0a] = 183,
+ [BNXT_ULP_ACT_HID_476e] = 184,
+ [BNXT_ULP_ACT_HID_7a7e] = 185,
+ [BNXT_ULP_ACT_HID_6e1a] = 186,
+ [BNXT_ULP_ACT_HID_0fd2] = 187,
+ [BNXT_ULP_ACT_HID_53fa] = 188,
+ [BNXT_ULP_ACT_HID_0b4e] = 189,
+ [BNXT_ULP_ACT_HID_650a] = 190,
+ [BNXT_ULP_ACT_HID_4f6e] = 191,
+ [BNXT_ULP_ACT_HID_06c2] = 192,
+ [BNXT_ULP_ACT_HID_761a] = 193,
+ [BNXT_ULP_ACT_HID_17d2] = 194,
+ [BNXT_ULP_ACT_HID_5bfa] = 195,
+ [BNXT_ULP_ACT_HID_134e] = 196,
+ [BNXT_ULP_ACT_HID_6d0a] = 197,
+ [BNXT_ULP_ACT_HID_576e] = 198,
+ [BNXT_ULP_ACT_HID_0ec2] = 199,
+ [BNXT_ULP_ACT_HID_025e] = 200,
+ [BNXT_ULP_ACT_HID_1fd2] = 201,
+ [BNXT_ULP_ACT_HID_440a] = 202,
+ [BNXT_ULP_ACT_HID_771a] = 203,
+ [BNXT_ULP_ACT_HID_551a] = 204,
+ [BNXT_ULP_ACT_HID_3f7e] = 205,
+ [BNXT_ULP_ACT_HID_728e] = 206,
+ [BNXT_ULP_ACT_HID_662a] = 207,
+ [BNXT_ULP_ACT_HID_07e2] = 208,
+ [BNXT_ULP_ACT_HID_4c0a] = 209,
+ [BNXT_ULP_ACT_HID_035e] = 210,
+ [BNXT_ULP_ACT_HID_5d1a] = 211,
+ [BNXT_ULP_ACT_HID_477e] = 212,
+ [BNXT_ULP_ACT_HID_7a8e] = 213,
+ [BNXT_ULP_ACT_HID_6e2a] = 214,
+ [BNXT_ULP_ACT_HID_0fe2] = 215,
+ [BNXT_ULP_ACT_HID_540a] = 216,
+ [BNXT_ULP_ACT_HID_0b5e] = 217,
+ [BNXT_ULP_ACT_HID_651a] = 218,
+ [BNXT_ULP_ACT_HID_4f7e] = 219,
+ [BNXT_ULP_ACT_HID_06d2] = 220,
+ [BNXT_ULP_ACT_HID_762a] = 221,
+ [BNXT_ULP_ACT_HID_17e2] = 222,
+ [BNXT_ULP_ACT_HID_5c0a] = 223,
+ [BNXT_ULP_ACT_HID_135e] = 224,
+ [BNXT_ULP_ACT_HID_6d1a] = 225,
+ [BNXT_ULP_ACT_HID_577e] = 226,
+ [BNXT_ULP_ACT_HID_0ed2] = 227,
+ [BNXT_ULP_ACT_HID_026e] = 228,
+ [BNXT_ULP_ACT_HID_1fe2] = 229,
+ [BNXT_ULP_ACT_HID_5d82] = 230,
+ [BNXT_ULP_ACT_HID_14d6] = 231,
+ [BNXT_ULP_ACT_HID_6e92] = 232,
+ [BNXT_ULP_ACT_HID_58f6] = 233,
+ [BNXT_ULP_ACT_HID_104a] = 234,
+ [BNXT_ULP_ACT_HID_215a] = 235,
+ [BNXT_ULP_ACT_HID_5d92] = 236,
+ [BNXT_ULP_ACT_HID_14e6] = 237,
+ [BNXT_ULP_ACT_HID_6ea2] = 238,
+ [BNXT_ULP_ACT_HID_5906] = 239,
+ [BNXT_ULP_ACT_HID_105a] = 240,
+ [BNXT_ULP_ACT_HID_216a] = 241,
+ [BNXT_ULP_ACT_HID_6582] = 242,
+ [BNXT_ULP_ACT_HID_1cd6] = 243,
+ [BNXT_ULP_ACT_HID_7692] = 244,
+ [BNXT_ULP_ACT_HID_60f6] = 245,
+ [BNXT_ULP_ACT_HID_184a] = 246,
+ [BNXT_ULP_ACT_HID_295a] = 247,
+ [BNXT_ULP_ACT_HID_6592] = 248,
+ [BNXT_ULP_ACT_HID_1ce6] = 249,
+ [BNXT_ULP_ACT_HID_76a2] = 250,
+ [BNXT_ULP_ACT_HID_6106] = 251,
+ [BNXT_ULP_ACT_HID_185a] = 252,
+ [BNXT_ULP_ACT_HID_296a] = 253,
+ [BNXT_ULP_ACT_HID_6d82] = 254,
+ [BNXT_ULP_ACT_HID_24d6] = 255,
+ [BNXT_ULP_ACT_HID_02d6] = 256,
+ [BNXT_ULP_ACT_HID_68f6] = 257,
+ [BNXT_ULP_ACT_HID_204a] = 258,
+ [BNXT_ULP_ACT_HID_315a] = 259,
+ [BNXT_ULP_ACT_HID_6d92] = 260,
+ [BNXT_ULP_ACT_HID_24e6] = 261,
+ [BNXT_ULP_ACT_HID_02e6] = 262,
+ [BNXT_ULP_ACT_HID_6906] = 263,
+ [BNXT_ULP_ACT_HID_205a] = 264,
+ [BNXT_ULP_ACT_HID_316a] = 265,
+ [BNXT_ULP_ACT_HID_7582] = 266,
+ [BNXT_ULP_ACT_HID_2cd6] = 267,
+ [BNXT_ULP_ACT_HID_0ad6] = 268,
+ [BNXT_ULP_ACT_HID_70f6] = 269,
+ [BNXT_ULP_ACT_HID_284a] = 270,
+ [BNXT_ULP_ACT_HID_395a] = 271,
+ [BNXT_ULP_ACT_HID_7592] = 272,
+ [BNXT_ULP_ACT_HID_2ce6] = 273,
+ [BNXT_ULP_ACT_HID_0ae6] = 274,
+ [BNXT_ULP_ACT_HID_7106] = 275,
+ [BNXT_ULP_ACT_HID_285a] = 276,
+ [BNXT_ULP_ACT_HID_396a] = 277,
+ [BNXT_ULP_ACT_HID_0020] = 278,
+ [BNXT_ULP_ACT_HID_0030] = 279,
+ [BNXT_ULP_ACT_HID_65d4] = 280,
+ [BNXT_ULP_ACT_HID_65e4] = 281,
+ [BNXT_ULP_ACT_HID_330a] = 282,
+ [BNXT_ULP_ACT_HID_331a] = 283,
+ [BNXT_ULP_ACT_HID_1cfe] = 284,
+ [BNXT_ULP_ACT_HID_1d0e] = 285,
+ [BNXT_ULP_ACT_HID_1474] = 286,
+ [BNXT_ULP_ACT_HID_4838] = 287,
+ [BNXT_ULP_ACT_HID_6458] = 288,
+ [BNXT_ULP_ACT_HID_1c68] = 289,
+ [BNXT_ULP_ACT_HID_6c34] = 290,
+ [BNXT_ULP_ACT_HID_5d08] = 291,
+ [BNXT_ULP_ACT_HID_5d10] = 292,
+ [BNXT_ULP_ACT_HID_5d20] = 293,
+ [BNXT_ULP_ACT_HID_2e18] = 294,
+ [BNXT_ULP_ACT_HID_29d4] = 295,
+ [BNXT_ULP_ACT_HID_7690] = 296,
+ [BNXT_ULP_ACT_HID_47a0] = 297,
+ [BNXT_ULP_ACT_HID_435c] = 298,
+ [BNXT_ULP_ACT_HID_5d18] = 299,
+ [BNXT_ULP_ACT_HID_2e28] = 300,
+ [BNXT_ULP_ACT_HID_29e4] = 301,
+ [BNXT_ULP_ACT_HID_76a0] = 302,
+ [BNXT_ULP_ACT_HID_47b0] = 303,
+ [BNXT_ULP_ACT_HID_436c] = 304,
+ [BNXT_ULP_ACT_HID_1436] = 305,
+ [BNXT_ULP_ACT_HID_143e] = 306,
+ [BNXT_ULP_ACT_HID_144e] = 307,
+ [BNXT_ULP_ACT_HID_6102] = 308,
+ [BNXT_ULP_ACT_HID_5cbe] = 309,
+ [BNXT_ULP_ACT_HID_2dbe] = 310,
+ [BNXT_ULP_ACT_HID_7a8a] = 311,
+ [BNXT_ULP_ACT_HID_7646] = 312,
+ [BNXT_ULP_ACT_HID_1446] = 313,
+ [BNXT_ULP_ACT_HID_6112] = 314,
+ [BNXT_ULP_ACT_HID_5cce] = 315,
+ [BNXT_ULP_ACT_HID_2dce] = 316,
+ [BNXT_ULP_ACT_HID_7a9a] = 317,
+ [BNXT_ULP_ACT_HID_7656] = 318,
+ [BNXT_ULP_ACT_HID_6508] = 319,
+ [BNXT_ULP_ACT_HID_6d08] = 320,
+ [BNXT_ULP_ACT_HID_7508] = 321,
+ [BNXT_ULP_ACT_HID_6518] = 322,
+ [BNXT_ULP_ACT_HID_6d18] = 323,
+ [BNXT_ULP_ACT_HID_7518] = 324,
+ [BNXT_ULP_ACT_HID_6e18] = 325,
+ [BNXT_ULP_ACT_HID_256c] = 326,
+ [BNXT_ULP_ACT_HID_036c] = 327,
+ [BNXT_ULP_ACT_HID_698c] = 328,
+ [BNXT_ULP_ACT_HID_20e0] = 329,
+ [BNXT_ULP_ACT_HID_31f0] = 330,
+ [BNXT_ULP_ACT_HID_7618] = 331,
+ [BNXT_ULP_ACT_HID_2d6c] = 332,
+ [BNXT_ULP_ACT_HID_0b6c] = 333,
+ [BNXT_ULP_ACT_HID_718c] = 334,
+ [BNXT_ULP_ACT_HID_28e0] = 335,
+ [BNXT_ULP_ACT_HID_39f0] = 336,
+ [BNXT_ULP_ACT_HID_025c] = 337,
+ [BNXT_ULP_ACT_HID_356c] = 338,
+ [BNXT_ULP_ACT_HID_136c] = 339,
+ [BNXT_ULP_ACT_HID_798c] = 340,
+ [BNXT_ULP_ACT_HID_30e0] = 341,
+ [BNXT_ULP_ACT_HID_41f0] = 342,
+ [BNXT_ULP_ACT_HID_0a5c] = 343,
+ [BNXT_ULP_ACT_HID_3d6c] = 344,
+ [BNXT_ULP_ACT_HID_1b6c] = 345,
+ [BNXT_ULP_ACT_HID_05d0] = 346,
+ [BNXT_ULP_ACT_HID_38e0] = 347,
+ [BNXT_ULP_ACT_HID_49f0] = 348,
+ [BNXT_ULP_ACT_HID_6e28] = 349,
+ [BNXT_ULP_ACT_HID_257c] = 350,
+ [BNXT_ULP_ACT_HID_037c] = 351,
+ [BNXT_ULP_ACT_HID_699c] = 352,
+ [BNXT_ULP_ACT_HID_20f0] = 353,
+ [BNXT_ULP_ACT_HID_3200] = 354,
+ [BNXT_ULP_ACT_HID_7628] = 355,
+ [BNXT_ULP_ACT_HID_2d7c] = 356,
+ [BNXT_ULP_ACT_HID_0b7c] = 357,
+ [BNXT_ULP_ACT_HID_719c] = 358,
+ [BNXT_ULP_ACT_HID_28f0] = 359,
+ [BNXT_ULP_ACT_HID_3a00] = 360,
+ [BNXT_ULP_ACT_HID_026c] = 361,
+ [BNXT_ULP_ACT_HID_357c] = 362,
+ [BNXT_ULP_ACT_HID_137c] = 363,
+ [BNXT_ULP_ACT_HID_799c] = 364,
+ [BNXT_ULP_ACT_HID_30f0] = 365,
+ [BNXT_ULP_ACT_HID_4200] = 366,
+ [BNXT_ULP_ACT_HID_0a6c] = 367,
+ [BNXT_ULP_ACT_HID_3d7c] = 368,
+ [BNXT_ULP_ACT_HID_1b7c] = 369,
+ [BNXT_ULP_ACT_HID_05e0] = 370,
+ [BNXT_ULP_ACT_HID_38f0] = 371,
+ [BNXT_ULP_ACT_HID_4a00] = 372,
+ [BNXT_ULP_ACT_HID_0be4] = 373,
+ [BNXT_ULP_ACT_HID_3ef4] = 374,
+ [BNXT_ULP_ACT_HID_1cf4] = 375,
+ [BNXT_ULP_ACT_HID_0758] = 376,
+ [BNXT_ULP_ACT_HID_3a68] = 377,
+ [BNXT_ULP_ACT_HID_4b78] = 378,
+ [BNXT_ULP_ACT_HID_0bf4] = 379,
+ [BNXT_ULP_ACT_HID_3f04] = 380,
+ [BNXT_ULP_ACT_HID_1d04] = 381,
+ [BNXT_ULP_ACT_HID_0768] = 382,
+ [BNXT_ULP_ACT_HID_3a78] = 383,
+ [BNXT_ULP_ACT_HID_4b88] = 384,
+ [BNXT_ULP_ACT_HID_46f4] = 385,
+ [BNXT_ULP_ACT_HID_24f4] = 386,
+ [BNXT_ULP_ACT_HID_0f58] = 387,
+ [BNXT_ULP_ACT_HID_13e4] = 388,
+ [BNXT_ULP_ACT_HID_4268] = 389,
+ [BNXT_ULP_ACT_HID_5378] = 390,
+ [BNXT_ULP_ACT_HID_13f4] = 391,
+ [BNXT_ULP_ACT_HID_4704] = 392,
+ [BNXT_ULP_ACT_HID_2504] = 393,
+ [BNXT_ULP_ACT_HID_0f68] = 394,
+ [BNXT_ULP_ACT_HID_4278] = 395,
+ [BNXT_ULP_ACT_HID_5388] = 396,
+ [BNXT_ULP_ACT_HID_1be4] = 397,
+ [BNXT_ULP_ACT_HID_4ef4] = 398,
+ [BNXT_ULP_ACT_HID_2cf4] = 399,
+ [BNXT_ULP_ACT_HID_1758] = 400,
+ [BNXT_ULP_ACT_HID_4a68] = 401,
+ [BNXT_ULP_ACT_HID_5b78] = 402,
+ [BNXT_ULP_ACT_HID_1bf4] = 403,
+ [BNXT_ULP_ACT_HID_4f04] = 404,
+ [BNXT_ULP_ACT_HID_2d04] = 405,
+ [BNXT_ULP_ACT_HID_1768] = 406,
+ [BNXT_ULP_ACT_HID_4a78] = 407,
+ [BNXT_ULP_ACT_HID_5b88] = 408,
+ [BNXT_ULP_ACT_HID_23e4] = 409,
+ [BNXT_ULP_ACT_HID_56f4] = 410,
+ [BNXT_ULP_ACT_HID_34f4] = 411,
+ [BNXT_ULP_ACT_HID_1f58] = 412,
+ [BNXT_ULP_ACT_HID_5268] = 413,
+ [BNXT_ULP_ACT_HID_6378] = 414,
+ [BNXT_ULP_ACT_HID_23f4] = 415,
+ [BNXT_ULP_ACT_HID_5704] = 416,
+ [BNXT_ULP_ACT_HID_3504] = 417,
+ [BNXT_ULP_ACT_HID_1f68] = 418,
+ [BNXT_ULP_ACT_HID_5278] = 419,
+ [BNXT_ULP_ACT_HID_6388] = 420,
+ [BNXT_ULP_ACT_HID_1c36] = 421,
+ [BNXT_ULP_ACT_HID_2436] = 422,
+ [BNXT_ULP_ACT_HID_2c36] = 423,
+ [BNXT_ULP_ACT_HID_1c46] = 424,
+ [BNXT_ULP_ACT_HID_2446] = 425,
+ [BNXT_ULP_ACT_HID_2c46] = 426,
+ [BNXT_ULP_ACT_HID_2546] = 427,
+ [BNXT_ULP_ACT_HID_5856] = 428,
+ [BNXT_ULP_ACT_HID_3656] = 429,
+ [BNXT_ULP_ACT_HID_20ba] = 430,
+ [BNXT_ULP_ACT_HID_53ca] = 431,
+ [BNXT_ULP_ACT_HID_64da] = 432,
+ [BNXT_ULP_ACT_HID_2d46] = 433,
+ [BNXT_ULP_ACT_HID_6056] = 434,
+ [BNXT_ULP_ACT_HID_3e56] = 435,
+ [BNXT_ULP_ACT_HID_28ba] = 436,
+ [BNXT_ULP_ACT_HID_5bca] = 437,
+ [BNXT_ULP_ACT_HID_6cda] = 438,
+ [BNXT_ULP_ACT_HID_3546] = 439,
+ [BNXT_ULP_ACT_HID_6856] = 440,
+ [BNXT_ULP_ACT_HID_4656] = 441,
+ [BNXT_ULP_ACT_HID_30ba] = 442,
+ [BNXT_ULP_ACT_HID_63ca] = 443,
+ [BNXT_ULP_ACT_HID_74da] = 444,
+ [BNXT_ULP_ACT_HID_3d46] = 445,
+ [BNXT_ULP_ACT_HID_7056] = 446,
+ [BNXT_ULP_ACT_HID_4e56] = 447,
+ [BNXT_ULP_ACT_HID_38ba] = 448,
+ [BNXT_ULP_ACT_HID_6bca] = 449,
+ [BNXT_ULP_ACT_HID_011e] = 450,
+ [BNXT_ULP_ACT_HID_2556] = 451,
+ [BNXT_ULP_ACT_HID_5866] = 452,
+ [BNXT_ULP_ACT_HID_3666] = 453,
+ [BNXT_ULP_ACT_HID_20ca] = 454,
+ [BNXT_ULP_ACT_HID_53da] = 455,
+ [BNXT_ULP_ACT_HID_64ea] = 456,
+ [BNXT_ULP_ACT_HID_2d56] = 457,
+ [BNXT_ULP_ACT_HID_6066] = 458,
+ [BNXT_ULP_ACT_HID_3e66] = 459,
+ [BNXT_ULP_ACT_HID_28ca] = 460,
+ [BNXT_ULP_ACT_HID_5bda] = 461,
+ [BNXT_ULP_ACT_HID_6cea] = 462,
+ [BNXT_ULP_ACT_HID_3556] = 463,
+ [BNXT_ULP_ACT_HID_6866] = 464,
+ [BNXT_ULP_ACT_HID_4666] = 465,
+ [BNXT_ULP_ACT_HID_30ca] = 466,
+ [BNXT_ULP_ACT_HID_63da] = 467,
+ [BNXT_ULP_ACT_HID_74ea] = 468,
+ [BNXT_ULP_ACT_HID_3d56] = 469,
+ [BNXT_ULP_ACT_HID_7066] = 470,
+ [BNXT_ULP_ACT_HID_4e66] = 471,
+ [BNXT_ULP_ACT_HID_38ca] = 472,
+ [BNXT_ULP_ACT_HID_6bda] = 473,
+ [BNXT_ULP_ACT_HID_012e] = 474,
+ [BNXT_ULP_ACT_HID_3ece] = 475,
+ [BNXT_ULP_ACT_HID_71de] = 476,
+ [BNXT_ULP_ACT_HID_4fde] = 477,
+ [BNXT_ULP_ACT_HID_3a42] = 478,
+ [BNXT_ULP_ACT_HID_6d52] = 479,
+ [BNXT_ULP_ACT_HID_02a6] = 480,
+ [BNXT_ULP_ACT_HID_3ede] = 481,
+ [BNXT_ULP_ACT_HID_71ee] = 482,
+ [BNXT_ULP_ACT_HID_4fee] = 483,
+ [BNXT_ULP_ACT_HID_3a52] = 484,
+ [BNXT_ULP_ACT_HID_6d62] = 485,
+ [BNXT_ULP_ACT_HID_02b6] = 486,
+ [BNXT_ULP_ACT_HID_79de] = 487,
+ [BNXT_ULP_ACT_HID_57de] = 488,
+ [BNXT_ULP_ACT_HID_4242] = 489,
+ [BNXT_ULP_ACT_HID_46ce] = 490,
+ [BNXT_ULP_ACT_HID_7552] = 491,
+ [BNXT_ULP_ACT_HID_0aa6] = 492,
+ [BNXT_ULP_ACT_HID_46de] = 493,
+ [BNXT_ULP_ACT_HID_79ee] = 494,
+ [BNXT_ULP_ACT_HID_57ee] = 495,
+ [BNXT_ULP_ACT_HID_4252] = 496,
+ [BNXT_ULP_ACT_HID_7562] = 497,
+ [BNXT_ULP_ACT_HID_0ab6] = 498,
+ [BNXT_ULP_ACT_HID_4ece] = 499,
+ [BNXT_ULP_ACT_HID_0622] = 500,
+ [BNXT_ULP_ACT_HID_5fde] = 501,
+ [BNXT_ULP_ACT_HID_4a42] = 502,
+ [BNXT_ULP_ACT_HID_0196] = 503,
+ [BNXT_ULP_ACT_HID_12a6] = 504,
+ [BNXT_ULP_ACT_HID_4ede] = 505,
+ [BNXT_ULP_ACT_HID_0632] = 506,
+ [BNXT_ULP_ACT_HID_5fee] = 507,
+ [BNXT_ULP_ACT_HID_4a52] = 508,
+ [BNXT_ULP_ACT_HID_01a6] = 509,
+ [BNXT_ULP_ACT_HID_12b6] = 510,
+ [BNXT_ULP_ACT_HID_56ce] = 511,
+ [BNXT_ULP_ACT_HID_0e22] = 512,
+ [BNXT_ULP_ACT_HID_67de] = 513,
+ [BNXT_ULP_ACT_HID_5242] = 514,
+ [BNXT_ULP_ACT_HID_0996] = 515,
+ [BNXT_ULP_ACT_HID_1aa6] = 516,
+ [BNXT_ULP_ACT_HID_56de] = 517,
+ [BNXT_ULP_ACT_HID_0e32] = 518,
+ [BNXT_ULP_ACT_HID_67ee] = 519,
+ [BNXT_ULP_ACT_HID_5252] = 520,
+ [BNXT_ULP_ACT_HID_09a6] = 521,
+ [BNXT_ULP_ACT_HID_1ab6] = 522,
+ [BNXT_ULP_ACT_HID_31d0] = 523,
+ [BNXT_ULP_ACT_HID_31e0] = 524,
+ [BNXT_ULP_ACT_HID_39d0] = 525,
+ [BNXT_ULP_ACT_HID_39e0] = 526,
+ [BNXT_ULP_ACT_HID_41d0] = 527,
+ [BNXT_ULP_ACT_HID_41e0] = 528,
+ [BNXT_ULP_ACT_HID_49d0] = 529,
+ [BNXT_ULP_ACT_HID_49e0] = 530,
+ [BNXT_ULP_ACT_HID_64ba] = 531,
+ [BNXT_ULP_ACT_HID_64ca] = 532,
+ [BNXT_ULP_ACT_HID_6cba] = 533,
+ [BNXT_ULP_ACT_HID_6cca] = 534,
+ [BNXT_ULP_ACT_HID_74ba] = 535,
+ [BNXT_ULP_ACT_HID_74ca] = 536,
+ [BNXT_ULP_ACT_HID_00fe] = 537,
+ [BNXT_ULP_ACT_HID_010e] = 538,
+ [BNXT_ULP_ACT_HID_331c] = 539,
+ [BNXT_ULP_ACT_HID_332c] = 540,
+ [BNXT_ULP_ACT_HID_6706] = 541,
+ [BNXT_ULP_ACT_HID_6716] = 542,
+ [BNXT_ULP_ACT_HID_1b6d] = 543,
+ [BNXT_ULP_ACT_HID_1b7d] = 544,
+ [BNXT_ULP_ACT_HID_641a] = 545
};
/* Array for the act matcher list */
@@ -121,7 +571,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[2] = {
- .act_hid = BNXT_ULP_ACT_HID_0001,
+ .act_hid = BNXT_ULP_ACT_HID_0008,
.act_pattern_id = 1,
.app_sig = 0,
.act_sig = { .bits =
@@ -130,7 +580,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[3] = {
- .act_hid = BNXT_ULP_ACT_HID_0400,
+ .act_hid = BNXT_ULP_ACT_HID_2000,
.act_pattern_id = 2,
.app_sig = 0,
.act_sig = { .bits =
@@ -139,7 +589,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[4] = {
- .act_hid = BNXT_ULP_ACT_HID_01ab,
+ .act_hid = BNXT_ULP_ACT_HID_1988,
.act_pattern_id = 3,
.app_sig = 0,
.act_sig = { .bits =
@@ -148,7 +598,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[5] = {
- .act_hid = BNXT_ULP_ACT_HID_0010,
+ .act_hid = BNXT_ULP_ACT_HID_0080,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
@@ -157,7 +607,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[6] = {
- .act_hid = BNXT_ULP_ACT_HID_05ab,
+ .act_hid = BNXT_ULP_ACT_HID_3988,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
@@ -167,7 +617,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[7] = {
- .act_hid = BNXT_ULP_ACT_HID_01bb,
+ .act_hid = BNXT_ULP_ACT_HID_1a08,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
@@ -177,7 +627,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[8] = {
- .act_hid = BNXT_ULP_ACT_HID_0002,
+ .act_hid = BNXT_ULP_ACT_HID_0010,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
@@ -186,902 +636,6269 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 1
},
[9] = {
- .act_hid = BNXT_ULP_ACT_HID_0003,
+ .act_hid = BNXT_ULP_ACT_HID_0040,
.act_pattern_id = 8,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_METER |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[10] = {
- .act_hid = BNXT_ULP_ACT_HID_0402,
+ .act_hid = BNXT_ULP_ACT_HID_0050,
.act_pattern_id = 9,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_METER |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[11] = {
- .act_hid = BNXT_ULP_ACT_HID_01ad,
+ .act_hid = BNXT_ULP_ACT_HID_0018,
.act_pattern_id = 10,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[12] = {
- .act_hid = BNXT_ULP_ACT_HID_0012,
+ .act_hid = BNXT_ULP_ACT_HID_2010,
.act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[13] = {
- .act_hid = BNXT_ULP_ACT_HID_05ad,
+ .act_hid = BNXT_ULP_ACT_HID_1998,
.act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[14] = {
- .act_hid = BNXT_ULP_ACT_HID_01bd,
+ .act_hid = BNXT_ULP_ACT_HID_0090,
.act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_VXLAN_DECAP |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[15] = {
- .act_hid = BNXT_ULP_ACT_HID_0613,
+ .act_hid = BNXT_ULP_ACT_HID_3998,
.act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[16] = {
- .act_hid = BNXT_ULP_ACT_HID_02a9,
+ .act_hid = BNXT_ULP_ACT_HID_1a18,
.act_pattern_id = 15,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[17] = {
- .act_hid = BNXT_ULP_ACT_HID_0054,
+ .act_hid = BNXT_ULP_ACT_HID_32ea,
.act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[18] = {
- .act_hid = BNXT_ULP_ACT_HID_0622,
+ .act_hid = BNXT_ULP_ACT_HID_32f2,
.act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[19] = {
- .act_hid = BNXT_ULP_ACT_HID_0454,
+ .act_hid = BNXT_ULP_ACT_HID_52ea,
.act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[20] = {
- .act_hid = BNXT_ULP_ACT_HID_0064,
+ .act_hid = BNXT_ULP_ACT_HID_4c72,
.act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[21] = {
- .act_hid = BNXT_ULP_ACT_HID_0614,
+ .act_hid = BNXT_ULP_ACT_HID_336a,
.act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[22] = {
- .act_hid = BNXT_ULP_ACT_HID_0615,
+ .act_hid = BNXT_ULP_ACT_HID_6c72,
.act_pattern_id = 21,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[23] = {
- .act_hid = BNXT_ULP_ACT_HID_02ab,
+ .act_hid = BNXT_ULP_ACT_HID_4cf2,
.act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_POP_VLAN |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[24] = {
- .act_hid = BNXT_ULP_ACT_HID_0056,
+ .act_hid = BNXT_ULP_ACT_HID_32fa,
.act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[25] = {
- .act_hid = BNXT_ULP_ACT_HID_0624,
+ .act_hid = BNXT_ULP_ACT_HID_3302,
.act_pattern_id = 24,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[26] = {
- .act_hid = BNXT_ULP_ACT_HID_0456,
+ .act_hid = BNXT_ULP_ACT_HID_52fa,
.act_pattern_id = 25,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[27] = {
- .act_hid = BNXT_ULP_ACT_HID_0066,
+ .act_hid = BNXT_ULP_ACT_HID_4c82,
.act_pattern_id = 26,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
[28] = {
- .act_hid = BNXT_ULP_ACT_HID_048d,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_337a,
+ .act_pattern_id = 27,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED |
- BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 2
+ .act_tid = 1
},
[29] = {
- .act_hid = BNXT_ULP_ACT_HID_048f,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_6c82,
+ .act_pattern_id = 28,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SHARED |
- BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_POP_VLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 2
+ .act_tid = 1
},
[30] = {
- .act_hid = BNXT_ULP_ACT_HID_04bc,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_4d02,
+ .act_pattern_id = 29,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[31] = {
- .act_hid = BNXT_ULP_ACT_HID_00a9,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_0808,
+ .act_pattern_id = 30,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[32] = {
- .act_hid = BNXT_ULP_ACT_HID_020f,
- .act_pattern_id = 2,
+ .act_hid = BNXT_ULP_ACT_HID_1008,
+ .act_pattern_id = 31,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[33] = {
- .act_hid = BNXT_ULP_ACT_HID_0153,
- .act_pattern_id = 3,
+ .act_hid = BNXT_ULP_ACT_HID_1808,
+ .act_pattern_id = 32,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[34] = {
- .act_hid = BNXT_ULP_ACT_HID_04a9,
- .act_pattern_id = 4,
+ .act_hid = BNXT_ULP_ACT_HID_0818,
+ .act_pattern_id = 33,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[35] = {
- .act_hid = BNXT_ULP_ACT_HID_01fc,
- .act_pattern_id = 5,
+ .act_hid = BNXT_ULP_ACT_HID_1018,
+ .act_pattern_id = 34,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[36] = {
- .act_hid = BNXT_ULP_ACT_HID_04be,
- .act_pattern_id = 6,
+ .act_hid = BNXT_ULP_ACT_HID_1818,
+ .act_pattern_id = 35,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[37] = {
- .act_hid = BNXT_ULP_ACT_HID_00ab,
- .act_pattern_id = 7,
+ .act_hid = BNXT_ULP_ACT_HID_0880,
+ .act_pattern_id = 36,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[38] = {
- .act_hid = BNXT_ULP_ACT_HID_0211,
- .act_pattern_id = 8,
+ .act_hid = BNXT_ULP_ACT_HID_1080,
+ .act_pattern_id = 37,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[39] = {
- .act_hid = BNXT_ULP_ACT_HID_0155,
- .act_pattern_id = 9,
+ .act_hid = BNXT_ULP_ACT_HID_1880,
+ .act_pattern_id = 38,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[40] = {
- .act_hid = BNXT_ULP_ACT_HID_04ab,
- .act_pattern_id = 10,
+ .act_hid = BNXT_ULP_ACT_HID_0890,
+ .act_pattern_id = 39,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[41] = {
- .act_hid = BNXT_ULP_ACT_HID_01fe,
- .act_pattern_id = 11,
+ .act_hid = BNXT_ULP_ACT_HID_1090,
+ .act_pattern_id = 40,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[42] = {
- .act_hid = BNXT_ULP_ACT_HID_0667,
- .act_pattern_id = 12,
+ .act_hid = BNXT_ULP_ACT_HID_1890,
+ .act_pattern_id = 41,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[43] = {
- .act_hid = BNXT_ULP_ACT_HID_0254,
- .act_pattern_id = 13,
+ .act_hid = BNXT_ULP_ACT_HID_3af2,
+ .act_pattern_id = 42,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[44] = {
- .act_hid = BNXT_ULP_ACT_HID_03ba,
- .act_pattern_id = 14,
+ .act_hid = BNXT_ULP_ACT_HID_42f2,
+ .act_pattern_id = 43,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[45] = {
- .act_hid = BNXT_ULP_ACT_HID_02fe,
- .act_pattern_id = 15,
+ .act_hid = BNXT_ULP_ACT_HID_4af2,
+ .act_pattern_id = 44,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[46] = {
- .act_hid = BNXT_ULP_ACT_HID_0654,
- .act_pattern_id = 16,
+ .act_hid = BNXT_ULP_ACT_HID_3b02,
+ .act_pattern_id = 45,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[47] = {
- .act_hid = BNXT_ULP_ACT_HID_03a7,
- .act_pattern_id = 17,
+ .act_hid = BNXT_ULP_ACT_HID_4302,
+ .act_pattern_id = 46,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[48] = {
- .act_hid = BNXT_ULP_ACT_HID_0669,
- .act_pattern_id = 18,
+ .act_hid = BNXT_ULP_ACT_HID_4b02,
+ .act_pattern_id = 47,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[49] = {
- .act_hid = BNXT_ULP_ACT_HID_0256,
- .act_pattern_id = 19,
+ .act_hid = BNXT_ULP_ACT_HID_3b6a,
+ .act_pattern_id = 48,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[50] = {
- .act_hid = BNXT_ULP_ACT_HID_03bc,
- .act_pattern_id = 20,
+ .act_hid = BNXT_ULP_ACT_HID_436a,
+ .act_pattern_id = 49,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[51] = {
- .act_hid = BNXT_ULP_ACT_HID_0300,
- .act_pattern_id = 21,
+ .act_hid = BNXT_ULP_ACT_HID_4b6a,
+ .act_pattern_id = 50,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[52] = {
- .act_hid = BNXT_ULP_ACT_HID_0656,
- .act_pattern_id = 22,
+ .act_hid = BNXT_ULP_ACT_HID_3b7a,
+ .act_pattern_id = 51,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[53] = {
- .act_hid = BNXT_ULP_ACT_HID_03a9,
- .act_pattern_id = 23,
+ .act_hid = BNXT_ULP_ACT_HID_437a,
+ .act_pattern_id = 52,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 3
+ .act_tid = 1
},
[54] = {
- .act_hid = BNXT_ULP_ACT_HID_021b,
- .act_pattern_id = 0,
+ .act_hid = BNXT_ULP_ACT_HID_4b7a,
+ .act_pattern_id = 53,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
},
[55] = {
- .act_hid = BNXT_ULP_ACT_HID_021c,
- .act_pattern_id = 1,
+ .act_hid = BNXT_ULP_ACT_HID_640d,
+ .act_pattern_id = 0,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DROP |
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [56] = {
+ .act_hid = BNXT_ULP_ACT_HID_641d,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [57] = {
+ .act_hid = BNXT_ULP_ACT_HID_071a,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [58] = {
+ .act_hid = BNXT_ULP_ACT_HID_0800,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [59] = {
+ .act_hid = BNXT_ULP_ACT_HID_1000,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [60] = {
+ .act_hid = BNXT_ULP_ACT_HID_1800,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [61] = {
+ .act_hid = BNXT_ULP_ACT_HID_0810,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [62] = {
+ .act_hid = BNXT_ULP_ACT_HID_1010,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [63] = {
+ .act_hid = BNXT_ULP_ACT_HID_1810,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [64] = {
+ .act_hid = BNXT_ULP_ACT_HID_1110,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [65] = {
+ .act_hid = BNXT_ULP_ACT_HID_4420,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [66] = {
+ .act_hid = BNXT_ULP_ACT_HID_2220,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [67] = {
+ .act_hid = BNXT_ULP_ACT_HID_0c84,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [68] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f94,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [69] = {
+ .act_hid = BNXT_ULP_ACT_HID_3330,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [70] = {
+ .act_hid = BNXT_ULP_ACT_HID_50a4,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [71] = {
+ .act_hid = BNXT_ULP_ACT_HID_1910,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [72] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c20,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [73] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a20,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [74] = {
+ .act_hid = BNXT_ULP_ACT_HID_1484,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [75] = {
+ .act_hid = BNXT_ULP_ACT_HID_4794,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [76] = {
+ .act_hid = BNXT_ULP_ACT_HID_3b30,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [77] = {
+ .act_hid = BNXT_ULP_ACT_HID_58a4,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [78] = {
+ .act_hid = BNXT_ULP_ACT_HID_2110,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [79] = {
+ .act_hid = BNXT_ULP_ACT_HID_5420,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [80] = {
+ .act_hid = BNXT_ULP_ACT_HID_3220,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [81] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c84,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [82] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f94,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [83] = {
+ .act_hid = BNXT_ULP_ACT_HID_4330,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [84] = {
+ .act_hid = BNXT_ULP_ACT_HID_60a4,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [85] = {
+ .act_hid = BNXT_ULP_ACT_HID_2910,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [86] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c20,
+ .act_pattern_id = 28,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [87] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a20,
+ .act_pattern_id = 29,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [88] = {
+ .act_hid = BNXT_ULP_ACT_HID_2484,
+ .act_pattern_id = 30,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [89] = {
+ .act_hid = BNXT_ULP_ACT_HID_5794,
+ .act_pattern_id = 31,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [90] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b30,
+ .act_pattern_id = 32,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [91] = {
+ .act_hid = BNXT_ULP_ACT_HID_68a4,
+ .act_pattern_id = 33,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [92] = {
+ .act_hid = BNXT_ULP_ACT_HID_1120,
+ .act_pattern_id = 34,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [93] = {
+ .act_hid = BNXT_ULP_ACT_HID_4430,
+ .act_pattern_id = 35,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [94] = {
+ .act_hid = BNXT_ULP_ACT_HID_2230,
+ .act_pattern_id = 36,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [95] = {
+ .act_hid = BNXT_ULP_ACT_HID_0c94,
+ .act_pattern_id = 37,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [96] = {
+ .act_hid = BNXT_ULP_ACT_HID_3fa4,
+ .act_pattern_id = 38,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [97] = {
+ .act_hid = BNXT_ULP_ACT_HID_3340,
+ .act_pattern_id = 39,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [98] = {
+ .act_hid = BNXT_ULP_ACT_HID_50b4,
+ .act_pattern_id = 40,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [99] = {
+ .act_hid = BNXT_ULP_ACT_HID_1920,
+ .act_pattern_id = 41,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [100] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c30,
+ .act_pattern_id = 42,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [101] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a30,
+ .act_pattern_id = 43,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [102] = {
+ .act_hid = BNXT_ULP_ACT_HID_1494,
+ .act_pattern_id = 44,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [103] = {
+ .act_hid = BNXT_ULP_ACT_HID_47a4,
+ .act_pattern_id = 45,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [104] = {
+ .act_hid = BNXT_ULP_ACT_HID_3b40,
+ .act_pattern_id = 46,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [105] = {
+ .act_hid = BNXT_ULP_ACT_HID_58b4,
+ .act_pattern_id = 47,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [106] = {
+ .act_hid = BNXT_ULP_ACT_HID_2120,
+ .act_pattern_id = 48,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [107] = {
+ .act_hid = BNXT_ULP_ACT_HID_5430,
+ .act_pattern_id = 49,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [108] = {
+ .act_hid = BNXT_ULP_ACT_HID_3230,
+ .act_pattern_id = 50,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [109] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c94,
+ .act_pattern_id = 51,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [110] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fa4,
+ .act_pattern_id = 52,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [111] = {
+ .act_hid = BNXT_ULP_ACT_HID_4340,
+ .act_pattern_id = 53,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [112] = {
+ .act_hid = BNXT_ULP_ACT_HID_60b4,
+ .act_pattern_id = 54,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [113] = {
+ .act_hid = BNXT_ULP_ACT_HID_2920,
+ .act_pattern_id = 55,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [114] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c30,
+ .act_pattern_id = 56,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [115] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a30,
+ .act_pattern_id = 57,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [116] = {
+ .act_hid = BNXT_ULP_ACT_HID_2494,
+ .act_pattern_id = 58,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [117] = {
+ .act_hid = BNXT_ULP_ACT_HID_57a4,
+ .act_pattern_id = 59,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [118] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b40,
+ .act_pattern_id = 60,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [119] = {
+ .act_hid = BNXT_ULP_ACT_HID_68b4,
+ .act_pattern_id = 61,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [120] = {
+ .act_hid = BNXT_ULP_ACT_HID_2a98,
+ .act_pattern_id = 62,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [121] = {
+ .act_hid = BNXT_ULP_ACT_HID_5da8,
+ .act_pattern_id = 63,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [122] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ba8,
+ .act_pattern_id = 64,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [123] = {
+ .act_hid = BNXT_ULP_ACT_HID_260c,
+ .act_pattern_id = 65,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [124] = {
+ .act_hid = BNXT_ULP_ACT_HID_591c,
+ .act_pattern_id = 66,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [125] = {
+ .act_hid = BNXT_ULP_ACT_HID_6a2c,
+ .act_pattern_id = 67,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [126] = {
+ .act_hid = BNXT_ULP_ACT_HID_2aa8,
+ .act_pattern_id = 68,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [127] = {
+ .act_hid = BNXT_ULP_ACT_HID_5db8,
+ .act_pattern_id = 69,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [128] = {
+ .act_hid = BNXT_ULP_ACT_HID_3bb8,
+ .act_pattern_id = 70,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [129] = {
+ .act_hid = BNXT_ULP_ACT_HID_261c,
+ .act_pattern_id = 71,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [130] = {
+ .act_hid = BNXT_ULP_ACT_HID_592c,
+ .act_pattern_id = 72,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [131] = {
+ .act_hid = BNXT_ULP_ACT_HID_6a3c,
+ .act_pattern_id = 73,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [132] = {
+ .act_hid = BNXT_ULP_ACT_HID_3298,
+ .act_pattern_id = 74,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [133] = {
+ .act_hid = BNXT_ULP_ACT_HID_65a8,
+ .act_pattern_id = 75,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [134] = {
+ .act_hid = BNXT_ULP_ACT_HID_43a8,
+ .act_pattern_id = 76,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [135] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e0c,
+ .act_pattern_id = 77,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [136] = {
+ .act_hid = BNXT_ULP_ACT_HID_611c,
+ .act_pattern_id = 78,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [137] = {
+ .act_hid = BNXT_ULP_ACT_HID_722c,
+ .act_pattern_id = 79,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [138] = {
+ .act_hid = BNXT_ULP_ACT_HID_32a8,
+ .act_pattern_id = 80,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [139] = {
+ .act_hid = BNXT_ULP_ACT_HID_65b8,
+ .act_pattern_id = 81,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [140] = {
+ .act_hid = BNXT_ULP_ACT_HID_43b8,
+ .act_pattern_id = 82,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [141] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e1c,
+ .act_pattern_id = 83,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [142] = {
+ .act_hid = BNXT_ULP_ACT_HID_612c,
+ .act_pattern_id = 84,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [143] = {
+ .act_hid = BNXT_ULP_ACT_HID_723c,
+ .act_pattern_id = 85,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [144] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a98,
+ .act_pattern_id = 86,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [145] = {
+ .act_hid = BNXT_ULP_ACT_HID_6da8,
+ .act_pattern_id = 87,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [146] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ba8,
+ .act_pattern_id = 88,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [147] = {
+ .act_hid = BNXT_ULP_ACT_HID_360c,
+ .act_pattern_id = 89,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [148] = {
+ .act_hid = BNXT_ULP_ACT_HID_691c,
+ .act_pattern_id = 90,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [149] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a2c,
+ .act_pattern_id = 91,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [150] = {
+ .act_hid = BNXT_ULP_ACT_HID_3aa8,
+ .act_pattern_id = 92,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [151] = {
+ .act_hid = BNXT_ULP_ACT_HID_6db8,
+ .act_pattern_id = 93,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [152] = {
+ .act_hid = BNXT_ULP_ACT_HID_4bb8,
+ .act_pattern_id = 94,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [153] = {
+ .act_hid = BNXT_ULP_ACT_HID_361c,
+ .act_pattern_id = 95,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [154] = {
+ .act_hid = BNXT_ULP_ACT_HID_692c,
+ .act_pattern_id = 96,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [155] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a3c,
+ .act_pattern_id = 97,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [156] = {
+ .act_hid = BNXT_ULP_ACT_HID_4298,
+ .act_pattern_id = 98,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [157] = {
+ .act_hid = BNXT_ULP_ACT_HID_75a8,
+ .act_pattern_id = 99,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [158] = {
+ .act_hid = BNXT_ULP_ACT_HID_53a8,
+ .act_pattern_id = 100,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [159] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e0c,
+ .act_pattern_id = 101,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [160] = {
+ .act_hid = BNXT_ULP_ACT_HID_711c,
+ .act_pattern_id = 102,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [161] = {
+ .act_hid = BNXT_ULP_ACT_HID_0670,
+ .act_pattern_id = 103,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [162] = {
+ .act_hid = BNXT_ULP_ACT_HID_42a8,
+ .act_pattern_id = 104,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [163] = {
+ .act_hid = BNXT_ULP_ACT_HID_75b8,
+ .act_pattern_id = 105,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [164] = {
+ .act_hid = BNXT_ULP_ACT_HID_53b8,
+ .act_pattern_id = 106,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [165] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e1c,
+ .act_pattern_id = 107,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [166] = {
+ .act_hid = BNXT_ULP_ACT_HID_712c,
+ .act_pattern_id = 108,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [167] = {
+ .act_hid = BNXT_ULP_ACT_HID_0680,
+ .act_pattern_id = 109,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [168] = {
+ .act_hid = BNXT_ULP_ACT_HID_3aea,
+ .act_pattern_id = 110,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [169] = {
+ .act_hid = BNXT_ULP_ACT_HID_42ea,
+ .act_pattern_id = 111,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [170] = {
+ .act_hid = BNXT_ULP_ACT_HID_4aea,
+ .act_pattern_id = 112,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [171] = {
+ .act_hid = BNXT_ULP_ACT_HID_3afa,
+ .act_pattern_id = 113,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [172] = {
+ .act_hid = BNXT_ULP_ACT_HID_42fa,
+ .act_pattern_id = 114,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [173] = {
+ .act_hid = BNXT_ULP_ACT_HID_4afa,
+ .act_pattern_id = 115,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [174] = {
+ .act_hid = BNXT_ULP_ACT_HID_43fa,
+ .act_pattern_id = 116,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [175] = {
+ .act_hid = BNXT_ULP_ACT_HID_770a,
+ .act_pattern_id = 117,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [176] = {
+ .act_hid = BNXT_ULP_ACT_HID_550a,
+ .act_pattern_id = 118,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [177] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f6e,
+ .act_pattern_id = 119,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [178] = {
+ .act_hid = BNXT_ULP_ACT_HID_727e,
+ .act_pattern_id = 120,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [179] = {
+ .act_hid = BNXT_ULP_ACT_HID_661a,
+ .act_pattern_id = 121,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [180] = {
+ .act_hid = BNXT_ULP_ACT_HID_07d2,
+ .act_pattern_id = 122,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [181] = {
+ .act_hid = BNXT_ULP_ACT_HID_4bfa,
+ .act_pattern_id = 123,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [182] = {
+ .act_hid = BNXT_ULP_ACT_HID_034e,
+ .act_pattern_id = 124,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [183] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d0a,
+ .act_pattern_id = 125,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [184] = {
+ .act_hid = BNXT_ULP_ACT_HID_476e,
+ .act_pattern_id = 126,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [185] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a7e,
+ .act_pattern_id = 127,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [186] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e1a,
+ .act_pattern_id = 128,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [187] = {
+ .act_hid = BNXT_ULP_ACT_HID_0fd2,
+ .act_pattern_id = 129,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [188] = {
+ .act_hid = BNXT_ULP_ACT_HID_53fa,
+ .act_pattern_id = 130,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [189] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b4e,
+ .act_pattern_id = 131,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [190] = {
+ .act_hid = BNXT_ULP_ACT_HID_650a,
+ .act_pattern_id = 132,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [191] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f6e,
+ .act_pattern_id = 133,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [192] = {
+ .act_hid = BNXT_ULP_ACT_HID_06c2,
+ .act_pattern_id = 134,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [193] = {
+ .act_hid = BNXT_ULP_ACT_HID_761a,
+ .act_pattern_id = 135,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [194] = {
+ .act_hid = BNXT_ULP_ACT_HID_17d2,
+ .act_pattern_id = 136,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [195] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bfa,
+ .act_pattern_id = 137,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [196] = {
+ .act_hid = BNXT_ULP_ACT_HID_134e,
+ .act_pattern_id = 138,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [197] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d0a,
+ .act_pattern_id = 139,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [198] = {
+ .act_hid = BNXT_ULP_ACT_HID_576e,
+ .act_pattern_id = 140,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [199] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ec2,
+ .act_pattern_id = 141,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [200] = {
+ .act_hid = BNXT_ULP_ACT_HID_025e,
+ .act_pattern_id = 142,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [201] = {
+ .act_hid = BNXT_ULP_ACT_HID_1fd2,
+ .act_pattern_id = 143,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [202] = {
+ .act_hid = BNXT_ULP_ACT_HID_440a,
+ .act_pattern_id = 144,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [203] = {
+ .act_hid = BNXT_ULP_ACT_HID_771a,
+ .act_pattern_id = 145,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [204] = {
+ .act_hid = BNXT_ULP_ACT_HID_551a,
+ .act_pattern_id = 146,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [205] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f7e,
+ .act_pattern_id = 147,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [206] = {
+ .act_hid = BNXT_ULP_ACT_HID_728e,
+ .act_pattern_id = 148,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [207] = {
+ .act_hid = BNXT_ULP_ACT_HID_662a,
+ .act_pattern_id = 149,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [208] = {
+ .act_hid = BNXT_ULP_ACT_HID_07e2,
+ .act_pattern_id = 150,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [209] = {
+ .act_hid = BNXT_ULP_ACT_HID_4c0a,
+ .act_pattern_id = 151,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [210] = {
+ .act_hid = BNXT_ULP_ACT_HID_035e,
+ .act_pattern_id = 152,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [211] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d1a,
+ .act_pattern_id = 153,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [212] = {
+ .act_hid = BNXT_ULP_ACT_HID_477e,
+ .act_pattern_id = 154,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [213] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a8e,
+ .act_pattern_id = 155,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [214] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e2a,
+ .act_pattern_id = 156,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [215] = {
+ .act_hid = BNXT_ULP_ACT_HID_0fe2,
+ .act_pattern_id = 157,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [216] = {
+ .act_hid = BNXT_ULP_ACT_HID_540a,
+ .act_pattern_id = 158,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [217] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b5e,
+ .act_pattern_id = 159,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [218] = {
+ .act_hid = BNXT_ULP_ACT_HID_651a,
+ .act_pattern_id = 160,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [219] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f7e,
+ .act_pattern_id = 161,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [220] = {
+ .act_hid = BNXT_ULP_ACT_HID_06d2,
+ .act_pattern_id = 162,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [221] = {
+ .act_hid = BNXT_ULP_ACT_HID_762a,
+ .act_pattern_id = 163,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [222] = {
+ .act_hid = BNXT_ULP_ACT_HID_17e2,
+ .act_pattern_id = 164,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [223] = {
+ .act_hid = BNXT_ULP_ACT_HID_5c0a,
+ .act_pattern_id = 165,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [224] = {
+ .act_hid = BNXT_ULP_ACT_HID_135e,
+ .act_pattern_id = 166,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [225] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d1a,
+ .act_pattern_id = 167,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [226] = {
+ .act_hid = BNXT_ULP_ACT_HID_577e,
+ .act_pattern_id = 168,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [227] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ed2,
+ .act_pattern_id = 169,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [228] = {
+ .act_hid = BNXT_ULP_ACT_HID_026e,
+ .act_pattern_id = 170,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [229] = {
+ .act_hid = BNXT_ULP_ACT_HID_1fe2,
+ .act_pattern_id = 171,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [230] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d82,
+ .act_pattern_id = 172,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [231] = {
+ .act_hid = BNXT_ULP_ACT_HID_14d6,
+ .act_pattern_id = 173,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [232] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e92,
+ .act_pattern_id = 174,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [233] = {
+ .act_hid = BNXT_ULP_ACT_HID_58f6,
+ .act_pattern_id = 175,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [234] = {
+ .act_hid = BNXT_ULP_ACT_HID_104a,
+ .act_pattern_id = 176,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [235] = {
+ .act_hid = BNXT_ULP_ACT_HID_215a,
+ .act_pattern_id = 177,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [236] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d92,
+ .act_pattern_id = 178,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [237] = {
+ .act_hid = BNXT_ULP_ACT_HID_14e6,
+ .act_pattern_id = 179,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [238] = {
+ .act_hid = BNXT_ULP_ACT_HID_6ea2,
+ .act_pattern_id = 180,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [239] = {
+ .act_hid = BNXT_ULP_ACT_HID_5906,
+ .act_pattern_id = 181,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [240] = {
+ .act_hid = BNXT_ULP_ACT_HID_105a,
+ .act_pattern_id = 182,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [241] = {
+ .act_hid = BNXT_ULP_ACT_HID_216a,
+ .act_pattern_id = 183,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [242] = {
+ .act_hid = BNXT_ULP_ACT_HID_6582,
+ .act_pattern_id = 184,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [243] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cd6,
+ .act_pattern_id = 185,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [244] = {
+ .act_hid = BNXT_ULP_ACT_HID_7692,
+ .act_pattern_id = 186,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [245] = {
+ .act_hid = BNXT_ULP_ACT_HID_60f6,
+ .act_pattern_id = 187,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [246] = {
+ .act_hid = BNXT_ULP_ACT_HID_184a,
+ .act_pattern_id = 188,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [247] = {
+ .act_hid = BNXT_ULP_ACT_HID_295a,
+ .act_pattern_id = 189,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [248] = {
+ .act_hid = BNXT_ULP_ACT_HID_6592,
+ .act_pattern_id = 190,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [249] = {
+ .act_hid = BNXT_ULP_ACT_HID_1ce6,
+ .act_pattern_id = 191,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [250] = {
+ .act_hid = BNXT_ULP_ACT_HID_76a2,
+ .act_pattern_id = 192,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [251] = {
+ .act_hid = BNXT_ULP_ACT_HID_6106,
+ .act_pattern_id = 193,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [252] = {
+ .act_hid = BNXT_ULP_ACT_HID_185a,
+ .act_pattern_id = 194,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [253] = {
+ .act_hid = BNXT_ULP_ACT_HID_296a,
+ .act_pattern_id = 195,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [254] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d82,
+ .act_pattern_id = 196,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [255] = {
+ .act_hid = BNXT_ULP_ACT_HID_24d6,
+ .act_pattern_id = 197,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [256] = {
+ .act_hid = BNXT_ULP_ACT_HID_02d6,
+ .act_pattern_id = 198,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [257] = {
+ .act_hid = BNXT_ULP_ACT_HID_68f6,
+ .act_pattern_id = 199,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [258] = {
+ .act_hid = BNXT_ULP_ACT_HID_204a,
+ .act_pattern_id = 200,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [259] = {
+ .act_hid = BNXT_ULP_ACT_HID_315a,
+ .act_pattern_id = 201,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [260] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d92,
+ .act_pattern_id = 202,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [261] = {
+ .act_hid = BNXT_ULP_ACT_HID_24e6,
+ .act_pattern_id = 203,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [262] = {
+ .act_hid = BNXT_ULP_ACT_HID_02e6,
+ .act_pattern_id = 204,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [263] = {
+ .act_hid = BNXT_ULP_ACT_HID_6906,
+ .act_pattern_id = 205,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [264] = {
+ .act_hid = BNXT_ULP_ACT_HID_205a,
+ .act_pattern_id = 206,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [265] = {
+ .act_hid = BNXT_ULP_ACT_HID_316a,
+ .act_pattern_id = 207,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [266] = {
+ .act_hid = BNXT_ULP_ACT_HID_7582,
+ .act_pattern_id = 208,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [267] = {
+ .act_hid = BNXT_ULP_ACT_HID_2cd6,
+ .act_pattern_id = 209,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [268] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ad6,
+ .act_pattern_id = 210,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [269] = {
+ .act_hid = BNXT_ULP_ACT_HID_70f6,
+ .act_pattern_id = 211,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [270] = {
+ .act_hid = BNXT_ULP_ACT_HID_284a,
+ .act_pattern_id = 212,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [271] = {
+ .act_hid = BNXT_ULP_ACT_HID_395a,
+ .act_pattern_id = 213,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [272] = {
+ .act_hid = BNXT_ULP_ACT_HID_7592,
+ .act_pattern_id = 214,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [273] = {
+ .act_hid = BNXT_ULP_ACT_HID_2ce6,
+ .act_pattern_id = 215,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [274] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ae6,
+ .act_pattern_id = 216,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [275] = {
+ .act_hid = BNXT_ULP_ACT_HID_7106,
+ .act_pattern_id = 217,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [276] = {
+ .act_hid = BNXT_ULP_ACT_HID_285a,
+ .act_pattern_id = 218,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [277] = {
+ .act_hid = BNXT_ULP_ACT_HID_396a,
+ .act_pattern_id = 219,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [278] = {
+ .act_hid = BNXT_ULP_ACT_HID_0020,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [279] = {
+ .act_hid = BNXT_ULP_ACT_HID_0030,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [280] = {
+ .act_hid = BNXT_ULP_ACT_HID_65d4,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [281] = {
+ .act_hid = BNXT_ULP_ACT_HID_65e4,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [282] = {
+ .act_hid = BNXT_ULP_ACT_HID_330a,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [283] = {
+ .act_hid = BNXT_ULP_ACT_HID_331a,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_RSS |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [284] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cfe,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 4
+ },
+ [285] = {
+ .act_hid = BNXT_ULP_ACT_HID_1d0e,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_QUEUE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 4
},
- [56] = {
- .act_hid = BNXT_ULP_ACT_HID_021e,
- .act_pattern_id = 2,
+ [286] = {
+ .act_hid = BNXT_ULP_ACT_HID_1474,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_METER_PROFILE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [287] = {
+ .act_hid = BNXT_ULP_ACT_HID_4838,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [288] = {
+ .act_hid = BNXT_ULP_ACT_HID_6458,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_METER_PROFILE |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [289] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c68,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [290] = {
+ .act_hid = BNXT_ULP_ACT_HID_6c34,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_UPDATE |
+ BNXT_ULP_ACT_BIT_SHARED_METER |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 5
+ },
+ [291] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d08,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [292] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d10,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [293] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d20,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [294] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e18,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [295] = {
+ .act_hid = BNXT_ULP_ACT_HID_29d4,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [296] = {
+ .act_hid = BNXT_ULP_ACT_HID_7690,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [297] = {
+ .act_hid = BNXT_ULP_ACT_HID_47a0,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [298] = {
+ .act_hid = BNXT_ULP_ACT_HID_435c,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [299] = {
+ .act_hid = BNXT_ULP_ACT_HID_5d18,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [300] = {
+ .act_hid = BNXT_ULP_ACT_HID_2e28,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [301] = {
+ .act_hid = BNXT_ULP_ACT_HID_29e4,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [302] = {
+ .act_hid = BNXT_ULP_ACT_HID_76a0,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [303] = {
+ .act_hid = BNXT_ULP_ACT_HID_47b0,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [304] = {
+ .act_hid = BNXT_ULP_ACT_HID_436c,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [305] = {
+ .act_hid = BNXT_ULP_ACT_HID_1436,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [306] = {
+ .act_hid = BNXT_ULP_ACT_HID_143e,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [307] = {
+ .act_hid = BNXT_ULP_ACT_HID_144e,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [308] = {
+ .act_hid = BNXT_ULP_ACT_HID_6102,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [309] = {
+ .act_hid = BNXT_ULP_ACT_HID_5cbe,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [310] = {
+ .act_hid = BNXT_ULP_ACT_HID_2dbe,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [311] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a8a,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [312] = {
+ .act_hid = BNXT_ULP_ACT_HID_7646,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [313] = {
+ .act_hid = BNXT_ULP_ACT_HID_1446,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [314] = {
+ .act_hid = BNXT_ULP_ACT_HID_6112,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [315] = {
+ .act_hid = BNXT_ULP_ACT_HID_5cce,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [316] = {
+ .act_hid = BNXT_ULP_ACT_HID_2dce,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [317] = {
+ .act_hid = BNXT_ULP_ACT_HID_7a9a,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [318] = {
+ .act_hid = BNXT_ULP_ACT_HID_7656,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_VLAN_VID |
+ BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 6
+ },
+ [319] = {
+ .act_hid = BNXT_ULP_ACT_HID_6508,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [320] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d08,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [321] = {
+ .act_hid = BNXT_ULP_ACT_HID_7508,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [322] = {
+ .act_hid = BNXT_ULP_ACT_HID_6518,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [323] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d18,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [324] = {
+ .act_hid = BNXT_ULP_ACT_HID_7518,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [325] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e18,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [326] = {
+ .act_hid = BNXT_ULP_ACT_HID_256c,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [327] = {
+ .act_hid = BNXT_ULP_ACT_HID_036c,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [328] = {
+ .act_hid = BNXT_ULP_ACT_HID_698c,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [329] = {
+ .act_hid = BNXT_ULP_ACT_HID_20e0,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [330] = {
+ .act_hid = BNXT_ULP_ACT_HID_31f0,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [331] = {
+ .act_hid = BNXT_ULP_ACT_HID_7618,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [332] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d6c,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [333] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b6c,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [334] = {
+ .act_hid = BNXT_ULP_ACT_HID_718c,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [335] = {
+ .act_hid = BNXT_ULP_ACT_HID_28e0,
+ .act_pattern_id = 16,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [336] = {
+ .act_hid = BNXT_ULP_ACT_HID_39f0,
+ .act_pattern_id = 17,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [337] = {
+ .act_hid = BNXT_ULP_ACT_HID_025c,
+ .act_pattern_id = 18,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [338] = {
+ .act_hid = BNXT_ULP_ACT_HID_356c,
+ .act_pattern_id = 19,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [339] = {
+ .act_hid = BNXT_ULP_ACT_HID_136c,
+ .act_pattern_id = 20,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [340] = {
+ .act_hid = BNXT_ULP_ACT_HID_798c,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [341] = {
+ .act_hid = BNXT_ULP_ACT_HID_30e0,
+ .act_pattern_id = 22,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [342] = {
+ .act_hid = BNXT_ULP_ACT_HID_41f0,
+ .act_pattern_id = 23,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [343] = {
+ .act_hid = BNXT_ULP_ACT_HID_0a5c,
+ .act_pattern_id = 24,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [344] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d6c,
+ .act_pattern_id = 25,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [345] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b6c,
+ .act_pattern_id = 26,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [346] = {
+ .act_hid = BNXT_ULP_ACT_HID_05d0,
+ .act_pattern_id = 27,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [347] = {
+ .act_hid = BNXT_ULP_ACT_HID_38e0,
+ .act_pattern_id = 28,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [348] = {
+ .act_hid = BNXT_ULP_ACT_HID_49f0,
+ .act_pattern_id = 29,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [349] = {
+ .act_hid = BNXT_ULP_ACT_HID_6e28,
+ .act_pattern_id = 30,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [350] = {
+ .act_hid = BNXT_ULP_ACT_HID_257c,
+ .act_pattern_id = 31,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [351] = {
+ .act_hid = BNXT_ULP_ACT_HID_037c,
+ .act_pattern_id = 32,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [352] = {
+ .act_hid = BNXT_ULP_ACT_HID_699c,
+ .act_pattern_id = 33,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [353] = {
+ .act_hid = BNXT_ULP_ACT_HID_20f0,
+ .act_pattern_id = 34,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [354] = {
+ .act_hid = BNXT_ULP_ACT_HID_3200,
+ .act_pattern_id = 35,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [355] = {
+ .act_hid = BNXT_ULP_ACT_HID_7628,
+ .act_pattern_id = 36,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [356] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d7c,
+ .act_pattern_id = 37,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [357] = {
+ .act_hid = BNXT_ULP_ACT_HID_0b7c,
+ .act_pattern_id = 38,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [358] = {
+ .act_hid = BNXT_ULP_ACT_HID_719c,
+ .act_pattern_id = 39,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [359] = {
+ .act_hid = BNXT_ULP_ACT_HID_28f0,
+ .act_pattern_id = 40,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [360] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a00,
+ .act_pattern_id = 41,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [361] = {
+ .act_hid = BNXT_ULP_ACT_HID_026c,
+ .act_pattern_id = 42,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [362] = {
+ .act_hid = BNXT_ULP_ACT_HID_357c,
+ .act_pattern_id = 43,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [363] = {
+ .act_hid = BNXT_ULP_ACT_HID_137c,
+ .act_pattern_id = 44,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [364] = {
+ .act_hid = BNXT_ULP_ACT_HID_799c,
+ .act_pattern_id = 45,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [365] = {
+ .act_hid = BNXT_ULP_ACT_HID_30f0,
+ .act_pattern_id = 46,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [366] = {
+ .act_hid = BNXT_ULP_ACT_HID_4200,
+ .act_pattern_id = 47,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [367] = {
+ .act_hid = BNXT_ULP_ACT_HID_0a6c,
+ .act_pattern_id = 48,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [368] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d7c,
+ .act_pattern_id = 49,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [369] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b7c,
+ .act_pattern_id = 50,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [370] = {
+ .act_hid = BNXT_ULP_ACT_HID_05e0,
+ .act_pattern_id = 51,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [371] = {
+ .act_hid = BNXT_ULP_ACT_HID_38f0,
+ .act_pattern_id = 52,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [372] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a00,
+ .act_pattern_id = 53,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [373] = {
+ .act_hid = BNXT_ULP_ACT_HID_0be4,
+ .act_pattern_id = 54,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [374] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ef4,
+ .act_pattern_id = 55,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [375] = {
+ .act_hid = BNXT_ULP_ACT_HID_1cf4,
+ .act_pattern_id = 56,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [376] = {
+ .act_hid = BNXT_ULP_ACT_HID_0758,
+ .act_pattern_id = 57,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [377] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a68,
+ .act_pattern_id = 58,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [378] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b78,
+ .act_pattern_id = 59,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [379] = {
+ .act_hid = BNXT_ULP_ACT_HID_0bf4,
+ .act_pattern_id = 60,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [380] = {
+ .act_hid = BNXT_ULP_ACT_HID_3f04,
+ .act_pattern_id = 61,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [381] = {
+ .act_hid = BNXT_ULP_ACT_HID_1d04,
+ .act_pattern_id = 62,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [382] = {
+ .act_hid = BNXT_ULP_ACT_HID_0768,
+ .act_pattern_id = 63,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [383] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a78,
+ .act_pattern_id = 64,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [384] = {
+ .act_hid = BNXT_ULP_ACT_HID_4b88,
+ .act_pattern_id = 65,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [385] = {
+ .act_hid = BNXT_ULP_ACT_HID_46f4,
+ .act_pattern_id = 66,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [386] = {
+ .act_hid = BNXT_ULP_ACT_HID_24f4,
+ .act_pattern_id = 67,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [387] = {
+ .act_hid = BNXT_ULP_ACT_HID_0f58,
+ .act_pattern_id = 68,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [388] = {
+ .act_hid = BNXT_ULP_ACT_HID_13e4,
+ .act_pattern_id = 69,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [389] = {
+ .act_hid = BNXT_ULP_ACT_HID_4268,
+ .act_pattern_id = 70,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [390] = {
+ .act_hid = BNXT_ULP_ACT_HID_5378,
+ .act_pattern_id = 71,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [391] = {
+ .act_hid = BNXT_ULP_ACT_HID_13f4,
+ .act_pattern_id = 72,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [392] = {
+ .act_hid = BNXT_ULP_ACT_HID_4704,
+ .act_pattern_id = 73,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [393] = {
+ .act_hid = BNXT_ULP_ACT_HID_2504,
+ .act_pattern_id = 74,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [394] = {
+ .act_hid = BNXT_ULP_ACT_HID_0f68,
+ .act_pattern_id = 75,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [395] = {
+ .act_hid = BNXT_ULP_ACT_HID_4278,
+ .act_pattern_id = 76,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [396] = {
+ .act_hid = BNXT_ULP_ACT_HID_5388,
+ .act_pattern_id = 77,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [397] = {
+ .act_hid = BNXT_ULP_ACT_HID_1be4,
+ .act_pattern_id = 78,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [398] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ef4,
+ .act_pattern_id = 79,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [399] = {
+ .act_hid = BNXT_ULP_ACT_HID_2cf4,
+ .act_pattern_id = 80,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [400] = {
+ .act_hid = BNXT_ULP_ACT_HID_1758,
+ .act_pattern_id = 81,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [401] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a68,
+ .act_pattern_id = 82,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [402] = {
+ .act_hid = BNXT_ULP_ACT_HID_5b78,
+ .act_pattern_id = 83,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [403] = {
+ .act_hid = BNXT_ULP_ACT_HID_1bf4,
+ .act_pattern_id = 84,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [404] = {
+ .act_hid = BNXT_ULP_ACT_HID_4f04,
+ .act_pattern_id = 85,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [405] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d04,
+ .act_pattern_id = 86,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [406] = {
+ .act_hid = BNXT_ULP_ACT_HID_1768,
+ .act_pattern_id = 87,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [407] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a78,
+ .act_pattern_id = 88,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [408] = {
+ .act_hid = BNXT_ULP_ACT_HID_5b88,
+ .act_pattern_id = 89,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [409] = {
+ .act_hid = BNXT_ULP_ACT_HID_23e4,
+ .act_pattern_id = 90,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [410] = {
+ .act_hid = BNXT_ULP_ACT_HID_56f4,
+ .act_pattern_id = 91,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [411] = {
+ .act_hid = BNXT_ULP_ACT_HID_34f4,
+ .act_pattern_id = 92,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [412] = {
+ .act_hid = BNXT_ULP_ACT_HID_1f58,
+ .act_pattern_id = 93,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [413] = {
+ .act_hid = BNXT_ULP_ACT_HID_5268,
+ .act_pattern_id = 94,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [414] = {
+ .act_hid = BNXT_ULP_ACT_HID_6378,
+ .act_pattern_id = 95,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [415] = {
+ .act_hid = BNXT_ULP_ACT_HID_23f4,
+ .act_pattern_id = 96,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [416] = {
+ .act_hid = BNXT_ULP_ACT_HID_5704,
+ .act_pattern_id = 97,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [417] = {
+ .act_hid = BNXT_ULP_ACT_HID_3504,
+ .act_pattern_id = 98,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [418] = {
+ .act_hid = BNXT_ULP_ACT_HID_1f68,
+ .act_pattern_id = 99,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [419] = {
+ .act_hid = BNXT_ULP_ACT_HID_5278,
+ .act_pattern_id = 100,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [420] = {
+ .act_hid = BNXT_ULP_ACT_HID_6388,
+ .act_pattern_id = 101,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [421] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c36,
+ .act_pattern_id = 102,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [422] = {
+ .act_hid = BNXT_ULP_ACT_HID_2436,
+ .act_pattern_id = 103,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [423] = {
+ .act_hid = BNXT_ULP_ACT_HID_2c36,
+ .act_pattern_id = 104,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [424] = {
+ .act_hid = BNXT_ULP_ACT_HID_1c46,
+ .act_pattern_id = 105,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [425] = {
+ .act_hid = BNXT_ULP_ACT_HID_2446,
+ .act_pattern_id = 106,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [426] = {
+ .act_hid = BNXT_ULP_ACT_HID_2c46,
+ .act_pattern_id = 107,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [427] = {
+ .act_hid = BNXT_ULP_ACT_HID_2546,
+ .act_pattern_id = 108,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [428] = {
+ .act_hid = BNXT_ULP_ACT_HID_5856,
+ .act_pattern_id = 109,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [429] = {
+ .act_hid = BNXT_ULP_ACT_HID_3656,
+ .act_pattern_id = 110,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [430] = {
+ .act_hid = BNXT_ULP_ACT_HID_20ba,
+ .act_pattern_id = 111,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [431] = {
+ .act_hid = BNXT_ULP_ACT_HID_53ca,
+ .act_pattern_id = 112,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [432] = {
+ .act_hid = BNXT_ULP_ACT_HID_64da,
+ .act_pattern_id = 113,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [433] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d46,
+ .act_pattern_id = 114,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [434] = {
+ .act_hid = BNXT_ULP_ACT_HID_6056,
+ .act_pattern_id = 115,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [435] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e56,
+ .act_pattern_id = 116,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [436] = {
+ .act_hid = BNXT_ULP_ACT_HID_28ba,
+ .act_pattern_id = 117,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [437] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bca,
+ .act_pattern_id = 118,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [438] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cda,
+ .act_pattern_id = 119,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [439] = {
+ .act_hid = BNXT_ULP_ACT_HID_3546,
+ .act_pattern_id = 120,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [440] = {
+ .act_hid = BNXT_ULP_ACT_HID_6856,
+ .act_pattern_id = 121,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [441] = {
+ .act_hid = BNXT_ULP_ACT_HID_4656,
+ .act_pattern_id = 122,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [442] = {
+ .act_hid = BNXT_ULP_ACT_HID_30ba,
+ .act_pattern_id = 123,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [443] = {
+ .act_hid = BNXT_ULP_ACT_HID_63ca,
+ .act_pattern_id = 124,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [444] = {
+ .act_hid = BNXT_ULP_ACT_HID_74da,
+ .act_pattern_id = 125,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [445] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d46,
+ .act_pattern_id = 126,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [446] = {
+ .act_hid = BNXT_ULP_ACT_HID_7056,
+ .act_pattern_id = 127,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [447] = {
+ .act_hid = BNXT_ULP_ACT_HID_4e56,
+ .act_pattern_id = 128,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [448] = {
+ .act_hid = BNXT_ULP_ACT_HID_38ba,
+ .act_pattern_id = 129,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [449] = {
+ .act_hid = BNXT_ULP_ACT_HID_6bca,
+ .act_pattern_id = 130,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [450] = {
+ .act_hid = BNXT_ULP_ACT_HID_011e,
+ .act_pattern_id = 131,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [451] = {
+ .act_hid = BNXT_ULP_ACT_HID_2556,
+ .act_pattern_id = 132,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [452] = {
+ .act_hid = BNXT_ULP_ACT_HID_5866,
+ .act_pattern_id = 133,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [453] = {
+ .act_hid = BNXT_ULP_ACT_HID_3666,
+ .act_pattern_id = 134,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [454] = {
+ .act_hid = BNXT_ULP_ACT_HID_20ca,
+ .act_pattern_id = 135,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [455] = {
+ .act_hid = BNXT_ULP_ACT_HID_53da,
+ .act_pattern_id = 136,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [456] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ea,
+ .act_pattern_id = 137,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [457] = {
+ .act_hid = BNXT_ULP_ACT_HID_2d56,
+ .act_pattern_id = 138,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [458] = {
+ .act_hid = BNXT_ULP_ACT_HID_6066,
+ .act_pattern_id = 139,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [459] = {
+ .act_hid = BNXT_ULP_ACT_HID_3e66,
+ .act_pattern_id = 140,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [460] = {
+ .act_hid = BNXT_ULP_ACT_HID_28ca,
+ .act_pattern_id = 141,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [461] = {
+ .act_hid = BNXT_ULP_ACT_HID_5bda,
+ .act_pattern_id = 142,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [462] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cea,
+ .act_pattern_id = 143,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [463] = {
+ .act_hid = BNXT_ULP_ACT_HID_3556,
+ .act_pattern_id = 144,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [464] = {
+ .act_hid = BNXT_ULP_ACT_HID_6866,
+ .act_pattern_id = 145,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [465] = {
+ .act_hid = BNXT_ULP_ACT_HID_4666,
+ .act_pattern_id = 146,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [466] = {
+ .act_hid = BNXT_ULP_ACT_HID_30ca,
+ .act_pattern_id = 147,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [467] = {
+ .act_hid = BNXT_ULP_ACT_HID_63da,
+ .act_pattern_id = 148,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [468] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ea,
+ .act_pattern_id = 149,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [469] = {
+ .act_hid = BNXT_ULP_ACT_HID_3d56,
+ .act_pattern_id = 150,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_DROP |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [57] = {
- .act_hid = BNXT_ULP_ACT_HID_063f,
- .act_pattern_id = 3,
+ [470] = {
+ .act_hid = BNXT_ULP_ACT_HID_7066,
+ .act_pattern_id = 151,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [58] = {
- .act_hid = BNXT_ULP_ACT_HID_0510,
- .act_pattern_id = 4,
+ [471] = {
+ .act_hid = BNXT_ULP_ACT_HID_4e66,
+ .act_pattern_id = 152,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [59] = {
- .act_hid = BNXT_ULP_ACT_HID_03c6,
- .act_pattern_id = 5,
+ [472] = {
+ .act_hid = BNXT_ULP_ACT_HID_38ca,
+ .act_pattern_id = 153,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [473] = {
+ .act_hid = BNXT_ULP_ACT_HID_6bda,
+ .act_pattern_id = 154,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [474] = {
+ .act_hid = BNXT_ULP_ACT_HID_012e,
+ .act_pattern_id = 155,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [475] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ece,
+ .act_pattern_id = 156,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [60] = {
- .act_hid = BNXT_ULP_ACT_HID_0082,
- .act_pattern_id = 6,
+ [476] = {
+ .act_hid = BNXT_ULP_ACT_HID_71de,
+ .act_pattern_id = 157,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [61] = {
- .act_hid = BNXT_ULP_ACT_HID_06bb,
- .act_pattern_id = 7,
+ [477] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fde,
+ .act_pattern_id = 158,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [62] = {
- .act_hid = BNXT_ULP_ACT_HID_021d,
- .act_pattern_id = 8,
+ [478] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a42,
+ .act_pattern_id = 159,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [479] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d52,
+ .act_pattern_id = 160,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [480] = {
+ .act_hid = BNXT_ULP_ACT_HID_02a6,
+ .act_pattern_id = 161,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [481] = {
+ .act_hid = BNXT_ULP_ACT_HID_3ede,
+ .act_pattern_id = 162,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [63] = {
- .act_hid = BNXT_ULP_ACT_HID_0641,
- .act_pattern_id = 9,
+ [482] = {
+ .act_hid = BNXT_ULP_ACT_HID_71ee,
+ .act_pattern_id = 163,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [64] = {
- .act_hid = BNXT_ULP_ACT_HID_0512,
- .act_pattern_id = 10,
+ [483] = {
+ .act_hid = BNXT_ULP_ACT_HID_4fee,
+ .act_pattern_id = 164,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [65] = {
- .act_hid = BNXT_ULP_ACT_HID_03c8,
- .act_pattern_id = 11,
+ [484] = {
+ .act_hid = BNXT_ULP_ACT_HID_3a52,
+ .act_pattern_id = 165,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [485] = {
+ .act_hid = BNXT_ULP_ACT_HID_6d62,
+ .act_pattern_id = 166,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [486] = {
+ .act_hid = BNXT_ULP_ACT_HID_02b6,
+ .act_pattern_id = 167,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [66] = {
- .act_hid = BNXT_ULP_ACT_HID_0084,
- .act_pattern_id = 12,
+ [487] = {
+ .act_hid = BNXT_ULP_ACT_HID_79de,
+ .act_pattern_id = 168,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [488] = {
+ .act_hid = BNXT_ULP_ACT_HID_57de,
+ .act_pattern_id = 169,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [489] = {
+ .act_hid = BNXT_ULP_ACT_HID_4242,
+ .act_pattern_id = 170,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [490] = {
+ .act_hid = BNXT_ULP_ACT_HID_46ce,
+ .act_pattern_id = 171,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [491] = {
+ .act_hid = BNXT_ULP_ACT_HID_7552,
+ .act_pattern_id = 172,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [492] = {
+ .act_hid = BNXT_ULP_ACT_HID_0aa6,
+ .act_pattern_id = 173,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [493] = {
+ .act_hid = BNXT_ULP_ACT_HID_46de,
+ .act_pattern_id = 174,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [494] = {
+ .act_hid = BNXT_ULP_ACT_HID_79ee,
+ .act_pattern_id = 175,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_PCP |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [67] = {
- .act_hid = BNXT_ULP_ACT_HID_06bd,
- .act_pattern_id = 13,
+ [495] = {
+ .act_hid = BNXT_ULP_ACT_HID_57ee,
+ .act_pattern_id = 176,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [496] = {
+ .act_hid = BNXT_ULP_ACT_HID_4252,
+ .act_pattern_id = 177,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [497] = {
+ .act_hid = BNXT_ULP_ACT_HID_7562,
+ .act_pattern_id = 178,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
BNXT_ULP_ACT_BIT_DEC_TTL |
- BNXT_ULP_ACT_BIT_SET_VLAN_VID |
- BNXT_ULP_ACT_BIT_PUSH_VLAN |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 4
+ .act_tid = 7
},
- [68] = {
- .act_hid = BNXT_ULP_ACT_HID_06d7,
- .act_pattern_id = 0,
+ [498] = {
+ .act_hid = BNXT_ULP_ACT_HID_0ab6,
+ .act_pattern_id = 179,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 7
+ },
+ [499] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ece,
+ .act_pattern_id = 180,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [69] = {
- .act_hid = BNXT_ULP_ACT_HID_02c4,
- .act_pattern_id = 1,
+ [500] = {
+ .act_hid = BNXT_ULP_ACT_HID_0622,
+ .act_pattern_id = 181,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [70] = {
- .act_hid = BNXT_ULP_ACT_HID_042a,
- .act_pattern_id = 2,
+ [501] = {
+ .act_hid = BNXT_ULP_ACT_HID_5fde,
+ .act_pattern_id = 182,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [71] = {
- .act_hid = BNXT_ULP_ACT_HID_036e,
- .act_pattern_id = 3,
+ [502] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a42,
+ .act_pattern_id = 183,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [72] = {
- .act_hid = BNXT_ULP_ACT_HID_06c4,
- .act_pattern_id = 4,
+ [503] = {
+ .act_hid = BNXT_ULP_ACT_HID_0196,
+ .act_pattern_id = 184,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [73] = {
- .act_hid = BNXT_ULP_ACT_HID_0417,
- .act_pattern_id = 5,
+ [504] = {
+ .act_hid = BNXT_ULP_ACT_HID_12a6,
+ .act_pattern_id = 185,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [74] = {
- .act_hid = BNXT_ULP_ACT_HID_06d9,
- .act_pattern_id = 6,
+ [505] = {
+ .act_hid = BNXT_ULP_ACT_HID_4ede,
+ .act_pattern_id = 186,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [75] = {
- .act_hid = BNXT_ULP_ACT_HID_02c6,
- .act_pattern_id = 7,
+ [506] = {
+ .act_hid = BNXT_ULP_ACT_HID_0632,
+ .act_pattern_id = 187,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [76] = {
- .act_hid = BNXT_ULP_ACT_HID_042c,
- .act_pattern_id = 8,
+ [507] = {
+ .act_hid = BNXT_ULP_ACT_HID_5fee,
+ .act_pattern_id = 188,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [77] = {
- .act_hid = BNXT_ULP_ACT_HID_0370,
- .act_pattern_id = 9,
+ [508] = {
+ .act_hid = BNXT_ULP_ACT_HID_4a52,
+ .act_pattern_id = 189,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [78] = {
- .act_hid = BNXT_ULP_ACT_HID_06c6,
- .act_pattern_id = 10,
+ [509] = {
+ .act_hid = BNXT_ULP_ACT_HID_01a6,
+ .act_pattern_id = 190,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [79] = {
- .act_hid = BNXT_ULP_ACT_HID_0419,
- .act_pattern_id = 11,
+ [510] = {
+ .act_hid = BNXT_ULP_ACT_HID_12b6,
+ .act_pattern_id = 191,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [80] = {
- .act_hid = BNXT_ULP_ACT_HID_0119,
- .act_pattern_id = 12,
+ [511] = {
+ .act_hid = BNXT_ULP_ACT_HID_56ce,
+ .act_pattern_id = 192,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [81] = {
- .act_hid = BNXT_ULP_ACT_HID_046f,
- .act_pattern_id = 13,
+ [512] = {
+ .act_hid = BNXT_ULP_ACT_HID_0e22,
+ .act_pattern_id = 193,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [82] = {
- .act_hid = BNXT_ULP_ACT_HID_05d5,
- .act_pattern_id = 14,
+ [513] = {
+ .act_hid = BNXT_ULP_ACT_HID_67de,
+ .act_pattern_id = 194,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [83] = {
- .act_hid = BNXT_ULP_ACT_HID_0519,
- .act_pattern_id = 15,
+ [514] = {
+ .act_hid = BNXT_ULP_ACT_HID_5242,
+ .act_pattern_id = 195,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [84] = {
- .act_hid = BNXT_ULP_ACT_HID_0106,
- .act_pattern_id = 16,
+ [515] = {
+ .act_hid = BNXT_ULP_ACT_HID_0996,
+ .act_pattern_id = 196,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [85] = {
- .act_hid = BNXT_ULP_ACT_HID_05c2,
- .act_pattern_id = 17,
+ [516] = {
+ .act_hid = BNXT_ULP_ACT_HID_1aa6,
+ .act_pattern_id = 197,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [86] = {
- .act_hid = BNXT_ULP_ACT_HID_011b,
- .act_pattern_id = 18,
+ [517] = {
+ .act_hid = BNXT_ULP_ACT_HID_56de,
+ .act_pattern_id = 198,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [87] = {
- .act_hid = BNXT_ULP_ACT_HID_0471,
- .act_pattern_id = 19,
+ [518] = {
+ .act_hid = BNXT_ULP_ACT_HID_0e32,
+ .act_pattern_id = 199,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [88] = {
- .act_hid = BNXT_ULP_ACT_HID_05d7,
- .act_pattern_id = 20,
+ [519] = {
+ .act_hid = BNXT_ULP_ACT_HID_67ee,
+ .act_pattern_id = 200,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [89] = {
- .act_hid = BNXT_ULP_ACT_HID_051b,
- .act_pattern_id = 21,
+ [520] = {
+ .act_hid = BNXT_ULP_ACT_HID_5252,
+ .act_pattern_id = 201,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [90] = {
- .act_hid = BNXT_ULP_ACT_HID_0108,
- .act_pattern_id = 22,
+ [521] = {
+ .act_hid = BNXT_ULP_ACT_HID_09a6,
+ .act_pattern_id = 202,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [91] = {
- .act_hid = BNXT_ULP_ACT_HID_05c4,
- .act_pattern_id = 23,
+ [522] = {
+ .act_hid = BNXT_ULP_ACT_HID_1ab6,
+ .act_pattern_id = 203,
.app_sig = 0,
.act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
BNXT_ULP_ACT_BIT_DEC_TTL |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
@@ -1089,25 +6906,255 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 5
+ .act_tid = 7
},
- [92] = {
- .act_hid = BNXT_ULP_ACT_HID_00a2,
+ [523] = {
+ .act_hid = BNXT_ULP_ACT_HID_31d0,
.act_pattern_id = 0,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 6
+ .act_tid = 8
},
- [93] = {
- .act_hid = BNXT_ULP_ACT_HID_00a4,
+ [524] = {
+ .act_hid = BNXT_ULP_ACT_HID_31e0,
.act_pattern_id = 1,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 6
+ .act_tid = 8
+ },
+ [525] = {
+ .act_hid = BNXT_ULP_ACT_HID_39d0,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [526] = {
+ .act_hid = BNXT_ULP_ACT_HID_39e0,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [527] = {
+ .act_hid = BNXT_ULP_ACT_HID_41d0,
+ .act_pattern_id = 4,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [528] = {
+ .act_hid = BNXT_ULP_ACT_HID_41e0,
+ .act_pattern_id = 5,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [529] = {
+ .act_hid = BNXT_ULP_ACT_HID_49d0,
+ .act_pattern_id = 6,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [530] = {
+ .act_hid = BNXT_ULP_ACT_HID_49e0,
+ .act_pattern_id = 7,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [531] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ba,
+ .act_pattern_id = 8,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [532] = {
+ .act_hid = BNXT_ULP_ACT_HID_64ca,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [533] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cba,
+ .act_pattern_id = 10,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [534] = {
+ .act_hid = BNXT_ULP_ACT_HID_6cca,
+ .act_pattern_id = 11,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [535] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ba,
+ .act_pattern_id = 12,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [536] = {
+ .act_hid = BNXT_ULP_ACT_HID_74ca,
+ .act_pattern_id = 13,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [537] = {
+ .act_hid = BNXT_ULP_ACT_HID_00fe,
+ .act_pattern_id = 14,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [538] = {
+ .act_hid = BNXT_ULP_ACT_HID_010e,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC |
+ BNXT_ULP_ACT_BIT_SET_MAC_DST |
+ BNXT_ULP_ACT_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 8
+ },
+ [539] = {
+ .act_hid = BNXT_ULP_ACT_HID_331c,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [540] = {
+ .act_hid = BNXT_ULP_ACT_HID_332c,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [541] = {
+ .act_hid = BNXT_ULP_ACT_HID_6706,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [542] = {
+ .act_hid = BNXT_ULP_ACT_HID_6716,
+ .act_pattern_id = 3,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 9
+ },
+ [543] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b6d,
+ .act_pattern_id = 0,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
+ },
+ [544] = {
+ .act_hid = BNXT_ULP_ACT_HID_1b7d,
+ .act_pattern_id = 1,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SHARED |
+ BNXT_ULP_ACT_BIT_SAMPLE |
+ BNXT_ULP_ACT_BIT_VF_TO_VF |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
+ },
+ [545] = {
+ .act_hid = BNXT_ULP_ACT_HID_641a,
+ .act_pattern_id = 2,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DELETE |
+ BNXT_ULP_ACT_BIT_SHARED_SAMPLE |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 10
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
index c127a53b32..1c68502ed0 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -16,1308 +14,1918 @@
* maps hash id to ulp_class_match_list[] index
*/
uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_CLASS_HID_55dd] = 1,
- [BNXT_ULP_CLASS_HID_1df1] = 2,
- [BNXT_ULP_CLASS_HID_3e55] = 3,
- [BNXT_ULP_CLASS_HID_0649] = 4,
- [BNXT_ULP_CLASS_HID_1011] = 5,
- [BNXT_ULP_CLASS_HID_40e9] = 6,
- [BNXT_ULP_CLASS_HID_3e99] = 7,
- [BNXT_ULP_CLASS_HID_06ad] = 8,
- [BNXT_ULP_CLASS_HID_38c7] = 9,
- [BNXT_ULP_CLASS_HID_00fb] = 10,
- [BNXT_ULP_CLASS_HID_24d3] = 11,
- [BNXT_ULP_CLASS_HID_559b] = 12,
- [BNXT_ULP_CLASS_HID_5003] = 13,
- [BNXT_ULP_CLASS_HID_1837] = 14,
- [BNXT_ULP_CLASS_HID_3bef] = 15,
- [BNXT_ULP_CLASS_HID_0403] = 16,
- [BNXT_ULP_CLASS_HID_3d3f] = 17,
- [BNXT_ULP_CLASS_HID_0543] = 18,
- [BNXT_ULP_CLASS_HID_292b] = 19,
- [BNXT_ULP_CLASS_HID_59e3] = 20,
- [BNXT_ULP_CLASS_HID_5d3b] = 21,
- [BNXT_ULP_CLASS_HID_254f] = 22,
- [BNXT_ULP_CLASS_HID_4917] = 23,
- [BNXT_ULP_CLASS_HID_113b] = 24,
- [BNXT_ULP_CLASS_HID_55fd] = 25,
- [BNXT_ULP_CLASS_HID_1dd1] = 26,
- [BNXT_ULP_CLASS_HID_3e75] = 27,
- [BNXT_ULP_CLASS_HID_0669] = 28,
- [BNXT_ULP_CLASS_HID_1ba1] = 29,
- [BNXT_ULP_CLASS_HID_4c69] = 30,
- [BNXT_ULP_CLASS_HID_0439] = 31,
- [BNXT_ULP_CLASS_HID_34e1] = 32,
- [BNXT_ULP_CLASS_HID_0465] = 33,
- [BNXT_ULP_CLASS_HID_352d] = 34,
- [BNXT_ULP_CLASS_HID_55b1] = 35,
- [BNXT_ULP_CLASS_HID_1da5] = 36,
- [BNXT_ULP_CLASS_HID_32fd] = 37,
- [BNXT_ULP_CLASS_HID_63a5] = 38,
- [BNXT_ULP_CLASS_HID_1b75] = 39,
- [BNXT_ULP_CLASS_HID_4c3d] = 40,
- [BNXT_ULP_CLASS_HID_1031] = 41,
- [BNXT_ULP_CLASS_HID_40c9] = 42,
- [BNXT_ULP_CLASS_HID_3eb9] = 43,
- [BNXT_ULP_CLASS_HID_068d] = 44,
- [BNXT_ULP_CLASS_HID_5039] = 45,
- [BNXT_ULP_CLASS_HID_180d] = 46,
- [BNXT_ULP_CLASS_HID_15fd] = 47,
- [BNXT_ULP_CLASS_HID_46b5] = 48,
- [BNXT_ULP_CLASS_HID_303d] = 49,
- [BNXT_ULP_CLASS_HID_60f5] = 50,
- [BNXT_ULP_CLASS_HID_5ea5] = 51,
- [BNXT_ULP_CLASS_HID_2689] = 52,
- [BNXT_ULP_CLASS_HID_0771] = 53,
- [BNXT_ULP_CLASS_HID_3809] = 54,
- [BNXT_ULP_CLASS_HID_35f9] = 55,
- [BNXT_ULP_CLASS_HID_66b1] = 56,
- [BNXT_ULP_CLASS_HID_559d] = 57,
- [BNXT_ULP_CLASS_HID_1db1] = 58,
- [BNXT_ULP_CLASS_HID_3e15] = 59,
- [BNXT_ULP_CLASS_HID_0609] = 60,
- [BNXT_ULP_CLASS_HID_1bc1] = 61,
- [BNXT_ULP_CLASS_HID_4c09] = 62,
- [BNXT_ULP_CLASS_HID_0459] = 63,
- [BNXT_ULP_CLASS_HID_3481] = 64,
- [BNXT_ULP_CLASS_HID_0405] = 65,
- [BNXT_ULP_CLASS_HID_354d] = 66,
- [BNXT_ULP_CLASS_HID_55d1] = 67,
- [BNXT_ULP_CLASS_HID_1dc5] = 68,
- [BNXT_ULP_CLASS_HID_329d] = 69,
- [BNXT_ULP_CLASS_HID_63c5] = 70,
- [BNXT_ULP_CLASS_HID_1b15] = 71,
- [BNXT_ULP_CLASS_HID_4c5d] = 72,
- [BNXT_ULP_CLASS_HID_1051] = 73,
- [BNXT_ULP_CLASS_HID_40a9] = 74,
- [BNXT_ULP_CLASS_HID_3ed9] = 75,
- [BNXT_ULP_CLASS_HID_06ed] = 76,
- [BNXT_ULP_CLASS_HID_5059] = 77,
- [BNXT_ULP_CLASS_HID_186d] = 78,
- [BNXT_ULP_CLASS_HID_159d] = 79,
- [BNXT_ULP_CLASS_HID_46d5] = 80,
- [BNXT_ULP_CLASS_HID_305d] = 81,
- [BNXT_ULP_CLASS_HID_6095] = 82,
- [BNXT_ULP_CLASS_HID_5ec5] = 83,
- [BNXT_ULP_CLASS_HID_26e9] = 84,
- [BNXT_ULP_CLASS_HID_0711] = 85,
- [BNXT_ULP_CLASS_HID_3869] = 86,
- [BNXT_ULP_CLASS_HID_3599] = 87,
- [BNXT_ULP_CLASS_HID_66d1] = 88,
- [BNXT_ULP_CLASS_HID_38e7] = 89,
- [BNXT_ULP_CLASS_HID_00db] = 90,
- [BNXT_ULP_CLASS_HID_24f3] = 91,
- [BNXT_ULP_CLASS_HID_55bb] = 92,
- [BNXT_ULP_CLASS_HID_5023] = 93,
- [BNXT_ULP_CLASS_HID_1817] = 94,
- [BNXT_ULP_CLASS_HID_3bcf] = 95,
- [BNXT_ULP_CLASS_HID_0423] = 96,
- [BNXT_ULP_CLASS_HID_58e3] = 97,
- [BNXT_ULP_CLASS_HID_20d7] = 98,
- [BNXT_ULP_CLASS_HID_448f] = 99,
- [BNXT_ULP_CLASS_HID_0ce3] = 100,
- [BNXT_ULP_CLASS_HID_076b] = 101,
- [BNXT_ULP_CLASS_HID_3813] = 102,
- [BNXT_ULP_CLASS_HID_5bcb] = 103,
- [BNXT_ULP_CLASS_HID_243f] = 104,
- [BNXT_ULP_CLASS_HID_144b] = 105,
- [BNXT_ULP_CLASS_HID_4573] = 106,
- [BNXT_ULP_CLASS_HID_0057] = 107,
- [BNXT_ULP_CLASS_HID_311f] = 108,
- [BNXT_ULP_CLASS_HID_2b87] = 109,
- [BNXT_ULP_CLASS_HID_5c4f] = 110,
- [BNXT_ULP_CLASS_HID_1793] = 111,
- [BNXT_ULP_CLASS_HID_485b] = 112,
- [BNXT_ULP_CLASS_HID_3447] = 113,
- [BNXT_ULP_CLASS_HID_650f] = 114,
- [BNXT_ULP_CLASS_HID_2053] = 115,
- [BNXT_ULP_CLASS_HID_511b] = 116,
- [BNXT_ULP_CLASS_HID_4b83] = 117,
- [BNXT_ULP_CLASS_HID_13f7] = 118,
- [BNXT_ULP_CLASS_HID_37af] = 119,
- [BNXT_ULP_CLASS_HID_6857] = 120,
- [BNXT_ULP_CLASS_HID_3d1f] = 121,
- [BNXT_ULP_CLASS_HID_0563] = 122,
- [BNXT_ULP_CLASS_HID_290b] = 123,
- [BNXT_ULP_CLASS_HID_59c3] = 124,
- [BNXT_ULP_CLASS_HID_5d1b] = 125,
- [BNXT_ULP_CLASS_HID_256f] = 126,
- [BNXT_ULP_CLASS_HID_4937] = 127,
- [BNXT_ULP_CLASS_HID_111b] = 128,
- [BNXT_ULP_CLASS_HID_25f4b] = 129,
- [BNXT_ULP_CLASS_HID_2275f] = 130,
- [BNXT_ULP_CLASS_HID_24b67] = 131,
- [BNXT_ULP_CLASS_HID_2134b] = 132,
- [BNXT_ULP_CLASS_HID_21683] = 133,
- [BNXT_ULP_CLASS_HID_2475b] = 134,
- [BNXT_ULP_CLASS_HID_202bf] = 135,
- [BNXT_ULP_CLASS_HID_23377] = 136,
- [BNXT_ULP_CLASS_HID_119db] = 137,
- [BNXT_ULP_CLASS_HID_14a93] = 138,
- [BNXT_ULP_CLASS_HID_105f7] = 139,
- [BNXT_ULP_CLASS_HID_1368f] = 140,
- [BNXT_ULP_CLASS_HID_139c7] = 141,
- [BNXT_ULP_CLASS_HID_1022b] = 142,
- [BNXT_ULP_CLASS_HID_125f3] = 143,
- [BNXT_ULP_CLASS_HID_1568b] = 144,
- [BNXT_ULP_CLASS_HID_33c37] = 145,
- [BNXT_ULP_CLASS_HID_3041b] = 146,
- [BNXT_ULP_CLASS_HID_32823] = 147,
- [BNXT_ULP_CLASS_HID_358fb] = 148,
- [BNXT_ULP_CLASS_HID_35c33] = 149,
- [BNXT_ULP_CLASS_HID_32407] = 150,
- [BNXT_ULP_CLASS_HID_3482f] = 151,
- [BNXT_ULP_CLASS_HID_31033] = 152,
- [BNXT_ULP_CLASS_HID_3887] = 153,
- [BNXT_ULP_CLASS_HID_00bb] = 154,
- [BNXT_ULP_CLASS_HID_2493] = 155,
- [BNXT_ULP_CLASS_HID_55db] = 156,
- [BNXT_ULP_CLASS_HID_5043] = 157,
- [BNXT_ULP_CLASS_HID_1877] = 158,
- [BNXT_ULP_CLASS_HID_3baf] = 159,
- [BNXT_ULP_CLASS_HID_0443] = 160,
- [BNXT_ULP_CLASS_HID_5883] = 161,
- [BNXT_ULP_CLASS_HID_20b7] = 162,
- [BNXT_ULP_CLASS_HID_44ef] = 163,
- [BNXT_ULP_CLASS_HID_0c83] = 164,
- [BNXT_ULP_CLASS_HID_070b] = 165,
- [BNXT_ULP_CLASS_HID_3873] = 166,
- [BNXT_ULP_CLASS_HID_5bab] = 167,
- [BNXT_ULP_CLASS_HID_245f] = 168,
- [BNXT_ULP_CLASS_HID_142b] = 169,
- [BNXT_ULP_CLASS_HID_4513] = 170,
- [BNXT_ULP_CLASS_HID_0037] = 171,
- [BNXT_ULP_CLASS_HID_317f] = 172,
- [BNXT_ULP_CLASS_HID_2be7] = 173,
- [BNXT_ULP_CLASS_HID_5c2f] = 174,
- [BNXT_ULP_CLASS_HID_17f3] = 175,
- [BNXT_ULP_CLASS_HID_483b] = 176,
- [BNXT_ULP_CLASS_HID_3427] = 177,
- [BNXT_ULP_CLASS_HID_656f] = 178,
- [BNXT_ULP_CLASS_HID_2033] = 179,
- [BNXT_ULP_CLASS_HID_517b] = 180,
- [BNXT_ULP_CLASS_HID_4be3] = 181,
- [BNXT_ULP_CLASS_HID_1397] = 182,
- [BNXT_ULP_CLASS_HID_37cf] = 183,
- [BNXT_ULP_CLASS_HID_6837] = 184,
- [BNXT_ULP_CLASS_HID_3d7f] = 185,
- [BNXT_ULP_CLASS_HID_0503] = 186,
- [BNXT_ULP_CLASS_HID_296b] = 187,
- [BNXT_ULP_CLASS_HID_59a3] = 188,
- [BNXT_ULP_CLASS_HID_5d7b] = 189,
- [BNXT_ULP_CLASS_HID_250f] = 190,
- [BNXT_ULP_CLASS_HID_4957] = 191,
- [BNXT_ULP_CLASS_HID_117b] = 192,
- [BNXT_ULP_CLASS_HID_25f2b] = 193,
- [BNXT_ULP_CLASS_HID_2273f] = 194,
- [BNXT_ULP_CLASS_HID_24b07] = 195,
- [BNXT_ULP_CLASS_HID_2132b] = 196,
- [BNXT_ULP_CLASS_HID_216e3] = 197,
- [BNXT_ULP_CLASS_HID_2473b] = 198,
- [BNXT_ULP_CLASS_HID_202df] = 199,
- [BNXT_ULP_CLASS_HID_23317] = 200,
- [BNXT_ULP_CLASS_HID_119bb] = 201,
- [BNXT_ULP_CLASS_HID_14af3] = 202,
- [BNXT_ULP_CLASS_HID_10597] = 203,
- [BNXT_ULP_CLASS_HID_136ef] = 204,
- [BNXT_ULP_CLASS_HID_139a7] = 205,
- [BNXT_ULP_CLASS_HID_1024b] = 206,
- [BNXT_ULP_CLASS_HID_12593] = 207,
- [BNXT_ULP_CLASS_HID_156eb] = 208,
- [BNXT_ULP_CLASS_HID_33c57] = 209,
- [BNXT_ULP_CLASS_HID_3047b] = 210,
- [BNXT_ULP_CLASS_HID_32843] = 211,
- [BNXT_ULP_CLASS_HID_3589b] = 212,
- [BNXT_ULP_CLASS_HID_35c53] = 213,
- [BNXT_ULP_CLASS_HID_32467] = 214,
- [BNXT_ULP_CLASS_HID_3484f] = 215,
- [BNXT_ULP_CLASS_HID_31053] = 216,
- [BNXT_ULP_CLASS_HID_5ce1] = 217,
- [BNXT_ULP_CLASS_HID_4579] = 218,
- [BNXT_ULP_CLASS_HID_1735] = 219,
- [BNXT_ULP_CLASS_HID_45bd] = 220,
- [BNXT_ULP_CLASS_HID_3feb] = 221,
- [BNXT_ULP_CLASS_HID_2bf7] = 222,
- [BNXT_ULP_CLASS_HID_5727] = 223,
- [BNXT_ULP_CLASS_HID_4333] = 224,
- [BNXT_ULP_CLASS_HID_4453] = 225,
- [BNXT_ULP_CLASS_HID_304f] = 226,
- [BNXT_ULP_CLASS_HID_645f] = 227,
- [BNXT_ULP_CLASS_HID_504b] = 228,
- [BNXT_ULP_CLASS_HID_5cc1] = 229,
- [BNXT_ULP_CLASS_HID_4559] = 230,
- [BNXT_ULP_CLASS_HID_2285] = 231,
- [BNXT_ULP_CLASS_HID_0b1d] = 232,
- [BNXT_ULP_CLASS_HID_0b49] = 233,
- [BNXT_ULP_CLASS_HID_5c95] = 234,
- [BNXT_ULP_CLASS_HID_39c1] = 235,
- [BNXT_ULP_CLASS_HID_2259] = 236,
- [BNXT_ULP_CLASS_HID_1715] = 237,
- [BNXT_ULP_CLASS_HID_459d] = 238,
- [BNXT_ULP_CLASS_HID_571d] = 239,
- [BNXT_ULP_CLASS_HID_1cd1] = 240,
- [BNXT_ULP_CLASS_HID_3711] = 241,
- [BNXT_ULP_CLASS_HID_6599] = 242,
- [BNXT_ULP_CLASS_HID_0e55] = 243,
- [BNXT_ULP_CLASS_HID_3cdd] = 244,
- [BNXT_ULP_CLASS_HID_5ca1] = 245,
- [BNXT_ULP_CLASS_HID_4539] = 246,
- [BNXT_ULP_CLASS_HID_22e5] = 247,
- [BNXT_ULP_CLASS_HID_0b7d] = 248,
- [BNXT_ULP_CLASS_HID_0b29] = 249,
- [BNXT_ULP_CLASS_HID_5cf5] = 250,
- [BNXT_ULP_CLASS_HID_39a1] = 251,
- [BNXT_ULP_CLASS_HID_2239] = 252,
- [BNXT_ULP_CLASS_HID_1775] = 253,
- [BNXT_ULP_CLASS_HID_45fd] = 254,
- [BNXT_ULP_CLASS_HID_577d] = 255,
- [BNXT_ULP_CLASS_HID_1cb1] = 256,
- [BNXT_ULP_CLASS_HID_3771] = 257,
- [BNXT_ULP_CLASS_HID_65f9] = 258,
- [BNXT_ULP_CLASS_HID_0e35] = 259,
- [BNXT_ULP_CLASS_HID_3cbd] = 260,
- [BNXT_ULP_CLASS_HID_3fcb] = 261,
- [BNXT_ULP_CLASS_HID_2bd7] = 262,
- [BNXT_ULP_CLASS_HID_5707] = 263,
- [BNXT_ULP_CLASS_HID_4313] = 264,
- [BNXT_ULP_CLASS_HID_5fc7] = 265,
- [BNXT_ULP_CLASS_HID_4bd3] = 266,
- [BNXT_ULP_CLASS_HID_0e4f] = 267,
- [BNXT_ULP_CLASS_HID_632f] = 268,
- [BNXT_ULP_CLASS_HID_1baf] = 269,
- [BNXT_ULP_CLASS_HID_07bb] = 270,
- [BNXT_ULP_CLASS_HID_32eb] = 271,
- [BNXT_ULP_CLASS_HID_1ef7] = 272,
- [BNXT_ULP_CLASS_HID_3bab] = 273,
- [BNXT_ULP_CLASS_HID_27b7] = 274,
- [BNXT_ULP_CLASS_HID_52e7] = 275,
- [BNXT_ULP_CLASS_HID_3ef3] = 276,
- [BNXT_ULP_CLASS_HID_4473] = 277,
- [BNXT_ULP_CLASS_HID_306f] = 278,
- [BNXT_ULP_CLASS_HID_647f] = 279,
- [BNXT_ULP_CLASS_HID_506b] = 280,
- [BNXT_ULP_CLASS_HID_266af] = 281,
- [BNXT_ULP_CLASS_HID_2525b] = 282,
- [BNXT_ULP_CLASS_HID_21de7] = 283,
- [BNXT_ULP_CLASS_HID_20993] = 284,
- [BNXT_ULP_CLASS_HID_1213f] = 285,
- [BNXT_ULP_CLASS_HID_10d2b] = 286,
- [BNXT_ULP_CLASS_HID_1413b] = 287,
- [BNXT_ULP_CLASS_HID_12cd7] = 288,
- [BNXT_ULP_CLASS_HID_3436b] = 289,
- [BNXT_ULP_CLASS_HID_32f07] = 290,
- [BNXT_ULP_CLASS_HID_36317] = 291,
- [BNXT_ULP_CLASS_HID_34f03] = 292,
- [BNXT_ULP_CLASS_HID_3fab] = 293,
- [BNXT_ULP_CLASS_HID_2bb7] = 294,
- [BNXT_ULP_CLASS_HID_5767] = 295,
- [BNXT_ULP_CLASS_HID_4373] = 296,
- [BNXT_ULP_CLASS_HID_5fa7] = 297,
- [BNXT_ULP_CLASS_HID_4bb3] = 298,
- [BNXT_ULP_CLASS_HID_0e2f] = 299,
- [BNXT_ULP_CLASS_HID_634f] = 300,
- [BNXT_ULP_CLASS_HID_1bcf] = 301,
- [BNXT_ULP_CLASS_HID_07db] = 302,
- [BNXT_ULP_CLASS_HID_328b] = 303,
- [BNXT_ULP_CLASS_HID_1e97] = 304,
- [BNXT_ULP_CLASS_HID_3bcb] = 305,
- [BNXT_ULP_CLASS_HID_27d7] = 306,
- [BNXT_ULP_CLASS_HID_5287] = 307,
- [BNXT_ULP_CLASS_HID_3e93] = 308,
- [BNXT_ULP_CLASS_HID_4413] = 309,
- [BNXT_ULP_CLASS_HID_300f] = 310,
- [BNXT_ULP_CLASS_HID_641f] = 311,
- [BNXT_ULP_CLASS_HID_500b] = 312,
- [BNXT_ULP_CLASS_HID_266cf] = 313,
- [BNXT_ULP_CLASS_HID_2523b] = 314,
- [BNXT_ULP_CLASS_HID_21d87] = 315,
- [BNXT_ULP_CLASS_HID_209f3] = 316,
- [BNXT_ULP_CLASS_HID_1215f] = 317,
- [BNXT_ULP_CLASS_HID_10d4b] = 318,
- [BNXT_ULP_CLASS_HID_1415b] = 319,
- [BNXT_ULP_CLASS_HID_12cb7] = 320,
- [BNXT_ULP_CLASS_HID_3430b] = 321,
- [BNXT_ULP_CLASS_HID_32f67] = 322,
- [BNXT_ULP_CLASS_HID_36377] = 323,
- [BNXT_ULP_CLASS_HID_34f63] = 324,
- [BNXT_ULP_CLASS_HID_29b5] = 325,
- [BNXT_ULP_CLASS_HID_29ad] = 326,
- [BNXT_ULP_CLASS_HID_29b7] = 327,
- [BNXT_ULP_CLASS_HID_1583] = 328,
- [BNXT_ULP_CLASS_HID_29af] = 329,
- [BNXT_ULP_CLASS_HID_159b] = 330,
- [BNXT_ULP_CLASS_HID_2995] = 331,
- [BNXT_ULP_CLASS_HID_298d] = 332,
- [BNXT_ULP_CLASS_HID_29f5] = 333,
- [BNXT_ULP_CLASS_HID_29ed] = 334,
- [BNXT_ULP_CLASS_HID_2997] = 335,
- [BNXT_ULP_CLASS_HID_15a3] = 336,
- [BNXT_ULP_CLASS_HID_298f] = 337,
- [BNXT_ULP_CLASS_HID_15bb] = 338,
- [BNXT_ULP_CLASS_HID_29f7] = 339,
- [BNXT_ULP_CLASS_HID_15c3] = 340,
- [BNXT_ULP_CLASS_HID_29ef] = 341,
- [BNXT_ULP_CLASS_HID_15db] = 342,
- [BNXT_ULP_CLASS_HID_1151] = 343,
- [BNXT_ULP_CLASS_HID_315d] = 344,
- [BNXT_ULP_CLASS_HID_3612] = 345,
- [BNXT_ULP_CLASS_HID_66da] = 346,
- [BNXT_ULP_CLASS_HID_243ca] = 347,
- [BNXT_ULP_CLASS_HID_20d8e] = 348,
- [BNXT_ULP_CLASS_HID_2e082] = 349,
- [BNXT_ULP_CLASS_HID_2ab46] = 350,
- [BNXT_ULP_CLASS_HID_25226] = 351,
- [BNXT_ULP_CLASS_HID_25cea] = 352,
- [BNXT_ULP_CLASS_HID_2c82a] = 353,
- [BNXT_ULP_CLASS_HID_2f9a2] = 354,
- [BNXT_ULP_CLASS_HID_23b56] = 355,
- [BNXT_ULP_CLASS_HID_205da] = 356,
- [BNXT_ULP_CLASS_HID_2d8ce] = 357,
- [BNXT_ULP_CLASS_HID_2a2d2] = 358,
- [BNXT_ULP_CLASS_HID_24a72] = 359,
- [BNXT_ULP_CLASS_HID_25476] = 360,
- [BNXT_ULP_CLASS_HID_2c076] = 361,
- [BNXT_ULP_CLASS_HID_2f1ee] = 362,
- [BNXT_ULP_CLASS_HID_20bb6] = 363,
- [BNXT_ULP_CLASS_HID_23d2e] = 364,
- [BNXT_ULP_CLASS_HID_2a96e] = 365,
- [BNXT_ULP_CLASS_HID_2dae6] = 366,
- [BNXT_ULP_CLASS_HID_25af2] = 367,
- [BNXT_ULP_CLASS_HID_24c6a] = 368,
- [BNXT_ULP_CLASS_HID_2c7aa] = 369,
- [BNXT_ULP_CLASS_HID_2c26e] = 370,
- [BNXT_ULP_CLASS_HID_203e2] = 371,
- [BNXT_ULP_CLASS_HID_2357a] = 372,
- [BNXT_ULP_CLASS_HID_2a0fa] = 373,
- [BNXT_ULP_CLASS_HID_2d272] = 374,
- [BNXT_ULP_CLASS_HID_2527e] = 375,
- [BNXT_ULP_CLASS_HID_243f6] = 376,
- [BNXT_ULP_CLASS_HID_2fff6] = 377,
- [BNXT_ULP_CLASS_HID_2e16e] = 378,
- [BNXT_ULP_CLASS_HID_2422d] = 379,
- [BNXT_ULP_CLASS_HID_20c69] = 380,
- [BNXT_ULP_CLASS_HID_2e165] = 381,
- [BNXT_ULP_CLASS_HID_2aaa1] = 382,
- [BNXT_ULP_CLASS_HID_253c1] = 383,
- [BNXT_ULP_CLASS_HID_25d0d] = 384,
- [BNXT_ULP_CLASS_HID_2c9cd] = 385,
- [BNXT_ULP_CLASS_HID_2f845] = 386,
- [BNXT_ULP_CLASS_HID_25afd] = 387,
- [BNXT_ULP_CLASS_HID_22439] = 388,
- [BNXT_ULP_CLASS_HID_290f9] = 389,
- [BNXT_ULP_CLASS_HID_2c371] = 390,
- [BNXT_ULP_CLASS_HID_24355] = 391,
- [BNXT_ULP_CLASS_HID_275dd] = 392,
- [BNXT_ULP_CLASS_HID_2e19d] = 393,
- [BNXT_ULP_CLASS_HID_2d015] = 394,
- [BNXT_ULP_CLASS_HID_2560d] = 395,
- [BNXT_ULP_CLASS_HID_21049] = 396,
- [BNXT_ULP_CLASS_HID_28c09] = 397,
- [BNXT_ULP_CLASS_HID_2be89] = 398,
- [BNXT_ULP_CLASS_HID_267a9] = 399,
- [BNXT_ULP_CLASS_HID_261ed] = 400,
- [BNXT_ULP_CLASS_HID_2ddad] = 401,
- [BNXT_ULP_CLASS_HID_2cc2d] = 402,
- [BNXT_ULP_CLASS_HID_26edd] = 403,
- [BNXT_ULP_CLASS_HID_22819] = 404,
- [BNXT_ULP_CLASS_HID_2a4d9] = 405,
- [BNXT_ULP_CLASS_HID_2d759] = 406,
- [BNXT_ULP_CLASS_HID_2573d] = 407,
- [BNXT_ULP_CLASS_HID_279bd] = 408,
- [BNXT_ULP_CLASS_HID_2f27d] = 409,
- [BNXT_ULP_CLASS_HID_2e4fd] = 410,
- [BNXT_ULP_CLASS_HID_24fbe] = 411,
- [BNXT_ULP_CLASS_HID_201fa] = 412,
- [BNXT_ULP_CLASS_HID_2ecf6] = 413,
- [BNXT_ULP_CLASS_HID_2a732] = 414,
- [BNXT_ULP_CLASS_HID_25e52] = 415,
- [BNXT_ULP_CLASS_HID_2509e] = 416,
- [BNXT_ULP_CLASS_HID_2c45e] = 417,
- [BNXT_ULP_CLASS_HID_2f5d6] = 418,
- [BNXT_ULP_CLASS_HID_23722] = 419,
- [BNXT_ULP_CLASS_HID_209ae] = 420,
- [BNXT_ULP_CLASS_HID_2d4ba] = 421,
- [BNXT_ULP_CLASS_HID_2aea6] = 422,
- [BNXT_ULP_CLASS_HID_24606] = 423,
- [BNXT_ULP_CLASS_HID_25802] = 424,
- [BNXT_ULP_CLASS_HID_2cc02] = 425,
- [BNXT_ULP_CLASS_HID_2fd9a] = 426,
- [BNXT_ULP_CLASS_HID_207c2] = 427,
- [BNXT_ULP_CLASS_HID_2315a] = 428,
- [BNXT_ULP_CLASS_HID_2a51a] = 429,
- [BNXT_ULP_CLASS_HID_2d692] = 430,
- [BNXT_ULP_CLASS_HID_25686] = 431,
- [BNXT_ULP_CLASS_HID_2401e] = 432,
- [BNXT_ULP_CLASS_HID_2cbde] = 433,
- [BNXT_ULP_CLASS_HID_2ce1a] = 434,
- [BNXT_ULP_CLASS_HID_20f96] = 435,
- [BNXT_ULP_CLASS_HID_2390e] = 436,
- [BNXT_ULP_CLASS_HID_2ac8e] = 437,
- [BNXT_ULP_CLASS_HID_2de06] = 438,
- [BNXT_ULP_CLASS_HID_25e0a] = 439,
- [BNXT_ULP_CLASS_HID_24f82] = 440,
- [BNXT_ULP_CLASS_HID_2f382] = 441,
- [BNXT_ULP_CLASS_HID_2ed1a] = 442,
- [BNXT_ULP_CLASS_HID_2576e] = 443,
- [BNXT_ULP_CLASS_HID_229aa] = 444,
- [BNXT_ULP_CLASS_HID_29d6a] = 445,
- [BNXT_ULP_CLASS_HID_2cee2] = 446,
- [BNXT_ULP_CLASS_HID_24ec6] = 447,
- [BNXT_ULP_CLASS_HID_2784e] = 448,
- [BNXT_ULP_CLASS_HID_2ec0e] = 449,
- [BNXT_ULP_CLASS_HID_2dd86] = 450,
- [BNXT_ULP_CLASS_HID_25f22] = 451,
- [BNXT_ULP_CLASS_HID_2112e] = 452,
- [BNXT_ULP_CLASS_HID_2852e] = 453,
- [BNXT_ULP_CLASS_HID_2b6a6] = 454,
- [BNXT_ULP_CLASS_HID_26d86] = 455,
- [BNXT_ULP_CLASS_HID_26002] = 456,
- [BNXT_ULP_CLASS_HID_2eb82] = 457,
- [BNXT_ULP_CLASS_HID_2c50a] = 458,
- [BNXT_ULP_CLASS_HID_22f82] = 459,
- [BNXT_ULP_CLASS_HID_2590a] = 460,
- [BNXT_ULP_CLASS_HID_2ccca] = 461,
- [BNXT_ULP_CLASS_HID_28706] = 462,
- [BNXT_ULP_CLASS_HID_27e46] = 463,
- [BNXT_ULP_CLASS_HID_26fce] = 464,
- [BNXT_ULP_CLASS_HID_2d38e] = 465,
- [BNXT_ULP_CLASS_HID_2d5ca] = 466,
- [BNXT_ULP_CLASS_HID_21706] = 467,
- [BNXT_ULP_CLASS_HID_2408e] = 468,
- [BNXT_ULP_CLASS_HID_2b48e] = 469,
- [BNXT_ULP_CLASS_HID_28e8a] = 470,
- [BNXT_ULP_CLASS_HID_2660a] = 471,
- [BNXT_ULP_CLASS_HID_25782] = 472,
- [BNXT_ULP_CLASS_HID_2db02] = 473,
- [BNXT_ULP_CLASS_HID_2dd8e] = 474,
- [BNXT_ULP_CLASS_HID_25b9e] = 475,
- [BNXT_ULP_CLASS_HID_21dda] = 476,
- [BNXT_ULP_CLASS_HID_2819a] = 477,
- [BNXT_ULP_CLASS_HID_2b31a] = 478,
- [BNXT_ULP_CLASS_HID_26a3a] = 479,
- [BNXT_ULP_CLASS_HID_26c7e] = 480,
- [BNXT_ULP_CLASS_HID_2d03e] = 481,
- [BNXT_ULP_CLASS_HID_2c1be] = 482,
- [BNXT_ULP_CLASS_HID_2430a] = 483,
- [BNXT_ULP_CLASS_HID_2058e] = 484,
- [BNXT_ULP_CLASS_HID_2890e] = 485,
- [BNXT_ULP_CLASS_HID_2ba8e] = 486,
- [BNXT_ULP_CLASS_HID_251ae] = 487,
- [BNXT_ULP_CLASS_HID_2542a] = 488,
- [BNXT_ULP_CLASS_HID_2dfaa] = 489,
- [BNXT_ULP_CLASS_HID_2c93a] = 490,
- [BNXT_ULP_CLASS_HID_213ca] = 491,
- [BNXT_ULP_CLASS_HID_24d5a] = 492,
- [BNXT_ULP_CLASS_HID_2b11a] = 493,
- [BNXT_ULP_CLASS_HID_28b4e] = 494,
- [BNXT_ULP_CLASS_HID_2624e] = 495,
- [BNXT_ULP_CLASS_HID_253de] = 496,
- [BNXT_ULP_CLASS_HID_2c79e] = 497,
- [BNXT_ULP_CLASS_HID_2d9da] = 498,
- [BNXT_ULP_CLASS_HID_21b1e] = 499,
- [BNXT_ULP_CLASS_HID_2350e] = 500,
- [BNXT_ULP_CLASS_HID_2b88e] = 501,
- [BNXT_ULP_CLASS_HID_2ea0e] = 502,
- [BNXT_ULP_CLASS_HID_26a0a] = 503,
- [BNXT_ULP_CLASS_HID_25b8a] = 504,
- [BNXT_ULP_CLASS_HID_2cf0a] = 505,
- [BNXT_ULP_CLASS_HID_2c18e] = 506,
- [BNXT_ULP_CLASS_HID_2634e] = 507,
- [BNXT_ULP_CLASS_HID_2258a] = 508,
- [BNXT_ULP_CLASS_HID_2a94a] = 509,
- [BNXT_ULP_CLASS_HID_2daca] = 510,
- [BNXT_ULP_CLASS_HID_25aae] = 511,
- [BNXT_ULP_CLASS_HID_2742e] = 512,
- [BNXT_ULP_CLASS_HID_2ffee] = 513,
- [BNXT_ULP_CLASS_HID_2e96e] = 514,
- [BNXT_ULP_CLASS_HID_26b0a] = 515,
- [BNXT_ULP_CLASS_HID_22d0e] = 516,
- [BNXT_ULP_CLASS_HID_2910e] = 517,
- [BNXT_ULP_CLASS_HID_2c28e] = 518,
- [BNXT_ULP_CLASS_HID_2422a] = 519,
- [BNXT_ULP_CLASS_HID_273aa] = 520,
- [BNXT_ULP_CLASS_HID_2e7aa] = 521,
- [BNXT_ULP_CLASS_HID_2d12a] = 522,
- [BNXT_ULP_CLASS_HID_23b8a] = 523,
- [BNXT_ULP_CLASS_HID_2550a] = 524,
- [BNXT_ULP_CLASS_HID_2d8ca] = 525,
- [BNXT_ULP_CLASS_HID_2930e] = 526,
- [BNXT_ULP_CLASS_HID_24a0e] = 527,
- [BNXT_ULP_CLASS_HID_24c4a] = 528,
- [BNXT_ULP_CLASS_HID_2ef4e] = 529,
- [BNXT_ULP_CLASS_HID_2e18a] = 530,
- [BNXT_ULP_CLASS_HID_2230e] = 531,
- [BNXT_ULP_CLASS_HID_25c8e] = 532,
- [BNXT_ULP_CLASS_HID_2c08e] = 533,
- [BNXT_ULP_CLASS_HID_29a8a] = 534,
- [BNXT_ULP_CLASS_HID_2718a] = 535,
- [BNXT_ULP_CLASS_HID_2630a] = 536,
- [BNXT_ULP_CLASS_HID_2d70a] = 537,
- [BNXT_ULP_CLASS_HID_2e90e] = 538,
- [BNXT_ULP_CLASS_HID_24e91] = 539,
- [BNXT_ULP_CLASS_HID_200d5] = 540,
- [BNXT_ULP_CLASS_HID_2edd9] = 541,
- [BNXT_ULP_CLASS_HID_2a61d] = 542,
- [BNXT_ULP_CLASS_HID_25f7d] = 543,
- [BNXT_ULP_CLASS_HID_251b1] = 544,
- [BNXT_ULP_CLASS_HID_2c571] = 545,
- [BNXT_ULP_CLASS_HID_2f4f9] = 546,
- [BNXT_ULP_CLASS_HID_25641] = 547,
- [BNXT_ULP_CLASS_HID_22885] = 548,
- [BNXT_ULP_CLASS_HID_29c45] = 549,
- [BNXT_ULP_CLASS_HID_2cfcd] = 550,
- [BNXT_ULP_CLASS_HID_24fe9] = 551,
- [BNXT_ULP_CLASS_HID_27961] = 552,
- [BNXT_ULP_CLASS_HID_2ed21] = 553,
- [BNXT_ULP_CLASS_HID_2dca9] = 554,
- [BNXT_ULP_CLASS_HID_25ab1] = 555,
- [BNXT_ULP_CLASS_HID_21cf5] = 556,
- [BNXT_ULP_CLASS_HID_280b5] = 557,
- [BNXT_ULP_CLASS_HID_2b235] = 558,
- [BNXT_ULP_CLASS_HID_26b15] = 559,
- [BNXT_ULP_CLASS_HID_26d51] = 560,
- [BNXT_ULP_CLASS_HID_2d111] = 561,
- [BNXT_ULP_CLASS_HID_2c091] = 562,
- [BNXT_ULP_CLASS_HID_26261] = 563,
- [BNXT_ULP_CLASS_HID_224a5] = 564,
- [BNXT_ULP_CLASS_HID_2a865] = 565,
- [BNXT_ULP_CLASS_HID_2dbe5] = 566,
- [BNXT_ULP_CLASS_HID_25b81] = 567,
- [BNXT_ULP_CLASS_HID_27501] = 568,
- [BNXT_ULP_CLASS_HID_2fec1] = 569,
- [BNXT_ULP_CLASS_HID_2e841] = 570,
- [BNXT_ULP_CLASS_HID_24085] = 571,
- [BNXT_ULP_CLASS_HID_21ac5] = 572,
- [BNXT_ULP_CLASS_HID_28e85] = 573,
- [BNXT_ULP_CLASS_HID_2b80d] = 574,
- [BNXT_ULP_CLASS_HID_2516d] = 575,
- [BNXT_ULP_CLASS_HID_26ba5] = 576,
- [BNXT_ULP_CLASS_HID_2df65] = 577,
- [BNXT_ULP_CLASS_HID_2ceed] = 578,
- [BNXT_ULP_CLASS_HID_26845] = 579,
- [BNXT_ULP_CLASS_HID_22285] = 580,
- [BNXT_ULP_CLASS_HID_29645] = 581,
- [BNXT_ULP_CLASS_HID_2c1cd] = 582,
- [BNXT_ULP_CLASS_HID_2418d] = 583,
- [BNXT_ULP_CLASS_HID_27365] = 584,
- [BNXT_ULP_CLASS_HID_2e725] = 585,
- [BNXT_ULP_CLASS_HID_2d6ad] = 586,
- [BNXT_ULP_CLASS_HID_25ca5] = 587,
- [BNXT_ULP_CLASS_HID_216e5] = 588,
- [BNXT_ULP_CLASS_HID_29aa5] = 589,
- [BNXT_ULP_CLASS_HID_2b425] = 590,
- [BNXT_ULP_CLASS_HID_26d05] = 591,
- [BNXT_ULP_CLASS_HID_26745] = 592,
- [BNXT_ULP_CLASS_HID_2eb05] = 593,
- [BNXT_ULP_CLASS_HID_2da85] = 594,
- [BNXT_ULP_CLASS_HID_20cc5] = 595,
- [BNXT_ULP_CLASS_HID_23ea5] = 596,
- [BNXT_ULP_CLASS_HID_2a265] = 597,
- [BNXT_ULP_CLASS_HID_2dde5] = 598,
- [BNXT_ULP_CLASS_HID_25da5] = 599,
- [BNXT_ULP_CLASS_HID_24f05] = 600,
- [BNXT_ULP_CLASS_HID_2f0c5] = 601,
- [BNXT_ULP_CLASS_HID_2e245] = 602,
- [BNXT_ULP_CLASS_HID_24d8b] = 603,
- [BNXT_ULP_CLASS_HID_207cf] = 604,
- [BNXT_ULP_CLASS_HID_28b8f] = 605,
- [BNXT_ULP_CLASS_HID_2a517] = 606,
- [BNXT_ULP_CLASS_HID_25277] = 607,
- [BNXT_ULP_CLASS_HID_254ab] = 608,
- [BNXT_ULP_CLASS_HID_2d86b] = 609,
- [BNXT_ULP_CLASS_HID_2cbf3] = 610,
- [BNXT_ULP_CLASS_HID_2554b] = 611,
- [BNXT_ULP_CLASS_HID_22f8f] = 612,
- [BNXT_ULP_CLASS_HID_2934f] = 613,
- [BNXT_ULP_CLASS_HID_2c2c7] = 614,
- [BNXT_ULP_CLASS_HID_242e3] = 615,
- [BNXT_ULP_CLASS_HID_27c6b] = 616,
- [BNXT_ULP_CLASS_HID_2e02b] = 617,
- [BNXT_ULP_CLASS_HID_2d3a3] = 618,
- [BNXT_ULP_CLASS_HID_259a3] = 619,
- [BNXT_ULP_CLASS_HID_213e7] = 620,
- [BNXT_ULP_CLASS_HID_287a7] = 621,
- [BNXT_ULP_CLASS_HID_2b137] = 622,
- [BNXT_ULP_CLASS_HID_26e17] = 623,
- [BNXT_ULP_CLASS_HID_26043] = 624,
- [BNXT_ULP_CLASS_HID_2d403] = 625,
- [BNXT_ULP_CLASS_HID_2c793] = 626,
- [BNXT_ULP_CLASS_HID_20827] = 627,
- [BNXT_ULP_CLASS_HID_23ba7] = 628,
- [BNXT_ULP_CLASS_HID_2af67] = 629,
- [BNXT_ULP_CLASS_HID_2dee7] = 630,
- [BNXT_ULP_CLASS_HID_25e83] = 631,
- [BNXT_ULP_CLASS_HID_24803] = 632,
- [BNXT_ULP_CLASS_HID_2fdc3] = 633,
- [BNXT_ULP_CLASS_HID_2ef43] = 634,
- [BNXT_ULP_CLASS_HID_247bf] = 635,
- [BNXT_ULP_CLASS_HID_219ff] = 636,
- [BNXT_ULP_CLASS_HID_28dbf] = 637,
- [BNXT_ULP_CLASS_HID_2bf07] = 638,
- [BNXT_ULP_CLASS_HID_25467] = 639,
- [BNXT_ULP_CLASS_HID_26e5f] = 640,
- [BNXT_ULP_CLASS_HID_2d21f] = 641,
- [BNXT_ULP_CLASS_HID_2cde7] = 642,
- [BNXT_ULP_CLASS_HID_26f6f] = 643,
- [BNXT_ULP_CLASS_HID_221af] = 644,
- [BNXT_ULP_CLASS_HID_2956f] = 645,
- [BNXT_ULP_CLASS_HID_2c4c7] = 646,
- [BNXT_ULP_CLASS_HID_24487] = 647,
- [BNXT_ULP_CLASS_HID_2760f] = 648,
- [BNXT_ULP_CLASS_HID_2fbcf] = 649,
- [BNXT_ULP_CLASS_HID_2d5a7] = 650,
- [BNXT_ULP_CLASS_HID_25357] = 651,
- [BNXT_ULP_CLASS_HID_21597] = 652,
- [BNXT_ULP_CLASS_HID_29957] = 653,
- [BNXT_ULP_CLASS_HID_2cb27] = 654,
- [BNXT_ULP_CLASS_HID_248f7] = 655,
- [BNXT_ULP_CLASS_HID_27a77] = 656,
- [BNXT_ULP_CLASS_HID_2ee37] = 657,
- [BNXT_ULP_CLASS_HID_2d987] = 658,
- [BNXT_ULP_CLASS_HID_203c7] = 659,
- [BNXT_ULP_CLASS_HID_23d47] = 660,
- [BNXT_ULP_CLASS_HID_2a107] = 661,
- [BNXT_ULP_CLASS_HID_2d0e7] = 662,
- [BNXT_ULP_CLASS_HID_250a7] = 663,
- [BNXT_ULP_CLASS_HID_24227] = 664,
- [BNXT_ULP_CLASS_HID_2f7e7] = 665,
- [BNXT_ULP_CLASS_HID_2c827] = 666,
- [BNXT_ULP_CLASS_HID_25422] = 667,
- [BNXT_ULP_CLASS_HID_21a66] = 668,
- [BNXT_ULP_CLASS_HID_2f76a] = 669,
- [BNXT_ULP_CLASS_HID_2bcae] = 670,
- [BNXT_ULP_CLASS_HID_245ce] = 671,
- [BNXT_ULP_CLASS_HID_24b02] = 672,
- [BNXT_ULP_CLASS_HID_2dfc2] = 673,
- [BNXT_ULP_CLASS_HID_2ee4a] = 674,
- [BNXT_ULP_CLASS_HID_22cbe] = 675,
- [BNXT_ULP_CLASS_HID_21232] = 676,
- [BNXT_ULP_CLASS_HID_2cf26] = 677,
- [BNXT_ULP_CLASS_HID_2b53a] = 678,
- [BNXT_ULP_CLASS_HID_25d9a] = 679,
- [BNXT_ULP_CLASS_HID_2439e] = 680,
- [BNXT_ULP_CLASS_HID_2d79e] = 681,
- [BNXT_ULP_CLASS_HID_2e606] = 682,
- [BNXT_ULP_CLASS_HID_21c5e] = 683,
- [BNXT_ULP_CLASS_HID_22ac6] = 684,
- [BNXT_ULP_CLASS_HID_2be86] = 685,
- [BNXT_ULP_CLASS_HID_2cd0e] = 686,
- [BNXT_ULP_CLASS_HID_24d1a] = 687,
- [BNXT_ULP_CLASS_HID_25b82] = 688,
- [BNXT_ULP_CLASS_HID_2d042] = 689,
- [BNXT_ULP_CLASS_HID_2d586] = 690,
- [BNXT_ULP_CLASS_HID_2140a] = 691,
- [BNXT_ULP_CLASS_HID_22292] = 692,
- [BNXT_ULP_CLASS_HID_2b712] = 693,
- [BNXT_ULP_CLASS_HID_2c59a] = 694,
- [BNXT_ULP_CLASS_HID_24596] = 695,
- [BNXT_ULP_CLASS_HID_2541e] = 696,
- [BNXT_ULP_CLASS_HID_2e81e] = 697,
- [BNXT_ULP_CLASS_HID_2f686] = 698,
- [BNXT_ULP_CLASS_HID_24cf2] = 699,
- [BNXT_ULP_CLASS_HID_23236] = 700,
- [BNXT_ULP_CLASS_HID_286f6] = 701,
- [BNXT_ULP_CLASS_HID_2d57e] = 702,
- [BNXT_ULP_CLASS_HID_2555a] = 703,
- [BNXT_ULP_CLASS_HID_263d2] = 704,
- [BNXT_ULP_CLASS_HID_2f792] = 705,
- [BNXT_ULP_CLASS_HID_2c61a] = 706,
- [BNXT_ULP_CLASS_HID_244be] = 707,
- [BNXT_ULP_CLASS_HID_20ab2] = 708,
- [BNXT_ULP_CLASS_HID_29eb2] = 709,
- [BNXT_ULP_CLASS_HID_2ad3a] = 710,
- [BNXT_ULP_CLASS_HID_2761a] = 711,
- [BNXT_ULP_CLASS_HID_27b9e] = 712,
- [BNXT_ULP_CLASS_HID_2f01e] = 713,
- [BNXT_ULP_CLASS_HID_2de96] = 714,
- [BNXT_ULP_CLASS_HID_2341e] = 715,
- [BNXT_ULP_CLASS_HID_24296] = 716,
- [BNXT_ULP_CLASS_HID_2d756] = 717,
- [BNXT_ULP_CLASS_HID_29c9a] = 718,
- [BNXT_ULP_CLASS_HID_265da] = 719,
- [BNXT_ULP_CLASS_HID_27452] = 720,
- [BNXT_ULP_CLASS_HID_2c812] = 721,
- [BNXT_ULP_CLASS_HID_2ce56] = 722,
- [BNXT_ULP_CLASS_HID_20c9a] = 723,
- [BNXT_ULP_CLASS_HID_25b12] = 724,
- [BNXT_ULP_CLASS_HID_2af12] = 725,
- [BNXT_ULP_CLASS_HID_29516] = 726,
- [BNXT_ULP_CLASS_HID_27d96] = 727,
- [BNXT_ULP_CLASS_HID_24c1e] = 728,
- [BNXT_ULP_CLASS_HID_2c09e] = 729,
- [BNXT_ULP_CLASS_HID_2c612] = 730,
- [BNXT_ULP_CLASS_HID_24002] = 731,
- [BNXT_ULP_CLASS_HID_20646] = 732,
- [BNXT_ULP_CLASS_HID_29a06] = 733,
- [BNXT_ULP_CLASS_HID_2a886] = 734,
- [BNXT_ULP_CLASS_HID_271a6] = 735,
- [BNXT_ULP_CLASS_HID_277e2] = 736,
- [BNXT_ULP_CLASS_HID_2cba2] = 737,
- [BNXT_ULP_CLASS_HID_2da22] = 738,
- [BNXT_ULP_CLASS_HID_25896] = 739,
- [BNXT_ULP_CLASS_HID_21e12] = 740,
- [BNXT_ULP_CLASS_HID_29292] = 741,
- [BNXT_ULP_CLASS_HID_2a112] = 742,
- [BNXT_ULP_CLASS_HID_24a32] = 743,
- [BNXT_ULP_CLASS_HID_24fb6] = 744,
- [BNXT_ULP_CLASS_HID_2c436] = 745,
- [BNXT_ULP_CLASS_HID_2d2a6] = 746,
- [BNXT_ULP_CLASS_HID_20856] = 747,
- [BNXT_ULP_CLASS_HID_256c6] = 748,
- [BNXT_ULP_CLASS_HID_2aa86] = 749,
- [BNXT_ULP_CLASS_HID_290d2] = 750,
- [BNXT_ULP_CLASS_HID_279d2] = 751,
- [BNXT_ULP_CLASS_HID_24842] = 752,
- [BNXT_ULP_CLASS_HID_2dc02] = 753,
- [BNXT_ULP_CLASS_HID_2c246] = 754,
- [BNXT_ULP_CLASS_HID_20082] = 755,
- [BNXT_ULP_CLASS_HID_22e92] = 756,
- [BNXT_ULP_CLASS_HID_2a312] = 757,
- [BNXT_ULP_CLASS_HID_2f192] = 758,
- [BNXT_ULP_CLASS_HID_27196] = 759,
- [BNXT_ULP_CLASS_HID_24016] = 760,
- [BNXT_ULP_CLASS_HID_2d496] = 761,
- [BNXT_ULP_CLASS_HID_2da12] = 762,
- [BNXT_ULP_CLASS_HID_278d2] = 763,
- [BNXT_ULP_CLASS_HID_23e16] = 764,
- [BNXT_ULP_CLASS_HID_2b2d6] = 765,
- [BNXT_ULP_CLASS_HID_2c156] = 766,
- [BNXT_ULP_CLASS_HID_24132] = 767,
- [BNXT_ULP_CLASS_HID_26fb2] = 768,
- [BNXT_ULP_CLASS_HID_2e472] = 769,
- [BNXT_ULP_CLASS_HID_2f2f2] = 770,
- [BNXT_ULP_CLASS_HID_27096] = 771,
- [BNXT_ULP_CLASS_HID_23692] = 772,
- [BNXT_ULP_CLASS_HID_28a92] = 773,
- [BNXT_ULP_CLASS_HID_2d912] = 774,
- [BNXT_ULP_CLASS_HID_259b6] = 775,
- [BNXT_ULP_CLASS_HID_26836] = 776,
- [BNXT_ULP_CLASS_HID_2fc36] = 777,
- [BNXT_ULP_CLASS_HID_2cab6] = 778,
- [BNXT_ULP_CLASS_HID_22016] = 779,
- [BNXT_ULP_CLASS_HID_24e96] = 780,
- [BNXT_ULP_CLASS_HID_2c356] = 781,
- [BNXT_ULP_CLASS_HID_28892] = 782,
- [BNXT_ULP_CLASS_HID_25192] = 783,
- [BNXT_ULP_CLASS_HID_257d6] = 784,
- [BNXT_ULP_CLASS_HID_2f4d2] = 785,
- [BNXT_ULP_CLASS_HID_2fa16] = 786,
- [BNXT_ULP_CLASS_HID_23892] = 787,
- [BNXT_ULP_CLASS_HID_24712] = 788,
- [BNXT_ULP_CLASS_HID_2db12] = 789,
- [BNXT_ULP_CLASS_HID_28116] = 790,
- [BNXT_ULP_CLASS_HID_26a16] = 791,
- [BNXT_ULP_CLASS_HID_27896] = 792,
- [BNXT_ULP_CLASS_HID_2cc96] = 793,
- [BNXT_ULP_CLASS_HID_2f292] = 794,
- [BNXT_ULP_CLASS_HID_24b05] = 795,
- [BNXT_ULP_CLASS_HID_20541] = 796,
- [BNXT_ULP_CLASS_HID_2e84d] = 797,
- [BNXT_ULP_CLASS_HID_2a389] = 798,
- [BNXT_ULP_CLASS_HID_25ae9] = 799,
- [BNXT_ULP_CLASS_HID_25425] = 800,
- [BNXT_ULP_CLASS_HID_2c0e5] = 801,
- [BNXT_ULP_CLASS_HID_2f16d] = 802,
- [BNXT_ULP_CLASS_HID_253d5] = 803,
- [BNXT_ULP_CLASS_HID_22d11] = 804,
- [BNXT_ULP_CLASS_HID_299d1] = 805,
- [BNXT_ULP_CLASS_HID_2ca59] = 806,
- [BNXT_ULP_CLASS_HID_24a7d] = 807,
- [BNXT_ULP_CLASS_HID_27cf5] = 808,
- [BNXT_ULP_CLASS_HID_2e8b5] = 809,
- [BNXT_ULP_CLASS_HID_2d93d] = 810,
- [BNXT_ULP_CLASS_HID_25f25] = 811,
- [BNXT_ULP_CLASS_HID_21961] = 812,
- [BNXT_ULP_CLASS_HID_28521] = 813,
- [BNXT_ULP_CLASS_HID_2b7a1] = 814,
- [BNXT_ULP_CLASS_HID_26e81] = 815,
- [BNXT_ULP_CLASS_HID_268c5] = 816,
- [BNXT_ULP_CLASS_HID_2d485] = 817,
- [BNXT_ULP_CLASS_HID_2c505] = 818,
- [BNXT_ULP_CLASS_HID_267f5] = 819,
- [BNXT_ULP_CLASS_HID_22131] = 820,
- [BNXT_ULP_CLASS_HID_2adf1] = 821,
- [BNXT_ULP_CLASS_HID_2de71] = 822,
- [BNXT_ULP_CLASS_HID_25e15] = 823,
- [BNXT_ULP_CLASS_HID_27095] = 824,
- [BNXT_ULP_CLASS_HID_2fb55] = 825,
- [BNXT_ULP_CLASS_HID_2edd5] = 826,
- [BNXT_ULP_CLASS_HID_24511] = 827,
- [BNXT_ULP_CLASS_HID_21f51] = 828,
- [BNXT_ULP_CLASS_HID_28b11] = 829,
- [BNXT_ULP_CLASS_HID_2bd99] = 830,
- [BNXT_ULP_CLASS_HID_254f9] = 831,
- [BNXT_ULP_CLASS_HID_26e31] = 832,
- [BNXT_ULP_CLASS_HID_2daf1] = 833,
- [BNXT_ULP_CLASS_HID_2cb79] = 834,
- [BNXT_ULP_CLASS_HID_26dd1] = 835,
- [BNXT_ULP_CLASS_HID_22711] = 836,
- [BNXT_ULP_CLASS_HID_293d1] = 837,
- [BNXT_ULP_CLASS_HID_2c459] = 838,
- [BNXT_ULP_CLASS_HID_24419] = 839,
- [BNXT_ULP_CLASS_HID_276f1] = 840,
- [BNXT_ULP_CLASS_HID_2e2b1] = 841,
- [BNXT_ULP_CLASS_HID_2d339] = 842,
- [BNXT_ULP_CLASS_HID_25931] = 843,
- [BNXT_ULP_CLASS_HID_21371] = 844,
- [BNXT_ULP_CLASS_HID_29f31] = 845,
- [BNXT_ULP_CLASS_HID_2b1b1] = 846,
- [BNXT_ULP_CLASS_HID_26891] = 847,
- [BNXT_ULP_CLASS_HID_262d1] = 848,
- [BNXT_ULP_CLASS_HID_2ee91] = 849,
- [BNXT_ULP_CLASS_HID_2df11] = 850,
- [BNXT_ULP_CLASS_HID_20951] = 851,
- [BNXT_ULP_CLASS_HID_23b31] = 852,
- [BNXT_ULP_CLASS_HID_2a7f1] = 853,
- [BNXT_ULP_CLASS_HID_2d871] = 854,
- [BNXT_ULP_CLASS_HID_25831] = 855,
- [BNXT_ULP_CLASS_HID_24a91] = 856,
- [BNXT_ULP_CLASS_HID_2f551] = 857,
- [BNXT_ULP_CLASS_HID_2e7d1] = 858,
- [BNXT_ULP_CLASS_HID_2481f] = 859,
- [BNXT_ULP_CLASS_HID_2025b] = 860,
- [BNXT_ULP_CLASS_HID_28e1b] = 861,
- [BNXT_ULP_CLASS_HID_2a083] = 862,
- [BNXT_ULP_CLASS_HID_257e3] = 863,
- [BNXT_ULP_CLASS_HID_2513f] = 864,
- [BNXT_ULP_CLASS_HID_2ddff] = 865,
- [BNXT_ULP_CLASS_HID_2ce67] = 866,
- [BNXT_ULP_CLASS_HID_250df] = 867,
- [BNXT_ULP_CLASS_HID_22a1b] = 868,
- [BNXT_ULP_CLASS_HID_296db] = 869,
- [BNXT_ULP_CLASS_HID_2c753] = 870,
- [BNXT_ULP_CLASS_HID_24777] = 871,
- [BNXT_ULP_CLASS_HID_279ff] = 872,
- [BNXT_ULP_CLASS_HID_2e5bf] = 873,
- [BNXT_ULP_CLASS_HID_2d637] = 874,
- [BNXT_ULP_CLASS_HID_25c37] = 875,
- [BNXT_ULP_CLASS_HID_21673] = 876,
- [BNXT_ULP_CLASS_HID_28233] = 877,
- [BNXT_ULP_CLASS_HID_2b4a3] = 878,
- [BNXT_ULP_CLASS_HID_26b83] = 879,
- [BNXT_ULP_CLASS_HID_265d7] = 880,
- [BNXT_ULP_CLASS_HID_2d197] = 881,
- [BNXT_ULP_CLASS_HID_2c207] = 882,
- [BNXT_ULP_CLASS_HID_20db3] = 883,
- [BNXT_ULP_CLASS_HID_23e33] = 884,
- [BNXT_ULP_CLASS_HID_2aaf3] = 885,
- [BNXT_ULP_CLASS_HID_2db73] = 886,
- [BNXT_ULP_CLASS_HID_25b17] = 887,
- [BNXT_ULP_CLASS_HID_24d97] = 888,
- [BNXT_ULP_CLASS_HID_2f857] = 889,
- [BNXT_ULP_CLASS_HID_2ead7] = 890,
- [BNXT_ULP_CLASS_HID_2422b] = 891,
- [BNXT_ULP_CLASS_HID_21c6b] = 892,
- [BNXT_ULP_CLASS_HID_2882b] = 893,
- [BNXT_ULP_CLASS_HID_2ba93] = 894,
- [BNXT_ULP_CLASS_HID_251f3] = 895,
- [BNXT_ULP_CLASS_HID_26bcb] = 896,
- [BNXT_ULP_CLASS_HID_2d78b] = 897,
- [BNXT_ULP_CLASS_HID_2c873] = 898,
- [BNXT_ULP_CLASS_HID_26afb] = 899,
- [BNXT_ULP_CLASS_HID_2243b] = 900,
- [BNXT_ULP_CLASS_HID_290fb] = 901,
- [BNXT_ULP_CLASS_HID_2c153] = 902,
- [BNXT_ULP_CLASS_HID_24113] = 903,
- [BNXT_ULP_CLASS_HID_2739b] = 904,
- [BNXT_ULP_CLASS_HID_2fe5b] = 905,
- [BNXT_ULP_CLASS_HID_2d033] = 906,
- [BNXT_ULP_CLASS_HID_256c3] = 907,
- [BNXT_ULP_CLASS_HID_21003] = 908,
- [BNXT_ULP_CLASS_HID_29cc3] = 909,
- [BNXT_ULP_CLASS_HID_2ceb3] = 910,
- [BNXT_ULP_CLASS_HID_24d63] = 911,
- [BNXT_ULP_CLASS_HID_27fe3] = 912,
- [BNXT_ULP_CLASS_HID_2eba3] = 913,
- [BNXT_ULP_CLASS_HID_2dc13] = 914,
- [BNXT_ULP_CLASS_HID_20653] = 915,
- [BNXT_ULP_CLASS_HID_238d3] = 916,
- [BNXT_ULP_CLASS_HID_2a493] = 917,
- [BNXT_ULP_CLASS_HID_2d573] = 918,
- [BNXT_ULP_CLASS_HID_25533] = 919,
- [BNXT_ULP_CLASS_HID_247b3] = 920,
- [BNXT_ULP_CLASS_HID_2f273] = 921,
- [BNXT_ULP_CLASS_HID_2cdb3] = 922,
- [BNXT_ULP_CLASS_HID_25c7d] = 923,
- [BNXT_ULP_CLASS_HID_21239] = 924,
- [BNXT_ULP_CLASS_HID_2ff35] = 925,
- [BNXT_ULP_CLASS_HID_2b4f1] = 926,
- [BNXT_ULP_CLASS_HID_24d91] = 927,
- [BNXT_ULP_CLASS_HID_2435d] = 928,
- [BNXT_ULP_CLASS_HID_2d79d] = 929,
- [BNXT_ULP_CLASS_HID_2e615] = 930,
- [BNXT_ULP_CLASS_HID_244ad] = 931,
- [BNXT_ULP_CLASS_HID_23a69] = 932,
- [BNXT_ULP_CLASS_HID_28ea9] = 933,
- [BNXT_ULP_CLASS_HID_2dd21] = 934,
- [BNXT_ULP_CLASS_HID_25d05] = 935,
- [BNXT_ULP_CLASS_HID_26b8d] = 936,
- [BNXT_ULP_CLASS_HID_2ffcd] = 937,
- [BNXT_ULP_CLASS_HID_2ce45] = 938,
- [BNXT_ULP_CLASS_HID_2485d] = 939,
- [BNXT_ULP_CLASS_HID_20e19] = 940,
- [BNXT_ULP_CLASS_HID_29259] = 941,
- [BNXT_ULP_CLASS_HID_2a0d9] = 942,
- [BNXT_ULP_CLASS_HID_279f9] = 943,
- [BNXT_ULP_CLASS_HID_27fbd] = 944,
- [BNXT_ULP_CLASS_HID_2c3fd] = 945,
- [BNXT_ULP_CLASS_HID_2d27d] = 946,
- [BNXT_ULP_CLASS_HID_2708d] = 947,
- [BNXT_ULP_CLASS_HID_23649] = 948,
- [BNXT_ULP_CLASS_HID_2ba89] = 949,
- [BNXT_ULP_CLASS_HID_2c909] = 950,
- [BNXT_ULP_CLASS_HID_2496d] = 951,
- [BNXT_ULP_CLASS_HID_267ed] = 952,
- [BNXT_ULP_CLASS_HID_2ec2d] = 953,
- [BNXT_ULP_CLASS_HID_2faad] = 954,
- [BNXT_ULP_CLASS_HID_34c6] = 955,
- [BNXT_ULP_CLASS_HID_0c22] = 956,
- [BNXT_ULP_CLASS_HID_1cbe] = 957,
- [BNXT_ULP_CLASS_HID_179a] = 958,
- [BNXT_ULP_CLASS_HID_59be] = 959,
- [BNXT_ULP_CLASS_HID_515a] = 960,
- [BNXT_ULP_CLASS_HID_1c72] = 961,
- [BNXT_ULP_CLASS_HID_171e] = 962,
- [BNXT_ULP_CLASS_HID_19c8] = 963,
- [BNXT_ULP_CLASS_HID_112c] = 964,
- [BNXT_ULP_CLASS_HID_4d68] = 965,
- [BNXT_ULP_CLASS_HID_444c] = 966,
- [BNXT_ULP_CLASS_HID_0e8c] = 967,
- [BNXT_ULP_CLASS_HID_09e0] = 968,
- [BNXT_ULP_CLASS_HID_1af0] = 969,
- [BNXT_ULP_CLASS_HID_15d4] = 970,
- [BNXT_ULP_CLASS_HID_1dd0] = 971,
- [BNXT_ULP_CLASS_HID_14f4] = 972,
- [BNXT_ULP_CLASS_HID_70b0] = 973,
- [BNXT_ULP_CLASS_HID_4854] = 974,
- [BNXT_ULP_CLASS_HID_3dd4] = 975,
- [BNXT_ULP_CLASS_HID_34f8] = 976,
- [BNXT_ULP_CLASS_HID_09e8] = 977,
- [BNXT_ULP_CLASS_HID_008c] = 978,
- [BNXT_ULP_CLASS_HID_34e6] = 979,
- [BNXT_ULP_CLASS_HID_0c02] = 980,
- [BNXT_ULP_CLASS_HID_1c9e] = 981,
- [BNXT_ULP_CLASS_HID_17ba] = 982,
- [BNXT_ULP_CLASS_HID_429e] = 983,
- [BNXT_ULP_CLASS_HID_5dba] = 984,
- [BNXT_ULP_CLASS_HID_2a16] = 985,
- [BNXT_ULP_CLASS_HID_2532] = 986,
- [BNXT_ULP_CLASS_HID_2da2] = 987,
- [BNXT_ULP_CLASS_HID_24fe] = 988,
- [BNXT_ULP_CLASS_HID_355a] = 989,
- [BNXT_ULP_CLASS_HID_0c76] = 990,
- [BNXT_ULP_CLASS_HID_13e6] = 991,
- [BNXT_ULP_CLASS_HID_7276] = 992,
- [BNXT_ULP_CLASS_HID_42d2] = 993,
- [BNXT_ULP_CLASS_HID_5dee] = 994,
- [BNXT_ULP_CLASS_HID_59de] = 995,
- [BNXT_ULP_CLASS_HID_513a] = 996,
- [BNXT_ULP_CLASS_HID_1c12] = 997,
- [BNXT_ULP_CLASS_HID_177e] = 998,
- [BNXT_ULP_CLASS_HID_0e92] = 999,
- [BNXT_ULP_CLASS_HID_09fe] = 1000,
- [BNXT_ULP_CLASS_HID_5c1a] = 1001,
- [BNXT_ULP_CLASS_HID_5746] = 1002,
- [BNXT_ULP_CLASS_HID_79da] = 1003,
- [BNXT_ULP_CLASS_HID_7106] = 1004,
- [BNXT_ULP_CLASS_HID_3c1e] = 1005,
- [BNXT_ULP_CLASS_HID_377a] = 1006,
- [BNXT_ULP_CLASS_HID_2e9e] = 1007,
- [BNXT_ULP_CLASS_HID_29fa] = 1008,
- [BNXT_ULP_CLASS_HID_14d2] = 1009,
- [BNXT_ULP_CLASS_HID_7742] = 1010,
- [BNXT_ULP_CLASS_HID_3706] = 1011,
- [BNXT_ULP_CLASS_HID_0fe2] = 1012,
- [BNXT_ULP_CLASS_HID_1f7e] = 1013,
- [BNXT_ULP_CLASS_HID_145a] = 1014,
- [BNXT_ULP_CLASS_HID_417e] = 1015,
- [BNXT_ULP_CLASS_HID_5e5a] = 1016,
- [BNXT_ULP_CLASS_HID_29f6] = 1017,
- [BNXT_ULP_CLASS_HID_26d2] = 1018,
- [BNXT_ULP_CLASS_HID_2e42] = 1019,
- [BNXT_ULP_CLASS_HID_271e] = 1020,
- [BNXT_ULP_CLASS_HID_36ba] = 1021,
- [BNXT_ULP_CLASS_HID_0f96] = 1022,
- [BNXT_ULP_CLASS_HID_1006] = 1023,
- [BNXT_ULP_CLASS_HID_7196] = 1024,
- [BNXT_ULP_CLASS_HID_4132] = 1025,
- [BNXT_ULP_CLASS_HID_5e0e] = 1026,
- [BNXT_ULP_CLASS_HID_59fe] = 1027,
- [BNXT_ULP_CLASS_HID_511a] = 1028,
- [BNXT_ULP_CLASS_HID_1c32] = 1029,
- [BNXT_ULP_CLASS_HID_175e] = 1030,
- [BNXT_ULP_CLASS_HID_0eb2] = 1031,
- [BNXT_ULP_CLASS_HID_09de] = 1032,
- [BNXT_ULP_CLASS_HID_5c3a] = 1033,
- [BNXT_ULP_CLASS_HID_5766] = 1034,
- [BNXT_ULP_CLASS_HID_79fa] = 1035,
- [BNXT_ULP_CLASS_HID_7126] = 1036,
- [BNXT_ULP_CLASS_HID_3c3e] = 1037,
- [BNXT_ULP_CLASS_HID_375a] = 1038,
- [BNXT_ULP_CLASS_HID_2ebe] = 1039,
- [BNXT_ULP_CLASS_HID_29da] = 1040,
- [BNXT_ULP_CLASS_HID_14f2] = 1041,
- [BNXT_ULP_CLASS_HID_7762] = 1042,
- [BNXT_ULP_CLASS_HID_19e8] = 1043,
- [BNXT_ULP_CLASS_HID_110c] = 1044,
- [BNXT_ULP_CLASS_HID_4d48] = 1045,
- [BNXT_ULP_CLASS_HID_446c] = 1046,
- [BNXT_ULP_CLASS_HID_0eac] = 1047,
- [BNXT_ULP_CLASS_HID_09c0] = 1048,
- [BNXT_ULP_CLASS_HID_1ad0] = 1049,
- [BNXT_ULP_CLASS_HID_15f4] = 1050,
- [BNXT_ULP_CLASS_HID_39ec] = 1051,
- [BNXT_ULP_CLASS_HID_3100] = 1052,
- [BNXT_ULP_CLASS_HID_0210] = 1053,
- [BNXT_ULP_CLASS_HID_1d34] = 1054,
- [BNXT_ULP_CLASS_HID_2ea0] = 1055,
- [BNXT_ULP_CLASS_HID_29c4] = 1056,
- [BNXT_ULP_CLASS_HID_3ad4] = 1057,
- [BNXT_ULP_CLASS_HID_35e8] = 1058,
- [BNXT_ULP_CLASS_HID_5d80] = 1059,
- [BNXT_ULP_CLASS_HID_54a4] = 1060,
- [BNXT_ULP_CLASS_HID_29b4] = 1061,
- [BNXT_ULP_CLASS_HID_20c8] = 1062,
- [BNXT_ULP_CLASS_HID_7244] = 1063,
- [BNXT_ULP_CLASS_HID_4d98] = 1064,
- [BNXT_ULP_CLASS_HID_5e68] = 1065,
- [BNXT_ULP_CLASS_HID_598c] = 1066,
- [BNXT_ULP_CLASS_HID_1248] = 1067,
- [BNXT_ULP_CLASS_HID_74d8] = 1068,
- [BNXT_ULP_CLASS_HID_49a8] = 1069,
- [BNXT_ULP_CLASS_HID_40cc] = 1070,
- [BNXT_ULP_CLASS_HID_0b0c] = 1071,
- [BNXT_ULP_CLASS_HID_0220] = 1072,
- [BNXT_ULP_CLASS_HID_1730] = 1073,
- [BNXT_ULP_CLASS_HID_7980] = 1074,
- [BNXT_ULP_CLASS_HID_1db0] = 1075,
- [BNXT_ULP_CLASS_HID_1494] = 1076,
- [BNXT_ULP_CLASS_HID_70d0] = 1077,
- [BNXT_ULP_CLASS_HID_4834] = 1078,
- [BNXT_ULP_CLASS_HID_3db4] = 1079,
- [BNXT_ULP_CLASS_HID_3498] = 1080,
- [BNXT_ULP_CLASS_HID_0988] = 1081,
- [BNXT_ULP_CLASS_HID_00ec] = 1082,
- [BNXT_ULP_CLASS_HID_23f44] = 1083,
- [BNXT_ULP_CLASS_HID_236a8] = 1084,
- [BNXT_ULP_CLASS_HID_20b58] = 1085,
- [BNXT_ULP_CLASS_HID_202bc] = 1086,
- [BNXT_ULP_CLASS_HID_25f48] = 1087,
- [BNXT_ULP_CLASS_HID_256ac] = 1088,
- [BNXT_ULP_CLASS_HID_22b5c] = 1089,
- [BNXT_ULP_CLASS_HID_22280] = 1090,
- [BNXT_ULP_CLASS_HID_14000] = 1091,
- [BNXT_ULP_CLASS_HID_15b64] = 1092,
- [BNXT_ULP_CLASS_HID_12c14] = 1093,
- [BNXT_ULP_CLASS_HID_12778] = 1094,
- [BNXT_ULP_CLASS_HID_118f8] = 1095,
- [BNXT_ULP_CLASS_HID_113dc] = 1096,
- [BNXT_ULP_CLASS_HID_14c18] = 1097,
- [BNXT_ULP_CLASS_HID_1477c] = 1098,
- [BNXT_ULP_CLASS_HID_31a88] = 1099,
- [BNXT_ULP_CLASS_HID_315ec] = 1100,
- [BNXT_ULP_CLASS_HID_34e28] = 1101,
- [BNXT_ULP_CLASS_HID_3490c] = 1102,
- [BNXT_ULP_CLASS_HID_33a8c] = 1103,
- [BNXT_ULP_CLASS_HID_335f0] = 1104,
- [BNXT_ULP_CLASS_HID_306e0] = 1105,
- [BNXT_ULP_CLASS_HID_301c4] = 1106,
- [BNXT_ULP_CLASS_HID_1a08] = 1107,
- [BNXT_ULP_CLASS_HID_12ec] = 1108,
- [BNXT_ULP_CLASS_HID_4ea8] = 1109,
- [BNXT_ULP_CLASS_HID_478c] = 1110,
- [BNXT_ULP_CLASS_HID_0d4c] = 1111,
- [BNXT_ULP_CLASS_HID_0a20] = 1112,
- [BNXT_ULP_CLASS_HID_1930] = 1113,
- [BNXT_ULP_CLASS_HID_1614] = 1114,
- [BNXT_ULP_CLASS_HID_3a0c] = 1115,
- [BNXT_ULP_CLASS_HID_32e0] = 1116,
- [BNXT_ULP_CLASS_HID_01f0] = 1117,
- [BNXT_ULP_CLASS_HID_1ed4] = 1118,
- [BNXT_ULP_CLASS_HID_2d40] = 1119,
- [BNXT_ULP_CLASS_HID_2a24] = 1120,
- [BNXT_ULP_CLASS_HID_3934] = 1121,
- [BNXT_ULP_CLASS_HID_3608] = 1122,
- [BNXT_ULP_CLASS_HID_5e60] = 1123,
- [BNXT_ULP_CLASS_HID_5744] = 1124,
- [BNXT_ULP_CLASS_HID_2a54] = 1125,
- [BNXT_ULP_CLASS_HID_2328] = 1126,
- [BNXT_ULP_CLASS_HID_71a4] = 1127,
- [BNXT_ULP_CLASS_HID_4e78] = 1128,
- [BNXT_ULP_CLASS_HID_5d88] = 1129,
- [BNXT_ULP_CLASS_HID_5a6c] = 1130,
- [BNXT_ULP_CLASS_HID_11a8] = 1131,
- [BNXT_ULP_CLASS_HID_7738] = 1132,
- [BNXT_ULP_CLASS_HID_4a48] = 1133,
- [BNXT_ULP_CLASS_HID_432c] = 1134,
- [BNXT_ULP_CLASS_HID_08ec] = 1135,
- [BNXT_ULP_CLASS_HID_01c0] = 1136,
- [BNXT_ULP_CLASS_HID_14d0] = 1137,
- [BNXT_ULP_CLASS_HID_7a60] = 1138,
- [BNXT_ULP_CLASS_HID_1d90] = 1139,
- [BNXT_ULP_CLASS_HID_14b4] = 1140,
- [BNXT_ULP_CLASS_HID_70f0] = 1141,
- [BNXT_ULP_CLASS_HID_4814] = 1142,
- [BNXT_ULP_CLASS_HID_3d94] = 1143,
- [BNXT_ULP_CLASS_HID_34b8] = 1144,
- [BNXT_ULP_CLASS_HID_09a8] = 1145,
- [BNXT_ULP_CLASS_HID_00cc] = 1146,
- [BNXT_ULP_CLASS_HID_23f64] = 1147,
- [BNXT_ULP_CLASS_HID_23688] = 1148,
- [BNXT_ULP_CLASS_HID_20b78] = 1149,
- [BNXT_ULP_CLASS_HID_2029c] = 1150,
- [BNXT_ULP_CLASS_HID_25f68] = 1151,
- [BNXT_ULP_CLASS_HID_2568c] = 1152,
- [BNXT_ULP_CLASS_HID_22b7c] = 1153,
- [BNXT_ULP_CLASS_HID_222a0] = 1154,
- [BNXT_ULP_CLASS_HID_14020] = 1155,
- [BNXT_ULP_CLASS_HID_15b44] = 1156,
- [BNXT_ULP_CLASS_HID_12c34] = 1157,
- [BNXT_ULP_CLASS_HID_12758] = 1158,
- [BNXT_ULP_CLASS_HID_118d8] = 1159,
- [BNXT_ULP_CLASS_HID_113fc] = 1160,
- [BNXT_ULP_CLASS_HID_14c38] = 1161,
- [BNXT_ULP_CLASS_HID_1475c] = 1162,
- [BNXT_ULP_CLASS_HID_31aa8] = 1163,
- [BNXT_ULP_CLASS_HID_315cc] = 1164,
- [BNXT_ULP_CLASS_HID_34e08] = 1165,
- [BNXT_ULP_CLASS_HID_3492c] = 1166,
- [BNXT_ULP_CLASS_HID_33aac] = 1167,
- [BNXT_ULP_CLASS_HID_335d0] = 1168,
- [BNXT_ULP_CLASS_HID_306c0] = 1169,
- [BNXT_ULP_CLASS_HID_301e4] = 1170,
- [BNXT_ULP_CLASS_HID_4d32] = 1171,
- [BNXT_ULP_CLASS_HID_54aa] = 1172,
- [BNXT_ULP_CLASS_HID_0686] = 1173,
- [BNXT_ULP_CLASS_HID_540e] = 1174,
- [BNXT_ULP_CLASS_HID_2e3c] = 1175,
- [BNXT_ULP_CLASS_HID_3a20] = 1176,
- [BNXT_ULP_CLASS_HID_46f0] = 1177,
- [BNXT_ULP_CLASS_HID_52e4] = 1178,
- [BNXT_ULP_CLASS_HID_55e4] = 1179,
- [BNXT_ULP_CLASS_HID_21f8] = 1180,
- [BNXT_ULP_CLASS_HID_75e8] = 1181,
- [BNXT_ULP_CLASS_HID_41fc] = 1182,
- [BNXT_ULP_CLASS_HID_4d12] = 1183,
- [BNXT_ULP_CLASS_HID_548a] = 1184,
- [BNXT_ULP_CLASS_HID_3356] = 1185,
- [BNXT_ULP_CLASS_HID_1ace] = 1186,
- [BNXT_ULP_CLASS_HID_1a9a] = 1187,
- [BNXT_ULP_CLASS_HID_4d46] = 1188,
- [BNXT_ULP_CLASS_HID_2812] = 1189,
- [BNXT_ULP_CLASS_HID_338a] = 1190,
- [BNXT_ULP_CLASS_HID_06e6] = 1191,
- [BNXT_ULP_CLASS_HID_546e] = 1192,
- [BNXT_ULP_CLASS_HID_46ee] = 1193,
- [BNXT_ULP_CLASS_HID_0d22] = 1194,
- [BNXT_ULP_CLASS_HID_26e2] = 1195,
- [BNXT_ULP_CLASS_HID_746a] = 1196,
- [BNXT_ULP_CLASS_HID_1fa6] = 1197,
- [BNXT_ULP_CLASS_HID_2d2e] = 1198,
- [BNXT_ULP_CLASS_HID_4ef2] = 1199,
- [BNXT_ULP_CLASS_HID_576a] = 1200,
- [BNXT_ULP_CLASS_HID_30b6] = 1201,
- [BNXT_ULP_CLASS_HID_192e] = 1202,
- [BNXT_ULP_CLASS_HID_197a] = 1203,
- [BNXT_ULP_CLASS_HID_4ea6] = 1204,
- [BNXT_ULP_CLASS_HID_2bf2] = 1205,
- [BNXT_ULP_CLASS_HID_306a] = 1206,
- [BNXT_ULP_CLASS_HID_06c6] = 1207,
- [BNXT_ULP_CLASS_HID_544e] = 1208,
- [BNXT_ULP_CLASS_HID_46ce] = 1209,
- [BNXT_ULP_CLASS_HID_0d02] = 1210,
- [BNXT_ULP_CLASS_HID_26c2] = 1211,
- [BNXT_ULP_CLASS_HID_744a] = 1212,
- [BNXT_ULP_CLASS_HID_1f86] = 1213,
- [BNXT_ULP_CLASS_HID_2d0e] = 1214,
- [BNXT_ULP_CLASS_HID_2e1c] = 1215,
- [BNXT_ULP_CLASS_HID_3a00] = 1216,
- [BNXT_ULP_CLASS_HID_46d0] = 1217,
- [BNXT_ULP_CLASS_HID_52c4] = 1218,
- [BNXT_ULP_CLASS_HID_4e10] = 1219,
- [BNXT_ULP_CLASS_HID_5a04] = 1220,
- [BNXT_ULP_CLASS_HID_1f98] = 1221,
- [BNXT_ULP_CLASS_HID_72f8] = 1222,
- [BNXT_ULP_CLASS_HID_0a78] = 1223,
- [BNXT_ULP_CLASS_HID_166c] = 1224,
- [BNXT_ULP_CLASS_HID_233c] = 1225,
- [BNXT_ULP_CLASS_HID_0f20] = 1226,
- [BNXT_ULP_CLASS_HID_2a7c] = 1227,
- [BNXT_ULP_CLASS_HID_3660] = 1228,
- [BNXT_ULP_CLASS_HID_4330] = 1229,
- [BNXT_ULP_CLASS_HID_2f24] = 1230,
- [BNXT_ULP_CLASS_HID_5584] = 1231,
- [BNXT_ULP_CLASS_HID_2198] = 1232,
- [BNXT_ULP_CLASS_HID_7588] = 1233,
- [BNXT_ULP_CLASS_HID_419c] = 1234,
- [BNXT_ULP_CLASS_HID_27758] = 1235,
- [BNXT_ULP_CLASS_HID_243ac] = 1236,
- [BNXT_ULP_CLASS_HID_20c10] = 1237,
- [BNXT_ULP_CLASS_HID_21864] = 1238,
- [BNXT_ULP_CLASS_HID_130c8] = 1239,
- [BNXT_ULP_CLASS_HID_11cdc] = 1240,
- [BNXT_ULP_CLASS_HID_150cc] = 1241,
- [BNXT_ULP_CLASS_HID_13d20] = 1242,
- [BNXT_ULP_CLASS_HID_3529c] = 1243,
- [BNXT_ULP_CLASS_HID_33ef0] = 1244,
- [BNXT_ULP_CLASS_HID_372e0] = 1245,
- [BNXT_ULP_CLASS_HID_35ef4] = 1246,
- [BNXT_ULP_CLASS_HID_2dfc] = 1247,
- [BNXT_ULP_CLASS_HID_39e0] = 1248,
- [BNXT_ULP_CLASS_HID_4530] = 1249,
- [BNXT_ULP_CLASS_HID_5124] = 1250,
- [BNXT_ULP_CLASS_HID_4df0] = 1251,
- [BNXT_ULP_CLASS_HID_59e4] = 1252,
- [BNXT_ULP_CLASS_HID_1c78] = 1253,
- [BNXT_ULP_CLASS_HID_7118] = 1254,
- [BNXT_ULP_CLASS_HID_0998] = 1255,
- [BNXT_ULP_CLASS_HID_158c] = 1256,
- [BNXT_ULP_CLASS_HID_20dc] = 1257,
- [BNXT_ULP_CLASS_HID_0cc0] = 1258,
- [BNXT_ULP_CLASS_HID_299c] = 1259,
- [BNXT_ULP_CLASS_HID_3580] = 1260,
- [BNXT_ULP_CLASS_HID_40d0] = 1261,
- [BNXT_ULP_CLASS_HID_2cc4] = 1262,
- [BNXT_ULP_CLASS_HID_55a4] = 1263,
- [BNXT_ULP_CLASS_HID_21b8] = 1264,
- [BNXT_ULP_CLASS_HID_75a8] = 1265,
- [BNXT_ULP_CLASS_HID_41bc] = 1266,
- [BNXT_ULP_CLASS_HID_27778] = 1267,
- [BNXT_ULP_CLASS_HID_2438c] = 1268,
- [BNXT_ULP_CLASS_HID_20c30] = 1269,
- [BNXT_ULP_CLASS_HID_21844] = 1270,
- [BNXT_ULP_CLASS_HID_130e8] = 1271,
- [BNXT_ULP_CLASS_HID_11cfc] = 1272,
- [BNXT_ULP_CLASS_HID_150ec] = 1273,
- [BNXT_ULP_CLASS_HID_13d00] = 1274,
- [BNXT_ULP_CLASS_HID_352bc] = 1275,
- [BNXT_ULP_CLASS_HID_33ed0] = 1276,
- [BNXT_ULP_CLASS_HID_372c0] = 1277,
- [BNXT_ULP_CLASS_HID_35ed4] = 1278,
- [BNXT_ULP_CLASS_HID_3866] = 1279,
- [BNXT_ULP_CLASS_HID_381e] = 1280,
- [BNXT_ULP_CLASS_HID_3860] = 1281,
- [BNXT_ULP_CLASS_HID_0454] = 1282,
- [BNXT_ULP_CLASS_HID_3818] = 1283,
- [BNXT_ULP_CLASS_HID_042c] = 1284,
- [BNXT_ULP_CLASS_HID_3846] = 1285,
- [BNXT_ULP_CLASS_HID_387e] = 1286,
- [BNXT_ULP_CLASS_HID_3ba6] = 1287,
- [BNXT_ULP_CLASS_HID_385e] = 1288,
- [BNXT_ULP_CLASS_HID_3840] = 1289,
- [BNXT_ULP_CLASS_HID_0474] = 1290,
- [BNXT_ULP_CLASS_HID_3878] = 1291,
- [BNXT_ULP_CLASS_HID_044c] = 1292,
- [BNXT_ULP_CLASS_HID_3ba0] = 1293,
- [BNXT_ULP_CLASS_HID_0794] = 1294,
- [BNXT_ULP_CLASS_HID_3858] = 1295,
- [BNXT_ULP_CLASS_HID_046c] = 1296
+ [BNXT_ULP_CLASS_HID_00b8] = 1,
+ [BNXT_ULP_CLASS_HID_0cc2] = 2,
+ [BNXT_ULP_CLASS_HID_10e4] = 3,
+ [BNXT_ULP_CLASS_HID_1d0e] = 4,
+ [BNXT_ULP_CLASS_HID_0286] = 5,
+ [BNXT_ULP_CLASS_HID_0e98] = 6,
+ [BNXT_ULP_CLASS_HID_1666] = 7,
+ [BNXT_ULP_CLASS_HID_02de] = 8,
+ [BNXT_ULP_CLASS_HID_81d25] = 9,
+ [BNXT_ULP_CLASS_HID_809ad] = 10,
+ [BNXT_ULP_CLASS_HID_80ae3] = 11,
+ [BNXT_ULP_CLASS_HID_8170d] = 12,
+ [BNXT_ULP_CLASS_HID_80773] = 13,
+ [BNXT_ULP_CLASS_HID_8139d] = 14,
+ [BNXT_ULP_CLASS_HID_814d3] = 15,
+ [BNXT_ULP_CLASS_HID_8015b] = 16,
+ [BNXT_ULP_CLASS_HID_21977] = 17,
+ [BNXT_ULP_CLASS_HID_205ef] = 18,
+ [BNXT_ULP_CLASS_HID_20735] = 19,
+ [BNXT_ULP_CLASS_HID_2134f] = 20,
+ [BNXT_ULP_CLASS_HID_61beb] = 21,
+ [BNXT_ULP_CLASS_HID_60863] = 22,
+ [BNXT_ULP_CLASS_HID_609a9] = 23,
+ [BNXT_ULP_CLASS_HID_615c3] = 24,
+ [BNXT_ULP_CLASS_HID_00a8] = 25,
+ [BNXT_ULP_CLASS_HID_0cd2] = 26,
+ [BNXT_ULP_CLASS_HID_10f4] = 27,
+ [BNXT_ULP_CLASS_HID_1d1e] = 28,
+ [BNXT_ULP_CLASS_HID_1488] = 29,
+ [BNXT_ULP_CLASS_HID_0110] = 30,
+ [BNXT_ULP_CLASS_HID_0532] = 31,
+ [BNXT_ULP_CLASS_HID_115c] = 32,
+ [BNXT_ULP_CLASS_HID_0ab8] = 33,
+ [BNXT_ULP_CLASS_HID_16a2] = 34,
+ [BNXT_ULP_CLASS_HID_1ac4] = 35,
+ [BNXT_ULP_CLASS_HID_074c] = 36,
+ [BNXT_ULP_CLASS_HID_1e98] = 37,
+ [BNXT_ULP_CLASS_HID_0ae0] = 38,
+ [BNXT_ULP_CLASS_HID_0f02] = 39,
+ [BNXT_ULP_CLASS_HID_1b2c] = 40,
+ [BNXT_ULP_CLASS_HID_0296] = 41,
+ [BNXT_ULP_CLASS_HID_0e88] = 42,
+ [BNXT_ULP_CLASS_HID_1676] = 43,
+ [BNXT_ULP_CLASS_HID_02ce] = 44,
+ [BNXT_ULP_CLASS_HID_8076e] = 45,
+ [BNXT_ULP_CLASS_HID_81380] = 46,
+ [BNXT_ULP_CLASS_HID_81b4e] = 47,
+ [BNXT_ULP_CLASS_HID_807c6] = 48,
+ [BNXT_ULP_CLASS_HID_404ea] = 49,
+ [BNXT_ULP_CLASS_HID_4110c] = 50,
+ [BNXT_ULP_CLASS_HID_418ca] = 51,
+ [BNXT_ULP_CLASS_HID_40542] = 52,
+ [BNXT_ULP_CLASS_HID_c09e2] = 53,
+ [BNXT_ULP_CLASS_HID_c1604] = 54,
+ [BNXT_ULP_CLASS_HID_c1dc2] = 55,
+ [BNXT_ULP_CLASS_HID_c0a5a] = 56,
+ [BNXT_ULP_CLASS_HID_0098] = 57,
+ [BNXT_ULP_CLASS_HID_0ce2] = 58,
+ [BNXT_ULP_CLASS_HID_10c4] = 59,
+ [BNXT_ULP_CLASS_HID_1d2e] = 60,
+ [BNXT_ULP_CLASS_HID_14b8] = 61,
+ [BNXT_ULP_CLASS_HID_0120] = 62,
+ [BNXT_ULP_CLASS_HID_0502] = 63,
+ [BNXT_ULP_CLASS_HID_116c] = 64,
+ [BNXT_ULP_CLASS_HID_0a88] = 65,
+ [BNXT_ULP_CLASS_HID_1692] = 66,
+ [BNXT_ULP_CLASS_HID_1af4] = 67,
+ [BNXT_ULP_CLASS_HID_077c] = 68,
+ [BNXT_ULP_CLASS_HID_1ea8] = 69,
+ [BNXT_ULP_CLASS_HID_0ad0] = 70,
+ [BNXT_ULP_CLASS_HID_0f32] = 71,
+ [BNXT_ULP_CLASS_HID_1b1c] = 72,
+ [BNXT_ULP_CLASS_HID_02a6] = 73,
+ [BNXT_ULP_CLASS_HID_0eb8] = 74,
+ [BNXT_ULP_CLASS_HID_1646] = 75,
+ [BNXT_ULP_CLASS_HID_02fe] = 76,
+ [BNXT_ULP_CLASS_HID_8075e] = 77,
+ [BNXT_ULP_CLASS_HID_813b0] = 78,
+ [BNXT_ULP_CLASS_HID_81b7e] = 79,
+ [BNXT_ULP_CLASS_HID_807f6] = 80,
+ [BNXT_ULP_CLASS_HID_404da] = 81,
+ [BNXT_ULP_CLASS_HID_4113c] = 82,
+ [BNXT_ULP_CLASS_HID_418fa] = 83,
+ [BNXT_ULP_CLASS_HID_40572] = 84,
+ [BNXT_ULP_CLASS_HID_c09d2] = 85,
+ [BNXT_ULP_CLASS_HID_c1634] = 86,
+ [BNXT_ULP_CLASS_HID_c1df2] = 87,
+ [BNXT_ULP_CLASS_HID_c0a6a] = 88,
+ [BNXT_ULP_CLASS_HID_81d35] = 89,
+ [BNXT_ULP_CLASS_HID_809bd] = 90,
+ [BNXT_ULP_CLASS_HID_80af3] = 91,
+ [BNXT_ULP_CLASS_HID_8171d] = 92,
+ [BNXT_ULP_CLASS_HID_80763] = 93,
+ [BNXT_ULP_CLASS_HID_8138d] = 94,
+ [BNXT_ULP_CLASS_HID_814c3] = 95,
+ [BNXT_ULP_CLASS_HID_8014b] = 96,
+ [BNXT_ULP_CLASS_HID_c001f] = 97,
+ [BNXT_ULP_CLASS_HID_c0c39] = 98,
+ [BNXT_ULP_CLASS_HID_c0d7f] = 99,
+ [BNXT_ULP_CLASS_HID_c1999] = 100,
+ [BNXT_ULP_CLASS_HID_c09ef] = 101,
+ [BNXT_ULP_CLASS_HID_c1609] = 102,
+ [BNXT_ULP_CLASS_HID_c174f] = 103,
+ [BNXT_ULP_CLASS_HID_c03d7] = 104,
+ [BNXT_ULP_CLASS_HID_a1e73] = 105,
+ [BNXT_ULP_CLASS_HID_a0afb] = 106,
+ [BNXT_ULP_CLASS_HID_a0c31] = 107,
+ [BNXT_ULP_CLASS_HID_a185b] = 108,
+ [BNXT_ULP_CLASS_HID_a08a1] = 109,
+ [BNXT_ULP_CLASS_HID_a14cb] = 110,
+ [BNXT_ULP_CLASS_HID_a1601] = 111,
+ [BNXT_ULP_CLASS_HID_a0289] = 112,
+ [BNXT_ULP_CLASS_HID_e015d] = 113,
+ [BNXT_ULP_CLASS_HID_e0d47] = 114,
+ [BNXT_ULP_CLASS_HID_e0ebd] = 115,
+ [BNXT_ULP_CLASS_HID_e1aa7] = 116,
+ [BNXT_ULP_CLASS_HID_e0b2d] = 117,
+ [BNXT_ULP_CLASS_HID_e1757] = 118,
+ [BNXT_ULP_CLASS_HID_e188d] = 119,
+ [BNXT_ULP_CLASS_HID_e0515] = 120,
+ [BNXT_ULP_CLASS_HID_21967] = 121,
+ [BNXT_ULP_CLASS_HID_205ff] = 122,
+ [BNXT_ULP_CLASS_HID_20725] = 123,
+ [BNXT_ULP_CLASS_HID_2135f] = 124,
+ [BNXT_ULP_CLASS_HID_61bfb] = 125,
+ [BNXT_ULP_CLASS_HID_60873] = 126,
+ [BNXT_ULP_CLASS_HID_609b9] = 127,
+ [BNXT_ULP_CLASS_HID_615d3] = 128,
+ [BNXT_ULP_CLASS_HID_30a55] = 129,
+ [BNXT_ULP_CLASS_HID_3164f] = 130,
+ [BNXT_ULP_CLASS_HID_317b5] = 131,
+ [BNXT_ULP_CLASS_HID_3040d] = 132,
+ [BNXT_ULP_CLASS_HID_70ca9] = 133,
+ [BNXT_ULP_CLASS_HID_718c3] = 134,
+ [BNXT_ULP_CLASS_HID_71a09] = 135,
+ [BNXT_ULP_CLASS_HID_70681] = 136,
+ [BNXT_ULP_CLASS_HID_2821d] = 137,
+ [BNXT_ULP_CLASS_HID_28e37] = 138,
+ [BNXT_ULP_CLASS_HID_28f7d] = 139,
+ [BNXT_ULP_CLASS_HID_29b97] = 140,
+ [BNXT_ULP_CLASS_HID_68491] = 141,
+ [BNXT_ULP_CLASS_HID_6908b] = 142,
+ [BNXT_ULP_CLASS_HID_691f1] = 143,
+ [BNXT_ULP_CLASS_HID_69deb] = 144,
+ [BNXT_ULP_CLASS_HID_3926d] = 145,
+ [BNXT_ULP_CLASS_HID_39e87] = 146,
+ [BNXT_ULP_CLASS_HID_38023] = 147,
+ [BNXT_ULP_CLASS_HID_38c45] = 148,
+ [BNXT_ULP_CLASS_HID_794e1] = 149,
+ [BNXT_ULP_CLASS_HID_78179] = 150,
+ [BNXT_ULP_CLASS_HID_782a7] = 151,
+ [BNXT_ULP_CLASS_HID_78ed9] = 152,
+ [BNXT_ULP_CLASS_HID_81d05] = 153,
+ [BNXT_ULP_CLASS_HID_8098d] = 154,
+ [BNXT_ULP_CLASS_HID_80ac3] = 155,
+ [BNXT_ULP_CLASS_HID_8172d] = 156,
+ [BNXT_ULP_CLASS_HID_80753] = 157,
+ [BNXT_ULP_CLASS_HID_813bd] = 158,
+ [BNXT_ULP_CLASS_HID_814f3] = 159,
+ [BNXT_ULP_CLASS_HID_8017b] = 160,
+ [BNXT_ULP_CLASS_HID_c002f] = 161,
+ [BNXT_ULP_CLASS_HID_c0c09] = 162,
+ [BNXT_ULP_CLASS_HID_c0d4f] = 163,
+ [BNXT_ULP_CLASS_HID_c19a9] = 164,
+ [BNXT_ULP_CLASS_HID_c09df] = 165,
+ [BNXT_ULP_CLASS_HID_c1639] = 166,
+ [BNXT_ULP_CLASS_HID_c177f] = 167,
+ [BNXT_ULP_CLASS_HID_c03e7] = 168,
+ [BNXT_ULP_CLASS_HID_a1e43] = 169,
+ [BNXT_ULP_CLASS_HID_a0acb] = 170,
+ [BNXT_ULP_CLASS_HID_a0c01] = 171,
+ [BNXT_ULP_CLASS_HID_a186b] = 172,
+ [BNXT_ULP_CLASS_HID_a0891] = 173,
+ [BNXT_ULP_CLASS_HID_a14fb] = 174,
+ [BNXT_ULP_CLASS_HID_a1631] = 175,
+ [BNXT_ULP_CLASS_HID_a02b9] = 176,
+ [BNXT_ULP_CLASS_HID_e016d] = 177,
+ [BNXT_ULP_CLASS_HID_e0d77] = 178,
+ [BNXT_ULP_CLASS_HID_e0e8d] = 179,
+ [BNXT_ULP_CLASS_HID_e1a97] = 180,
+ [BNXT_ULP_CLASS_HID_e0b1d] = 181,
+ [BNXT_ULP_CLASS_HID_e1767] = 182,
+ [BNXT_ULP_CLASS_HID_e18bd] = 183,
+ [BNXT_ULP_CLASS_HID_e0525] = 184,
+ [BNXT_ULP_CLASS_HID_21957] = 185,
+ [BNXT_ULP_CLASS_HID_205cf] = 186,
+ [BNXT_ULP_CLASS_HID_20715] = 187,
+ [BNXT_ULP_CLASS_HID_2136f] = 188,
+ [BNXT_ULP_CLASS_HID_61bcb] = 189,
+ [BNXT_ULP_CLASS_HID_60843] = 190,
+ [BNXT_ULP_CLASS_HID_60989] = 191,
+ [BNXT_ULP_CLASS_HID_615e3] = 192,
+ [BNXT_ULP_CLASS_HID_30a65] = 193,
+ [BNXT_ULP_CLASS_HID_3167f] = 194,
+ [BNXT_ULP_CLASS_HID_31785] = 195,
+ [BNXT_ULP_CLASS_HID_3043d] = 196,
+ [BNXT_ULP_CLASS_HID_70c99] = 197,
+ [BNXT_ULP_CLASS_HID_718f3] = 198,
+ [BNXT_ULP_CLASS_HID_71a39] = 199,
+ [BNXT_ULP_CLASS_HID_706b1] = 200,
+ [BNXT_ULP_CLASS_HID_2822d] = 201,
+ [BNXT_ULP_CLASS_HID_28e07] = 202,
+ [BNXT_ULP_CLASS_HID_28f4d] = 203,
+ [BNXT_ULP_CLASS_HID_29ba7] = 204,
+ [BNXT_ULP_CLASS_HID_684a1] = 205,
+ [BNXT_ULP_CLASS_HID_690bb] = 206,
+ [BNXT_ULP_CLASS_HID_691c1] = 207,
+ [BNXT_ULP_CLASS_HID_69ddb] = 208,
+ [BNXT_ULP_CLASS_HID_3925d] = 209,
+ [BNXT_ULP_CLASS_HID_39eb7] = 210,
+ [BNXT_ULP_CLASS_HID_38013] = 211,
+ [BNXT_ULP_CLASS_HID_38c75] = 212,
+ [BNXT_ULP_CLASS_HID_794d1] = 213,
+ [BNXT_ULP_CLASS_HID_78149] = 214,
+ [BNXT_ULP_CLASS_HID_78297] = 215,
+ [BNXT_ULP_CLASS_HID_78ee9] = 216,
+ [BNXT_ULP_CLASS_HID_0816] = 217,
+ [BNXT_ULP_CLASS_HID_1852] = 218,
+ [BNXT_ULP_CLASS_HID_09f4] = 219,
+ [BNXT_ULP_CLASS_HID_1dd4] = 220,
+ [BNXT_ULP_CLASS_HID_804f1] = 221,
+ [BNXT_ULP_CLASS_HID_81251] = 222,
+ [BNXT_ULP_CLASS_HID_80ee1] = 223,
+ [BNXT_ULP_CLASS_HID_81c41] = 224,
+ [BNXT_ULP_CLASS_HID_2013b] = 225,
+ [BNXT_ULP_CLASS_HID_20e9b] = 226,
+ [BNXT_ULP_CLASS_HID_603bf] = 227,
+ [BNXT_ULP_CLASS_HID_6111f] = 228,
+ [BNXT_ULP_CLASS_HID_0806] = 229,
+ [BNXT_ULP_CLASS_HID_1842] = 230,
+ [BNXT_ULP_CLASS_HID_1be6] = 231,
+ [BNXT_ULP_CLASS_HID_0c80] = 232,
+ [BNXT_ULP_CLASS_HID_1216] = 233,
+ [BNXT_ULP_CLASS_HID_02b0] = 234,
+ [BNXT_ULP_CLASS_HID_0654] = 235,
+ [BNXT_ULP_CLASS_HID_1690] = 236,
+ [BNXT_ULP_CLASS_HID_09e4] = 237,
+ [BNXT_ULP_CLASS_HID_1dc4] = 238,
+ [BNXT_ULP_CLASS_HID_80efc] = 239,
+ [BNXT_ULP_CLASS_HID_80332] = 240,
+ [BNXT_ULP_CLASS_HID_40c78] = 241,
+ [BNXT_ULP_CLASS_HID_400be] = 242,
+ [BNXT_ULP_CLASS_HID_c1170] = 243,
+ [BNXT_ULP_CLASS_HID_c05b6] = 244,
+ [BNXT_ULP_CLASS_HID_0836] = 245,
+ [BNXT_ULP_CLASS_HID_1872] = 246,
+ [BNXT_ULP_CLASS_HID_1bd6] = 247,
+ [BNXT_ULP_CLASS_HID_0cb0] = 248,
+ [BNXT_ULP_CLASS_HID_1226] = 249,
+ [BNXT_ULP_CLASS_HID_0280] = 250,
+ [BNXT_ULP_CLASS_HID_0664] = 251,
+ [BNXT_ULP_CLASS_HID_16a0] = 252,
+ [BNXT_ULP_CLASS_HID_09d4] = 253,
+ [BNXT_ULP_CLASS_HID_1df4] = 254,
+ [BNXT_ULP_CLASS_HID_80ecc] = 255,
+ [BNXT_ULP_CLASS_HID_80302] = 256,
+ [BNXT_ULP_CLASS_HID_40c48] = 257,
+ [BNXT_ULP_CLASS_HID_4008e] = 258,
+ [BNXT_ULP_CLASS_HID_c1140] = 259,
+ [BNXT_ULP_CLASS_HID_c0586] = 260,
+ [BNXT_ULP_CLASS_HID_804e1] = 261,
+ [BNXT_ULP_CLASS_HID_81241] = 262,
+ [BNXT_ULP_CLASS_HID_80ef1] = 263,
+ [BNXT_ULP_CLASS_HID_81c51] = 264,
+ [BNXT_ULP_CLASS_HID_c076d] = 265,
+ [BNXT_ULP_CLASS_HID_c14cd] = 266,
+ [BNXT_ULP_CLASS_HID_c117d] = 267,
+ [BNXT_ULP_CLASS_HID_c1edd] = 268,
+ [BNXT_ULP_CLASS_HID_a062f] = 269,
+ [BNXT_ULP_CLASS_HID_a138f] = 270,
+ [BNXT_ULP_CLASS_HID_a103f] = 271,
+ [BNXT_ULP_CLASS_HID_a1d9f] = 272,
+ [BNXT_ULP_CLASS_HID_e08ab] = 273,
+ [BNXT_ULP_CLASS_HID_e160b] = 274,
+ [BNXT_ULP_CLASS_HID_e12bb] = 275,
+ [BNXT_ULP_CLASS_HID_e0079] = 276,
+ [BNXT_ULP_CLASS_HID_2012b] = 277,
+ [BNXT_ULP_CLASS_HID_20e8b] = 278,
+ [BNXT_ULP_CLASS_HID_603af] = 279,
+ [BNXT_ULP_CLASS_HID_6110f] = 280,
+ [BNXT_ULP_CLASS_HID_311bb] = 281,
+ [BNXT_ULP_CLASS_HID_31f1b] = 282,
+ [BNXT_ULP_CLASS_HID_7143f] = 283,
+ [BNXT_ULP_CLASS_HID_701fd] = 284,
+ [BNXT_ULP_CLASS_HID_28963] = 285,
+ [BNXT_ULP_CLASS_HID_296c3] = 286,
+ [BNXT_ULP_CLASS_HID_68be7] = 287,
+ [BNXT_ULP_CLASS_HID_69947] = 288,
+ [BNXT_ULP_CLASS_HID_399f3] = 289,
+ [BNXT_ULP_CLASS_HID_387b1] = 290,
+ [BNXT_ULP_CLASS_HID_79c77] = 291,
+ [BNXT_ULP_CLASS_HID_78a35] = 292,
+ [BNXT_ULP_CLASS_HID_804d1] = 293,
+ [BNXT_ULP_CLASS_HID_81271] = 294,
+ [BNXT_ULP_CLASS_HID_80ec1] = 295,
+ [BNXT_ULP_CLASS_HID_81c61] = 296,
+ [BNXT_ULP_CLASS_HID_c075d] = 297,
+ [BNXT_ULP_CLASS_HID_c14fd] = 298,
+ [BNXT_ULP_CLASS_HID_c114d] = 299,
+ [BNXT_ULP_CLASS_HID_c1eed] = 300,
+ [BNXT_ULP_CLASS_HID_a061f] = 301,
+ [BNXT_ULP_CLASS_HID_a13bf] = 302,
+ [BNXT_ULP_CLASS_HID_a100f] = 303,
+ [BNXT_ULP_CLASS_HID_a1daf] = 304,
+ [BNXT_ULP_CLASS_HID_e089b] = 305,
+ [BNXT_ULP_CLASS_HID_e163b] = 306,
+ [BNXT_ULP_CLASS_HID_e128b] = 307,
+ [BNXT_ULP_CLASS_HID_e0049] = 308,
+ [BNXT_ULP_CLASS_HID_2011b] = 309,
+ [BNXT_ULP_CLASS_HID_20ebb] = 310,
+ [BNXT_ULP_CLASS_HID_6039f] = 311,
+ [BNXT_ULP_CLASS_HID_6113f] = 312,
+ [BNXT_ULP_CLASS_HID_3118b] = 313,
+ [BNXT_ULP_CLASS_HID_31f2b] = 314,
+ [BNXT_ULP_CLASS_HID_7140f] = 315,
+ [BNXT_ULP_CLASS_HID_701cd] = 316,
+ [BNXT_ULP_CLASS_HID_28953] = 317,
+ [BNXT_ULP_CLASS_HID_296f3] = 318,
+ [BNXT_ULP_CLASS_HID_68bd7] = 319,
+ [BNXT_ULP_CLASS_HID_69977] = 320,
+ [BNXT_ULP_CLASS_HID_399c3] = 321,
+ [BNXT_ULP_CLASS_HID_38781] = 322,
+ [BNXT_ULP_CLASS_HID_79c47] = 323,
+ [BNXT_ULP_CLASS_HID_78a05] = 324,
+ [BNXT_ULP_CLASS_HID_04a4] = 325,
+ [BNXT_ULP_CLASS_HID_04a8] = 326,
+ [BNXT_ULP_CLASS_HID_04a5] = 327,
+ [BNXT_ULP_CLASS_HID_1205] = 328,
+ [BNXT_ULP_CLASS_HID_04a9] = 329,
+ [BNXT_ULP_CLASS_HID_1209] = 330,
+ [BNXT_ULP_CLASS_HID_04b4] = 331,
+ [BNXT_ULP_CLASS_HID_04b8] = 332,
+ [BNXT_ULP_CLASS_HID_0484] = 333,
+ [BNXT_ULP_CLASS_HID_0488] = 334,
+ [BNXT_ULP_CLASS_HID_04b5] = 335,
+ [BNXT_ULP_CLASS_HID_1215] = 336,
+ [BNXT_ULP_CLASS_HID_04b9] = 337,
+ [BNXT_ULP_CLASS_HID_1219] = 338,
+ [BNXT_ULP_CLASS_HID_0485] = 339,
+ [BNXT_ULP_CLASS_HID_1225] = 340,
+ [BNXT_ULP_CLASS_HID_0489] = 341,
+ [BNXT_ULP_CLASS_HID_1229] = 342,
+ [BNXT_ULP_CLASS_HID_0226] = 343,
+ [BNXT_ULP_CLASS_HID_4045a] = 344,
+ [BNXT_ULP_CLASS_HID_0daa] = 345,
+ [BNXT_ULP_CLASS_HID_11b0] = 346,
+ [BNXT_ULP_CLASS_HID_403f8] = 347,
+ [BNXT_ULP_CLASS_HID_4161e] = 348,
+ [BNXT_ULP_CLASS_HID_40439] = 349,
+ [BNXT_ULP_CLASS_HID_41405] = 350,
+ [BNXT_ULP_CLASS_HID_51449] = 351,
+ [BNXT_ULP_CLASS_HID_50b33] = 352,
+ [BNXT_ULP_CLASS_HID_48c01] = 353,
+ [BNXT_ULP_CLASS_HID_483eb] = 354,
+ [BNXT_ULP_CLASS_HID_5833f] = 355,
+ [BNXT_ULP_CLASS_HID_5937b] = 356,
+ [BNXT_ULP_CLASS_HID_41875] = 357,
+ [BNXT_ULP_CLASS_HID_40f5f] = 358,
+ [BNXT_ULP_CLASS_HID_50f23] = 359,
+ [BNXT_ULP_CLASS_HID_51f6f] = 360,
+ [BNXT_ULP_CLASS_HID_4875b] = 361,
+ [BNXT_ULP_CLASS_HID_49727] = 362,
+ [BNXT_ULP_CLASS_HID_5976b] = 363,
+ [BNXT_ULP_CLASS_HID_58655] = 364,
+ [BNXT_ULP_CLASS_HID_4125f] = 365,
+ [BNXT_ULP_CLASS_HID_401f9] = 366,
+ [BNXT_ULP_CLASS_HID_501cd] = 367,
+ [BNXT_ULP_CLASS_HID_51149] = 368,
+ [BNXT_ULP_CLASS_HID_49a67] = 369,
+ [BNXT_ULP_CLASS_HID_489c1] = 370,
+ [BNXT_ULP_CLASS_HID_58955] = 371,
+ [BNXT_ULP_CLASS_HID_59951] = 372,
+ [BNXT_ULP_CLASS_HID_40569] = 373,
+ [BNXT_ULP_CLASS_HID_41575] = 374,
+ [BNXT_ULP_CLASS_HID_51579] = 375,
+ [BNXT_ULP_CLASS_HID_50463] = 376,
+ [BNXT_ULP_CLASS_HID_48d71] = 377,
+ [BNXT_ULP_CLASS_HID_49d7d] = 378,
+ [BNXT_ULP_CLASS_HID_59d41] = 379,
+ [BNXT_ULP_CLASS_HID_58c6b] = 380,
+ [BNXT_ULP_CLASS_HID_10255] = 381,
+ [BNXT_ULP_CLASS_HID_11675] = 382,
+ [BNXT_ULP_CLASS_HID_14649] = 383,
+ [BNXT_ULP_CLASS_HID_15a69] = 384,
+ [BNXT_ULP_CLASS_HID_1205b] = 385,
+ [BNXT_ULP_CLASS_HID_1347b] = 386,
+ [BNXT_ULP_CLASS_HID_16bbf] = 387,
+ [BNXT_ULP_CLASS_HID_1785f] = 388,
+ [BNXT_ULP_CLASS_HID_11551] = 389,
+ [BNXT_ULP_CLASS_HID_10897] = 390,
+ [BNXT_ULP_CLASS_HID_15955] = 391,
+ [BNXT_ULP_CLASS_HID_14c8b] = 392,
+ [BNXT_ULP_CLASS_HID_13b47] = 393,
+ [BNXT_ULP_CLASS_HID_12e85] = 394,
+ [BNXT_ULP_CLASS_HID_17f5b] = 395,
+ [BNXT_ULP_CLASS_HID_17299] = 396,
+ [BNXT_ULP_CLASS_HID_10fe7] = 397,
+ [BNXT_ULP_CLASS_HID_10325] = 398,
+ [BNXT_ULP_CLASS_HID_153cb] = 399,
+ [BNXT_ULP_CLASS_HID_14709] = 400,
+ [BNXT_ULP_CLASS_HID_12dc5] = 401,
+ [BNXT_ULP_CLASS_HID_1212b] = 402,
+ [BNXT_ULP_CLASS_HID_171c9] = 403,
+ [BNXT_ULP_CLASS_HID_1650f] = 404,
+ [BNXT_ULP_CLASS_HID_10201] = 405,
+ [BNXT_ULP_CLASS_HID_116c1] = 406,
+ [BNXT_ULP_CLASS_HID_14605] = 407,
+ [BNXT_ULP_CLASS_HID_15a05] = 408,
+ [BNXT_ULP_CLASS_HID_12007] = 409,
+ [BNXT_ULP_CLASS_HID_13407] = 410,
+ [BNXT_ULP_CLASS_HID_1640b] = 411,
+ [BNXT_ULP_CLASS_HID_1780b] = 412,
+ [BNXT_ULP_CLASS_HID_404b0] = 413,
+ [BNXT_ULP_CLASS_HID_4148c] = 414,
+ [BNXT_ULP_CLASS_HID_514c0] = 415,
+ [BNXT_ULP_CLASS_HID_50bba] = 416,
+ [BNXT_ULP_CLASS_HID_48c88] = 417,
+ [BNXT_ULP_CLASS_HID_48362] = 418,
+ [BNXT_ULP_CLASS_HID_583b6] = 419,
+ [BNXT_ULP_CLASS_HID_593f2] = 420,
+ [BNXT_ULP_CLASS_HID_41f54] = 421,
+ [BNXT_ULP_CLASS_HID_40fce] = 422,
+ [BNXT_ULP_CLASS_HID_50e02] = 423,
+ [BNXT_ULP_CLASS_HID_51e5e] = 424,
+ [BNXT_ULP_CLASS_HID_487ca] = 425,
+ [BNXT_ULP_CLASS_HID_49606] = 426,
+ [BNXT_ULP_CLASS_HID_5965a] = 427,
+ [BNXT_ULP_CLASS_HID_58514] = 428,
+ [BNXT_ULP_CLASS_HID_412c2] = 429,
+ [BNXT_ULP_CLASS_HID_401ac] = 430,
+ [BNXT_ULP_CLASS_HID_501e0] = 431,
+ [BNXT_ULP_CLASS_HID_511cc] = 432,
+ [BNXT_ULP_CLASS_HID_4990a] = 433,
+ [BNXT_ULP_CLASS_HID_489e4] = 434,
+ [BNXT_ULP_CLASS_HID_589c8] = 435,
+ [BNXT_ULP_CLASS_HID_59804] = 436,
+ [BNXT_ULP_CLASS_HID_40404] = 437,
+ [BNXT_ULP_CLASS_HID_41440] = 438,
+ [BNXT_ULP_CLASS_HID_51484] = 439,
+ [BNXT_ULP_CLASS_HID_50b0e] = 440,
+ [BNXT_ULP_CLASS_HID_48c4c] = 441,
+ [BNXT_ULP_CLASS_HID_48306] = 442,
+ [BNXT_ULP_CLASS_HID_5830a] = 443,
+ [BNXT_ULP_CLASS_HID_59346] = 444,
+ [BNXT_ULP_CLASS_HID_102cc] = 445,
+ [BNXT_ULP_CLASS_HID_116ec] = 446,
+ [BNXT_ULP_CLASS_HID_146d0] = 447,
+ [BNXT_ULP_CLASS_HID_15af0] = 448,
+ [BNXT_ULP_CLASS_HID_120c2] = 449,
+ [BNXT_ULP_CLASS_HID_134e2] = 450,
+ [BNXT_ULP_CLASS_HID_16b26] = 451,
+ [BNXT_ULP_CLASS_HID_178c6] = 452,
+ [BNXT_ULP_CLASS_HID_115c6] = 453,
+ [BNXT_ULP_CLASS_HID_10804] = 454,
+ [BNXT_ULP_CLASS_HID_15822] = 455,
+ [BNXT_ULP_CLASS_HID_14c60] = 456,
+ [BNXT_ULP_CLASS_HID_13bd4] = 457,
+ [BNXT_ULP_CLASS_HID_12e12] = 458,
+ [BNXT_ULP_CLASS_HID_17e30] = 459,
+ [BNXT_ULP_CLASS_HID_17276] = 460,
+ [BNXT_ULP_CLASS_HID_11f1a] = 461,
+ [BNXT_ULP_CLASS_HID_11358] = 462,
+ [BNXT_ULP_CLASS_HID_14398] = 463,
+ [BNXT_ULP_CLASS_HID_157b8] = 464,
+ [BNXT_ULP_CLASS_HID_13d68] = 465,
+ [BNXT_ULP_CLASS_HID_131aa] = 466,
+ [BNXT_ULP_CLASS_HID_16192] = 467,
+ [BNXT_ULP_CLASS_HID_175b2] = 468,
+ [BNXT_ULP_CLASS_HID_112b2] = 469,
+ [BNXT_ULP_CLASS_HID_106f0] = 470,
+ [BNXT_ULP_CLASS_HID_15692] = 471,
+ [BNXT_ULP_CLASS_HID_14ad0] = 472,
+ [BNXT_ULP_CLASS_HID_13080] = 473,
+ [BNXT_ULP_CLASS_HID_124c2] = 474,
+ [BNXT_ULP_CLASS_HID_174e0] = 475,
+ [BNXT_ULP_CLASS_HID_16f22] = 476,
+ [BNXT_ULP_CLASS_HID_4025b] = 477,
+ [BNXT_ULP_CLASS_HID_41267] = 478,
+ [BNXT_ULP_CLASS_HID_5122b] = 479,
+ [BNXT_ULP_CLASS_HID_50d51] = 480,
+ [BNXT_ULP_CLASS_HID_48a63] = 481,
+ [BNXT_ULP_CLASS_HID_48589] = 482,
+ [BNXT_ULP_CLASS_HID_5855d] = 483,
+ [BNXT_ULP_CLASS_HID_59519] = 484,
+ [BNXT_ULP_CLASS_HID_41e17] = 485,
+ [BNXT_ULP_CLASS_HID_4093d] = 486,
+ [BNXT_ULP_CLASS_HID_50941] = 487,
+ [BNXT_ULP_CLASS_HID_5190d] = 488,
+ [BNXT_ULP_CLASS_HID_48139] = 489,
+ [BNXT_ULP_CLASS_HID_49145] = 490,
+ [BNXT_ULP_CLASS_HID_59109] = 491,
+ [BNXT_ULP_CLASS_HID_58037] = 492,
+ [BNXT_ULP_CLASS_HID_4143d] = 493,
+ [BNXT_ULP_CLASS_HID_4079b] = 494,
+ [BNXT_ULP_CLASS_HID_507af] = 495,
+ [BNXT_ULP_CLASS_HID_5172b] = 496,
+ [BNXT_ULP_CLASS_HID_49c05] = 497,
+ [BNXT_ULP_CLASS_HID_48fa3] = 498,
+ [BNXT_ULP_CLASS_HID_58f37] = 499,
+ [BNXT_ULP_CLASS_HID_59f33] = 500,
+ [BNXT_ULP_CLASS_HID_4030b] = 501,
+ [BNXT_ULP_CLASS_HID_41317] = 502,
+ [BNXT_ULP_CLASS_HID_5131b] = 503,
+ [BNXT_ULP_CLASS_HID_50201] = 504,
+ [BNXT_ULP_CLASS_HID_48b13] = 505,
+ [BNXT_ULP_CLASS_HID_49b1f] = 506,
+ [BNXT_ULP_CLASS_HID_59b23] = 507,
+ [BNXT_ULP_CLASS_HID_58a09] = 508,
+ [BNXT_ULP_CLASS_HID_419bf] = 509,
+ [BNXT_ULP_CLASS_HID_40925] = 510,
+ [BNXT_ULP_CLASS_HID_508e9] = 511,
+ [BNXT_ULP_CLASS_HID_518b5] = 512,
+ [BNXT_ULP_CLASS_HID_48121] = 513,
+ [BNXT_ULP_CLASS_HID_490ed] = 514,
+ [BNXT_ULP_CLASS_HID_590b1] = 515,
+ [BNXT_ULP_CLASS_HID_583ff] = 516,
+ [BNXT_ULP_CLASS_HID_41475] = 517,
+ [BNXT_ULP_CLASS_HID_40473] = 518,
+ [BNXT_ULP_CLASS_HID_50427] = 519,
+ [BNXT_ULP_CLASS_HID_51763] = 520,
+ [BNXT_ULP_CLASS_HID_49c3d] = 521,
+ [BNXT_ULP_CLASS_HID_48c3b] = 522,
+ [BNXT_ULP_CLASS_HID_58f6f] = 523,
+ [BNXT_ULP_CLASS_HID_59f2b] = 524,
+ [BNXT_ULP_CLASS_HID_40333] = 525,
+ [BNXT_ULP_CLASS_HID_412bf] = 526,
+ [BNXT_ULP_CLASS_HID_512a3] = 527,
+ [BNXT_ULP_CLASS_HID_50229] = 528,
+ [BNXT_ULP_CLASS_HID_48abb] = 529,
+ [BNXT_ULP_CLASS_HID_49aa7] = 530,
+ [BNXT_ULP_CLASS_HID_59a2b] = 531,
+ [BNXT_ULP_CLASS_HID_595b1] = 532,
+ [BNXT_ULP_CLASS_HID_41e2f] = 533,
+ [BNXT_ULP_CLASS_HID_40e35] = 534,
+ [BNXT_ULP_CLASS_HID_50939] = 535,
+ [BNXT_ULP_CLASS_HID_51925] = 536,
+ [BNXT_ULP_CLASS_HID_48631] = 537,
+ [BNXT_ULP_CLASS_HID_4913d] = 538,
+ [BNXT_ULP_CLASS_HID_59121] = 539,
+ [BNXT_ULP_CLASS_HID_5812f] = 540,
+ [BNXT_ULP_CLASS_HID_41429] = 541,
+ [BNXT_ULP_CLASS_HID_40747] = 542,
+ [BNXT_ULP_CLASS_HID_5070b] = 543,
+ [BNXT_ULP_CLASS_HID_51727] = 544,
+ [BNXT_ULP_CLASS_HID_49fe1] = 545,
+ [BNXT_ULP_CLASS_HID_48f0f] = 546,
+ [BNXT_ULP_CLASS_HID_58f23] = 547,
+ [BNXT_ULP_CLASS_HID_59eef] = 548,
+ [BNXT_ULP_CLASS_HID_40347] = 549,
+ [BNXT_ULP_CLASS_HID_41303] = 550,
+ [BNXT_ULP_CLASS_HID_51247] = 551,
+ [BNXT_ULP_CLASS_HID_5026d] = 552,
+ [BNXT_ULP_CLASS_HID_48b0f] = 553,
+ [BNXT_ULP_CLASS_HID_49a4b] = 554,
+ [BNXT_ULP_CLASS_HID_59a0f] = 555,
+ [BNXT_ULP_CLASS_HID_58a05] = 556,
+ [BNXT_ULP_CLASS_HID_41983] = 557,
+ [BNXT_ULP_CLASS_HID_40929] = 558,
+ [BNXT_ULP_CLASS_HID_5092d] = 559,
+ [BNXT_ULP_CLASS_HID_518a9] = 560,
+ [BNXT_ULP_CLASS_HID_48125] = 561,
+ [BNXT_ULP_CLASS_HID_49121] = 562,
+ [BNXT_ULP_CLASS_HID_59085] = 563,
+ [BNXT_ULP_CLASS_HID_58023] = 564,
+ [BNXT_ULP_CLASS_HID_41509] = 565,
+ [BNXT_ULP_CLASS_HID_40407] = 566,
+ [BNXT_ULP_CLASS_HID_5040b] = 567,
+ [BNXT_ULP_CLASS_HID_51407] = 568,
+ [BNXT_ULP_CLASS_HID_49d21] = 569,
+ [BNXT_ULP_CLASS_HID_48c0f] = 570,
+ [BNXT_ULP_CLASS_HID_58c03] = 571,
+ [BNXT_ULP_CLASS_HID_59f0f] = 572,
+ [BNXT_ULP_CLASS_HID_402ef] = 573,
+ [BNXT_ULP_CLASS_HID_412ab] = 574,
+ [BNXT_ULP_CLASS_HID_5126f] = 575,
+ [BNXT_ULP_CLASS_HID_50de5] = 576,
+ [BNXT_ULP_CLASS_HID_48aa7] = 577,
+ [BNXT_ULP_CLASS_HID_485ed] = 578,
+ [BNXT_ULP_CLASS_HID_585e1] = 579,
+ [BNXT_ULP_CLASS_HID_595ad] = 580,
+ [BNXT_ULP_CLASS_HID_41e6b] = 581,
+ [BNXT_ULP_CLASS_HID_40961] = 582,
+ [BNXT_ULP_CLASS_HID_50925] = 583,
+ [BNXT_ULP_CLASS_HID_51961] = 584,
+ [BNXT_ULP_CLASS_HID_4816d] = 585,
+ [BNXT_ULP_CLASS_HID_49129] = 586,
+ [BNXT_ULP_CLASS_HID_5916d] = 587,
+ [BNXT_ULP_CLASS_HID_5806b] = 588,
+ [BNXT_ULP_CLASS_HID_414a1] = 589,
+ [BNXT_ULP_CLASS_HID_4042f] = 590,
+ [BNXT_ULP_CLASS_HID_507a3] = 591,
+ [BNXT_ULP_CLASS_HID_517af] = 592,
+ [BNXT_ULP_CLASS_HID_49c29] = 593,
+ [BNXT_ULP_CLASS_HID_48fa7] = 594,
+ [BNXT_ULP_CLASS_HID_58fab] = 595,
+ [BNXT_ULP_CLASS_HID_59f27] = 596,
+ [BNXT_ULP_CLASS_HID_4032f] = 597,
+ [BNXT_ULP_CLASS_HID_4132b] = 598,
+ [BNXT_ULP_CLASS_HID_5132f] = 599,
+ [BNXT_ULP_CLASS_HID_50225] = 600,
+ [BNXT_ULP_CLASS_HID_48b27] = 601,
+ [BNXT_ULP_CLASS_HID_49b23] = 602,
+ [BNXT_ULP_CLASS_HID_59b27] = 603,
+ [BNXT_ULP_CLASS_HID_58a2d] = 604,
+ [BNXT_ULP_CLASS_HID_10437] = 605,
+ [BNXT_ULP_CLASS_HID_11017] = 606,
+ [BNXT_ULP_CLASS_HID_1402b] = 607,
+ [BNXT_ULP_CLASS_HID_15c0b] = 608,
+ [BNXT_ULP_CLASS_HID_12639] = 609,
+ [BNXT_ULP_CLASS_HID_13219] = 610,
+ [BNXT_ULP_CLASS_HID_16ddd] = 611,
+ [BNXT_ULP_CLASS_HID_17e3d] = 612,
+ [BNXT_ULP_CLASS_HID_11333] = 613,
+ [BNXT_ULP_CLASS_HID_10ef5] = 614,
+ [BNXT_ULP_CLASS_HID_15f37] = 615,
+ [BNXT_ULP_CLASS_HID_14ae9] = 616,
+ [BNXT_ULP_CLASS_HID_13d25] = 617,
+ [BNXT_ULP_CLASS_HID_128e7] = 618,
+ [BNXT_ULP_CLASS_HID_17939] = 619,
+ [BNXT_ULP_CLASS_HID_174fb] = 620,
+ [BNXT_ULP_CLASS_HID_10985] = 621,
+ [BNXT_ULP_CLASS_HID_10547] = 622,
+ [BNXT_ULP_CLASS_HID_155a9] = 623,
+ [BNXT_ULP_CLASS_HID_1416b] = 624,
+ [BNXT_ULP_CLASS_HID_12ba7] = 625,
+ [BNXT_ULP_CLASS_HID_12749] = 626,
+ [BNXT_ULP_CLASS_HID_177ab] = 627,
+ [BNXT_ULP_CLASS_HID_1636d] = 628,
+ [BNXT_ULP_CLASS_HID_10463] = 629,
+ [BNXT_ULP_CLASS_HID_110a3] = 630,
+ [BNXT_ULP_CLASS_HID_14067] = 631,
+ [BNXT_ULP_CLASS_HID_15c67] = 632,
+ [BNXT_ULP_CLASS_HID_12665] = 633,
+ [BNXT_ULP_CLASS_HID_13265] = 634,
+ [BNXT_ULP_CLASS_HID_16269] = 635,
+ [BNXT_ULP_CLASS_HID_17e69] = 636,
+ [BNXT_ULP_CLASS_HID_1133d] = 637,
+ [BNXT_ULP_CLASS_HID_10eff] = 638,
+ [BNXT_ULP_CLASS_HID_15ed9] = 639,
+ [BNXT_ULP_CLASS_HID_14a9b] = 640,
+ [BNXT_ULP_CLASS_HID_13d2f] = 641,
+ [BNXT_ULP_CLASS_HID_128e9] = 642,
+ [BNXT_ULP_CLASS_HID_178cb] = 643,
+ [BNXT_ULP_CLASS_HID_1748d] = 644,
+ [BNXT_ULP_CLASS_HID_109fb] = 645,
+ [BNXT_ULP_CLASS_HID_105bd] = 646,
+ [BNXT_ULP_CLASS_HID_155bf] = 647,
+ [BNXT_ULP_CLASS_HID_14179] = 648,
+ [BNXT_ULP_CLASS_HID_12bed] = 649,
+ [BNXT_ULP_CLASS_HID_127af] = 650,
+ [BNXT_ULP_CLASS_HID_177a9] = 651,
+ [BNXT_ULP_CLASS_HID_1636b] = 652,
+ [BNXT_ULP_CLASS_HID_1046d] = 653,
+ [BNXT_ULP_CLASS_HID_1104d] = 654,
+ [BNXT_ULP_CLASS_HID_14009] = 655,
+ [BNXT_ULP_CLASS_HID_15c69] = 656,
+ [BNXT_ULP_CLASS_HID_1260f] = 657,
+ [BNXT_ULP_CLASS_HID_1326f] = 658,
+ [BNXT_ULP_CLASS_HID_1622b] = 659,
+ [BNXT_ULP_CLASS_HID_17e0b] = 660,
+ [BNXT_ULP_CLASS_HID_11369] = 661,
+ [BNXT_ULP_CLASS_HID_10f2b] = 662,
+ [BNXT_ULP_CLASS_HID_15f6d] = 663,
+ [BNXT_ULP_CLASS_HID_14b2f] = 664,
+ [BNXT_ULP_CLASS_HID_13d6b] = 665,
+ [BNXT_ULP_CLASS_HID_1292d] = 666,
+ [BNXT_ULP_CLASS_HID_1792f] = 667,
+ [BNXT_ULP_CLASS_HID_174e9] = 668,
+ [BNXT_ULP_CLASS_HID_119e1] = 669,
+ [BNXT_ULP_CLASS_HID_115a3] = 670,
+ [BNXT_ULP_CLASS_HID_14563] = 671,
+ [BNXT_ULP_CLASS_HID_15143] = 672,
+ [BNXT_ULP_CLASS_HID_13b93] = 673,
+ [BNXT_ULP_CLASS_HID_13751] = 674,
+ [BNXT_ULP_CLASS_HID_16769] = 675,
+ [BNXT_ULP_CLASS_HID_17349] = 676,
+ [BNXT_ULP_CLASS_HID_114ab] = 677,
+ [BNXT_ULP_CLASS_HID_10061] = 678,
+ [BNXT_ULP_CLASS_HID_15063] = 679,
+ [BNXT_ULP_CLASS_HID_14c21] = 680,
+ [BNXT_ULP_CLASS_HID_13671] = 681,
+ [BNXT_ULP_CLASS_HID_12233] = 682,
+ [BNXT_ULP_CLASS_HID_17271] = 683,
+ [BNXT_ULP_CLASS_HID_16e33] = 684,
+ [BNXT_ULP_CLASS_HID_102c1] = 685,
+ [BNXT_ULP_CLASS_HID_11f21] = 686,
+ [BNXT_ULP_CLASS_HID_14ee1] = 687,
+ [BNXT_ULP_CLASS_HID_15ac1] = 688,
+ [BNXT_ULP_CLASS_HID_12cc3] = 689,
+ [BNXT_ULP_CLASS_HID_13923] = 690,
+ [BNXT_ULP_CLASS_HID_168e3] = 691,
+ [BNXT_ULP_CLASS_HID_164a9] = 692,
+ [BNXT_ULP_CLASS_HID_11e29] = 693,
+ [BNXT_ULP_CLASS_HID_115eb] = 694,
+ [BNXT_ULP_CLASS_HID_145a3] = 695,
+ [BNXT_ULP_CLASS_HID_151a3] = 696,
+ [BNXT_ULP_CLASS_HID_1382b] = 697,
+ [BNXT_ULP_CLASS_HID_137e1] = 698,
+ [BNXT_ULP_CLASS_HID_167a1] = 699,
+ [BNXT_ULP_CLASS_HID_173a1] = 700,
+ [BNXT_ULP_CLASS_HID_11449] = 701,
+ [BNXT_ULP_CLASS_HID_1000b] = 702,
+ [BNXT_ULP_CLASS_HID_15069] = 703,
+ [BNXT_ULP_CLASS_HID_14c2b] = 704,
+ [BNXT_ULP_CLASS_HID_1367b] = 705,
+ [BNXT_ULP_CLASS_HID_12239] = 706,
+ [BNXT_ULP_CLASS_HID_1721b] = 707,
+ [BNXT_ULP_CLASS_HID_169d9] = 708,
+ [BNXT_ULP_CLASS_HID_1033b] = 709,
+ [BNXT_ULP_CLASS_HID_11f3b] = 710,
+ [BNXT_ULP_CLASS_HID_14f2b] = 711,
+ [BNXT_ULP_CLASS_HID_15b2b] = 712,
+ [BNXT_ULP_CLASS_HID_12d39] = 713,
+ [BNXT_ULP_CLASS_HID_13939] = 714,
+ [BNXT_ULP_CLASS_HID_168f9] = 715,
+ [BNXT_ULP_CLASS_HID_164bb] = 716,
+ [BNXT_ULP_CLASS_HID_119cb] = 717,
+ [BNXT_ULP_CLASS_HID_11589] = 718,
+ [BNXT_ULP_CLASS_HID_14549] = 719,
+ [BNXT_ULP_CLASS_HID_151a9] = 720,
+ [BNXT_ULP_CLASS_HID_13bc9] = 721,
+ [BNXT_ULP_CLASS_HID_1378b] = 722,
+ [BNXT_ULP_CLASS_HID_1674b] = 723,
+ [BNXT_ULP_CLASS_HID_173ab] = 724,
+ [BNXT_ULP_CLASS_HID_114a9] = 725,
+ [BNXT_ULP_CLASS_HID_1006b] = 726,
+ [BNXT_ULP_CLASS_HID_150a9] = 727,
+ [BNXT_ULP_CLASS_HID_14c6b] = 728,
+ [BNXT_ULP_CLASS_HID_136ab] = 729,
+ [BNXT_ULP_CLASS_HID_12269] = 730,
+ [BNXT_ULP_CLASS_HID_172ab] = 731,
+ [BNXT_ULP_CLASS_HID_16e69] = 732,
+ [BNXT_ULP_CLASS_HID_402d2] = 733,
+ [BNXT_ULP_CLASS_HID_412ee] = 734,
+ [BNXT_ULP_CLASS_HID_512a2] = 735,
+ [BNXT_ULP_CLASS_HID_50dd8] = 736,
+ [BNXT_ULP_CLASS_HID_48aea] = 737,
+ [BNXT_ULP_CLASS_HID_48500] = 738,
+ [BNXT_ULP_CLASS_HID_585d4] = 739,
+ [BNXT_ULP_CLASS_HID_59590] = 740,
+ [BNXT_ULP_CLASS_HID_41936] = 741,
+ [BNXT_ULP_CLASS_HID_409ac] = 742,
+ [BNXT_ULP_CLASS_HID_50860] = 743,
+ [BNXT_ULP_CLASS_HID_5183c] = 744,
+ [BNXT_ULP_CLASS_HID_481a8] = 745,
+ [BNXT_ULP_CLASS_HID_49064] = 746,
+ [BNXT_ULP_CLASS_HID_59038] = 747,
+ [BNXT_ULP_CLASS_HID_58376] = 748,
+ [BNXT_ULP_CLASS_HID_414a0] = 749,
+ [BNXT_ULP_CLASS_HID_407ce] = 750,
+ [BNXT_ULP_CLASS_HID_50782] = 751,
+ [BNXT_ULP_CLASS_HID_517ae] = 752,
+ [BNXT_ULP_CLASS_HID_49f68] = 753,
+ [BNXT_ULP_CLASS_HID_48f86] = 754,
+ [BNXT_ULP_CLASS_HID_58faa] = 755,
+ [BNXT_ULP_CLASS_HID_59e66] = 756,
+ [BNXT_ULP_CLASS_HID_40266] = 757,
+ [BNXT_ULP_CLASS_HID_41222] = 758,
+ [BNXT_ULP_CLASS_HID_512e6] = 759,
+ [BNXT_ULP_CLASS_HID_50d6c] = 760,
+ [BNXT_ULP_CLASS_HID_48a2e] = 761,
+ [BNXT_ULP_CLASS_HID_48564] = 762,
+ [BNXT_ULP_CLASS_HID_58568] = 763,
+ [BNXT_ULP_CLASS_HID_59524] = 764,
+ [BNXT_ULP_CLASS_HID_419d8] = 765,
+ [BNXT_ULP_CLASS_HID_4087e] = 766,
+ [BNXT_ULP_CLASS_HID_5080a] = 767,
+ [BNXT_ULP_CLASS_HID_518ce] = 768,
+ [BNXT_ULP_CLASS_HID_4807a] = 769,
+ [BNXT_ULP_CLASS_HID_4900e] = 770,
+ [BNXT_ULP_CLASS_HID_590ca] = 771,
+ [BNXT_ULP_CLASS_HID_58378] = 772,
+ [BNXT_ULP_CLASS_HID_414be] = 773,
+ [BNXT_ULP_CLASS_HID_4073c] = 774,
+ [BNXT_ULP_CLASS_HID_507e8] = 775,
+ [BNXT_ULP_CLASS_HID_517ac] = 776,
+ [BNXT_ULP_CLASS_HID_49f7e] = 777,
+ [BNXT_ULP_CLASS_HID_48fec] = 778,
+ [BNXT_ULP_CLASS_HID_58fa8] = 779,
+ [BNXT_ULP_CLASS_HID_59e7c] = 780,
+ [BNXT_ULP_CLASS_HID_40208] = 781,
+ [BNXT_ULP_CLASS_HID_412cc] = 782,
+ [BNXT_ULP_CLASS_HID_51288] = 783,
+ [BNXT_ULP_CLASS_HID_50d2e] = 784,
+ [BNXT_ULP_CLASS_HID_48ac8] = 785,
+ [BNXT_ULP_CLASS_HID_4856e] = 786,
+ [BNXT_ULP_CLASS_HID_5852a] = 787,
+ [BNXT_ULP_CLASS_HID_595ce] = 788,
+ [BNXT_ULP_CLASS_HID_4196c] = 789,
+ [BNXT_ULP_CLASS_HID_409aa] = 790,
+ [BNXT_ULP_CLASS_HID_5086e] = 791,
+ [BNXT_ULP_CLASS_HID_5182a] = 792,
+ [BNXT_ULP_CLASS_HID_481ae] = 793,
+ [BNXT_ULP_CLASS_HID_4906a] = 794,
+ [BNXT_ULP_CLASS_HID_5902e] = 795,
+ [BNXT_ULP_CLASS_HID_580ac] = 796,
+ [BNXT_ULP_CLASS_HID_40766] = 797,
+ [BNXT_ULP_CLASS_HID_41726] = 798,
+ [BNXT_ULP_CLASS_HID_517f6] = 799,
+ [BNXT_ULP_CLASS_HID_5066c] = 800,
+ [BNXT_ULP_CLASS_HID_48f3e] = 801,
+ [BNXT_ULP_CLASS_HID_49ffe] = 802,
+ [BNXT_ULP_CLASS_HID_59f8e] = 803,
+ [BNXT_ULP_CLASS_HID_58e24] = 804,
+ [BNXT_ULP_CLASS_HID_4126e] = 805,
+ [BNXT_ULP_CLASS_HID_402e4] = 806,
+ [BNXT_ULP_CLASS_HID_502b4] = 807,
+ [BNXT_ULP_CLASS_HID_51d74] = 808,
+ [BNXT_ULP_CLASS_HID_49a26] = 809,
+ [BNXT_ULP_CLASS_HID_48abc] = 810,
+ [BNXT_ULP_CLASS_HID_5956c] = 811,
+ [BNXT_ULP_CLASS_HID_585ee] = 812,
+ [BNXT_ULP_CLASS_HID_409e4] = 813,
+ [BNXT_ULP_CLASS_HID_419a4] = 814,
+ [BNXT_ULP_CLASS_HID_51844] = 815,
+ [BNXT_ULP_CLASS_HID_508e6] = 816,
+ [BNXT_ULP_CLASS_HID_4918c] = 817,
+ [BNXT_ULP_CLASS_HID_4802e] = 818,
+ [BNXT_ULP_CLASS_HID_580ee] = 819,
+ [BNXT_ULP_CLASS_HID_590ae] = 820,
+ [BNXT_ULP_CLASS_HID_404ae] = 821,
+ [BNXT_ULP_CLASS_HID_41766] = 822,
+ [BNXT_ULP_CLASS_HID_5172e] = 823,
+ [BNXT_ULP_CLASS_HID_507a4] = 824,
+ [BNXT_ULP_CLASS_HID_48f66] = 825,
+ [BNXT_ULP_CLASS_HID_49f2e] = 826,
+ [BNXT_ULP_CLASS_HID_59fe6] = 827,
+ [BNXT_ULP_CLASS_HID_58e6c] = 828,
+ [BNXT_ULP_CLASS_HID_4126c] = 829,
+ [BNXT_ULP_CLASS_HID_4028e] = 830,
+ [BNXT_ULP_CLASS_HID_50d5e] = 831,
+ [BNXT_ULP_CLASS_HID_51d1e] = 832,
+ [BNXT_ULP_CLASS_HID_49a2c] = 833,
+ [BNXT_ULP_CLASS_HID_4954e] = 834,
+ [BNXT_ULP_CLASS_HID_5951e] = 835,
+ [BNXT_ULP_CLASS_HID_5858c] = 836,
+ [BNXT_ULP_CLASS_HID_409fe] = 837,
+ [BNXT_ULP_CLASS_HID_419ee] = 838,
+ [BNXT_ULP_CLASS_HID_519ae] = 839,
+ [BNXT_ULP_CLASS_HID_508fc] = 840,
+ [BNXT_ULP_CLASS_HID_491ee] = 841,
+ [BNXT_ULP_CLASS_HID_4802c] = 842,
+ [BNXT_ULP_CLASS_HID_580fc] = 843,
+ [BNXT_ULP_CLASS_HID_590bc] = 844,
+ [BNXT_ULP_CLASS_HID_4074c] = 845,
+ [BNXT_ULP_CLASS_HID_4170c] = 846,
+ [BNXT_ULP_CLASS_HID_5172c] = 847,
+ [BNXT_ULP_CLASS_HID_5064e] = 848,
+ [BNXT_ULP_CLASS_HID_48f0c] = 849,
+ [BNXT_ULP_CLASS_HID_49fcc] = 850,
+ [BNXT_ULP_CLASS_HID_59fec] = 851,
+ [BNXT_ULP_CLASS_HID_58e0e] = 852,
+ [BNXT_ULP_CLASS_HID_413ac] = 853,
+ [BNXT_ULP_CLASS_HID_402ee] = 854,
+ [BNXT_ULP_CLASS_HID_502ae] = 855,
+ [BNXT_ULP_CLASS_HID_512ae] = 856,
+ [BNXT_ULP_CLASS_HID_49a6c] = 857,
+ [BNXT_ULP_CLASS_HID_48aae] = 858,
+ [BNXT_ULP_CLASS_HID_58aae] = 859,
+ [BNXT_ULP_CLASS_HID_585ec] = 860,
+ [BNXT_ULP_CLASS_HID_104ae] = 861,
+ [BNXT_ULP_CLASS_HID_1108e] = 862,
+ [BNXT_ULP_CLASS_HID_140b2] = 863,
+ [BNXT_ULP_CLASS_HID_15c92] = 864,
+ [BNXT_ULP_CLASS_HID_126a0] = 865,
+ [BNXT_ULP_CLASS_HID_13280] = 866,
+ [BNXT_ULP_CLASS_HID_16d44] = 867,
+ [BNXT_ULP_CLASS_HID_17ea4] = 868,
+ [BNXT_ULP_CLASS_HID_113a4] = 869,
+ [BNXT_ULP_CLASS_HID_10e66] = 870,
+ [BNXT_ULP_CLASS_HID_15e40] = 871,
+ [BNXT_ULP_CLASS_HID_14a02] = 872,
+ [BNXT_ULP_CLASS_HID_13db6] = 873,
+ [BNXT_ULP_CLASS_HID_12870] = 874,
+ [BNXT_ULP_CLASS_HID_17852] = 875,
+ [BNXT_ULP_CLASS_HID_17414] = 876,
+ [BNXT_ULP_CLASS_HID_11978] = 877,
+ [BNXT_ULP_CLASS_HID_1153a] = 878,
+ [BNXT_ULP_CLASS_HID_145fa] = 879,
+ [BNXT_ULP_CLASS_HID_151da] = 880,
+ [BNXT_ULP_CLASS_HID_13b0a] = 881,
+ [BNXT_ULP_CLASS_HID_137c8] = 882,
+ [BNXT_ULP_CLASS_HID_167f0] = 883,
+ [BNXT_ULP_CLASS_HID_173d0] = 884,
+ [BNXT_ULP_CLASS_HID_114d0] = 885,
+ [BNXT_ULP_CLASS_HID_10092] = 886,
+ [BNXT_ULP_CLASS_HID_150f0] = 887,
+ [BNXT_ULP_CLASS_HID_14cb2] = 888,
+ [BNXT_ULP_CLASS_HID_136e2] = 889,
+ [BNXT_ULP_CLASS_HID_122a0] = 890,
+ [BNXT_ULP_CLASS_HID_17282] = 891,
+ [BNXT_ULP_CLASS_HID_16940] = 892,
+ [BNXT_ULP_CLASS_HID_11b90] = 893,
+ [BNXT_ULP_CLASS_HID_11654] = 894,
+ [BNXT_ULP_CLASS_HID_14618] = 895,
+ [BNXT_ULP_CLASS_HID_15278] = 896,
+ [BNXT_ULP_CLASS_HID_12404] = 897,
+ [BNXT_ULP_CLASS_HID_13064] = 898,
+ [BNXT_ULP_CLASS_HID_16028] = 899,
+ [BNXT_ULP_CLASS_HID_17c08] = 900,
+ [BNXT_ULP_CLASS_HID_11100] = 901,
+ [BNXT_ULP_CLASS_HID_10dc4] = 902,
+ [BNXT_ULP_CLASS_HID_15d24] = 903,
+ [BNXT_ULP_CLASS_HID_149d0] = 904,
+ [BNXT_ULP_CLASS_HID_13314] = 905,
+ [BNXT_ULP_CLASS_HID_12fd4] = 906,
+ [BNXT_ULP_CLASS_HID_17f20] = 907,
+ [BNXT_ULP_CLASS_HID_16be0] = 908,
+ [BNXT_ULP_CLASS_HID_11cd8] = 909,
+ [BNXT_ULP_CLASS_HID_10880] = 910,
+ [BNXT_ULP_CLASS_HID_158e0] = 911,
+ [BNXT_ULP_CLASS_HID_154a0] = 912,
+ [BNXT_ULP_CLASS_HID_13ed0] = 913,
+ [BNXT_ULP_CLASS_HID_12a90] = 914,
+ [BNXT_ULP_CLASS_HID_16550] = 915,
+ [BNXT_ULP_CLASS_HID_176b0] = 916,
+ [BNXT_ULP_CLASS_HID_10bb0] = 917,
+ [BNXT_ULP_CLASS_HID_10670] = 918,
+ [BNXT_ULP_CLASS_HID_15650] = 919,
+ [BNXT_ULP_CLASS_HID_14210] = 920,
+ [BNXT_ULP_CLASS_HID_13440] = 921,
+ [BNXT_ULP_CLASS_HID_12000] = 922,
+ [BNXT_ULP_CLASS_HID_17060] = 923,
+ [BNXT_ULP_CLASS_HID_16c20] = 924,
+ [BNXT_ULP_CLASS_HID_11511] = 925,
+ [BNXT_ULP_CLASS_HID_101d3] = 926,
+ [BNXT_ULP_CLASS_HID_15135] = 927,
+ [BNXT_ULP_CLASS_HID_14df7] = 928,
+ [BNXT_ULP_CLASS_HID_13723] = 929,
+ [BNXT_ULP_CLASS_HID_123e5] = 930,
+ [BNXT_ULP_CLASS_HID_173c7] = 931,
+ [BNXT_ULP_CLASS_HID_16f89] = 932,
+ [BNXT_ULP_CLASS_HID_10081] = 933,
+ [BNXT_ULP_CLASS_HID_11ce1] = 934,
+ [BNXT_ULP_CLASS_HID_14ca5] = 935,
+ [BNXT_ULP_CLASS_HID_15885] = 936,
+ [BNXT_ULP_CLASS_HID_12293] = 937,
+ [BNXT_ULP_CLASS_HID_13ef3] = 938,
+ [BNXT_ULP_CLASS_HID_16eb7] = 939,
+ [BNXT_ULP_CLASS_HID_16561] = 940,
+ [BNXT_ULP_CLASS_HID_10e59] = 941,
+ [BNXT_ULP_CLASS_HID_11bb9] = 942,
+ [BNXT_ULP_CLASS_HID_14a61] = 943,
+ [BNXT_ULP_CLASS_HID_14623] = 944,
+ [BNXT_ULP_CLASS_HID_1286b] = 945,
+ [BNXT_ULP_CLASS_HID_12411] = 946,
+ [BNXT_ULP_CLASS_HID_17473] = 947,
+ [BNXT_ULP_CLASS_HID_16031] = 948,
+ [BNXT_ULP_CLASS_HID_10531] = 949,
+ [BNXT_ULP_CLASS_HID_11111] = 950,
+ [BNXT_ULP_CLASS_HID_141d1] = 951,
+ [BNXT_ULP_CLASS_HID_15d31] = 952,
+ [BNXT_ULP_CLASS_HID_127c3] = 953,
+ [BNXT_ULP_CLASS_HID_13323] = 954,
+ [BNXT_ULP_CLASS_HID_163e3] = 955,
+ [BNXT_ULP_CLASS_HID_17fc3] = 956,
+ [BNXT_ULP_CLASS_HID_108f5] = 957,
+ [BNXT_ULP_CLASS_HID_104b9] = 958,
+ [BNXT_ULP_CLASS_HID_15499] = 959,
+ [BNXT_ULP_CLASS_HID_1435d] = 960,
+ [BNXT_ULP_CLASS_HID_12a89] = 961,
+ [BNXT_ULP_CLASS_HID_12149] = 962,
+ [BNXT_ULP_CLASS_HID_176ad] = 963,
+ [BNXT_ULP_CLASS_HID_16d6d] = 964,
+ [BNXT_ULP_CLASS_HID_10665] = 965,
+ [BNXT_ULP_CLASS_HID_11245] = 966,
+ [BNXT_ULP_CLASS_HID_14271] = 967,
+ [BNXT_ULP_CLASS_HID_15e51] = 968,
+ [BNXT_ULP_CLASS_HID_12061] = 969,
+ [BNXT_ULP_CLASS_HID_13c41] = 970,
+ [BNXT_ULP_CLASS_HID_16c05] = 971,
+ [BNXT_ULP_CLASS_HID_17865] = 972,
+ [BNXT_ULP_CLASS_HID_10d21] = 973,
+ [BNXT_ULP_CLASS_HID_11901] = 974,
+ [BNXT_ULP_CLASS_HID_149c1] = 975,
+ [BNXT_ULP_CLASS_HID_14589] = 976,
+ [BNXT_ULP_CLASS_HID_12f31] = 977,
+ [BNXT_ULP_CLASS_HID_13b11] = 978,
+ [BNXT_ULP_CLASS_HID_16bd9] = 979,
+ [BNXT_ULP_CLASS_HID_16799] = 980,
+ [BNXT_ULP_CLASS_HID_11831] = 981,
+ [BNXT_ULP_CLASS_HID_114f1] = 982,
+ [BNXT_ULP_CLASS_HID_144b1] = 983,
+ [BNXT_ULP_CLASS_HID_15091] = 984,
+ [BNXT_ULP_CLASS_HID_13ac1] = 985,
+ [BNXT_ULP_CLASS_HID_13681] = 986,
+ [BNXT_ULP_CLASS_HID_166b1] = 987,
+ [BNXT_ULP_CLASS_HID_17291] = 988,
+ [BNXT_ULP_CLASS_HID_4007d] = 989,
+ [BNXT_ULP_CLASS_HID_41041] = 990,
+ [BNXT_ULP_CLASS_HID_5100d] = 991,
+ [BNXT_ULP_CLASS_HID_50f77] = 992,
+ [BNXT_ULP_CLASS_HID_48845] = 993,
+ [BNXT_ULP_CLASS_HID_487af] = 994,
+ [BNXT_ULP_CLASS_HID_5877b] = 995,
+ [BNXT_ULP_CLASS_HID_5973f] = 996,
+ [BNXT_ULP_CLASS_HID_41c31] = 997,
+ [BNXT_ULP_CLASS_HID_40b1b] = 998,
+ [BNXT_ULP_CLASS_HID_50b67] = 999,
+ [BNXT_ULP_CLASS_HID_51b2b] = 1000,
+ [BNXT_ULP_CLASS_HID_4831f] = 1001,
+ [BNXT_ULP_CLASS_HID_49363] = 1002,
+ [BNXT_ULP_CLASS_HID_5932f] = 1003,
+ [BNXT_ULP_CLASS_HID_58211] = 1004,
+ [BNXT_ULP_CLASS_HID_4161b] = 1005,
+ [BNXT_ULP_CLASS_HID_405bd] = 1006,
+ [BNXT_ULP_CLASS_HID_50589] = 1007,
+ [BNXT_ULP_CLASS_HID_5150d] = 1008,
+ [BNXT_ULP_CLASS_HID_49e23] = 1009,
+ [BNXT_ULP_CLASS_HID_48d85] = 1010,
+ [BNXT_ULP_CLASS_HID_58d11] = 1011,
+ [BNXT_ULP_CLASS_HID_59d15] = 1012,
+ [BNXT_ULP_CLASS_HID_4012d] = 1013,
+ [BNXT_ULP_CLASS_HID_41131] = 1014,
+ [BNXT_ULP_CLASS_HID_5113d] = 1015,
+ [BNXT_ULP_CLASS_HID_50027] = 1016,
+ [BNXT_ULP_CLASS_HID_48935] = 1017,
+ [BNXT_ULP_CLASS_HID_49939] = 1018,
+ [BNXT_ULP_CLASS_HID_59905] = 1019,
+ [BNXT_ULP_CLASS_HID_5882f] = 1020,
+ [BNXT_ULP_CLASS_HID_41b99] = 1021,
+ [BNXT_ULP_CLASS_HID_40b03] = 1022,
+ [BNXT_ULP_CLASS_HID_50acf] = 1023,
+ [BNXT_ULP_CLASS_HID_51a93] = 1024,
+ [BNXT_ULP_CLASS_HID_48307] = 1025,
+ [BNXT_ULP_CLASS_HID_492cb] = 1026,
+ [BNXT_ULP_CLASS_HID_59297] = 1027,
+ [BNXT_ULP_CLASS_HID_581d9] = 1028,
+ [BNXT_ULP_CLASS_HID_41653] = 1029,
+ [BNXT_ULP_CLASS_HID_40655] = 1030,
+ [BNXT_ULP_CLASS_HID_50601] = 1031,
+ [BNXT_ULP_CLASS_HID_51545] = 1032,
+ [BNXT_ULP_CLASS_HID_49e1b] = 1033,
+ [BNXT_ULP_CLASS_HID_48e1d] = 1034,
+ [BNXT_ULP_CLASS_HID_58d49] = 1035,
+ [BNXT_ULP_CLASS_HID_59d0d] = 1036,
+ [BNXT_ULP_CLASS_HID_40115] = 1037,
+ [BNXT_ULP_CLASS_HID_41099] = 1038,
+ [BNXT_ULP_CLASS_HID_51085] = 1039,
+ [BNXT_ULP_CLASS_HID_5000f] = 1040,
+ [BNXT_ULP_CLASS_HID_4889d] = 1041,
+ [BNXT_ULP_CLASS_HID_49881] = 1042,
+ [BNXT_ULP_CLASS_HID_5980d] = 1043,
+ [BNXT_ULP_CLASS_HID_59797] = 1044,
+ [BNXT_ULP_CLASS_HID_41c09] = 1045,
+ [BNXT_ULP_CLASS_HID_40c13] = 1046,
+ [BNXT_ULP_CLASS_HID_50b1f] = 1047,
+ [BNXT_ULP_CLASS_HID_51b03] = 1048,
+ [BNXT_ULP_CLASS_HID_48417] = 1049,
+ [BNXT_ULP_CLASS_HID_4931b] = 1050,
+ [BNXT_ULP_CLASS_HID_59307] = 1051,
+ [BNXT_ULP_CLASS_HID_58309] = 1052,
+ [BNXT_ULP_CLASS_HID_4160f] = 1053,
+ [BNXT_ULP_CLASS_HID_40561] = 1054,
+ [BNXT_ULP_CLASS_HID_5052d] = 1055,
+ [BNXT_ULP_CLASS_HID_51501] = 1056,
+ [BNXT_ULP_CLASS_HID_49dc7] = 1057,
+ [BNXT_ULP_CLASS_HID_48d29] = 1058,
+ [BNXT_ULP_CLASS_HID_58d05] = 1059,
+ [BNXT_ULP_CLASS_HID_59cc9] = 1060,
+ [BNXT_ULP_CLASS_HID_40161] = 1061,
+ [BNXT_ULP_CLASS_HID_41125] = 1062,
+ [BNXT_ULP_CLASS_HID_51061] = 1063,
+ [BNXT_ULP_CLASS_HID_5004b] = 1064,
+ [BNXT_ULP_CLASS_HID_48929] = 1065,
+ [BNXT_ULP_CLASS_HID_4986d] = 1066,
+ [BNXT_ULP_CLASS_HID_59829] = 1067,
+ [BNXT_ULP_CLASS_HID_58823] = 1068,
+ [BNXT_ULP_CLASS_HID_41ba5] = 1069,
+ [BNXT_ULP_CLASS_HID_40b0f] = 1070,
+ [BNXT_ULP_CLASS_HID_50b0b] = 1071,
+ [BNXT_ULP_CLASS_HID_51a8f] = 1072,
+ [BNXT_ULP_CLASS_HID_48303] = 1073,
+ [BNXT_ULP_CLASS_HID_49307] = 1074,
+ [BNXT_ULP_CLASS_HID_592a3] = 1075,
+ [BNXT_ULP_CLASS_HID_58205] = 1076,
+ [BNXT_ULP_CLASS_HID_4172f] = 1077,
+ [BNXT_ULP_CLASS_HID_40621] = 1078,
+ [BNXT_ULP_CLASS_HID_5062d] = 1079,
+ [BNXT_ULP_CLASS_HID_51621] = 1080,
+ [BNXT_ULP_CLASS_HID_49f07] = 1081,
+ [BNXT_ULP_CLASS_HID_48e29] = 1082,
+ [BNXT_ULP_CLASS_HID_58e25] = 1083,
+ [BNXT_ULP_CLASS_HID_59d29] = 1084,
+ [BNXT_ULP_CLASS_HID_400c9] = 1085,
+ [BNXT_ULP_CLASS_HID_4108d] = 1086,
+ [BNXT_ULP_CLASS_HID_51049] = 1087,
+ [BNXT_ULP_CLASS_HID_50fc3] = 1088,
+ [BNXT_ULP_CLASS_HID_48881] = 1089,
+ [BNXT_ULP_CLASS_HID_487cb] = 1090,
+ [BNXT_ULP_CLASS_HID_587c7] = 1091,
+ [BNXT_ULP_CLASS_HID_5978b] = 1092,
+ [BNXT_ULP_CLASS_HID_41c4d] = 1093,
+ [BNXT_ULP_CLASS_HID_40b47] = 1094,
+ [BNXT_ULP_CLASS_HID_50b03] = 1095,
+ [BNXT_ULP_CLASS_HID_51b47] = 1096,
+ [BNXT_ULP_CLASS_HID_4834b] = 1097,
+ [BNXT_ULP_CLASS_HID_4930f] = 1098,
+ [BNXT_ULP_CLASS_HID_5934b] = 1099,
+ [BNXT_ULP_CLASS_HID_5824d] = 1100,
+ [BNXT_ULP_CLASS_HID_41687] = 1101,
+ [BNXT_ULP_CLASS_HID_40609] = 1102,
+ [BNXT_ULP_CLASS_HID_50585] = 1103,
+ [BNXT_ULP_CLASS_HID_51589] = 1104,
+ [BNXT_ULP_CLASS_HID_49e0f] = 1105,
+ [BNXT_ULP_CLASS_HID_48d81] = 1106,
+ [BNXT_ULP_CLASS_HID_58d8d] = 1107,
+ [BNXT_ULP_CLASS_HID_59d01] = 1108,
+ [BNXT_ULP_CLASS_HID_40109] = 1109,
+ [BNXT_ULP_CLASS_HID_4110d] = 1110,
+ [BNXT_ULP_CLASS_HID_51109] = 1111,
+ [BNXT_ULP_CLASS_HID_50003] = 1112,
+ [BNXT_ULP_CLASS_HID_48901] = 1113,
+ [BNXT_ULP_CLASS_HID_49905] = 1114,
+ [BNXT_ULP_CLASS_HID_59901] = 1115,
+ [BNXT_ULP_CLASS_HID_5880b] = 1116,
+ [BNXT_ULP_CLASS_HID_10619] = 1117,
+ [BNXT_ULP_CLASS_HID_11239] = 1118,
+ [BNXT_ULP_CLASS_HID_14205] = 1119,
+ [BNXT_ULP_CLASS_HID_15e25] = 1120,
+ [BNXT_ULP_CLASS_HID_12417] = 1121,
+ [BNXT_ULP_CLASS_HID_13037] = 1122,
+ [BNXT_ULP_CLASS_HID_16ff3] = 1123,
+ [BNXT_ULP_CLASS_HID_17c13] = 1124,
+ [BNXT_ULP_CLASS_HID_1111d] = 1125,
+ [BNXT_ULP_CLASS_HID_10cdb] = 1126,
+ [BNXT_ULP_CLASS_HID_15d19] = 1127,
+ [BNXT_ULP_CLASS_HID_148c7] = 1128,
+ [BNXT_ULP_CLASS_HID_13f0b] = 1129,
+ [BNXT_ULP_CLASS_HID_12ac9] = 1130,
+ [BNXT_ULP_CLASS_HID_17b17] = 1131,
+ [BNXT_ULP_CLASS_HID_176d5] = 1132,
+ [BNXT_ULP_CLASS_HID_10bab] = 1133,
+ [BNXT_ULP_CLASS_HID_10769] = 1134,
+ [BNXT_ULP_CLASS_HID_15787] = 1135,
+ [BNXT_ULP_CLASS_HID_14345] = 1136,
+ [BNXT_ULP_CLASS_HID_12989] = 1137,
+ [BNXT_ULP_CLASS_HID_12567] = 1138,
+ [BNXT_ULP_CLASS_HID_17585] = 1139,
+ [BNXT_ULP_CLASS_HID_16143] = 1140,
+ [BNXT_ULP_CLASS_HID_1064d] = 1141,
+ [BNXT_ULP_CLASS_HID_1128d] = 1142,
+ [BNXT_ULP_CLASS_HID_14249] = 1143,
+ [BNXT_ULP_CLASS_HID_15e49] = 1144,
+ [BNXT_ULP_CLASS_HID_1244b] = 1145,
+ [BNXT_ULP_CLASS_HID_1304b] = 1146,
+ [BNXT_ULP_CLASS_HID_16047] = 1147,
+ [BNXT_ULP_CLASS_HID_17c47] = 1148,
+ [BNXT_ULP_CLASS_HID_11113] = 1149,
+ [BNXT_ULP_CLASS_HID_10cd1] = 1150,
+ [BNXT_ULP_CLASS_HID_15cf7] = 1151,
+ [BNXT_ULP_CLASS_HID_148b5] = 1152,
+ [BNXT_ULP_CLASS_HID_13f01] = 1153,
+ [BNXT_ULP_CLASS_HID_12ac7] = 1154,
+ [BNXT_ULP_CLASS_HID_17ae5] = 1155,
+ [BNXT_ULP_CLASS_HID_176a3] = 1156,
+ [BNXT_ULP_CLASS_HID_10bd5] = 1157,
+ [BNXT_ULP_CLASS_HID_10793] = 1158,
+ [BNXT_ULP_CLASS_HID_15791] = 1159,
+ [BNXT_ULP_CLASS_HID_14357] = 1160,
+ [BNXT_ULP_CLASS_HID_129c3] = 1161,
+ [BNXT_ULP_CLASS_HID_12581] = 1162,
+ [BNXT_ULP_CLASS_HID_17587] = 1163,
+ [BNXT_ULP_CLASS_HID_16145] = 1164,
+ [BNXT_ULP_CLASS_HID_10643] = 1165,
+ [BNXT_ULP_CLASS_HID_11263] = 1166,
+ [BNXT_ULP_CLASS_HID_14227] = 1167,
+ [BNXT_ULP_CLASS_HID_15e47] = 1168,
+ [BNXT_ULP_CLASS_HID_12421] = 1169,
+ [BNXT_ULP_CLASS_HID_13041] = 1170,
+ [BNXT_ULP_CLASS_HID_16005] = 1171,
+ [BNXT_ULP_CLASS_HID_17c25] = 1172,
+ [BNXT_ULP_CLASS_HID_11147] = 1173,
+ [BNXT_ULP_CLASS_HID_10d05] = 1174,
+ [BNXT_ULP_CLASS_HID_15d43] = 1175,
+ [BNXT_ULP_CLASS_HID_14901] = 1176,
+ [BNXT_ULP_CLASS_HID_13f45] = 1177,
+ [BNXT_ULP_CLASS_HID_12b03] = 1178,
+ [BNXT_ULP_CLASS_HID_17b01] = 1179,
+ [BNXT_ULP_CLASS_HID_176c7] = 1180,
+ [BNXT_ULP_CLASS_HID_11bcf] = 1181,
+ [BNXT_ULP_CLASS_HID_1178d] = 1182,
+ [BNXT_ULP_CLASS_HID_1474d] = 1183,
+ [BNXT_ULP_CLASS_HID_1536d] = 1184,
+ [BNXT_ULP_CLASS_HID_139bd] = 1185,
+ [BNXT_ULP_CLASS_HID_1357f] = 1186,
+ [BNXT_ULP_CLASS_HID_16547] = 1187,
+ [BNXT_ULP_CLASS_HID_17167] = 1188,
+ [BNXT_ULP_CLASS_HID_11685] = 1189,
+ [BNXT_ULP_CLASS_HID_1024f] = 1190,
+ [BNXT_ULP_CLASS_HID_1524d] = 1191,
+ [BNXT_ULP_CLASS_HID_14e0f] = 1192,
+ [BNXT_ULP_CLASS_HID_1345f] = 1193,
+ [BNXT_ULP_CLASS_HID_1201d] = 1194,
+ [BNXT_ULP_CLASS_HID_1705f] = 1195,
+ [BNXT_ULP_CLASS_HID_16c1d] = 1196,
+ [BNXT_ULP_CLASS_HID_100ef] = 1197,
+ [BNXT_ULP_CLASS_HID_11d0f] = 1198,
+ [BNXT_ULP_CLASS_HID_14ccf] = 1199,
+ [BNXT_ULP_CLASS_HID_158ef] = 1200,
+ [BNXT_ULP_CLASS_HID_12eed] = 1201,
+ [BNXT_ULP_CLASS_HID_13b0d] = 1202,
+ [BNXT_ULP_CLASS_HID_16acd] = 1203,
+ [BNXT_ULP_CLASS_HID_16687] = 1204,
+ [BNXT_ULP_CLASS_HID_11c07] = 1205,
+ [BNXT_ULP_CLASS_HID_117c5] = 1206,
+ [BNXT_ULP_CLASS_HID_1478d] = 1207,
+ [BNXT_ULP_CLASS_HID_1538d] = 1208,
+ [BNXT_ULP_CLASS_HID_13a05] = 1209,
+ [BNXT_ULP_CLASS_HID_135cf] = 1210,
+ [BNXT_ULP_CLASS_HID_1658f] = 1211,
+ [BNXT_ULP_CLASS_HID_1718f] = 1212,
+ [BNXT_ULP_CLASS_HID_11667] = 1213,
+ [BNXT_ULP_CLASS_HID_10225] = 1214,
+ [BNXT_ULP_CLASS_HID_15247] = 1215,
+ [BNXT_ULP_CLASS_HID_14e05] = 1216,
+ [BNXT_ULP_CLASS_HID_13455] = 1217,
+ [BNXT_ULP_CLASS_HID_12017] = 1218,
+ [BNXT_ULP_CLASS_HID_17035] = 1219,
+ [BNXT_ULP_CLASS_HID_16bf7] = 1220,
+ [BNXT_ULP_CLASS_HID_10115] = 1221,
+ [BNXT_ULP_CLASS_HID_11d15] = 1222,
+ [BNXT_ULP_CLASS_HID_14d05] = 1223,
+ [BNXT_ULP_CLASS_HID_15905] = 1224,
+ [BNXT_ULP_CLASS_HID_12f17] = 1225,
+ [BNXT_ULP_CLASS_HID_13b17] = 1226,
+ [BNXT_ULP_CLASS_HID_16ad7] = 1227,
+ [BNXT_ULP_CLASS_HID_16695] = 1228,
+ [BNXT_ULP_CLASS_HID_11be5] = 1229,
+ [BNXT_ULP_CLASS_HID_117a7] = 1230,
+ [BNXT_ULP_CLASS_HID_14767] = 1231,
+ [BNXT_ULP_CLASS_HID_15387] = 1232,
+ [BNXT_ULP_CLASS_HID_139e7] = 1233,
+ [BNXT_ULP_CLASS_HID_135a5] = 1234,
+ [BNXT_ULP_CLASS_HID_16565] = 1235,
+ [BNXT_ULP_CLASS_HID_17185] = 1236,
+ [BNXT_ULP_CLASS_HID_11687] = 1237,
+ [BNXT_ULP_CLASS_HID_10245] = 1238,
+ [BNXT_ULP_CLASS_HID_15287] = 1239,
+ [BNXT_ULP_CLASS_HID_14e45] = 1240,
+ [BNXT_ULP_CLASS_HID_13485] = 1241,
+ [BNXT_ULP_CLASS_HID_12047] = 1242,
+ [BNXT_ULP_CLASS_HID_17085] = 1243,
+ [BNXT_ULP_CLASS_HID_16c47] = 1244,
+ [BNXT_ULP_CLASS_HID_400f4] = 1245,
+ [BNXT_ULP_CLASS_HID_410c8] = 1246,
+ [BNXT_ULP_CLASS_HID_51084] = 1247,
+ [BNXT_ULP_CLASS_HID_50ffe] = 1248,
+ [BNXT_ULP_CLASS_HID_488cc] = 1249,
+ [BNXT_ULP_CLASS_HID_48726] = 1250,
+ [BNXT_ULP_CLASS_HID_587f2] = 1251,
+ [BNXT_ULP_CLASS_HID_597b6] = 1252,
+ [BNXT_ULP_CLASS_HID_41b10] = 1253,
+ [BNXT_ULP_CLASS_HID_40b8a] = 1254,
+ [BNXT_ULP_CLASS_HID_50a46] = 1255,
+ [BNXT_ULP_CLASS_HID_51a1a] = 1256,
+ [BNXT_ULP_CLASS_HID_4838e] = 1257,
+ [BNXT_ULP_CLASS_HID_49242] = 1258,
+ [BNXT_ULP_CLASS_HID_5921e] = 1259,
+ [BNXT_ULP_CLASS_HID_58150] = 1260,
+ [BNXT_ULP_CLASS_HID_41686] = 1261,
+ [BNXT_ULP_CLASS_HID_405e8] = 1262,
+ [BNXT_ULP_CLASS_HID_505a4] = 1263,
+ [BNXT_ULP_CLASS_HID_51588] = 1264,
+ [BNXT_ULP_CLASS_HID_49d4e] = 1265,
+ [BNXT_ULP_CLASS_HID_48da0] = 1266,
+ [BNXT_ULP_CLASS_HID_58d8c] = 1267,
+ [BNXT_ULP_CLASS_HID_59c40] = 1268,
+ [BNXT_ULP_CLASS_HID_40040] = 1269,
+ [BNXT_ULP_CLASS_HID_41004] = 1270,
+ [BNXT_ULP_CLASS_HID_510c0] = 1271,
+ [BNXT_ULP_CLASS_HID_50f4a] = 1272,
+ [BNXT_ULP_CLASS_HID_48808] = 1273,
+ [BNXT_ULP_CLASS_HID_48742] = 1274,
+ [BNXT_ULP_CLASS_HID_5874e] = 1275,
+ [BNXT_ULP_CLASS_HID_59702] = 1276,
+ [BNXT_ULP_CLASS_HID_41bfe] = 1277,
+ [BNXT_ULP_CLASS_HID_40a58] = 1278,
+ [BNXT_ULP_CLASS_HID_50a2c] = 1279,
+ [BNXT_ULP_CLASS_HID_51ae8] = 1280,
+ [BNXT_ULP_CLASS_HID_4825c] = 1281,
+ [BNXT_ULP_CLASS_HID_49228] = 1282,
+ [BNXT_ULP_CLASS_HID_592ec] = 1283,
+ [BNXT_ULP_CLASS_HID_5815e] = 1284,
+ [BNXT_ULP_CLASS_HID_41698] = 1285,
+ [BNXT_ULP_CLASS_HID_4051a] = 1286,
+ [BNXT_ULP_CLASS_HID_505ce] = 1287,
+ [BNXT_ULP_CLASS_HID_5158a] = 1288,
+ [BNXT_ULP_CLASS_HID_49d58] = 1289,
+ [BNXT_ULP_CLASS_HID_48dca] = 1290,
+ [BNXT_ULP_CLASS_HID_58d8e] = 1291,
+ [BNXT_ULP_CLASS_HID_59c5a] = 1292,
+ [BNXT_ULP_CLASS_HID_4002e] = 1293,
+ [BNXT_ULP_CLASS_HID_410ea] = 1294,
+ [BNXT_ULP_CLASS_HID_510ae] = 1295,
+ [BNXT_ULP_CLASS_HID_50f08] = 1296,
+ [BNXT_ULP_CLASS_HID_488ee] = 1297,
+ [BNXT_ULP_CLASS_HID_48748] = 1298,
+ [BNXT_ULP_CLASS_HID_5870c] = 1299,
+ [BNXT_ULP_CLASS_HID_597e8] = 1300,
+ [BNXT_ULP_CLASS_HID_41b4a] = 1301,
+ [BNXT_ULP_CLASS_HID_40b8c] = 1302,
+ [BNXT_ULP_CLASS_HID_50a48] = 1303,
+ [BNXT_ULP_CLASS_HID_51a0c] = 1304,
+ [BNXT_ULP_CLASS_HID_48388] = 1305,
+ [BNXT_ULP_CLASS_HID_4924c] = 1306,
+ [BNXT_ULP_CLASS_HID_59208] = 1307,
+ [BNXT_ULP_CLASS_HID_5828a] = 1308,
+ [BNXT_ULP_CLASS_HID_40540] = 1309,
+ [BNXT_ULP_CLASS_HID_41500] = 1310,
+ [BNXT_ULP_CLASS_HID_515d0] = 1311,
+ [BNXT_ULP_CLASS_HID_5044a] = 1312,
+ [BNXT_ULP_CLASS_HID_48d18] = 1313,
+ [BNXT_ULP_CLASS_HID_49dd8] = 1314,
+ [BNXT_ULP_CLASS_HID_59da8] = 1315,
+ [BNXT_ULP_CLASS_HID_58c02] = 1316,
+ [BNXT_ULP_CLASS_HID_41048] = 1317,
+ [BNXT_ULP_CLASS_HID_400c2] = 1318,
+ [BNXT_ULP_CLASS_HID_50092] = 1319,
+ [BNXT_ULP_CLASS_HID_51f52] = 1320,
+ [BNXT_ULP_CLASS_HID_49800] = 1321,
+ [BNXT_ULP_CLASS_HID_4889a] = 1322,
+ [BNXT_ULP_CLASS_HID_5974a] = 1323,
+ [BNXT_ULP_CLASS_HID_587c8] = 1324,
+ [BNXT_ULP_CLASS_HID_40bc2] = 1325,
+ [BNXT_ULP_CLASS_HID_41b82] = 1326,
+ [BNXT_ULP_CLASS_HID_51a62] = 1327,
+ [BNXT_ULP_CLASS_HID_50ac0] = 1328,
+ [BNXT_ULP_CLASS_HID_493aa] = 1329,
+ [BNXT_ULP_CLASS_HID_48208] = 1330,
+ [BNXT_ULP_CLASS_HID_582c8] = 1331,
+ [BNXT_ULP_CLASS_HID_59288] = 1332,
+ [BNXT_ULP_CLASS_HID_40688] = 1333,
+ [BNXT_ULP_CLASS_HID_41540] = 1334,
+ [BNXT_ULP_CLASS_HID_51508] = 1335,
+ [BNXT_ULP_CLASS_HID_50582] = 1336,
+ [BNXT_ULP_CLASS_HID_48d40] = 1337,
+ [BNXT_ULP_CLASS_HID_49d08] = 1338,
+ [BNXT_ULP_CLASS_HID_59dc0] = 1339,
+ [BNXT_ULP_CLASS_HID_58c4a] = 1340,
+ [BNXT_ULP_CLASS_HID_4104a] = 1341,
+ [BNXT_ULP_CLASS_HID_400a8] = 1342,
+ [BNXT_ULP_CLASS_HID_50f78] = 1343,
+ [BNXT_ULP_CLASS_HID_51f38] = 1344,
+ [BNXT_ULP_CLASS_HID_4980a] = 1345,
+ [BNXT_ULP_CLASS_HID_49768] = 1346,
+ [BNXT_ULP_CLASS_HID_59738] = 1347,
+ [BNXT_ULP_CLASS_HID_587aa] = 1348,
+ [BNXT_ULP_CLASS_HID_40bd8] = 1349,
+ [BNXT_ULP_CLASS_HID_41bc8] = 1350,
+ [BNXT_ULP_CLASS_HID_51b88] = 1351,
+ [BNXT_ULP_CLASS_HID_50ada] = 1352,
+ [BNXT_ULP_CLASS_HID_493c8] = 1353,
+ [BNXT_ULP_CLASS_HID_4820a] = 1354,
+ [BNXT_ULP_CLASS_HID_582da] = 1355,
+ [BNXT_ULP_CLASS_HID_5929a] = 1356,
+ [BNXT_ULP_CLASS_HID_4056a] = 1357,
+ [BNXT_ULP_CLASS_HID_4152a] = 1358,
+ [BNXT_ULP_CLASS_HID_5150a] = 1359,
+ [BNXT_ULP_CLASS_HID_50468] = 1360,
+ [BNXT_ULP_CLASS_HID_48d2a] = 1361,
+ [BNXT_ULP_CLASS_HID_49dea] = 1362,
+ [BNXT_ULP_CLASS_HID_59dca] = 1363,
+ [BNXT_ULP_CLASS_HID_58c28] = 1364,
+ [BNXT_ULP_CLASS_HID_4118a] = 1365,
+ [BNXT_ULP_CLASS_HID_400c8] = 1366,
+ [BNXT_ULP_CLASS_HID_50088] = 1367,
+ [BNXT_ULP_CLASS_HID_51088] = 1368,
+ [BNXT_ULP_CLASS_HID_4984a] = 1369,
+ [BNXT_ULP_CLASS_HID_48888] = 1370,
+ [BNXT_ULP_CLASS_HID_58888] = 1371,
+ [BNXT_ULP_CLASS_HID_587ca] = 1372,
+ [BNXT_ULP_CLASS_HID_10690] = 1373,
+ [BNXT_ULP_CLASS_HID_112b0] = 1374,
+ [BNXT_ULP_CLASS_HID_1428c] = 1375,
+ [BNXT_ULP_CLASS_HID_15eac] = 1376,
+ [BNXT_ULP_CLASS_HID_1249e] = 1377,
+ [BNXT_ULP_CLASS_HID_130be] = 1378,
+ [BNXT_ULP_CLASS_HID_16f7a] = 1379,
+ [BNXT_ULP_CLASS_HID_17c9a] = 1380,
+ [BNXT_ULP_CLASS_HID_1119a] = 1381,
+ [BNXT_ULP_CLASS_HID_10c58] = 1382,
+ [BNXT_ULP_CLASS_HID_15c7e] = 1383,
+ [BNXT_ULP_CLASS_HID_1483c] = 1384,
+ [BNXT_ULP_CLASS_HID_13f88] = 1385,
+ [BNXT_ULP_CLASS_HID_12a4e] = 1386,
+ [BNXT_ULP_CLASS_HID_17a6c] = 1387,
+ [BNXT_ULP_CLASS_HID_1762a] = 1388,
+ [BNXT_ULP_CLASS_HID_11b46] = 1389,
+ [BNXT_ULP_CLASS_HID_11704] = 1390,
+ [BNXT_ULP_CLASS_HID_147c4] = 1391,
+ [BNXT_ULP_CLASS_HID_153e4] = 1392,
+ [BNXT_ULP_CLASS_HID_13934] = 1393,
+ [BNXT_ULP_CLASS_HID_135f6] = 1394,
+ [BNXT_ULP_CLASS_HID_165ce] = 1395,
+ [BNXT_ULP_CLASS_HID_171ee] = 1396,
+ [BNXT_ULP_CLASS_HID_116ee] = 1397,
+ [BNXT_ULP_CLASS_HID_102ac] = 1398,
+ [BNXT_ULP_CLASS_HID_152ce] = 1399,
+ [BNXT_ULP_CLASS_HID_14e8c] = 1400,
+ [BNXT_ULP_CLASS_HID_134dc] = 1401,
+ [BNXT_ULP_CLASS_HID_1209e] = 1402,
+ [BNXT_ULP_CLASS_HID_170bc] = 1403,
+ [BNXT_ULP_CLASS_HID_16b7e] = 1404,
+ [BNXT_ULP_CLASS_HID_119ae] = 1405,
+ [BNXT_ULP_CLASS_HID_1146a] = 1406,
+ [BNXT_ULP_CLASS_HID_14426] = 1407,
+ [BNXT_ULP_CLASS_HID_15046] = 1408,
+ [BNXT_ULP_CLASS_HID_1263a] = 1409,
+ [BNXT_ULP_CLASS_HID_1325a] = 1410,
+ [BNXT_ULP_CLASS_HID_16216] = 1411,
+ [BNXT_ULP_CLASS_HID_17e36] = 1412,
+ [BNXT_ULP_CLASS_HID_1133e] = 1413,
+ [BNXT_ULP_CLASS_HID_10ffa] = 1414,
+ [BNXT_ULP_CLASS_HID_15f1a] = 1415,
+ [BNXT_ULP_CLASS_HID_14bee] = 1416,
+ [BNXT_ULP_CLASS_HID_1312a] = 1417,
+ [BNXT_ULP_CLASS_HID_12dea] = 1418,
+ [BNXT_ULP_CLASS_HID_17d1e] = 1419,
+ [BNXT_ULP_CLASS_HID_169de] = 1420,
+ [BNXT_ULP_CLASS_HID_11ee6] = 1421,
+ [BNXT_ULP_CLASS_HID_10abe] = 1422,
+ [BNXT_ULP_CLASS_HID_15ade] = 1423,
+ [BNXT_ULP_CLASS_HID_1569e] = 1424,
+ [BNXT_ULP_CLASS_HID_13cee] = 1425,
+ [BNXT_ULP_CLASS_HID_128ae] = 1426,
+ [BNXT_ULP_CLASS_HID_1676e] = 1427,
+ [BNXT_ULP_CLASS_HID_1748e] = 1428,
+ [BNXT_ULP_CLASS_HID_1098e] = 1429,
+ [BNXT_ULP_CLASS_HID_1044e] = 1430,
+ [BNXT_ULP_CLASS_HID_1546e] = 1431,
+ [BNXT_ULP_CLASS_HID_1402e] = 1432,
+ [BNXT_ULP_CLASS_HID_1367e] = 1433,
+ [BNXT_ULP_CLASS_HID_1223e] = 1434,
+ [BNXT_ULP_CLASS_HID_1725e] = 1435,
+ [BNXT_ULP_CLASS_HID_16e1e] = 1436,
+ [BNXT_ULP_CLASS_HID_1172f] = 1437,
+ [BNXT_ULP_CLASS_HID_103ed] = 1438,
+ [BNXT_ULP_CLASS_HID_1530b] = 1439,
+ [BNXT_ULP_CLASS_HID_14fc9] = 1440,
+ [BNXT_ULP_CLASS_HID_1351d] = 1441,
+ [BNXT_ULP_CLASS_HID_121db] = 1442,
+ [BNXT_ULP_CLASS_HID_171f9] = 1443,
+ [BNXT_ULP_CLASS_HID_16db7] = 1444,
+ [BNXT_ULP_CLASS_HID_102bf] = 1445,
+ [BNXT_ULP_CLASS_HID_11edf] = 1446,
+ [BNXT_ULP_CLASS_HID_14e9b] = 1447,
+ [BNXT_ULP_CLASS_HID_15abb] = 1448,
+ [BNXT_ULP_CLASS_HID_120ad] = 1449,
+ [BNXT_ULP_CLASS_HID_13ccd] = 1450,
+ [BNXT_ULP_CLASS_HID_16c89] = 1451,
+ [BNXT_ULP_CLASS_HID_1675f] = 1452,
+ [BNXT_ULP_CLASS_HID_10c67] = 1453,
+ [BNXT_ULP_CLASS_HID_11987] = 1454,
+ [BNXT_ULP_CLASS_HID_1485f] = 1455,
+ [BNXT_ULP_CLASS_HID_1441d] = 1456,
+ [BNXT_ULP_CLASS_HID_12a55] = 1457,
+ [BNXT_ULP_CLASS_HID_1262f] = 1458,
+ [BNXT_ULP_CLASS_HID_1764d] = 1459,
+ [BNXT_ULP_CLASS_HID_1620f] = 1460,
+ [BNXT_ULP_CLASS_HID_1070f] = 1461,
+ [BNXT_ULP_CLASS_HID_1132f] = 1462,
+ [BNXT_ULP_CLASS_HID_143ef] = 1463,
+ [BNXT_ULP_CLASS_HID_15f0f] = 1464,
+ [BNXT_ULP_CLASS_HID_125fd] = 1465,
+ [BNXT_ULP_CLASS_HID_1311d] = 1466,
+ [BNXT_ULP_CLASS_HID_161dd] = 1467,
+ [BNXT_ULP_CLASS_HID_17dfd] = 1468,
+ [BNXT_ULP_CLASS_HID_10acb] = 1469,
+ [BNXT_ULP_CLASS_HID_10687] = 1470,
+ [BNXT_ULP_CLASS_HID_156a7] = 1471,
+ [BNXT_ULP_CLASS_HID_14163] = 1472,
+ [BNXT_ULP_CLASS_HID_128b7] = 1473,
+ [BNXT_ULP_CLASS_HID_12377] = 1474,
+ [BNXT_ULP_CLASS_HID_17493] = 1475,
+ [BNXT_ULP_CLASS_HID_16f53] = 1476,
+ [BNXT_ULP_CLASS_HID_1045b] = 1477,
+ [BNXT_ULP_CLASS_HID_1107b] = 1478,
+ [BNXT_ULP_CLASS_HID_1404f] = 1479,
+ [BNXT_ULP_CLASS_HID_15c6f] = 1480,
+ [BNXT_ULP_CLASS_HID_1225f] = 1481,
+ [BNXT_ULP_CLASS_HID_13e7f] = 1482,
+ [BNXT_ULP_CLASS_HID_16e3b] = 1483,
+ [BNXT_ULP_CLASS_HID_17a5b] = 1484,
+ [BNXT_ULP_CLASS_HID_10f1f] = 1485,
+ [BNXT_ULP_CLASS_HID_11b3f] = 1486,
+ [BNXT_ULP_CLASS_HID_14bff] = 1487,
+ [BNXT_ULP_CLASS_HID_147b7] = 1488,
+ [BNXT_ULP_CLASS_HID_12d0f] = 1489,
+ [BNXT_ULP_CLASS_HID_1392f] = 1490,
+ [BNXT_ULP_CLASS_HID_169e7] = 1491,
+ [BNXT_ULP_CLASS_HID_165a7] = 1492,
+ [BNXT_ULP_CLASS_HID_11a0f] = 1493,
+ [BNXT_ULP_CLASS_HID_116cf] = 1494,
+ [BNXT_ULP_CLASS_HID_1468f] = 1495,
+ [BNXT_ULP_CLASS_HID_152af] = 1496,
+ [BNXT_ULP_CLASS_HID_138ff] = 1497,
+ [BNXT_ULP_CLASS_HID_134bf] = 1498,
+ [BNXT_ULP_CLASS_HID_1648f] = 1499,
+ [BNXT_ULP_CLASS_HID_170af] = 1500,
+ [BNXT_ULP_CLASS_HID_40c38] = 1501,
+ [BNXT_ULP_CLASS_HID_41c04] = 1502,
+ [BNXT_ULP_CLASS_HID_51c48] = 1503,
+ [BNXT_ULP_CLASS_HID_50332] = 1504,
+ [BNXT_ULP_CLASS_HID_48400] = 1505,
+ [BNXT_ULP_CLASS_HID_48bea] = 1506,
+ [BNXT_ULP_CLASS_HID_58b3e] = 1507,
+ [BNXT_ULP_CLASS_HID_59b7a] = 1508,
+ [BNXT_ULP_CLASS_HID_417dc] = 1509,
+ [BNXT_ULP_CLASS_HID_40746] = 1510,
+ [BNXT_ULP_CLASS_HID_5068a] = 1511,
+ [BNXT_ULP_CLASS_HID_516d6] = 1512,
+ [BNXT_ULP_CLASS_HID_48f42] = 1513,
+ [BNXT_ULP_CLASS_HID_49e8e] = 1514,
+ [BNXT_ULP_CLASS_HID_59ed2] = 1515,
+ [BNXT_ULP_CLASS_HID_58d9c] = 1516,
+ [BNXT_ULP_CLASS_HID_41a4a] = 1517,
+ [BNXT_ULP_CLASS_HID_40924] = 1518,
+ [BNXT_ULP_CLASS_HID_50968] = 1519,
+ [BNXT_ULP_CLASS_HID_51944] = 1520,
+ [BNXT_ULP_CLASS_HID_49182] = 1521,
+ [BNXT_ULP_CLASS_HID_4816c] = 1522,
+ [BNXT_ULP_CLASS_HID_58140] = 1523,
+ [BNXT_ULP_CLASS_HID_5908c] = 1524,
+ [BNXT_ULP_CLASS_HID_40c8c] = 1525,
+ [BNXT_ULP_CLASS_HID_41cc8] = 1526,
+ [BNXT_ULP_CLASS_HID_51c0c] = 1527,
+ [BNXT_ULP_CLASS_HID_50386] = 1528,
+ [BNXT_ULP_CLASS_HID_484c4] = 1529,
+ [BNXT_ULP_CLASS_HID_48b8e] = 1530,
+ [BNXT_ULP_CLASS_HID_58b82] = 1531,
+ [BNXT_ULP_CLASS_HID_59bce] = 1532,
+ [BNXT_ULP_CLASS_HID_10a54] = 1533,
+ [BNXT_ULP_CLASS_HID_11e74] = 1534,
+ [BNXT_ULP_CLASS_HID_14e48] = 1535,
+ [BNXT_ULP_CLASS_HID_15268] = 1536,
+ [BNXT_ULP_CLASS_HID_1285a] = 1537,
+ [BNXT_ULP_CLASS_HID_13c7a] = 1538,
+ [BNXT_ULP_CLASS_HID_163be] = 1539,
+ [BNXT_ULP_CLASS_HID_1705e] = 1540,
+ [BNXT_ULP_CLASS_HID_11d5e] = 1541,
+ [BNXT_ULP_CLASS_HID_1009c] = 1542,
+ [BNXT_ULP_CLASS_HID_150ba] = 1543,
+ [BNXT_ULP_CLASS_HID_144f8] = 1544,
+ [BNXT_ULP_CLASS_HID_1334c] = 1545,
+ [BNXT_ULP_CLASS_HID_1268a] = 1546,
+ [BNXT_ULP_CLASS_HID_176a8] = 1547,
+ [BNXT_ULP_CLASS_HID_17aee] = 1548,
+ [BNXT_ULP_CLASS_HID_11782] = 1549,
+ [BNXT_ULP_CLASS_HID_11bc0] = 1550,
+ [BNXT_ULP_CLASS_HID_14b00] = 1551,
+ [BNXT_ULP_CLASS_HID_15f20] = 1552,
+ [BNXT_ULP_CLASS_HID_135f0] = 1553,
+ [BNXT_ULP_CLASS_HID_13932] = 1554,
+ [BNXT_ULP_CLASS_HID_1690a] = 1555,
+ [BNXT_ULP_CLASS_HID_17d2a] = 1556,
+ [BNXT_ULP_CLASS_HID_11a2a] = 1557,
+ [BNXT_ULP_CLASS_HID_10e68] = 1558,
+ [BNXT_ULP_CLASS_HID_15e0a] = 1559,
+ [BNXT_ULP_CLASS_HID_14248] = 1560,
+ [BNXT_ULP_CLASS_HID_13818] = 1561,
+ [BNXT_ULP_CLASS_HID_12c5a] = 1562,
+ [BNXT_ULP_CLASS_HID_17c78] = 1563,
+ [BNXT_ULP_CLASS_HID_167ba] = 1564,
+ [BNXT_ULP_CLASS_HID_1f91] = 1565,
+ [BNXT_ULP_CLASS_HID_0763] = 1566,
+ [BNXT_ULP_CLASS_HID_0f7b] = 1567,
+ [BNXT_ULP_CLASS_HID_16af] = 1568,
+ [BNXT_ULP_CLASS_HID_1daf] = 1569,
+ [BNXT_ULP_CLASS_HID_0539] = 1570,
+ [BNXT_ULP_CLASS_HID_01ed] = 1571,
+ [BNXT_ULP_CLASS_HID_097f] = 1572,
+ [BNXT_ULP_CLASS_HID_81ab8] = 1573,
+ [BNXT_ULP_CLASS_HID_8020e] = 1574,
+ [BNXT_ULP_CLASS_HID_815d8] = 1575,
+ [BNXT_ULP_CLASS_HID_81cae] = 1576,
+ [BNXT_ULP_CLASS_HID_810a8] = 1577,
+ [BNXT_ULP_CLASS_HID_8183e] = 1578,
+ [BNXT_ULP_CLASS_HID_8036a] = 1579,
+ [BNXT_ULP_CLASS_HID_80af8] = 1580,
+ [BNXT_ULP_CLASS_HID_206fe] = 1581,
+ [BNXT_ULP_CLASS_HID_20e4c] = 1582,
+ [BNXT_ULP_CLASS_HID_2111e] = 1583,
+ [BNXT_ULP_CLASS_HID_218ec] = 1584,
+ [BNXT_ULP_CLASS_HID_60472] = 1585,
+ [BNXT_ULP_CLASS_HID_603c0] = 1586,
+ [BNXT_ULP_CLASS_HID_61692] = 1587,
+ [BNXT_ULP_CLASS_HID_61e60] = 1588,
+ [BNXT_ULP_CLASS_HID_1f81] = 1589,
+ [BNXT_ULP_CLASS_HID_0773] = 1590,
+ [BNXT_ULP_CLASS_HID_0f6b] = 1591,
+ [BNXT_ULP_CLASS_HID_16bf] = 1592,
+ [BNXT_ULP_CLASS_HID_03cf] = 1593,
+ [BNXT_ULP_CLASS_HID_0ab1] = 1594,
+ [BNXT_ULP_CLASS_HID_130b] = 1595,
+ [BNXT_ULP_CLASS_HID_1afd] = 1596,
+ [BNXT_ULP_CLASS_HID_1591] = 1597,
+ [BNXT_ULP_CLASS_HID_1d03] = 1598,
+ [BNXT_ULP_CLASS_HID_057b] = 1599,
+ [BNXT_ULP_CLASS_HID_0ced] = 1600,
+ [BNXT_ULP_CLASS_HID_19df] = 1601,
+ [BNXT_ULP_CLASS_HID_0141] = 1602,
+ [BNXT_ULP_CLASS_HID_08b9] = 1603,
+ [BNXT_ULP_CLASS_HID_108d] = 1604,
+ [BNXT_ULP_CLASS_HID_1dbf] = 1605,
+ [BNXT_ULP_CLASS_HID_0529] = 1606,
+ [BNXT_ULP_CLASS_HID_01fd] = 1607,
+ [BNXT_ULP_CLASS_HID_096f] = 1608,
+ [BNXT_ULP_CLASS_HID_810b7] = 1609,
+ [BNXT_ULP_CLASS_HID_81821] = 1610,
+ [BNXT_ULP_CLASS_HID_804f5] = 1611,
+ [BNXT_ULP_CLASS_HID_80c67] = 1612,
+ [BNXT_ULP_CLASS_HID_41333] = 1613,
+ [BNXT_ULP_CLASS_HID_41aad] = 1614,
+ [BNXT_ULP_CLASS_HID_40771] = 1615,
+ [BNXT_ULP_CLASS_HID_40ee3] = 1616,
+ [BNXT_ULP_CLASS_HID_c16cb] = 1617,
+ [BNXT_ULP_CLASS_HID_c1da5] = 1618,
+ [BNXT_ULP_CLASS_HID_c1a09] = 1619,
+ [BNXT_ULP_CLASS_HID_c01fb] = 1620,
+ [BNXT_ULP_CLASS_HID_1ff1] = 1621,
+ [BNXT_ULP_CLASS_HID_0703] = 1622,
+ [BNXT_ULP_CLASS_HID_0f1b] = 1623,
+ [BNXT_ULP_CLASS_HID_16cf] = 1624,
+ [BNXT_ULP_CLASS_HID_03bf] = 1625,
+ [BNXT_ULP_CLASS_HID_0ac1] = 1626,
+ [BNXT_ULP_CLASS_HID_137b] = 1627,
+ [BNXT_ULP_CLASS_HID_1a8d] = 1628,
+ [BNXT_ULP_CLASS_HID_15e1] = 1629,
+ [BNXT_ULP_CLASS_HID_1d73] = 1630,
+ [BNXT_ULP_CLASS_HID_050b] = 1631,
+ [BNXT_ULP_CLASS_HID_0c9d] = 1632,
+ [BNXT_ULP_CLASS_HID_19af] = 1633,
+ [BNXT_ULP_CLASS_HID_0131] = 1634,
+ [BNXT_ULP_CLASS_HID_08c9] = 1635,
+ [BNXT_ULP_CLASS_HID_10fd] = 1636,
+ [BNXT_ULP_CLASS_HID_1dcf] = 1637,
+ [BNXT_ULP_CLASS_HID_0559] = 1638,
+ [BNXT_ULP_CLASS_HID_018d] = 1639,
+ [BNXT_ULP_CLASS_HID_091f] = 1640,
+ [BNXT_ULP_CLASS_HID_810c7] = 1641,
+ [BNXT_ULP_CLASS_HID_81851] = 1642,
+ [BNXT_ULP_CLASS_HID_80485] = 1643,
+ [BNXT_ULP_CLASS_HID_80c17] = 1644,
+ [BNXT_ULP_CLASS_HID_41343] = 1645,
+ [BNXT_ULP_CLASS_HID_41add] = 1646,
+ [BNXT_ULP_CLASS_HID_40701] = 1647,
+ [BNXT_ULP_CLASS_HID_40e93] = 1648,
+ [BNXT_ULP_CLASS_HID_c16bb] = 1649,
+ [BNXT_ULP_CLASS_HID_c1dd5] = 1650,
+ [BNXT_ULP_CLASS_HID_c1a79] = 1651,
+ [BNXT_ULP_CLASS_HID_c018b] = 1652,
+ [BNXT_ULP_CLASS_HID_81aa8] = 1653,
+ [BNXT_ULP_CLASS_HID_8021e] = 1654,
+ [BNXT_ULP_CLASS_HID_815c8] = 1655,
+ [BNXT_ULP_CLASS_HID_81cbe] = 1656,
+ [BNXT_ULP_CLASS_HID_810b8] = 1657,
+ [BNXT_ULP_CLASS_HID_8182e] = 1658,
+ [BNXT_ULP_CLASS_HID_8037a] = 1659,
+ [BNXT_ULP_CLASS_HID_80ae8] = 1660,
+ [BNXT_ULP_CLASS_HID_c1834] = 1661,
+ [BNXT_ULP_CLASS_HID_c079a] = 1662,
+ [BNXT_ULP_CLASS_HID_c0af6] = 1663,
+ [BNXT_ULP_CLASS_HID_c123a] = 1664,
+ [BNXT_ULP_CLASS_HID_c16c4] = 1665,
+ [BNXT_ULP_CLASS_HID_c1daa] = 1666,
+ [BNXT_ULP_CLASS_HID_c0086] = 1667,
+ [BNXT_ULP_CLASS_HID_c0874] = 1668,
+ [BNXT_ULP_CLASS_HID_a19ea] = 1669,
+ [BNXT_ULP_CLASS_HID_a0158] = 1670,
+ [BNXT_ULP_CLASS_HID_a0bb4] = 1671,
+ [BNXT_ULP_CLASS_HID_a13f8] = 1672,
+ [BNXT_ULP_CLASS_HID_a17fa] = 1673,
+ [BNXT_ULP_CLASS_HID_a1f68] = 1674,
+ [BNXT_ULP_CLASS_HID_a0244] = 1675,
+ [BNXT_ULP_CLASS_HID_a092a] = 1676,
+ [BNXT_ULP_CLASS_HID_e1f76] = 1677,
+ [BNXT_ULP_CLASS_HID_e06e4] = 1678,
+ [BNXT_ULP_CLASS_HID_e0930] = 1679,
+ [BNXT_ULP_CLASS_HID_e1104] = 1680,
+ [BNXT_ULP_CLASS_HID_e1506] = 1681,
+ [BNXT_ULP_CLASS_HID_e1cf4] = 1682,
+ [BNXT_ULP_CLASS_HID_e07c0] = 1683,
+ [BNXT_ULP_CLASS_HID_e0eb6] = 1684,
+ [BNXT_ULP_CLASS_HID_206ee] = 1685,
+ [BNXT_ULP_CLASS_HID_20e5c] = 1686,
+ [BNXT_ULP_CLASS_HID_2110e] = 1687,
+ [BNXT_ULP_CLASS_HID_218fc] = 1688,
+ [BNXT_ULP_CLASS_HID_60462] = 1689,
+ [BNXT_ULP_CLASS_HID_603d0] = 1690,
+ [BNXT_ULP_CLASS_HID_61682] = 1691,
+ [BNXT_ULP_CLASS_HID_61e70] = 1692,
+ [BNXT_ULP_CLASS_HID_3167e] = 1693,
+ [BNXT_ULP_CLASS_HID_31dec] = 1694,
+ [BNXT_ULP_CLASS_HID_30030] = 1695,
+ [BNXT_ULP_CLASS_HID_30fae] = 1696,
+ [BNXT_ULP_CLASS_HID_70b14] = 1697,
+ [BNXT_ULP_CLASS_HID_71360] = 1698,
+ [BNXT_ULP_CLASS_HID_705b4] = 1699,
+ [BNXT_ULP_CLASS_HID_70d22] = 1700,
+ [BNXT_ULP_CLASS_HID_29e26] = 1701,
+ [BNXT_ULP_CLASS_HID_28594] = 1702,
+ [BNXT_ULP_CLASS_HID_288f8] = 1703,
+ [BNXT_ULP_CLASS_HID_29034] = 1704,
+ [BNXT_ULP_CLASS_HID_693ba] = 1705,
+ [BNXT_ULP_CLASS_HID_69b28] = 1706,
+ [BNXT_ULP_CLASS_HID_68e7c] = 1707,
+ [BNXT_ULP_CLASS_HID_69648] = 1708,
+ [BNXT_ULP_CLASS_HID_38de8] = 1709,
+ [BNXT_ULP_CLASS_HID_39524] = 1710,
+ [BNXT_ULP_CLASS_HID_39808] = 1711,
+ [BNXT_ULP_CLASS_HID_387e6] = 1712,
+ [BNXT_ULP_CLASS_HID_7836c] = 1713,
+ [BNXT_ULP_CLASS_HID_78ada] = 1714,
+ [BNXT_ULP_CLASS_HID_79d8c] = 1715,
+ [BNXT_ULP_CLASS_HID_7857a] = 1716,
+ [BNXT_ULP_CLASS_HID_81ad8] = 1717,
+ [BNXT_ULP_CLASS_HID_8026e] = 1718,
+ [BNXT_ULP_CLASS_HID_815b8] = 1719,
+ [BNXT_ULP_CLASS_HID_81cce] = 1720,
+ [BNXT_ULP_CLASS_HID_810c8] = 1721,
+ [BNXT_ULP_CLASS_HID_8185e] = 1722,
+ [BNXT_ULP_CLASS_HID_8030a] = 1723,
+ [BNXT_ULP_CLASS_HID_80a98] = 1724,
+ [BNXT_ULP_CLASS_HID_c1844] = 1725,
+ [BNXT_ULP_CLASS_HID_c07ea] = 1726,
+ [BNXT_ULP_CLASS_HID_c0a86] = 1727,
+ [BNXT_ULP_CLASS_HID_c124a] = 1728,
+ [BNXT_ULP_CLASS_HID_c16b4] = 1729,
+ [BNXT_ULP_CLASS_HID_c1dda] = 1730,
+ [BNXT_ULP_CLASS_HID_c00f6] = 1731,
+ [BNXT_ULP_CLASS_HID_c0804] = 1732,
+ [BNXT_ULP_CLASS_HID_a199a] = 1733,
+ [BNXT_ULP_CLASS_HID_a0128] = 1734,
+ [BNXT_ULP_CLASS_HID_a0bc4] = 1735,
+ [BNXT_ULP_CLASS_HID_a1388] = 1736,
+ [BNXT_ULP_CLASS_HID_a178a] = 1737,
+ [BNXT_ULP_CLASS_HID_a1f18] = 1738,
+ [BNXT_ULP_CLASS_HID_a0234] = 1739,
+ [BNXT_ULP_CLASS_HID_a095a] = 1740,
+ [BNXT_ULP_CLASS_HID_e1f06] = 1741,
+ [BNXT_ULP_CLASS_HID_e0694] = 1742,
+ [BNXT_ULP_CLASS_HID_e0940] = 1743,
+ [BNXT_ULP_CLASS_HID_e1174] = 1744,
+ [BNXT_ULP_CLASS_HID_e1576] = 1745,
+ [BNXT_ULP_CLASS_HID_e1c84] = 1746,
+ [BNXT_ULP_CLASS_HID_e07b0] = 1747,
+ [BNXT_ULP_CLASS_HID_e0ec6] = 1748,
+ [BNXT_ULP_CLASS_HID_2069e] = 1749,
+ [BNXT_ULP_CLASS_HID_20e2c] = 1750,
+ [BNXT_ULP_CLASS_HID_2117e] = 1751,
+ [BNXT_ULP_CLASS_HID_2188c] = 1752,
+ [BNXT_ULP_CLASS_HID_60412] = 1753,
+ [BNXT_ULP_CLASS_HID_603a0] = 1754,
+ [BNXT_ULP_CLASS_HID_616f2] = 1755,
+ [BNXT_ULP_CLASS_HID_61e00] = 1756,
+ [BNXT_ULP_CLASS_HID_3160e] = 1757,
+ [BNXT_ULP_CLASS_HID_31d9c] = 1758,
+ [BNXT_ULP_CLASS_HID_30040] = 1759,
+ [BNXT_ULP_CLASS_HID_30fde] = 1760,
+ [BNXT_ULP_CLASS_HID_70b64] = 1761,
+ [BNXT_ULP_CLASS_HID_71310] = 1762,
+ [BNXT_ULP_CLASS_HID_705c4] = 1763,
+ [BNXT_ULP_CLASS_HID_70d52] = 1764,
+ [BNXT_ULP_CLASS_HID_29e56] = 1765,
+ [BNXT_ULP_CLASS_HID_285e4] = 1766,
+ [BNXT_ULP_CLASS_HID_28888] = 1767,
+ [BNXT_ULP_CLASS_HID_29044] = 1768,
+ [BNXT_ULP_CLASS_HID_693ca] = 1769,
+ [BNXT_ULP_CLASS_HID_69b58] = 1770,
+ [BNXT_ULP_CLASS_HID_68e0c] = 1771,
+ [BNXT_ULP_CLASS_HID_69638] = 1772,
+ [BNXT_ULP_CLASS_HID_38d98] = 1773,
+ [BNXT_ULP_CLASS_HID_39554] = 1774,
+ [BNXT_ULP_CLASS_HID_39878] = 1775,
+ [BNXT_ULP_CLASS_HID_38796] = 1776,
+ [BNXT_ULP_CLASS_HID_7831c] = 1777,
+ [BNXT_ULP_CLASS_HID_78aaa] = 1778,
+ [BNXT_ULP_CLASS_HID_79dfc] = 1779,
+ [BNXT_ULP_CLASS_HID_7850a] = 1780,
+ [BNXT_ULP_CLASS_HID_03b7] = 1781,
+ [BNXT_ULP_CLASS_HID_13f3] = 1782,
+ [BNXT_ULP_CLASS_HID_0255] = 1783,
+ [BNXT_ULP_CLASS_HID_1675] = 1784,
+ [BNXT_ULP_CLASS_HID_80f52] = 1785,
+ [BNXT_ULP_CLASS_HID_819f2] = 1786,
+ [BNXT_ULP_CLASS_HID_80542] = 1787,
+ [BNXT_ULP_CLASS_HID_817e2] = 1788,
+ [BNXT_ULP_CLASS_HID_20a98] = 1789,
+ [BNXT_ULP_CLASS_HID_20538] = 1790,
+ [BNXT_ULP_CLASS_HID_6081c] = 1791,
+ [BNXT_ULP_CLASS_HID_61abc] = 1792,
+ [BNXT_ULP_CLASS_HID_03a7] = 1793,
+ [BNXT_ULP_CLASS_HID_13e3] = 1794,
+ [BNXT_ULP_CLASS_HID_1047] = 1795,
+ [BNXT_ULP_CLASS_HID_0721] = 1796,
+ [BNXT_ULP_CLASS_HID_19b7] = 1797,
+ [BNXT_ULP_CLASS_HID_0911] = 1798,
+ [BNXT_ULP_CLASS_HID_0df5] = 1799,
+ [BNXT_ULP_CLASS_HID_1d31] = 1800,
+ [BNXT_ULP_CLASS_HID_0245] = 1801,
+ [BNXT_ULP_CLASS_HID_1665] = 1802,
+ [BNXT_ULP_CLASS_HID_8055d] = 1803,
+ [BNXT_ULP_CLASS_HID_80893] = 1804,
+ [BNXT_ULP_CLASS_HID_407d9] = 1805,
+ [BNXT_ULP_CLASS_HID_40b1f] = 1806,
+ [BNXT_ULP_CLASS_HID_c1ad1] = 1807,
+ [BNXT_ULP_CLASS_HID_c0e17] = 1808,
+ [BNXT_ULP_CLASS_HID_03d7] = 1809,
+ [BNXT_ULP_CLASS_HID_1393] = 1810,
+ [BNXT_ULP_CLASS_HID_1037] = 1811,
+ [BNXT_ULP_CLASS_HID_0751] = 1812,
+ [BNXT_ULP_CLASS_HID_19c7] = 1813,
+ [BNXT_ULP_CLASS_HID_0961] = 1814,
+ [BNXT_ULP_CLASS_HID_0d85] = 1815,
+ [BNXT_ULP_CLASS_HID_1d41] = 1816,
+ [BNXT_ULP_CLASS_HID_0235] = 1817,
+ [BNXT_ULP_CLASS_HID_1615] = 1818,
+ [BNXT_ULP_CLASS_HID_8052d] = 1819,
+ [BNXT_ULP_CLASS_HID_808e3] = 1820,
+ [BNXT_ULP_CLASS_HID_407a9] = 1821,
+ [BNXT_ULP_CLASS_HID_40b6f] = 1822,
+ [BNXT_ULP_CLASS_HID_c1aa1] = 1823,
+ [BNXT_ULP_CLASS_HID_c0e67] = 1824,
+ [BNXT_ULP_CLASS_HID_80f42] = 1825,
+ [BNXT_ULP_CLASS_HID_819e2] = 1826,
+ [BNXT_ULP_CLASS_HID_80552] = 1827,
+ [BNXT_ULP_CLASS_HID_817f2] = 1828,
+ [BNXT_ULP_CLASS_HID_c0cce] = 1829,
+ [BNXT_ULP_CLASS_HID_c1f6e] = 1830,
+ [BNXT_ULP_CLASS_HID_c1ade] = 1831,
+ [BNXT_ULP_CLASS_HID_c157e] = 1832,
+ [BNXT_ULP_CLASS_HID_a0d8c] = 1833,
+ [BNXT_ULP_CLASS_HID_a182c] = 1834,
+ [BNXT_ULP_CLASS_HID_a1b9c] = 1835,
+ [BNXT_ULP_CLASS_HID_a163c] = 1836,
+ [BNXT_ULP_CLASS_HID_e0308] = 1837,
+ [BNXT_ULP_CLASS_HID_e1da8] = 1838,
+ [BNXT_ULP_CLASS_HID_e1918] = 1839,
+ [BNXT_ULP_CLASS_HID_e0bda] = 1840,
+ [BNXT_ULP_CLASS_HID_20a88] = 1841,
+ [BNXT_ULP_CLASS_HID_20528] = 1842,
+ [BNXT_ULP_CLASS_HID_6080c] = 1843,
+ [BNXT_ULP_CLASS_HID_61aac] = 1844,
+ [BNXT_ULP_CLASS_HID_31a18] = 1845,
+ [BNXT_ULP_CLASS_HID_314b8] = 1846,
+ [BNXT_ULP_CLASS_HID_71f9c] = 1847,
+ [BNXT_ULP_CLASS_HID_70a5e] = 1848,
+ [BNXT_ULP_CLASS_HID_282c0] = 1849,
+ [BNXT_ULP_CLASS_HID_29d60] = 1850,
+ [BNXT_ULP_CLASS_HID_68044] = 1851,
+ [BNXT_ULP_CLASS_HID_692e4] = 1852,
+ [BNXT_ULP_CLASS_HID_39250] = 1853,
+ [BNXT_ULP_CLASS_HID_38c12] = 1854,
+ [BNXT_ULP_CLASS_HID_797d4] = 1855,
+ [BNXT_ULP_CLASS_HID_78196] = 1856,
+ [BNXT_ULP_CLASS_HID_80f32] = 1857,
+ [BNXT_ULP_CLASS_HID_81992] = 1858,
+ [BNXT_ULP_CLASS_HID_80522] = 1859,
+ [BNXT_ULP_CLASS_HID_81782] = 1860,
+ [BNXT_ULP_CLASS_HID_c0cbe] = 1861,
+ [BNXT_ULP_CLASS_HID_c1f1e] = 1862,
+ [BNXT_ULP_CLASS_HID_c1aae] = 1863,
+ [BNXT_ULP_CLASS_HID_c150e] = 1864,
+ [BNXT_ULP_CLASS_HID_a0dfc] = 1865,
+ [BNXT_ULP_CLASS_HID_a185c] = 1866,
+ [BNXT_ULP_CLASS_HID_a1bec] = 1867,
+ [BNXT_ULP_CLASS_HID_a164c] = 1868,
+ [BNXT_ULP_CLASS_HID_e0378] = 1869,
+ [BNXT_ULP_CLASS_HID_e1dd8] = 1870,
+ [BNXT_ULP_CLASS_HID_e1968] = 1871,
+ [BNXT_ULP_CLASS_HID_e0baa] = 1872,
+ [BNXT_ULP_CLASS_HID_20af8] = 1873,
+ [BNXT_ULP_CLASS_HID_20558] = 1874,
+ [BNXT_ULP_CLASS_HID_6087c] = 1875,
+ [BNXT_ULP_CLASS_HID_61adc] = 1876,
+ [BNXT_ULP_CLASS_HID_31a68] = 1877,
+ [BNXT_ULP_CLASS_HID_314c8] = 1878,
+ [BNXT_ULP_CLASS_HID_71fec] = 1879,
+ [BNXT_ULP_CLASS_HID_70a2e] = 1880,
+ [BNXT_ULP_CLASS_HID_282b0] = 1881,
+ [BNXT_ULP_CLASS_HID_29d10] = 1882,
+ [BNXT_ULP_CLASS_HID_68034] = 1883,
+ [BNXT_ULP_CLASS_HID_69294] = 1884,
+ [BNXT_ULP_CLASS_HID_39220] = 1885,
+ [BNXT_ULP_CLASS_HID_38c62] = 1886,
+ [BNXT_ULP_CLASS_HID_797a4] = 1887,
+ [BNXT_ULP_CLASS_HID_781e6] = 1888,
+ [BNXT_ULP_CLASS_HID_0f05] = 1889,
+ [BNXT_ULP_CLASS_HID_0f09] = 1890,
+ [BNXT_ULP_CLASS_HID_0f06] = 1891,
+ [BNXT_ULP_CLASS_HID_19a6] = 1892,
+ [BNXT_ULP_CLASS_HID_0f0a] = 1893,
+ [BNXT_ULP_CLASS_HID_19aa] = 1894,
+ [BNXT_ULP_CLASS_HID_0f15] = 1895,
+ [BNXT_ULP_CLASS_HID_0f19] = 1896,
+ [BNXT_ULP_CLASS_HID_0f65] = 1897,
+ [BNXT_ULP_CLASS_HID_0f69] = 1898,
+ [BNXT_ULP_CLASS_HID_0f16] = 1899,
+ [BNXT_ULP_CLASS_HID_19b6] = 1900,
+ [BNXT_ULP_CLASS_HID_0f1a] = 1901,
+ [BNXT_ULP_CLASS_HID_19ba] = 1902,
+ [BNXT_ULP_CLASS_HID_0f66] = 1903,
+ [BNXT_ULP_CLASS_HID_19c6] = 1904,
+ [BNXT_ULP_CLASS_HID_0f6a] = 1905,
+ [BNXT_ULP_CLASS_HID_19ca] = 1906
};
/* Array for the proto matcher list */
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
[1] = {
- .class_hid = BNXT_ULP_CLASS_HID_55dd,
+ .class_hid = BNXT_ULP_CLASS_HID_00b8,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -1332,7 +1940,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[2] = {
- .class_hid = BNXT_ULP_CLASS_HID_1df1,
+ .class_hid = BNXT_ULP_CLASS_HID_0cc2,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4104UL,
@@ -1348,7 +1956,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[3] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e55,
+ .class_hid = BNXT_ULP_CLASS_HID_10e4,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -1364,7 +1972,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[4] = {
- .class_hid = BNXT_ULP_CLASS_HID_0649,
+ .class_hid = BNXT_ULP_CLASS_HID_1d0e,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6152UL,
@@ -1381,7 +1989,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[5] = {
- .class_hid = BNXT_ULP_CLASS_HID_1011,
+ .class_hid = BNXT_ULP_CLASS_HID_0286,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -1396,7 +2004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[6] = {
- .class_hid = BNXT_ULP_CLASS_HID_40e9,
+ .class_hid = BNXT_ULP_CLASS_HID_0e98,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16392UL,
@@ -1412,7 +2020,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[7] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e99,
+ .class_hid = BNXT_ULP_CLASS_HID_1666,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -1428,7 +2036,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[8] = {
- .class_hid = BNXT_ULP_CLASS_HID_06ad,
+ .class_hid = BNXT_ULP_CLASS_HID_02de,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24584UL,
@@ -1445,7 +2053,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[9] = {
- .class_hid = BNXT_ULP_CLASS_HID_38c7,
+ .class_hid = BNXT_ULP_CLASS_HID_81d25,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -1461,7 +2069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[10] = {
- .class_hid = BNXT_ULP_CLASS_HID_00fb,
+ .class_hid = BNXT_ULP_CLASS_HID_809ad,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32776UL,
@@ -1478,7 +2086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[11] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d3,
+ .class_hid = BNXT_ULP_CLASS_HID_80ae3,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -1495,7 +2103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[12] = {
- .class_hid = BNXT_ULP_CLASS_HID_559b,
+ .class_hid = BNXT_ULP_CLASS_HID_8170d,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32840UL,
@@ -1513,7 +2121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[13] = {
- .class_hid = BNXT_ULP_CLASS_HID_5003,
+ .class_hid = BNXT_ULP_CLASS_HID_80773,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -1530,7 +2138,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[14] = {
- .class_hid = BNXT_ULP_CLASS_HID_1837,
+ .class_hid = BNXT_ULP_CLASS_HID_8139d,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49160UL,
@@ -1548,7 +2156,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[15] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bef,
+ .class_hid = BNXT_ULP_CLASS_HID_814d3,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -1566,7 +2174,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[16] = {
- .class_hid = BNXT_ULP_CLASS_HID_0403,
+ .class_hid = BNXT_ULP_CLASS_HID_8015b,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49224UL,
@@ -1585,7 +2193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[17] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d3f,
+ .class_hid = BNXT_ULP_CLASS_HID_21977,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -1601,7 +2209,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[18] = {
- .class_hid = BNXT_ULP_CLASS_HID_0543,
+ .class_hid = BNXT_ULP_CLASS_HID_205ef,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131080UL,
@@ -1618,7 +2226,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[19] = {
- .class_hid = BNXT_ULP_CLASS_HID_292b,
+ .class_hid = BNXT_ULP_CLASS_HID_20735,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -1635,7 +2243,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[20] = {
- .class_hid = BNXT_ULP_CLASS_HID_59e3,
+ .class_hid = BNXT_ULP_CLASS_HID_2134f,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131144UL,
@@ -1653,7 +2261,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[21] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d3b,
+ .class_hid = BNXT_ULP_CLASS_HID_61beb,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -1670,7 +2278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[22] = {
- .class_hid = BNXT_ULP_CLASS_HID_254f,
+ .class_hid = BNXT_ULP_CLASS_HID_60863,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196616UL,
@@ -1688,7 +2296,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[23] = {
- .class_hid = BNXT_ULP_CLASS_HID_4917,
+ .class_hid = BNXT_ULP_CLASS_HID_609a9,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -1706,7 +2314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[24] = {
- .class_hid = BNXT_ULP_CLASS_HID_113b,
+ .class_hid = BNXT_ULP_CLASS_HID_615c3,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196680UL,
@@ -1725,7 +2333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[25] = {
- .class_hid = BNXT_ULP_CLASS_HID_55fd,
+ .class_hid = BNXT_ULP_CLASS_HID_00a8,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -1741,7 +2349,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[26] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dd1,
+ .class_hid = BNXT_ULP_CLASS_HID_0cd2,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4104UL,
@@ -1758,7 +2366,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[27] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e75,
+ .class_hid = BNXT_ULP_CLASS_HID_10f4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -1775,7 +2383,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[28] = {
- .class_hid = BNXT_ULP_CLASS_HID_0669,
+ .class_hid = BNXT_ULP_CLASS_HID_1d1e,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6152UL,
@@ -1793,7 +2401,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[29] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ba1,
+ .class_hid = BNXT_ULP_CLASS_HID_1488,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -1810,7 +2418,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[30] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c69,
+ .class_hid = BNXT_ULP_CLASS_HID_0110,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12296UL,
@@ -1828,7 +2436,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[31] = {
- .class_hid = BNXT_ULP_CLASS_HID_0439,
+ .class_hid = BNXT_ULP_CLASS_HID_0532,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -1846,7 +2454,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[32] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e1,
+ .class_hid = BNXT_ULP_CLASS_HID_115c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14344UL,
@@ -1865,7 +2473,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[33] = {
- .class_hid = BNXT_ULP_CLASS_HID_0465,
+ .class_hid = BNXT_ULP_CLASS_HID_0ab8,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -1882,7 +2490,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[34] = {
- .class_hid = BNXT_ULP_CLASS_HID_352d,
+ .class_hid = BNXT_ULP_CLASS_HID_16a2,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20488UL,
@@ -1900,7 +2508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[35] = {
- .class_hid = BNXT_ULP_CLASS_HID_55b1,
+ .class_hid = BNXT_ULP_CLASS_HID_1ac4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -1918,7 +2526,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[36] = {
- .class_hid = BNXT_ULP_CLASS_HID_1da5,
+ .class_hid = BNXT_ULP_CLASS_HID_074c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22536UL,
@@ -1937,7 +2545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[37] = {
- .class_hid = BNXT_ULP_CLASS_HID_32fd,
+ .class_hid = BNXT_ULP_CLASS_HID_1e98,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -1955,7 +2563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[38] = {
- .class_hid = BNXT_ULP_CLASS_HID_63a5,
+ .class_hid = BNXT_ULP_CLASS_HID_0ae0,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28680UL,
@@ -1974,7 +2582,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[39] = {
- .class_hid = BNXT_ULP_CLASS_HID_1b75,
+ .class_hid = BNXT_ULP_CLASS_HID_0f02,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -1993,7 +2601,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[40] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c3d,
+ .class_hid = BNXT_ULP_CLASS_HID_1b2c,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30728UL,
@@ -2013,7 +2621,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[41] = {
- .class_hid = BNXT_ULP_CLASS_HID_1031,
+ .class_hid = BNXT_ULP_CLASS_HID_0296,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -2029,7 +2637,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[42] = {
- .class_hid = BNXT_ULP_CLASS_HID_40c9,
+ .class_hid = BNXT_ULP_CLASS_HID_0e88,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16392UL,
@@ -2046,7 +2654,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[43] = {
- .class_hid = BNXT_ULP_CLASS_HID_3eb9,
+ .class_hid = BNXT_ULP_CLASS_HID_1676,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -2063,7 +2671,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[44] = {
- .class_hid = BNXT_ULP_CLASS_HID_068d,
+ .class_hid = BNXT_ULP_CLASS_HID_02ce,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24584UL,
@@ -2081,7 +2689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[45] = {
- .class_hid = BNXT_ULP_CLASS_HID_5039,
+ .class_hid = BNXT_ULP_CLASS_HID_8076e,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -2098,7 +2706,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[46] = {
- .class_hid = BNXT_ULP_CLASS_HID_180d,
+ .class_hid = BNXT_ULP_CLASS_HID_81380,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49160UL,
@@ -2116,7 +2724,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[47] = {
- .class_hid = BNXT_ULP_CLASS_HID_15fd,
+ .class_hid = BNXT_ULP_CLASS_HID_81b4e,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -2134,7 +2742,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[48] = {
- .class_hid = BNXT_ULP_CLASS_HID_46b5,
+ .class_hid = BNXT_ULP_CLASS_HID_807c6,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57352UL,
@@ -2153,7 +2761,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[49] = {
- .class_hid = BNXT_ULP_CLASS_HID_303d,
+ .class_hid = BNXT_ULP_CLASS_HID_404ea,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -2170,7 +2778,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[50] = {
- .class_hid = BNXT_ULP_CLASS_HID_60f5,
+ .class_hid = BNXT_ULP_CLASS_HID_4110c,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81928UL,
@@ -2188,7 +2796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[51] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ea5,
+ .class_hid = BNXT_ULP_CLASS_HID_418ca,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -2206,7 +2814,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[52] = {
- .class_hid = BNXT_ULP_CLASS_HID_2689,
+ .class_hid = BNXT_ULP_CLASS_HID_40542,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90120UL,
@@ -2225,7 +2833,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[53] = {
- .class_hid = BNXT_ULP_CLASS_HID_0771,
+ .class_hid = BNXT_ULP_CLASS_HID_c09e2,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -2243,7 +2851,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[54] = {
- .class_hid = BNXT_ULP_CLASS_HID_3809,
+ .class_hid = BNXT_ULP_CLASS_HID_c1604,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114696UL,
@@ -2262,7 +2870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[55] = {
- .class_hid = BNXT_ULP_CLASS_HID_35f9,
+ .class_hid = BNXT_ULP_CLASS_HID_c1dc2,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -2281,7 +2889,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[56] = {
- .class_hid = BNXT_ULP_CLASS_HID_66b1,
+ .class_hid = BNXT_ULP_CLASS_HID_c0a5a,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122888UL,
@@ -2301,7 +2909,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[57] = {
- .class_hid = BNXT_ULP_CLASS_HID_559d,
+ .class_hid = BNXT_ULP_CLASS_HID_0098,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -2317,7 +2925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[58] = {
- .class_hid = BNXT_ULP_CLASS_HID_1db1,
+ .class_hid = BNXT_ULP_CLASS_HID_0ce2,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4104UL,
@@ -2334,7 +2942,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[59] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e15,
+ .class_hid = BNXT_ULP_CLASS_HID_10c4,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -2351,7 +2959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[60] = {
- .class_hid = BNXT_ULP_CLASS_HID_0609,
+ .class_hid = BNXT_ULP_CLASS_HID_1d2e,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6152UL,
@@ -2369,7 +2977,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[61] = {
- .class_hid = BNXT_ULP_CLASS_HID_1bc1,
+ .class_hid = BNXT_ULP_CLASS_HID_14b8,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -2386,7 +2994,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[62] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c09,
+ .class_hid = BNXT_ULP_CLASS_HID_0120,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12296UL,
@@ -2404,7 +3012,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[63] = {
- .class_hid = BNXT_ULP_CLASS_HID_0459,
+ .class_hid = BNXT_ULP_CLASS_HID_0502,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -2422,7 +3030,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[64] = {
- .class_hid = BNXT_ULP_CLASS_HID_3481,
+ .class_hid = BNXT_ULP_CLASS_HID_116c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14344UL,
@@ -2441,7 +3049,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[65] = {
- .class_hid = BNXT_ULP_CLASS_HID_0405,
+ .class_hid = BNXT_ULP_CLASS_HID_0a88,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -2458,7 +3066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[66] = {
- .class_hid = BNXT_ULP_CLASS_HID_354d,
+ .class_hid = BNXT_ULP_CLASS_HID_1692,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20488UL,
@@ -2476,7 +3084,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[67] = {
- .class_hid = BNXT_ULP_CLASS_HID_55d1,
+ .class_hid = BNXT_ULP_CLASS_HID_1af4,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -2494,7 +3102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[68] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dc5,
+ .class_hid = BNXT_ULP_CLASS_HID_077c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22536UL,
@@ -2513,7 +3121,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[69] = {
- .class_hid = BNXT_ULP_CLASS_HID_329d,
+ .class_hid = BNXT_ULP_CLASS_HID_1ea8,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -2531,7 +3139,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[70] = {
- .class_hid = BNXT_ULP_CLASS_HID_63c5,
+ .class_hid = BNXT_ULP_CLASS_HID_0ad0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28680UL,
@@ -2550,7 +3158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[71] = {
- .class_hid = BNXT_ULP_CLASS_HID_1b15,
+ .class_hid = BNXT_ULP_CLASS_HID_0f32,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -2569,7 +3177,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[72] = {
- .class_hid = BNXT_ULP_CLASS_HID_4c5d,
+ .class_hid = BNXT_ULP_CLASS_HID_1b1c,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30728UL,
@@ -2589,7 +3197,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[73] = {
- .class_hid = BNXT_ULP_CLASS_HID_1051,
+ .class_hid = BNXT_ULP_CLASS_HID_02a6,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -2605,7 +3213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[74] = {
- .class_hid = BNXT_ULP_CLASS_HID_40a9,
+ .class_hid = BNXT_ULP_CLASS_HID_0eb8,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16392UL,
@@ -2622,7 +3230,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[75] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ed9,
+ .class_hid = BNXT_ULP_CLASS_HID_1646,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -2639,7 +3247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[76] = {
- .class_hid = BNXT_ULP_CLASS_HID_06ed,
+ .class_hid = BNXT_ULP_CLASS_HID_02fe,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24584UL,
@@ -2657,7 +3265,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[77] = {
- .class_hid = BNXT_ULP_CLASS_HID_5059,
+ .class_hid = BNXT_ULP_CLASS_HID_8075e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -2674,7 +3282,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[78] = {
- .class_hid = BNXT_ULP_CLASS_HID_186d,
+ .class_hid = BNXT_ULP_CLASS_HID_813b0,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49160UL,
@@ -2692,7 +3300,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[79] = {
- .class_hid = BNXT_ULP_CLASS_HID_159d,
+ .class_hid = BNXT_ULP_CLASS_HID_81b7e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -2710,7 +3318,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[80] = {
- .class_hid = BNXT_ULP_CLASS_HID_46d5,
+ .class_hid = BNXT_ULP_CLASS_HID_807f6,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57352UL,
@@ -2729,7 +3337,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[81] = {
- .class_hid = BNXT_ULP_CLASS_HID_305d,
+ .class_hid = BNXT_ULP_CLASS_HID_404da,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -2746,7 +3354,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[82] = {
- .class_hid = BNXT_ULP_CLASS_HID_6095,
+ .class_hid = BNXT_ULP_CLASS_HID_4113c,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81928UL,
@@ -2764,7 +3372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[83] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ec5,
+ .class_hid = BNXT_ULP_CLASS_HID_418fa,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -2782,7 +3390,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[84] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e9,
+ .class_hid = BNXT_ULP_CLASS_HID_40572,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90120UL,
@@ -2801,7 +3409,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[85] = {
- .class_hid = BNXT_ULP_CLASS_HID_0711,
+ .class_hid = BNXT_ULP_CLASS_HID_c09d2,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -2819,7 +3427,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[86] = {
- .class_hid = BNXT_ULP_CLASS_HID_3869,
+ .class_hid = BNXT_ULP_CLASS_HID_c1634,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114696UL,
@@ -2838,7 +3446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[87] = {
- .class_hid = BNXT_ULP_CLASS_HID_3599,
+ .class_hid = BNXT_ULP_CLASS_HID_c1df2,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -2857,7 +3465,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[88] = {
- .class_hid = BNXT_ULP_CLASS_HID_66d1,
+ .class_hid = BNXT_ULP_CLASS_HID_c0a6a,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122888UL,
@@ -2877,7 +3485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[89] = {
- .class_hid = BNXT_ULP_CLASS_HID_38e7,
+ .class_hid = BNXT_ULP_CLASS_HID_81d35,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -2894,7 +3502,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[90] = {
- .class_hid = BNXT_ULP_CLASS_HID_00db,
+ .class_hid = BNXT_ULP_CLASS_HID_809bd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32776UL,
@@ -2912,7 +3520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[91] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f3,
+ .class_hid = BNXT_ULP_CLASS_HID_80af3,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -2930,7 +3538,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[92] = {
- .class_hid = BNXT_ULP_CLASS_HID_55bb,
+ .class_hid = BNXT_ULP_CLASS_HID_8171d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32840UL,
@@ -2949,7 +3557,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[93] = {
- .class_hid = BNXT_ULP_CLASS_HID_5023,
+ .class_hid = BNXT_ULP_CLASS_HID_80763,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -2967,7 +3575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[94] = {
- .class_hid = BNXT_ULP_CLASS_HID_1817,
+ .class_hid = BNXT_ULP_CLASS_HID_8138d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49160UL,
@@ -2986,7 +3594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[95] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bcf,
+ .class_hid = BNXT_ULP_CLASS_HID_814c3,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -3005,7 +3613,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[96] = {
- .class_hid = BNXT_ULP_CLASS_HID_0423,
+ .class_hid = BNXT_ULP_CLASS_HID_8014b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49224UL,
@@ -3025,7 +3633,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[97] = {
- .class_hid = BNXT_ULP_CLASS_HID_58e3,
+ .class_hid = BNXT_ULP_CLASS_HID_c001f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -3043,7 +3651,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[98] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d7,
+ .class_hid = BNXT_ULP_CLASS_HID_c0c39,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98312UL,
@@ -3062,7 +3670,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[99] = {
- .class_hid = BNXT_ULP_CLASS_HID_448f,
+ .class_hid = BNXT_ULP_CLASS_HID_c0d7f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -3081,7 +3689,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[100] = {
- .class_hid = BNXT_ULP_CLASS_HID_0ce3,
+ .class_hid = BNXT_ULP_CLASS_HID_c1999,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98376UL,
@@ -3101,7 +3709,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[101] = {
- .class_hid = BNXT_ULP_CLASS_HID_076b,
+ .class_hid = BNXT_ULP_CLASS_HID_c09ef,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -3120,7 +3728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[102] = {
- .class_hid = BNXT_ULP_CLASS_HID_3813,
+ .class_hid = BNXT_ULP_CLASS_HID_c1609,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114696UL,
@@ -3140,7 +3748,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[103] = {
- .class_hid = BNXT_ULP_CLASS_HID_5bcb,
+ .class_hid = BNXT_ULP_CLASS_HID_c174f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -3160,7 +3768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[104] = {
- .class_hid = BNXT_ULP_CLASS_HID_243f,
+ .class_hid = BNXT_ULP_CLASS_HID_c03d7,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114760UL,
@@ -3181,7 +3789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[105] = {
- .class_hid = BNXT_ULP_CLASS_HID_144b,
+ .class_hid = BNXT_ULP_CLASS_HID_a1e73,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -3199,7 +3807,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[106] = {
- .class_hid = BNXT_ULP_CLASS_HID_4573,
+ .class_hid = BNXT_ULP_CLASS_HID_a0afb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163848UL,
@@ -3218,7 +3826,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[107] = {
- .class_hid = BNXT_ULP_CLASS_HID_0057,
+ .class_hid = BNXT_ULP_CLASS_HID_a0c31,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -3237,7 +3845,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[108] = {
- .class_hid = BNXT_ULP_CLASS_HID_311f,
+ .class_hid = BNXT_ULP_CLASS_HID_a185b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163912UL,
@@ -3257,7 +3865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[109] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b87,
+ .class_hid = BNXT_ULP_CLASS_HID_a08a1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -3276,7 +3884,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[110] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c4f,
+ .class_hid = BNXT_ULP_CLASS_HID_a14cb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180232UL,
@@ -3296,7 +3904,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[111] = {
- .class_hid = BNXT_ULP_CLASS_HID_1793,
+ .class_hid = BNXT_ULP_CLASS_HID_a1601,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -3316,7 +3924,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[112] = {
- .class_hid = BNXT_ULP_CLASS_HID_485b,
+ .class_hid = BNXT_ULP_CLASS_HID_a0289,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180296UL,
@@ -3337,7 +3945,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[113] = {
- .class_hid = BNXT_ULP_CLASS_HID_3447,
+ .class_hid = BNXT_ULP_CLASS_HID_e015d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -3356,7 +3964,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[114] = {
- .class_hid = BNXT_ULP_CLASS_HID_650f,
+ .class_hid = BNXT_ULP_CLASS_HID_e0d47,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229384UL,
@@ -3376,7 +3984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[115] = {
- .class_hid = BNXT_ULP_CLASS_HID_2053,
+ .class_hid = BNXT_ULP_CLASS_HID_e0ebd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -3396,7 +4004,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[116] = {
- .class_hid = BNXT_ULP_CLASS_HID_511b,
+ .class_hid = BNXT_ULP_CLASS_HID_e1aa7,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229448UL,
@@ -3417,7 +4025,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[117] = {
- .class_hid = BNXT_ULP_CLASS_HID_4b83,
+ .class_hid = BNXT_ULP_CLASS_HID_e0b2d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -3437,7 +4045,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[118] = {
- .class_hid = BNXT_ULP_CLASS_HID_13f7,
+ .class_hid = BNXT_ULP_CLASS_HID_e1757,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245768UL,
@@ -3458,7 +4066,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[119] = {
- .class_hid = BNXT_ULP_CLASS_HID_37af,
+ .class_hid = BNXT_ULP_CLASS_HID_e188d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -3479,7 +4087,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[120] = {
- .class_hid = BNXT_ULP_CLASS_HID_6857,
+ .class_hid = BNXT_ULP_CLASS_HID_e0515,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245832UL,
@@ -3501,7 +4109,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[121] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d1f,
+ .class_hid = BNXT_ULP_CLASS_HID_21967,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -3518,7 +4126,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[122] = {
- .class_hid = BNXT_ULP_CLASS_HID_0563,
+ .class_hid = BNXT_ULP_CLASS_HID_205ff,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131080UL,
@@ -3536,7 +4144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[123] = {
- .class_hid = BNXT_ULP_CLASS_HID_290b,
+ .class_hid = BNXT_ULP_CLASS_HID_20725,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -3554,7 +4162,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[124] = {
- .class_hid = BNXT_ULP_CLASS_HID_59c3,
+ .class_hid = BNXT_ULP_CLASS_HID_2135f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131144UL,
@@ -3573,7 +4181,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[125] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d1b,
+ .class_hid = BNXT_ULP_CLASS_HID_61bfb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -3591,7 +4199,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[126] = {
- .class_hid = BNXT_ULP_CLASS_HID_256f,
+ .class_hid = BNXT_ULP_CLASS_HID_60873,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196616UL,
@@ -3610,7 +4218,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[127] = {
- .class_hid = BNXT_ULP_CLASS_HID_4937,
+ .class_hid = BNXT_ULP_CLASS_HID_609b9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -3629,7 +4237,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[128] = {
- .class_hid = BNXT_ULP_CLASS_HID_111b,
+ .class_hid = BNXT_ULP_CLASS_HID_615d3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196680UL,
@@ -3649,7 +4257,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[129] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f4b,
+ .class_hid = BNXT_ULP_CLASS_HID_30a55,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -3667,7 +4275,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[130] = {
- .class_hid = BNXT_ULP_CLASS_HID_2275f,
+ .class_hid = BNXT_ULP_CLASS_HID_3164f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393224UL,
@@ -3686,7 +4294,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[131] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b67,
+ .class_hid = BNXT_ULP_CLASS_HID_317b5,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -3705,7 +4313,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[132] = {
- .class_hid = BNXT_ULP_CLASS_HID_2134b,
+ .class_hid = BNXT_ULP_CLASS_HID_3040d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393288UL,
@@ -3725,7 +4333,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[133] = {
- .class_hid = BNXT_ULP_CLASS_HID_21683,
+ .class_hid = BNXT_ULP_CLASS_HID_70ca9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -3744,7 +4352,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[134] = {
- .class_hid = BNXT_ULP_CLASS_HID_2475b,
+ .class_hid = BNXT_ULP_CLASS_HID_718c3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458760UL,
@@ -3764,7 +4372,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[135] = {
- .class_hid = BNXT_ULP_CLASS_HID_202bf,
+ .class_hid = BNXT_ULP_CLASS_HID_71a09,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -3784,7 +4392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[136] = {
- .class_hid = BNXT_ULP_CLASS_HID_23377,
+ .class_hid = BNXT_ULP_CLASS_HID_70681,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458824UL,
@@ -3805,7 +4413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[137] = {
- .class_hid = BNXT_ULP_CLASS_HID_119db,
+ .class_hid = BNXT_ULP_CLASS_HID_2821d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -3823,7 +4431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[138] = {
- .class_hid = BNXT_ULP_CLASS_HID_14a93,
+ .class_hid = BNXT_ULP_CLASS_HID_28e37,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655368UL,
@@ -3842,7 +4450,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[139] = {
- .class_hid = BNXT_ULP_CLASS_HID_105f7,
+ .class_hid = BNXT_ULP_CLASS_HID_28f7d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -3861,7 +4469,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[140] = {
- .class_hid = BNXT_ULP_CLASS_HID_1368f,
+ .class_hid = BNXT_ULP_CLASS_HID_29b97,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655432UL,
@@ -3881,7 +4489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[141] = {
- .class_hid = BNXT_ULP_CLASS_HID_139c7,
+ .class_hid = BNXT_ULP_CLASS_HID_68491,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -3900,7 +4508,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[142] = {
- .class_hid = BNXT_ULP_CLASS_HID_1022b,
+ .class_hid = BNXT_ULP_CLASS_HID_6908b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720904UL,
@@ -3920,7 +4528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[143] = {
- .class_hid = BNXT_ULP_CLASS_HID_125f3,
+ .class_hid = BNXT_ULP_CLASS_HID_691f1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -3940,7 +4548,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[144] = {
- .class_hid = BNXT_ULP_CLASS_HID_1568b,
+ .class_hid = BNXT_ULP_CLASS_HID_69deb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720968UL,
@@ -3961,7 +4569,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[145] = {
- .class_hid = BNXT_ULP_CLASS_HID_33c37,
+ .class_hid = BNXT_ULP_CLASS_HID_3926d,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -3980,7 +4588,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[146] = {
- .class_hid = BNXT_ULP_CLASS_HID_3041b,
+ .class_hid = BNXT_ULP_CLASS_HID_39e87,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917512UL,
@@ -4000,7 +4608,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[147] = {
- .class_hid = BNXT_ULP_CLASS_HID_32823,
+ .class_hid = BNXT_ULP_CLASS_HID_38023,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -4020,7 +4628,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[148] = {
- .class_hid = BNXT_ULP_CLASS_HID_358fb,
+ .class_hid = BNXT_ULP_CLASS_HID_38c45,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917576UL,
@@ -4041,7 +4649,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[149] = {
- .class_hid = BNXT_ULP_CLASS_HID_35c33,
+ .class_hid = BNXT_ULP_CLASS_HID_794e1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -4061,7 +4669,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[150] = {
- .class_hid = BNXT_ULP_CLASS_HID_32407,
+ .class_hid = BNXT_ULP_CLASS_HID_78179,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983048UL,
@@ -4082,7 +4690,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[151] = {
- .class_hid = BNXT_ULP_CLASS_HID_3482f,
+ .class_hid = BNXT_ULP_CLASS_HID_782a7,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -4103,7 +4711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[152] = {
- .class_hid = BNXT_ULP_CLASS_HID_31033,
+ .class_hid = BNXT_ULP_CLASS_HID_78ed9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983112UL,
@@ -4125,7 +4733,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[153] = {
- .class_hid = BNXT_ULP_CLASS_HID_3887,
+ .class_hid = BNXT_ULP_CLASS_HID_81d05,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -4142,7 +4750,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[154] = {
- .class_hid = BNXT_ULP_CLASS_HID_00bb,
+ .class_hid = BNXT_ULP_CLASS_HID_8098d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32776UL,
@@ -4160,7 +4768,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[155] = {
- .class_hid = BNXT_ULP_CLASS_HID_2493,
+ .class_hid = BNXT_ULP_CLASS_HID_80ac3,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -4178,7 +4786,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[156] = {
- .class_hid = BNXT_ULP_CLASS_HID_55db,
+ .class_hid = BNXT_ULP_CLASS_HID_8172d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32840UL,
@@ -4197,7 +4805,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[157] = {
- .class_hid = BNXT_ULP_CLASS_HID_5043,
+ .class_hid = BNXT_ULP_CLASS_HID_80753,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -4215,7 +4823,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[158] = {
- .class_hid = BNXT_ULP_CLASS_HID_1877,
+ .class_hid = BNXT_ULP_CLASS_HID_813bd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49160UL,
@@ -4234,7 +4842,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[159] = {
- .class_hid = BNXT_ULP_CLASS_HID_3baf,
+ .class_hid = BNXT_ULP_CLASS_HID_814f3,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -4253,7 +4861,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[160] = {
- .class_hid = BNXT_ULP_CLASS_HID_0443,
+ .class_hid = BNXT_ULP_CLASS_HID_8017b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49224UL,
@@ -4273,7 +4881,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[161] = {
- .class_hid = BNXT_ULP_CLASS_HID_5883,
+ .class_hid = BNXT_ULP_CLASS_HID_c002f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -4291,7 +4899,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[162] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b7,
+ .class_hid = BNXT_ULP_CLASS_HID_c0c09,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98312UL,
@@ -4310,7 +4918,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[163] = {
- .class_hid = BNXT_ULP_CLASS_HID_44ef,
+ .class_hid = BNXT_ULP_CLASS_HID_c0d4f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -4329,7 +4937,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[164] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c83,
+ .class_hid = BNXT_ULP_CLASS_HID_c19a9,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98376UL,
@@ -4349,7 +4957,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[165] = {
- .class_hid = BNXT_ULP_CLASS_HID_070b,
+ .class_hid = BNXT_ULP_CLASS_HID_c09df,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -4368,7 +4976,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[166] = {
- .class_hid = BNXT_ULP_CLASS_HID_3873,
+ .class_hid = BNXT_ULP_CLASS_HID_c1639,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114696UL,
@@ -4388,7 +4996,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[167] = {
- .class_hid = BNXT_ULP_CLASS_HID_5bab,
+ .class_hid = BNXT_ULP_CLASS_HID_c177f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -4408,7 +5016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[168] = {
- .class_hid = BNXT_ULP_CLASS_HID_245f,
+ .class_hid = BNXT_ULP_CLASS_HID_c03e7,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114760UL,
@@ -4429,7 +5037,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[169] = {
- .class_hid = BNXT_ULP_CLASS_HID_142b,
+ .class_hid = BNXT_ULP_CLASS_HID_a1e43,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -4447,7 +5055,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[170] = {
- .class_hid = BNXT_ULP_CLASS_HID_4513,
+ .class_hid = BNXT_ULP_CLASS_HID_a0acb,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163848UL,
@@ -4466,7 +5074,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[171] = {
- .class_hid = BNXT_ULP_CLASS_HID_0037,
+ .class_hid = BNXT_ULP_CLASS_HID_a0c01,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -4485,7 +5093,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[172] = {
- .class_hid = BNXT_ULP_CLASS_HID_317f,
+ .class_hid = BNXT_ULP_CLASS_HID_a186b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163912UL,
@@ -4505,7 +5113,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[173] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be7,
+ .class_hid = BNXT_ULP_CLASS_HID_a0891,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -4524,7 +5132,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[174] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c2f,
+ .class_hid = BNXT_ULP_CLASS_HID_a14fb,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180232UL,
@@ -4544,7 +5152,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[175] = {
- .class_hid = BNXT_ULP_CLASS_HID_17f3,
+ .class_hid = BNXT_ULP_CLASS_HID_a1631,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -4564,7 +5172,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[176] = {
- .class_hid = BNXT_ULP_CLASS_HID_483b,
+ .class_hid = BNXT_ULP_CLASS_HID_a02b9,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180296UL,
@@ -4585,7 +5193,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[177] = {
- .class_hid = BNXT_ULP_CLASS_HID_3427,
+ .class_hid = BNXT_ULP_CLASS_HID_e016d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -4604,7 +5212,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[178] = {
- .class_hid = BNXT_ULP_CLASS_HID_656f,
+ .class_hid = BNXT_ULP_CLASS_HID_e0d77,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229384UL,
@@ -4624,7 +5232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[179] = {
- .class_hid = BNXT_ULP_CLASS_HID_2033,
+ .class_hid = BNXT_ULP_CLASS_HID_e0e8d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -4644,7 +5252,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[180] = {
- .class_hid = BNXT_ULP_CLASS_HID_517b,
+ .class_hid = BNXT_ULP_CLASS_HID_e1a97,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229448UL,
@@ -4665,7 +5273,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[181] = {
- .class_hid = BNXT_ULP_CLASS_HID_4be3,
+ .class_hid = BNXT_ULP_CLASS_HID_e0b1d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -4685,7 +5293,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[182] = {
- .class_hid = BNXT_ULP_CLASS_HID_1397,
+ .class_hid = BNXT_ULP_CLASS_HID_e1767,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245768UL,
@@ -4706,7 +5314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[183] = {
- .class_hid = BNXT_ULP_CLASS_HID_37cf,
+ .class_hid = BNXT_ULP_CLASS_HID_e18bd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -4727,7 +5335,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[184] = {
- .class_hid = BNXT_ULP_CLASS_HID_6837,
+ .class_hid = BNXT_ULP_CLASS_HID_e0525,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245832UL,
@@ -4749,7 +5357,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[185] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d7f,
+ .class_hid = BNXT_ULP_CLASS_HID_21957,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -4766,7 +5374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[186] = {
- .class_hid = BNXT_ULP_CLASS_HID_0503,
+ .class_hid = BNXT_ULP_CLASS_HID_205cf,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131080UL,
@@ -4784,7 +5392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[187] = {
- .class_hid = BNXT_ULP_CLASS_HID_296b,
+ .class_hid = BNXT_ULP_CLASS_HID_20715,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -4802,7 +5410,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[188] = {
- .class_hid = BNXT_ULP_CLASS_HID_59a3,
+ .class_hid = BNXT_ULP_CLASS_HID_2136f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131144UL,
@@ -4821,7 +5429,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[189] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d7b,
+ .class_hid = BNXT_ULP_CLASS_HID_61bcb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -4839,7 +5447,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[190] = {
- .class_hid = BNXT_ULP_CLASS_HID_250f,
+ .class_hid = BNXT_ULP_CLASS_HID_60843,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196616UL,
@@ -4858,7 +5466,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[191] = {
- .class_hid = BNXT_ULP_CLASS_HID_4957,
+ .class_hid = BNXT_ULP_CLASS_HID_60989,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -4877,7 +5485,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[192] = {
- .class_hid = BNXT_ULP_CLASS_HID_117b,
+ .class_hid = BNXT_ULP_CLASS_HID_615e3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196680UL,
@@ -4897,7 +5505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[193] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f2b,
+ .class_hid = BNXT_ULP_CLASS_HID_30a65,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -4915,7 +5523,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[194] = {
- .class_hid = BNXT_ULP_CLASS_HID_2273f,
+ .class_hid = BNXT_ULP_CLASS_HID_3167f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393224UL,
@@ -4934,7 +5542,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[195] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b07,
+ .class_hid = BNXT_ULP_CLASS_HID_31785,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -4953,7 +5561,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[196] = {
- .class_hid = BNXT_ULP_CLASS_HID_2132b,
+ .class_hid = BNXT_ULP_CLASS_HID_3043d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393288UL,
@@ -4973,7 +5581,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[197] = {
- .class_hid = BNXT_ULP_CLASS_HID_216e3,
+ .class_hid = BNXT_ULP_CLASS_HID_70c99,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -4992,7 +5600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[198] = {
- .class_hid = BNXT_ULP_CLASS_HID_2473b,
+ .class_hid = BNXT_ULP_CLASS_HID_718f3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458760UL,
@@ -5012,7 +5620,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[199] = {
- .class_hid = BNXT_ULP_CLASS_HID_202df,
+ .class_hid = BNXT_ULP_CLASS_HID_71a39,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -5032,7 +5640,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[200] = {
- .class_hid = BNXT_ULP_CLASS_HID_23317,
+ .class_hid = BNXT_ULP_CLASS_HID_706b1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458824UL,
@@ -5053,7 +5661,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[201] = {
- .class_hid = BNXT_ULP_CLASS_HID_119bb,
+ .class_hid = BNXT_ULP_CLASS_HID_2822d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -5071,7 +5679,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[202] = {
- .class_hid = BNXT_ULP_CLASS_HID_14af3,
+ .class_hid = BNXT_ULP_CLASS_HID_28e07,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655368UL,
@@ -5090,7 +5698,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[203] = {
- .class_hid = BNXT_ULP_CLASS_HID_10597,
+ .class_hid = BNXT_ULP_CLASS_HID_28f4d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -5109,7 +5717,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[204] = {
- .class_hid = BNXT_ULP_CLASS_HID_136ef,
+ .class_hid = BNXT_ULP_CLASS_HID_29ba7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655432UL,
@@ -5129,7 +5737,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[205] = {
- .class_hid = BNXT_ULP_CLASS_HID_139a7,
+ .class_hid = BNXT_ULP_CLASS_HID_684a1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -5148,7 +5756,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[206] = {
- .class_hid = BNXT_ULP_CLASS_HID_1024b,
+ .class_hid = BNXT_ULP_CLASS_HID_690bb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720904UL,
@@ -5168,7 +5776,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[207] = {
- .class_hid = BNXT_ULP_CLASS_HID_12593,
+ .class_hid = BNXT_ULP_CLASS_HID_691c1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -5188,7 +5796,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[208] = {
- .class_hid = BNXT_ULP_CLASS_HID_156eb,
+ .class_hid = BNXT_ULP_CLASS_HID_69ddb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720968UL,
@@ -5209,7 +5817,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[209] = {
- .class_hid = BNXT_ULP_CLASS_HID_33c57,
+ .class_hid = BNXT_ULP_CLASS_HID_3925d,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -5228,7 +5836,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[210] = {
- .class_hid = BNXT_ULP_CLASS_HID_3047b,
+ .class_hid = BNXT_ULP_CLASS_HID_39eb7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917512UL,
@@ -5248,7 +5856,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[211] = {
- .class_hid = BNXT_ULP_CLASS_HID_32843,
+ .class_hid = BNXT_ULP_CLASS_HID_38013,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -5268,7 +5876,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[212] = {
- .class_hid = BNXT_ULP_CLASS_HID_3589b,
+ .class_hid = BNXT_ULP_CLASS_HID_38c75,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917576UL,
@@ -5289,7 +5897,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[213] = {
- .class_hid = BNXT_ULP_CLASS_HID_35c53,
+ .class_hid = BNXT_ULP_CLASS_HID_794d1,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -5309,7 +5917,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[214] = {
- .class_hid = BNXT_ULP_CLASS_HID_32467,
+ .class_hid = BNXT_ULP_CLASS_HID_78149,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983048UL,
@@ -5330,7 +5938,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[215] = {
- .class_hid = BNXT_ULP_CLASS_HID_3484f,
+ .class_hid = BNXT_ULP_CLASS_HID_78297,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -5351,7 +5959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[216] = {
- .class_hid = BNXT_ULP_CLASS_HID_31053,
+ .class_hid = BNXT_ULP_CLASS_HID_78ee9,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983112UL,
@@ -5373,7 +5981,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[217] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ce1,
+ .class_hid = BNXT_ULP_CLASS_HID_0816,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -5387,7 +5995,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[218] = {
- .class_hid = BNXT_ULP_CLASS_HID_4579,
+ .class_hid = BNXT_ULP_CLASS_HID_1852,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -5402,7 +6010,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_IPV6_DST_ADDR }
},
[219] = {
- .class_hid = BNXT_ULP_CLASS_HID_1735,
+ .class_hid = BNXT_ULP_CLASS_HID_09f4,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -5416,7 +6024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[220] = {
- .class_hid = BNXT_ULP_CLASS_HID_45bd,
+ .class_hid = BNXT_ULP_CLASS_HID_1dd4,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -5431,7 +6039,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_IPV4_DST_ADDR }
},
[221] = {
- .class_hid = BNXT_ULP_CLASS_HID_3feb,
+ .class_hid = BNXT_ULP_CLASS_HID_804f1,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -5446,7 +6054,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[222] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf7,
+ .class_hid = BNXT_ULP_CLASS_HID_81251,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -5462,7 +6070,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[223] = {
- .class_hid = BNXT_ULP_CLASS_HID_5727,
+ .class_hid = BNXT_ULP_CLASS_HID_80ee1,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -5478,7 +6086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[224] = {
- .class_hid = BNXT_ULP_CLASS_HID_4333,
+ .class_hid = BNXT_ULP_CLASS_HID_81c41,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -5495,7 +6103,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_IPV6_DST_ADDR }
},
[225] = {
- .class_hid = BNXT_ULP_CLASS_HID_4453,
+ .class_hid = BNXT_ULP_CLASS_HID_2013b,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -5510,7 +6118,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[226] = {
- .class_hid = BNXT_ULP_CLASS_HID_304f,
+ .class_hid = BNXT_ULP_CLASS_HID_20e9b,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -5526,7 +6134,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[227] = {
- .class_hid = BNXT_ULP_CLASS_HID_645f,
+ .class_hid = BNXT_ULP_CLASS_HID_603bf,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -5542,7 +6150,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[228] = {
- .class_hid = BNXT_ULP_CLASS_HID_504b,
+ .class_hid = BNXT_ULP_CLASS_HID_6111f,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -5559,7 +6167,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_IPV4_DST_ADDR }
},
[229] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cc1,
+ .class_hid = BNXT_ULP_CLASS_HID_0806,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -5574,7 +6182,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[230] = {
- .class_hid = BNXT_ULP_CLASS_HID_4559,
+ .class_hid = BNXT_ULP_CLASS_HID_1842,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -5590,7 +6198,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_IPV6_DST_ADDR }
},
[231] = {
- .class_hid = BNXT_ULP_CLASS_HID_2285,
+ .class_hid = BNXT_ULP_CLASS_HID_1be6,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -5606,7 +6214,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[232] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b1d,
+ .class_hid = BNXT_ULP_CLASS_HID_0c80,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -5623,7 +6231,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_SRC_PORT }
},
[233] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b49,
+ .class_hid = BNXT_ULP_CLASS_HID_1216,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -5639,7 +6247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[234] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c95,
+ .class_hid = BNXT_ULP_CLASS_HID_02b0,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -5656,7 +6264,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[235] = {
- .class_hid = BNXT_ULP_CLASS_HID_39c1,
+ .class_hid = BNXT_ULP_CLASS_HID_0654,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -5673,7 +6281,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[236] = {
- .class_hid = BNXT_ULP_CLASS_HID_2259,
+ .class_hid = BNXT_ULP_CLASS_HID_1690,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -5691,7 +6299,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_TCP_DST_PORT }
},
[237] = {
- .class_hid = BNXT_ULP_CLASS_HID_1715,
+ .class_hid = BNXT_ULP_CLASS_HID_09e4,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -5706,7 +6314,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[238] = {
- .class_hid = BNXT_ULP_CLASS_HID_459d,
+ .class_hid = BNXT_ULP_CLASS_HID_1dc4,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -5722,7 +6330,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_IPV4_DST_ADDR }
},
[239] = {
- .class_hid = BNXT_ULP_CLASS_HID_571d,
+ .class_hid = BNXT_ULP_CLASS_HID_80efc,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -5738,7 +6346,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[240] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cd1,
+ .class_hid = BNXT_ULP_CLASS_HID_80332,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -5755,7 +6363,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_SRC_PORT }
},
[241] = {
- .class_hid = BNXT_ULP_CLASS_HID_3711,
+ .class_hid = BNXT_ULP_CLASS_HID_40c78,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -5771,7 +6379,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[242] = {
- .class_hid = BNXT_ULP_CLASS_HID_6599,
+ .class_hid = BNXT_ULP_CLASS_HID_400be,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -5788,7 +6396,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[243] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e55,
+ .class_hid = BNXT_ULP_CLASS_HID_c1170,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -5805,7 +6413,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[244] = {
- .class_hid = BNXT_ULP_CLASS_HID_3cdd,
+ .class_hid = BNXT_ULP_CLASS_HID_c05b6,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -5823,7 +6431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_TCP_DST_PORT }
},
[245] = {
- .class_hid = BNXT_ULP_CLASS_HID_5ca1,
+ .class_hid = BNXT_ULP_CLASS_HID_0836,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -5838,7 +6446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[246] = {
- .class_hid = BNXT_ULP_CLASS_HID_4539,
+ .class_hid = BNXT_ULP_CLASS_HID_1872,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -5854,7 +6462,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_IPV6_DST_ADDR }
},
[247] = {
- .class_hid = BNXT_ULP_CLASS_HID_22e5,
+ .class_hid = BNXT_ULP_CLASS_HID_1bd6,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -5870,7 +6478,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[248] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b7d,
+ .class_hid = BNXT_ULP_CLASS_HID_0cb0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -5887,7 +6495,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_SRC_PORT }
},
[249] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b29,
+ .class_hid = BNXT_ULP_CLASS_HID_1226,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -5903,7 +6511,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[250] = {
- .class_hid = BNXT_ULP_CLASS_HID_5cf5,
+ .class_hid = BNXT_ULP_CLASS_HID_0280,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -5920,7 +6528,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[251] = {
- .class_hid = BNXT_ULP_CLASS_HID_39a1,
+ .class_hid = BNXT_ULP_CLASS_HID_0664,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -5937,7 +6545,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[252] = {
- .class_hid = BNXT_ULP_CLASS_HID_2239,
+ .class_hid = BNXT_ULP_CLASS_HID_16a0,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -5955,7 +6563,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_UDP_DST_PORT }
},
[253] = {
- .class_hid = BNXT_ULP_CLASS_HID_1775,
+ .class_hid = BNXT_ULP_CLASS_HID_09d4,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -5970,7 +6578,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[254] = {
- .class_hid = BNXT_ULP_CLASS_HID_45fd,
+ .class_hid = BNXT_ULP_CLASS_HID_1df4,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -5986,7 +6594,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_IPV4_DST_ADDR }
},
[255] = {
- .class_hid = BNXT_ULP_CLASS_HID_577d,
+ .class_hid = BNXT_ULP_CLASS_HID_80ecc,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -6002,7 +6610,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[256] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cb1,
+ .class_hid = BNXT_ULP_CLASS_HID_80302,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -6019,7 +6627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_SRC_PORT }
},
[257] = {
- .class_hid = BNXT_ULP_CLASS_HID_3771,
+ .class_hid = BNXT_ULP_CLASS_HID_40c48,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -6035,7 +6643,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[258] = {
- .class_hid = BNXT_ULP_CLASS_HID_65f9,
+ .class_hid = BNXT_ULP_CLASS_HID_4008e,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -6052,7 +6660,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[259] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e35,
+ .class_hid = BNXT_ULP_CLASS_HID_c1140,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -6069,7 +6677,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[260] = {
- .class_hid = BNXT_ULP_CLASS_HID_3cbd,
+ .class_hid = BNXT_ULP_CLASS_HID_c0586,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -6087,7 +6695,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_UDP_DST_PORT }
},
[261] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fcb,
+ .class_hid = BNXT_ULP_CLASS_HID_804e1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -6103,7 +6711,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[262] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bd7,
+ .class_hid = BNXT_ULP_CLASS_HID_81241,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -6120,7 +6728,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[263] = {
- .class_hid = BNXT_ULP_CLASS_HID_5707,
+ .class_hid = BNXT_ULP_CLASS_HID_80ef1,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -6137,7 +6745,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[264] = {
- .class_hid = BNXT_ULP_CLASS_HID_4313,
+ .class_hid = BNXT_ULP_CLASS_HID_81c51,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -6155,7 +6763,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_IPV6_DST_ADDR }
},
[265] = {
- .class_hid = BNXT_ULP_CLASS_HID_5fc7,
+ .class_hid = BNXT_ULP_CLASS_HID_c076d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -6172,7 +6780,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[266] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bd3,
+ .class_hid = BNXT_ULP_CLASS_HID_c14cd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -6190,7 +6798,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[267] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e4f,
+ .class_hid = BNXT_ULP_CLASS_HID_c117d,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -6208,7 +6816,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[268] = {
- .class_hid = BNXT_ULP_CLASS_HID_632f,
+ .class_hid = BNXT_ULP_CLASS_HID_c1edd,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -6227,7 +6835,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_SRC_PORT }
},
[269] = {
- .class_hid = BNXT_ULP_CLASS_HID_1baf,
+ .class_hid = BNXT_ULP_CLASS_HID_a062f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -6244,7 +6852,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[270] = {
- .class_hid = BNXT_ULP_CLASS_HID_07bb,
+ .class_hid = BNXT_ULP_CLASS_HID_a138f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -6262,7 +6870,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[271] = {
- .class_hid = BNXT_ULP_CLASS_HID_32eb,
+ .class_hid = BNXT_ULP_CLASS_HID_a103f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -6280,7 +6888,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[272] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ef7,
+ .class_hid = BNXT_ULP_CLASS_HID_a1d9f,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -6299,7 +6907,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[273] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bab,
+ .class_hid = BNXT_ULP_CLASS_HID_e08ab,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -6317,7 +6925,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[274] = {
- .class_hid = BNXT_ULP_CLASS_HID_27b7,
+ .class_hid = BNXT_ULP_CLASS_HID_e160b,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -6336,7 +6944,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[275] = {
- .class_hid = BNXT_ULP_CLASS_HID_52e7,
+ .class_hid = BNXT_ULP_CLASS_HID_e12bb,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -6355,7 +6963,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[276] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ef3,
+ .class_hid = BNXT_ULP_CLASS_HID_e0079,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -6375,7 +6983,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_TCP_DST_PORT }
},
[277] = {
- .class_hid = BNXT_ULP_CLASS_HID_4473,
+ .class_hid = BNXT_ULP_CLASS_HID_2012b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -6391,7 +6999,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[278] = {
- .class_hid = BNXT_ULP_CLASS_HID_306f,
+ .class_hid = BNXT_ULP_CLASS_HID_20e8b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -6408,7 +7016,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[279] = {
- .class_hid = BNXT_ULP_CLASS_HID_647f,
+ .class_hid = BNXT_ULP_CLASS_HID_603af,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -6425,7 +7033,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[280] = {
- .class_hid = BNXT_ULP_CLASS_HID_506b,
+ .class_hid = BNXT_ULP_CLASS_HID_6110f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -6443,7 +7051,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_IPV4_DST_ADDR }
},
[281] = {
- .class_hid = BNXT_ULP_CLASS_HID_266af,
+ .class_hid = BNXT_ULP_CLASS_HID_311bb,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -6460,7 +7068,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[282] = {
- .class_hid = BNXT_ULP_CLASS_HID_2525b,
+ .class_hid = BNXT_ULP_CLASS_HID_31f1b,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -6478,7 +7086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[283] = {
- .class_hid = BNXT_ULP_CLASS_HID_21de7,
+ .class_hid = BNXT_ULP_CLASS_HID_7143f,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -6496,7 +7104,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[284] = {
- .class_hid = BNXT_ULP_CLASS_HID_20993,
+ .class_hid = BNXT_ULP_CLASS_HID_701fd,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -6515,7 +7123,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_SRC_PORT }
},
[285] = {
- .class_hid = BNXT_ULP_CLASS_HID_1213f,
+ .class_hid = BNXT_ULP_CLASS_HID_28963,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -6532,7 +7140,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[286] = {
- .class_hid = BNXT_ULP_CLASS_HID_10d2b,
+ .class_hid = BNXT_ULP_CLASS_HID_296c3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -6550,7 +7158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[287] = {
- .class_hid = BNXT_ULP_CLASS_HID_1413b,
+ .class_hid = BNXT_ULP_CLASS_HID_68be7,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -6568,7 +7176,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[288] = {
- .class_hid = BNXT_ULP_CLASS_HID_12cd7,
+ .class_hid = BNXT_ULP_CLASS_HID_69947,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -6587,7 +7195,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[289] = {
- .class_hid = BNXT_ULP_CLASS_HID_3436b,
+ .class_hid = BNXT_ULP_CLASS_HID_399f3,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -6605,7 +7213,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[290] = {
- .class_hid = BNXT_ULP_CLASS_HID_32f07,
+ .class_hid = BNXT_ULP_CLASS_HID_387b1,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -6624,7 +7232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[291] = {
- .class_hid = BNXT_ULP_CLASS_HID_36317,
+ .class_hid = BNXT_ULP_CLASS_HID_79c77,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -6643,7 +7251,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[292] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f03,
+ .class_hid = BNXT_ULP_CLASS_HID_78a35,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -6663,7 +7271,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_TCP_DST_PORT }
},
[293] = {
- .class_hid = BNXT_ULP_CLASS_HID_3fab,
+ .class_hid = BNXT_ULP_CLASS_HID_804d1,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -6679,7 +7287,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[294] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bb7,
+ .class_hid = BNXT_ULP_CLASS_HID_81271,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -6696,7 +7304,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[295] = {
- .class_hid = BNXT_ULP_CLASS_HID_5767,
+ .class_hid = BNXT_ULP_CLASS_HID_80ec1,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -6713,7 +7321,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[296] = {
- .class_hid = BNXT_ULP_CLASS_HID_4373,
+ .class_hid = BNXT_ULP_CLASS_HID_81c61,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -6731,7 +7339,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_IPV6_DST_ADDR }
},
[297] = {
- .class_hid = BNXT_ULP_CLASS_HID_5fa7,
+ .class_hid = BNXT_ULP_CLASS_HID_c075d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -6748,7 +7356,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[298] = {
- .class_hid = BNXT_ULP_CLASS_HID_4bb3,
+ .class_hid = BNXT_ULP_CLASS_HID_c14fd,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -6766,7 +7374,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[299] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e2f,
+ .class_hid = BNXT_ULP_CLASS_HID_c114d,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -6784,7 +7392,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[300] = {
- .class_hid = BNXT_ULP_CLASS_HID_634f,
+ .class_hid = BNXT_ULP_CLASS_HID_c1eed,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -6803,7 +7411,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_SRC_PORT }
},
[301] = {
- .class_hid = BNXT_ULP_CLASS_HID_1bcf,
+ .class_hid = BNXT_ULP_CLASS_HID_a061f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -6820,7 +7428,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[302] = {
- .class_hid = BNXT_ULP_CLASS_HID_07db,
+ .class_hid = BNXT_ULP_CLASS_HID_a13bf,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -6838,7 +7446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[303] = {
- .class_hid = BNXT_ULP_CLASS_HID_328b,
+ .class_hid = BNXT_ULP_CLASS_HID_a100f,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -6856,7 +7464,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[304] = {
- .class_hid = BNXT_ULP_CLASS_HID_1e97,
+ .class_hid = BNXT_ULP_CLASS_HID_a1daf,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -6875,7 +7483,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[305] = {
- .class_hid = BNXT_ULP_CLASS_HID_3bcb,
+ .class_hid = BNXT_ULP_CLASS_HID_e089b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -6893,7 +7501,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[306] = {
- .class_hid = BNXT_ULP_CLASS_HID_27d7,
+ .class_hid = BNXT_ULP_CLASS_HID_e163b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -6912,7 +7520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[307] = {
- .class_hid = BNXT_ULP_CLASS_HID_5287,
+ .class_hid = BNXT_ULP_CLASS_HID_e128b,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -6931,7 +7539,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[308] = {
- .class_hid = BNXT_ULP_CLASS_HID_3e93,
+ .class_hid = BNXT_ULP_CLASS_HID_e0049,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -6951,7 +7559,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_UDP_DST_PORT }
},
[309] = {
- .class_hid = BNXT_ULP_CLASS_HID_4413,
+ .class_hid = BNXT_ULP_CLASS_HID_2011b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -6967,7 +7575,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[310] = {
- .class_hid = BNXT_ULP_CLASS_HID_300f,
+ .class_hid = BNXT_ULP_CLASS_HID_20ebb,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -6984,7 +7592,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[311] = {
- .class_hid = BNXT_ULP_CLASS_HID_641f,
+ .class_hid = BNXT_ULP_CLASS_HID_6039f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -7001,7 +7609,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[312] = {
- .class_hid = BNXT_ULP_CLASS_HID_500b,
+ .class_hid = BNXT_ULP_CLASS_HID_6113f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -7019,7 +7627,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_IPV4_DST_ADDR }
},
[313] = {
- .class_hid = BNXT_ULP_CLASS_HID_266cf,
+ .class_hid = BNXT_ULP_CLASS_HID_3118b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -7036,7 +7644,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[314] = {
- .class_hid = BNXT_ULP_CLASS_HID_2523b,
+ .class_hid = BNXT_ULP_CLASS_HID_31f2b,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -7054,7 +7662,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[315] = {
- .class_hid = BNXT_ULP_CLASS_HID_21d87,
+ .class_hid = BNXT_ULP_CLASS_HID_7140f,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -7072,7 +7680,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[316] = {
- .class_hid = BNXT_ULP_CLASS_HID_209f3,
+ .class_hid = BNXT_ULP_CLASS_HID_701cd,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -7091,7 +7699,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_SRC_PORT }
},
[317] = {
- .class_hid = BNXT_ULP_CLASS_HID_1215f,
+ .class_hid = BNXT_ULP_CLASS_HID_28953,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -7108,7 +7716,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[318] = {
- .class_hid = BNXT_ULP_CLASS_HID_10d4b,
+ .class_hid = BNXT_ULP_CLASS_HID_296f3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -7126,7 +7734,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[319] = {
- .class_hid = BNXT_ULP_CLASS_HID_1415b,
+ .class_hid = BNXT_ULP_CLASS_HID_68bd7,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -7144,7 +7752,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[320] = {
- .class_hid = BNXT_ULP_CLASS_HID_12cb7,
+ .class_hid = BNXT_ULP_CLASS_HID_69977,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -7163,7 +7771,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[321] = {
- .class_hid = BNXT_ULP_CLASS_HID_3430b,
+ .class_hid = BNXT_ULP_CLASS_HID_399c3,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -7181,7 +7789,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[322] = {
- .class_hid = BNXT_ULP_CLASS_HID_32f67,
+ .class_hid = BNXT_ULP_CLASS_HID_38781,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -7200,7 +7808,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[323] = {
- .class_hid = BNXT_ULP_CLASS_HID_36377,
+ .class_hid = BNXT_ULP_CLASS_HID_79c47,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -7219,7 +7827,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[324] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f63,
+ .class_hid = BNXT_ULP_CLASS_HID_78a05,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -7239,7 +7847,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_UDP_DST_PORT }
},
[325] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b5,
+ .class_hid = BNXT_ULP_CLASS_HID_04a4,
.class_tid = 1,
.hdr_sig_id = 0,
.flow_sig_id = 8UL,
@@ -7254,7 +7862,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_0_BITMASK_O_ETH_SMAC }
},
[326] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ad,
+ .class_hid = BNXT_ULP_CLASS_HID_04a8,
.class_tid = 1,
.hdr_sig_id = 1,
.flow_sig_id = 8UL,
@@ -7269,7 +7877,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_1_BITMASK_O_ETH_SMAC }
},
[327] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b7,
+ .class_hid = BNXT_ULP_CLASS_HID_04a5,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 8UL,
@@ -7285,7 +7893,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_O_ETH_SMAC }
},
[328] = {
- .class_hid = BNXT_ULP_CLASS_HID_1583,
+ .class_hid = BNXT_ULP_CLASS_HID_1205,
.class_tid = 1,
.hdr_sig_id = 2,
.flow_sig_id = 72UL,
@@ -7302,7 +7910,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_2_BITMASK_OO_VLAN_VID }
},
[329] = {
- .class_hid = BNXT_ULP_CLASS_HID_29af,
+ .class_hid = BNXT_ULP_CLASS_HID_04a9,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 8UL,
@@ -7318,7 +7926,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_O_ETH_SMAC }
},
[330] = {
- .class_hid = BNXT_ULP_CLASS_HID_159b,
+ .class_hid = BNXT_ULP_CLASS_HID_1209,
.class_tid = 1,
.hdr_sig_id = 3,
.flow_sig_id = 72UL,
@@ -7335,7 +7943,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_3_BITMASK_OO_VLAN_VID }
},
[331] = {
- .class_hid = BNXT_ULP_CLASS_HID_2995,
+ .class_hid = BNXT_ULP_CLASS_HID_04b4,
.class_tid = 1,
.hdr_sig_id = 4,
.flow_sig_id = 8UL,
@@ -7351,7 +7959,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_4_BITMASK_O_ETH_SMAC }
},
[332] = {
- .class_hid = BNXT_ULP_CLASS_HID_298d,
+ .class_hid = BNXT_ULP_CLASS_HID_04b8,
.class_tid = 1,
.hdr_sig_id = 5,
.flow_sig_id = 8UL,
@@ -7367,7 +7975,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_5_BITMASK_O_ETH_SMAC }
},
[333] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f5,
+ .class_hid = BNXT_ULP_CLASS_HID_0484,
.class_tid = 1,
.hdr_sig_id = 6,
.flow_sig_id = 8UL,
@@ -7383,7 +7991,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_6_BITMASK_O_ETH_SMAC }
},
[334] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ed,
+ .class_hid = BNXT_ULP_CLASS_HID_0488,
.class_tid = 1,
.hdr_sig_id = 7,
.flow_sig_id = 8UL,
@@ -7399,7 +8007,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_7_BITMASK_O_ETH_SMAC }
},
[335] = {
- .class_hid = BNXT_ULP_CLASS_HID_2997,
+ .class_hid = BNXT_ULP_CLASS_HID_04b5,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 8UL,
@@ -7416,7 +8024,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_O_ETH_SMAC }
},
[336] = {
- .class_hid = BNXT_ULP_CLASS_HID_15a3,
+ .class_hid = BNXT_ULP_CLASS_HID_1215,
.class_tid = 1,
.hdr_sig_id = 8,
.flow_sig_id = 72UL,
@@ -7434,7 +8042,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_8_BITMASK_OO_VLAN_VID }
},
[337] = {
- .class_hid = BNXT_ULP_CLASS_HID_298f,
+ .class_hid = BNXT_ULP_CLASS_HID_04b9,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 8UL,
@@ -7451,7 +8059,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_O_ETH_SMAC }
},
[338] = {
- .class_hid = BNXT_ULP_CLASS_HID_15bb,
+ .class_hid = BNXT_ULP_CLASS_HID_1219,
.class_tid = 1,
.hdr_sig_id = 9,
.flow_sig_id = 72UL,
@@ -7469,7 +8077,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_9_BITMASK_OO_VLAN_VID }
},
[339] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f7,
+ .class_hid = BNXT_ULP_CLASS_HID_0485,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 8UL,
@@ -7486,7 +8094,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_O_ETH_SMAC }
},
[340] = {
- .class_hid = BNXT_ULP_CLASS_HID_15c3,
+ .class_hid = BNXT_ULP_CLASS_HID_1225,
.class_tid = 1,
.hdr_sig_id = 10,
.flow_sig_id = 72UL,
@@ -7504,7 +8112,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_10_BITMASK_OO_VLAN_VID }
},
[341] = {
- .class_hid = BNXT_ULP_CLASS_HID_29ef,
+ .class_hid = BNXT_ULP_CLASS_HID_0489,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 8UL,
@@ -7521,7 +8129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_O_ETH_SMAC }
},
[342] = {
- .class_hid = BNXT_ULP_CLASS_HID_15db,
+ .class_hid = BNXT_ULP_CLASS_HID_1229,
.class_tid = 1,
.hdr_sig_id = 11,
.flow_sig_id = 72UL,
@@ -7539,7 +8147,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_11_BITMASK_OO_VLAN_VID }
},
[343] = {
- .class_hid = BNXT_ULP_CLASS_HID_1151,
+ .class_hid = BNXT_ULP_CLASS_HID_0226,
.class_tid = 1,
.hdr_sig_id = 12,
.flow_sig_id = 16384UL,
@@ -7556,7 +8164,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_IPV4_DST_ADDR }
},
[344] = {
- .class_hid = BNXT_ULP_CLASS_HID_315d,
+ .class_hid = BNXT_ULP_CLASS_HID_4045a,
.class_tid = 1,
.hdr_sig_id = 12,
.flow_sig_id = 81920UL,
@@ -7574,776 +8182,776 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT }
},
[345] = {
- .class_hid = BNXT_ULP_CLASS_HID_3612,
+ .class_hid = BNXT_ULP_CLASS_HID_0daa,
.class_tid = 2,
.hdr_sig_id = 0,
- .flow_sig_id = 81920UL,
+ .flow_sig_id = 20480UL,
.flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_F1 |
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[346] = {
- .class_hid = BNXT_ULP_CLASS_HID_66da,
+ .class_hid = BNXT_ULP_CLASS_HID_11b0,
.class_tid = 2,
.hdr_sig_id = 0,
- .flow_sig_id = 81928UL,
+ .flow_sig_id = 20488UL,
.flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_F1 |
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT }
},
[347] = {
- .class_hid = BNXT_ULP_CLASS_HID_243ca,
+ .class_hid = BNXT_ULP_CLASS_HID_403f8,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 265216UL,
- .flow_pattern_id = 1,
+ .flow_sig_id = 81920UL,
+ .flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
},
[348] = {
- .class_hid = BNXT_ULP_CLASS_HID_20d8e,
+ .class_hid = BNXT_ULP_CLASS_HID_4161e,
.class_tid = 2,
.hdr_sig_id = 1,
- .flow_sig_id = 273408UL,
- .flow_pattern_id = 1,
+ .flow_sig_id = 81928UL,
+ .flow_pattern_id = 0,
.app_sig = 0,
.hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_F1 |
+ BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT }
},
[349] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e082,
+ .class_hid = BNXT_ULP_CLASS_HID_40439,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
},
[350] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ab46,
+ .class_hid = BNXT_ULP_CLASS_HID_41405,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
},
[351] = {
- .class_hid = BNXT_ULP_CLASS_HID_25226,
+ .class_hid = BNXT_ULP_CLASS_HID_51449,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[352] = {
- .class_hid = BNXT_ULP_CLASS_HID_25cea,
+ .class_hid = BNXT_ULP_CLASS_HID_50b33,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 330496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
},
[353] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c82a,
+ .class_hid = BNXT_ULP_CLASS_HID_48c01,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 590592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[354] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f9a2,
+ .class_hid = BNXT_ULP_CLASS_HID_483eb,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 592640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[355] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b56,
+ .class_hid = BNXT_ULP_CLASS_HID_5833f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 852736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[356] = {
- .class_hid = BNXT_ULP_CLASS_HID_205da,
+ .class_hid = BNXT_ULP_CLASS_HID_5937b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 854784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
},
[357] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d8ce,
+ .class_hid = BNXT_ULP_CLASS_HID_41875,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134284032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[358] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a2d2,
+ .class_hid = BNXT_ULP_CLASS_HID_40f5f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134286080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[359] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a72,
+ .class_hid = BNXT_ULP_CLASS_HID_50f23,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134546176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[360] = {
- .class_hid = BNXT_ULP_CLASS_HID_25476,
+ .class_hid = BNXT_ULP_CLASS_HID_51f6f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134548224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[361] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c076,
+ .class_hid = BNXT_ULP_CLASS_HID_4875b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134808320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[362] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f1ee,
+ .class_hid = BNXT_ULP_CLASS_HID_49727,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 134810368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[363] = {
- .class_hid = BNXT_ULP_CLASS_HID_20bb6,
+ .class_hid = BNXT_ULP_CLASS_HID_5976b,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 135070464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[364] = {
- .class_hid = BNXT_ULP_CLASS_HID_23d2e,
+ .class_hid = BNXT_ULP_CLASS_HID_58655,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 135072512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR }
},
[365] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a96e,
+ .class_hid = BNXT_ULP_CLASS_HID_4125f,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268501760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[366] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dae6,
+ .class_hid = BNXT_ULP_CLASS_HID_401f9,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268503808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[367] = {
- .class_hid = BNXT_ULP_CLASS_HID_25af2,
+ .class_hid = BNXT_ULP_CLASS_HID_501cd,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268763904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[368] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c6a,
+ .class_hid = BNXT_ULP_CLASS_HID_51149,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 268765952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[369] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c7aa,
+ .class_hid = BNXT_ULP_CLASS_HID_49a67,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269026048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[370] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c26e,
+ .class_hid = BNXT_ULP_CLASS_HID_489c1,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269028096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[371] = {
- .class_hid = BNXT_ULP_CLASS_HID_203e2,
+ .class_hid = BNXT_ULP_CLASS_HID_58955,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269288192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[372] = {
- .class_hid = BNXT_ULP_CLASS_HID_2357a,
+ .class_hid = BNXT_ULP_CLASS_HID_59951,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 269290240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[373] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a0fa,
+ .class_hid = BNXT_ULP_CLASS_HID_40569,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402719488UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[374] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d272,
+ .class_hid = BNXT_ULP_CLASS_HID_41575,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402721536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[375] = {
- .class_hid = BNXT_ULP_CLASS_HID_2527e,
+ .class_hid = BNXT_ULP_CLASS_HID_51579,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402981632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[376] = {
- .class_hid = BNXT_ULP_CLASS_HID_243f6,
+ .class_hid = BNXT_ULP_CLASS_HID_50463,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 402983680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[377] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fff6,
+ .class_hid = BNXT_ULP_CLASS_HID_48d71,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 403243776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[378] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e16e,
+ .class_hid = BNXT_ULP_CLASS_HID_49d7d,
.class_tid = 2,
- .hdr_sig_id = 1,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 2,
+ .flow_sig_id = 403245824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[379] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422d,
+ .class_hid = BNXT_ULP_CLASS_HID_59d41,
.class_tid = 2,
.hdr_sig_id = 2,
- .flow_sig_id = 265216UL,
+ .flow_sig_id = 403505920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[380] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c69,
+ .class_hid = BNXT_ULP_CLASS_HID_58c6b,
.class_tid = 2,
.hdr_sig_id = 2,
- .flow_sig_id = 273408UL,
+ .flow_sig_id = 403507968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR }
},
[381] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e165,
+ .class_hid = BNXT_ULP_CLASS_HID_10255,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8351,19 +8959,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
},
[382] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aaa1,
+ .class_hid = BNXT_ULP_CLASS_HID_11675,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8371,20 +8978,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
},
[383] = {
- .class_hid = BNXT_ULP_CLASS_HID_253c1,
+ .class_hid = BNXT_ULP_CLASS_HID_14649,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8392,19 +8998,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[384] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d0d,
+ .class_hid = BNXT_ULP_CLASS_HID_15a69,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8412,20 +9018,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
},
[385] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c9cd,
+ .class_hid = BNXT_ULP_CLASS_HID_1205b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8433,20 +9039,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[386] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f845,
+ .class_hid = BNXT_ULP_CLASS_HID_1347b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8454,21 +9059,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[387] = {
- .class_hid = BNXT_ULP_CLASS_HID_25afd,
+ .class_hid = BNXT_ULP_CLASS_HID_16bbf,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8476,19 +9080,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[388] = {
- .class_hid = BNXT_ULP_CLASS_HID_22439,
+ .class_hid = BNXT_ULP_CLASS_HID_1785f,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8496,20 +9101,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
},
[389] = {
- .class_hid = BNXT_ULP_CLASS_HID_290f9,
+ .class_hid = BNXT_ULP_CLASS_HID_11551,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 537136128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8517,20 +9123,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[390] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c371,
+ .class_hid = BNXT_ULP_CLASS_HID_10897,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 537144320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8538,21 +9143,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[391] = {
- .class_hid = BNXT_ULP_CLASS_HID_24355,
+ .class_hid = BNXT_ULP_CLASS_HID_15955,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538184704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8560,20 +9164,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[392] = {
- .class_hid = BNXT_ULP_CLASS_HID_275dd,
+ .class_hid = BNXT_ULP_CLASS_HID_14c8b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 538192896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8581,21 +9185,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[393] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e19d,
+ .class_hid = BNXT_ULP_CLASS_HID_13b47,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 539233280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8603,21 +9207,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[394] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d015,
+ .class_hid = BNXT_ULP_CLASS_HID_12e85,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 539241472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8625,22 +9228,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[395] = {
- .class_hid = BNXT_ULP_CLASS_HID_2560d,
+ .class_hid = BNXT_ULP_CLASS_HID_17f5b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540281856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8648,19 +9250,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[396] = {
- .class_hid = BNXT_ULP_CLASS_HID_21049,
+ .class_hid = BNXT_ULP_CLASS_HID_17299,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 540290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8668,20 +9272,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
},
[397] = {
- .class_hid = BNXT_ULP_CLASS_HID_28c09,
+ .class_hid = BNXT_ULP_CLASS_HID_10fe7,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1074007040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8689,20 +9295,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[398] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be89,
+ .class_hid = BNXT_ULP_CLASS_HID_10325,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1074015232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8710,21 +9315,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[399] = {
- .class_hid = BNXT_ULP_CLASS_HID_267a9,
+ .class_hid = BNXT_ULP_CLASS_HID_153cb,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075055616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8732,20 +9336,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[400] = {
- .class_hid = BNXT_ULP_CLASS_HID_261ed,
+ .class_hid = BNXT_ULP_CLASS_HID_14709,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1075063808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8753,21 +9357,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[401] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ddad,
+ .class_hid = BNXT_ULP_CLASS_HID_12dc5,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1076104192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8775,21 +9379,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[402] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc2d,
+ .class_hid = BNXT_ULP_CLASS_HID_1212b,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1076112384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8797,22 +9400,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[403] = {
- .class_hid = BNXT_ULP_CLASS_HID_26edd,
+ .class_hid = BNXT_ULP_CLASS_HID_171c9,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077152768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8820,20 +9422,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[404] = {
- .class_hid = BNXT_ULP_CLASS_HID_22819,
+ .class_hid = BNXT_ULP_CLASS_HID_1650f,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1077160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8841,21 +9444,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[405] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a4d9,
+ .class_hid = BNXT_ULP_CLASS_HID_10201,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1610877952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8863,21 +9467,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[406] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d759,
+ .class_hid = BNXT_ULP_CLASS_HID_116c1,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1610886144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8885,22 +9488,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[407] = {
- .class_hid = BNXT_ULP_CLASS_HID_2573d,
+ .class_hid = BNXT_ULP_CLASS_HID_14605,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611926528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8908,21 +9510,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[408] = {
- .class_hid = BNXT_ULP_CLASS_HID_279bd,
+ .class_hid = BNXT_ULP_CLASS_HID_15a05,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1611934720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8930,22 +9532,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[409] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f27d,
+ .class_hid = BNXT_ULP_CLASS_HID_12007,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1612975104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8953,22 +9555,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[410] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e4fd,
+ .class_hid = BNXT_ULP_CLASS_HID_13407,
.class_tid = 2,
- .hdr_sig_id = 2,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 3,
+ .flow_sig_id = 1612983296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -8976,23 +9577,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[411] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fbe,
+ .class_hid = BNXT_ULP_CLASS_HID_1640b,
.class_tid = 2,
.hdr_sig_id = 3,
- .flow_sig_id = 265216UL,
+ .flow_sig_id = 1614023680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9001,18 +9601,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[412] = {
- .class_hid = BNXT_ULP_CLASS_HID_201fa,
+ .class_hid = BNXT_ULP_CLASS_HID_1780b,
.class_tid = 2,
.hdr_sig_id = 3,
- .flow_sig_id = 273408UL,
+ .flow_sig_id = 1614031872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -9021,2224 +9624,16438 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
},
[413] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ecf6,
+ .class_hid = BNXT_ULP_CLASS_HID_404b0,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
},
[414] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a732,
+ .class_hid = BNXT_ULP_CLASS_HID_4148c,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
},
[415] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e52,
+ .class_hid = BNXT_ULP_CLASS_HID_514c0,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50bba,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ },
+ [417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c88,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48362,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_583b6,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_593f2,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ },
+ [421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41f54,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40fce,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50e02,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51e5e,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487ca,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49606,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5965a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58514,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412c2,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_401ac,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_501e0,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_511cc,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4990a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_489e4,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_589c8,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59804,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40404,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41440,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51484,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b0e,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c4c,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48306,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5830a,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59346,
+ .class_tid = 2,
+ .hdr_sig_id = 4,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102cc,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ },
+ [446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116ec,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ },
+ [447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_146d0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15af0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ },
+ [449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_120c2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134e2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16b26,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_178c6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ },
+ [453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115c6,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10804,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15822,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c60,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13bd4,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12e12,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e30,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17276,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f1a,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11358,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14398,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_157b8,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d68,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_131aa,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16192,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_175b2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_112b2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_106f0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15692,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ad0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13080,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_124c2,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174e0,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f22,
+ .class_tid = 2,
+ .hdr_sig_id = 5,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4025b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ },
+ [478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41267,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ },
+ [479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5122b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ },
+ [480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d51,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ },
+ [481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48a63,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48589,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5855d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59519,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ },
+ [485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e17,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134284032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4093d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134286080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50941,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134546176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5190d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134548224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48139,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134808320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49145,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 134810368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59109,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 135070464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58037,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 135072512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4143d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268501760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4079b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268503808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507af,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268763904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 268765952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c05,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269026048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fa3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269028096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f37,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269288192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f33,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 269290240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4030b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402719488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41317,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402721536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5131b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402981632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50201,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 402983680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b13,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403243776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49b1f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403245824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403505920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a09,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 403507968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419bf,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508e9,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518b5,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_490ed,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590b1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_583ff,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41475,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671154944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40473,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671156992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50427,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671417088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51763,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c3d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671679232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c3b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671681280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f6f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671941376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 671943424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40333,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805372672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412bf,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805374720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512a3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805634816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50229,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805636864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48abb,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805896960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49aa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 805899008UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59a2b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 806159104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595b1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 806161152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e2f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939590400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40e35,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939592448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50939,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939852544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 939854592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48631,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940114688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4913d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940116736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940376832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5812f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 940378880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT }
+ },
+ [541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41429,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40747,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5070b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51727,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49fe1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58f23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59eef,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40347,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208025856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41303,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208027904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51247,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208288000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5026d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208290048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208550144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a4b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208552192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59a0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208812288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a05,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1208814336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41983,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342243584UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40929,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342245632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5092d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342505728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518a9,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342507776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48125,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342767872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49121,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1342769920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59085,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1343030016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58023,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1343032064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41509,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476461312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40407,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476463360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5040b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476723456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51407,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476725504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d21,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476985600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48c0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1476987648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c03,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1477247744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f0f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1477249792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402ef,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412ab,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5126f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50de5,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_485ed,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585e1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595ad,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41e6b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1744896768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40961,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1744898816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50925,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745158912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51961,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745160960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4816d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745421056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49129,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745423104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5916d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745683200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5806b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1745685248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414a1,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879114496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4042f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879116544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507a3,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879376640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517af,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879378688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49c29,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879638784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fa7,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879640832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58fab,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879900928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 1879902976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4032f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013332224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4132b,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013334272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5132f,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013594368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50225,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013596416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013856512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49b23,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2013858560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b27,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2014118656UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58a2d,
+ .class_tid = 2,
+ .hdr_sig_id = 6,
+ .flow_sig_id = 2014120704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT }
+ },
+ [605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10437,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ },
+ [606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11017,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ },
+ [607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1402b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ },
+ [608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c0b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ },
+ [609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12639,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13219,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ddd,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e3d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ },
+ [613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11333,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 537136128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10ef5,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 537144320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f37,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 538184704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ae9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 538192896UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d25,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 539233280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128e7,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 539241472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17939,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 540281856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174fb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 540290048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10985,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1074007040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10547,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1074015232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_155a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1075055616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1416b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1075063808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ba7,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1076104192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12749,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1076112384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_177ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1077152768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1636d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1077160960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10463,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1610877952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_110a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1610886144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14067,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1611926528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c67,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1611934720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12665,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1612975104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13265,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1612983296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16269,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1614023680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 1614031872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1133d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10eff,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ed9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a9b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d2f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128e9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_178cb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1748d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_109fb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2684619776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_105bd,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2684627968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_155bf,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2685668352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14179,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2685676544UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12bed,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2686716928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_127af,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2686725120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [651] = {
+ .class_hid = BNXT_ULP_CLASS_HID_177a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2687765504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [652] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1636b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 2687773696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [653] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1046d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3221490688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [654] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1104d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3221498880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [655] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14009,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3222539264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [656] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3222547456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [657] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1260f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3223587840UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [658] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1326f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3223596032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [659] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1622b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3224636416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [660] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e0b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3224644608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [661] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11369,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3758361600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [662] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3758369792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [663] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f6d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3759410176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [664] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14b2f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3759418368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [665] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13d6b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3760458752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [666] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1292d,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3760466944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [667] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1792f,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3761507328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [668] = {
+ .class_hid = BNXT_ULP_CLASS_HID_174e9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 3761515520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT }
+ },
+ [669] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119e1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [670] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [671] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14563,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [672] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15143,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [673] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b93,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [674] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13751,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [675] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16769,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [676] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17349,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [677] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4832103424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [678] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10061,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4832111616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [679] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15063,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4833152000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [680] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c21,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4833160192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [681] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13671,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4834200576UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [682] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12233,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4834208768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [683] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17271,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4835249152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [684] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e33,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 4835257344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [685] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102c1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5368974336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [686] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f21,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5368982528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [687] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ee1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5370022912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [688] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ac1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5370031104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [689] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12cc3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5371071488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [690] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13923,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5371079680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [691] = {
+ .class_hid = BNXT_ULP_CLASS_HID_168e3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5372120064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [692] = {
+ .class_hid = BNXT_ULP_CLASS_HID_164a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5372128256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [693] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e29,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5905845248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [694] = {
+ .class_hid = BNXT_ULP_CLASS_HID_115eb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5905853440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [695] = {
+ .class_hid = BNXT_ULP_CLASS_HID_145a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5906893824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [696] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151a3,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5906902016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [697] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1382b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5907942400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [698] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137e1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5907950592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [699] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167a1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5908990976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [700] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173a1,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 5908999168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [701] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11449,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [702] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1000b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [703] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15069,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [704] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [705] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1367b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [706] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12239,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [707] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1721b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [708] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169d9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [709] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1033b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6979587072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [710] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11f3b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6979595264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [711] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14f2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6980635648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [712] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15b2b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6980643840UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [713] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d39,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6981684224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [714] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13939,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6981692416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [715] = {
+ .class_hid = BNXT_ULP_CLASS_HID_168f9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6982732800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [716] = {
+ .class_hid = BNXT_ULP_CLASS_HID_164bb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 6982740992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [717] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119cb,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7516457984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [718] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11589,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7516466176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [719] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14549,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7517506560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [720] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7517514752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [721] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13bc9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7518555136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [722] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1378b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7518563328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [723] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1674b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7519603712UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [724] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 7519611904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [725] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8053328896UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [726] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1006b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8053337088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [727] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150a9,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8054377472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [728] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14c6b,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8054385664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [729] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8055426048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [730] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12269,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8055434240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [731] = {
+ .class_hid = BNXT_ULP_CLASS_HID_172ab,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8056474624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [732] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e69,
+ .class_tid = 2,
+ .hdr_sig_id = 7,
+ .flow_sig_id = 8056482816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT }
+ },
+ [733] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402d2,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI }
+ },
+ [734] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI }
+ },
+ [735] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512a2,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC }
+ },
+ [736] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50dd8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC }
+ },
+ [737] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aea,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [738] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48500,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [739] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585d4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [740] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59590,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC }
+ },
+ [741] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41936,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [742] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [743] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50860,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [744] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5183c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [745] = {
+ .class_hid = BNXT_ULP_CLASS_HID_481a8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [746] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49064,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [747] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59038,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [748] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58376,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [749] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414a0,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [750] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [751] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50782,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [752] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [753] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f68,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [754] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f86,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [755] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58faa,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [756] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59e66,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [757] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40266,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [758] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41222,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [759] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512e6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [760] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [761] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48a2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [762] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48564,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [763] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58568,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [764] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59524,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [765] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419d8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147549952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [766] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4087e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147552000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [767] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5080a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147812096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [768] = {
+ .class_hid = BNXT_ULP_CLASS_HID_518ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2147814144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [769] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4807a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148074240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [770] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4900e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148076288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [771] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590ca,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148336384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [772] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58378,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2148338432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [773] = {
+ .class_hid = BNXT_ULP_CLASS_HID_414be,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684420864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [774] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4073c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684422912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [775] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507e8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684683008UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [776] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684685056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [777] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f7e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684945152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [778] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48fec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2684947200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [779] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58fa8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2685207296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [780] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59e7c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 2685209344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [781] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40208,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221291776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [782] = {
+ .class_hid = BNXT_ULP_CLASS_HID_412cc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221293824UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [783] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51288,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221553920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [784] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221555968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [785] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48ac8,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221816064UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [786] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4856e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3221818112UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [787] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5852a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3222078208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [788] = {
+ .class_hid = BNXT_ULP_CLASS_HID_595ce,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3222080256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [789] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4196c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758162688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [790] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409aa,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758164736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [791] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5086e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758424832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [792] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5182a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758426880UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [793] = {
+ .class_hid = BNXT_ULP_CLASS_HID_481ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758686976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [794] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4906a,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758689024UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [795] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5902e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758949120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [796] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 3758951168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT }
+ },
+ [797] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40766,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295033600UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [798] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41726,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295035648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [799] = {
+ .class_hid = BNXT_ULP_CLASS_HID_517f6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295295744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [800] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5066c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295297792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [801] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f3e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295557888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [802] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49ffe,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295559936UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [803] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59f8e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295820032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [804] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e24,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4295822080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [805] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4126e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4831904512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [806] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402e4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4831906560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [807] = {
+ .class_hid = BNXT_ULP_CLASS_HID_502b4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832166656UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [808] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51d74,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832168704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [809] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a26,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832428800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [810] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48abc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832430848UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [811] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5956c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832690944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [812] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 4832692992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [813] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409e4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5368775424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [814] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419a4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5368777472UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [815] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51844,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369037568UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [816] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508e6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369039616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [817] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4918c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369299712UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [818] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4802e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369301760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [819] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369561856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [820] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5369563904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [821] = {
+ .class_hid = BNXT_ULP_CLASS_HID_404ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905646336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [822] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41766,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905648384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [823] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905908480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [824] = {
+ .class_hid = BNXT_ULP_CLASS_HID_507a4,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5905910528UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [825] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f66,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906170624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [826] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f2e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906172672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [827] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59fe6,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906432768UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [828] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 5906434816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [829] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4126c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442517248UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [830] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4028e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442519296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [831] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50d5e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442779392UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [832] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51d1e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6442781440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [833] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a2c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443041536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [834] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4954e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443043584UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [835] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5951e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443303680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [836] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5858c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6443305728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [837] = {
+ .class_hid = BNXT_ULP_CLASS_HID_409fe,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979388160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [838] = {
+ .class_hid = BNXT_ULP_CLASS_HID_419ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979390208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [839] = {
+ .class_hid = BNXT_ULP_CLASS_HID_519ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979650304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [840] = {
+ .class_hid = BNXT_ULP_CLASS_HID_508fc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979652352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [841] = {
+ .class_hid = BNXT_ULP_CLASS_HID_491ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979912448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [842] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4802c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6979914496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [843] = {
+ .class_hid = BNXT_ULP_CLASS_HID_580fc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6980174592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [844] = {
+ .class_hid = BNXT_ULP_CLASS_HID_590bc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 6980176640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [845] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4074c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516259072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [846] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4170c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516261120UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [847] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5172c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516521216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [848] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5064e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516523264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [849] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f0c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516783360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [850] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49fcc,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7516785408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [851] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59fec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7517045504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [852] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e0e,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 7517047552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [853] = {
+ .class_hid = BNXT_ULP_CLASS_HID_413ac,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053129984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [854] = {
+ .class_hid = BNXT_ULP_CLASS_HID_402ee,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053132032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [855] = {
+ .class_hid = BNXT_ULP_CLASS_HID_502ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053392128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [856] = {
+ .class_hid = BNXT_ULP_CLASS_HID_512ae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053394176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [857] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49a6c,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053654272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [858] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48aae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053656320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [859] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58aae,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053916416UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [860] = {
+ .class_hid = BNXT_ULP_CLASS_HID_585ec,
+ .class_tid = 2,
+ .hdr_sig_id = 8,
+ .flow_sig_id = 8053918464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT }
+ },
+ [861] = {
+ .class_hid = BNXT_ULP_CLASS_HID_104ae,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 265216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI }
+ },
+ [862] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1108e,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 273408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI }
+ },
+ [863] = {
+ .class_hid = BNXT_ULP_CLASS_HID_140b2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 1313792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC }
+ },
+ [864] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c92,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 1321984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC }
+ },
+ [865] = {
+ .class_hid = BNXT_ULP_CLASS_HID_126a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2362368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [866] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13280,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2370560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [867] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16d44,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 3410944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [868] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ea4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 3419136UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC }
+ },
+ [869] = {
+ .class_hid = BNXT_ULP_CLASS_HID_113a4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2147748864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [870] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e66,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2147757056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [871] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e40,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2148797440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [872] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a02,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2148805632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [873] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13db6,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2149846016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [874] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12870,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2149854208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [875] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17852,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2150894592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [876] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17414,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 2150902784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR }
+ },
+ [877] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11978,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4295232512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [878] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1153a,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4295240704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [879] = {
+ .class_hid = BNXT_ULP_CLASS_HID_145fa,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4296281088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [880] = {
+ .class_hid = BNXT_ULP_CLASS_HID_151da,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4296289280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [881] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b0a,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4297329664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [882] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137c8,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4297337856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [883] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167f0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4298378240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [884] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 4298386432UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [885] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6442716160UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [886] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10092,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6442724352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [887] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150f0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6443764736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [888] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14cb2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6443772928UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [889] = {
+ .class_hid = BNXT_ULP_CLASS_HID_136e2,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6444813312UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [890] = {
+ .class_hid = BNXT_ULP_CLASS_HID_122a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6444821504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [891] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17282,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6445861888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [892] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16940,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 6445870080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR }
+ },
+ [893] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b90,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8590199808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [894] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11654,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8590208000UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [895] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14618,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8591248384UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [896] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15278,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8591256576UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [897] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12404,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8592296960UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [898] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13064,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8592305152UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [899] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16028,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8593345536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [900] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c08,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 8593353728UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [901] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11100,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10737683456UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [902] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10dc4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10737691648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [903] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d24,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10738732032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [904] = {
+ .class_hid = BNXT_ULP_CLASS_HID_149d0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10738740224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [905] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13314,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10739780608UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [906] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12fd4,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10739788800UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [907] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17f20,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10740829184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [908] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16be0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 10740837376UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [909] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11cd8,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12885167104UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [910] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10880,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12885175296UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [911] = {
+ .class_hid = BNXT_ULP_CLASS_HID_158e0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12886215680UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [912] = {
+ .class_hid = BNXT_ULP_CLASS_HID_154a0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12886223872UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [913] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ed0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12887264256UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [914] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a90,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12887272448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [915] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16550,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12888312832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [916] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176b0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 12888321024UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [917] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bb0,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15032650752UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [918] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10670,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15032658944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [919] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15650,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15033699328UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [920] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14210,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15033707520UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [921] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13440,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15034747904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [922] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12000,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15034756096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [923] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17060,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15035796480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [924] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c20,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 15035804672UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT }
+ },
+ [925] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11511,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17180134400UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [926] = {
+ .class_hid = BNXT_ULP_CLASS_HID_101d3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17180142592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [927] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15135,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17181182976UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [928] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14df7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17181191168UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [929] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13723,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17182231552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [930] = {
+ .class_hid = BNXT_ULP_CLASS_HID_123e5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17182239744UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [931] = {
+ .class_hid = BNXT_ULP_CLASS_HID_173c7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17183280128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [932] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f89,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 17183288320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [933] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10081,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19327618048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [934] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11ce1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19327626240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [935] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ca5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19328666624UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [936] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15885,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19328674816UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [937] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12293,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19329715200UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [938] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ef3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19329723392UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [939] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16eb7,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19330763776UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [940] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16561,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 19330771968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [941] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e59,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21475101696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [942] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bb9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21475109888UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [943] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14a61,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21476150272UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [944] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14623,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21476158464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [945] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1286b,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21477198848UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [946] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12411,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21477207040UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [947] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17473,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21478247424UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [948] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16031,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 21478255616UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [949] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10531,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23622585344UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [950] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11111,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23622593536UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [951] = {
+ .class_hid = BNXT_ULP_CLASS_HID_141d1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23623633920UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [952] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d31,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23623642112UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [953] = {
+ .class_hid = BNXT_ULP_CLASS_HID_127c3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23624682496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [954] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13323,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23624690688UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [955] = {
+ .class_hid = BNXT_ULP_CLASS_HID_163e3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23625731072UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [956] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17fc3,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 23625739264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [957] = {
+ .class_hid = BNXT_ULP_CLASS_HID_108f5,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25770068992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [958] = {
+ .class_hid = BNXT_ULP_CLASS_HID_104b9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25770077184UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [959] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15499,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25771117568UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [960] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1435d,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25771125760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [961] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a89,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25772166144UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [962] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12149,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25772174336UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [963] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176ad,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25773214720UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [964] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16d6d,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 25773222912UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [965] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10665,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27917552640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [966] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11245,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27917560832UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [967] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14271,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27918601216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [968] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e51,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27918609408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [969] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12061,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27919649792UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [970] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13c41,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27919657984UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [971] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c05,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27920698368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [972] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17865,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 27920706560UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [973] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10d21,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30065036288UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [974] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11901,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30065044480UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [975] = {
+ .class_hid = BNXT_ULP_CLASS_HID_149c1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30066084864UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [976] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14589,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30066093056UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [977] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12f31,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30067133440UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [978] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b11,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30067141632UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [979] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bd9,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30068182016UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [980] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16799,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 30068190208UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [981] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11831,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32212519936UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [982] = {
+ .class_hid = BNXT_ULP_CLASS_HID_114f1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32212528128UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [983] = {
+ .class_hid = BNXT_ULP_CLASS_HID_144b1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32213568512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [984] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15091,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32213576704UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [985] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ac1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32214617088UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [986] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13681,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32214625280UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [987] = {
+ .class_hid = BNXT_ULP_CLASS_HID_166b1,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32215665664UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [988] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17291,
+ .class_tid = 2,
+ .hdr_sig_id = 9,
+ .flow_sig_id = 32215673856UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT |
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT }
+ },
+ [989] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4007d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI }
+ },
+ [990] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41041,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI }
+ },
+ [991] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5100d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC }
+ },
+ [992] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f77,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC }
+ },
+ [993] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48845,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [994] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487af,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [995] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5877b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [996] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5973f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC }
+ },
+ [997] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c31,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134284032UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [998] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b1b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134286080UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [999] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b67,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134546176UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1000] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b2b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134548224UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1001] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4831f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134808320UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1002] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49363,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 134810368UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1003] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5932f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 135070464UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1004] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58211,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 135072512UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR }
+ },
+ [1005] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4161b,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268501760UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1006] = {
+ .class_hid = BNXT_ULP_CLASS_HID_405bd,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268503808UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1007] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50589,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268763904UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1008] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5150d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 268765952UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1009] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e23,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269026048UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1010] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d85,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269028096UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1011] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d11,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269288192UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1012] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d15,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 269290240UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1013] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4012d,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402719488UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [416] = {
- .class_hid = BNXT_ULP_CLASS_HID_2509e,
+ [1014] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41131,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402721536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [417] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c45e,
+ [1015] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5113d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402981632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [418] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f5d6,
+ [1016] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50027,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 402983680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [419] = {
- .class_hid = BNXT_ULP_CLASS_HID_23722,
+ [1017] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48935,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403243776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [420] = {
- .class_hid = BNXT_ULP_CLASS_HID_209ae,
+ [1018] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49939,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403245824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
},
- [421] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d4ba,
+ [1019] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59905,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403505920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1020] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5882f,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 403507968UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR }
+ },
+ [1021] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b99,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1022] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b03,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1023] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50acf,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1024] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a93,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1025] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48307,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1026] = {
+ .class_hid = BNXT_ULP_CLASS_HID_492cb,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1027] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59297,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1028] = {
+ .class_hid = BNXT_ULP_CLASS_HID_581d9,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1029] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41653,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671154944UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
+ },
+ [1030] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40655,
+ .class_tid = 2,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671156992UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [422] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aea6,
+ [1031] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50601,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671417088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [423] = {
- .class_hid = BNXT_ULP_CLASS_HID_24606,
+ [1032] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51545,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [424] = {
- .class_hid = BNXT_ULP_CLASS_HID_25802,
+ [1033] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e1b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671679232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [425] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc02,
+ [1034] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48e1d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671681280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [426] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fd9a,
+ [1035] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d49,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671941376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [427] = {
- .class_hid = BNXT_ULP_CLASS_HID_207c2,
+ [1036] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d0d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 671943424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [428] = {
- .class_hid = BNXT_ULP_CLASS_HID_2315a,
+ [1037] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40115,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805372672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [429] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a51a,
+ [1038] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41099,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805374720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [430] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d692,
+ [1039] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51085,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805634816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [431] = {
- .class_hid = BNXT_ULP_CLASS_HID_25686,
+ [1040] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5000f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805636864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [432] = {
- .class_hid = BNXT_ULP_CLASS_HID_2401e,
+ [1041] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4889d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805896960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [433] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cbde,
+ [1042] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49881,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 805899008UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [434] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce1a,
+ [1043] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5980d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 806159104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [435] = {
- .class_hid = BNXT_ULP_CLASS_HID_20f96,
+ [1044] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59797,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 806161152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [436] = {
- .class_hid = BNXT_ULP_CLASS_HID_2390e,
+ [1045] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c09,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939590400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [437] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ac8e,
+ [1046] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c13,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939592448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [438] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de06,
+ [1047] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b1f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939852544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [439] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e0a,
+ [1048] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b03,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 939854592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [440] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f82,
+ [1049] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48417,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940114688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [441] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f382,
+ [1050] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4931b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940116736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [442] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ed1a,
+ [1051] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59307,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940376832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [443] = {
- .class_hid = BNXT_ULP_CLASS_HID_2576e,
+ [1052] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58309,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 940378880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT }
},
- [444] = {
- .class_hid = BNXT_ULP_CLASS_HID_229aa,
+ [1053] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4160f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1073808128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [445] = {
- .class_hid = BNXT_ULP_CLASS_HID_29d6a,
+ [1054] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40561,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1073810176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [446] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cee2,
+ [1055] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5052d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074070272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [447] = {
- .class_hid = BNXT_ULP_CLASS_HID_24ec6,
+ [1056] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51501,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074072320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [448] = {
- .class_hid = BNXT_ULP_CLASS_HID_2784e,
+ [1057] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dc7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074332416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [449] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ec0e,
+ [1058] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074334464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [450] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd86,
+ [1059] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d05,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074594560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [451] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f22,
+ [1060] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59cc9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2684619776UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1074596608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [452] = {
- .class_hid = BNXT_ULP_CLASS_HID_2112e,
+ [1061] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40161,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2684627968UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208025856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [453] = {
- .class_hid = BNXT_ULP_CLASS_HID_2852e,
+ [1062] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41125,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2685668352UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208027904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [454] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b6a6,
+ [1063] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51061,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2685676544UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208288000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [455] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d86,
+ [1064] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5004b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2686716928UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [456] = {
- .class_hid = BNXT_ULP_CLASS_HID_26002,
+ [1065] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48929,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2686725120UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208550144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [457] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eb82,
+ [1066] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4986d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2687765504UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208552192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [458] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c50a,
+ [1067] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59829,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 2687773696UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208812288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [459] = {
- .class_hid = BNXT_ULP_CLASS_HID_22f82,
+ [1068] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58823,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3221490688UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1208814336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [460] = {
- .class_hid = BNXT_ULP_CLASS_HID_2590a,
+ [1069] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41ba5,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3221498880UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342243584UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [461] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ccca,
+ [1070] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b0f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3222539264UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342245632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [462] = {
- .class_hid = BNXT_ULP_CLASS_HID_28706,
+ [1071] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b0b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3222547456UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342505728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [463] = {
- .class_hid = BNXT_ULP_CLASS_HID_27e46,
+ [1072] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a8f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3223587840UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342507776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [464] = {
- .class_hid = BNXT_ULP_CLASS_HID_26fce,
+ [1073] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48303,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3223596032UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342767872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [465] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d38e,
+ [1074] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49307,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3224636416UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1342769920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [466] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d5ca,
+ [1075] = {
+ .class_hid = BNXT_ULP_CLASS_HID_592a3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3224644608UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1343030016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [467] = {
- .class_hid = BNXT_ULP_CLASS_HID_21706,
+ [1076] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58205,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3758361600UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1343032064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [468] = {
- .class_hid = BNXT_ULP_CLASS_HID_2408e,
+ [1077] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4172f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3758369792UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476461312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [469] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b48e,
+ [1078] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40621,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3759410176UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476463360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [470] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e8a,
+ [1079] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5062d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3759418368UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476723456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [471] = {
- .class_hid = BNXT_ULP_CLASS_HID_2660a,
+ [1080] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51621,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3760458752UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476725504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [472] = {
- .class_hid = BNXT_ULP_CLASS_HID_25782,
+ [1081] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49f07,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3760466944UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476985600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [473] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db02,
+ [1082] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48e29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3761507328UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1476987648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [474] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd8e,
+ [1083] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58e25,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 3761515520UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1477247744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [475] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b9e,
+ [1084] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d29,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1477249792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [476] = {
- .class_hid = BNXT_ULP_CLASS_HID_21dda,
+ [1085] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610679040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [477] = {
- .class_hid = BNXT_ULP_CLASS_HID_2819a,
+ [1086] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4108d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610681088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [478] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b31a,
+ [1087] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51049,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610941184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [479] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a3a,
+ [1088] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50fc3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1610943232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [480] = {
- .class_hid = BNXT_ULP_CLASS_HID_26c7e,
+ [1089] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48881,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611203328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [481] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d03e,
+ [1090] = {
+ .class_hid = BNXT_ULP_CLASS_HID_487cb,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611205376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [482] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c1be,
+ [1091] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587c7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611465472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [483] = {
- .class_hid = BNXT_ULP_CLASS_HID_2430a,
+ [1092] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5978b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4832103424UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1611467520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [484] = {
- .class_hid = BNXT_ULP_CLASS_HID_2058e,
+ [1093] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c4d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4832111616UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1744896768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [485] = {
- .class_hid = BNXT_ULP_CLASS_HID_2890e,
+ [1094] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b47,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4833152000UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1744898816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [486] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba8e,
+ [1095] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50b03,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4833160192UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745158912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [487] = {
- .class_hid = BNXT_ULP_CLASS_HID_251ae,
+ [1096] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b47,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4834200576UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [488] = {
- .class_hid = BNXT_ULP_CLASS_HID_2542a,
+ [1097] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4834b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4834208768UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745421056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [489] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfaa,
+ [1098] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4930f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4835249152UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745423104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [490] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c93a,
+ [1099] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5934b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 4835257344UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745683200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [491] = {
- .class_hid = BNXT_ULP_CLASS_HID_213ca,
+ [1100] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5824d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5368974336UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1745685248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [492] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d5a,
+ [1101] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41687,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5368982528UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879114496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [493] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b11a,
+ [1102] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40609,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5370022912UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879116544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [494] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b4e,
+ [1103] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50585,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5370031104UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879376640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [495] = {
- .class_hid = BNXT_ULP_CLASS_HID_2624e,
+ [1104] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51589,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5371071488UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879378688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [496] = {
- .class_hid = BNXT_ULP_CLASS_HID_253de,
+ [1105] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e0f,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5371079680UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879638784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [497] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c79e,
+ [1106] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d81,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5372120064UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879640832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [498] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d9da,
+ [1107] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5372128256UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879900928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [499] = {
- .class_hid = BNXT_ULP_CLASS_HID_21b1e,
+ [1108] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59d01,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5905845248UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 1879902976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [500] = {
- .class_hid = BNXT_ULP_CLASS_HID_2350e,
+ [1109] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40109,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5905853440UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013332224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [501] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b88e,
+ [1110] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4110d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5906893824UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013334272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [502] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ea0e,
+ [1111] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51109,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5906902016UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013594368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [503] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a0a,
+ [1112] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50003,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5907942400UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013596416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [504] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b8a,
+ [1113] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48901,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5907950592UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013856512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [505] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cf0a,
+ [1114] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49905,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5908990976UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2013858560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [506] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c18e,
+ [1115] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59901,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 5908999168UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2014118656UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [507] = {
- .class_hid = BNXT_ULP_CLASS_HID_2634e,
+ [1116] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5880b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 10,
+ .flow_sig_id = 2014120704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT }
},
- [508] = {
- .class_hid = BNXT_ULP_CLASS_HID_2258a,
+ [1117] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10619,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11247,21 +26064,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI }
},
- [509] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a94a,
+ [1118] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11239,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11270,21 +26084,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI }
},
- [510] = {
- .class_hid = BNXT_ULP_CLASS_HID_2daca,
+ [1119] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14205,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11293,22 +26105,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC }
},
- [511] = {
- .class_hid = BNXT_ULP_CLASS_HID_25aae,
+ [1120] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e25,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11317,21 +26126,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC }
},
- [512] = {
- .class_hid = BNXT_ULP_CLASS_HID_2742e,
+ [1121] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12417,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11340,22 +26148,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [513] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ffee,
+ [1122] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13037,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11364,22 +26169,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [514] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e96e,
+ [1123] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ff3,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11388,23 +26191,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [515] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b0a,
+ [1124] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c13,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6979587072UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11413,21 +26213,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC }
},
- [516] = {
- .class_hid = BNXT_ULP_CLASS_HID_22d0e,
+ [1125] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1111d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6979595264UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 537136128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11436,22 +26236,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [517] = {
- .class_hid = BNXT_ULP_CLASS_HID_2910e,
+ [1126] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10cdb,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6980635648UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 537144320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11460,22 +26257,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [518] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c28e,
+ [1127] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d19,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6980643840UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 538184704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11484,23 +26279,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [519] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422a,
+ [1128] = {
+ .class_hid = BNXT_ULP_CLASS_HID_148c7,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6981684224UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 538192896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11509,22 +26301,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [520] = {
- .class_hid = BNXT_ULP_CLASS_HID_273aa,
+ [1129] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f0b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6981692416UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 539233280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11533,23 +26324,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [521] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e7aa,
+ [1130] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ac9,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6982732800UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 539241472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11558,23 +26346,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [522] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d12a,
+ [1131] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17b17,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 6982740992UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 540281856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11583,24 +26369,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [523] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b8a,
+ [1132] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176d5,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7516457984UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 540290048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11609,21 +26392,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR }
},
- [524] = {
- .class_hid = BNXT_ULP_CLASS_HID_2550a,
+ [1133] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bab,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7516466176UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1074007040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11632,22 +26416,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [525] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d8ca,
+ [1134] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10769,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7517506560UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1074015232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11656,22 +26437,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [526] = {
- .class_hid = BNXT_ULP_CLASS_HID_2930e,
+ [1135] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15787,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7517514752UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1075055616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11680,23 +26459,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [527] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a0e,
+ [1136] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14345,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7518555136UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1075063808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11705,22 +26481,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [528] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c4a,
+ [1137] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12989,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7518563328UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1076104192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11729,23 +26504,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [529] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ef4e,
+ [1138] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12567,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7519603712UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1076112384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11754,23 +26526,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [530] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e18a,
+ [1139] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17585,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 7519611904UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1077152768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11779,24 +26549,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [531] = {
- .class_hid = BNXT_ULP_CLASS_HID_2230e,
+ [1140] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16143,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8053328896UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1077160960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11805,22 +26572,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [532] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c8e,
+ [1141] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1064d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8053337088UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1610877952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11829,23 +26596,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [533] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c08e,
+ [1142] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1128d,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8054377472UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1610886144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11854,23 +26618,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [534] = {
- .class_hid = BNXT_ULP_CLASS_HID_29a8a,
+ [1143] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14249,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8054385664UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1611926528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11879,24 +26641,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [535] = {
- .class_hid = BNXT_ULP_CLASS_HID_2718a,
+ [1144] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e49,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8055426048UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1611934720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11905,23 +26664,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [536] = {
- .class_hid = BNXT_ULP_CLASS_HID_2630a,
+ [1145] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1244b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8055434240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1612975104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11930,24 +26688,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [537] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d70a,
+ [1146] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1304b,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8056474624UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1612983296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11956,24 +26711,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [538] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e90e,
+ [1147] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16047,
.class_tid = 2,
- .hdr_sig_id = 3,
- .flow_sig_id = 8056482816UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1614023680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -11982,25 +26735,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV6 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [539] = {
- .class_hid = BNXT_ULP_CLASS_HID_24e91,
+ [1148] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c47,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 1614031872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12008,19 +26758,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR }
},
- [540] = {
- .class_hid = BNXT_ULP_CLASS_HID_200d5,
+ [1149] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11113,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2147748864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12028,20 +26783,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [541] = {
- .class_hid = BNXT_ULP_CLASS_HID_2edd9,
+ [1150] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10cd1,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2147757056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12049,20 +26804,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [542] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a61d,
+ [1151] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15cf7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2148797440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12070,21 +26826,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [543] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f7d,
+ [1152] = {
+ .class_hid = BNXT_ULP_CLASS_HID_148b5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2148805632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12092,20 +26848,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [544] = {
- .class_hid = BNXT_ULP_CLASS_HID_251b1,
+ [1153] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f01,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2149846016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12113,21 +26871,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [545] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c571,
+ [1154] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12ac7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2149854208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12135,21 +26893,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [546] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f4f9,
+ [1155] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17ae5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2150894592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12157,22 +26916,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [547] = {
- .class_hid = BNXT_ULP_CLASS_HID_25641,
+ [1156] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176a3,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2150902784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12180,20 +26939,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [548] = {
- .class_hid = BNXT_ULP_CLASS_HID_22885,
+ [1157] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10bd5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2684619776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12201,21 +26963,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [549] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c45,
+ [1158] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10793,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2684627968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12223,21 +26985,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [550] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cfcd,
+ [1159] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15791,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2685668352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12245,22 +27008,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [551] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fe9,
+ [1160] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14357,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2685676544UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12268,21 +27031,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [552] = {
- .class_hid = BNXT_ULP_CLASS_HID_27961,
+ [1161] = {
+ .class_hid = BNXT_ULP_CLASS_HID_129c3,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2686716928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12290,22 +27055,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [553] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ed21,
+ [1162] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12581,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2686725120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12313,22 +27078,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [554] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dca9,
+ [1163] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17587,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2687765504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12336,23 +27102,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [555] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ab1,
+ [1164] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16145,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 2687773696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12360,20 +27126,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [556] = {
- .class_hid = BNXT_ULP_CLASS_HID_21cf5,
+ [1165] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10643,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3221490688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12381,21 +27151,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [557] = {
- .class_hid = BNXT_ULP_CLASS_HID_280b5,
+ [1166] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11263,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3221498880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12403,21 +27173,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [558] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b235,
+ [1167] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14227,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3222539264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12425,22 +27196,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [559] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b15,
+ [1168] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e47,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3222547456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12448,21 +27219,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [560] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d51,
+ [1169] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12421,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3223587840UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12470,22 +27243,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [561] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d111,
+ [1170] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13041,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3223596032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12493,22 +27266,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [562] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c091,
+ [1171] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16005,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3224636416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12516,23 +27290,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [563] = {
- .class_hid = BNXT_ULP_CLASS_HID_26261,
+ [1172] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c25,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3224644608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12540,21 +27314,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [564] = {
- .class_hid = BNXT_ULP_CLASS_HID_224a5,
+ [1173] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11147,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3758361600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12562,22 +27339,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [565] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a865,
+ [1174] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10d05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3758369792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12585,22 +27362,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [566] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dbe5,
+ [1175] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15d43,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3759410176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12608,23 +27386,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [567] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b81,
+ [1176] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14901,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3759418368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12632,22 +27410,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [568] = {
- .class_hid = BNXT_ULP_CLASS_HID_27501,
+ [1177] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f45,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3760458752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12655,23 +27435,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [569] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fec1,
+ [1178] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12b03,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3760466944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12679,23 +27459,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [570] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e841,
+ [1179] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17b01,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3761507328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12703,24 +27484,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [571] = {
- .class_hid = BNXT_ULP_CLASS_HID_24085,
+ [1180] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176c7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8590199808UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 3761515520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12728,20 +27509,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT }
},
- [572] = {
- .class_hid = BNXT_ULP_CLASS_HID_21ac5,
+ [1181] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bcf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8590208000UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4295232512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12749,21 +27535,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [573] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e85,
+ [1182] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1178d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8591248384UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4295240704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12771,21 +27556,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [574] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b80d,
+ [1183] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1474d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8591256576UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4296281088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12793,22 +27578,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [575] = {
- .class_hid = BNXT_ULP_CLASS_HID_2516d,
+ [1184] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1536d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8592296960UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4296289280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12816,21 +27600,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [576] = {
- .class_hid = BNXT_ULP_CLASS_HID_26ba5,
+ [1185] = {
+ .class_hid = BNXT_ULP_CLASS_HID_139bd,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8592305152UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4297329664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12838,22 +27623,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [577] = {
- .class_hid = BNXT_ULP_CLASS_HID_2df65,
+ [1186] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1357f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8593345536UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4297337856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12861,22 +27645,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [578] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ceed,
+ [1187] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16547,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 8593353728UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4298378240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12884,23 +27668,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [579] = {
- .class_hid = BNXT_ULP_CLASS_HID_26845,
+ [1188] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17167,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10737683456UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4298386432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12908,21 +27691,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [580] = {
- .class_hid = BNXT_ULP_CLASS_HID_22285,
+ [1189] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11685,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10737691648UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4832103424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12930,22 +27715,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [581] = {
- .class_hid = BNXT_ULP_CLASS_HID_29645,
+ [1190] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1024f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10738732032UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4832111616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12953,22 +27737,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [582] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c1cd,
+ [1191] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1524d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10738740224UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4833152000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -12976,23 +27760,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [583] = {
- .class_hid = BNXT_ULP_CLASS_HID_2418d,
+ [1192] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e0f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10739780608UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4833160192UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13000,22 +27783,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [584] = {
- .class_hid = BNXT_ULP_CLASS_HID_27365,
+ [1193] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1345f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10739788800UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4834200576UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13023,23 +27807,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [585] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e725,
+ [1194] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1201d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10740829184UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4834208768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13047,23 +27830,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [586] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d6ad,
+ [1195] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 10740837376UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4835249152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13071,24 +27854,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [587] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ca5,
+ [1196] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c1d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12885167104UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 4835257344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13096,21 +27878,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [588] = {
- .class_hid = BNXT_ULP_CLASS_HID_216e5,
+ [1197] = {
+ .class_hid = BNXT_ULP_CLASS_HID_100ef,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12885175296UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5368974336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13118,45 +27903,44 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [589] = {
- .class_hid = BNXT_ULP_CLASS_HID_29aa5,
+ [1198] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d0f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12886215680UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5368982528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [590] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b425,
+ [1199] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14ccf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12886223872UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5370022912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13164,23 +27948,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [591] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d05,
+ [1200] = {
+ .class_hid = BNXT_ULP_CLASS_HID_158ef,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12887264256UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5370031104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13188,22 +27971,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [592] = {
- .class_hid = BNXT_ULP_CLASS_HID_26745,
+ [1201] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12eed,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12887272448UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5371071488UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13211,23 +27995,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [593] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eb05,
+ [1202] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b0d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12888312832UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5371079680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13235,23 +28018,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [594] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da85,
+ [1203] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16acd,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 12888321024UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5372120064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13259,24 +28042,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [595] = {
- .class_hid = BNXT_ULP_CLASS_HID_20cc5,
+ [1204] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16687,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15032650752UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5372128256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13284,22 +28066,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [596] = {
- .class_hid = BNXT_ULP_CLASS_HID_23ea5,
+ [1205] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11c07,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15032658944UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5905845248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13307,23 +28091,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [597] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a265,
+ [1206] = {
+ .class_hid = BNXT_ULP_CLASS_HID_117c5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15033699328UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5905853440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13331,23 +28114,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [598] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dde5,
+ [1207] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1478d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15033707520UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5906893824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13355,24 +28138,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [599] = {
- .class_hid = BNXT_ULP_CLASS_HID_25da5,
+ [1208] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1538d,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15034747904UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5906902016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13380,23 +28162,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [600] = {
- .class_hid = BNXT_ULP_CLASS_HID_24f05,
+ [1209] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13a05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15034756096UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5907942400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13404,24 +28187,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [601] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f0c5,
+ [1210] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135cf,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15035796480UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5907950592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13429,24 +28211,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [602] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e245,
+ [1211] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1658f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 15035804672UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5908990976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13454,25 +28236,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [603] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d8b,
+ [1212] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1718f,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17180134400UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 5908999168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13480,20 +28261,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [604] = {
- .class_hid = BNXT_ULP_CLASS_HID_207cf,
+ [1213] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11667,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17180142592UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6442716160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13501,21 +28287,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [605] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b8f,
+ [1214] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10225,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17181182976UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6442724352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13523,21 +28309,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [606] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a517,
+ [1215] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15247,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17181191168UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6443764736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13545,22 +28332,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [607] = {
- .class_hid = BNXT_ULP_CLASS_HID_25277,
+ [1216] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17182231552UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6443772928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13568,21 +28355,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [608] = {
- .class_hid = BNXT_ULP_CLASS_HID_254ab,
+ [1217] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13455,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17182239744UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6444813312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13590,22 +28379,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [609] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d86b,
+ [1218] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12017,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17183280128UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6444821504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13613,22 +28402,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [610] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cbf3,
+ [1219] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17035,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 17183288320UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6445861888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13636,23 +28426,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [611] = {
- .class_hid = BNXT_ULP_CLASS_HID_2554b,
+ [1220] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bf7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19327618048UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6445870080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13660,21 +28450,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [612] = {
- .class_hid = BNXT_ULP_CLASS_HID_22f8f,
+ [1221] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10115,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19327626240UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6979587072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13682,22 +28475,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [613] = {
- .class_hid = BNXT_ULP_CLASS_HID_2934f,
+ [1222] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d15,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19328666624UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6979595264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13705,22 +28498,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [614] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c2c7,
+ [1223] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14d05,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19328674816UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6980635648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13728,23 +28522,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [615] = {
- .class_hid = BNXT_ULP_CLASS_HID_242e3,
+ [1224] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15905,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19329715200UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6980643840UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13752,22 +28546,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [616] = {
- .class_hid = BNXT_ULP_CLASS_HID_27c6b,
+ [1225] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12f17,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19329723392UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6981684224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13775,23 +28571,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [617] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e02b,
+ [1226] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13b17,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19330763776UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6981692416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13799,23 +28595,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [618] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d3a3,
+ [1227] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16ad7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 19330771968UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6982732800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13823,24 +28620,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [619] = {
- .class_hid = BNXT_ULP_CLASS_HID_259a3,
+ [1228] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16695,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21475101696UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 6982740992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13848,21 +28645,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [620] = {
- .class_hid = BNXT_ULP_CLASS_HID_213e7,
+ [1229] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11be5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21475109888UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7516457984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13870,22 +28671,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [621] = {
- .class_hid = BNXT_ULP_CLASS_HID_287a7,
+ [1230] = {
+ .class_hid = BNXT_ULP_CLASS_HID_117a7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21476150272UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7516466176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13893,22 +28694,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [622] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b137,
+ [1231] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14767,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21476158464UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7517506560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13916,23 +28718,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [623] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e17,
+ [1232] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15387,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21477198848UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7517514752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13940,22 +28742,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [624] = {
- .class_hid = BNXT_ULP_CLASS_HID_26043,
+ [1233] = {
+ .class_hid = BNXT_ULP_CLASS_HID_139e7,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21477207040UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7518555136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13963,23 +28767,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [625] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d403,
+ [1234] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135a5,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21478247424UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7518563328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -13987,23 +28791,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [626] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c793,
+ [1235] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16565,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 21478255616UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7519603712UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14011,24 +28816,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [627] = {
- .class_hid = BNXT_ULP_CLASS_HID_20827,
+ [1236] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17185,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23622585344UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 7519611904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14036,22 +28841,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [628] = {
- .class_hid = BNXT_ULP_CLASS_HID_23ba7,
+ [1237] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11687,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23622593536UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8053328896UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14059,23 +28867,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [629] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af67,
+ [1238] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10245,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23623633920UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8053337088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14083,23 +28891,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [630] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dee7,
+ [1239] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15287,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23623642112UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8054377472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14107,24 +28916,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [631] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e83,
+ [1240] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e45,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23624682496UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8054385664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14132,23 +28941,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [632] = {
- .class_hid = BNXT_ULP_CLASS_HID_24803,
+ [1241] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13485,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23624690688UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8055426048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14156,24 +28967,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [633] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fdc3,
+ [1242] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12047,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23625731072UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8055434240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14181,24 +28992,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [634] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ef43,
+ [1243] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17085,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 23625739264UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8056474624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14206,25 +29018,25 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [635] = {
- .class_hid = BNXT_ULP_CLASS_HID_247bf,
+ [1244] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c47,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25770068992UL,
+ .hdr_sig_id = 11,
+ .flow_sig_id = 8056482816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -14232,3007 +29044,3034 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT }
},
- [636] = {
- .class_hid = BNXT_ULP_CLASS_HID_219ff,
+ [1245] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400f4,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25770077184UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 66304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI }
},
- [637] = {
- .class_hid = BNXT_ULP_CLASS_HID_28dbf,
+ [1246] = {
+ .class_hid = BNXT_ULP_CLASS_HID_410c8,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25771117568UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 68352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI }
},
- [638] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf07,
+ [1247] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51084,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25771125760UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 328448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC }
},
- [639] = {
- .class_hid = BNXT_ULP_CLASS_HID_25467,
+ [1248] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ffe,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25772166144UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 330496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC }
},
- [640] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e5f,
+ [1249] = {
+ .class_hid = BNXT_ULP_CLASS_HID_488cc,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25772174336UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 590592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [641] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d21f,
+ [1250] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48726,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25773214720UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 592640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [642] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cde7,
+ [1251] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587f2,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 25773222912UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 852736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [643] = {
- .class_hid = BNXT_ULP_CLASS_HID_26f6f,
+ [1252] = {
+ .class_hid = BNXT_ULP_CLASS_HID_597b6,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27917552640UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 854784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC }
},
- [644] = {
- .class_hid = BNXT_ULP_CLASS_HID_221af,
+ [1253] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b10,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27917560832UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 536937216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [645] = {
- .class_hid = BNXT_ULP_CLASS_HID_2956f,
+ [1254] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b8a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27918601216UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 536939264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [646] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c4c7,
+ [1255] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a46,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27918609408UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537199360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [647] = {
- .class_hid = BNXT_ULP_CLASS_HID_24487,
+ [1256] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a1a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27919649792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537201408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [648] = {
- .class_hid = BNXT_ULP_CLASS_HID_2760f,
+ [1257] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4838e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27919657984UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537461504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [649] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fbcf,
+ [1258] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49242,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27920698368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537463552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [650] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d5a7,
+ [1259] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5921e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 27920706560UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537723648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [651] = {
- .class_hid = BNXT_ULP_CLASS_HID_25357,
+ [1260] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58150,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30065036288UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 537725696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR }
},
- [652] = {
- .class_hid = BNXT_ULP_CLASS_HID_21597,
+ [1261] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41686,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30065044480UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1073808128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [653] = {
- .class_hid = BNXT_ULP_CLASS_HID_29957,
+ [1262] = {
+ .class_hid = BNXT_ULP_CLASS_HID_405e8,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30066084864UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1073810176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [654] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cb27,
+ [1263] = {
+ .class_hid = BNXT_ULP_CLASS_HID_505a4,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30066093056UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074070272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [655] = {
- .class_hid = BNXT_ULP_CLASS_HID_248f7,
+ [1264] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51588,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30067133440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074072320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [656] = {
- .class_hid = BNXT_ULP_CLASS_HID_27a77,
+ [1265] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d4e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30067141632UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074332416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [657] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee37,
+ [1266] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48da0,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30068182016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074334464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [658] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d987,
+ [1267] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8c,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 30068190208UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074594560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [659] = {
- .class_hid = BNXT_ULP_CLASS_HID_203c7,
+ [1268] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59c40,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32212519936UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1074596608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [660] = {
- .class_hid = BNXT_ULP_CLASS_HID_23d47,
+ [1269] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40040,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32212528128UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610679040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [661] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a107,
+ [1270] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41004,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32213568512UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610681088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [662] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d0e7,
+ [1271] = {
+ .class_hid = BNXT_ULP_CLASS_HID_510c0,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32213576704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610941184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [663] = {
- .class_hid = BNXT_ULP_CLASS_HID_250a7,
+ [1272] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f4a,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32214617088UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1610943232UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [664] = {
- .class_hid = BNXT_ULP_CLASS_HID_24227,
+ [1273] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48808,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32214625280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611203328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [665] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f7e7,
+ [1274] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48742,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32215665664UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611205376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [666] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c827,
+ [1275] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5874e,
.class_tid = 2,
- .hdr_sig_id = 4,
- .flow_sig_id = 32215673856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611465472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_TCP |
+ BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT |
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [667] = {
- .class_hid = BNXT_ULP_CLASS_HID_25422,
+ [1276] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59702,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 1611467520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR }
},
- [668] = {
- .class_hid = BNXT_ULP_CLASS_HID_21a66,
+ [1277] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41bfe,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147549952UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [669] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f76a,
+ [1278] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40a58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147552000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [670] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bcae,
+ [1279] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a2c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147812096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [671] = {
- .class_hid = BNXT_ULP_CLASS_HID_245ce,
+ [1280] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51ae8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2147814144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [672] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b02,
+ [1281] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4825c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148074240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [673] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfc2,
+ [1282] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49228,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148076288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [674] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee4a,
+ [1283] = {
+ .class_hid = BNXT_ULP_CLASS_HID_592ec,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148336384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [675] = {
- .class_hid = BNXT_ULP_CLASS_HID_22cbe,
+ [1284] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5815e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 537136128UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2148338432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [676] = {
- .class_hid = BNXT_ULP_CLASS_HID_21232,
+ [1285] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41698,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 537144320UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684420864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [677] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cf26,
+ [1286] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4051a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 538184704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684422912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [678] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b53a,
+ [1287] = {
+ .class_hid = BNXT_ULP_CLASS_HID_505ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 538192896UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684683008UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [679] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d9a,
+ [1288] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5158a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 539233280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684685056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [680] = {
- .class_hid = BNXT_ULP_CLASS_HID_2439e,
+ [1289] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 539241472UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684945152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [681] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d79e,
+ [1290] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48dca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 540281856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2684947200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [682] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e606,
+ [1291] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d8e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 540290048UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2685207296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [683] = {
- .class_hid = BNXT_ULP_CLASS_HID_21c5e,
+ [1292] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59c5a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1074007040UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 2685209344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [684] = {
- .class_hid = BNXT_ULP_CLASS_HID_22ac6,
+ [1293] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4002e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1074015232UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221291776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [685] = {
- .class_hid = BNXT_ULP_CLASS_HID_2be86,
+ [1294] = {
+ .class_hid = BNXT_ULP_CLASS_HID_410ea,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1075055616UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221293824UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [686] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cd0e,
+ [1295] = {
+ .class_hid = BNXT_ULP_CLASS_HID_510ae,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1075063808UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221553920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [687] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d1a,
+ [1296] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f08,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1076104192UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221555968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [688] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b82,
+ [1297] = {
+ .class_hid = BNXT_ULP_CLASS_HID_488ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1076112384UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221816064UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [689] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d042,
+ [1298] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48748,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1077152768UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3221818112UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [690] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d586,
+ [1299] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5870c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1077160960UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3222078208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [691] = {
- .class_hid = BNXT_ULP_CLASS_HID_2140a,
+ [1300] = {
+ .class_hid = BNXT_ULP_CLASS_HID_597e8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1610877952UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3222080256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [692] = {
- .class_hid = BNXT_ULP_CLASS_HID_22292,
+ [1301] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b4a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1610886144UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758162688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [693] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b712,
+ [1302] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b8c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1611926528UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758164736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [694] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c59a,
+ [1303] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50a48,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1611934720UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758424832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [695] = {
- .class_hid = BNXT_ULP_CLASS_HID_24596,
+ [1304] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a0c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1612975104UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758426880UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [696] = {
- .class_hid = BNXT_ULP_CLASS_HID_2541e,
+ [1305] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48388,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1612983296UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758686976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [697] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e81e,
+ [1306] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4924c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1614023680UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758689024UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [698] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f686,
+ [1307] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59208,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 1614031872UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758949120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [699] = {
- .class_hid = BNXT_ULP_CLASS_HID_24cf2,
+ [1308] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5828a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 3758951168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT }
},
- [700] = {
- .class_hid = BNXT_ULP_CLASS_HID_23236,
+ [1309] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40540,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295033600UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [701] = {
- .class_hid = BNXT_ULP_CLASS_HID_286f6,
+ [1310] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41500,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295035648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [702] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d57e,
+ [1311] = {
+ .class_hid = BNXT_ULP_CLASS_HID_515d0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295295744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [703] = {
- .class_hid = BNXT_ULP_CLASS_HID_2555a,
+ [1312] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5044a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295297792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [704] = {
- .class_hid = BNXT_ULP_CLASS_HID_263d2,
+ [1313] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d18,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295557888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [705] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f792,
+ [1314] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dd8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295559936UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [706] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c61a,
+ [1315] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59da8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295820032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [707] = {
- .class_hid = BNXT_ULP_CLASS_HID_244be,
+ [1316] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c02,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2684619776UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4295822080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [708] = {
- .class_hid = BNXT_ULP_CLASS_HID_20ab2,
+ [1317] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41048,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2684627968UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4831904512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [709] = {
- .class_hid = BNXT_ULP_CLASS_HID_29eb2,
+ [1318] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c2,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2685668352UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4831906560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [710] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ad3a,
+ [1319] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50092,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2685676544UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832166656UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [711] = {
- .class_hid = BNXT_ULP_CLASS_HID_2761a,
+ [1320] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51f52,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2686716928UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832168704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [712] = {
- .class_hid = BNXT_ULP_CLASS_HID_27b9e,
+ [1321] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49800,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2686725120UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832428800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [713] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f01e,
+ [1322] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4889a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2687765504UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832430848UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [714] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de96,
+ [1323] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5974a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 2687773696UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832690944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [715] = {
- .class_hid = BNXT_ULP_CLASS_HID_2341e,
+ [1324] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3221490688UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 4832692992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [716] = {
- .class_hid = BNXT_ULP_CLASS_HID_24296,
+ [1325] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40bc2,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3221498880UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5368775424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [717] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d756,
+ [1326] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41b82,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3222539264UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5368777472UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [718] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c9a,
+ [1327] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51a62,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3222547456UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369037568UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [719] = {
- .class_hid = BNXT_ULP_CLASS_HID_265da,
+ [1328] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ac0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3223587840UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369039616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [720] = {
- .class_hid = BNXT_ULP_CLASS_HID_27452,
+ [1329] = {
+ .class_hid = BNXT_ULP_CLASS_HID_493aa,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3223596032UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369299712UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [721] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c812,
+ [1330] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48208,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3224636416UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369301760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [722] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce56,
+ [1331] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3224644608UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369561856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [723] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c9a,
+ [1332] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59288,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3758361600UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5369563904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [724] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b12,
+ [1333] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40688,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3758369792UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905646336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [725] = {
- .class_hid = BNXT_ULP_CLASS_HID_2af12,
+ [1334] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41540,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3759410176UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905648384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [726] = {
- .class_hid = BNXT_ULP_CLASS_HID_29516,
+ [1335] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51508,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3759418368UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905908480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [727] = {
- .class_hid = BNXT_ULP_CLASS_HID_27d96,
+ [1336] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50582,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3760458752UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5905910528UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [728] = {
- .class_hid = BNXT_ULP_CLASS_HID_24c1e,
+ [1337] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d40,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3760466944UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906170624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [729] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c09e,
+ [1338] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49d08,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3761507328UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906172672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [730] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c612,
+ [1339] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59dc0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 3761515520UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906432768UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [731] = {
- .class_hid = BNXT_ULP_CLASS_HID_24002,
+ [1340] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c4a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 5906434816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [732] = {
- .class_hid = BNXT_ULP_CLASS_HID_20646,
+ [1341] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4104a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442517248UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [733] = {
- .class_hid = BNXT_ULP_CLASS_HID_29a06,
+ [1342] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400a8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442519296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [734] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a886,
+ [1343] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50f78,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442779392UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [735] = {
- .class_hid = BNXT_ULP_CLASS_HID_271a6,
+ [1344] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51f38,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6442781440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [736] = {
- .class_hid = BNXT_ULP_CLASS_HID_277e2,
+ [1345] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4980a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443041536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [737] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cba2,
+ [1346] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49768,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443043584UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [738] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da22,
+ [1347] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59738,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443303680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [739] = {
- .class_hid = BNXT_ULP_CLASS_HID_25896,
+ [1348] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587aa,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4832103424UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6443305728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [740] = {
- .class_hid = BNXT_ULP_CLASS_HID_21e12,
+ [1349] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40bd8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4832111616UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979388160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [741] = {
- .class_hid = BNXT_ULP_CLASS_HID_29292,
+ [1350] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41bc8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4833152000UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979390208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [742] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a112,
+ [1351] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51b88,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4833160192UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979650304UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [743] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a32,
+ [1352] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50ada,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4834200576UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979652352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [744] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fb6,
+ [1353] = {
+ .class_hid = BNXT_ULP_CLASS_HID_493c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4834208768UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979912448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [745] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c436,
+ [1354] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4820a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4835249152UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6979914496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [746] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d2a6,
+ [1355] = {
+ .class_hid = BNXT_ULP_CLASS_HID_582da,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 4835257344UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6980174592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [747] = {
- .class_hid = BNXT_ULP_CLASS_HID_20856,
+ [1356] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5929a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5368974336UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 6980176640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [748] = {
- .class_hid = BNXT_ULP_CLASS_HID_256c6,
+ [1357] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4056a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5368982528UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516259072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [749] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aa86,
+ [1358] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4152a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5370022912UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516261120UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
+ },
+ [1359] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5150a,
+ .class_tid = 2,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516521216UL,
+ .flow_pattern_id = 1,
+ .app_sig = 0,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [750] = {
- .class_hid = BNXT_ULP_CLASS_HID_290d2,
+ [1360] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50468,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5370031104UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516523264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [751] = {
- .class_hid = BNXT_ULP_CLASS_HID_279d2,
+ [1361] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48d2a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5371071488UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516783360UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [752] = {
- .class_hid = BNXT_ULP_CLASS_HID_24842,
+ [1362] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49dea,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5371079680UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7516785408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [753] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dc02,
+ [1363] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59dca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5372120064UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7517045504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [754] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c246,
+ [1364] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58c28,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5372128256UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 7517047552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [755] = {
- .class_hid = BNXT_ULP_CLASS_HID_20082,
+ [1365] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4118a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5905845248UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053129984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [756] = {
- .class_hid = BNXT_ULP_CLASS_HID_22e92,
+ [1366] = {
+ .class_hid = BNXT_ULP_CLASS_HID_400c8,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5905853440UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053132032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [757] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a312,
+ [1367] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50088,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5906893824UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053392128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [758] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f192,
+ [1368] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51088,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5906902016UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053394176UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [759] = {
- .class_hid = BNXT_ULP_CLASS_HID_27196,
+ [1369] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4984a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5907942400UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053654272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [760] = {
- .class_hid = BNXT_ULP_CLASS_HID_24016,
+ [1370] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48888,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5907950592UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053656320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [761] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d496,
+ [1371] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58888,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5908990976UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053916416UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [762] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da12,
+ [1372] = {
+ .class_hid = BNXT_ULP_CLASS_HID_587ca,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 5908999168UL,
+ .hdr_sig_id = 12,
+ .flow_sig_id = 8053918464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT }
},
- [763] = {
- .class_hid = BNXT_ULP_CLASS_HID_278d2,
+ [1373] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10690,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 265216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17240,21 +32079,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI }
},
- [764] = {
- .class_hid = BNXT_ULP_CLASS_HID_23e16,
+ [1374] = {
+ .class_hid = BNXT_ULP_CLASS_HID_112b0,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 273408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17262,22 +32099,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI }
},
- [765] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b2d6,
+ [1375] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1428c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 1313792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17285,22 +32120,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC }
},
- [766] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c156,
+ [1376] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15eac,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 1321984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17308,23 +32141,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC }
},
- [767] = {
- .class_hid = BNXT_ULP_CLASS_HID_24132,
+ [1377] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1249e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2362368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17332,22 +32163,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [768] = {
- .class_hid = BNXT_ULP_CLASS_HID_26fb2,
+ [1378] = {
+ .class_hid = BNXT_ULP_CLASS_HID_130be,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2370560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17355,23 +32184,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [769] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e472,
+ [1379] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f7a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 3410944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17379,23 +32206,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [770] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f2f2,
+ [1380] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c9a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 3419136UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17403,24 +32228,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC }
},
- [771] = {
- .class_hid = BNXT_ULP_CLASS_HID_27096,
+ [1381] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1119a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6979587072UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2147748864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17428,22 +32251,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [772] = {
- .class_hid = BNXT_ULP_CLASS_HID_23692,
+ [1382] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10c58,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6979595264UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2147757056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17451,23 +32272,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [773] = {
- .class_hid = BNXT_ULP_CLASS_HID_28a92,
+ [1383] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c7e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6980635648UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2148797440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17475,23 +32294,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [774] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d912,
+ [1384] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1483c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6980643840UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2148805632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17499,24 +32316,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [775] = {
- .class_hid = BNXT_ULP_CLASS_HID_259b6,
+ [1385] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f88,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6981684224UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2149846016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17524,23 +32339,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [776] = {
- .class_hid = BNXT_ULP_CLASS_HID_26836,
+ [1386] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a4e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6981692416UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2149854208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17548,24 +32361,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [777] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fc36,
+ [1387] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17a6c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6982732800UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2150894592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17573,24 +32384,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [778] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cab6,
+ [1388] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1762a,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 6982740992UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 2150902784UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17598,25 +32407,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR }
},
- [779] = {
- .class_hid = BNXT_ULP_CLASS_HID_22016,
+ [1389] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b46,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7516457984UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4295232512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17624,22 +32431,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [780] = {
- .class_hid = BNXT_ULP_CLASS_HID_24e96,
+ [1390] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11704,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7516466176UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4295240704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17647,23 +32452,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [781] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c356,
+ [1391] = {
+ .class_hid = BNXT_ULP_CLASS_HID_147c4,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7517506560UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4296281088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17671,23 +32474,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [782] = {
- .class_hid = BNXT_ULP_CLASS_HID_28892,
+ [1392] = {
+ .class_hid = BNXT_ULP_CLASS_HID_153e4,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7517514752UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4296289280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17695,24 +32496,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [783] = {
- .class_hid = BNXT_ULP_CLASS_HID_25192,
+ [1393] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13934,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7518555136UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4297329664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17720,23 +32519,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [784] = {
- .class_hid = BNXT_ULP_CLASS_HID_257d6,
+ [1394] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135f6,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7518563328UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4297337856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17744,24 +32541,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [785] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f4d2,
+ [1395] = {
+ .class_hid = BNXT_ULP_CLASS_HID_165ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7519603712UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4298378240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17769,24 +32564,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [786] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fa16,
+ [1396] = {
+ .class_hid = BNXT_ULP_CLASS_HID_171ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 7519611904UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 4298386432UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17794,25 +32587,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [787] = {
- .class_hid = BNXT_ULP_CLASS_HID_23892,
+ [1397] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116ee,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8053328896UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6442716160UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17820,23 +32611,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [788] = {
- .class_hid = BNXT_ULP_CLASS_HID_24712,
+ [1398] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102ac,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8053337088UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6442724352UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17844,24 +32633,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [789] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db12,
+ [1399] = {
+ .class_hid = BNXT_ULP_CLASS_HID_152ce,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8054377472UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6443764736UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17869,24 +32656,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [790] = {
- .class_hid = BNXT_ULP_CLASS_HID_28116,
+ [1400] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e8c,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8054385664UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6443772928UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17894,25 +32679,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [791] = {
- .class_hid = BNXT_ULP_CLASS_HID_26a16,
+ [1401] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134dc,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8055426048UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6444813312UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17920,24 +32703,22 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [792] = {
- .class_hid = BNXT_ULP_CLASS_HID_27896,
+ [1402] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1209e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8055434240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6444821504UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17945,25 +32726,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [793] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc96,
+ [1403] = {
+ .class_hid = BNXT_ULP_CLASS_HID_170bc,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8056474624UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6445861888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17971,25 +32750,23 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [794] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f292,
+ [1404] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16b7e,
.class_tid = 2,
- .hdr_sig_id = 5,
- .flow_sig_id = 8056482816UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 6445870080UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -17997,26 +32774,24 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV6 |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR }
},
- [795] = {
- .class_hid = BNXT_ULP_CLASS_HID_24b05,
+ [1405] = {
+ .class_hid = BNXT_ULP_CLASS_HID_119ae,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 265216UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8590199808UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18028,15 +32803,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [796] = {
- .class_hid = BNXT_ULP_CLASS_HID_20541,
+ [1406] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1146a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 273408UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8590208000UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18048,16 +32824,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [797] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e84d,
+ [1407] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14426,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 1313792UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8591248384UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18069,16 +32846,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [798] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a389,
+ [1408] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15046,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 1321984UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8591256576UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18090,17 +32868,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [799] = {
- .class_hid = BNXT_ULP_CLASS_HID_25ae9,
+ [1409] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1263a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2362368UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8592296960UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18112,16 +32891,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [800] = {
- .class_hid = BNXT_ULP_CLASS_HID_25425,
+ [1410] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1325a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2370560UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8592305152UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18133,17 +32913,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [801] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c0e5,
+ [1411] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16216,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 3410944UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8593345536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18155,17 +32936,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [802] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f16d,
+ [1412] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17e36,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 3419136UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 8593353728UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18177,18 +32959,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [803] = {
- .class_hid = BNXT_ULP_CLASS_HID_253d5,
+ [1413] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1133e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2147748864UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10737683456UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18200,16 +32983,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [804] = {
- .class_hid = BNXT_ULP_CLASS_HID_22d11,
+ [1414] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10ffa,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2147757056UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10737691648UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18221,17 +33005,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [805] = {
- .class_hid = BNXT_ULP_CLASS_HID_299d1,
+ [1415] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f1a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2148797440UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10738732032UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18243,17 +33028,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [806] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ca59,
+ [1416] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14bee,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2148805632UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10738740224UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18265,18 +33051,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [807] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a7d,
+ [1417] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1312a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2149846016UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10739780608UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18288,17 +33075,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [808] = {
- .class_hid = BNXT_ULP_CLASS_HID_27cf5,
+ [1418] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12dea,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2149854208UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10739788800UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18310,18 +33098,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [809] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e8b5,
+ [1419] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17d1e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2150894592UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10740829184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18333,18 +33122,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [810] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d93d,
+ [1420] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169de,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 2150902784UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 10740837376UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18356,19 +33146,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [811] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f25,
+ [1421] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11ee6,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4295232512UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12885167104UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18380,16 +33171,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [812] = {
- .class_hid = BNXT_ULP_CLASS_HID_21961,
+ [1422] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10abe,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4295240704UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12885175296UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18401,17 +33193,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [813] = {
- .class_hid = BNXT_ULP_CLASS_HID_28521,
+ [1423] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15ade,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4296281088UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12886215680UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18423,17 +33216,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [814] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b7a1,
+ [1424] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1569e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4296289280UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12886223872UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18445,18 +33239,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [815] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e81,
+ [1425] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13cee,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4297329664UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12887264256UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18468,17 +33263,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [816] = {
- .class_hid = BNXT_ULP_CLASS_HID_268c5,
+ [1426] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128ae,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4297337856UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12887272448UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18490,18 +33286,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [817] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d485,
+ [1427] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1676e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4298378240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12888312832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18513,18 +33310,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [818] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c505,
+ [1428] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1748e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 4298386432UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 12888321024UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18536,19 +33334,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [819] = {
- .class_hid = BNXT_ULP_CLASS_HID_267f5,
+ [1429] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1098e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6442716160UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15032650752UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18560,17 +33359,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [820] = {
- .class_hid = BNXT_ULP_CLASS_HID_22131,
+ [1430] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1044e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6442724352UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15032658944UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18582,18 +33382,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [821] = {
- .class_hid = BNXT_ULP_CLASS_HID_2adf1,
+ [1431] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1546e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6443764736UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15033699328UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18605,18 +33406,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [822] = {
- .class_hid = BNXT_ULP_CLASS_HID_2de71,
+ [1432] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1402e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6443772928UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15033707520UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18628,19 +33430,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [823] = {
- .class_hid = BNXT_ULP_CLASS_HID_25e15,
+ [1433] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1367e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6444813312UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15034747904UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18652,18 +33455,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [824] = {
- .class_hid = BNXT_ULP_CLASS_HID_27095,
+ [1434] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1223e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6444821504UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15034756096UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18675,19 +33479,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [825] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fb55,
+ [1435] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1725e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6445861888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15035796480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18699,19 +33504,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [826] = {
- .class_hid = BNXT_ULP_CLASS_HID_2edd5,
+ [1436] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e1e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 6445870080UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 15035804672UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18723,20 +33529,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT }
},
- [827] = {
- .class_hid = BNXT_ULP_CLASS_HID_24511,
+ [1437] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1172f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8590199808UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17180134400UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18748,16 +33555,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [828] = {
- .class_hid = BNXT_ULP_CLASS_HID_21f51,
+ [1438] = {
+ .class_hid = BNXT_ULP_CLASS_HID_103ed,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8590208000UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17180142592UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18769,17 +33576,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [829] = {
- .class_hid = BNXT_ULP_CLASS_HID_28b11,
+ [1439] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1530b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8591248384UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17181182976UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18791,17 +33598,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [830] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bd99,
+ [1440] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14fc9,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8591256576UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17181191168UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18813,18 +33620,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [831] = {
- .class_hid = BNXT_ULP_CLASS_HID_254f9,
+ [1441] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1351d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8592296960UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17182231552UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18836,17 +33643,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [832] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e31,
+ [1442] = {
+ .class_hid = BNXT_ULP_CLASS_HID_121db,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8592305152UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17182239744UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18858,18 +33665,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [833] = {
- .class_hid = BNXT_ULP_CLASS_HID_2daf1,
+ [1443] = {
+ .class_hid = BNXT_ULP_CLASS_HID_171f9,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8593345536UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17183280128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18881,18 +33688,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [834] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cb79,
+ [1444] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16db7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 8593353728UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 17183288320UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18904,19 +33711,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [835] = {
- .class_hid = BNXT_ULP_CLASS_HID_26dd1,
+ [1445] = {
+ .class_hid = BNXT_ULP_CLASS_HID_102bf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10737683456UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19327618048UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18928,17 +33735,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [836] = {
- .class_hid = BNXT_ULP_CLASS_HID_22711,
+ [1446] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11edf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10737691648UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19327626240UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18950,18 +33757,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [837] = {
- .class_hid = BNXT_ULP_CLASS_HID_293d1,
+ [1447] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e9b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10738732032UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19328666624UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18973,18 +33780,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [838] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c459,
+ [1448] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15abb,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10738740224UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19328674816UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -18996,19 +33803,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [839] = {
- .class_hid = BNXT_ULP_CLASS_HID_24419,
+ [1449] = {
+ .class_hid = BNXT_ULP_CLASS_HID_120ad,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10739780608UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19329715200UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19020,18 +33827,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [840] = {
- .class_hid = BNXT_ULP_CLASS_HID_276f1,
+ [1450] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13ccd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10739788800UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19329723392UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19043,19 +33850,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [841] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e2b1,
+ [1451] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16c89,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10740829184UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19330763776UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19067,19 +33874,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [842] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d339,
+ [1452] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1675f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 10740837376UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 19330771968UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19091,20 +33898,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [843] = {
- .class_hid = BNXT_ULP_CLASS_HID_25931,
+ [1453] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10c67,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12885167104UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21475101696UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19116,17 +33923,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [844] = {
- .class_hid = BNXT_ULP_CLASS_HID_21371,
+ [1454] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11987,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12885175296UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21475109888UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19138,18 +33945,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [845] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f31,
+ [1455] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1485f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12886215680UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21476150272UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19161,18 +33968,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [846] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b1b1,
+ [1456] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1441d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12886223872UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21476158464UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19184,19 +33991,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [847] = {
- .class_hid = BNXT_ULP_CLASS_HID_26891,
+ [1457] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12a55,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12887264256UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21477198848UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19208,18 +34015,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [848] = {
- .class_hid = BNXT_ULP_CLASS_HID_262d1,
+ [1458] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1262f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12887272448UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21477207040UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19231,19 +34038,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [849] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ee91,
+ [1459] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1764d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12888312832UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21478247424UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19255,19 +34062,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [850] = {
- .class_hid = BNXT_ULP_CLASS_HID_2df11,
+ [1460] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1620f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 12888321024UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 21478255616UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19279,20 +34086,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [851] = {
- .class_hid = BNXT_ULP_CLASS_HID_20951,
+ [1461] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1070f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15032650752UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23622585344UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19304,18 +34111,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [852] = {
- .class_hid = BNXT_ULP_CLASS_HID_23b31,
+ [1462] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1132f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15032658944UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23622593536UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19327,19 +34134,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [853] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a7f1,
+ [1463] = {
+ .class_hid = BNXT_ULP_CLASS_HID_143ef,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15033699328UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23623633920UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19351,19 +34158,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [854] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d871,
+ [1464] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15033707520UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23623642112UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19375,20 +34182,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [855] = {
- .class_hid = BNXT_ULP_CLASS_HID_25831,
+ [1465] = {
+ .class_hid = BNXT_ULP_CLASS_HID_125fd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15034747904UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23624682496UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19400,19 +34207,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [856] = {
- .class_hid = BNXT_ULP_CLASS_HID_24a91,
+ [1466] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1311d,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15034756096UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23624690688UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19424,20 +34231,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [857] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f551,
+ [1467] = {
+ .class_hid = BNXT_ULP_CLASS_HID_161dd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15035796480UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23625731072UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19449,20 +34256,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [858] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e7d1,
+ [1468] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17dfd,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 15035804672UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 23625739264UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19474,21 +34281,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [859] = {
- .class_hid = BNXT_ULP_CLASS_HID_2481f,
+ [1469] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10acb,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17180134400UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25770068992UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19500,16 +34307,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [860] = {
- .class_hid = BNXT_ULP_CLASS_HID_2025b,
+ [1470] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10687,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17180142592UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25770077184UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19521,17 +34329,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [861] = {
- .class_hid = BNXT_ULP_CLASS_HID_28e1b,
+ [1471] = {
+ .class_hid = BNXT_ULP_CLASS_HID_156a7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17181182976UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25771117568UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19543,17 +34352,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [862] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a083,
+ [1472] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14163,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17181191168UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25771125760UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19565,18 +34375,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [863] = {
- .class_hid = BNXT_ULP_CLASS_HID_257e3,
+ [1473] = {
+ .class_hid = BNXT_ULP_CLASS_HID_128b7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17182231552UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25772166144UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19588,17 +34399,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [864] = {
- .class_hid = BNXT_ULP_CLASS_HID_2513f,
+ [1474] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12377,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17182239744UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25772174336UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19610,18 +34422,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [865] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ddff,
+ [1475] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17493,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17183280128UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25773214720UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19633,18 +34446,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [866] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce67,
+ [1476] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16f53,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 17183288320UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 25773222912UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19656,19 +34470,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [867] = {
- .class_hid = BNXT_ULP_CLASS_HID_250df,
+ [1477] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1045b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19327618048UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27917552640UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19680,17 +34495,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [868] = {
- .class_hid = BNXT_ULP_CLASS_HID_22a1b,
+ [1478] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1107b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19327626240UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27917560832UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19702,18 +34518,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [869] = {
- .class_hid = BNXT_ULP_CLASS_HID_296db,
+ [1479] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1404f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19328666624UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27918601216UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19725,18 +34542,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [870] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c753,
+ [1480] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15c6f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19328674816UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27918609408UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19748,19 +34566,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [871] = {
- .class_hid = BNXT_ULP_CLASS_HID_24777,
+ [1481] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1225f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19329715200UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27919649792UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19772,18 +34591,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [872] = {
- .class_hid = BNXT_ULP_CLASS_HID_279ff,
+ [1482] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13e7f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19329723392UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27919657984UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19795,19 +34615,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [873] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e5bf,
+ [1483] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16e3b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19330763776UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27920698368UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19819,19 +34640,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [874] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d637,
+ [1484] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17a5b,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 19330771968UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 27920706560UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19843,20 +34665,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [875] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c37,
+ [1485] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10f1f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21475101696UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30065036288UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19868,17 +34691,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [876] = {
- .class_hid = BNXT_ULP_CLASS_HID_21673,
+ [1486] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11b3f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21475109888UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30065044480UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19890,18 +34714,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [877] = {
- .class_hid = BNXT_ULP_CLASS_HID_28233,
+ [1487] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14bff,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21476150272UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30066084864UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19913,18 +34738,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [878] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b4a3,
+ [1488] = {
+ .class_hid = BNXT_ULP_CLASS_HID_147b7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21476158464UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30066093056UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19936,19 +34762,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [879] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b83,
+ [1489] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12d0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21477198848UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30067133440UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19960,18 +34787,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [880] = {
- .class_hid = BNXT_ULP_CLASS_HID_265d7,
+ [1490] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1392f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21477207040UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30067141632UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -19983,19 +34811,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [881] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d197,
+ [1491] = {
+ .class_hid = BNXT_ULP_CLASS_HID_169e7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21478247424UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30068182016UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20007,19 +34836,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [882] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c207,
+ [1492] = {
+ .class_hid = BNXT_ULP_CLASS_HID_165a7,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 21478255616UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 30068190208UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20031,20 +34861,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [883] = {
- .class_hid = BNXT_ULP_CLASS_HID_20db3,
+ [1493] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11a0f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23622585344UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32212519936UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20056,18 +34887,19 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [884] = {
- .class_hid = BNXT_ULP_CLASS_HID_23e33,
+ [1494] = {
+ .class_hid = BNXT_ULP_CLASS_HID_116cf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23622593536UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32212528128UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20079,19 +34911,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [885] = {
- .class_hid = BNXT_ULP_CLASS_HID_2aaf3,
+ [1495] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1468f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23623633920UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32213568512UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20103,19 +34936,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [886] = {
- .class_hid = BNXT_ULP_CLASS_HID_2db73,
+ [1496] = {
+ .class_hid = BNXT_ULP_CLASS_HID_152af,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23623642112UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32213576704UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20127,20 +34961,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [887] = {
- .class_hid = BNXT_ULP_CLASS_HID_25b17,
+ [1497] = {
+ .class_hid = BNXT_ULP_CLASS_HID_138ff,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23624682496UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32214617088UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20152,19 +34987,20 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [888] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d97,
+ [1498] = {
+ .class_hid = BNXT_ULP_CLASS_HID_134bf,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23624690688UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32214625280UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20176,20 +35012,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [889] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f857,
+ [1499] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1648f,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23625731072UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32215665664UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20201,20 +35038,21 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [890] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ead7,
+ [1500] = {
+ .class_hid = BNXT_ULP_CLASS_HID_170af,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 23625739264UL,
+ .hdr_sig_id = 13,
+ .flow_sig_id = 32215673856UL,
.flow_pattern_id = 1,
.app_sig = 0,
.hdr_sig = { .bits =
@@ -20226,804 +35064,741 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT }
},
- [891] = {
- .class_hid = BNXT_ULP_CLASS_HID_2422b,
+ [1501] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c38,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25770068992UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 66304UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI }
},
- [892] = {
- .class_hid = BNXT_ULP_CLASS_HID_21c6b,
+ [1502] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41c04,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25770077184UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 68352UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI }
},
- [893] = {
- .class_hid = BNXT_ULP_CLASS_HID_2882b,
+ [1503] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51c48,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25771117568UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 328448UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC }
},
- [894] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba93,
+ [1504] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50332,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25771125760UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 330496UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC }
},
- [895] = {
- .class_hid = BNXT_ULP_CLASS_HID_251f3,
+ [1505] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48400,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25772166144UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 590592UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [896] = {
- .class_hid = BNXT_ULP_CLASS_HID_26bcb,
+ [1506] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48bea,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25772174336UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 592640UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [897] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d78b,
+ [1507] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b3e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25773214720UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 852736UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [898] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c873,
+ [1508] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59b7a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 25773222912UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 854784UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC }
},
- [899] = {
- .class_hid = BNXT_ULP_CLASS_HID_26afb,
+ [1509] = {
+ .class_hid = BNXT_ULP_CLASS_HID_417dc,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27917552640UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 536937216UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [900] = {
- .class_hid = BNXT_ULP_CLASS_HID_2243b,
+ [1510] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40746,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27917560832UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 536939264UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [901] = {
- .class_hid = BNXT_ULP_CLASS_HID_290fb,
+ [1511] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5068a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27918601216UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537199360UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [902] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c153,
+ [1512] = {
+ .class_hid = BNXT_ULP_CLASS_HID_516d6,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27918609408UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537201408UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [903] = {
- .class_hid = BNXT_ULP_CLASS_HID_24113,
+ [1513] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48f42,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27919649792UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537461504UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [904] = {
- .class_hid = BNXT_ULP_CLASS_HID_2739b,
- .class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27919657984UL,
- .flow_pattern_id = 1,
+ [1514] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49e8e,
+ .class_tid = 2,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537463552UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [905] = {
- .class_hid = BNXT_ULP_CLASS_HID_2fe5b,
+ [1515] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59ed2,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27920698368UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537723648UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [906] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d033,
+ [1516] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58d9c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 27920706560UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 537725696UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR }
},
- [907] = {
- .class_hid = BNXT_ULP_CLASS_HID_256c3,
+ [1517] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41a4a,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30065036288UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1073808128UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [908] = {
- .class_hid = BNXT_ULP_CLASS_HID_21003,
+ [1518] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40924,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30065044480UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1073810176UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [909] = {
- .class_hid = BNXT_ULP_CLASS_HID_29cc3,
+ [1519] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50968,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30066084864UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074070272UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [910] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ceb3,
+ [1520] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51944,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30066093056UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074072320UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [911] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d63,
+ [1521] = {
+ .class_hid = BNXT_ULP_CLASS_HID_49182,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30067133440UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074332416UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [912] = {
- .class_hid = BNXT_ULP_CLASS_HID_27fe3,
+ [1522] = {
+ .class_hid = BNXT_ULP_CLASS_HID_4816c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30067141632UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074334464UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [913] = {
- .class_hid = BNXT_ULP_CLASS_HID_2eba3,
+ [1523] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58140,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30068182016UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074594560UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [914] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dc13,
+ [1524] = {
+ .class_hid = BNXT_ULP_CLASS_HID_5908c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 30068190208UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1074596608UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [915] = {
- .class_hid = BNXT_ULP_CLASS_HID_20653,
+ [1525] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40c8c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32212519936UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610679040UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [916] = {
- .class_hid = BNXT_ULP_CLASS_HID_238d3,
+ [1526] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41cc8,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32212528128UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610681088UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [917] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a493,
+ [1527] = {
+ .class_hid = BNXT_ULP_CLASS_HID_51c0c,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32213568512UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610941184UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [918] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d573,
+ [1528] = {
+ .class_hid = BNXT_ULP_CLASS_HID_50386,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32213576704UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1610943232UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [919] = {
- .class_hid = BNXT_ULP_CLASS_HID_25533,
+ [1529] = {
+ .class_hid = BNXT_ULP_CLASS_HID_484c4,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32214617088UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611203328UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [920] = {
- .class_hid = BNXT_ULP_CLASS_HID_247b3,
+ [1530] = {
+ .class_hid = BNXT_ULP_CLASS_HID_48b8e,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32214625280UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611205376UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [921] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f273,
+ [1531] = {
+ .class_hid = BNXT_ULP_CLASS_HID_58b82,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32215665664UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611465472UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [922] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cdb3,
+ [1532] = {
+ .class_hid = BNXT_ULP_CLASS_HID_59bce,
.class_tid = 2,
- .hdr_sig_id = 6,
- .flow_sig_id = 32215673856UL,
- .flow_pattern_id = 1,
+ .hdr_sig_id = 14,
+ .flow_sig_id = 1611467520UL,
+ .flow_pattern_id = 2,
.app_sig = 0,
.hdr_sig = { .bits =
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_HDR_BIT_I_ETH |
BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT }
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR }
},
- [923] = {
- .class_hid = BNXT_ULP_CLASS_HID_25c7d,
+ [1533] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10a54,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 265216UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21036,14 +35811,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI }
},
- [924] = {
- .class_hid = BNXT_ULP_CLASS_HID_21239,
+ [1534] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11e74,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 273408UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21056,15 +35831,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI }
},
- [925] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ff35,
+ [1535] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14e48,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 1313792UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21077,15 +35852,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC }
},
- [926] = {
- .class_hid = BNXT_ULP_CLASS_HID_2b4f1,
+ [1536] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15268,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 1321984UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21098,16 +35873,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC }
},
- [927] = {
- .class_hid = BNXT_ULP_CLASS_HID_24d91,
+ [1537] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1285a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2362368UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21120,15 +35895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [928] = {
- .class_hid = BNXT_ULP_CLASS_HID_2435d,
+ [1538] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13c7a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2370560UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21141,16 +35916,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [929] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d79d,
+ [1539] = {
+ .class_hid = BNXT_ULP_CLASS_HID_163be,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 3410944UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21163,16 +35938,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [930] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e615,
+ [1540] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1705e,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 3419136UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21185,17 +35960,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC }
},
- [931] = {
- .class_hid = BNXT_ULP_CLASS_HID_244ad,
+ [1541] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11d5e,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2147748864UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21208,15 +35983,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [932] = {
- .class_hid = BNXT_ULP_CLASS_HID_23a69,
+ [1542] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1009c,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2147757056UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21229,16 +36004,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [933] = {
- .class_hid = BNXT_ULP_CLASS_HID_28ea9,
+ [1543] = {
+ .class_hid = BNXT_ULP_CLASS_HID_150ba,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2148797440UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21251,16 +36026,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [934] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dd21,
+ [1544] = {
+ .class_hid = BNXT_ULP_CLASS_HID_144f8,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2148805632UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21273,17 +36048,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [935] = {
- .class_hid = BNXT_ULP_CLASS_HID_25d05,
+ [1545] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1334c,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2149846016UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21296,16 +36071,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [936] = {
- .class_hid = BNXT_ULP_CLASS_HID_26b8d,
+ [1546] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1268a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2149854208UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21318,17 +36093,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [937] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ffcd,
+ [1547] = {
+ .class_hid = BNXT_ULP_CLASS_HID_176a8,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2150894592UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21341,17 +36116,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [938] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ce45,
+ [1548] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17aee,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 2150902784UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21364,18 +36139,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR }
},
- [939] = {
- .class_hid = BNXT_ULP_CLASS_HID_2485d,
+ [1549] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11782,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4295232512UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21388,15 +36163,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [940] = {
- .class_hid = BNXT_ULP_CLASS_HID_20e19,
+ [1550] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11bc0,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4295240704UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21409,16 +36184,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [941] = {
- .class_hid = BNXT_ULP_CLASS_HID_29259,
+ [1551] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14b00,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4296281088UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21431,16 +36206,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [942] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a0d9,
+ [1552] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15f20,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4296289280UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21453,17 +36228,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [943] = {
- .class_hid = BNXT_ULP_CLASS_HID_279f9,
+ [1553] = {
+ .class_hid = BNXT_ULP_CLASS_HID_135f0,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4297329664UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21476,16 +36251,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [944] = {
- .class_hid = BNXT_ULP_CLASS_HID_27fbd,
+ [1554] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13932,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4297337856UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21498,17 +36273,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [945] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c3fd,
+ [1555] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1690a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4298378240UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21521,17 +36296,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [946] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d27d,
+ [1556] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17d2a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 4298386432UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21544,18 +36319,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [947] = {
- .class_hid = BNXT_ULP_CLASS_HID_2708d,
+ [1557] = {
+ .class_hid = BNXT_ULP_CLASS_HID_11a2a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6442716160UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21568,16 +36343,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [948] = {
- .class_hid = BNXT_ULP_CLASS_HID_23649,
+ [1558] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10e68,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6442724352UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21590,17 +36365,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [949] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ba89,
+ [1559] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e0a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6443764736UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21613,17 +36388,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [950] = {
- .class_hid = BNXT_ULP_CLASS_HID_2c909,
+ [1560] = {
+ .class_hid = BNXT_ULP_CLASS_HID_14248,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6443772928UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21636,18 +36411,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [951] = {
- .class_hid = BNXT_ULP_CLASS_HID_2496d,
+ [1561] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13818,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6444813312UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21660,17 +36435,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [952] = {
- .class_hid = BNXT_ULP_CLASS_HID_267ed,
+ [1562] = {
+ .class_hid = BNXT_ULP_CLASS_HID_12c5a,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6444821504UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21683,18 +36458,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [953] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ec2d,
+ [1563] = {
+ .class_hid = BNXT_ULP_CLASS_HID_17c78,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6445861888UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21707,18 +36482,18 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [954] = {
- .class_hid = BNXT_ULP_CLASS_HID_2faad,
+ [1564] = {
+ .class_hid = BNXT_ULP_CLASS_HID_167ba,
.class_tid = 2,
- .hdr_sig_id = 7,
+ .hdr_sig_id = 15,
.flow_sig_id = 6445870080UL,
.flow_pattern_id = 2,
.app_sig = 0,
@@ -21731,17 +36506,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_I_ICMP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF_0_2_7_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR }
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR }
},
- [955] = {
- .class_hid = BNXT_ULP_CLASS_HID_34c6,
+ [1565] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f91,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -21755,8 +36530,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [956] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c22,
+ [1566] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0763,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4100UL,
@@ -21771,8 +36546,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [957] = {
- .class_hid = BNXT_ULP_CLASS_HID_1cbe,
+ [1567] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f7b,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -21787,8 +36562,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [958] = {
- .class_hid = BNXT_ULP_CLASS_HID_179a,
+ [1568] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16af,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6148UL,
@@ -21804,8 +36579,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [959] = {
- .class_hid = BNXT_ULP_CLASS_HID_59be,
+ [1569] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1daf,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -21819,8 +36594,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [960] = {
- .class_hid = BNXT_ULP_CLASS_HID_515a,
+ [1570] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0539,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16388UL,
@@ -21835,8 +36610,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [961] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c72,
+ [1571] = {
+ .class_hid = BNXT_ULP_CLASS_HID_01ed,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -21851,8 +36626,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [962] = {
- .class_hid = BNXT_ULP_CLASS_HID_171e,
+ [1572] = {
+ .class_hid = BNXT_ULP_CLASS_HID_097f,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24580UL,
@@ -21868,8 +36643,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [963] = {
- .class_hid = BNXT_ULP_CLASS_HID_19c8,
+ [1573] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81ab8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -21884,8 +36659,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [964] = {
- .class_hid = BNXT_ULP_CLASS_HID_112c,
+ [1574] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8020e,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32772UL,
@@ -21901,8 +36676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [965] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d68,
+ [1575] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815d8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -21918,8 +36693,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [966] = {
- .class_hid = BNXT_ULP_CLASS_HID_444c,
+ [1576] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cae,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32836UL,
@@ -21936,8 +36711,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [967] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e8c,
+ [1577] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810a8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -21953,8 +36728,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [968] = {
- .class_hid = BNXT_ULP_CLASS_HID_09e0,
+ [1578] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8183e,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49156UL,
@@ -21971,8 +36746,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [969] = {
- .class_hid = BNXT_ULP_CLASS_HID_1af0,
+ [1579] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8036a,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -21989,8 +36764,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [970] = {
- .class_hid = BNXT_ULP_CLASS_HID_15d4,
+ [1580] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80af8,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49220UL,
@@ -22008,8 +36783,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [971] = {
- .class_hid = BNXT_ULP_CLASS_HID_1dd0,
+ [1581] = {
+ .class_hid = BNXT_ULP_CLASS_HID_206fe,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -22024,8 +36799,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [972] = {
- .class_hid = BNXT_ULP_CLASS_HID_14f4,
+ [1582] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e4c,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131076UL,
@@ -22041,8 +36816,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [973] = {
- .class_hid = BNXT_ULP_CLASS_HID_70b0,
+ [1583] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2111e,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -22058,8 +36833,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [974] = {
- .class_hid = BNXT_ULP_CLASS_HID_4854,
+ [1584] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218ec,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131140UL,
@@ -22076,8 +36851,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [975] = {
- .class_hid = BNXT_ULP_CLASS_HID_3dd4,
+ [1585] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60472,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -22093,8 +36868,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [976] = {
- .class_hid = BNXT_ULP_CLASS_HID_34f8,
+ [1586] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603c0,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196612UL,
@@ -22111,8 +36886,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [977] = {
- .class_hid = BNXT_ULP_CLASS_HID_09e8,
+ [1587] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61692,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -22129,8 +36904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [978] = {
- .class_hid = BNXT_ULP_CLASS_HID_008c,
+ [1588] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e60,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196676UL,
@@ -22148,8 +36923,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [979] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e6,
+ [1589] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1f81,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -22164,8 +36939,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [980] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c02,
+ [1590] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0773,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4100UL,
@@ -22181,8 +36956,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [981] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c9e,
+ [1591] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f6b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -22198,8 +36973,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [982] = {
- .class_hid = BNXT_ULP_CLASS_HID_17ba,
+ [1592] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16bf,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6148UL,
@@ -22216,8 +36991,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [983] = {
- .class_hid = BNXT_ULP_CLASS_HID_429e,
+ [1593] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03cf,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -22233,8 +37008,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [984] = {
- .class_hid = BNXT_ULP_CLASS_HID_5dba,
+ [1594] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ab1,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12292UL,
@@ -22251,8 +37026,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [985] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a16,
+ [1595] = {
+ .class_hid = BNXT_ULP_CLASS_HID_130b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -22269,8 +37044,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [986] = {
- .class_hid = BNXT_ULP_CLASS_HID_2532,
+ [1596] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1afd,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14340UL,
@@ -22288,8 +37063,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [987] = {
- .class_hid = BNXT_ULP_CLASS_HID_2da2,
+ [1597] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1591,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -22305,8 +37080,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [988] = {
- .class_hid = BNXT_ULP_CLASS_HID_24fe,
+ [1598] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d03,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20484UL,
@@ -22323,8 +37098,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [989] = {
- .class_hid = BNXT_ULP_CLASS_HID_355a,
+ [1599] = {
+ .class_hid = BNXT_ULP_CLASS_HID_057b,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -22341,8 +37116,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [990] = {
- .class_hid = BNXT_ULP_CLASS_HID_0c76,
+ [1600] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ced,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22532UL,
@@ -22360,8 +37135,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [991] = {
- .class_hid = BNXT_ULP_CLASS_HID_13e6,
+ [1601] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19df,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -22378,8 +37153,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [992] = {
- .class_hid = BNXT_ULP_CLASS_HID_7276,
+ [1602] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0141,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28676UL,
@@ -22397,8 +37172,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [993] = {
- .class_hid = BNXT_ULP_CLASS_HID_42d2,
+ [1603] = {
+ .class_hid = BNXT_ULP_CLASS_HID_08b9,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -22416,8 +37191,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [994] = {
- .class_hid = BNXT_ULP_CLASS_HID_5dee,
+ [1604] = {
+ .class_hid = BNXT_ULP_CLASS_HID_108d,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30724UL,
@@ -22436,8 +37211,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [995] = {
- .class_hid = BNXT_ULP_CLASS_HID_59de,
+ [1605] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dbf,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -22452,8 +37227,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [996] = {
- .class_hid = BNXT_ULP_CLASS_HID_513a,
+ [1606] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0529,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16388UL,
@@ -22469,8 +37244,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [997] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c12,
+ [1607] = {
+ .class_hid = BNXT_ULP_CLASS_HID_01fd,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -22486,8 +37261,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [998] = {
- .class_hid = BNXT_ULP_CLASS_HID_177e,
+ [1608] = {
+ .class_hid = BNXT_ULP_CLASS_HID_096f,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24580UL,
@@ -22504,8 +37279,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [999] = {
- .class_hid = BNXT_ULP_CLASS_HID_0e92,
+ [1609] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810b7,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -22521,8 +37296,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1000] = {
- .class_hid = BNXT_ULP_CLASS_HID_09fe,
+ [1610] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81821,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49156UL,
@@ -22539,8 +37314,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1001] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c1a,
+ [1611] = {
+ .class_hid = BNXT_ULP_CLASS_HID_804f5,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -22557,8 +37332,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1002] = {
- .class_hid = BNXT_ULP_CLASS_HID_5746,
+ [1612] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80c67,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57348UL,
@@ -22576,8 +37351,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1003] = {
- .class_hid = BNXT_ULP_CLASS_HID_79da,
+ [1613] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41333,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -22593,8 +37368,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1004] = {
- .class_hid = BNXT_ULP_CLASS_HID_7106,
+ [1614] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41aad,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81924UL,
@@ -22611,8 +37386,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1005] = {
- .class_hid = BNXT_ULP_CLASS_HID_3c1e,
+ [1615] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40771,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -22629,8 +37404,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1006] = {
- .class_hid = BNXT_ULP_CLASS_HID_377a,
+ [1616] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40ee3,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90116UL,
@@ -22648,8 +37423,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1007] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e9e,
+ [1617] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16cb,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -22666,8 +37441,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1008] = {
- .class_hid = BNXT_ULP_CLASS_HID_29fa,
+ [1618] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1da5,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114692UL,
@@ -22685,8 +37460,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1009] = {
- .class_hid = BNXT_ULP_CLASS_HID_14d2,
+ [1619] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1a09,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -22704,8 +37479,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1010] = {
- .class_hid = BNXT_ULP_CLASS_HID_7742,
+ [1620] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c01fb,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122884UL,
@@ -22724,8 +37499,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1011] = {
- .class_hid = BNXT_ULP_CLASS_HID_3706,
+ [1621] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1ff1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -22740,8 +37515,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1012] = {
- .class_hid = BNXT_ULP_CLASS_HID_0fe2,
+ [1622] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0703,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4100UL,
@@ -22757,8 +37532,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1013] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f7e,
+ [1623] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f1b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -22774,8 +37549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1014] = {
- .class_hid = BNXT_ULP_CLASS_HID_145a,
+ [1624] = {
+ .class_hid = BNXT_ULP_CLASS_HID_16cf,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6148UL,
@@ -22792,8 +37567,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1015] = {
- .class_hid = BNXT_ULP_CLASS_HID_417e,
+ [1625] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03bf,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -22809,8 +37584,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1016] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e5a,
+ [1626] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0ac1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12292UL,
@@ -22827,8 +37602,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1017] = {
- .class_hid = BNXT_ULP_CLASS_HID_29f6,
+ [1627] = {
+ .class_hid = BNXT_ULP_CLASS_HID_137b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -22845,8 +37620,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1018] = {
- .class_hid = BNXT_ULP_CLASS_HID_26d2,
+ [1628] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1a8d,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14340UL,
@@ -22864,8 +37639,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1019] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e42,
+ [1629] = {
+ .class_hid = BNXT_ULP_CLASS_HID_15e1,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -22881,8 +37656,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1020] = {
- .class_hid = BNXT_ULP_CLASS_HID_271e,
+ [1630] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d73,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20484UL,
@@ -22899,8 +37674,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1021] = {
- .class_hid = BNXT_ULP_CLASS_HID_36ba,
+ [1631] = {
+ .class_hid = BNXT_ULP_CLASS_HID_050b,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -22917,8 +37692,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1022] = {
- .class_hid = BNXT_ULP_CLASS_HID_0f96,
+ [1632] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0c9d,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22532UL,
@@ -22936,8 +37711,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1023] = {
- .class_hid = BNXT_ULP_CLASS_HID_1006,
+ [1633] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19af,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -22954,8 +37729,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1024] = {
- .class_hid = BNXT_ULP_CLASS_HID_7196,
+ [1634] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0131,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28676UL,
@@ -22973,8 +37748,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1025] = {
- .class_hid = BNXT_ULP_CLASS_HID_4132,
+ [1635] = {
+ .class_hid = BNXT_ULP_CLASS_HID_08c9,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -22992,8 +37767,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1026] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e0e,
+ [1636] = {
+ .class_hid = BNXT_ULP_CLASS_HID_10fd,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30724UL,
@@ -23012,8 +37787,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1027] = {
- .class_hid = BNXT_ULP_CLASS_HID_59fe,
+ [1637] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1dcf,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -23028,8 +37803,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1028] = {
- .class_hid = BNXT_ULP_CLASS_HID_511a,
+ [1638] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0559,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16388UL,
@@ -23045,8 +37820,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1029] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c32,
+ [1639] = {
+ .class_hid = BNXT_ULP_CLASS_HID_018d,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -23062,8 +37837,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1030] = {
- .class_hid = BNXT_ULP_CLASS_HID_175e,
+ [1640] = {
+ .class_hid = BNXT_ULP_CLASS_HID_091f,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24580UL,
@@ -23080,8 +37855,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1031] = {
- .class_hid = BNXT_ULP_CLASS_HID_0eb2,
+ [1641] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810c7,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -23097,8 +37872,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1032] = {
- .class_hid = BNXT_ULP_CLASS_HID_09de,
+ [1642] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81851,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49156UL,
@@ -23115,8 +37890,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1033] = {
- .class_hid = BNXT_ULP_CLASS_HID_5c3a,
+ [1643] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80485,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -23133,8 +37908,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1034] = {
- .class_hid = BNXT_ULP_CLASS_HID_5766,
+ [1644] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80c17,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57348UL,
@@ -23152,8 +37927,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1035] = {
- .class_hid = BNXT_ULP_CLASS_HID_79fa,
+ [1645] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41343,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -23169,8 +37944,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1036] = {
- .class_hid = BNXT_ULP_CLASS_HID_7126,
+ [1646] = {
+ .class_hid = BNXT_ULP_CLASS_HID_41add,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81924UL,
@@ -23187,8 +37962,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1037] = {
- .class_hid = BNXT_ULP_CLASS_HID_3c3e,
+ [1647] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40701,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -23205,8 +37980,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1038] = {
- .class_hid = BNXT_ULP_CLASS_HID_375a,
+ [1648] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40e93,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90116UL,
@@ -23224,8 +37999,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1039] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ebe,
+ [1649] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16bb,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -23242,8 +38017,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1040] = {
- .class_hid = BNXT_ULP_CLASS_HID_29da,
+ [1650] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1dd5,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114692UL,
@@ -23261,8 +38036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1041] = {
- .class_hid = BNXT_ULP_CLASS_HID_14f2,
+ [1651] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1a79,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -23280,8 +38055,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1042] = {
- .class_hid = BNXT_ULP_CLASS_HID_7762,
+ [1652] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c018b,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122884UL,
@@ -23300,8 +38075,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1043] = {
- .class_hid = BNXT_ULP_CLASS_HID_19e8,
+ [1653] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81aa8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -23317,8 +38092,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1044] = {
- .class_hid = BNXT_ULP_CLASS_HID_110c,
+ [1654] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8021e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32772UL,
@@ -23335,8 +38110,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1045] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d48,
+ [1655] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815c8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -23353,8 +38128,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1046] = {
- .class_hid = BNXT_ULP_CLASS_HID_446c,
+ [1656] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cbe,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32836UL,
@@ -23372,8 +38147,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1047] = {
- .class_hid = BNXT_ULP_CLASS_HID_0eac,
+ [1657] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810b8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -23390,8 +38165,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1048] = {
- .class_hid = BNXT_ULP_CLASS_HID_09c0,
+ [1658] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8182e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49156UL,
@@ -23409,8 +38184,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1049] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ad0,
+ [1659] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8037a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -23428,8 +38203,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1050] = {
- .class_hid = BNXT_ULP_CLASS_HID_15f4,
+ [1660] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80ae8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49220UL,
@@ -23448,8 +38223,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1051] = {
- .class_hid = BNXT_ULP_CLASS_HID_39ec,
+ [1661] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1834,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -23466,8 +38241,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1052] = {
- .class_hid = BNXT_ULP_CLASS_HID_3100,
+ [1662] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c079a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98308UL,
@@ -23485,8 +38260,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1053] = {
- .class_hid = BNXT_ULP_CLASS_HID_0210,
+ [1663] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0af6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -23504,8 +38279,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1054] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d34,
+ [1664] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c123a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98372UL,
@@ -23524,8 +38299,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1055] = {
- .class_hid = BNXT_ULP_CLASS_HID_2ea0,
+ [1665] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16c4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -23543,8 +38318,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1056] = {
- .class_hid = BNXT_ULP_CLASS_HID_29c4,
+ [1666] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1daa,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114692UL,
@@ -23563,8 +38338,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1057] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ad4,
+ [1667] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0086,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -23583,8 +38358,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1058] = {
- .class_hid = BNXT_ULP_CLASS_HID_35e8,
+ [1668] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0874,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114756UL,
@@ -23604,8 +38379,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1059] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d80,
+ [1669] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a19ea,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -23622,8 +38397,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1060] = {
- .class_hid = BNXT_ULP_CLASS_HID_54a4,
+ [1670] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0158,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163844UL,
@@ -23641,8 +38416,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1061] = {
- .class_hid = BNXT_ULP_CLASS_HID_29b4,
+ [1671] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0bb4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -23660,8 +38435,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1062] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c8,
+ [1672] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a13f8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163908UL,
@@ -23680,8 +38455,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1063] = {
- .class_hid = BNXT_ULP_CLASS_HID_7244,
+ [1673] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a17fa,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -23699,8 +38474,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1064] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d98,
+ [1674] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1f68,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180228UL,
@@ -23719,8 +38494,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1065] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e68,
+ [1675] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0244,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -23739,8 +38514,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1066] = {
- .class_hid = BNXT_ULP_CLASS_HID_598c,
+ [1676] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a092a,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180292UL,
@@ -23760,8 +38535,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1067] = {
- .class_hid = BNXT_ULP_CLASS_HID_1248,
+ [1677] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1f76,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -23779,8 +38554,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1068] = {
- .class_hid = BNXT_ULP_CLASS_HID_74d8,
+ [1678] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e06e4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229380UL,
@@ -23799,8 +38574,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1069] = {
- .class_hid = BNXT_ULP_CLASS_HID_49a8,
+ [1679] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0930,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -23819,8 +38594,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1070] = {
- .class_hid = BNXT_ULP_CLASS_HID_40cc,
+ [1680] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1104,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229444UL,
@@ -23840,8 +38615,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1071] = {
- .class_hid = BNXT_ULP_CLASS_HID_0b0c,
+ [1681] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1506,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -23860,8 +38635,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1072] = {
- .class_hid = BNXT_ULP_CLASS_HID_0220,
+ [1682] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1cf4,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245764UL,
@@ -23881,8 +38656,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1073] = {
- .class_hid = BNXT_ULP_CLASS_HID_1730,
+ [1683] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e07c0,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -23902,8 +38677,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1074] = {
- .class_hid = BNXT_ULP_CLASS_HID_7980,
+ [1684] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0eb6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245828UL,
@@ -23924,8 +38699,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1075] = {
- .class_hid = BNXT_ULP_CLASS_HID_1db0,
+ [1685] = {
+ .class_hid = BNXT_ULP_CLASS_HID_206ee,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -23941,8 +38716,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1076] = {
- .class_hid = BNXT_ULP_CLASS_HID_1494,
+ [1686] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e5c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131076UL,
@@ -23959,8 +38734,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1077] = {
- .class_hid = BNXT_ULP_CLASS_HID_70d0,
+ [1687] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2110e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -23977,8 +38752,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1078] = {
- .class_hid = BNXT_ULP_CLASS_HID_4834,
+ [1688] = {
+ .class_hid = BNXT_ULP_CLASS_HID_218fc,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131140UL,
@@ -23996,8 +38771,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1079] = {
- .class_hid = BNXT_ULP_CLASS_HID_3db4,
+ [1689] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60462,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -24014,8 +38789,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1080] = {
- .class_hid = BNXT_ULP_CLASS_HID_3498,
+ [1690] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603d0,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196612UL,
@@ -24033,8 +38808,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1081] = {
- .class_hid = BNXT_ULP_CLASS_HID_0988,
+ [1691] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61682,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -24052,8 +38827,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1082] = {
- .class_hid = BNXT_ULP_CLASS_HID_00ec,
+ [1692] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e70,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196676UL,
@@ -24072,8 +38847,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1083] = {
- .class_hid = BNXT_ULP_CLASS_HID_23f44,
+ [1693] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3167e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -24090,8 +38865,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1084] = {
- .class_hid = BNXT_ULP_CLASS_HID_236a8,
+ [1694] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31dec,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393220UL,
@@ -24109,8 +38884,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1085] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b58,
+ [1695] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30030,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -24128,8 +38903,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1086] = {
- .class_hid = BNXT_ULP_CLASS_HID_202bc,
+ [1696] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30fae,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393284UL,
@@ -24148,8 +38923,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1087] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f48,
+ [1697] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70b14,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -24167,8 +38942,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1088] = {
- .class_hid = BNXT_ULP_CLASS_HID_256ac,
+ [1698] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71360,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458756UL,
@@ -24187,8 +38962,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1089] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b5c,
+ [1699] = {
+ .class_hid = BNXT_ULP_CLASS_HID_705b4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -24207,8 +38982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1090] = {
- .class_hid = BNXT_ULP_CLASS_HID_22280,
+ [1700] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70d22,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458820UL,
@@ -24228,8 +39003,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1091] = {
- .class_hid = BNXT_ULP_CLASS_HID_14000,
+ [1701] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29e26,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -24246,8 +39021,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1092] = {
- .class_hid = BNXT_ULP_CLASS_HID_15b64,
+ [1702] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28594,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655364UL,
@@ -24265,8 +39040,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1093] = {
- .class_hid = BNXT_ULP_CLASS_HID_12c14,
+ [1703] = {
+ .class_hid = BNXT_ULP_CLASS_HID_288f8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -24284,8 +39059,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1094] = {
- .class_hid = BNXT_ULP_CLASS_HID_12778,
+ [1704] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29034,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655428UL,
@@ -24304,8 +39079,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1095] = {
- .class_hid = BNXT_ULP_CLASS_HID_118f8,
+ [1705] = {
+ .class_hid = BNXT_ULP_CLASS_HID_693ba,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -24323,8 +39098,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1096] = {
- .class_hid = BNXT_ULP_CLASS_HID_113dc,
+ [1706] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69b28,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720900UL,
@@ -24343,8 +39118,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1097] = {
- .class_hid = BNXT_ULP_CLASS_HID_14c18,
+ [1707] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68e7c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -24363,8 +39138,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1098] = {
- .class_hid = BNXT_ULP_CLASS_HID_1477c,
+ [1708] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69648,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720964UL,
@@ -24384,8 +39159,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1099] = {
- .class_hid = BNXT_ULP_CLASS_HID_31a88,
+ [1709] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38de8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -24403,8 +39178,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1100] = {
- .class_hid = BNXT_ULP_CLASS_HID_315ec,
+ [1710] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39524,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917508UL,
@@ -24423,8 +39198,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1101] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e28,
+ [1711] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39808,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -24443,8 +39218,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1102] = {
- .class_hid = BNXT_ULP_CLASS_HID_3490c,
+ [1712] = {
+ .class_hid = BNXT_ULP_CLASS_HID_387e6,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917572UL,
@@ -24464,8 +39239,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1103] = {
- .class_hid = BNXT_ULP_CLASS_HID_33a8c,
+ [1713] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7836c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -24484,8 +39259,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1104] = {
- .class_hid = BNXT_ULP_CLASS_HID_335f0,
+ [1714] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78ada,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983044UL,
@@ -24505,8 +39280,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1105] = {
- .class_hid = BNXT_ULP_CLASS_HID_306e0,
+ [1715] = {
+ .class_hid = BNXT_ULP_CLASS_HID_79d8c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -24526,8 +39301,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1106] = {
- .class_hid = BNXT_ULP_CLASS_HID_301c4,
+ [1716] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7857a,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983108UL,
@@ -24548,8 +39323,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1107] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a08,
+ [1717] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81ad8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -24565,8 +39340,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1108] = {
- .class_hid = BNXT_ULP_CLASS_HID_12ec,
+ [1718] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8026e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32772UL,
@@ -24583,8 +39358,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1109] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea8,
+ [1719] = {
+ .class_hid = BNXT_ULP_CLASS_HID_815b8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -24601,8 +39376,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1110] = {
- .class_hid = BNXT_ULP_CLASS_HID_478c,
+ [1720] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81cce,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32836UL,
@@ -24620,8 +39395,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1111] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d4c,
+ [1721] = {
+ .class_hid = BNXT_ULP_CLASS_HID_810c8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -24638,8 +39413,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1112] = {
- .class_hid = BNXT_ULP_CLASS_HID_0a20,
+ [1722] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8185e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49156UL,
@@ -24657,8 +39432,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1113] = {
- .class_hid = BNXT_ULP_CLASS_HID_1930,
+ [1723] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8030a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -24676,8 +39451,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1114] = {
- .class_hid = BNXT_ULP_CLASS_HID_1614,
+ [1724] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80a98,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49220UL,
@@ -24696,8 +39471,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1115] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a0c,
+ [1725] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1844,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -24714,8 +39489,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1116] = {
- .class_hid = BNXT_ULP_CLASS_HID_32e0,
+ [1726] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c07ea,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98308UL,
@@ -24733,8 +39508,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1117] = {
- .class_hid = BNXT_ULP_CLASS_HID_01f0,
+ [1727] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0a86,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -24752,8 +39527,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1118] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ed4,
+ [1728] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c124a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98372UL,
@@ -24772,8 +39547,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1119] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d40,
+ [1729] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c16b4,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -24791,8 +39566,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1120] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a24,
+ [1730] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1dda,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114692UL,
@@ -24811,8 +39586,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1121] = {
- .class_hid = BNXT_ULP_CLASS_HID_3934,
+ [1731] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c00f6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -24831,8 +39606,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1122] = {
- .class_hid = BNXT_ULP_CLASS_HID_3608,
+ [1732] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0804,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114756UL,
@@ -24852,8 +39627,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1123] = {
- .class_hid = BNXT_ULP_CLASS_HID_5e60,
+ [1733] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a199a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -24870,8 +39645,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1124] = {
- .class_hid = BNXT_ULP_CLASS_HID_5744,
+ [1734] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0128,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163844UL,
@@ -24889,8 +39664,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1125] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a54,
+ [1735] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0bc4,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -24908,8 +39683,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1126] = {
- .class_hid = BNXT_ULP_CLASS_HID_2328,
+ [1736] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1388,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163908UL,
@@ -24928,8 +39703,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1127] = {
- .class_hid = BNXT_ULP_CLASS_HID_71a4,
+ [1737] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a178a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -24947,8 +39722,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1128] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e78,
+ [1738] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1f18,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180228UL,
@@ -24967,8 +39742,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1129] = {
- .class_hid = BNXT_ULP_CLASS_HID_5d88,
+ [1739] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0234,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -24987,8 +39762,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1130] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a6c,
+ [1740] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a095a,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180292UL,
@@ -25008,8 +39783,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1131] = {
- .class_hid = BNXT_ULP_CLASS_HID_11a8,
+ [1741] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1f06,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -25027,8 +39802,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1132] = {
- .class_hid = BNXT_ULP_CLASS_HID_7738,
+ [1742] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0694,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229380UL,
@@ -25047,8 +39822,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1133] = {
- .class_hid = BNXT_ULP_CLASS_HID_4a48,
+ [1743] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0940,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -25067,8 +39842,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1134] = {
- .class_hid = BNXT_ULP_CLASS_HID_432c,
+ [1744] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1174,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229444UL,
@@ -25088,8 +39863,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1135] = {
- .class_hid = BNXT_ULP_CLASS_HID_08ec,
+ [1745] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1576,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -25108,8 +39883,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1136] = {
- .class_hid = BNXT_ULP_CLASS_HID_01c0,
+ [1746] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1c84,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245764UL,
@@ -25129,8 +39904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1137] = {
- .class_hid = BNXT_ULP_CLASS_HID_14d0,
+ [1747] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e07b0,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -25150,8 +39925,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1138] = {
- .class_hid = BNXT_ULP_CLASS_HID_7a60,
+ [1748] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0ec6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245828UL,
@@ -25172,8 +39947,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1139] = {
- .class_hid = BNXT_ULP_CLASS_HID_1d90,
+ [1749] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2069e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -25189,8 +39964,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1140] = {
- .class_hid = BNXT_ULP_CLASS_HID_14b4,
+ [1750] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20e2c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131076UL,
@@ -25207,8 +39982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1141] = {
- .class_hid = BNXT_ULP_CLASS_HID_70f0,
+ [1751] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2117e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -25225,8 +40000,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1142] = {
- .class_hid = BNXT_ULP_CLASS_HID_4814,
+ [1752] = {
+ .class_hid = BNXT_ULP_CLASS_HID_2188c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131140UL,
@@ -25244,8 +40019,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1143] = {
- .class_hid = BNXT_ULP_CLASS_HID_3d94,
+ [1753] = {
+ .class_hid = BNXT_ULP_CLASS_HID_60412,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -25262,8 +40037,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1144] = {
- .class_hid = BNXT_ULP_CLASS_HID_34b8,
+ [1754] = {
+ .class_hid = BNXT_ULP_CLASS_HID_603a0,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196612UL,
@@ -25281,8 +40056,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1145] = {
- .class_hid = BNXT_ULP_CLASS_HID_09a8,
+ [1755] = {
+ .class_hid = BNXT_ULP_CLASS_HID_616f2,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -25300,8 +40075,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1146] = {
- .class_hid = BNXT_ULP_CLASS_HID_00cc,
+ [1756] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61e00,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196676UL,
@@ -25320,8 +40095,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1147] = {
- .class_hid = BNXT_ULP_CLASS_HID_23f64,
+ [1757] = {
+ .class_hid = BNXT_ULP_CLASS_HID_3160e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -25338,8 +40113,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1148] = {
- .class_hid = BNXT_ULP_CLASS_HID_23688,
+ [1758] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31d9c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393220UL,
@@ -25357,8 +40132,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1149] = {
- .class_hid = BNXT_ULP_CLASS_HID_20b78,
+ [1759] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30040,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -25376,8 +40151,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1150] = {
- .class_hid = BNXT_ULP_CLASS_HID_2029c,
+ [1760] = {
+ .class_hid = BNXT_ULP_CLASS_HID_30fde,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393284UL,
@@ -25396,8 +40171,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1151] = {
- .class_hid = BNXT_ULP_CLASS_HID_25f68,
+ [1761] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70b64,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -25415,8 +40190,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1152] = {
- .class_hid = BNXT_ULP_CLASS_HID_2568c,
+ [1762] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71310,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458756UL,
@@ -25435,8 +40210,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1153] = {
- .class_hid = BNXT_ULP_CLASS_HID_22b7c,
+ [1763] = {
+ .class_hid = BNXT_ULP_CLASS_HID_705c4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -25455,8 +40230,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1154] = {
- .class_hid = BNXT_ULP_CLASS_HID_222a0,
+ [1764] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70d52,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458820UL,
@@ -25476,8 +40251,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1155] = {
- .class_hid = BNXT_ULP_CLASS_HID_14020,
+ [1765] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29e56,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -25494,8 +40269,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1156] = {
- .class_hid = BNXT_ULP_CLASS_HID_15b44,
+ [1766] = {
+ .class_hid = BNXT_ULP_CLASS_HID_285e4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655364UL,
@@ -25513,8 +40288,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1157] = {
- .class_hid = BNXT_ULP_CLASS_HID_12c34,
+ [1767] = {
+ .class_hid = BNXT_ULP_CLASS_HID_28888,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -25532,8 +40307,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1158] = {
- .class_hid = BNXT_ULP_CLASS_HID_12758,
+ [1768] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29044,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655428UL,
@@ -25552,8 +40327,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1159] = {
- .class_hid = BNXT_ULP_CLASS_HID_118d8,
+ [1769] = {
+ .class_hid = BNXT_ULP_CLASS_HID_693ca,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -25571,8 +40346,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1160] = {
- .class_hid = BNXT_ULP_CLASS_HID_113fc,
+ [1770] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69b58,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720900UL,
@@ -25591,8 +40366,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1161] = {
- .class_hid = BNXT_ULP_CLASS_HID_14c38,
+ [1771] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68e0c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -25611,8 +40386,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1162] = {
- .class_hid = BNXT_ULP_CLASS_HID_1475c,
+ [1772] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69638,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720964UL,
@@ -25632,8 +40407,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1163] = {
- .class_hid = BNXT_ULP_CLASS_HID_31aa8,
+ [1773] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38d98,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -25651,8 +40426,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1164] = {
- .class_hid = BNXT_ULP_CLASS_HID_315cc,
+ [1774] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39554,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917508UL,
@@ -25671,8 +40446,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1165] = {
- .class_hid = BNXT_ULP_CLASS_HID_34e08,
+ [1775] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39878,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -25691,8 +40466,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1166] = {
- .class_hid = BNXT_ULP_CLASS_HID_3492c,
+ [1776] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38796,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917572UL,
@@ -25712,8 +40487,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1167] = {
- .class_hid = BNXT_ULP_CLASS_HID_33aac,
+ [1777] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7831c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -25732,8 +40507,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1168] = {
- .class_hid = BNXT_ULP_CLASS_HID_335d0,
+ [1778] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78aaa,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983044UL,
@@ -25753,8 +40528,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1169] = {
- .class_hid = BNXT_ULP_CLASS_HID_306c0,
+ [1779] = {
+ .class_hid = BNXT_ULP_CLASS_HID_79dfc,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -25774,8 +40549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1170] = {
- .class_hid = BNXT_ULP_CLASS_HID_301e4,
+ [1780] = {
+ .class_hid = BNXT_ULP_CLASS_HID_7850a,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983108UL,
@@ -25796,8 +40571,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1171] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d32,
+ [1781] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03b7,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4096UL,
@@ -25810,8 +40585,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [1172] = {
- .class_hid = BNXT_ULP_CLASS_HID_54aa,
+ [1782] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13f3,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 6144UL,
@@ -25825,8 +40600,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR }
},
- [1173] = {
- .class_hid = BNXT_ULP_CLASS_HID_0686,
+ [1783] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0255,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 16384UL,
@@ -25839,8 +40614,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [1174] = {
- .class_hid = BNXT_ULP_CLASS_HID_540e,
+ [1784] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1675,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 24576UL,
@@ -25854,8 +40629,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR }
},
- [1175] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e3c,
+ [1785] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f52,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32768UL,
@@ -25869,8 +40644,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1176] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a20,
+ [1786] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819f2,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 32832UL,
@@ -25885,8 +40660,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1177] = {
- .class_hid = BNXT_ULP_CLASS_HID_46f0,
+ [1787] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80542,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49152UL,
@@ -25901,8 +40676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1178] = {
- .class_hid = BNXT_ULP_CLASS_HID_52e4,
+ [1788] = {
+ .class_hid = BNXT_ULP_CLASS_HID_817e2,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 49216UL,
@@ -25918,8 +40693,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR }
},
- [1179] = {
- .class_hid = BNXT_ULP_CLASS_HID_55e4,
+ [1789] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a98,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131072UL,
@@ -25933,8 +40708,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1180] = {
- .class_hid = BNXT_ULP_CLASS_HID_21f8,
+ [1790] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20538,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 131136UL,
@@ -25949,8 +40724,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1181] = {
- .class_hid = BNXT_ULP_CLASS_HID_75e8,
+ [1791] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6081c,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196608UL,
@@ -25965,8 +40740,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1182] = {
- .class_hid = BNXT_ULP_CLASS_HID_41fc,
+ [1792] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61abc,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 196672UL,
@@ -25982,8 +40757,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR }
},
- [1183] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d12,
+ [1793] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03a7,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4096UL,
@@ -25997,8 +40772,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [1184] = {
- .class_hid = BNXT_ULP_CLASS_HID_548a,
+ [1794] = {
+ .class_hid = BNXT_ULP_CLASS_HID_13e3,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 6144UL,
@@ -26013,8 +40788,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR }
},
- [1185] = {
- .class_hid = BNXT_ULP_CLASS_HID_3356,
+ [1795] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1047,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 12288UL,
@@ -26029,8 +40804,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [1186] = {
- .class_hid = BNXT_ULP_CLASS_HID_1ace,
+ [1796] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0721,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 14336UL,
@@ -26046,8 +40821,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT }
},
- [1187] = {
- .class_hid = BNXT_ULP_CLASS_HID_1a9a,
+ [1797] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19b7,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 20480UL,
@@ -26062,8 +40837,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1188] = {
- .class_hid = BNXT_ULP_CLASS_HID_4d46,
+ [1798] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0911,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 22528UL,
@@ -26079,8 +40854,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1189] = {
- .class_hid = BNXT_ULP_CLASS_HID_2812,
+ [1799] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0df5,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 28672UL,
@@ -26096,8 +40871,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1190] = {
- .class_hid = BNXT_ULP_CLASS_HID_338a,
+ [1800] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d31,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 30720UL,
@@ -26114,8 +40889,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT }
},
- [1191] = {
- .class_hid = BNXT_ULP_CLASS_HID_06e6,
+ [1801] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0245,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 16384UL,
@@ -26129,8 +40904,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [1192] = {
- .class_hid = BNXT_ULP_CLASS_HID_546e,
+ [1802] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1665,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 24576UL,
@@ -26145,8 +40920,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR }
},
- [1193] = {
- .class_hid = BNXT_ULP_CLASS_HID_46ee,
+ [1803] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8055d,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 49152UL,
@@ -26161,8 +40936,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1194] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d22,
+ [1804] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80893,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 57344UL,
@@ -26178,8 +40953,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT }
},
- [1195] = {
- .class_hid = BNXT_ULP_CLASS_HID_26e2,
+ [1805] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407d9,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 81920UL,
@@ -26194,8 +40969,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1196] = {
- .class_hid = BNXT_ULP_CLASS_HID_746a,
+ [1806] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b1f,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 90112UL,
@@ -26211,8 +40986,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1197] = {
- .class_hid = BNXT_ULP_CLASS_HID_1fa6,
+ [1807] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1ad1,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 114688UL,
@@ -26228,8 +41003,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1198] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d2e,
+ [1808] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e17,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 122880UL,
@@ -26246,8 +41021,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT }
},
- [1199] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ef2,
+ [1809] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03d7,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4096UL,
@@ -26261,8 +41036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1200] = {
- .class_hid = BNXT_ULP_CLASS_HID_576a,
+ [1810] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1393,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 6144UL,
@@ -26277,8 +41052,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR }
},
- [1201] = {
- .class_hid = BNXT_ULP_CLASS_HID_30b6,
+ [1811] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1037,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 12288UL,
@@ -26293,8 +41068,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1202] = {
- .class_hid = BNXT_ULP_CLASS_HID_192e,
+ [1812] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0751,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 14336UL,
@@ -26310,8 +41085,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT }
},
- [1203] = {
- .class_hid = BNXT_ULP_CLASS_HID_197a,
+ [1813] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19c7,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 20480UL,
@@ -26326,8 +41101,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1204] = {
- .class_hid = BNXT_ULP_CLASS_HID_4ea6,
+ [1814] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0961,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 22528UL,
@@ -26343,8 +41118,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1205] = {
- .class_hid = BNXT_ULP_CLASS_HID_2bf2,
+ [1815] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0d85,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 28672UL,
@@ -26360,8 +41135,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1206] = {
- .class_hid = BNXT_ULP_CLASS_HID_306a,
+ [1816] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1d41,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 30720UL,
@@ -26378,8 +41153,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT }
},
- [1207] = {
- .class_hid = BNXT_ULP_CLASS_HID_06c6,
+ [1817] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0235,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 16384UL,
@@ -26393,8 +41168,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1208] = {
- .class_hid = BNXT_ULP_CLASS_HID_544e,
+ [1818] = {
+ .class_hid = BNXT_ULP_CLASS_HID_1615,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 24576UL,
@@ -26409,8 +41184,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR }
},
- [1209] = {
- .class_hid = BNXT_ULP_CLASS_HID_46ce,
+ [1819] = {
+ .class_hid = BNXT_ULP_CLASS_HID_8052d,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 49152UL,
@@ -26425,8 +41200,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1210] = {
- .class_hid = BNXT_ULP_CLASS_HID_0d02,
+ [1820] = {
+ .class_hid = BNXT_ULP_CLASS_HID_808e3,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 57344UL,
@@ -26442,8 +41217,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT }
},
- [1211] = {
- .class_hid = BNXT_ULP_CLASS_HID_26c2,
+ [1821] = {
+ .class_hid = BNXT_ULP_CLASS_HID_407a9,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 81920UL,
@@ -26458,8 +41233,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1212] = {
- .class_hid = BNXT_ULP_CLASS_HID_744a,
+ [1822] = {
+ .class_hid = BNXT_ULP_CLASS_HID_40b6f,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 90112UL,
@@ -26475,8 +41250,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1213] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f86,
+ [1823] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1aa1,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 114688UL,
@@ -26492,8 +41267,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1214] = {
- .class_hid = BNXT_ULP_CLASS_HID_2d0e,
+ [1824] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0e67,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 122880UL,
@@ -26510,8 +41285,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT }
},
- [1215] = {
- .class_hid = BNXT_ULP_CLASS_HID_2e1c,
+ [1825] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f42,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32768UL,
@@ -26526,8 +41301,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1216] = {
- .class_hid = BNXT_ULP_CLASS_HID_3a00,
+ [1826] = {
+ .class_hid = BNXT_ULP_CLASS_HID_819e2,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 32832UL,
@@ -26543,8 +41318,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1217] = {
- .class_hid = BNXT_ULP_CLASS_HID_46d0,
+ [1827] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80552,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49152UL,
@@ -26560,8 +41335,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1218] = {
- .class_hid = BNXT_ULP_CLASS_HID_52c4,
+ [1828] = {
+ .class_hid = BNXT_ULP_CLASS_HID_817f2,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 49216UL,
@@ -26578,8 +41353,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR }
},
- [1219] = {
- .class_hid = BNXT_ULP_CLASS_HID_4e10,
+ [1829] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0cce,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98304UL,
@@ -26595,8 +41370,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1220] = {
- .class_hid = BNXT_ULP_CLASS_HID_5a04,
+ [1830] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1f6e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 98368UL,
@@ -26613,8 +41388,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1221] = {
- .class_hid = BNXT_ULP_CLASS_HID_1f98,
+ [1831] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1ade,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114688UL,
@@ -26631,8 +41406,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1222] = {
- .class_hid = BNXT_ULP_CLASS_HID_72f8,
+ [1832] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c157e,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 114752UL,
@@ -26650,8 +41425,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT }
},
- [1223] = {
- .class_hid = BNXT_ULP_CLASS_HID_0a78,
+ [1833] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0d8c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163840UL,
@@ -26667,8 +41442,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1224] = {
- .class_hid = BNXT_ULP_CLASS_HID_166c,
+ [1834] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a182c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 163904UL,
@@ -26685,8 +41460,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1225] = {
- .class_hid = BNXT_ULP_CLASS_HID_233c,
+ [1835] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1b9c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180224UL,
@@ -26703,8 +41478,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1226] = {
- .class_hid = BNXT_ULP_CLASS_HID_0f20,
+ [1836] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a163c,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 180288UL,
@@ -26722,8 +41497,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1227] = {
- .class_hid = BNXT_ULP_CLASS_HID_2a7c,
+ [1837] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0308,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229376UL,
@@ -26740,8 +41515,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1228] = {
- .class_hid = BNXT_ULP_CLASS_HID_3660,
+ [1838] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1da8,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 229440UL,
@@ -26759,8 +41534,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1229] = {
- .class_hid = BNXT_ULP_CLASS_HID_4330,
+ [1839] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1918,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245760UL,
@@ -26778,8 +41553,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1230] = {
- .class_hid = BNXT_ULP_CLASS_HID_2f24,
+ [1840] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0bda,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 245824UL,
@@ -26798,8 +41573,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT }
},
- [1231] = {
- .class_hid = BNXT_ULP_CLASS_HID_5584,
+ [1841] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20a88,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131072UL,
@@ -26814,8 +41589,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1232] = {
- .class_hid = BNXT_ULP_CLASS_HID_2198,
+ [1842] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20528,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 131136UL,
@@ -26831,8 +41606,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1233] = {
- .class_hid = BNXT_ULP_CLASS_HID_7588,
+ [1843] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6080c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196608UL,
@@ -26848,8 +41623,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1234] = {
- .class_hid = BNXT_ULP_CLASS_HID_419c,
+ [1844] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61aac,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 196672UL,
@@ -26866,8 +41641,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR }
},
- [1235] = {
- .class_hid = BNXT_ULP_CLASS_HID_27758,
+ [1845] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31a18,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393216UL,
@@ -26883,8 +41658,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1236] = {
- .class_hid = BNXT_ULP_CLASS_HID_243ac,
+ [1846] = {
+ .class_hid = BNXT_ULP_CLASS_HID_314b8,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 393280UL,
@@ -26901,8 +41676,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1237] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c10,
+ [1847] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71f9c,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458752UL,
@@ -26919,8 +41694,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1238] = {
- .class_hid = BNXT_ULP_CLASS_HID_21864,
+ [1848] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70a5e,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 458816UL,
@@ -26938,8 +41713,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT }
},
- [1239] = {
- .class_hid = BNXT_ULP_CLASS_HID_130c8,
+ [1849] = {
+ .class_hid = BNXT_ULP_CLASS_HID_282c0,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655360UL,
@@ -26955,8 +41730,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1240] = {
- .class_hid = BNXT_ULP_CLASS_HID_11cdc,
+ [1850] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29d60,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 655424UL,
@@ -26973,8 +41748,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1241] = {
- .class_hid = BNXT_ULP_CLASS_HID_150cc,
+ [1851] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68044,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720896UL,
@@ -26991,8 +41766,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1242] = {
- .class_hid = BNXT_ULP_CLASS_HID_13d20,
+ [1852] = {
+ .class_hid = BNXT_ULP_CLASS_HID_692e4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 720960UL,
@@ -27010,8 +41785,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1243] = {
- .class_hid = BNXT_ULP_CLASS_HID_3529c,
+ [1853] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39250,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917504UL,
@@ -27028,8 +41803,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1244] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ef0,
+ [1854] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38c12,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 917568UL,
@@ -27047,8 +41822,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1245] = {
- .class_hid = BNXT_ULP_CLASS_HID_372e0,
+ [1855] = {
+ .class_hid = BNXT_ULP_CLASS_HID_797d4,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983040UL,
@@ -27066,8 +41841,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1246] = {
- .class_hid = BNXT_ULP_CLASS_HID_35ef4,
+ [1856] = {
+ .class_hid = BNXT_ULP_CLASS_HID_78196,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 983104UL,
@@ -27086,8 +41861,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT |
BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT }
},
- [1247] = {
- .class_hid = BNXT_ULP_CLASS_HID_2dfc,
+ [1857] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80f32,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32768UL,
@@ -27102,8 +41877,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1248] = {
- .class_hid = BNXT_ULP_CLASS_HID_39e0,
+ [1858] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81992,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 32832UL,
@@ -27119,8 +41894,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1249] = {
- .class_hid = BNXT_ULP_CLASS_HID_4530,
+ [1859] = {
+ .class_hid = BNXT_ULP_CLASS_HID_80522,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49152UL,
@@ -27136,8 +41911,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1250] = {
- .class_hid = BNXT_ULP_CLASS_HID_5124,
+ [1860] = {
+ .class_hid = BNXT_ULP_CLASS_HID_81782,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 49216UL,
@@ -27154,8 +41929,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR }
},
- [1251] = {
- .class_hid = BNXT_ULP_CLASS_HID_4df0,
+ [1861] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c0cbe,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98304UL,
@@ -27171,8 +41946,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1252] = {
- .class_hid = BNXT_ULP_CLASS_HID_59e4,
+ [1862] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1f1e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 98368UL,
@@ -27189,8 +41964,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1253] = {
- .class_hid = BNXT_ULP_CLASS_HID_1c78,
+ [1863] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c1aae,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114688UL,
@@ -27207,8 +41982,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1254] = {
- .class_hid = BNXT_ULP_CLASS_HID_7118,
+ [1864] = {
+ .class_hid = BNXT_ULP_CLASS_HID_c150e,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 114752UL,
@@ -27226,8 +42001,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT }
},
- [1255] = {
- .class_hid = BNXT_ULP_CLASS_HID_0998,
+ [1865] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a0dfc,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163840UL,
@@ -27243,8 +42018,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1256] = {
- .class_hid = BNXT_ULP_CLASS_HID_158c,
+ [1866] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a185c,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 163904UL,
@@ -27261,8 +42036,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1257] = {
- .class_hid = BNXT_ULP_CLASS_HID_20dc,
+ [1867] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a1bec,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180224UL,
@@ -27279,8 +42054,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1258] = {
- .class_hid = BNXT_ULP_CLASS_HID_0cc0,
+ [1868] = {
+ .class_hid = BNXT_ULP_CLASS_HID_a164c,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 180288UL,
@@ -27298,8 +42073,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1259] = {
- .class_hid = BNXT_ULP_CLASS_HID_299c,
+ [1869] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0378,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229376UL,
@@ -27316,8 +42091,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1260] = {
- .class_hid = BNXT_ULP_CLASS_HID_3580,
+ [1870] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1dd8,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 229440UL,
@@ -27335,8 +42110,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1261] = {
- .class_hid = BNXT_ULP_CLASS_HID_40d0,
+ [1871] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e1968,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245760UL,
@@ -27354,8 +42129,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1262] = {
- .class_hid = BNXT_ULP_CLASS_HID_2cc4,
+ [1872] = {
+ .class_hid = BNXT_ULP_CLASS_HID_e0baa,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 245824UL,
@@ -27374,8 +42149,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT }
},
- [1263] = {
- .class_hid = BNXT_ULP_CLASS_HID_55a4,
+ [1873] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20af8,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131072UL,
@@ -27390,8 +42165,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.field_sig = { .bits =
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1264] = {
- .class_hid = BNXT_ULP_CLASS_HID_21b8,
+ [1874] = {
+ .class_hid = BNXT_ULP_CLASS_HID_20558,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 131136UL,
@@ -27407,8 +42182,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1265] = {
- .class_hid = BNXT_ULP_CLASS_HID_75a8,
+ [1875] = {
+ .class_hid = BNXT_ULP_CLASS_HID_6087c,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196608UL,
@@ -27424,8 +42199,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1266] = {
- .class_hid = BNXT_ULP_CLASS_HID_41bc,
+ [1876] = {
+ .class_hid = BNXT_ULP_CLASS_HID_61adc,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 196672UL,
@@ -27442,8 +42217,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR }
},
- [1267] = {
- .class_hid = BNXT_ULP_CLASS_HID_27778,
+ [1877] = {
+ .class_hid = BNXT_ULP_CLASS_HID_31a68,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393216UL,
@@ -27459,8 +42234,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1268] = {
- .class_hid = BNXT_ULP_CLASS_HID_2438c,
+ [1878] = {
+ .class_hid = BNXT_ULP_CLASS_HID_314c8,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 393280UL,
@@ -27477,8 +42252,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1269] = {
- .class_hid = BNXT_ULP_CLASS_HID_20c30,
+ [1879] = {
+ .class_hid = BNXT_ULP_CLASS_HID_71fec,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458752UL,
@@ -27495,8 +42270,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1270] = {
- .class_hid = BNXT_ULP_CLASS_HID_21844,
+ [1880] = {
+ .class_hid = BNXT_ULP_CLASS_HID_70a2e,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 458816UL,
@@ -27514,8 +42289,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT }
},
- [1271] = {
- .class_hid = BNXT_ULP_CLASS_HID_130e8,
+ [1881] = {
+ .class_hid = BNXT_ULP_CLASS_HID_282b0,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655360UL,
@@ -27531,8 +42306,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1272] = {
- .class_hid = BNXT_ULP_CLASS_HID_11cfc,
+ [1882] = {
+ .class_hid = BNXT_ULP_CLASS_HID_29d10,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 655424UL,
@@ -27549,8 +42324,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1273] = {
- .class_hid = BNXT_ULP_CLASS_HID_150ec,
+ [1883] = {
+ .class_hid = BNXT_ULP_CLASS_HID_68034,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720896UL,
@@ -27567,8 +42342,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1274] = {
- .class_hid = BNXT_ULP_CLASS_HID_13d00,
+ [1884] = {
+ .class_hid = BNXT_ULP_CLASS_HID_69294,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 720960UL,
@@ -27586,8 +42361,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1275] = {
- .class_hid = BNXT_ULP_CLASS_HID_352bc,
+ [1885] = {
+ .class_hid = BNXT_ULP_CLASS_HID_39220,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917504UL,
@@ -27604,8 +42379,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1276] = {
- .class_hid = BNXT_ULP_CLASS_HID_33ed0,
+ [1886] = {
+ .class_hid = BNXT_ULP_CLASS_HID_38c62,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 917568UL,
@@ -27623,8 +42398,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1277] = {
- .class_hid = BNXT_ULP_CLASS_HID_372c0,
+ [1887] = {
+ .class_hid = BNXT_ULP_CLASS_HID_797a4,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983040UL,
@@ -27642,8 +42417,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1278] = {
- .class_hid = BNXT_ULP_CLASS_HID_35ed4,
+ [1888] = {
+ .class_hid = BNXT_ULP_CLASS_HID_781e6,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 983104UL,
@@ -27662,8 +42437,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT |
BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT }
},
- [1279] = {
- .class_hid = BNXT_ULP_CLASS_HID_3866,
+ [1889] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f05,
.class_tid = 3,
.hdr_sig_id = 0,
.flow_sig_id = 4UL,
@@ -27677,8 +42452,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC }
},
- [1280] = {
- .class_hid = BNXT_ULP_CLASS_HID_381e,
+ [1890] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f09,
.class_tid = 3,
.hdr_sig_id = 1,
.flow_sig_id = 4UL,
@@ -27692,8 +42467,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC }
},
- [1281] = {
- .class_hid = BNXT_ULP_CLASS_HID_3860,
+ [1891] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f06,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 4UL,
@@ -27708,8 +42483,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC }
},
- [1282] = {
- .class_hid = BNXT_ULP_CLASS_HID_0454,
+ [1892] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19a6,
.class_tid = 3,
.hdr_sig_id = 2,
.flow_sig_id = 68UL,
@@ -27725,8 +42500,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID }
},
- [1283] = {
- .class_hid = BNXT_ULP_CLASS_HID_3818,
+ [1893] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f0a,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 4UL,
@@ -27741,8 +42516,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC }
},
- [1284] = {
- .class_hid = BNXT_ULP_CLASS_HID_042c,
+ [1894] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19aa,
.class_tid = 3,
.hdr_sig_id = 3,
.flow_sig_id = 68UL,
@@ -27758,8 +42533,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID }
},
- [1285] = {
- .class_hid = BNXT_ULP_CLASS_HID_3846,
+ [1895] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f15,
.class_tid = 3,
.hdr_sig_id = 4,
.flow_sig_id = 4UL,
@@ -27774,8 +42549,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC }
},
- [1286] = {
- .class_hid = BNXT_ULP_CLASS_HID_387e,
+ [1896] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f19,
.class_tid = 3,
.hdr_sig_id = 5,
.flow_sig_id = 4UL,
@@ -27790,8 +42565,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC }
},
- [1287] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ba6,
+ [1897] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f65,
.class_tid = 3,
.hdr_sig_id = 6,
.flow_sig_id = 4UL,
@@ -27806,8 +42581,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC }
},
- [1288] = {
- .class_hid = BNXT_ULP_CLASS_HID_385e,
+ [1898] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f69,
.class_tid = 3,
.hdr_sig_id = 7,
.flow_sig_id = 4UL,
@@ -27822,8 +42597,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC }
},
- [1289] = {
- .class_hid = BNXT_ULP_CLASS_HID_3840,
+ [1899] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f16,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 4UL,
@@ -27839,8 +42614,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC }
},
- [1290] = {
- .class_hid = BNXT_ULP_CLASS_HID_0474,
+ [1900] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19b6,
.class_tid = 3,
.hdr_sig_id = 8,
.flow_sig_id = 68UL,
@@ -27857,8 +42632,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID }
},
- [1291] = {
- .class_hid = BNXT_ULP_CLASS_HID_3878,
+ [1901] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f1a,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 4UL,
@@ -27874,8 +42649,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC }
},
- [1292] = {
- .class_hid = BNXT_ULP_CLASS_HID_044c,
+ [1902] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19ba,
.class_tid = 3,
.hdr_sig_id = 9,
.flow_sig_id = 68UL,
@@ -27892,8 +42667,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID }
},
- [1293] = {
- .class_hid = BNXT_ULP_CLASS_HID_3ba0,
+ [1903] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f66,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 4UL,
@@ -27909,8 +42684,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC }
},
- [1294] = {
- .class_hid = BNXT_ULP_CLASS_HID_0794,
+ [1904] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19c6,
.class_tid = 3,
.hdr_sig_id = 10,
.flow_sig_id = 68UL,
@@ -27927,8 +42702,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID }
},
- [1295] = {
- .class_hid = BNXT_ULP_CLASS_HID_3858,
+ [1905] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0f6a,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 4UL,
@@ -27944,8 +42719,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC }
},
- [1296] = {
- .class_hid = BNXT_ULP_CLASS_HID_046c,
+ [1906] = {
+ .class_hid = BNXT_ULP_CLASS_HID_19ca,
.class_tid = 3,
.hdr_sig_id = 11,
.flow_sig_id = 68UL,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index 739c546d9e..9ad25dbdb6 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -1,66 +1,65 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 46
+#define BNXT_ULP_REGFILE_MAX_SZ 61
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
-#define BNXT_ULP_GEN_TBL_MAX_SZ 18
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 262144
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 1297
-#define BNXT_ULP_CLASS_HID_LOW_PRIME 6701
-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
-#define BNXT_ULP_CLASS_HID_SHFTR 28
+#define BNXT_ULP_GEN_TBL_MAX_SZ 36
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 1048576
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 1907
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 4049
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
+#define BNXT_ULP_CLASS_HID_SHFTR 29
#define BNXT_ULP_CLASS_HID_SHFTL 28
-#define BNXT_ULP_CLASS_HID_MASK 262143
-#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
+#define BNXT_ULP_CLASS_HID_MASK 1048575
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 32768
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 546
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
-#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
-#define BNXT_ULP_ACT_HID_SHFTR 27
-#define BNXT_ULP_ACT_HID_SHFTL 26
-#define BNXT_ULP_ACT_HID_MASK 2047
-#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 16
-#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 132
-#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 144
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 409
-#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 12
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 25
+#define BNXT_ULP_ACT_HID_SHFTL 27
+#define BNXT_ULP_ACT_HID_MASK 32767
+#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 46
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 537
+#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 187
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 970
+#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 25
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
#define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
-#define BNXT_ULP_HDR_SIG_ID_SHIFT 4
+#define BNXT_ULP_HDR_SIG_ID_SHIFT 5
+#define BNXT_ULP_APP_ID_CONFIG 0
#define BNXT_ULP_APP_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 13805
#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6
#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 606
#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26
#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 618
#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49
#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6
-#define ULP_THOR_CLASS_TBL_LIST_SIZE 116
-#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2323
+#define ULP_THOR_CLASS_TBL_LIST_SIZE 124
+#define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 2514
#define ULP_THOR_CLASS_IDENT_LIST_SIZE 38
-#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
-#define ULP_THOR_CLASS_COND_LIST_SIZE 54
-#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
+#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1517
+#define ULP_THOR_CLASS_COND_LIST_SIZE 55
+#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 11
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 46
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
-#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
-#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
-#define ULP_THOR_ACT_TBL_LIST_SIZE 36
-#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
-#define ULP_THOR_ACT_IDENT_LIST_SIZE 3
-#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 505
-#define ULP_THOR_ACT_COND_LIST_SIZE 27
+#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 616
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 65
+#define ULP_THOR_ACT_TMPL_LIST_SIZE 11
+#define ULP_THOR_ACT_TBL_LIST_SIZE 96
+#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 34
+#define ULP_THOR_ACT_IDENT_LIST_SIZE 19
+#define ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE 794
+#define ULP_THOR_ACT_COND_LIST_SIZE 75
enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_MARK = 0x0000000000000001,
@@ -90,7 +89,18 @@ enum bnxt_ulp_act_bit {
BNXT_ULP_ACT_BIT_SHARED = 0x0000000001000000,
BNXT_ULP_ACT_BIT_SAMPLE = 0x0000000002000000,
BNXT_ULP_ACT_BIT_SHARED_SAMPLE = 0x0000000004000000,
- BNXT_ULP_ACT_BIT_LAST = 0x0000000008000000
+ BNXT_ULP_ACT_BIT_QUEUE = 0x0000000008000000,
+ BNXT_ULP_ACT_BIT_DELETE = 0x0000000010000000,
+ BNXT_ULP_ACT_BIT_UPDATE = 0x0000000020000000,
+ BNXT_ULP_ACT_BIT_SHARED_METER = 0x0000000040000000,
+ BNXT_ULP_ACT_BIT_METER_PROFILE = 0x0000000080000000,
+ BNXT_ULP_ACT_BIT_GOTO_CHAIN = 0x0000000100000000,
+ BNXT_ULP_ACT_BIT_VF_TO_VF = 0x0000000200000000,
+ BNXT_ULP_ACT_BIT_IP_ENCAP = 0x0000000400000000,
+ BNXT_ULP_ACT_BIT_IP_DECAP = 0x0000000800000000,
+ BNXT_ULP_ACT_BIT_L2_ENCAP = 0x0000001000000000,
+ BNXT_ULP_ACT_BIT_L2_DECAP = 0x0000002000000000,
+ BNXT_ULP_ACT_BIT_LAST = 0x0000004000000000
};
enum bnxt_ulp_hdr_bit {
@@ -112,10 +122,13 @@ enum bnxt_ulp_hdr_bit {
BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000008000,
BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000,
- BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000,
- BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000,
- BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000100000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000
+ BNXT_ULP_HDR_BIT_O_ECPRI = 0x0000000000040000,
+ BNXT_ULP_HDR_BIT_O_ROE = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_F1 = 0x0000000000100000,
+ BNXT_ULP_HDR_BIT_F2 = 0x0000000000200000,
+ BNXT_ULP_HDR_BIT_SVIF_IGNORE = 0x0000000000400000,
+ BNXT_ULP_HDR_BIT_O_SRV6 = 0x0000000000800000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000001000000
};
enum bnxt_ulp_accept_opc {
@@ -141,11 +154,11 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_NOT_USED = 0,
BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 1,
BNXT_ULP_CF_IDX_O_VTAG_NUM = 2,
- BNXT_ULP_CF_IDX_O_NO_VTAG = 3,
+ BNXT_ULP_CF_IDX_O_HAS_VTAG = 3,
BNXT_ULP_CF_IDX_O_ONE_VTAG = 4,
BNXT_ULP_CF_IDX_O_TWO_VTAGS = 5,
BNXT_ULP_CF_IDX_I_VTAG_NUM = 6,
- BNXT_ULP_CF_IDX_I_NO_VTAG = 7,
+ BNXT_ULP_CF_IDX_I_HAS_VTAG = 7,
BNXT_ULP_CF_IDX_I_ONE_VTAG = 8,
BNXT_ULP_CF_IDX_I_TWO_VTAGS = 9,
BNXT_ULP_CF_IDX_INCOMING_IF = 10,
@@ -214,7 +227,17 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_II_VLAN_FB_VID = 73,
BNXT_ULP_CF_IDX_SOCKET_DIRECT = 74,
BNXT_ULP_CF_IDX_SOCKET_DIRECT_VPORT = 75,
- BNXT_ULP_CF_IDX_LAST = 76
+ BNXT_ULP_CF_IDX_TUNNEL_SPORT = 76,
+ BNXT_ULP_CF_IDX_VF_META_FID = 77,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID = 78,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE = 79,
+ BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE = 80,
+ BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED = 81,
+ BNXT_ULP_CF_IDX_CHAIN_ID_METADATA = 82,
+ BNXT_ULP_CF_IDX_SRV6_UPAR_ID = 83,
+ BNXT_ULP_CF_IDX_SRV6_T_ID = 84,
+ BNXT_ULP_CF_IDX_GENERIC_SIZE = 85,
+ BNXT_ULP_CF_IDX_LAST = 86
};
enum bnxt_ulp_cond_list_opc {
@@ -242,7 +265,9 @@ enum bnxt_ulp_cond_opc {
BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET = 13,
BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET = 14,
BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET = 15,
- BNXT_ULP_COND_OPC_LAST = 16
+ BNXT_ULP_COND_OPC_ACT_PROP_IS_SET = 16,
+ BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET = 17,
+ BNXT_ULP_COND_OPC_LAST = 18
};
enum bnxt_ulp_critical_resource {
@@ -297,15 +322,30 @@ enum bnxt_ulp_enc_field {
BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 = 23,
BNXT_ULP_ENC_FIELD_VXLAN_VNI = 24,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 = 25,
- BNXT_ULP_ENC_FIELD_LAST = 26
+ BNXT_ULP_ENC_FIELD_SRV6_NEXT_HDR = 26,
+ BNXT_ULP_ENC_FIELD_SRV6_HDR_LEN = 27,
+ BNXT_ULP_ENC_FIELD_SRV6_ROUTING_TYPE = 28,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LEFT = 29,
+ BNXT_ULP_ENC_FIELD_SRV6_LAST_ENTRY = 30,
+ BNXT_ULP_ENC_FIELD_SRV6_FLAGS = 31,
+ BNXT_ULP_ENC_FIELD_SRV6_TAG = 32,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST0 = 33,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST1 = 34,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST2 = 35,
+ BNXT_ULP_ENC_FIELD_SRV6_SEG_LIST3 = 36,
+ BNXT_ULP_ENC_FIELD_GENERIC_SIZE = 37,
+ BNXT_ULP_ENC_FIELD_GENERIC_RSVD = 38,
+ BNXT_ULP_ENC_FIELD_LAST = 39
};
enum bnxt_ulp_fdb_opc {
BNXT_ULP_FDB_OPC_PUSH_FID = 0,
BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE = 1,
BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE = 2,
- BNXT_ULP_FDB_OPC_NOP = 3,
- BNXT_ULP_FDB_OPC_LAST = 4
+ BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE = 3,
+ BNXT_ULP_FDB_OPC_CLEAR_RID_REGFILE = 4,
+ BNXT_ULP_FDB_OPC_NOP = 5,
+ BNXT_ULP_FDB_OPC_LAST = 6
};
enum bnxt_ulp_fdb_type {
@@ -364,7 +404,9 @@ enum bnxt_ulp_func_opc {
BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8,
BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9,
BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10,
- BNXT_ULP_FUNC_OPC_LAST = 11
+ BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_ALLOC = 11,
+ BNXT_ULP_FUNC_OPC_TUNNEL_DST_PORT_FREE = 12,
+ BNXT_ULP_FUNC_OPC_LAST = 13
};
enum bnxt_ulp_func_src {
@@ -391,71 +433,101 @@ enum bnxt_ulp_generic_tbl_opc {
enum bnxt_ulp_glb_rf_idx {
BNXT_ULP_GLB_RF_IDX_NOT_USED = 0,
BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID = 1,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 2,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 3,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 4,
- BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 5,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 6,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 7,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 8,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 9,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 10,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 11,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 12,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 13,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 14,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 15,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 16,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 17,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 18,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 19,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 20,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 21,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 22,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 23,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 24,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 25,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 26,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 27,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 28,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 29,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 30,
- BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 31,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 32,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 33,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 = 34,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 35,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 36,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 37,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 38,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 39,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 40,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 41,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 42,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 43,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 44,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 45,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 46,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 47,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 48,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 49,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 50,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 51,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 52,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 53,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 54,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 55,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 56,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 57,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 58,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 59,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 60,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 61,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 62,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 63,
- BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 64,
- BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 65,
- BNXT_ULP_GLB_RF_IDX_LAST = 66
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0 = 2,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1 = 3,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_2 = 4,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR = 5,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID = 6,
+ BNXT_ULP_GLB_RF_IDX_GLB_L2_CNTXT_ID_0 = 7,
+ BNXT_ULP_GLB_RF_IDX_GLB_L2_CNTXT_ID_1 = 8,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID = 9,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID = 10,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID = 11,
+ BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR = 12,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR = 13,
+ BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR = 14,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 = 15,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 = 16,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 = 17,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 = 18,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 = 19,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 = 20,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6 = 21,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7 = 22,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_8 = 23,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_9 = 24,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 = 25,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 = 26,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 = 27,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3 = 28,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 = 29,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_5 = 30,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_6 = 31,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_7 = 32,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_8 = 33,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0 = 34,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1 = 35,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2 = 36,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3 = 37,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4 = 38,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5 = 39,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6 = 40,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7 = 41,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_8 = 42,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_9 = 43,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0 = 44,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1 = 45,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2 = 46,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3 = 47,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4 = 48,
+ BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_5 = 49,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 = 50,
+ BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_1 = 51,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 = 52,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 = 53,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 = 54,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 = 55,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0 = 56,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1 = 57,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2 = 58,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3 = 59,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0 = 60,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1 = 61,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2 = 62,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3 = 63,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0 = 64,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_1 = 65,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0 = 66,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1 = 67,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2 = 68,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3 = 69,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4 = 70,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5 = 71,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6 = 72,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7 = 73,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8 = 74,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9 = 75,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10 = 76,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0 = 77,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_1 = 78,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0 = 79,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1 = 80,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2 = 81,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3 = 82,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4 = 83,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0 = 84,
+ BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1 = 85,
+ BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID = 86,
+ BNXT_ULP_GLB_RF_IDX_RECYCLE_PROF_FUNC_ID = 87,
+ BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_UPAR_ID = 88,
+ BNXT_ULP_GLB_RF_IDX_GLB_ECPRI_PROF_FUNC_ID = 89,
+ BNXT_ULP_GLB_RF_IDX_LAST = 90
+};
+
+enum bnxt_ulp_global_register_tbl_opc {
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_WR_REGFILE = 1,
+ BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_LAST = 2
};
enum bnxt_ulp_hdr_type {
@@ -482,7 +554,8 @@ enum bnxt_ulp_index_tbl_opc {
BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE = 4,
BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE = 5,
BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE = 6,
- BNXT_ULP_INDEX_TBL_OPC_LAST = 7
+ BNXT_ULP_INDEX_TBL_OPC_UPDATE_REGFILE = 7,
+ BNXT_ULP_INDEX_TBL_OPC_LAST = 8
};
enum bnxt_ulp_mark_db_opc {
@@ -516,14 +589,25 @@ enum bnxt_ulp_port_table {
BNXT_ULP_PORT_TABLE_PHY_PORT_SPIF = 14,
BNXT_ULP_PORT_TABLE_PHY_PORT_PARIF = 15,
BNXT_ULP_PORT_TABLE_PHY_PORT_VPORT = 16,
- BNXT_ULP_PORT_TABLE_LAST = 17
+ BNXT_ULP_PORT_TABLE_PORT_IS_PF = 17,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA = 18,
+ BNXT_ULP_PORT_TABLE_LAST = 19
};
enum bnxt_ulp_pri_opc {
BNXT_ULP_PRI_OPC_NOT_USED = 0,
BNXT_ULP_PRI_OPC_CONST = 1,
BNXT_ULP_PRI_OPC_APP_PRI = 2,
- BNXT_ULP_PRI_OPC_LAST = 3
+ BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST = 3,
+ BNXT_ULP_PRI_OPC_LAST = 4
+};
+
+enum bnxt_ulp_ref_cnt_opc {
+ BNXT_ULP_REF_CNT_OPC_DEFAULT = 0,
+ BNXT_ULP_REF_CNT_OPC_NOP = 1,
+ BNXT_ULP_REF_CNT_OPC_DEC = 2,
+ BNXT_ULP_REF_CNT_OPC_INC = 3,
+ BNXT_ULP_REF_CNT_OPC_LAST = 4
};
enum bnxt_ulp_rf_idx {
@@ -573,13 +657,22 @@ enum bnxt_ulp_rf_idx {
BNXT_ULP_RF_IDX_SOCK_DIR_PARIF = 43,
BNXT_ULP_RF_IDX_SOCK_DIR_ACT_PTR = 44,
BNXT_ULP_RF_IDX_SOCK_DIR_PARENT_MAC = 45,
- BNXT_ULP_RF_IDX_LAST = 46
-};
-
-enum bnxt_ulp_shared_session {
- BNXT_ULP_SHARED_SESSION_NO = 0,
- BNXT_ULP_SHARED_SESSION_YES = 1,
- BNXT_ULP_SHARED_SESSION_LAST = 2
+ BNXT_ULP_RF_IDX_RSS_VNIC = 46,
+ BNXT_ULP_RF_IDX_PORT_IS_PF = 47,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 = 48,
+ BNXT_ULP_RF_IDX_METER_PTR_0 = 49,
+ BNXT_ULP_RF_IDX_REF_CNT = 50,
+ BNXT_ULP_RF_IDX_RF_0 = 51,
+ BNXT_ULP_RF_IDX_RF_1 = 52,
+ BNXT_ULP_RF_IDX_RF_2 = 53,
+ BNXT_ULP_RF_IDX_RF_3 = 54,
+ BNXT_ULP_RF_IDX_RF_4 = 55,
+ BNXT_ULP_RF_IDX_RF_5 = 56,
+ BNXT_ULP_RF_IDX_RF_6 = 57,
+ BNXT_ULP_RF_IDX_RF_7 = 58,
+ BNXT_ULP_RF_IDX_VF_FUNC_METADATA = 59,
+ BNXT_ULP_RF_IDX_CHAIN_ID_METADATA = 60,
+ BNXT_ULP_RF_IDX_LAST = 61
};
enum bnxt_ulp_tcam_tbl_opc {
@@ -598,11 +691,22 @@ enum bnxt_ulp_template_type {
BNXT_ULP_TEMPLATE_TYPE_LAST = 2
};
+enum bnxt_ulp_vnic_tbl_opc {
+ BNXT_ULP_VNIC_TBL_OPC_NOT_USED = 0,
+ BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE = 1,
+ BNXT_ULP_VNIC_TBL_OPC_LAST = 2
+};
+
enum bnxt_ulp_app_cap {
BNXT_ULP_APP_CAP_SHARED_EN = 0x00000001,
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN = 0x00000002,
BNXT_ULP_APP_CAP_UNICAST_ONLY = 0x00000004,
- BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT = 0x00000008,
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT = 0x00000010,
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT = 0x00000020,
+ BNXT_ULP_APP_CAP_CUST_VXLAN = 0x00000040,
+ BNXT_ULP_APP_CAP_HA_DYNAMIC = 0x00000080,
+ BNXT_ULP_APP_CAP_SRV6 = 0x00000100
};
enum bnxt_ulp_fdb_resource_flags {
@@ -628,7 +732,9 @@ enum bnxt_ulp_resource_func {
BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,
BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,
- BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88
+ BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE = 0x88,
+ BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE = 0x89,
+ BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE = 0x8a
};
enum bnxt_ulp_resource_sub_type {
@@ -646,7 +752,30 @@ enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE = 6,
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE = 7,
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOCKET_DIRECT_CACHE = 8,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE = 9,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE = 10,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE = 11,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE = 12,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE = 13,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL = 14,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE = 15,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE = 16,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE = 17,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_RSS_PARAMS = 18,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI = 1
+};
+
+enum bnxt_ulp_session_type {
+ BNXT_ULP_SESSION_TYPE_DEFAULT = 0x00,
+ BNXT_ULP_SESSION_TYPE_SHARED = 0x01,
+ BNXT_ULP_SESSION_TYPE_SHARED_WC = 0x02,
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC = 0x04,
+ BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA = 0x08,
+ BNXT_ULP_SESSION_TYPE_LAST = 0x10
};
enum bnxt_ulp_act_prop_sz {
@@ -664,8 +793,8 @@ enum bnxt_ulp_act_prop_sz {
BNXT_ULP_ACT_PROP_SZ_MARK = 4,
BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
BNXT_ULP_ACT_PROP_SZ_METER = 4,
- BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
- BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 6,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 6,
BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN = 2,
BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP = 1,
BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID = 2,
@@ -696,6 +825,28 @@ enum bnxt_ulp_act_prop_sz {
BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL = 4,
BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN = 4,
BNXT_ULP_ACT_PROP_SZ_RSS_KEY = 40,
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM = 2,
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE = 32,
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR = 3,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR = 3,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS = 2,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698 = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBND = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBND = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBSM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBSM = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CF = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL_UPDATE = 1,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL = 1,
+ BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID = 2,
BNXT_ULP_ACT_PROP_SZ_LAST = 4
};
@@ -715,38 +866,60 @@ enum bnxt_ulp_act_prop_idx {
BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
BNXT_ULP_ACT_PROP_IDX_METER = 52,
BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
- BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
- BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 72,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 74,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 75,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 77,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 81,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 85,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 101,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 117,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 119,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 121,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 125,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 129,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 133,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 137,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 141,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 145,
- BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 149,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 153,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 159,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 165,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 173,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
- BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
- BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 261,
- BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 269,
- BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 277,
- BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 281,
- BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 285,
- BNXT_ULP_ACT_PROP_IDX_LAST = 325
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 62,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN = 68,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP = 70,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID = 71,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 73,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 77,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 81,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 97,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 113,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 115,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 117,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 121,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 125,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 129,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 133,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 137,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 141,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 145,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 149,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 155,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 161,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 169,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 201,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 217,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 221,
+ BNXT_ULP_ACT_PROP_IDX_JUMP = 253,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE = 257,
+ BNXT_ULP_ACT_PROP_IDX_RSS_TYPES = 265,
+ BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL = 273,
+ BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN = 277,
+ BNXT_ULP_ACT_PROP_IDX_RSS_KEY = 281,
+ BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM = 321,
+ BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE = 323,
+ BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX = 355,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE = 357,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID = 358,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR = 362,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR = 365,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS = 368,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS = 370,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 = 372,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM = 373,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND = 374,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND = 375,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM = 376,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM = 377,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF = 378,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID = 379,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE = 383,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN = 384,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE = 385,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL = 386,
+ BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID = 387,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 389
};
enum ulp_wp_sym {
@@ -905,6 +1078,11 @@ enum ulp_wp_sym {
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_NORMAL = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_FAST = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_FAST = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RFS_ACT = 0,
+ ULP_WP_SYM_EM_WM_OPCODE_OP_RECYCLE = 0,
ULP_WP_SYM_POP_VLAN_NO = 0,
ULP_WP_SYM_POP_VLAN_YES = 1,
ULP_WP_SYM_VLAN_DEL_RPT_DISABLED = 0,
@@ -980,7 +1158,15 @@ enum ulp_wp_sym {
ULP_WP_SYM_VF_FUNC_PARIF = 15,
ULP_WP_SYM_NO = 0,
ULP_WP_SYM_YES = 1,
- ULP_WP_SYM_RECYCLE_DST = 0x800
+ ULP_WP_SYM_RECYCLE_DST = 0x800,
+ ULP_WP_SYM_VF_2_VFR_META_VAL = 0,
+ ULP_WP_SYM_VF_2_VF_META_VAL = 0,
+ ULP_WP_SYM_VF_2_VFR_META_MASK = 0,
+ ULP_WP_SYM_META_PROFILE_0 = 0,
+ ULP_WP_SYM_CHAIN_META_VAL = 0,
+ ULP_WP_SYM_L2_ECPRI_ETYPE = 0,
+ ULP_WP_SYM_L4_ECPRI_ETYPE = 0,
+ ULP_WP_SYM_L2_ROE_ETYPE = 0
};
enum ulp_thor_sym {
@@ -1139,6 +1325,11 @@ enum ulp_thor_sym {
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
ULP_THOR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_NORMAL = 0,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_FAST = 1,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_FAST = 2,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RFS_ACT = 3,
+ ULP_THOR_SYM_EM_WM_OPCODE_OP_RECYCLE = 4,
ULP_THOR_SYM_POP_VLAN_NO = 0,
ULP_THOR_SYM_POP_VLAN_YES = 1,
ULP_THOR_SYM_VLAN_DEL_RPT_DISABLED = 0,
@@ -1214,1402 +1405,2472 @@ enum ulp_thor_sym {
ULP_THOR_SYM_VF_FUNC_PARIF = 15,
ULP_THOR_SYM_NO = 0,
ULP_THOR_SYM_YES = 1,
- ULP_THOR_SYM_RECYCLE_DST = 0x800
+ ULP_THOR_SYM_RECYCLE_DST = 1039,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL = 8192,
+ ULP_THOR_SYM_VF_2_VF_META_VAL = 4096,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK = 61440,
+ ULP_THOR_SYM_META_PROFILE_0 = 0,
+ ULP_THOR_SYM_CHAIN_META_VAL = 12288,
+ ULP_THOR_SYM_L2_ECPRI_ETYPE = 44798,
+ ULP_THOR_SYM_L4_ECPRI_ETYPE = 2048,
+ ULP_THOR_SYM_L2_ROE_ETYPE = 64573
};
enum bnxt_ulp_class_hid {
- BNXT_ULP_CLASS_HID_55dd = 0x55dd,
- BNXT_ULP_CLASS_HID_1df1 = 0x1df1,
- BNXT_ULP_CLASS_HID_3e55 = 0x3e55,
- BNXT_ULP_CLASS_HID_0649 = 0x0649,
- BNXT_ULP_CLASS_HID_1011 = 0x1011,
- BNXT_ULP_CLASS_HID_40e9 = 0x40e9,
- BNXT_ULP_CLASS_HID_3e99 = 0x3e99,
- BNXT_ULP_CLASS_HID_06ad = 0x06ad,
- BNXT_ULP_CLASS_HID_38c7 = 0x38c7,
- BNXT_ULP_CLASS_HID_00fb = 0x00fb,
- BNXT_ULP_CLASS_HID_24d3 = 0x24d3,
- BNXT_ULP_CLASS_HID_559b = 0x559b,
- BNXT_ULP_CLASS_HID_5003 = 0x5003,
- BNXT_ULP_CLASS_HID_1837 = 0x1837,
- BNXT_ULP_CLASS_HID_3bef = 0x3bef,
- BNXT_ULP_CLASS_HID_0403 = 0x0403,
- BNXT_ULP_CLASS_HID_3d3f = 0x3d3f,
- BNXT_ULP_CLASS_HID_0543 = 0x0543,
- BNXT_ULP_CLASS_HID_292b = 0x292b,
- BNXT_ULP_CLASS_HID_59e3 = 0x59e3,
- BNXT_ULP_CLASS_HID_5d3b = 0x5d3b,
- BNXT_ULP_CLASS_HID_254f = 0x254f,
- BNXT_ULP_CLASS_HID_4917 = 0x4917,
- BNXT_ULP_CLASS_HID_113b = 0x113b,
- BNXT_ULP_CLASS_HID_55fd = 0x55fd,
- BNXT_ULP_CLASS_HID_1dd1 = 0x1dd1,
- BNXT_ULP_CLASS_HID_3e75 = 0x3e75,
- BNXT_ULP_CLASS_HID_0669 = 0x0669,
- BNXT_ULP_CLASS_HID_1ba1 = 0x1ba1,
- BNXT_ULP_CLASS_HID_4c69 = 0x4c69,
- BNXT_ULP_CLASS_HID_0439 = 0x0439,
- BNXT_ULP_CLASS_HID_34e1 = 0x34e1,
- BNXT_ULP_CLASS_HID_0465 = 0x0465,
- BNXT_ULP_CLASS_HID_352d = 0x352d,
- BNXT_ULP_CLASS_HID_55b1 = 0x55b1,
- BNXT_ULP_CLASS_HID_1da5 = 0x1da5,
- BNXT_ULP_CLASS_HID_32fd = 0x32fd,
- BNXT_ULP_CLASS_HID_63a5 = 0x63a5,
- BNXT_ULP_CLASS_HID_1b75 = 0x1b75,
- BNXT_ULP_CLASS_HID_4c3d = 0x4c3d,
- BNXT_ULP_CLASS_HID_1031 = 0x1031,
- BNXT_ULP_CLASS_HID_40c9 = 0x40c9,
- BNXT_ULP_CLASS_HID_3eb9 = 0x3eb9,
- BNXT_ULP_CLASS_HID_068d = 0x068d,
- BNXT_ULP_CLASS_HID_5039 = 0x5039,
- BNXT_ULP_CLASS_HID_180d = 0x180d,
- BNXT_ULP_CLASS_HID_15fd = 0x15fd,
- BNXT_ULP_CLASS_HID_46b5 = 0x46b5,
- BNXT_ULP_CLASS_HID_303d = 0x303d,
- BNXT_ULP_CLASS_HID_60f5 = 0x60f5,
- BNXT_ULP_CLASS_HID_5ea5 = 0x5ea5,
- BNXT_ULP_CLASS_HID_2689 = 0x2689,
- BNXT_ULP_CLASS_HID_0771 = 0x0771,
- BNXT_ULP_CLASS_HID_3809 = 0x3809,
- BNXT_ULP_CLASS_HID_35f9 = 0x35f9,
- BNXT_ULP_CLASS_HID_66b1 = 0x66b1,
- BNXT_ULP_CLASS_HID_559d = 0x559d,
- BNXT_ULP_CLASS_HID_1db1 = 0x1db1,
- BNXT_ULP_CLASS_HID_3e15 = 0x3e15,
- BNXT_ULP_CLASS_HID_0609 = 0x0609,
- BNXT_ULP_CLASS_HID_1bc1 = 0x1bc1,
- BNXT_ULP_CLASS_HID_4c09 = 0x4c09,
- BNXT_ULP_CLASS_HID_0459 = 0x0459,
- BNXT_ULP_CLASS_HID_3481 = 0x3481,
- BNXT_ULP_CLASS_HID_0405 = 0x0405,
- BNXT_ULP_CLASS_HID_354d = 0x354d,
- BNXT_ULP_CLASS_HID_55d1 = 0x55d1,
- BNXT_ULP_CLASS_HID_1dc5 = 0x1dc5,
- BNXT_ULP_CLASS_HID_329d = 0x329d,
- BNXT_ULP_CLASS_HID_63c5 = 0x63c5,
- BNXT_ULP_CLASS_HID_1b15 = 0x1b15,
- BNXT_ULP_CLASS_HID_4c5d = 0x4c5d,
- BNXT_ULP_CLASS_HID_1051 = 0x1051,
- BNXT_ULP_CLASS_HID_40a9 = 0x40a9,
- BNXT_ULP_CLASS_HID_3ed9 = 0x3ed9,
- BNXT_ULP_CLASS_HID_06ed = 0x06ed,
- BNXT_ULP_CLASS_HID_5059 = 0x5059,
- BNXT_ULP_CLASS_HID_186d = 0x186d,
- BNXT_ULP_CLASS_HID_159d = 0x159d,
- BNXT_ULP_CLASS_HID_46d5 = 0x46d5,
- BNXT_ULP_CLASS_HID_305d = 0x305d,
- BNXT_ULP_CLASS_HID_6095 = 0x6095,
- BNXT_ULP_CLASS_HID_5ec5 = 0x5ec5,
- BNXT_ULP_CLASS_HID_26e9 = 0x26e9,
- BNXT_ULP_CLASS_HID_0711 = 0x0711,
- BNXT_ULP_CLASS_HID_3869 = 0x3869,
- BNXT_ULP_CLASS_HID_3599 = 0x3599,
- BNXT_ULP_CLASS_HID_66d1 = 0x66d1,
- BNXT_ULP_CLASS_HID_38e7 = 0x38e7,
- BNXT_ULP_CLASS_HID_00db = 0x00db,
- BNXT_ULP_CLASS_HID_24f3 = 0x24f3,
- BNXT_ULP_CLASS_HID_55bb = 0x55bb,
- BNXT_ULP_CLASS_HID_5023 = 0x5023,
- BNXT_ULP_CLASS_HID_1817 = 0x1817,
- BNXT_ULP_CLASS_HID_3bcf = 0x3bcf,
- BNXT_ULP_CLASS_HID_0423 = 0x0423,
- BNXT_ULP_CLASS_HID_58e3 = 0x58e3,
- BNXT_ULP_CLASS_HID_20d7 = 0x20d7,
- BNXT_ULP_CLASS_HID_448f = 0x448f,
- BNXT_ULP_CLASS_HID_0ce3 = 0x0ce3,
- BNXT_ULP_CLASS_HID_076b = 0x076b,
- BNXT_ULP_CLASS_HID_3813 = 0x3813,
- BNXT_ULP_CLASS_HID_5bcb = 0x5bcb,
- BNXT_ULP_CLASS_HID_243f = 0x243f,
- BNXT_ULP_CLASS_HID_144b = 0x144b,
- BNXT_ULP_CLASS_HID_4573 = 0x4573,
- BNXT_ULP_CLASS_HID_0057 = 0x0057,
- BNXT_ULP_CLASS_HID_311f = 0x311f,
- BNXT_ULP_CLASS_HID_2b87 = 0x2b87,
- BNXT_ULP_CLASS_HID_5c4f = 0x5c4f,
- BNXT_ULP_CLASS_HID_1793 = 0x1793,
- BNXT_ULP_CLASS_HID_485b = 0x485b,
- BNXT_ULP_CLASS_HID_3447 = 0x3447,
- BNXT_ULP_CLASS_HID_650f = 0x650f,
- BNXT_ULP_CLASS_HID_2053 = 0x2053,
- BNXT_ULP_CLASS_HID_511b = 0x511b,
- BNXT_ULP_CLASS_HID_4b83 = 0x4b83,
- BNXT_ULP_CLASS_HID_13f7 = 0x13f7,
- BNXT_ULP_CLASS_HID_37af = 0x37af,
- BNXT_ULP_CLASS_HID_6857 = 0x6857,
- BNXT_ULP_CLASS_HID_3d1f = 0x3d1f,
- BNXT_ULP_CLASS_HID_0563 = 0x0563,
- BNXT_ULP_CLASS_HID_290b = 0x290b,
- BNXT_ULP_CLASS_HID_59c3 = 0x59c3,
- BNXT_ULP_CLASS_HID_5d1b = 0x5d1b,
- BNXT_ULP_CLASS_HID_256f = 0x256f,
- BNXT_ULP_CLASS_HID_4937 = 0x4937,
- BNXT_ULP_CLASS_HID_111b = 0x111b,
- BNXT_ULP_CLASS_HID_25f4b = 0x25f4b,
- BNXT_ULP_CLASS_HID_2275f = 0x2275f,
- BNXT_ULP_CLASS_HID_24b67 = 0x24b67,
- BNXT_ULP_CLASS_HID_2134b = 0x2134b,
- BNXT_ULP_CLASS_HID_21683 = 0x21683,
- BNXT_ULP_CLASS_HID_2475b = 0x2475b,
- BNXT_ULP_CLASS_HID_202bf = 0x202bf,
- BNXT_ULP_CLASS_HID_23377 = 0x23377,
- BNXT_ULP_CLASS_HID_119db = 0x119db,
- BNXT_ULP_CLASS_HID_14a93 = 0x14a93,
- BNXT_ULP_CLASS_HID_105f7 = 0x105f7,
- BNXT_ULP_CLASS_HID_1368f = 0x1368f,
- BNXT_ULP_CLASS_HID_139c7 = 0x139c7,
- BNXT_ULP_CLASS_HID_1022b = 0x1022b,
- BNXT_ULP_CLASS_HID_125f3 = 0x125f3,
- BNXT_ULP_CLASS_HID_1568b = 0x1568b,
- BNXT_ULP_CLASS_HID_33c37 = 0x33c37,
- BNXT_ULP_CLASS_HID_3041b = 0x3041b,
- BNXT_ULP_CLASS_HID_32823 = 0x32823,
- BNXT_ULP_CLASS_HID_358fb = 0x358fb,
- BNXT_ULP_CLASS_HID_35c33 = 0x35c33,
- BNXT_ULP_CLASS_HID_32407 = 0x32407,
- BNXT_ULP_CLASS_HID_3482f = 0x3482f,
- BNXT_ULP_CLASS_HID_31033 = 0x31033,
- BNXT_ULP_CLASS_HID_3887 = 0x3887,
- BNXT_ULP_CLASS_HID_00bb = 0x00bb,
- BNXT_ULP_CLASS_HID_2493 = 0x2493,
- BNXT_ULP_CLASS_HID_55db = 0x55db,
- BNXT_ULP_CLASS_HID_5043 = 0x5043,
- BNXT_ULP_CLASS_HID_1877 = 0x1877,
- BNXT_ULP_CLASS_HID_3baf = 0x3baf,
- BNXT_ULP_CLASS_HID_0443 = 0x0443,
- BNXT_ULP_CLASS_HID_5883 = 0x5883,
- BNXT_ULP_CLASS_HID_20b7 = 0x20b7,
- BNXT_ULP_CLASS_HID_44ef = 0x44ef,
- BNXT_ULP_CLASS_HID_0c83 = 0x0c83,
- BNXT_ULP_CLASS_HID_070b = 0x070b,
- BNXT_ULP_CLASS_HID_3873 = 0x3873,
- BNXT_ULP_CLASS_HID_5bab = 0x5bab,
- BNXT_ULP_CLASS_HID_245f = 0x245f,
- BNXT_ULP_CLASS_HID_142b = 0x142b,
- BNXT_ULP_CLASS_HID_4513 = 0x4513,
- BNXT_ULP_CLASS_HID_0037 = 0x0037,
- BNXT_ULP_CLASS_HID_317f = 0x317f,
- BNXT_ULP_CLASS_HID_2be7 = 0x2be7,
- BNXT_ULP_CLASS_HID_5c2f = 0x5c2f,
- BNXT_ULP_CLASS_HID_17f3 = 0x17f3,
- BNXT_ULP_CLASS_HID_483b = 0x483b,
- BNXT_ULP_CLASS_HID_3427 = 0x3427,
- BNXT_ULP_CLASS_HID_656f = 0x656f,
- BNXT_ULP_CLASS_HID_2033 = 0x2033,
- BNXT_ULP_CLASS_HID_517b = 0x517b,
- BNXT_ULP_CLASS_HID_4be3 = 0x4be3,
- BNXT_ULP_CLASS_HID_1397 = 0x1397,
- BNXT_ULP_CLASS_HID_37cf = 0x37cf,
- BNXT_ULP_CLASS_HID_6837 = 0x6837,
- BNXT_ULP_CLASS_HID_3d7f = 0x3d7f,
- BNXT_ULP_CLASS_HID_0503 = 0x0503,
- BNXT_ULP_CLASS_HID_296b = 0x296b,
- BNXT_ULP_CLASS_HID_59a3 = 0x59a3,
- BNXT_ULP_CLASS_HID_5d7b = 0x5d7b,
- BNXT_ULP_CLASS_HID_250f = 0x250f,
- BNXT_ULP_CLASS_HID_4957 = 0x4957,
- BNXT_ULP_CLASS_HID_117b = 0x117b,
- BNXT_ULP_CLASS_HID_25f2b = 0x25f2b,
- BNXT_ULP_CLASS_HID_2273f = 0x2273f,
- BNXT_ULP_CLASS_HID_24b07 = 0x24b07,
- BNXT_ULP_CLASS_HID_2132b = 0x2132b,
- BNXT_ULP_CLASS_HID_216e3 = 0x216e3,
- BNXT_ULP_CLASS_HID_2473b = 0x2473b,
- BNXT_ULP_CLASS_HID_202df = 0x202df,
- BNXT_ULP_CLASS_HID_23317 = 0x23317,
- BNXT_ULP_CLASS_HID_119bb = 0x119bb,
- BNXT_ULP_CLASS_HID_14af3 = 0x14af3,
- BNXT_ULP_CLASS_HID_10597 = 0x10597,
- BNXT_ULP_CLASS_HID_136ef = 0x136ef,
- BNXT_ULP_CLASS_HID_139a7 = 0x139a7,
- BNXT_ULP_CLASS_HID_1024b = 0x1024b,
- BNXT_ULP_CLASS_HID_12593 = 0x12593,
- BNXT_ULP_CLASS_HID_156eb = 0x156eb,
- BNXT_ULP_CLASS_HID_33c57 = 0x33c57,
- BNXT_ULP_CLASS_HID_3047b = 0x3047b,
- BNXT_ULP_CLASS_HID_32843 = 0x32843,
- BNXT_ULP_CLASS_HID_3589b = 0x3589b,
- BNXT_ULP_CLASS_HID_35c53 = 0x35c53,
- BNXT_ULP_CLASS_HID_32467 = 0x32467,
- BNXT_ULP_CLASS_HID_3484f = 0x3484f,
- BNXT_ULP_CLASS_HID_31053 = 0x31053,
- BNXT_ULP_CLASS_HID_5ce1 = 0x5ce1,
- BNXT_ULP_CLASS_HID_4579 = 0x4579,
- BNXT_ULP_CLASS_HID_1735 = 0x1735,
- BNXT_ULP_CLASS_HID_45bd = 0x45bd,
- BNXT_ULP_CLASS_HID_3feb = 0x3feb,
- BNXT_ULP_CLASS_HID_2bf7 = 0x2bf7,
- BNXT_ULP_CLASS_HID_5727 = 0x5727,
- BNXT_ULP_CLASS_HID_4333 = 0x4333,
- BNXT_ULP_CLASS_HID_4453 = 0x4453,
- BNXT_ULP_CLASS_HID_304f = 0x304f,
- BNXT_ULP_CLASS_HID_645f = 0x645f,
- BNXT_ULP_CLASS_HID_504b = 0x504b,
- BNXT_ULP_CLASS_HID_5cc1 = 0x5cc1,
- BNXT_ULP_CLASS_HID_4559 = 0x4559,
- BNXT_ULP_CLASS_HID_2285 = 0x2285,
- BNXT_ULP_CLASS_HID_0b1d = 0x0b1d,
- BNXT_ULP_CLASS_HID_0b49 = 0x0b49,
- BNXT_ULP_CLASS_HID_5c95 = 0x5c95,
- BNXT_ULP_CLASS_HID_39c1 = 0x39c1,
- BNXT_ULP_CLASS_HID_2259 = 0x2259,
- BNXT_ULP_CLASS_HID_1715 = 0x1715,
- BNXT_ULP_CLASS_HID_459d = 0x459d,
- BNXT_ULP_CLASS_HID_571d = 0x571d,
- BNXT_ULP_CLASS_HID_1cd1 = 0x1cd1,
- BNXT_ULP_CLASS_HID_3711 = 0x3711,
- BNXT_ULP_CLASS_HID_6599 = 0x6599,
- BNXT_ULP_CLASS_HID_0e55 = 0x0e55,
- BNXT_ULP_CLASS_HID_3cdd = 0x3cdd,
- BNXT_ULP_CLASS_HID_5ca1 = 0x5ca1,
- BNXT_ULP_CLASS_HID_4539 = 0x4539,
- BNXT_ULP_CLASS_HID_22e5 = 0x22e5,
- BNXT_ULP_CLASS_HID_0b7d = 0x0b7d,
- BNXT_ULP_CLASS_HID_0b29 = 0x0b29,
- BNXT_ULP_CLASS_HID_5cf5 = 0x5cf5,
- BNXT_ULP_CLASS_HID_39a1 = 0x39a1,
- BNXT_ULP_CLASS_HID_2239 = 0x2239,
- BNXT_ULP_CLASS_HID_1775 = 0x1775,
- BNXT_ULP_CLASS_HID_45fd = 0x45fd,
- BNXT_ULP_CLASS_HID_577d = 0x577d,
- BNXT_ULP_CLASS_HID_1cb1 = 0x1cb1,
- BNXT_ULP_CLASS_HID_3771 = 0x3771,
- BNXT_ULP_CLASS_HID_65f9 = 0x65f9,
- BNXT_ULP_CLASS_HID_0e35 = 0x0e35,
- BNXT_ULP_CLASS_HID_3cbd = 0x3cbd,
- BNXT_ULP_CLASS_HID_3fcb = 0x3fcb,
- BNXT_ULP_CLASS_HID_2bd7 = 0x2bd7,
- BNXT_ULP_CLASS_HID_5707 = 0x5707,
- BNXT_ULP_CLASS_HID_4313 = 0x4313,
- BNXT_ULP_CLASS_HID_5fc7 = 0x5fc7,
- BNXT_ULP_CLASS_HID_4bd3 = 0x4bd3,
- BNXT_ULP_CLASS_HID_0e4f = 0x0e4f,
- BNXT_ULP_CLASS_HID_632f = 0x632f,
- BNXT_ULP_CLASS_HID_1baf = 0x1baf,
- BNXT_ULP_CLASS_HID_07bb = 0x07bb,
- BNXT_ULP_CLASS_HID_32eb = 0x32eb,
- BNXT_ULP_CLASS_HID_1ef7 = 0x1ef7,
- BNXT_ULP_CLASS_HID_3bab = 0x3bab,
- BNXT_ULP_CLASS_HID_27b7 = 0x27b7,
- BNXT_ULP_CLASS_HID_52e7 = 0x52e7,
- BNXT_ULP_CLASS_HID_3ef3 = 0x3ef3,
- BNXT_ULP_CLASS_HID_4473 = 0x4473,
- BNXT_ULP_CLASS_HID_306f = 0x306f,
- BNXT_ULP_CLASS_HID_647f = 0x647f,
- BNXT_ULP_CLASS_HID_506b = 0x506b,
- BNXT_ULP_CLASS_HID_266af = 0x266af,
- BNXT_ULP_CLASS_HID_2525b = 0x2525b,
- BNXT_ULP_CLASS_HID_21de7 = 0x21de7,
- BNXT_ULP_CLASS_HID_20993 = 0x20993,
- BNXT_ULP_CLASS_HID_1213f = 0x1213f,
- BNXT_ULP_CLASS_HID_10d2b = 0x10d2b,
- BNXT_ULP_CLASS_HID_1413b = 0x1413b,
- BNXT_ULP_CLASS_HID_12cd7 = 0x12cd7,
- BNXT_ULP_CLASS_HID_3436b = 0x3436b,
- BNXT_ULP_CLASS_HID_32f07 = 0x32f07,
- BNXT_ULP_CLASS_HID_36317 = 0x36317,
- BNXT_ULP_CLASS_HID_34f03 = 0x34f03,
- BNXT_ULP_CLASS_HID_3fab = 0x3fab,
- BNXT_ULP_CLASS_HID_2bb7 = 0x2bb7,
- BNXT_ULP_CLASS_HID_5767 = 0x5767,
- BNXT_ULP_CLASS_HID_4373 = 0x4373,
- BNXT_ULP_CLASS_HID_5fa7 = 0x5fa7,
- BNXT_ULP_CLASS_HID_4bb3 = 0x4bb3,
- BNXT_ULP_CLASS_HID_0e2f = 0x0e2f,
- BNXT_ULP_CLASS_HID_634f = 0x634f,
- BNXT_ULP_CLASS_HID_1bcf = 0x1bcf,
- BNXT_ULP_CLASS_HID_07db = 0x07db,
- BNXT_ULP_CLASS_HID_328b = 0x328b,
- BNXT_ULP_CLASS_HID_1e97 = 0x1e97,
- BNXT_ULP_CLASS_HID_3bcb = 0x3bcb,
- BNXT_ULP_CLASS_HID_27d7 = 0x27d7,
- BNXT_ULP_CLASS_HID_5287 = 0x5287,
- BNXT_ULP_CLASS_HID_3e93 = 0x3e93,
- BNXT_ULP_CLASS_HID_4413 = 0x4413,
- BNXT_ULP_CLASS_HID_300f = 0x300f,
- BNXT_ULP_CLASS_HID_641f = 0x641f,
- BNXT_ULP_CLASS_HID_500b = 0x500b,
- BNXT_ULP_CLASS_HID_266cf = 0x266cf,
- BNXT_ULP_CLASS_HID_2523b = 0x2523b,
- BNXT_ULP_CLASS_HID_21d87 = 0x21d87,
- BNXT_ULP_CLASS_HID_209f3 = 0x209f3,
- BNXT_ULP_CLASS_HID_1215f = 0x1215f,
- BNXT_ULP_CLASS_HID_10d4b = 0x10d4b,
- BNXT_ULP_CLASS_HID_1415b = 0x1415b,
- BNXT_ULP_CLASS_HID_12cb7 = 0x12cb7,
- BNXT_ULP_CLASS_HID_3430b = 0x3430b,
- BNXT_ULP_CLASS_HID_32f67 = 0x32f67,
- BNXT_ULP_CLASS_HID_36377 = 0x36377,
- BNXT_ULP_CLASS_HID_34f63 = 0x34f63,
- BNXT_ULP_CLASS_HID_29b5 = 0x29b5,
- BNXT_ULP_CLASS_HID_29ad = 0x29ad,
- BNXT_ULP_CLASS_HID_29b7 = 0x29b7,
- BNXT_ULP_CLASS_HID_1583 = 0x1583,
- BNXT_ULP_CLASS_HID_29af = 0x29af,
- BNXT_ULP_CLASS_HID_159b = 0x159b,
- BNXT_ULP_CLASS_HID_2995 = 0x2995,
- BNXT_ULP_CLASS_HID_298d = 0x298d,
- BNXT_ULP_CLASS_HID_29f5 = 0x29f5,
- BNXT_ULP_CLASS_HID_29ed = 0x29ed,
- BNXT_ULP_CLASS_HID_2997 = 0x2997,
- BNXT_ULP_CLASS_HID_15a3 = 0x15a3,
- BNXT_ULP_CLASS_HID_298f = 0x298f,
- BNXT_ULP_CLASS_HID_15bb = 0x15bb,
- BNXT_ULP_CLASS_HID_29f7 = 0x29f7,
- BNXT_ULP_CLASS_HID_15c3 = 0x15c3,
- BNXT_ULP_CLASS_HID_29ef = 0x29ef,
- BNXT_ULP_CLASS_HID_15db = 0x15db,
- BNXT_ULP_CLASS_HID_1151 = 0x1151,
- BNXT_ULP_CLASS_HID_315d = 0x315d,
- BNXT_ULP_CLASS_HID_3612 = 0x3612,
- BNXT_ULP_CLASS_HID_66da = 0x66da,
- BNXT_ULP_CLASS_HID_243ca = 0x243ca,
- BNXT_ULP_CLASS_HID_20d8e = 0x20d8e,
- BNXT_ULP_CLASS_HID_2e082 = 0x2e082,
- BNXT_ULP_CLASS_HID_2ab46 = 0x2ab46,
- BNXT_ULP_CLASS_HID_25226 = 0x25226,
- BNXT_ULP_CLASS_HID_25cea = 0x25cea,
- BNXT_ULP_CLASS_HID_2c82a = 0x2c82a,
- BNXT_ULP_CLASS_HID_2f9a2 = 0x2f9a2,
- BNXT_ULP_CLASS_HID_23b56 = 0x23b56,
- BNXT_ULP_CLASS_HID_205da = 0x205da,
- BNXT_ULP_CLASS_HID_2d8ce = 0x2d8ce,
- BNXT_ULP_CLASS_HID_2a2d2 = 0x2a2d2,
- BNXT_ULP_CLASS_HID_24a72 = 0x24a72,
- BNXT_ULP_CLASS_HID_25476 = 0x25476,
- BNXT_ULP_CLASS_HID_2c076 = 0x2c076,
- BNXT_ULP_CLASS_HID_2f1ee = 0x2f1ee,
- BNXT_ULP_CLASS_HID_20bb6 = 0x20bb6,
- BNXT_ULP_CLASS_HID_23d2e = 0x23d2e,
- BNXT_ULP_CLASS_HID_2a96e = 0x2a96e,
- BNXT_ULP_CLASS_HID_2dae6 = 0x2dae6,
- BNXT_ULP_CLASS_HID_25af2 = 0x25af2,
- BNXT_ULP_CLASS_HID_24c6a = 0x24c6a,
- BNXT_ULP_CLASS_HID_2c7aa = 0x2c7aa,
- BNXT_ULP_CLASS_HID_2c26e = 0x2c26e,
- BNXT_ULP_CLASS_HID_203e2 = 0x203e2,
- BNXT_ULP_CLASS_HID_2357a = 0x2357a,
- BNXT_ULP_CLASS_HID_2a0fa = 0x2a0fa,
- BNXT_ULP_CLASS_HID_2d272 = 0x2d272,
- BNXT_ULP_CLASS_HID_2527e = 0x2527e,
- BNXT_ULP_CLASS_HID_243f6 = 0x243f6,
- BNXT_ULP_CLASS_HID_2fff6 = 0x2fff6,
- BNXT_ULP_CLASS_HID_2e16e = 0x2e16e,
- BNXT_ULP_CLASS_HID_2422d = 0x2422d,
- BNXT_ULP_CLASS_HID_20c69 = 0x20c69,
- BNXT_ULP_CLASS_HID_2e165 = 0x2e165,
- BNXT_ULP_CLASS_HID_2aaa1 = 0x2aaa1,
- BNXT_ULP_CLASS_HID_253c1 = 0x253c1,
- BNXT_ULP_CLASS_HID_25d0d = 0x25d0d,
- BNXT_ULP_CLASS_HID_2c9cd = 0x2c9cd,
- BNXT_ULP_CLASS_HID_2f845 = 0x2f845,
- BNXT_ULP_CLASS_HID_25afd = 0x25afd,
- BNXT_ULP_CLASS_HID_22439 = 0x22439,
- BNXT_ULP_CLASS_HID_290f9 = 0x290f9,
- BNXT_ULP_CLASS_HID_2c371 = 0x2c371,
- BNXT_ULP_CLASS_HID_24355 = 0x24355,
- BNXT_ULP_CLASS_HID_275dd = 0x275dd,
- BNXT_ULP_CLASS_HID_2e19d = 0x2e19d,
- BNXT_ULP_CLASS_HID_2d015 = 0x2d015,
- BNXT_ULP_CLASS_HID_2560d = 0x2560d,
- BNXT_ULP_CLASS_HID_21049 = 0x21049,
- BNXT_ULP_CLASS_HID_28c09 = 0x28c09,
- BNXT_ULP_CLASS_HID_2be89 = 0x2be89,
- BNXT_ULP_CLASS_HID_267a9 = 0x267a9,
- BNXT_ULP_CLASS_HID_261ed = 0x261ed,
- BNXT_ULP_CLASS_HID_2ddad = 0x2ddad,
- BNXT_ULP_CLASS_HID_2cc2d = 0x2cc2d,
- BNXT_ULP_CLASS_HID_26edd = 0x26edd,
- BNXT_ULP_CLASS_HID_22819 = 0x22819,
- BNXT_ULP_CLASS_HID_2a4d9 = 0x2a4d9,
- BNXT_ULP_CLASS_HID_2d759 = 0x2d759,
- BNXT_ULP_CLASS_HID_2573d = 0x2573d,
- BNXT_ULP_CLASS_HID_279bd = 0x279bd,
- BNXT_ULP_CLASS_HID_2f27d = 0x2f27d,
- BNXT_ULP_CLASS_HID_2e4fd = 0x2e4fd,
- BNXT_ULP_CLASS_HID_24fbe = 0x24fbe,
- BNXT_ULP_CLASS_HID_201fa = 0x201fa,
- BNXT_ULP_CLASS_HID_2ecf6 = 0x2ecf6,
- BNXT_ULP_CLASS_HID_2a732 = 0x2a732,
- BNXT_ULP_CLASS_HID_25e52 = 0x25e52,
- BNXT_ULP_CLASS_HID_2509e = 0x2509e,
- BNXT_ULP_CLASS_HID_2c45e = 0x2c45e,
- BNXT_ULP_CLASS_HID_2f5d6 = 0x2f5d6,
- BNXT_ULP_CLASS_HID_23722 = 0x23722,
- BNXT_ULP_CLASS_HID_209ae = 0x209ae,
- BNXT_ULP_CLASS_HID_2d4ba = 0x2d4ba,
- BNXT_ULP_CLASS_HID_2aea6 = 0x2aea6,
- BNXT_ULP_CLASS_HID_24606 = 0x24606,
- BNXT_ULP_CLASS_HID_25802 = 0x25802,
- BNXT_ULP_CLASS_HID_2cc02 = 0x2cc02,
- BNXT_ULP_CLASS_HID_2fd9a = 0x2fd9a,
- BNXT_ULP_CLASS_HID_207c2 = 0x207c2,
- BNXT_ULP_CLASS_HID_2315a = 0x2315a,
- BNXT_ULP_CLASS_HID_2a51a = 0x2a51a,
- BNXT_ULP_CLASS_HID_2d692 = 0x2d692,
- BNXT_ULP_CLASS_HID_25686 = 0x25686,
- BNXT_ULP_CLASS_HID_2401e = 0x2401e,
- BNXT_ULP_CLASS_HID_2cbde = 0x2cbde,
- BNXT_ULP_CLASS_HID_2ce1a = 0x2ce1a,
- BNXT_ULP_CLASS_HID_20f96 = 0x20f96,
- BNXT_ULP_CLASS_HID_2390e = 0x2390e,
- BNXT_ULP_CLASS_HID_2ac8e = 0x2ac8e,
- BNXT_ULP_CLASS_HID_2de06 = 0x2de06,
- BNXT_ULP_CLASS_HID_25e0a = 0x25e0a,
- BNXT_ULP_CLASS_HID_24f82 = 0x24f82,
- BNXT_ULP_CLASS_HID_2f382 = 0x2f382,
- BNXT_ULP_CLASS_HID_2ed1a = 0x2ed1a,
- BNXT_ULP_CLASS_HID_2576e = 0x2576e,
- BNXT_ULP_CLASS_HID_229aa = 0x229aa,
- BNXT_ULP_CLASS_HID_29d6a = 0x29d6a,
- BNXT_ULP_CLASS_HID_2cee2 = 0x2cee2,
- BNXT_ULP_CLASS_HID_24ec6 = 0x24ec6,
- BNXT_ULP_CLASS_HID_2784e = 0x2784e,
- BNXT_ULP_CLASS_HID_2ec0e = 0x2ec0e,
- BNXT_ULP_CLASS_HID_2dd86 = 0x2dd86,
- BNXT_ULP_CLASS_HID_25f22 = 0x25f22,
- BNXT_ULP_CLASS_HID_2112e = 0x2112e,
- BNXT_ULP_CLASS_HID_2852e = 0x2852e,
- BNXT_ULP_CLASS_HID_2b6a6 = 0x2b6a6,
- BNXT_ULP_CLASS_HID_26d86 = 0x26d86,
- BNXT_ULP_CLASS_HID_26002 = 0x26002,
- BNXT_ULP_CLASS_HID_2eb82 = 0x2eb82,
- BNXT_ULP_CLASS_HID_2c50a = 0x2c50a,
- BNXT_ULP_CLASS_HID_22f82 = 0x22f82,
- BNXT_ULP_CLASS_HID_2590a = 0x2590a,
- BNXT_ULP_CLASS_HID_2ccca = 0x2ccca,
- BNXT_ULP_CLASS_HID_28706 = 0x28706,
- BNXT_ULP_CLASS_HID_27e46 = 0x27e46,
- BNXT_ULP_CLASS_HID_26fce = 0x26fce,
- BNXT_ULP_CLASS_HID_2d38e = 0x2d38e,
- BNXT_ULP_CLASS_HID_2d5ca = 0x2d5ca,
- BNXT_ULP_CLASS_HID_21706 = 0x21706,
- BNXT_ULP_CLASS_HID_2408e = 0x2408e,
- BNXT_ULP_CLASS_HID_2b48e = 0x2b48e,
- BNXT_ULP_CLASS_HID_28e8a = 0x28e8a,
- BNXT_ULP_CLASS_HID_2660a = 0x2660a,
- BNXT_ULP_CLASS_HID_25782 = 0x25782,
- BNXT_ULP_CLASS_HID_2db02 = 0x2db02,
- BNXT_ULP_CLASS_HID_2dd8e = 0x2dd8e,
- BNXT_ULP_CLASS_HID_25b9e = 0x25b9e,
- BNXT_ULP_CLASS_HID_21dda = 0x21dda,
- BNXT_ULP_CLASS_HID_2819a = 0x2819a,
- BNXT_ULP_CLASS_HID_2b31a = 0x2b31a,
- BNXT_ULP_CLASS_HID_26a3a = 0x26a3a,
- BNXT_ULP_CLASS_HID_26c7e = 0x26c7e,
- BNXT_ULP_CLASS_HID_2d03e = 0x2d03e,
- BNXT_ULP_CLASS_HID_2c1be = 0x2c1be,
- BNXT_ULP_CLASS_HID_2430a = 0x2430a,
- BNXT_ULP_CLASS_HID_2058e = 0x2058e,
- BNXT_ULP_CLASS_HID_2890e = 0x2890e,
- BNXT_ULP_CLASS_HID_2ba8e = 0x2ba8e,
- BNXT_ULP_CLASS_HID_251ae = 0x251ae,
- BNXT_ULP_CLASS_HID_2542a = 0x2542a,
- BNXT_ULP_CLASS_HID_2dfaa = 0x2dfaa,
- BNXT_ULP_CLASS_HID_2c93a = 0x2c93a,
- BNXT_ULP_CLASS_HID_213ca = 0x213ca,
- BNXT_ULP_CLASS_HID_24d5a = 0x24d5a,
- BNXT_ULP_CLASS_HID_2b11a = 0x2b11a,
- BNXT_ULP_CLASS_HID_28b4e = 0x28b4e,
- BNXT_ULP_CLASS_HID_2624e = 0x2624e,
- BNXT_ULP_CLASS_HID_253de = 0x253de,
- BNXT_ULP_CLASS_HID_2c79e = 0x2c79e,
- BNXT_ULP_CLASS_HID_2d9da = 0x2d9da,
- BNXT_ULP_CLASS_HID_21b1e = 0x21b1e,
- BNXT_ULP_CLASS_HID_2350e = 0x2350e,
- BNXT_ULP_CLASS_HID_2b88e = 0x2b88e,
- BNXT_ULP_CLASS_HID_2ea0e = 0x2ea0e,
- BNXT_ULP_CLASS_HID_26a0a = 0x26a0a,
- BNXT_ULP_CLASS_HID_25b8a = 0x25b8a,
- BNXT_ULP_CLASS_HID_2cf0a = 0x2cf0a,
- BNXT_ULP_CLASS_HID_2c18e = 0x2c18e,
- BNXT_ULP_CLASS_HID_2634e = 0x2634e,
- BNXT_ULP_CLASS_HID_2258a = 0x2258a,
- BNXT_ULP_CLASS_HID_2a94a = 0x2a94a,
- BNXT_ULP_CLASS_HID_2daca = 0x2daca,
- BNXT_ULP_CLASS_HID_25aae = 0x25aae,
- BNXT_ULP_CLASS_HID_2742e = 0x2742e,
- BNXT_ULP_CLASS_HID_2ffee = 0x2ffee,
- BNXT_ULP_CLASS_HID_2e96e = 0x2e96e,
- BNXT_ULP_CLASS_HID_26b0a = 0x26b0a,
- BNXT_ULP_CLASS_HID_22d0e = 0x22d0e,
- BNXT_ULP_CLASS_HID_2910e = 0x2910e,
- BNXT_ULP_CLASS_HID_2c28e = 0x2c28e,
- BNXT_ULP_CLASS_HID_2422a = 0x2422a,
- BNXT_ULP_CLASS_HID_273aa = 0x273aa,
- BNXT_ULP_CLASS_HID_2e7aa = 0x2e7aa,
- BNXT_ULP_CLASS_HID_2d12a = 0x2d12a,
- BNXT_ULP_CLASS_HID_23b8a = 0x23b8a,
- BNXT_ULP_CLASS_HID_2550a = 0x2550a,
- BNXT_ULP_CLASS_HID_2d8ca = 0x2d8ca,
- BNXT_ULP_CLASS_HID_2930e = 0x2930e,
- BNXT_ULP_CLASS_HID_24a0e = 0x24a0e,
- BNXT_ULP_CLASS_HID_24c4a = 0x24c4a,
- BNXT_ULP_CLASS_HID_2ef4e = 0x2ef4e,
- BNXT_ULP_CLASS_HID_2e18a = 0x2e18a,
- BNXT_ULP_CLASS_HID_2230e = 0x2230e,
- BNXT_ULP_CLASS_HID_25c8e = 0x25c8e,
- BNXT_ULP_CLASS_HID_2c08e = 0x2c08e,
- BNXT_ULP_CLASS_HID_29a8a = 0x29a8a,
- BNXT_ULP_CLASS_HID_2718a = 0x2718a,
- BNXT_ULP_CLASS_HID_2630a = 0x2630a,
- BNXT_ULP_CLASS_HID_2d70a = 0x2d70a,
- BNXT_ULP_CLASS_HID_2e90e = 0x2e90e,
- BNXT_ULP_CLASS_HID_24e91 = 0x24e91,
- BNXT_ULP_CLASS_HID_200d5 = 0x200d5,
- BNXT_ULP_CLASS_HID_2edd9 = 0x2edd9,
- BNXT_ULP_CLASS_HID_2a61d = 0x2a61d,
- BNXT_ULP_CLASS_HID_25f7d = 0x25f7d,
- BNXT_ULP_CLASS_HID_251b1 = 0x251b1,
- BNXT_ULP_CLASS_HID_2c571 = 0x2c571,
- BNXT_ULP_CLASS_HID_2f4f9 = 0x2f4f9,
- BNXT_ULP_CLASS_HID_25641 = 0x25641,
- BNXT_ULP_CLASS_HID_22885 = 0x22885,
- BNXT_ULP_CLASS_HID_29c45 = 0x29c45,
- BNXT_ULP_CLASS_HID_2cfcd = 0x2cfcd,
- BNXT_ULP_CLASS_HID_24fe9 = 0x24fe9,
- BNXT_ULP_CLASS_HID_27961 = 0x27961,
- BNXT_ULP_CLASS_HID_2ed21 = 0x2ed21,
- BNXT_ULP_CLASS_HID_2dca9 = 0x2dca9,
- BNXT_ULP_CLASS_HID_25ab1 = 0x25ab1,
- BNXT_ULP_CLASS_HID_21cf5 = 0x21cf5,
- BNXT_ULP_CLASS_HID_280b5 = 0x280b5,
- BNXT_ULP_CLASS_HID_2b235 = 0x2b235,
- BNXT_ULP_CLASS_HID_26b15 = 0x26b15,
- BNXT_ULP_CLASS_HID_26d51 = 0x26d51,
- BNXT_ULP_CLASS_HID_2d111 = 0x2d111,
- BNXT_ULP_CLASS_HID_2c091 = 0x2c091,
- BNXT_ULP_CLASS_HID_26261 = 0x26261,
- BNXT_ULP_CLASS_HID_224a5 = 0x224a5,
- BNXT_ULP_CLASS_HID_2a865 = 0x2a865,
- BNXT_ULP_CLASS_HID_2dbe5 = 0x2dbe5,
- BNXT_ULP_CLASS_HID_25b81 = 0x25b81,
- BNXT_ULP_CLASS_HID_27501 = 0x27501,
- BNXT_ULP_CLASS_HID_2fec1 = 0x2fec1,
- BNXT_ULP_CLASS_HID_2e841 = 0x2e841,
- BNXT_ULP_CLASS_HID_24085 = 0x24085,
- BNXT_ULP_CLASS_HID_21ac5 = 0x21ac5,
- BNXT_ULP_CLASS_HID_28e85 = 0x28e85,
- BNXT_ULP_CLASS_HID_2b80d = 0x2b80d,
- BNXT_ULP_CLASS_HID_2516d = 0x2516d,
- BNXT_ULP_CLASS_HID_26ba5 = 0x26ba5,
- BNXT_ULP_CLASS_HID_2df65 = 0x2df65,
- BNXT_ULP_CLASS_HID_2ceed = 0x2ceed,
- BNXT_ULP_CLASS_HID_26845 = 0x26845,
- BNXT_ULP_CLASS_HID_22285 = 0x22285,
- BNXT_ULP_CLASS_HID_29645 = 0x29645,
- BNXT_ULP_CLASS_HID_2c1cd = 0x2c1cd,
- BNXT_ULP_CLASS_HID_2418d = 0x2418d,
- BNXT_ULP_CLASS_HID_27365 = 0x27365,
- BNXT_ULP_CLASS_HID_2e725 = 0x2e725,
- BNXT_ULP_CLASS_HID_2d6ad = 0x2d6ad,
- BNXT_ULP_CLASS_HID_25ca5 = 0x25ca5,
- BNXT_ULP_CLASS_HID_216e5 = 0x216e5,
- BNXT_ULP_CLASS_HID_29aa5 = 0x29aa5,
- BNXT_ULP_CLASS_HID_2b425 = 0x2b425,
- BNXT_ULP_CLASS_HID_26d05 = 0x26d05,
- BNXT_ULP_CLASS_HID_26745 = 0x26745,
- BNXT_ULP_CLASS_HID_2eb05 = 0x2eb05,
- BNXT_ULP_CLASS_HID_2da85 = 0x2da85,
- BNXT_ULP_CLASS_HID_20cc5 = 0x20cc5,
- BNXT_ULP_CLASS_HID_23ea5 = 0x23ea5,
- BNXT_ULP_CLASS_HID_2a265 = 0x2a265,
- BNXT_ULP_CLASS_HID_2dde5 = 0x2dde5,
- BNXT_ULP_CLASS_HID_25da5 = 0x25da5,
- BNXT_ULP_CLASS_HID_24f05 = 0x24f05,
- BNXT_ULP_CLASS_HID_2f0c5 = 0x2f0c5,
- BNXT_ULP_CLASS_HID_2e245 = 0x2e245,
- BNXT_ULP_CLASS_HID_24d8b = 0x24d8b,
- BNXT_ULP_CLASS_HID_207cf = 0x207cf,
- BNXT_ULP_CLASS_HID_28b8f = 0x28b8f,
- BNXT_ULP_CLASS_HID_2a517 = 0x2a517,
- BNXT_ULP_CLASS_HID_25277 = 0x25277,
- BNXT_ULP_CLASS_HID_254ab = 0x254ab,
- BNXT_ULP_CLASS_HID_2d86b = 0x2d86b,
- BNXT_ULP_CLASS_HID_2cbf3 = 0x2cbf3,
- BNXT_ULP_CLASS_HID_2554b = 0x2554b,
- BNXT_ULP_CLASS_HID_22f8f = 0x22f8f,
- BNXT_ULP_CLASS_HID_2934f = 0x2934f,
- BNXT_ULP_CLASS_HID_2c2c7 = 0x2c2c7,
- BNXT_ULP_CLASS_HID_242e3 = 0x242e3,
- BNXT_ULP_CLASS_HID_27c6b = 0x27c6b,
- BNXT_ULP_CLASS_HID_2e02b = 0x2e02b,
- BNXT_ULP_CLASS_HID_2d3a3 = 0x2d3a3,
- BNXT_ULP_CLASS_HID_259a3 = 0x259a3,
- BNXT_ULP_CLASS_HID_213e7 = 0x213e7,
- BNXT_ULP_CLASS_HID_287a7 = 0x287a7,
- BNXT_ULP_CLASS_HID_2b137 = 0x2b137,
- BNXT_ULP_CLASS_HID_26e17 = 0x26e17,
- BNXT_ULP_CLASS_HID_26043 = 0x26043,
- BNXT_ULP_CLASS_HID_2d403 = 0x2d403,
- BNXT_ULP_CLASS_HID_2c793 = 0x2c793,
- BNXT_ULP_CLASS_HID_20827 = 0x20827,
- BNXT_ULP_CLASS_HID_23ba7 = 0x23ba7,
- BNXT_ULP_CLASS_HID_2af67 = 0x2af67,
- BNXT_ULP_CLASS_HID_2dee7 = 0x2dee7,
- BNXT_ULP_CLASS_HID_25e83 = 0x25e83,
- BNXT_ULP_CLASS_HID_24803 = 0x24803,
- BNXT_ULP_CLASS_HID_2fdc3 = 0x2fdc3,
- BNXT_ULP_CLASS_HID_2ef43 = 0x2ef43,
- BNXT_ULP_CLASS_HID_247bf = 0x247bf,
- BNXT_ULP_CLASS_HID_219ff = 0x219ff,
- BNXT_ULP_CLASS_HID_28dbf = 0x28dbf,
- BNXT_ULP_CLASS_HID_2bf07 = 0x2bf07,
- BNXT_ULP_CLASS_HID_25467 = 0x25467,
- BNXT_ULP_CLASS_HID_26e5f = 0x26e5f,
- BNXT_ULP_CLASS_HID_2d21f = 0x2d21f,
- BNXT_ULP_CLASS_HID_2cde7 = 0x2cde7,
- BNXT_ULP_CLASS_HID_26f6f = 0x26f6f,
- BNXT_ULP_CLASS_HID_221af = 0x221af,
- BNXT_ULP_CLASS_HID_2956f = 0x2956f,
- BNXT_ULP_CLASS_HID_2c4c7 = 0x2c4c7,
- BNXT_ULP_CLASS_HID_24487 = 0x24487,
- BNXT_ULP_CLASS_HID_2760f = 0x2760f,
- BNXT_ULP_CLASS_HID_2fbcf = 0x2fbcf,
- BNXT_ULP_CLASS_HID_2d5a7 = 0x2d5a7,
- BNXT_ULP_CLASS_HID_25357 = 0x25357,
- BNXT_ULP_CLASS_HID_21597 = 0x21597,
- BNXT_ULP_CLASS_HID_29957 = 0x29957,
- BNXT_ULP_CLASS_HID_2cb27 = 0x2cb27,
- BNXT_ULP_CLASS_HID_248f7 = 0x248f7,
- BNXT_ULP_CLASS_HID_27a77 = 0x27a77,
- BNXT_ULP_CLASS_HID_2ee37 = 0x2ee37,
- BNXT_ULP_CLASS_HID_2d987 = 0x2d987,
- BNXT_ULP_CLASS_HID_203c7 = 0x203c7,
- BNXT_ULP_CLASS_HID_23d47 = 0x23d47,
- BNXT_ULP_CLASS_HID_2a107 = 0x2a107,
- BNXT_ULP_CLASS_HID_2d0e7 = 0x2d0e7,
- BNXT_ULP_CLASS_HID_250a7 = 0x250a7,
- BNXT_ULP_CLASS_HID_24227 = 0x24227,
- BNXT_ULP_CLASS_HID_2f7e7 = 0x2f7e7,
- BNXT_ULP_CLASS_HID_2c827 = 0x2c827,
- BNXT_ULP_CLASS_HID_25422 = 0x25422,
- BNXT_ULP_CLASS_HID_21a66 = 0x21a66,
- BNXT_ULP_CLASS_HID_2f76a = 0x2f76a,
- BNXT_ULP_CLASS_HID_2bcae = 0x2bcae,
- BNXT_ULP_CLASS_HID_245ce = 0x245ce,
- BNXT_ULP_CLASS_HID_24b02 = 0x24b02,
- BNXT_ULP_CLASS_HID_2dfc2 = 0x2dfc2,
- BNXT_ULP_CLASS_HID_2ee4a = 0x2ee4a,
- BNXT_ULP_CLASS_HID_22cbe = 0x22cbe,
- BNXT_ULP_CLASS_HID_21232 = 0x21232,
- BNXT_ULP_CLASS_HID_2cf26 = 0x2cf26,
- BNXT_ULP_CLASS_HID_2b53a = 0x2b53a,
- BNXT_ULP_CLASS_HID_25d9a = 0x25d9a,
- BNXT_ULP_CLASS_HID_2439e = 0x2439e,
- BNXT_ULP_CLASS_HID_2d79e = 0x2d79e,
- BNXT_ULP_CLASS_HID_2e606 = 0x2e606,
- BNXT_ULP_CLASS_HID_21c5e = 0x21c5e,
- BNXT_ULP_CLASS_HID_22ac6 = 0x22ac6,
- BNXT_ULP_CLASS_HID_2be86 = 0x2be86,
- BNXT_ULP_CLASS_HID_2cd0e = 0x2cd0e,
- BNXT_ULP_CLASS_HID_24d1a = 0x24d1a,
- BNXT_ULP_CLASS_HID_25b82 = 0x25b82,
- BNXT_ULP_CLASS_HID_2d042 = 0x2d042,
- BNXT_ULP_CLASS_HID_2d586 = 0x2d586,
- BNXT_ULP_CLASS_HID_2140a = 0x2140a,
- BNXT_ULP_CLASS_HID_22292 = 0x22292,
- BNXT_ULP_CLASS_HID_2b712 = 0x2b712,
- BNXT_ULP_CLASS_HID_2c59a = 0x2c59a,
- BNXT_ULP_CLASS_HID_24596 = 0x24596,
- BNXT_ULP_CLASS_HID_2541e = 0x2541e,
- BNXT_ULP_CLASS_HID_2e81e = 0x2e81e,
- BNXT_ULP_CLASS_HID_2f686 = 0x2f686,
- BNXT_ULP_CLASS_HID_24cf2 = 0x24cf2,
- BNXT_ULP_CLASS_HID_23236 = 0x23236,
- BNXT_ULP_CLASS_HID_286f6 = 0x286f6,
- BNXT_ULP_CLASS_HID_2d57e = 0x2d57e,
- BNXT_ULP_CLASS_HID_2555a = 0x2555a,
- BNXT_ULP_CLASS_HID_263d2 = 0x263d2,
- BNXT_ULP_CLASS_HID_2f792 = 0x2f792,
- BNXT_ULP_CLASS_HID_2c61a = 0x2c61a,
- BNXT_ULP_CLASS_HID_244be = 0x244be,
- BNXT_ULP_CLASS_HID_20ab2 = 0x20ab2,
- BNXT_ULP_CLASS_HID_29eb2 = 0x29eb2,
- BNXT_ULP_CLASS_HID_2ad3a = 0x2ad3a,
- BNXT_ULP_CLASS_HID_2761a = 0x2761a,
- BNXT_ULP_CLASS_HID_27b9e = 0x27b9e,
- BNXT_ULP_CLASS_HID_2f01e = 0x2f01e,
- BNXT_ULP_CLASS_HID_2de96 = 0x2de96,
- BNXT_ULP_CLASS_HID_2341e = 0x2341e,
- BNXT_ULP_CLASS_HID_24296 = 0x24296,
- BNXT_ULP_CLASS_HID_2d756 = 0x2d756,
- BNXT_ULP_CLASS_HID_29c9a = 0x29c9a,
- BNXT_ULP_CLASS_HID_265da = 0x265da,
- BNXT_ULP_CLASS_HID_27452 = 0x27452,
- BNXT_ULP_CLASS_HID_2c812 = 0x2c812,
- BNXT_ULP_CLASS_HID_2ce56 = 0x2ce56,
- BNXT_ULP_CLASS_HID_20c9a = 0x20c9a,
- BNXT_ULP_CLASS_HID_25b12 = 0x25b12,
- BNXT_ULP_CLASS_HID_2af12 = 0x2af12,
- BNXT_ULP_CLASS_HID_29516 = 0x29516,
- BNXT_ULP_CLASS_HID_27d96 = 0x27d96,
- BNXT_ULP_CLASS_HID_24c1e = 0x24c1e,
- BNXT_ULP_CLASS_HID_2c09e = 0x2c09e,
- BNXT_ULP_CLASS_HID_2c612 = 0x2c612,
- BNXT_ULP_CLASS_HID_24002 = 0x24002,
- BNXT_ULP_CLASS_HID_20646 = 0x20646,
- BNXT_ULP_CLASS_HID_29a06 = 0x29a06,
- BNXT_ULP_CLASS_HID_2a886 = 0x2a886,
- BNXT_ULP_CLASS_HID_271a6 = 0x271a6,
- BNXT_ULP_CLASS_HID_277e2 = 0x277e2,
- BNXT_ULP_CLASS_HID_2cba2 = 0x2cba2,
- BNXT_ULP_CLASS_HID_2da22 = 0x2da22,
- BNXT_ULP_CLASS_HID_25896 = 0x25896,
- BNXT_ULP_CLASS_HID_21e12 = 0x21e12,
- BNXT_ULP_CLASS_HID_29292 = 0x29292,
- BNXT_ULP_CLASS_HID_2a112 = 0x2a112,
- BNXT_ULP_CLASS_HID_24a32 = 0x24a32,
- BNXT_ULP_CLASS_HID_24fb6 = 0x24fb6,
- BNXT_ULP_CLASS_HID_2c436 = 0x2c436,
- BNXT_ULP_CLASS_HID_2d2a6 = 0x2d2a6,
- BNXT_ULP_CLASS_HID_20856 = 0x20856,
- BNXT_ULP_CLASS_HID_256c6 = 0x256c6,
- BNXT_ULP_CLASS_HID_2aa86 = 0x2aa86,
- BNXT_ULP_CLASS_HID_290d2 = 0x290d2,
- BNXT_ULP_CLASS_HID_279d2 = 0x279d2,
- BNXT_ULP_CLASS_HID_24842 = 0x24842,
- BNXT_ULP_CLASS_HID_2dc02 = 0x2dc02,
- BNXT_ULP_CLASS_HID_2c246 = 0x2c246,
- BNXT_ULP_CLASS_HID_20082 = 0x20082,
- BNXT_ULP_CLASS_HID_22e92 = 0x22e92,
- BNXT_ULP_CLASS_HID_2a312 = 0x2a312,
- BNXT_ULP_CLASS_HID_2f192 = 0x2f192,
- BNXT_ULP_CLASS_HID_27196 = 0x27196,
- BNXT_ULP_CLASS_HID_24016 = 0x24016,
- BNXT_ULP_CLASS_HID_2d496 = 0x2d496,
- BNXT_ULP_CLASS_HID_2da12 = 0x2da12,
- BNXT_ULP_CLASS_HID_278d2 = 0x278d2,
- BNXT_ULP_CLASS_HID_23e16 = 0x23e16,
- BNXT_ULP_CLASS_HID_2b2d6 = 0x2b2d6,
- BNXT_ULP_CLASS_HID_2c156 = 0x2c156,
- BNXT_ULP_CLASS_HID_24132 = 0x24132,
- BNXT_ULP_CLASS_HID_26fb2 = 0x26fb2,
- BNXT_ULP_CLASS_HID_2e472 = 0x2e472,
- BNXT_ULP_CLASS_HID_2f2f2 = 0x2f2f2,
- BNXT_ULP_CLASS_HID_27096 = 0x27096,
- BNXT_ULP_CLASS_HID_23692 = 0x23692,
- BNXT_ULP_CLASS_HID_28a92 = 0x28a92,
- BNXT_ULP_CLASS_HID_2d912 = 0x2d912,
- BNXT_ULP_CLASS_HID_259b6 = 0x259b6,
- BNXT_ULP_CLASS_HID_26836 = 0x26836,
- BNXT_ULP_CLASS_HID_2fc36 = 0x2fc36,
- BNXT_ULP_CLASS_HID_2cab6 = 0x2cab6,
- BNXT_ULP_CLASS_HID_22016 = 0x22016,
- BNXT_ULP_CLASS_HID_24e96 = 0x24e96,
- BNXT_ULP_CLASS_HID_2c356 = 0x2c356,
- BNXT_ULP_CLASS_HID_28892 = 0x28892,
- BNXT_ULP_CLASS_HID_25192 = 0x25192,
- BNXT_ULP_CLASS_HID_257d6 = 0x257d6,
- BNXT_ULP_CLASS_HID_2f4d2 = 0x2f4d2,
- BNXT_ULP_CLASS_HID_2fa16 = 0x2fa16,
- BNXT_ULP_CLASS_HID_23892 = 0x23892,
- BNXT_ULP_CLASS_HID_24712 = 0x24712,
- BNXT_ULP_CLASS_HID_2db12 = 0x2db12,
- BNXT_ULP_CLASS_HID_28116 = 0x28116,
- BNXT_ULP_CLASS_HID_26a16 = 0x26a16,
- BNXT_ULP_CLASS_HID_27896 = 0x27896,
- BNXT_ULP_CLASS_HID_2cc96 = 0x2cc96,
- BNXT_ULP_CLASS_HID_2f292 = 0x2f292,
- BNXT_ULP_CLASS_HID_24b05 = 0x24b05,
- BNXT_ULP_CLASS_HID_20541 = 0x20541,
- BNXT_ULP_CLASS_HID_2e84d = 0x2e84d,
- BNXT_ULP_CLASS_HID_2a389 = 0x2a389,
- BNXT_ULP_CLASS_HID_25ae9 = 0x25ae9,
- BNXT_ULP_CLASS_HID_25425 = 0x25425,
- BNXT_ULP_CLASS_HID_2c0e5 = 0x2c0e5,
- BNXT_ULP_CLASS_HID_2f16d = 0x2f16d,
- BNXT_ULP_CLASS_HID_253d5 = 0x253d5,
- BNXT_ULP_CLASS_HID_22d11 = 0x22d11,
- BNXT_ULP_CLASS_HID_299d1 = 0x299d1,
- BNXT_ULP_CLASS_HID_2ca59 = 0x2ca59,
- BNXT_ULP_CLASS_HID_24a7d = 0x24a7d,
- BNXT_ULP_CLASS_HID_27cf5 = 0x27cf5,
- BNXT_ULP_CLASS_HID_2e8b5 = 0x2e8b5,
- BNXT_ULP_CLASS_HID_2d93d = 0x2d93d,
- BNXT_ULP_CLASS_HID_25f25 = 0x25f25,
- BNXT_ULP_CLASS_HID_21961 = 0x21961,
- BNXT_ULP_CLASS_HID_28521 = 0x28521,
- BNXT_ULP_CLASS_HID_2b7a1 = 0x2b7a1,
- BNXT_ULP_CLASS_HID_26e81 = 0x26e81,
- BNXT_ULP_CLASS_HID_268c5 = 0x268c5,
- BNXT_ULP_CLASS_HID_2d485 = 0x2d485,
- BNXT_ULP_CLASS_HID_2c505 = 0x2c505,
- BNXT_ULP_CLASS_HID_267f5 = 0x267f5,
- BNXT_ULP_CLASS_HID_22131 = 0x22131,
- BNXT_ULP_CLASS_HID_2adf1 = 0x2adf1,
- BNXT_ULP_CLASS_HID_2de71 = 0x2de71,
- BNXT_ULP_CLASS_HID_25e15 = 0x25e15,
- BNXT_ULP_CLASS_HID_27095 = 0x27095,
- BNXT_ULP_CLASS_HID_2fb55 = 0x2fb55,
- BNXT_ULP_CLASS_HID_2edd5 = 0x2edd5,
- BNXT_ULP_CLASS_HID_24511 = 0x24511,
- BNXT_ULP_CLASS_HID_21f51 = 0x21f51,
- BNXT_ULP_CLASS_HID_28b11 = 0x28b11,
- BNXT_ULP_CLASS_HID_2bd99 = 0x2bd99,
- BNXT_ULP_CLASS_HID_254f9 = 0x254f9,
- BNXT_ULP_CLASS_HID_26e31 = 0x26e31,
- BNXT_ULP_CLASS_HID_2daf1 = 0x2daf1,
- BNXT_ULP_CLASS_HID_2cb79 = 0x2cb79,
- BNXT_ULP_CLASS_HID_26dd1 = 0x26dd1,
- BNXT_ULP_CLASS_HID_22711 = 0x22711,
- BNXT_ULP_CLASS_HID_293d1 = 0x293d1,
- BNXT_ULP_CLASS_HID_2c459 = 0x2c459,
- BNXT_ULP_CLASS_HID_24419 = 0x24419,
- BNXT_ULP_CLASS_HID_276f1 = 0x276f1,
- BNXT_ULP_CLASS_HID_2e2b1 = 0x2e2b1,
- BNXT_ULP_CLASS_HID_2d339 = 0x2d339,
- BNXT_ULP_CLASS_HID_25931 = 0x25931,
- BNXT_ULP_CLASS_HID_21371 = 0x21371,
- BNXT_ULP_CLASS_HID_29f31 = 0x29f31,
- BNXT_ULP_CLASS_HID_2b1b1 = 0x2b1b1,
- BNXT_ULP_CLASS_HID_26891 = 0x26891,
- BNXT_ULP_CLASS_HID_262d1 = 0x262d1,
- BNXT_ULP_CLASS_HID_2ee91 = 0x2ee91,
- BNXT_ULP_CLASS_HID_2df11 = 0x2df11,
- BNXT_ULP_CLASS_HID_20951 = 0x20951,
- BNXT_ULP_CLASS_HID_23b31 = 0x23b31,
- BNXT_ULP_CLASS_HID_2a7f1 = 0x2a7f1,
- BNXT_ULP_CLASS_HID_2d871 = 0x2d871,
- BNXT_ULP_CLASS_HID_25831 = 0x25831,
- BNXT_ULP_CLASS_HID_24a91 = 0x24a91,
- BNXT_ULP_CLASS_HID_2f551 = 0x2f551,
- BNXT_ULP_CLASS_HID_2e7d1 = 0x2e7d1,
- BNXT_ULP_CLASS_HID_2481f = 0x2481f,
- BNXT_ULP_CLASS_HID_2025b = 0x2025b,
- BNXT_ULP_CLASS_HID_28e1b = 0x28e1b,
- BNXT_ULP_CLASS_HID_2a083 = 0x2a083,
- BNXT_ULP_CLASS_HID_257e3 = 0x257e3,
- BNXT_ULP_CLASS_HID_2513f = 0x2513f,
- BNXT_ULP_CLASS_HID_2ddff = 0x2ddff,
- BNXT_ULP_CLASS_HID_2ce67 = 0x2ce67,
- BNXT_ULP_CLASS_HID_250df = 0x250df,
- BNXT_ULP_CLASS_HID_22a1b = 0x22a1b,
- BNXT_ULP_CLASS_HID_296db = 0x296db,
- BNXT_ULP_CLASS_HID_2c753 = 0x2c753,
- BNXT_ULP_CLASS_HID_24777 = 0x24777,
- BNXT_ULP_CLASS_HID_279ff = 0x279ff,
- BNXT_ULP_CLASS_HID_2e5bf = 0x2e5bf,
- BNXT_ULP_CLASS_HID_2d637 = 0x2d637,
- BNXT_ULP_CLASS_HID_25c37 = 0x25c37,
- BNXT_ULP_CLASS_HID_21673 = 0x21673,
- BNXT_ULP_CLASS_HID_28233 = 0x28233,
- BNXT_ULP_CLASS_HID_2b4a3 = 0x2b4a3,
- BNXT_ULP_CLASS_HID_26b83 = 0x26b83,
- BNXT_ULP_CLASS_HID_265d7 = 0x265d7,
- BNXT_ULP_CLASS_HID_2d197 = 0x2d197,
- BNXT_ULP_CLASS_HID_2c207 = 0x2c207,
- BNXT_ULP_CLASS_HID_20db3 = 0x20db3,
- BNXT_ULP_CLASS_HID_23e33 = 0x23e33,
- BNXT_ULP_CLASS_HID_2aaf3 = 0x2aaf3,
- BNXT_ULP_CLASS_HID_2db73 = 0x2db73,
- BNXT_ULP_CLASS_HID_25b17 = 0x25b17,
- BNXT_ULP_CLASS_HID_24d97 = 0x24d97,
- BNXT_ULP_CLASS_HID_2f857 = 0x2f857,
- BNXT_ULP_CLASS_HID_2ead7 = 0x2ead7,
- BNXT_ULP_CLASS_HID_2422b = 0x2422b,
- BNXT_ULP_CLASS_HID_21c6b = 0x21c6b,
- BNXT_ULP_CLASS_HID_2882b = 0x2882b,
- BNXT_ULP_CLASS_HID_2ba93 = 0x2ba93,
- BNXT_ULP_CLASS_HID_251f3 = 0x251f3,
- BNXT_ULP_CLASS_HID_26bcb = 0x26bcb,
- BNXT_ULP_CLASS_HID_2d78b = 0x2d78b,
- BNXT_ULP_CLASS_HID_2c873 = 0x2c873,
- BNXT_ULP_CLASS_HID_26afb = 0x26afb,
- BNXT_ULP_CLASS_HID_2243b = 0x2243b,
- BNXT_ULP_CLASS_HID_290fb = 0x290fb,
- BNXT_ULP_CLASS_HID_2c153 = 0x2c153,
- BNXT_ULP_CLASS_HID_24113 = 0x24113,
- BNXT_ULP_CLASS_HID_2739b = 0x2739b,
- BNXT_ULP_CLASS_HID_2fe5b = 0x2fe5b,
- BNXT_ULP_CLASS_HID_2d033 = 0x2d033,
- BNXT_ULP_CLASS_HID_256c3 = 0x256c3,
- BNXT_ULP_CLASS_HID_21003 = 0x21003,
- BNXT_ULP_CLASS_HID_29cc3 = 0x29cc3,
- BNXT_ULP_CLASS_HID_2ceb3 = 0x2ceb3,
- BNXT_ULP_CLASS_HID_24d63 = 0x24d63,
- BNXT_ULP_CLASS_HID_27fe3 = 0x27fe3,
- BNXT_ULP_CLASS_HID_2eba3 = 0x2eba3,
- BNXT_ULP_CLASS_HID_2dc13 = 0x2dc13,
- BNXT_ULP_CLASS_HID_20653 = 0x20653,
- BNXT_ULP_CLASS_HID_238d3 = 0x238d3,
- BNXT_ULP_CLASS_HID_2a493 = 0x2a493,
- BNXT_ULP_CLASS_HID_2d573 = 0x2d573,
- BNXT_ULP_CLASS_HID_25533 = 0x25533,
- BNXT_ULP_CLASS_HID_247b3 = 0x247b3,
- BNXT_ULP_CLASS_HID_2f273 = 0x2f273,
- BNXT_ULP_CLASS_HID_2cdb3 = 0x2cdb3,
- BNXT_ULP_CLASS_HID_25c7d = 0x25c7d,
- BNXT_ULP_CLASS_HID_21239 = 0x21239,
- BNXT_ULP_CLASS_HID_2ff35 = 0x2ff35,
- BNXT_ULP_CLASS_HID_2b4f1 = 0x2b4f1,
- BNXT_ULP_CLASS_HID_24d91 = 0x24d91,
- BNXT_ULP_CLASS_HID_2435d = 0x2435d,
- BNXT_ULP_CLASS_HID_2d79d = 0x2d79d,
- BNXT_ULP_CLASS_HID_2e615 = 0x2e615,
- BNXT_ULP_CLASS_HID_244ad = 0x244ad,
- BNXT_ULP_CLASS_HID_23a69 = 0x23a69,
- BNXT_ULP_CLASS_HID_28ea9 = 0x28ea9,
- BNXT_ULP_CLASS_HID_2dd21 = 0x2dd21,
- BNXT_ULP_CLASS_HID_25d05 = 0x25d05,
- BNXT_ULP_CLASS_HID_26b8d = 0x26b8d,
- BNXT_ULP_CLASS_HID_2ffcd = 0x2ffcd,
- BNXT_ULP_CLASS_HID_2ce45 = 0x2ce45,
- BNXT_ULP_CLASS_HID_2485d = 0x2485d,
- BNXT_ULP_CLASS_HID_20e19 = 0x20e19,
- BNXT_ULP_CLASS_HID_29259 = 0x29259,
- BNXT_ULP_CLASS_HID_2a0d9 = 0x2a0d9,
- BNXT_ULP_CLASS_HID_279f9 = 0x279f9,
- BNXT_ULP_CLASS_HID_27fbd = 0x27fbd,
- BNXT_ULP_CLASS_HID_2c3fd = 0x2c3fd,
- BNXT_ULP_CLASS_HID_2d27d = 0x2d27d,
- BNXT_ULP_CLASS_HID_2708d = 0x2708d,
- BNXT_ULP_CLASS_HID_23649 = 0x23649,
- BNXT_ULP_CLASS_HID_2ba89 = 0x2ba89,
- BNXT_ULP_CLASS_HID_2c909 = 0x2c909,
- BNXT_ULP_CLASS_HID_2496d = 0x2496d,
- BNXT_ULP_CLASS_HID_267ed = 0x267ed,
- BNXT_ULP_CLASS_HID_2ec2d = 0x2ec2d,
- BNXT_ULP_CLASS_HID_2faad = 0x2faad,
- BNXT_ULP_CLASS_HID_34c6 = 0x34c6,
- BNXT_ULP_CLASS_HID_0c22 = 0x0c22,
- BNXT_ULP_CLASS_HID_1cbe = 0x1cbe,
- BNXT_ULP_CLASS_HID_179a = 0x179a,
- BNXT_ULP_CLASS_HID_59be = 0x59be,
- BNXT_ULP_CLASS_HID_515a = 0x515a,
- BNXT_ULP_CLASS_HID_1c72 = 0x1c72,
- BNXT_ULP_CLASS_HID_171e = 0x171e,
- BNXT_ULP_CLASS_HID_19c8 = 0x19c8,
- BNXT_ULP_CLASS_HID_112c = 0x112c,
- BNXT_ULP_CLASS_HID_4d68 = 0x4d68,
- BNXT_ULP_CLASS_HID_444c = 0x444c,
- BNXT_ULP_CLASS_HID_0e8c = 0x0e8c,
- BNXT_ULP_CLASS_HID_09e0 = 0x09e0,
- BNXT_ULP_CLASS_HID_1af0 = 0x1af0,
- BNXT_ULP_CLASS_HID_15d4 = 0x15d4,
- BNXT_ULP_CLASS_HID_1dd0 = 0x1dd0,
- BNXT_ULP_CLASS_HID_14f4 = 0x14f4,
- BNXT_ULP_CLASS_HID_70b0 = 0x70b0,
- BNXT_ULP_CLASS_HID_4854 = 0x4854,
- BNXT_ULP_CLASS_HID_3dd4 = 0x3dd4,
- BNXT_ULP_CLASS_HID_34f8 = 0x34f8,
- BNXT_ULP_CLASS_HID_09e8 = 0x09e8,
- BNXT_ULP_CLASS_HID_008c = 0x008c,
- BNXT_ULP_CLASS_HID_34e6 = 0x34e6,
- BNXT_ULP_CLASS_HID_0c02 = 0x0c02,
- BNXT_ULP_CLASS_HID_1c9e = 0x1c9e,
- BNXT_ULP_CLASS_HID_17ba = 0x17ba,
- BNXT_ULP_CLASS_HID_429e = 0x429e,
- BNXT_ULP_CLASS_HID_5dba = 0x5dba,
- BNXT_ULP_CLASS_HID_2a16 = 0x2a16,
- BNXT_ULP_CLASS_HID_2532 = 0x2532,
- BNXT_ULP_CLASS_HID_2da2 = 0x2da2,
- BNXT_ULP_CLASS_HID_24fe = 0x24fe,
- BNXT_ULP_CLASS_HID_355a = 0x355a,
- BNXT_ULP_CLASS_HID_0c76 = 0x0c76,
- BNXT_ULP_CLASS_HID_13e6 = 0x13e6,
- BNXT_ULP_CLASS_HID_7276 = 0x7276,
- BNXT_ULP_CLASS_HID_42d2 = 0x42d2,
- BNXT_ULP_CLASS_HID_5dee = 0x5dee,
- BNXT_ULP_CLASS_HID_59de = 0x59de,
- BNXT_ULP_CLASS_HID_513a = 0x513a,
- BNXT_ULP_CLASS_HID_1c12 = 0x1c12,
- BNXT_ULP_CLASS_HID_177e = 0x177e,
- BNXT_ULP_CLASS_HID_0e92 = 0x0e92,
- BNXT_ULP_CLASS_HID_09fe = 0x09fe,
- BNXT_ULP_CLASS_HID_5c1a = 0x5c1a,
- BNXT_ULP_CLASS_HID_5746 = 0x5746,
- BNXT_ULP_CLASS_HID_79da = 0x79da,
- BNXT_ULP_CLASS_HID_7106 = 0x7106,
- BNXT_ULP_CLASS_HID_3c1e = 0x3c1e,
- BNXT_ULP_CLASS_HID_377a = 0x377a,
- BNXT_ULP_CLASS_HID_2e9e = 0x2e9e,
- BNXT_ULP_CLASS_HID_29fa = 0x29fa,
- BNXT_ULP_CLASS_HID_14d2 = 0x14d2,
- BNXT_ULP_CLASS_HID_7742 = 0x7742,
- BNXT_ULP_CLASS_HID_3706 = 0x3706,
- BNXT_ULP_CLASS_HID_0fe2 = 0x0fe2,
- BNXT_ULP_CLASS_HID_1f7e = 0x1f7e,
- BNXT_ULP_CLASS_HID_145a = 0x145a,
- BNXT_ULP_CLASS_HID_417e = 0x417e,
- BNXT_ULP_CLASS_HID_5e5a = 0x5e5a,
- BNXT_ULP_CLASS_HID_29f6 = 0x29f6,
- BNXT_ULP_CLASS_HID_26d2 = 0x26d2,
- BNXT_ULP_CLASS_HID_2e42 = 0x2e42,
- BNXT_ULP_CLASS_HID_271e = 0x271e,
- BNXT_ULP_CLASS_HID_36ba = 0x36ba,
- BNXT_ULP_CLASS_HID_0f96 = 0x0f96,
- BNXT_ULP_CLASS_HID_1006 = 0x1006,
- BNXT_ULP_CLASS_HID_7196 = 0x7196,
- BNXT_ULP_CLASS_HID_4132 = 0x4132,
- BNXT_ULP_CLASS_HID_5e0e = 0x5e0e,
- BNXT_ULP_CLASS_HID_59fe = 0x59fe,
- BNXT_ULP_CLASS_HID_511a = 0x511a,
- BNXT_ULP_CLASS_HID_1c32 = 0x1c32,
- BNXT_ULP_CLASS_HID_175e = 0x175e,
- BNXT_ULP_CLASS_HID_0eb2 = 0x0eb2,
- BNXT_ULP_CLASS_HID_09de = 0x09de,
- BNXT_ULP_CLASS_HID_5c3a = 0x5c3a,
- BNXT_ULP_CLASS_HID_5766 = 0x5766,
- BNXT_ULP_CLASS_HID_79fa = 0x79fa,
- BNXT_ULP_CLASS_HID_7126 = 0x7126,
- BNXT_ULP_CLASS_HID_3c3e = 0x3c3e,
- BNXT_ULP_CLASS_HID_375a = 0x375a,
- BNXT_ULP_CLASS_HID_2ebe = 0x2ebe,
- BNXT_ULP_CLASS_HID_29da = 0x29da,
- BNXT_ULP_CLASS_HID_14f2 = 0x14f2,
- BNXT_ULP_CLASS_HID_7762 = 0x7762,
- BNXT_ULP_CLASS_HID_19e8 = 0x19e8,
- BNXT_ULP_CLASS_HID_110c = 0x110c,
- BNXT_ULP_CLASS_HID_4d48 = 0x4d48,
- BNXT_ULP_CLASS_HID_446c = 0x446c,
- BNXT_ULP_CLASS_HID_0eac = 0x0eac,
- BNXT_ULP_CLASS_HID_09c0 = 0x09c0,
- BNXT_ULP_CLASS_HID_1ad0 = 0x1ad0,
- BNXT_ULP_CLASS_HID_15f4 = 0x15f4,
- BNXT_ULP_CLASS_HID_39ec = 0x39ec,
- BNXT_ULP_CLASS_HID_3100 = 0x3100,
- BNXT_ULP_CLASS_HID_0210 = 0x0210,
- BNXT_ULP_CLASS_HID_1d34 = 0x1d34,
- BNXT_ULP_CLASS_HID_2ea0 = 0x2ea0,
- BNXT_ULP_CLASS_HID_29c4 = 0x29c4,
- BNXT_ULP_CLASS_HID_3ad4 = 0x3ad4,
- BNXT_ULP_CLASS_HID_35e8 = 0x35e8,
- BNXT_ULP_CLASS_HID_5d80 = 0x5d80,
- BNXT_ULP_CLASS_HID_54a4 = 0x54a4,
- BNXT_ULP_CLASS_HID_29b4 = 0x29b4,
- BNXT_ULP_CLASS_HID_20c8 = 0x20c8,
- BNXT_ULP_CLASS_HID_7244 = 0x7244,
- BNXT_ULP_CLASS_HID_4d98 = 0x4d98,
- BNXT_ULP_CLASS_HID_5e68 = 0x5e68,
- BNXT_ULP_CLASS_HID_598c = 0x598c,
- BNXT_ULP_CLASS_HID_1248 = 0x1248,
- BNXT_ULP_CLASS_HID_74d8 = 0x74d8,
- BNXT_ULP_CLASS_HID_49a8 = 0x49a8,
- BNXT_ULP_CLASS_HID_40cc = 0x40cc,
- BNXT_ULP_CLASS_HID_0b0c = 0x0b0c,
- BNXT_ULP_CLASS_HID_0220 = 0x0220,
- BNXT_ULP_CLASS_HID_1730 = 0x1730,
- BNXT_ULP_CLASS_HID_7980 = 0x7980,
- BNXT_ULP_CLASS_HID_1db0 = 0x1db0,
- BNXT_ULP_CLASS_HID_1494 = 0x1494,
- BNXT_ULP_CLASS_HID_70d0 = 0x70d0,
- BNXT_ULP_CLASS_HID_4834 = 0x4834,
- BNXT_ULP_CLASS_HID_3db4 = 0x3db4,
- BNXT_ULP_CLASS_HID_3498 = 0x3498,
- BNXT_ULP_CLASS_HID_0988 = 0x0988,
- BNXT_ULP_CLASS_HID_00ec = 0x00ec,
- BNXT_ULP_CLASS_HID_23f44 = 0x23f44,
- BNXT_ULP_CLASS_HID_236a8 = 0x236a8,
- BNXT_ULP_CLASS_HID_20b58 = 0x20b58,
- BNXT_ULP_CLASS_HID_202bc = 0x202bc,
- BNXT_ULP_CLASS_HID_25f48 = 0x25f48,
- BNXT_ULP_CLASS_HID_256ac = 0x256ac,
- BNXT_ULP_CLASS_HID_22b5c = 0x22b5c,
- BNXT_ULP_CLASS_HID_22280 = 0x22280,
- BNXT_ULP_CLASS_HID_14000 = 0x14000,
- BNXT_ULP_CLASS_HID_15b64 = 0x15b64,
- BNXT_ULP_CLASS_HID_12c14 = 0x12c14,
- BNXT_ULP_CLASS_HID_12778 = 0x12778,
- BNXT_ULP_CLASS_HID_118f8 = 0x118f8,
- BNXT_ULP_CLASS_HID_113dc = 0x113dc,
- BNXT_ULP_CLASS_HID_14c18 = 0x14c18,
- BNXT_ULP_CLASS_HID_1477c = 0x1477c,
- BNXT_ULP_CLASS_HID_31a88 = 0x31a88,
- BNXT_ULP_CLASS_HID_315ec = 0x315ec,
- BNXT_ULP_CLASS_HID_34e28 = 0x34e28,
- BNXT_ULP_CLASS_HID_3490c = 0x3490c,
- BNXT_ULP_CLASS_HID_33a8c = 0x33a8c,
- BNXT_ULP_CLASS_HID_335f0 = 0x335f0,
- BNXT_ULP_CLASS_HID_306e0 = 0x306e0,
- BNXT_ULP_CLASS_HID_301c4 = 0x301c4,
- BNXT_ULP_CLASS_HID_1a08 = 0x1a08,
- BNXT_ULP_CLASS_HID_12ec = 0x12ec,
- BNXT_ULP_CLASS_HID_4ea8 = 0x4ea8,
- BNXT_ULP_CLASS_HID_478c = 0x478c,
- BNXT_ULP_CLASS_HID_0d4c = 0x0d4c,
- BNXT_ULP_CLASS_HID_0a20 = 0x0a20,
- BNXT_ULP_CLASS_HID_1930 = 0x1930,
- BNXT_ULP_CLASS_HID_1614 = 0x1614,
- BNXT_ULP_CLASS_HID_3a0c = 0x3a0c,
- BNXT_ULP_CLASS_HID_32e0 = 0x32e0,
- BNXT_ULP_CLASS_HID_01f0 = 0x01f0,
- BNXT_ULP_CLASS_HID_1ed4 = 0x1ed4,
- BNXT_ULP_CLASS_HID_2d40 = 0x2d40,
- BNXT_ULP_CLASS_HID_2a24 = 0x2a24,
- BNXT_ULP_CLASS_HID_3934 = 0x3934,
- BNXT_ULP_CLASS_HID_3608 = 0x3608,
- BNXT_ULP_CLASS_HID_5e60 = 0x5e60,
- BNXT_ULP_CLASS_HID_5744 = 0x5744,
- BNXT_ULP_CLASS_HID_2a54 = 0x2a54,
- BNXT_ULP_CLASS_HID_2328 = 0x2328,
- BNXT_ULP_CLASS_HID_71a4 = 0x71a4,
- BNXT_ULP_CLASS_HID_4e78 = 0x4e78,
- BNXT_ULP_CLASS_HID_5d88 = 0x5d88,
- BNXT_ULP_CLASS_HID_5a6c = 0x5a6c,
- BNXT_ULP_CLASS_HID_11a8 = 0x11a8,
- BNXT_ULP_CLASS_HID_7738 = 0x7738,
- BNXT_ULP_CLASS_HID_4a48 = 0x4a48,
- BNXT_ULP_CLASS_HID_432c = 0x432c,
- BNXT_ULP_CLASS_HID_08ec = 0x08ec,
- BNXT_ULP_CLASS_HID_01c0 = 0x01c0,
- BNXT_ULP_CLASS_HID_14d0 = 0x14d0,
- BNXT_ULP_CLASS_HID_7a60 = 0x7a60,
- BNXT_ULP_CLASS_HID_1d90 = 0x1d90,
- BNXT_ULP_CLASS_HID_14b4 = 0x14b4,
- BNXT_ULP_CLASS_HID_70f0 = 0x70f0,
- BNXT_ULP_CLASS_HID_4814 = 0x4814,
- BNXT_ULP_CLASS_HID_3d94 = 0x3d94,
- BNXT_ULP_CLASS_HID_34b8 = 0x34b8,
- BNXT_ULP_CLASS_HID_09a8 = 0x09a8,
- BNXT_ULP_CLASS_HID_00cc = 0x00cc,
- BNXT_ULP_CLASS_HID_23f64 = 0x23f64,
- BNXT_ULP_CLASS_HID_23688 = 0x23688,
- BNXT_ULP_CLASS_HID_20b78 = 0x20b78,
- BNXT_ULP_CLASS_HID_2029c = 0x2029c,
- BNXT_ULP_CLASS_HID_25f68 = 0x25f68,
- BNXT_ULP_CLASS_HID_2568c = 0x2568c,
- BNXT_ULP_CLASS_HID_22b7c = 0x22b7c,
- BNXT_ULP_CLASS_HID_222a0 = 0x222a0,
- BNXT_ULP_CLASS_HID_14020 = 0x14020,
- BNXT_ULP_CLASS_HID_15b44 = 0x15b44,
- BNXT_ULP_CLASS_HID_12c34 = 0x12c34,
- BNXT_ULP_CLASS_HID_12758 = 0x12758,
- BNXT_ULP_CLASS_HID_118d8 = 0x118d8,
- BNXT_ULP_CLASS_HID_113fc = 0x113fc,
- BNXT_ULP_CLASS_HID_14c38 = 0x14c38,
- BNXT_ULP_CLASS_HID_1475c = 0x1475c,
- BNXT_ULP_CLASS_HID_31aa8 = 0x31aa8,
- BNXT_ULP_CLASS_HID_315cc = 0x315cc,
- BNXT_ULP_CLASS_HID_34e08 = 0x34e08,
- BNXT_ULP_CLASS_HID_3492c = 0x3492c,
- BNXT_ULP_CLASS_HID_33aac = 0x33aac,
- BNXT_ULP_CLASS_HID_335d0 = 0x335d0,
- BNXT_ULP_CLASS_HID_306c0 = 0x306c0,
- BNXT_ULP_CLASS_HID_301e4 = 0x301e4,
- BNXT_ULP_CLASS_HID_4d32 = 0x4d32,
- BNXT_ULP_CLASS_HID_54aa = 0x54aa,
- BNXT_ULP_CLASS_HID_0686 = 0x0686,
- BNXT_ULP_CLASS_HID_540e = 0x540e,
- BNXT_ULP_CLASS_HID_2e3c = 0x2e3c,
- BNXT_ULP_CLASS_HID_3a20 = 0x3a20,
- BNXT_ULP_CLASS_HID_46f0 = 0x46f0,
- BNXT_ULP_CLASS_HID_52e4 = 0x52e4,
- BNXT_ULP_CLASS_HID_55e4 = 0x55e4,
- BNXT_ULP_CLASS_HID_21f8 = 0x21f8,
- BNXT_ULP_CLASS_HID_75e8 = 0x75e8,
- BNXT_ULP_CLASS_HID_41fc = 0x41fc,
- BNXT_ULP_CLASS_HID_4d12 = 0x4d12,
- BNXT_ULP_CLASS_HID_548a = 0x548a,
- BNXT_ULP_CLASS_HID_3356 = 0x3356,
- BNXT_ULP_CLASS_HID_1ace = 0x1ace,
- BNXT_ULP_CLASS_HID_1a9a = 0x1a9a,
- BNXT_ULP_CLASS_HID_4d46 = 0x4d46,
- BNXT_ULP_CLASS_HID_2812 = 0x2812,
- BNXT_ULP_CLASS_HID_338a = 0x338a,
- BNXT_ULP_CLASS_HID_06e6 = 0x06e6,
- BNXT_ULP_CLASS_HID_546e = 0x546e,
- BNXT_ULP_CLASS_HID_46ee = 0x46ee,
- BNXT_ULP_CLASS_HID_0d22 = 0x0d22,
- BNXT_ULP_CLASS_HID_26e2 = 0x26e2,
- BNXT_ULP_CLASS_HID_746a = 0x746a,
- BNXT_ULP_CLASS_HID_1fa6 = 0x1fa6,
- BNXT_ULP_CLASS_HID_2d2e = 0x2d2e,
- BNXT_ULP_CLASS_HID_4ef2 = 0x4ef2,
- BNXT_ULP_CLASS_HID_576a = 0x576a,
- BNXT_ULP_CLASS_HID_30b6 = 0x30b6,
- BNXT_ULP_CLASS_HID_192e = 0x192e,
- BNXT_ULP_CLASS_HID_197a = 0x197a,
- BNXT_ULP_CLASS_HID_4ea6 = 0x4ea6,
- BNXT_ULP_CLASS_HID_2bf2 = 0x2bf2,
- BNXT_ULP_CLASS_HID_306a = 0x306a,
- BNXT_ULP_CLASS_HID_06c6 = 0x06c6,
- BNXT_ULP_CLASS_HID_544e = 0x544e,
- BNXT_ULP_CLASS_HID_46ce = 0x46ce,
- BNXT_ULP_CLASS_HID_0d02 = 0x0d02,
- BNXT_ULP_CLASS_HID_26c2 = 0x26c2,
- BNXT_ULP_CLASS_HID_744a = 0x744a,
- BNXT_ULP_CLASS_HID_1f86 = 0x1f86,
- BNXT_ULP_CLASS_HID_2d0e = 0x2d0e,
- BNXT_ULP_CLASS_HID_2e1c = 0x2e1c,
- BNXT_ULP_CLASS_HID_3a00 = 0x3a00,
- BNXT_ULP_CLASS_HID_46d0 = 0x46d0,
- BNXT_ULP_CLASS_HID_52c4 = 0x52c4,
- BNXT_ULP_CLASS_HID_4e10 = 0x4e10,
- BNXT_ULP_CLASS_HID_5a04 = 0x5a04,
- BNXT_ULP_CLASS_HID_1f98 = 0x1f98,
- BNXT_ULP_CLASS_HID_72f8 = 0x72f8,
- BNXT_ULP_CLASS_HID_0a78 = 0x0a78,
- BNXT_ULP_CLASS_HID_166c = 0x166c,
- BNXT_ULP_CLASS_HID_233c = 0x233c,
- BNXT_ULP_CLASS_HID_0f20 = 0x0f20,
- BNXT_ULP_CLASS_HID_2a7c = 0x2a7c,
- BNXT_ULP_CLASS_HID_3660 = 0x3660,
- BNXT_ULP_CLASS_HID_4330 = 0x4330,
- BNXT_ULP_CLASS_HID_2f24 = 0x2f24,
- BNXT_ULP_CLASS_HID_5584 = 0x5584,
- BNXT_ULP_CLASS_HID_2198 = 0x2198,
- BNXT_ULP_CLASS_HID_7588 = 0x7588,
- BNXT_ULP_CLASS_HID_419c = 0x419c,
- BNXT_ULP_CLASS_HID_27758 = 0x27758,
- BNXT_ULP_CLASS_HID_243ac = 0x243ac,
- BNXT_ULP_CLASS_HID_20c10 = 0x20c10,
- BNXT_ULP_CLASS_HID_21864 = 0x21864,
- BNXT_ULP_CLASS_HID_130c8 = 0x130c8,
- BNXT_ULP_CLASS_HID_11cdc = 0x11cdc,
- BNXT_ULP_CLASS_HID_150cc = 0x150cc,
- BNXT_ULP_CLASS_HID_13d20 = 0x13d20,
- BNXT_ULP_CLASS_HID_3529c = 0x3529c,
- BNXT_ULP_CLASS_HID_33ef0 = 0x33ef0,
- BNXT_ULP_CLASS_HID_372e0 = 0x372e0,
- BNXT_ULP_CLASS_HID_35ef4 = 0x35ef4,
- BNXT_ULP_CLASS_HID_2dfc = 0x2dfc,
- BNXT_ULP_CLASS_HID_39e0 = 0x39e0,
- BNXT_ULP_CLASS_HID_4530 = 0x4530,
- BNXT_ULP_CLASS_HID_5124 = 0x5124,
- BNXT_ULP_CLASS_HID_4df0 = 0x4df0,
- BNXT_ULP_CLASS_HID_59e4 = 0x59e4,
- BNXT_ULP_CLASS_HID_1c78 = 0x1c78,
- BNXT_ULP_CLASS_HID_7118 = 0x7118,
- BNXT_ULP_CLASS_HID_0998 = 0x0998,
- BNXT_ULP_CLASS_HID_158c = 0x158c,
- BNXT_ULP_CLASS_HID_20dc = 0x20dc,
- BNXT_ULP_CLASS_HID_0cc0 = 0x0cc0,
- BNXT_ULP_CLASS_HID_299c = 0x299c,
- BNXT_ULP_CLASS_HID_3580 = 0x3580,
- BNXT_ULP_CLASS_HID_40d0 = 0x40d0,
- BNXT_ULP_CLASS_HID_2cc4 = 0x2cc4,
- BNXT_ULP_CLASS_HID_55a4 = 0x55a4,
- BNXT_ULP_CLASS_HID_21b8 = 0x21b8,
- BNXT_ULP_CLASS_HID_75a8 = 0x75a8,
- BNXT_ULP_CLASS_HID_41bc = 0x41bc,
- BNXT_ULP_CLASS_HID_27778 = 0x27778,
- BNXT_ULP_CLASS_HID_2438c = 0x2438c,
- BNXT_ULP_CLASS_HID_20c30 = 0x20c30,
- BNXT_ULP_CLASS_HID_21844 = 0x21844,
- BNXT_ULP_CLASS_HID_130e8 = 0x130e8,
- BNXT_ULP_CLASS_HID_11cfc = 0x11cfc,
- BNXT_ULP_CLASS_HID_150ec = 0x150ec,
- BNXT_ULP_CLASS_HID_13d00 = 0x13d00,
- BNXT_ULP_CLASS_HID_352bc = 0x352bc,
- BNXT_ULP_CLASS_HID_33ed0 = 0x33ed0,
- BNXT_ULP_CLASS_HID_372c0 = 0x372c0,
- BNXT_ULP_CLASS_HID_35ed4 = 0x35ed4,
- BNXT_ULP_CLASS_HID_3866 = 0x3866,
- BNXT_ULP_CLASS_HID_381e = 0x381e,
- BNXT_ULP_CLASS_HID_3860 = 0x3860,
- BNXT_ULP_CLASS_HID_0454 = 0x0454,
- BNXT_ULP_CLASS_HID_3818 = 0x3818,
- BNXT_ULP_CLASS_HID_042c = 0x042c,
- BNXT_ULP_CLASS_HID_3846 = 0x3846,
- BNXT_ULP_CLASS_HID_387e = 0x387e,
- BNXT_ULP_CLASS_HID_3ba6 = 0x3ba6,
- BNXT_ULP_CLASS_HID_385e = 0x385e,
- BNXT_ULP_CLASS_HID_3840 = 0x3840,
- BNXT_ULP_CLASS_HID_0474 = 0x0474,
- BNXT_ULP_CLASS_HID_3878 = 0x3878,
- BNXT_ULP_CLASS_HID_044c = 0x044c,
- BNXT_ULP_CLASS_HID_3ba0 = 0x3ba0,
- BNXT_ULP_CLASS_HID_0794 = 0x0794,
- BNXT_ULP_CLASS_HID_3858 = 0x3858,
- BNXT_ULP_CLASS_HID_046c = 0x046c
+ BNXT_ULP_CLASS_HID_00b8 = 0x00b8,
+ BNXT_ULP_CLASS_HID_0cc2 = 0x0cc2,
+ BNXT_ULP_CLASS_HID_10e4 = 0x10e4,
+ BNXT_ULP_CLASS_HID_1d0e = 0x1d0e,
+ BNXT_ULP_CLASS_HID_0286 = 0x0286,
+ BNXT_ULP_CLASS_HID_0e98 = 0x0e98,
+ BNXT_ULP_CLASS_HID_1666 = 0x1666,
+ BNXT_ULP_CLASS_HID_02de = 0x02de,
+ BNXT_ULP_CLASS_HID_81d25 = 0x81d25,
+ BNXT_ULP_CLASS_HID_809ad = 0x809ad,
+ BNXT_ULP_CLASS_HID_80ae3 = 0x80ae3,
+ BNXT_ULP_CLASS_HID_8170d = 0x8170d,
+ BNXT_ULP_CLASS_HID_80773 = 0x80773,
+ BNXT_ULP_CLASS_HID_8139d = 0x8139d,
+ BNXT_ULP_CLASS_HID_814d3 = 0x814d3,
+ BNXT_ULP_CLASS_HID_8015b = 0x8015b,
+ BNXT_ULP_CLASS_HID_21977 = 0x21977,
+ BNXT_ULP_CLASS_HID_205ef = 0x205ef,
+ BNXT_ULP_CLASS_HID_20735 = 0x20735,
+ BNXT_ULP_CLASS_HID_2134f = 0x2134f,
+ BNXT_ULP_CLASS_HID_61beb = 0x61beb,
+ BNXT_ULP_CLASS_HID_60863 = 0x60863,
+ BNXT_ULP_CLASS_HID_609a9 = 0x609a9,
+ BNXT_ULP_CLASS_HID_615c3 = 0x615c3,
+ BNXT_ULP_CLASS_HID_00a8 = 0x00a8,
+ BNXT_ULP_CLASS_HID_0cd2 = 0x0cd2,
+ BNXT_ULP_CLASS_HID_10f4 = 0x10f4,
+ BNXT_ULP_CLASS_HID_1d1e = 0x1d1e,
+ BNXT_ULP_CLASS_HID_1488 = 0x1488,
+ BNXT_ULP_CLASS_HID_0110 = 0x0110,
+ BNXT_ULP_CLASS_HID_0532 = 0x0532,
+ BNXT_ULP_CLASS_HID_115c = 0x115c,
+ BNXT_ULP_CLASS_HID_0ab8 = 0x0ab8,
+ BNXT_ULP_CLASS_HID_16a2 = 0x16a2,
+ BNXT_ULP_CLASS_HID_1ac4 = 0x1ac4,
+ BNXT_ULP_CLASS_HID_074c = 0x074c,
+ BNXT_ULP_CLASS_HID_1e98 = 0x1e98,
+ BNXT_ULP_CLASS_HID_0ae0 = 0x0ae0,
+ BNXT_ULP_CLASS_HID_0f02 = 0x0f02,
+ BNXT_ULP_CLASS_HID_1b2c = 0x1b2c,
+ BNXT_ULP_CLASS_HID_0296 = 0x0296,
+ BNXT_ULP_CLASS_HID_0e88 = 0x0e88,
+ BNXT_ULP_CLASS_HID_1676 = 0x1676,
+ BNXT_ULP_CLASS_HID_02ce = 0x02ce,
+ BNXT_ULP_CLASS_HID_8076e = 0x8076e,
+ BNXT_ULP_CLASS_HID_81380 = 0x81380,
+ BNXT_ULP_CLASS_HID_81b4e = 0x81b4e,
+ BNXT_ULP_CLASS_HID_807c6 = 0x807c6,
+ BNXT_ULP_CLASS_HID_404ea = 0x404ea,
+ BNXT_ULP_CLASS_HID_4110c = 0x4110c,
+ BNXT_ULP_CLASS_HID_418ca = 0x418ca,
+ BNXT_ULP_CLASS_HID_40542 = 0x40542,
+ BNXT_ULP_CLASS_HID_c09e2 = 0xc09e2,
+ BNXT_ULP_CLASS_HID_c1604 = 0xc1604,
+ BNXT_ULP_CLASS_HID_c1dc2 = 0xc1dc2,
+ BNXT_ULP_CLASS_HID_c0a5a = 0xc0a5a,
+ BNXT_ULP_CLASS_HID_0098 = 0x0098,
+ BNXT_ULP_CLASS_HID_0ce2 = 0x0ce2,
+ BNXT_ULP_CLASS_HID_10c4 = 0x10c4,
+ BNXT_ULP_CLASS_HID_1d2e = 0x1d2e,
+ BNXT_ULP_CLASS_HID_14b8 = 0x14b8,
+ BNXT_ULP_CLASS_HID_0120 = 0x0120,
+ BNXT_ULP_CLASS_HID_0502 = 0x0502,
+ BNXT_ULP_CLASS_HID_116c = 0x116c,
+ BNXT_ULP_CLASS_HID_0a88 = 0x0a88,
+ BNXT_ULP_CLASS_HID_1692 = 0x1692,
+ BNXT_ULP_CLASS_HID_1af4 = 0x1af4,
+ BNXT_ULP_CLASS_HID_077c = 0x077c,
+ BNXT_ULP_CLASS_HID_1ea8 = 0x1ea8,
+ BNXT_ULP_CLASS_HID_0ad0 = 0x0ad0,
+ BNXT_ULP_CLASS_HID_0f32 = 0x0f32,
+ BNXT_ULP_CLASS_HID_1b1c = 0x1b1c,
+ BNXT_ULP_CLASS_HID_02a6 = 0x02a6,
+ BNXT_ULP_CLASS_HID_0eb8 = 0x0eb8,
+ BNXT_ULP_CLASS_HID_1646 = 0x1646,
+ BNXT_ULP_CLASS_HID_02fe = 0x02fe,
+ BNXT_ULP_CLASS_HID_8075e = 0x8075e,
+ BNXT_ULP_CLASS_HID_813b0 = 0x813b0,
+ BNXT_ULP_CLASS_HID_81b7e = 0x81b7e,
+ BNXT_ULP_CLASS_HID_807f6 = 0x807f6,
+ BNXT_ULP_CLASS_HID_404da = 0x404da,
+ BNXT_ULP_CLASS_HID_4113c = 0x4113c,
+ BNXT_ULP_CLASS_HID_418fa = 0x418fa,
+ BNXT_ULP_CLASS_HID_40572 = 0x40572,
+ BNXT_ULP_CLASS_HID_c09d2 = 0xc09d2,
+ BNXT_ULP_CLASS_HID_c1634 = 0xc1634,
+ BNXT_ULP_CLASS_HID_c1df2 = 0xc1df2,
+ BNXT_ULP_CLASS_HID_c0a6a = 0xc0a6a,
+ BNXT_ULP_CLASS_HID_81d35 = 0x81d35,
+ BNXT_ULP_CLASS_HID_809bd = 0x809bd,
+ BNXT_ULP_CLASS_HID_80af3 = 0x80af3,
+ BNXT_ULP_CLASS_HID_8171d = 0x8171d,
+ BNXT_ULP_CLASS_HID_80763 = 0x80763,
+ BNXT_ULP_CLASS_HID_8138d = 0x8138d,
+ BNXT_ULP_CLASS_HID_814c3 = 0x814c3,
+ BNXT_ULP_CLASS_HID_8014b = 0x8014b,
+ BNXT_ULP_CLASS_HID_c001f = 0xc001f,
+ BNXT_ULP_CLASS_HID_c0c39 = 0xc0c39,
+ BNXT_ULP_CLASS_HID_c0d7f = 0xc0d7f,
+ BNXT_ULP_CLASS_HID_c1999 = 0xc1999,
+ BNXT_ULP_CLASS_HID_c09ef = 0xc09ef,
+ BNXT_ULP_CLASS_HID_c1609 = 0xc1609,
+ BNXT_ULP_CLASS_HID_c174f = 0xc174f,
+ BNXT_ULP_CLASS_HID_c03d7 = 0xc03d7,
+ BNXT_ULP_CLASS_HID_a1e73 = 0xa1e73,
+ BNXT_ULP_CLASS_HID_a0afb = 0xa0afb,
+ BNXT_ULP_CLASS_HID_a0c31 = 0xa0c31,
+ BNXT_ULP_CLASS_HID_a185b = 0xa185b,
+ BNXT_ULP_CLASS_HID_a08a1 = 0xa08a1,
+ BNXT_ULP_CLASS_HID_a14cb = 0xa14cb,
+ BNXT_ULP_CLASS_HID_a1601 = 0xa1601,
+ BNXT_ULP_CLASS_HID_a0289 = 0xa0289,
+ BNXT_ULP_CLASS_HID_e015d = 0xe015d,
+ BNXT_ULP_CLASS_HID_e0d47 = 0xe0d47,
+ BNXT_ULP_CLASS_HID_e0ebd = 0xe0ebd,
+ BNXT_ULP_CLASS_HID_e1aa7 = 0xe1aa7,
+ BNXT_ULP_CLASS_HID_e0b2d = 0xe0b2d,
+ BNXT_ULP_CLASS_HID_e1757 = 0xe1757,
+ BNXT_ULP_CLASS_HID_e188d = 0xe188d,
+ BNXT_ULP_CLASS_HID_e0515 = 0xe0515,
+ BNXT_ULP_CLASS_HID_21967 = 0x21967,
+ BNXT_ULP_CLASS_HID_205ff = 0x205ff,
+ BNXT_ULP_CLASS_HID_20725 = 0x20725,
+ BNXT_ULP_CLASS_HID_2135f = 0x2135f,
+ BNXT_ULP_CLASS_HID_61bfb = 0x61bfb,
+ BNXT_ULP_CLASS_HID_60873 = 0x60873,
+ BNXT_ULP_CLASS_HID_609b9 = 0x609b9,
+ BNXT_ULP_CLASS_HID_615d3 = 0x615d3,
+ BNXT_ULP_CLASS_HID_30a55 = 0x30a55,
+ BNXT_ULP_CLASS_HID_3164f = 0x3164f,
+ BNXT_ULP_CLASS_HID_317b5 = 0x317b5,
+ BNXT_ULP_CLASS_HID_3040d = 0x3040d,
+ BNXT_ULP_CLASS_HID_70ca9 = 0x70ca9,
+ BNXT_ULP_CLASS_HID_718c3 = 0x718c3,
+ BNXT_ULP_CLASS_HID_71a09 = 0x71a09,
+ BNXT_ULP_CLASS_HID_70681 = 0x70681,
+ BNXT_ULP_CLASS_HID_2821d = 0x2821d,
+ BNXT_ULP_CLASS_HID_28e37 = 0x28e37,
+ BNXT_ULP_CLASS_HID_28f7d = 0x28f7d,
+ BNXT_ULP_CLASS_HID_29b97 = 0x29b97,
+ BNXT_ULP_CLASS_HID_68491 = 0x68491,
+ BNXT_ULP_CLASS_HID_6908b = 0x6908b,
+ BNXT_ULP_CLASS_HID_691f1 = 0x691f1,
+ BNXT_ULP_CLASS_HID_69deb = 0x69deb,
+ BNXT_ULP_CLASS_HID_3926d = 0x3926d,
+ BNXT_ULP_CLASS_HID_39e87 = 0x39e87,
+ BNXT_ULP_CLASS_HID_38023 = 0x38023,
+ BNXT_ULP_CLASS_HID_38c45 = 0x38c45,
+ BNXT_ULP_CLASS_HID_794e1 = 0x794e1,
+ BNXT_ULP_CLASS_HID_78179 = 0x78179,
+ BNXT_ULP_CLASS_HID_782a7 = 0x782a7,
+ BNXT_ULP_CLASS_HID_78ed9 = 0x78ed9,
+ BNXT_ULP_CLASS_HID_81d05 = 0x81d05,
+ BNXT_ULP_CLASS_HID_8098d = 0x8098d,
+ BNXT_ULP_CLASS_HID_80ac3 = 0x80ac3,
+ BNXT_ULP_CLASS_HID_8172d = 0x8172d,
+ BNXT_ULP_CLASS_HID_80753 = 0x80753,
+ BNXT_ULP_CLASS_HID_813bd = 0x813bd,
+ BNXT_ULP_CLASS_HID_814f3 = 0x814f3,
+ BNXT_ULP_CLASS_HID_8017b = 0x8017b,
+ BNXT_ULP_CLASS_HID_c002f = 0xc002f,
+ BNXT_ULP_CLASS_HID_c0c09 = 0xc0c09,
+ BNXT_ULP_CLASS_HID_c0d4f = 0xc0d4f,
+ BNXT_ULP_CLASS_HID_c19a9 = 0xc19a9,
+ BNXT_ULP_CLASS_HID_c09df = 0xc09df,
+ BNXT_ULP_CLASS_HID_c1639 = 0xc1639,
+ BNXT_ULP_CLASS_HID_c177f = 0xc177f,
+ BNXT_ULP_CLASS_HID_c03e7 = 0xc03e7,
+ BNXT_ULP_CLASS_HID_a1e43 = 0xa1e43,
+ BNXT_ULP_CLASS_HID_a0acb = 0xa0acb,
+ BNXT_ULP_CLASS_HID_a0c01 = 0xa0c01,
+ BNXT_ULP_CLASS_HID_a186b = 0xa186b,
+ BNXT_ULP_CLASS_HID_a0891 = 0xa0891,
+ BNXT_ULP_CLASS_HID_a14fb = 0xa14fb,
+ BNXT_ULP_CLASS_HID_a1631 = 0xa1631,
+ BNXT_ULP_CLASS_HID_a02b9 = 0xa02b9,
+ BNXT_ULP_CLASS_HID_e016d = 0xe016d,
+ BNXT_ULP_CLASS_HID_e0d77 = 0xe0d77,
+ BNXT_ULP_CLASS_HID_e0e8d = 0xe0e8d,
+ BNXT_ULP_CLASS_HID_e1a97 = 0xe1a97,
+ BNXT_ULP_CLASS_HID_e0b1d = 0xe0b1d,
+ BNXT_ULP_CLASS_HID_e1767 = 0xe1767,
+ BNXT_ULP_CLASS_HID_e18bd = 0xe18bd,
+ BNXT_ULP_CLASS_HID_e0525 = 0xe0525,
+ BNXT_ULP_CLASS_HID_21957 = 0x21957,
+ BNXT_ULP_CLASS_HID_205cf = 0x205cf,
+ BNXT_ULP_CLASS_HID_20715 = 0x20715,
+ BNXT_ULP_CLASS_HID_2136f = 0x2136f,
+ BNXT_ULP_CLASS_HID_61bcb = 0x61bcb,
+ BNXT_ULP_CLASS_HID_60843 = 0x60843,
+ BNXT_ULP_CLASS_HID_60989 = 0x60989,
+ BNXT_ULP_CLASS_HID_615e3 = 0x615e3,
+ BNXT_ULP_CLASS_HID_30a65 = 0x30a65,
+ BNXT_ULP_CLASS_HID_3167f = 0x3167f,
+ BNXT_ULP_CLASS_HID_31785 = 0x31785,
+ BNXT_ULP_CLASS_HID_3043d = 0x3043d,
+ BNXT_ULP_CLASS_HID_70c99 = 0x70c99,
+ BNXT_ULP_CLASS_HID_718f3 = 0x718f3,
+ BNXT_ULP_CLASS_HID_71a39 = 0x71a39,
+ BNXT_ULP_CLASS_HID_706b1 = 0x706b1,
+ BNXT_ULP_CLASS_HID_2822d = 0x2822d,
+ BNXT_ULP_CLASS_HID_28e07 = 0x28e07,
+ BNXT_ULP_CLASS_HID_28f4d = 0x28f4d,
+ BNXT_ULP_CLASS_HID_29ba7 = 0x29ba7,
+ BNXT_ULP_CLASS_HID_684a1 = 0x684a1,
+ BNXT_ULP_CLASS_HID_690bb = 0x690bb,
+ BNXT_ULP_CLASS_HID_691c1 = 0x691c1,
+ BNXT_ULP_CLASS_HID_69ddb = 0x69ddb,
+ BNXT_ULP_CLASS_HID_3925d = 0x3925d,
+ BNXT_ULP_CLASS_HID_39eb7 = 0x39eb7,
+ BNXT_ULP_CLASS_HID_38013 = 0x38013,
+ BNXT_ULP_CLASS_HID_38c75 = 0x38c75,
+ BNXT_ULP_CLASS_HID_794d1 = 0x794d1,
+ BNXT_ULP_CLASS_HID_78149 = 0x78149,
+ BNXT_ULP_CLASS_HID_78297 = 0x78297,
+ BNXT_ULP_CLASS_HID_78ee9 = 0x78ee9,
+ BNXT_ULP_CLASS_HID_0816 = 0x0816,
+ BNXT_ULP_CLASS_HID_1852 = 0x1852,
+ BNXT_ULP_CLASS_HID_09f4 = 0x09f4,
+ BNXT_ULP_CLASS_HID_1dd4 = 0x1dd4,
+ BNXT_ULP_CLASS_HID_804f1 = 0x804f1,
+ BNXT_ULP_CLASS_HID_81251 = 0x81251,
+ BNXT_ULP_CLASS_HID_80ee1 = 0x80ee1,
+ BNXT_ULP_CLASS_HID_81c41 = 0x81c41,
+ BNXT_ULP_CLASS_HID_2013b = 0x2013b,
+ BNXT_ULP_CLASS_HID_20e9b = 0x20e9b,
+ BNXT_ULP_CLASS_HID_603bf = 0x603bf,
+ BNXT_ULP_CLASS_HID_6111f = 0x6111f,
+ BNXT_ULP_CLASS_HID_0806 = 0x0806,
+ BNXT_ULP_CLASS_HID_1842 = 0x1842,
+ BNXT_ULP_CLASS_HID_1be6 = 0x1be6,
+ BNXT_ULP_CLASS_HID_0c80 = 0x0c80,
+ BNXT_ULP_CLASS_HID_1216 = 0x1216,
+ BNXT_ULP_CLASS_HID_02b0 = 0x02b0,
+ BNXT_ULP_CLASS_HID_0654 = 0x0654,
+ BNXT_ULP_CLASS_HID_1690 = 0x1690,
+ BNXT_ULP_CLASS_HID_09e4 = 0x09e4,
+ BNXT_ULP_CLASS_HID_1dc4 = 0x1dc4,
+ BNXT_ULP_CLASS_HID_80efc = 0x80efc,
+ BNXT_ULP_CLASS_HID_80332 = 0x80332,
+ BNXT_ULP_CLASS_HID_40c78 = 0x40c78,
+ BNXT_ULP_CLASS_HID_400be = 0x400be,
+ BNXT_ULP_CLASS_HID_c1170 = 0xc1170,
+ BNXT_ULP_CLASS_HID_c05b6 = 0xc05b6,
+ BNXT_ULP_CLASS_HID_0836 = 0x0836,
+ BNXT_ULP_CLASS_HID_1872 = 0x1872,
+ BNXT_ULP_CLASS_HID_1bd6 = 0x1bd6,
+ BNXT_ULP_CLASS_HID_0cb0 = 0x0cb0,
+ BNXT_ULP_CLASS_HID_1226 = 0x1226,
+ BNXT_ULP_CLASS_HID_0280 = 0x0280,
+ BNXT_ULP_CLASS_HID_0664 = 0x0664,
+ BNXT_ULP_CLASS_HID_16a0 = 0x16a0,
+ BNXT_ULP_CLASS_HID_09d4 = 0x09d4,
+ BNXT_ULP_CLASS_HID_1df4 = 0x1df4,
+ BNXT_ULP_CLASS_HID_80ecc = 0x80ecc,
+ BNXT_ULP_CLASS_HID_80302 = 0x80302,
+ BNXT_ULP_CLASS_HID_40c48 = 0x40c48,
+ BNXT_ULP_CLASS_HID_4008e = 0x4008e,
+ BNXT_ULP_CLASS_HID_c1140 = 0xc1140,
+ BNXT_ULP_CLASS_HID_c0586 = 0xc0586,
+ BNXT_ULP_CLASS_HID_804e1 = 0x804e1,
+ BNXT_ULP_CLASS_HID_81241 = 0x81241,
+ BNXT_ULP_CLASS_HID_80ef1 = 0x80ef1,
+ BNXT_ULP_CLASS_HID_81c51 = 0x81c51,
+ BNXT_ULP_CLASS_HID_c076d = 0xc076d,
+ BNXT_ULP_CLASS_HID_c14cd = 0xc14cd,
+ BNXT_ULP_CLASS_HID_c117d = 0xc117d,
+ BNXT_ULP_CLASS_HID_c1edd = 0xc1edd,
+ BNXT_ULP_CLASS_HID_a062f = 0xa062f,
+ BNXT_ULP_CLASS_HID_a138f = 0xa138f,
+ BNXT_ULP_CLASS_HID_a103f = 0xa103f,
+ BNXT_ULP_CLASS_HID_a1d9f = 0xa1d9f,
+ BNXT_ULP_CLASS_HID_e08ab = 0xe08ab,
+ BNXT_ULP_CLASS_HID_e160b = 0xe160b,
+ BNXT_ULP_CLASS_HID_e12bb = 0xe12bb,
+ BNXT_ULP_CLASS_HID_e0079 = 0xe0079,
+ BNXT_ULP_CLASS_HID_2012b = 0x2012b,
+ BNXT_ULP_CLASS_HID_20e8b = 0x20e8b,
+ BNXT_ULP_CLASS_HID_603af = 0x603af,
+ BNXT_ULP_CLASS_HID_6110f = 0x6110f,
+ BNXT_ULP_CLASS_HID_311bb = 0x311bb,
+ BNXT_ULP_CLASS_HID_31f1b = 0x31f1b,
+ BNXT_ULP_CLASS_HID_7143f = 0x7143f,
+ BNXT_ULP_CLASS_HID_701fd = 0x701fd,
+ BNXT_ULP_CLASS_HID_28963 = 0x28963,
+ BNXT_ULP_CLASS_HID_296c3 = 0x296c3,
+ BNXT_ULP_CLASS_HID_68be7 = 0x68be7,
+ BNXT_ULP_CLASS_HID_69947 = 0x69947,
+ BNXT_ULP_CLASS_HID_399f3 = 0x399f3,
+ BNXT_ULP_CLASS_HID_387b1 = 0x387b1,
+ BNXT_ULP_CLASS_HID_79c77 = 0x79c77,
+ BNXT_ULP_CLASS_HID_78a35 = 0x78a35,
+ BNXT_ULP_CLASS_HID_804d1 = 0x804d1,
+ BNXT_ULP_CLASS_HID_81271 = 0x81271,
+ BNXT_ULP_CLASS_HID_80ec1 = 0x80ec1,
+ BNXT_ULP_CLASS_HID_81c61 = 0x81c61,
+ BNXT_ULP_CLASS_HID_c075d = 0xc075d,
+ BNXT_ULP_CLASS_HID_c14fd = 0xc14fd,
+ BNXT_ULP_CLASS_HID_c114d = 0xc114d,
+ BNXT_ULP_CLASS_HID_c1eed = 0xc1eed,
+ BNXT_ULP_CLASS_HID_a061f = 0xa061f,
+ BNXT_ULP_CLASS_HID_a13bf = 0xa13bf,
+ BNXT_ULP_CLASS_HID_a100f = 0xa100f,
+ BNXT_ULP_CLASS_HID_a1daf = 0xa1daf,
+ BNXT_ULP_CLASS_HID_e089b = 0xe089b,
+ BNXT_ULP_CLASS_HID_e163b = 0xe163b,
+ BNXT_ULP_CLASS_HID_e128b = 0xe128b,
+ BNXT_ULP_CLASS_HID_e0049 = 0xe0049,
+ BNXT_ULP_CLASS_HID_2011b = 0x2011b,
+ BNXT_ULP_CLASS_HID_20ebb = 0x20ebb,
+ BNXT_ULP_CLASS_HID_6039f = 0x6039f,
+ BNXT_ULP_CLASS_HID_6113f = 0x6113f,
+ BNXT_ULP_CLASS_HID_3118b = 0x3118b,
+ BNXT_ULP_CLASS_HID_31f2b = 0x31f2b,
+ BNXT_ULP_CLASS_HID_7140f = 0x7140f,
+ BNXT_ULP_CLASS_HID_701cd = 0x701cd,
+ BNXT_ULP_CLASS_HID_28953 = 0x28953,
+ BNXT_ULP_CLASS_HID_296f3 = 0x296f3,
+ BNXT_ULP_CLASS_HID_68bd7 = 0x68bd7,
+ BNXT_ULP_CLASS_HID_69977 = 0x69977,
+ BNXT_ULP_CLASS_HID_399c3 = 0x399c3,
+ BNXT_ULP_CLASS_HID_38781 = 0x38781,
+ BNXT_ULP_CLASS_HID_79c47 = 0x79c47,
+ BNXT_ULP_CLASS_HID_78a05 = 0x78a05,
+ BNXT_ULP_CLASS_HID_04a4 = 0x04a4,
+ BNXT_ULP_CLASS_HID_04a8 = 0x04a8,
+ BNXT_ULP_CLASS_HID_04a5 = 0x04a5,
+ BNXT_ULP_CLASS_HID_1205 = 0x1205,
+ BNXT_ULP_CLASS_HID_04a9 = 0x04a9,
+ BNXT_ULP_CLASS_HID_1209 = 0x1209,
+ BNXT_ULP_CLASS_HID_04b4 = 0x04b4,
+ BNXT_ULP_CLASS_HID_04b8 = 0x04b8,
+ BNXT_ULP_CLASS_HID_0484 = 0x0484,
+ BNXT_ULP_CLASS_HID_0488 = 0x0488,
+ BNXT_ULP_CLASS_HID_04b5 = 0x04b5,
+ BNXT_ULP_CLASS_HID_1215 = 0x1215,
+ BNXT_ULP_CLASS_HID_04b9 = 0x04b9,
+ BNXT_ULP_CLASS_HID_1219 = 0x1219,
+ BNXT_ULP_CLASS_HID_0485 = 0x0485,
+ BNXT_ULP_CLASS_HID_1225 = 0x1225,
+ BNXT_ULP_CLASS_HID_0489 = 0x0489,
+ BNXT_ULP_CLASS_HID_1229 = 0x1229,
+ BNXT_ULP_CLASS_HID_0226 = 0x0226,
+ BNXT_ULP_CLASS_HID_4045a = 0x4045a,
+ BNXT_ULP_CLASS_HID_0daa = 0x0daa,
+ BNXT_ULP_CLASS_HID_11b0 = 0x11b0,
+ BNXT_ULP_CLASS_HID_403f8 = 0x403f8,
+ BNXT_ULP_CLASS_HID_4161e = 0x4161e,
+ BNXT_ULP_CLASS_HID_40439 = 0x40439,
+ BNXT_ULP_CLASS_HID_41405 = 0x41405,
+ BNXT_ULP_CLASS_HID_51449 = 0x51449,
+ BNXT_ULP_CLASS_HID_50b33 = 0x50b33,
+ BNXT_ULP_CLASS_HID_48c01 = 0x48c01,
+ BNXT_ULP_CLASS_HID_483eb = 0x483eb,
+ BNXT_ULP_CLASS_HID_5833f = 0x5833f,
+ BNXT_ULP_CLASS_HID_5937b = 0x5937b,
+ BNXT_ULP_CLASS_HID_41875 = 0x41875,
+ BNXT_ULP_CLASS_HID_40f5f = 0x40f5f,
+ BNXT_ULP_CLASS_HID_50f23 = 0x50f23,
+ BNXT_ULP_CLASS_HID_51f6f = 0x51f6f,
+ BNXT_ULP_CLASS_HID_4875b = 0x4875b,
+ BNXT_ULP_CLASS_HID_49727 = 0x49727,
+ BNXT_ULP_CLASS_HID_5976b = 0x5976b,
+ BNXT_ULP_CLASS_HID_58655 = 0x58655,
+ BNXT_ULP_CLASS_HID_4125f = 0x4125f,
+ BNXT_ULP_CLASS_HID_401f9 = 0x401f9,
+ BNXT_ULP_CLASS_HID_501cd = 0x501cd,
+ BNXT_ULP_CLASS_HID_51149 = 0x51149,
+ BNXT_ULP_CLASS_HID_49a67 = 0x49a67,
+ BNXT_ULP_CLASS_HID_489c1 = 0x489c1,
+ BNXT_ULP_CLASS_HID_58955 = 0x58955,
+ BNXT_ULP_CLASS_HID_59951 = 0x59951,
+ BNXT_ULP_CLASS_HID_40569 = 0x40569,
+ BNXT_ULP_CLASS_HID_41575 = 0x41575,
+ BNXT_ULP_CLASS_HID_51579 = 0x51579,
+ BNXT_ULP_CLASS_HID_50463 = 0x50463,
+ BNXT_ULP_CLASS_HID_48d71 = 0x48d71,
+ BNXT_ULP_CLASS_HID_49d7d = 0x49d7d,
+ BNXT_ULP_CLASS_HID_59d41 = 0x59d41,
+ BNXT_ULP_CLASS_HID_58c6b = 0x58c6b,
+ BNXT_ULP_CLASS_HID_10255 = 0x10255,
+ BNXT_ULP_CLASS_HID_11675 = 0x11675,
+ BNXT_ULP_CLASS_HID_14649 = 0x14649,
+ BNXT_ULP_CLASS_HID_15a69 = 0x15a69,
+ BNXT_ULP_CLASS_HID_1205b = 0x1205b,
+ BNXT_ULP_CLASS_HID_1347b = 0x1347b,
+ BNXT_ULP_CLASS_HID_16bbf = 0x16bbf,
+ BNXT_ULP_CLASS_HID_1785f = 0x1785f,
+ BNXT_ULP_CLASS_HID_11551 = 0x11551,
+ BNXT_ULP_CLASS_HID_10897 = 0x10897,
+ BNXT_ULP_CLASS_HID_15955 = 0x15955,
+ BNXT_ULP_CLASS_HID_14c8b = 0x14c8b,
+ BNXT_ULP_CLASS_HID_13b47 = 0x13b47,
+ BNXT_ULP_CLASS_HID_12e85 = 0x12e85,
+ BNXT_ULP_CLASS_HID_17f5b = 0x17f5b,
+ BNXT_ULP_CLASS_HID_17299 = 0x17299,
+ BNXT_ULP_CLASS_HID_10fe7 = 0x10fe7,
+ BNXT_ULP_CLASS_HID_10325 = 0x10325,
+ BNXT_ULP_CLASS_HID_153cb = 0x153cb,
+ BNXT_ULP_CLASS_HID_14709 = 0x14709,
+ BNXT_ULP_CLASS_HID_12dc5 = 0x12dc5,
+ BNXT_ULP_CLASS_HID_1212b = 0x1212b,
+ BNXT_ULP_CLASS_HID_171c9 = 0x171c9,
+ BNXT_ULP_CLASS_HID_1650f = 0x1650f,
+ BNXT_ULP_CLASS_HID_10201 = 0x10201,
+ BNXT_ULP_CLASS_HID_116c1 = 0x116c1,
+ BNXT_ULP_CLASS_HID_14605 = 0x14605,
+ BNXT_ULP_CLASS_HID_15a05 = 0x15a05,
+ BNXT_ULP_CLASS_HID_12007 = 0x12007,
+ BNXT_ULP_CLASS_HID_13407 = 0x13407,
+ BNXT_ULP_CLASS_HID_1640b = 0x1640b,
+ BNXT_ULP_CLASS_HID_1780b = 0x1780b,
+ BNXT_ULP_CLASS_HID_404b0 = 0x404b0,
+ BNXT_ULP_CLASS_HID_4148c = 0x4148c,
+ BNXT_ULP_CLASS_HID_514c0 = 0x514c0,
+ BNXT_ULP_CLASS_HID_50bba = 0x50bba,
+ BNXT_ULP_CLASS_HID_48c88 = 0x48c88,
+ BNXT_ULP_CLASS_HID_48362 = 0x48362,
+ BNXT_ULP_CLASS_HID_583b6 = 0x583b6,
+ BNXT_ULP_CLASS_HID_593f2 = 0x593f2,
+ BNXT_ULP_CLASS_HID_41f54 = 0x41f54,
+ BNXT_ULP_CLASS_HID_40fce = 0x40fce,
+ BNXT_ULP_CLASS_HID_50e02 = 0x50e02,
+ BNXT_ULP_CLASS_HID_51e5e = 0x51e5e,
+ BNXT_ULP_CLASS_HID_487ca = 0x487ca,
+ BNXT_ULP_CLASS_HID_49606 = 0x49606,
+ BNXT_ULP_CLASS_HID_5965a = 0x5965a,
+ BNXT_ULP_CLASS_HID_58514 = 0x58514,
+ BNXT_ULP_CLASS_HID_412c2 = 0x412c2,
+ BNXT_ULP_CLASS_HID_401ac = 0x401ac,
+ BNXT_ULP_CLASS_HID_501e0 = 0x501e0,
+ BNXT_ULP_CLASS_HID_511cc = 0x511cc,
+ BNXT_ULP_CLASS_HID_4990a = 0x4990a,
+ BNXT_ULP_CLASS_HID_489e4 = 0x489e4,
+ BNXT_ULP_CLASS_HID_589c8 = 0x589c8,
+ BNXT_ULP_CLASS_HID_59804 = 0x59804,
+ BNXT_ULP_CLASS_HID_40404 = 0x40404,
+ BNXT_ULP_CLASS_HID_41440 = 0x41440,
+ BNXT_ULP_CLASS_HID_51484 = 0x51484,
+ BNXT_ULP_CLASS_HID_50b0e = 0x50b0e,
+ BNXT_ULP_CLASS_HID_48c4c = 0x48c4c,
+ BNXT_ULP_CLASS_HID_48306 = 0x48306,
+ BNXT_ULP_CLASS_HID_5830a = 0x5830a,
+ BNXT_ULP_CLASS_HID_59346 = 0x59346,
+ BNXT_ULP_CLASS_HID_102cc = 0x102cc,
+ BNXT_ULP_CLASS_HID_116ec = 0x116ec,
+ BNXT_ULP_CLASS_HID_146d0 = 0x146d0,
+ BNXT_ULP_CLASS_HID_15af0 = 0x15af0,
+ BNXT_ULP_CLASS_HID_120c2 = 0x120c2,
+ BNXT_ULP_CLASS_HID_134e2 = 0x134e2,
+ BNXT_ULP_CLASS_HID_16b26 = 0x16b26,
+ BNXT_ULP_CLASS_HID_178c6 = 0x178c6,
+ BNXT_ULP_CLASS_HID_115c6 = 0x115c6,
+ BNXT_ULP_CLASS_HID_10804 = 0x10804,
+ BNXT_ULP_CLASS_HID_15822 = 0x15822,
+ BNXT_ULP_CLASS_HID_14c60 = 0x14c60,
+ BNXT_ULP_CLASS_HID_13bd4 = 0x13bd4,
+ BNXT_ULP_CLASS_HID_12e12 = 0x12e12,
+ BNXT_ULP_CLASS_HID_17e30 = 0x17e30,
+ BNXT_ULP_CLASS_HID_17276 = 0x17276,
+ BNXT_ULP_CLASS_HID_11f1a = 0x11f1a,
+ BNXT_ULP_CLASS_HID_11358 = 0x11358,
+ BNXT_ULP_CLASS_HID_14398 = 0x14398,
+ BNXT_ULP_CLASS_HID_157b8 = 0x157b8,
+ BNXT_ULP_CLASS_HID_13d68 = 0x13d68,
+ BNXT_ULP_CLASS_HID_131aa = 0x131aa,
+ BNXT_ULP_CLASS_HID_16192 = 0x16192,
+ BNXT_ULP_CLASS_HID_175b2 = 0x175b2,
+ BNXT_ULP_CLASS_HID_112b2 = 0x112b2,
+ BNXT_ULP_CLASS_HID_106f0 = 0x106f0,
+ BNXT_ULP_CLASS_HID_15692 = 0x15692,
+ BNXT_ULP_CLASS_HID_14ad0 = 0x14ad0,
+ BNXT_ULP_CLASS_HID_13080 = 0x13080,
+ BNXT_ULP_CLASS_HID_124c2 = 0x124c2,
+ BNXT_ULP_CLASS_HID_174e0 = 0x174e0,
+ BNXT_ULP_CLASS_HID_16f22 = 0x16f22,
+ BNXT_ULP_CLASS_HID_4025b = 0x4025b,
+ BNXT_ULP_CLASS_HID_41267 = 0x41267,
+ BNXT_ULP_CLASS_HID_5122b = 0x5122b,
+ BNXT_ULP_CLASS_HID_50d51 = 0x50d51,
+ BNXT_ULP_CLASS_HID_48a63 = 0x48a63,
+ BNXT_ULP_CLASS_HID_48589 = 0x48589,
+ BNXT_ULP_CLASS_HID_5855d = 0x5855d,
+ BNXT_ULP_CLASS_HID_59519 = 0x59519,
+ BNXT_ULP_CLASS_HID_41e17 = 0x41e17,
+ BNXT_ULP_CLASS_HID_4093d = 0x4093d,
+ BNXT_ULP_CLASS_HID_50941 = 0x50941,
+ BNXT_ULP_CLASS_HID_5190d = 0x5190d,
+ BNXT_ULP_CLASS_HID_48139 = 0x48139,
+ BNXT_ULP_CLASS_HID_49145 = 0x49145,
+ BNXT_ULP_CLASS_HID_59109 = 0x59109,
+ BNXT_ULP_CLASS_HID_58037 = 0x58037,
+ BNXT_ULP_CLASS_HID_4143d = 0x4143d,
+ BNXT_ULP_CLASS_HID_4079b = 0x4079b,
+ BNXT_ULP_CLASS_HID_507af = 0x507af,
+ BNXT_ULP_CLASS_HID_5172b = 0x5172b,
+ BNXT_ULP_CLASS_HID_49c05 = 0x49c05,
+ BNXT_ULP_CLASS_HID_48fa3 = 0x48fa3,
+ BNXT_ULP_CLASS_HID_58f37 = 0x58f37,
+ BNXT_ULP_CLASS_HID_59f33 = 0x59f33,
+ BNXT_ULP_CLASS_HID_4030b = 0x4030b,
+ BNXT_ULP_CLASS_HID_41317 = 0x41317,
+ BNXT_ULP_CLASS_HID_5131b = 0x5131b,
+ BNXT_ULP_CLASS_HID_50201 = 0x50201,
+ BNXT_ULP_CLASS_HID_48b13 = 0x48b13,
+ BNXT_ULP_CLASS_HID_49b1f = 0x49b1f,
+ BNXT_ULP_CLASS_HID_59b23 = 0x59b23,
+ BNXT_ULP_CLASS_HID_58a09 = 0x58a09,
+ BNXT_ULP_CLASS_HID_419bf = 0x419bf,
+ BNXT_ULP_CLASS_HID_40925 = 0x40925,
+ BNXT_ULP_CLASS_HID_508e9 = 0x508e9,
+ BNXT_ULP_CLASS_HID_518b5 = 0x518b5,
+ BNXT_ULP_CLASS_HID_48121 = 0x48121,
+ BNXT_ULP_CLASS_HID_490ed = 0x490ed,
+ BNXT_ULP_CLASS_HID_590b1 = 0x590b1,
+ BNXT_ULP_CLASS_HID_583ff = 0x583ff,
+ BNXT_ULP_CLASS_HID_41475 = 0x41475,
+ BNXT_ULP_CLASS_HID_40473 = 0x40473,
+ BNXT_ULP_CLASS_HID_50427 = 0x50427,
+ BNXT_ULP_CLASS_HID_51763 = 0x51763,
+ BNXT_ULP_CLASS_HID_49c3d = 0x49c3d,
+ BNXT_ULP_CLASS_HID_48c3b = 0x48c3b,
+ BNXT_ULP_CLASS_HID_58f6f = 0x58f6f,
+ BNXT_ULP_CLASS_HID_59f2b = 0x59f2b,
+ BNXT_ULP_CLASS_HID_40333 = 0x40333,
+ BNXT_ULP_CLASS_HID_412bf = 0x412bf,
+ BNXT_ULP_CLASS_HID_512a3 = 0x512a3,
+ BNXT_ULP_CLASS_HID_50229 = 0x50229,
+ BNXT_ULP_CLASS_HID_48abb = 0x48abb,
+ BNXT_ULP_CLASS_HID_49aa7 = 0x49aa7,
+ BNXT_ULP_CLASS_HID_59a2b = 0x59a2b,
+ BNXT_ULP_CLASS_HID_595b1 = 0x595b1,
+ BNXT_ULP_CLASS_HID_41e2f = 0x41e2f,
+ BNXT_ULP_CLASS_HID_40e35 = 0x40e35,
+ BNXT_ULP_CLASS_HID_50939 = 0x50939,
+ BNXT_ULP_CLASS_HID_51925 = 0x51925,
+ BNXT_ULP_CLASS_HID_48631 = 0x48631,
+ BNXT_ULP_CLASS_HID_4913d = 0x4913d,
+ BNXT_ULP_CLASS_HID_59121 = 0x59121,
+ BNXT_ULP_CLASS_HID_5812f = 0x5812f,
+ BNXT_ULP_CLASS_HID_41429 = 0x41429,
+ BNXT_ULP_CLASS_HID_40747 = 0x40747,
+ BNXT_ULP_CLASS_HID_5070b = 0x5070b,
+ BNXT_ULP_CLASS_HID_51727 = 0x51727,
+ BNXT_ULP_CLASS_HID_49fe1 = 0x49fe1,
+ BNXT_ULP_CLASS_HID_48f0f = 0x48f0f,
+ BNXT_ULP_CLASS_HID_58f23 = 0x58f23,
+ BNXT_ULP_CLASS_HID_59eef = 0x59eef,
+ BNXT_ULP_CLASS_HID_40347 = 0x40347,
+ BNXT_ULP_CLASS_HID_41303 = 0x41303,
+ BNXT_ULP_CLASS_HID_51247 = 0x51247,
+ BNXT_ULP_CLASS_HID_5026d = 0x5026d,
+ BNXT_ULP_CLASS_HID_48b0f = 0x48b0f,
+ BNXT_ULP_CLASS_HID_49a4b = 0x49a4b,
+ BNXT_ULP_CLASS_HID_59a0f = 0x59a0f,
+ BNXT_ULP_CLASS_HID_58a05 = 0x58a05,
+ BNXT_ULP_CLASS_HID_41983 = 0x41983,
+ BNXT_ULP_CLASS_HID_40929 = 0x40929,
+ BNXT_ULP_CLASS_HID_5092d = 0x5092d,
+ BNXT_ULP_CLASS_HID_518a9 = 0x518a9,
+ BNXT_ULP_CLASS_HID_48125 = 0x48125,
+ BNXT_ULP_CLASS_HID_49121 = 0x49121,
+ BNXT_ULP_CLASS_HID_59085 = 0x59085,
+ BNXT_ULP_CLASS_HID_58023 = 0x58023,
+ BNXT_ULP_CLASS_HID_41509 = 0x41509,
+ BNXT_ULP_CLASS_HID_40407 = 0x40407,
+ BNXT_ULP_CLASS_HID_5040b = 0x5040b,
+ BNXT_ULP_CLASS_HID_51407 = 0x51407,
+ BNXT_ULP_CLASS_HID_49d21 = 0x49d21,
+ BNXT_ULP_CLASS_HID_48c0f = 0x48c0f,
+ BNXT_ULP_CLASS_HID_58c03 = 0x58c03,
+ BNXT_ULP_CLASS_HID_59f0f = 0x59f0f,
+ BNXT_ULP_CLASS_HID_402ef = 0x402ef,
+ BNXT_ULP_CLASS_HID_412ab = 0x412ab,
+ BNXT_ULP_CLASS_HID_5126f = 0x5126f,
+ BNXT_ULP_CLASS_HID_50de5 = 0x50de5,
+ BNXT_ULP_CLASS_HID_48aa7 = 0x48aa7,
+ BNXT_ULP_CLASS_HID_485ed = 0x485ed,
+ BNXT_ULP_CLASS_HID_585e1 = 0x585e1,
+ BNXT_ULP_CLASS_HID_595ad = 0x595ad,
+ BNXT_ULP_CLASS_HID_41e6b = 0x41e6b,
+ BNXT_ULP_CLASS_HID_40961 = 0x40961,
+ BNXT_ULP_CLASS_HID_50925 = 0x50925,
+ BNXT_ULP_CLASS_HID_51961 = 0x51961,
+ BNXT_ULP_CLASS_HID_4816d = 0x4816d,
+ BNXT_ULP_CLASS_HID_49129 = 0x49129,
+ BNXT_ULP_CLASS_HID_5916d = 0x5916d,
+ BNXT_ULP_CLASS_HID_5806b = 0x5806b,
+ BNXT_ULP_CLASS_HID_414a1 = 0x414a1,
+ BNXT_ULP_CLASS_HID_4042f = 0x4042f,
+ BNXT_ULP_CLASS_HID_507a3 = 0x507a3,
+ BNXT_ULP_CLASS_HID_517af = 0x517af,
+ BNXT_ULP_CLASS_HID_49c29 = 0x49c29,
+ BNXT_ULP_CLASS_HID_48fa7 = 0x48fa7,
+ BNXT_ULP_CLASS_HID_58fab = 0x58fab,
+ BNXT_ULP_CLASS_HID_59f27 = 0x59f27,
+ BNXT_ULP_CLASS_HID_4032f = 0x4032f,
+ BNXT_ULP_CLASS_HID_4132b = 0x4132b,
+ BNXT_ULP_CLASS_HID_5132f = 0x5132f,
+ BNXT_ULP_CLASS_HID_50225 = 0x50225,
+ BNXT_ULP_CLASS_HID_48b27 = 0x48b27,
+ BNXT_ULP_CLASS_HID_49b23 = 0x49b23,
+ BNXT_ULP_CLASS_HID_59b27 = 0x59b27,
+ BNXT_ULP_CLASS_HID_58a2d = 0x58a2d,
+ BNXT_ULP_CLASS_HID_10437 = 0x10437,
+ BNXT_ULP_CLASS_HID_11017 = 0x11017,
+ BNXT_ULP_CLASS_HID_1402b = 0x1402b,
+ BNXT_ULP_CLASS_HID_15c0b = 0x15c0b,
+ BNXT_ULP_CLASS_HID_12639 = 0x12639,
+ BNXT_ULP_CLASS_HID_13219 = 0x13219,
+ BNXT_ULP_CLASS_HID_16ddd = 0x16ddd,
+ BNXT_ULP_CLASS_HID_17e3d = 0x17e3d,
+ BNXT_ULP_CLASS_HID_11333 = 0x11333,
+ BNXT_ULP_CLASS_HID_10ef5 = 0x10ef5,
+ BNXT_ULP_CLASS_HID_15f37 = 0x15f37,
+ BNXT_ULP_CLASS_HID_14ae9 = 0x14ae9,
+ BNXT_ULP_CLASS_HID_13d25 = 0x13d25,
+ BNXT_ULP_CLASS_HID_128e7 = 0x128e7,
+ BNXT_ULP_CLASS_HID_17939 = 0x17939,
+ BNXT_ULP_CLASS_HID_174fb = 0x174fb,
+ BNXT_ULP_CLASS_HID_10985 = 0x10985,
+ BNXT_ULP_CLASS_HID_10547 = 0x10547,
+ BNXT_ULP_CLASS_HID_155a9 = 0x155a9,
+ BNXT_ULP_CLASS_HID_1416b = 0x1416b,
+ BNXT_ULP_CLASS_HID_12ba7 = 0x12ba7,
+ BNXT_ULP_CLASS_HID_12749 = 0x12749,
+ BNXT_ULP_CLASS_HID_177ab = 0x177ab,
+ BNXT_ULP_CLASS_HID_1636d = 0x1636d,
+ BNXT_ULP_CLASS_HID_10463 = 0x10463,
+ BNXT_ULP_CLASS_HID_110a3 = 0x110a3,
+ BNXT_ULP_CLASS_HID_14067 = 0x14067,
+ BNXT_ULP_CLASS_HID_15c67 = 0x15c67,
+ BNXT_ULP_CLASS_HID_12665 = 0x12665,
+ BNXT_ULP_CLASS_HID_13265 = 0x13265,
+ BNXT_ULP_CLASS_HID_16269 = 0x16269,
+ BNXT_ULP_CLASS_HID_17e69 = 0x17e69,
+ BNXT_ULP_CLASS_HID_1133d = 0x1133d,
+ BNXT_ULP_CLASS_HID_10eff = 0x10eff,
+ BNXT_ULP_CLASS_HID_15ed9 = 0x15ed9,
+ BNXT_ULP_CLASS_HID_14a9b = 0x14a9b,
+ BNXT_ULP_CLASS_HID_13d2f = 0x13d2f,
+ BNXT_ULP_CLASS_HID_128e9 = 0x128e9,
+ BNXT_ULP_CLASS_HID_178cb = 0x178cb,
+ BNXT_ULP_CLASS_HID_1748d = 0x1748d,
+ BNXT_ULP_CLASS_HID_109fb = 0x109fb,
+ BNXT_ULP_CLASS_HID_105bd = 0x105bd,
+ BNXT_ULP_CLASS_HID_155bf = 0x155bf,
+ BNXT_ULP_CLASS_HID_14179 = 0x14179,
+ BNXT_ULP_CLASS_HID_12bed = 0x12bed,
+ BNXT_ULP_CLASS_HID_127af = 0x127af,
+ BNXT_ULP_CLASS_HID_177a9 = 0x177a9,
+ BNXT_ULP_CLASS_HID_1636b = 0x1636b,
+ BNXT_ULP_CLASS_HID_1046d = 0x1046d,
+ BNXT_ULP_CLASS_HID_1104d = 0x1104d,
+ BNXT_ULP_CLASS_HID_14009 = 0x14009,
+ BNXT_ULP_CLASS_HID_15c69 = 0x15c69,
+ BNXT_ULP_CLASS_HID_1260f = 0x1260f,
+ BNXT_ULP_CLASS_HID_1326f = 0x1326f,
+ BNXT_ULP_CLASS_HID_1622b = 0x1622b,
+ BNXT_ULP_CLASS_HID_17e0b = 0x17e0b,
+ BNXT_ULP_CLASS_HID_11369 = 0x11369,
+ BNXT_ULP_CLASS_HID_10f2b = 0x10f2b,
+ BNXT_ULP_CLASS_HID_15f6d = 0x15f6d,
+ BNXT_ULP_CLASS_HID_14b2f = 0x14b2f,
+ BNXT_ULP_CLASS_HID_13d6b = 0x13d6b,
+ BNXT_ULP_CLASS_HID_1292d = 0x1292d,
+ BNXT_ULP_CLASS_HID_1792f = 0x1792f,
+ BNXT_ULP_CLASS_HID_174e9 = 0x174e9,
+ BNXT_ULP_CLASS_HID_119e1 = 0x119e1,
+ BNXT_ULP_CLASS_HID_115a3 = 0x115a3,
+ BNXT_ULP_CLASS_HID_14563 = 0x14563,
+ BNXT_ULP_CLASS_HID_15143 = 0x15143,
+ BNXT_ULP_CLASS_HID_13b93 = 0x13b93,
+ BNXT_ULP_CLASS_HID_13751 = 0x13751,
+ BNXT_ULP_CLASS_HID_16769 = 0x16769,
+ BNXT_ULP_CLASS_HID_17349 = 0x17349,
+ BNXT_ULP_CLASS_HID_114ab = 0x114ab,
+ BNXT_ULP_CLASS_HID_10061 = 0x10061,
+ BNXT_ULP_CLASS_HID_15063 = 0x15063,
+ BNXT_ULP_CLASS_HID_14c21 = 0x14c21,
+ BNXT_ULP_CLASS_HID_13671 = 0x13671,
+ BNXT_ULP_CLASS_HID_12233 = 0x12233,
+ BNXT_ULP_CLASS_HID_17271 = 0x17271,
+ BNXT_ULP_CLASS_HID_16e33 = 0x16e33,
+ BNXT_ULP_CLASS_HID_102c1 = 0x102c1,
+ BNXT_ULP_CLASS_HID_11f21 = 0x11f21,
+ BNXT_ULP_CLASS_HID_14ee1 = 0x14ee1,
+ BNXT_ULP_CLASS_HID_15ac1 = 0x15ac1,
+ BNXT_ULP_CLASS_HID_12cc3 = 0x12cc3,
+ BNXT_ULP_CLASS_HID_13923 = 0x13923,
+ BNXT_ULP_CLASS_HID_168e3 = 0x168e3,
+ BNXT_ULP_CLASS_HID_164a9 = 0x164a9,
+ BNXT_ULP_CLASS_HID_11e29 = 0x11e29,
+ BNXT_ULP_CLASS_HID_115eb = 0x115eb,
+ BNXT_ULP_CLASS_HID_145a3 = 0x145a3,
+ BNXT_ULP_CLASS_HID_151a3 = 0x151a3,
+ BNXT_ULP_CLASS_HID_1382b = 0x1382b,
+ BNXT_ULP_CLASS_HID_137e1 = 0x137e1,
+ BNXT_ULP_CLASS_HID_167a1 = 0x167a1,
+ BNXT_ULP_CLASS_HID_173a1 = 0x173a1,
+ BNXT_ULP_CLASS_HID_11449 = 0x11449,
+ BNXT_ULP_CLASS_HID_1000b = 0x1000b,
+ BNXT_ULP_CLASS_HID_15069 = 0x15069,
+ BNXT_ULP_CLASS_HID_14c2b = 0x14c2b,
+ BNXT_ULP_CLASS_HID_1367b = 0x1367b,
+ BNXT_ULP_CLASS_HID_12239 = 0x12239,
+ BNXT_ULP_CLASS_HID_1721b = 0x1721b,
+ BNXT_ULP_CLASS_HID_169d9 = 0x169d9,
+ BNXT_ULP_CLASS_HID_1033b = 0x1033b,
+ BNXT_ULP_CLASS_HID_11f3b = 0x11f3b,
+ BNXT_ULP_CLASS_HID_14f2b = 0x14f2b,
+ BNXT_ULP_CLASS_HID_15b2b = 0x15b2b,
+ BNXT_ULP_CLASS_HID_12d39 = 0x12d39,
+ BNXT_ULP_CLASS_HID_13939 = 0x13939,
+ BNXT_ULP_CLASS_HID_168f9 = 0x168f9,
+ BNXT_ULP_CLASS_HID_164bb = 0x164bb,
+ BNXT_ULP_CLASS_HID_119cb = 0x119cb,
+ BNXT_ULP_CLASS_HID_11589 = 0x11589,
+ BNXT_ULP_CLASS_HID_14549 = 0x14549,
+ BNXT_ULP_CLASS_HID_151a9 = 0x151a9,
+ BNXT_ULP_CLASS_HID_13bc9 = 0x13bc9,
+ BNXT_ULP_CLASS_HID_1378b = 0x1378b,
+ BNXT_ULP_CLASS_HID_1674b = 0x1674b,
+ BNXT_ULP_CLASS_HID_173ab = 0x173ab,
+ BNXT_ULP_CLASS_HID_114a9 = 0x114a9,
+ BNXT_ULP_CLASS_HID_1006b = 0x1006b,
+ BNXT_ULP_CLASS_HID_150a9 = 0x150a9,
+ BNXT_ULP_CLASS_HID_14c6b = 0x14c6b,
+ BNXT_ULP_CLASS_HID_136ab = 0x136ab,
+ BNXT_ULP_CLASS_HID_12269 = 0x12269,
+ BNXT_ULP_CLASS_HID_172ab = 0x172ab,
+ BNXT_ULP_CLASS_HID_16e69 = 0x16e69,
+ BNXT_ULP_CLASS_HID_402d2 = 0x402d2,
+ BNXT_ULP_CLASS_HID_412ee = 0x412ee,
+ BNXT_ULP_CLASS_HID_512a2 = 0x512a2,
+ BNXT_ULP_CLASS_HID_50dd8 = 0x50dd8,
+ BNXT_ULP_CLASS_HID_48aea = 0x48aea,
+ BNXT_ULP_CLASS_HID_48500 = 0x48500,
+ BNXT_ULP_CLASS_HID_585d4 = 0x585d4,
+ BNXT_ULP_CLASS_HID_59590 = 0x59590,
+ BNXT_ULP_CLASS_HID_41936 = 0x41936,
+ BNXT_ULP_CLASS_HID_409ac = 0x409ac,
+ BNXT_ULP_CLASS_HID_50860 = 0x50860,
+ BNXT_ULP_CLASS_HID_5183c = 0x5183c,
+ BNXT_ULP_CLASS_HID_481a8 = 0x481a8,
+ BNXT_ULP_CLASS_HID_49064 = 0x49064,
+ BNXT_ULP_CLASS_HID_59038 = 0x59038,
+ BNXT_ULP_CLASS_HID_58376 = 0x58376,
+ BNXT_ULP_CLASS_HID_414a0 = 0x414a0,
+ BNXT_ULP_CLASS_HID_407ce = 0x407ce,
+ BNXT_ULP_CLASS_HID_50782 = 0x50782,
+ BNXT_ULP_CLASS_HID_517ae = 0x517ae,
+ BNXT_ULP_CLASS_HID_49f68 = 0x49f68,
+ BNXT_ULP_CLASS_HID_48f86 = 0x48f86,
+ BNXT_ULP_CLASS_HID_58faa = 0x58faa,
+ BNXT_ULP_CLASS_HID_59e66 = 0x59e66,
+ BNXT_ULP_CLASS_HID_40266 = 0x40266,
+ BNXT_ULP_CLASS_HID_41222 = 0x41222,
+ BNXT_ULP_CLASS_HID_512e6 = 0x512e6,
+ BNXT_ULP_CLASS_HID_50d6c = 0x50d6c,
+ BNXT_ULP_CLASS_HID_48a2e = 0x48a2e,
+ BNXT_ULP_CLASS_HID_48564 = 0x48564,
+ BNXT_ULP_CLASS_HID_58568 = 0x58568,
+ BNXT_ULP_CLASS_HID_59524 = 0x59524,
+ BNXT_ULP_CLASS_HID_419d8 = 0x419d8,
+ BNXT_ULP_CLASS_HID_4087e = 0x4087e,
+ BNXT_ULP_CLASS_HID_5080a = 0x5080a,
+ BNXT_ULP_CLASS_HID_518ce = 0x518ce,
+ BNXT_ULP_CLASS_HID_4807a = 0x4807a,
+ BNXT_ULP_CLASS_HID_4900e = 0x4900e,
+ BNXT_ULP_CLASS_HID_590ca = 0x590ca,
+ BNXT_ULP_CLASS_HID_58378 = 0x58378,
+ BNXT_ULP_CLASS_HID_414be = 0x414be,
+ BNXT_ULP_CLASS_HID_4073c = 0x4073c,
+ BNXT_ULP_CLASS_HID_507e8 = 0x507e8,
+ BNXT_ULP_CLASS_HID_517ac = 0x517ac,
+ BNXT_ULP_CLASS_HID_49f7e = 0x49f7e,
+ BNXT_ULP_CLASS_HID_48fec = 0x48fec,
+ BNXT_ULP_CLASS_HID_58fa8 = 0x58fa8,
+ BNXT_ULP_CLASS_HID_59e7c = 0x59e7c,
+ BNXT_ULP_CLASS_HID_40208 = 0x40208,
+ BNXT_ULP_CLASS_HID_412cc = 0x412cc,
+ BNXT_ULP_CLASS_HID_51288 = 0x51288,
+ BNXT_ULP_CLASS_HID_50d2e = 0x50d2e,
+ BNXT_ULP_CLASS_HID_48ac8 = 0x48ac8,
+ BNXT_ULP_CLASS_HID_4856e = 0x4856e,
+ BNXT_ULP_CLASS_HID_5852a = 0x5852a,
+ BNXT_ULP_CLASS_HID_595ce = 0x595ce,
+ BNXT_ULP_CLASS_HID_4196c = 0x4196c,
+ BNXT_ULP_CLASS_HID_409aa = 0x409aa,
+ BNXT_ULP_CLASS_HID_5086e = 0x5086e,
+ BNXT_ULP_CLASS_HID_5182a = 0x5182a,
+ BNXT_ULP_CLASS_HID_481ae = 0x481ae,
+ BNXT_ULP_CLASS_HID_4906a = 0x4906a,
+ BNXT_ULP_CLASS_HID_5902e = 0x5902e,
+ BNXT_ULP_CLASS_HID_580ac = 0x580ac,
+ BNXT_ULP_CLASS_HID_40766 = 0x40766,
+ BNXT_ULP_CLASS_HID_41726 = 0x41726,
+ BNXT_ULP_CLASS_HID_517f6 = 0x517f6,
+ BNXT_ULP_CLASS_HID_5066c = 0x5066c,
+ BNXT_ULP_CLASS_HID_48f3e = 0x48f3e,
+ BNXT_ULP_CLASS_HID_49ffe = 0x49ffe,
+ BNXT_ULP_CLASS_HID_59f8e = 0x59f8e,
+ BNXT_ULP_CLASS_HID_58e24 = 0x58e24,
+ BNXT_ULP_CLASS_HID_4126e = 0x4126e,
+ BNXT_ULP_CLASS_HID_402e4 = 0x402e4,
+ BNXT_ULP_CLASS_HID_502b4 = 0x502b4,
+ BNXT_ULP_CLASS_HID_51d74 = 0x51d74,
+ BNXT_ULP_CLASS_HID_49a26 = 0x49a26,
+ BNXT_ULP_CLASS_HID_48abc = 0x48abc,
+ BNXT_ULP_CLASS_HID_5956c = 0x5956c,
+ BNXT_ULP_CLASS_HID_585ee = 0x585ee,
+ BNXT_ULP_CLASS_HID_409e4 = 0x409e4,
+ BNXT_ULP_CLASS_HID_419a4 = 0x419a4,
+ BNXT_ULP_CLASS_HID_51844 = 0x51844,
+ BNXT_ULP_CLASS_HID_508e6 = 0x508e6,
+ BNXT_ULP_CLASS_HID_4918c = 0x4918c,
+ BNXT_ULP_CLASS_HID_4802e = 0x4802e,
+ BNXT_ULP_CLASS_HID_580ee = 0x580ee,
+ BNXT_ULP_CLASS_HID_590ae = 0x590ae,
+ BNXT_ULP_CLASS_HID_404ae = 0x404ae,
+ BNXT_ULP_CLASS_HID_41766 = 0x41766,
+ BNXT_ULP_CLASS_HID_5172e = 0x5172e,
+ BNXT_ULP_CLASS_HID_507a4 = 0x507a4,
+ BNXT_ULP_CLASS_HID_48f66 = 0x48f66,
+ BNXT_ULP_CLASS_HID_49f2e = 0x49f2e,
+ BNXT_ULP_CLASS_HID_59fe6 = 0x59fe6,
+ BNXT_ULP_CLASS_HID_58e6c = 0x58e6c,
+ BNXT_ULP_CLASS_HID_4126c = 0x4126c,
+ BNXT_ULP_CLASS_HID_4028e = 0x4028e,
+ BNXT_ULP_CLASS_HID_50d5e = 0x50d5e,
+ BNXT_ULP_CLASS_HID_51d1e = 0x51d1e,
+ BNXT_ULP_CLASS_HID_49a2c = 0x49a2c,
+ BNXT_ULP_CLASS_HID_4954e = 0x4954e,
+ BNXT_ULP_CLASS_HID_5951e = 0x5951e,
+ BNXT_ULP_CLASS_HID_5858c = 0x5858c,
+ BNXT_ULP_CLASS_HID_409fe = 0x409fe,
+ BNXT_ULP_CLASS_HID_419ee = 0x419ee,
+ BNXT_ULP_CLASS_HID_519ae = 0x519ae,
+ BNXT_ULP_CLASS_HID_508fc = 0x508fc,
+ BNXT_ULP_CLASS_HID_491ee = 0x491ee,
+ BNXT_ULP_CLASS_HID_4802c = 0x4802c,
+ BNXT_ULP_CLASS_HID_580fc = 0x580fc,
+ BNXT_ULP_CLASS_HID_590bc = 0x590bc,
+ BNXT_ULP_CLASS_HID_4074c = 0x4074c,
+ BNXT_ULP_CLASS_HID_4170c = 0x4170c,
+ BNXT_ULP_CLASS_HID_5172c = 0x5172c,
+ BNXT_ULP_CLASS_HID_5064e = 0x5064e,
+ BNXT_ULP_CLASS_HID_48f0c = 0x48f0c,
+ BNXT_ULP_CLASS_HID_49fcc = 0x49fcc,
+ BNXT_ULP_CLASS_HID_59fec = 0x59fec,
+ BNXT_ULP_CLASS_HID_58e0e = 0x58e0e,
+ BNXT_ULP_CLASS_HID_413ac = 0x413ac,
+ BNXT_ULP_CLASS_HID_402ee = 0x402ee,
+ BNXT_ULP_CLASS_HID_502ae = 0x502ae,
+ BNXT_ULP_CLASS_HID_512ae = 0x512ae,
+ BNXT_ULP_CLASS_HID_49a6c = 0x49a6c,
+ BNXT_ULP_CLASS_HID_48aae = 0x48aae,
+ BNXT_ULP_CLASS_HID_58aae = 0x58aae,
+ BNXT_ULP_CLASS_HID_585ec = 0x585ec,
+ BNXT_ULP_CLASS_HID_104ae = 0x104ae,
+ BNXT_ULP_CLASS_HID_1108e = 0x1108e,
+ BNXT_ULP_CLASS_HID_140b2 = 0x140b2,
+ BNXT_ULP_CLASS_HID_15c92 = 0x15c92,
+ BNXT_ULP_CLASS_HID_126a0 = 0x126a0,
+ BNXT_ULP_CLASS_HID_13280 = 0x13280,
+ BNXT_ULP_CLASS_HID_16d44 = 0x16d44,
+ BNXT_ULP_CLASS_HID_17ea4 = 0x17ea4,
+ BNXT_ULP_CLASS_HID_113a4 = 0x113a4,
+ BNXT_ULP_CLASS_HID_10e66 = 0x10e66,
+ BNXT_ULP_CLASS_HID_15e40 = 0x15e40,
+ BNXT_ULP_CLASS_HID_14a02 = 0x14a02,
+ BNXT_ULP_CLASS_HID_13db6 = 0x13db6,
+ BNXT_ULP_CLASS_HID_12870 = 0x12870,
+ BNXT_ULP_CLASS_HID_17852 = 0x17852,
+ BNXT_ULP_CLASS_HID_17414 = 0x17414,
+ BNXT_ULP_CLASS_HID_11978 = 0x11978,
+ BNXT_ULP_CLASS_HID_1153a = 0x1153a,
+ BNXT_ULP_CLASS_HID_145fa = 0x145fa,
+ BNXT_ULP_CLASS_HID_151da = 0x151da,
+ BNXT_ULP_CLASS_HID_13b0a = 0x13b0a,
+ BNXT_ULP_CLASS_HID_137c8 = 0x137c8,
+ BNXT_ULP_CLASS_HID_167f0 = 0x167f0,
+ BNXT_ULP_CLASS_HID_173d0 = 0x173d0,
+ BNXT_ULP_CLASS_HID_114d0 = 0x114d0,
+ BNXT_ULP_CLASS_HID_10092 = 0x10092,
+ BNXT_ULP_CLASS_HID_150f0 = 0x150f0,
+ BNXT_ULP_CLASS_HID_14cb2 = 0x14cb2,
+ BNXT_ULP_CLASS_HID_136e2 = 0x136e2,
+ BNXT_ULP_CLASS_HID_122a0 = 0x122a0,
+ BNXT_ULP_CLASS_HID_17282 = 0x17282,
+ BNXT_ULP_CLASS_HID_16940 = 0x16940,
+ BNXT_ULP_CLASS_HID_11b90 = 0x11b90,
+ BNXT_ULP_CLASS_HID_11654 = 0x11654,
+ BNXT_ULP_CLASS_HID_14618 = 0x14618,
+ BNXT_ULP_CLASS_HID_15278 = 0x15278,
+ BNXT_ULP_CLASS_HID_12404 = 0x12404,
+ BNXT_ULP_CLASS_HID_13064 = 0x13064,
+ BNXT_ULP_CLASS_HID_16028 = 0x16028,
+ BNXT_ULP_CLASS_HID_17c08 = 0x17c08,
+ BNXT_ULP_CLASS_HID_11100 = 0x11100,
+ BNXT_ULP_CLASS_HID_10dc4 = 0x10dc4,
+ BNXT_ULP_CLASS_HID_15d24 = 0x15d24,
+ BNXT_ULP_CLASS_HID_149d0 = 0x149d0,
+ BNXT_ULP_CLASS_HID_13314 = 0x13314,
+ BNXT_ULP_CLASS_HID_12fd4 = 0x12fd4,
+ BNXT_ULP_CLASS_HID_17f20 = 0x17f20,
+ BNXT_ULP_CLASS_HID_16be0 = 0x16be0,
+ BNXT_ULP_CLASS_HID_11cd8 = 0x11cd8,
+ BNXT_ULP_CLASS_HID_10880 = 0x10880,
+ BNXT_ULP_CLASS_HID_158e0 = 0x158e0,
+ BNXT_ULP_CLASS_HID_154a0 = 0x154a0,
+ BNXT_ULP_CLASS_HID_13ed0 = 0x13ed0,
+ BNXT_ULP_CLASS_HID_12a90 = 0x12a90,
+ BNXT_ULP_CLASS_HID_16550 = 0x16550,
+ BNXT_ULP_CLASS_HID_176b0 = 0x176b0,
+ BNXT_ULP_CLASS_HID_10bb0 = 0x10bb0,
+ BNXT_ULP_CLASS_HID_10670 = 0x10670,
+ BNXT_ULP_CLASS_HID_15650 = 0x15650,
+ BNXT_ULP_CLASS_HID_14210 = 0x14210,
+ BNXT_ULP_CLASS_HID_13440 = 0x13440,
+ BNXT_ULP_CLASS_HID_12000 = 0x12000,
+ BNXT_ULP_CLASS_HID_17060 = 0x17060,
+ BNXT_ULP_CLASS_HID_16c20 = 0x16c20,
+ BNXT_ULP_CLASS_HID_11511 = 0x11511,
+ BNXT_ULP_CLASS_HID_101d3 = 0x101d3,
+ BNXT_ULP_CLASS_HID_15135 = 0x15135,
+ BNXT_ULP_CLASS_HID_14df7 = 0x14df7,
+ BNXT_ULP_CLASS_HID_13723 = 0x13723,
+ BNXT_ULP_CLASS_HID_123e5 = 0x123e5,
+ BNXT_ULP_CLASS_HID_173c7 = 0x173c7,
+ BNXT_ULP_CLASS_HID_16f89 = 0x16f89,
+ BNXT_ULP_CLASS_HID_10081 = 0x10081,
+ BNXT_ULP_CLASS_HID_11ce1 = 0x11ce1,
+ BNXT_ULP_CLASS_HID_14ca5 = 0x14ca5,
+ BNXT_ULP_CLASS_HID_15885 = 0x15885,
+ BNXT_ULP_CLASS_HID_12293 = 0x12293,
+ BNXT_ULP_CLASS_HID_13ef3 = 0x13ef3,
+ BNXT_ULP_CLASS_HID_16eb7 = 0x16eb7,
+ BNXT_ULP_CLASS_HID_16561 = 0x16561,
+ BNXT_ULP_CLASS_HID_10e59 = 0x10e59,
+ BNXT_ULP_CLASS_HID_11bb9 = 0x11bb9,
+ BNXT_ULP_CLASS_HID_14a61 = 0x14a61,
+ BNXT_ULP_CLASS_HID_14623 = 0x14623,
+ BNXT_ULP_CLASS_HID_1286b = 0x1286b,
+ BNXT_ULP_CLASS_HID_12411 = 0x12411,
+ BNXT_ULP_CLASS_HID_17473 = 0x17473,
+ BNXT_ULP_CLASS_HID_16031 = 0x16031,
+ BNXT_ULP_CLASS_HID_10531 = 0x10531,
+ BNXT_ULP_CLASS_HID_11111 = 0x11111,
+ BNXT_ULP_CLASS_HID_141d1 = 0x141d1,
+ BNXT_ULP_CLASS_HID_15d31 = 0x15d31,
+ BNXT_ULP_CLASS_HID_127c3 = 0x127c3,
+ BNXT_ULP_CLASS_HID_13323 = 0x13323,
+ BNXT_ULP_CLASS_HID_163e3 = 0x163e3,
+ BNXT_ULP_CLASS_HID_17fc3 = 0x17fc3,
+ BNXT_ULP_CLASS_HID_108f5 = 0x108f5,
+ BNXT_ULP_CLASS_HID_104b9 = 0x104b9,
+ BNXT_ULP_CLASS_HID_15499 = 0x15499,
+ BNXT_ULP_CLASS_HID_1435d = 0x1435d,
+ BNXT_ULP_CLASS_HID_12a89 = 0x12a89,
+ BNXT_ULP_CLASS_HID_12149 = 0x12149,
+ BNXT_ULP_CLASS_HID_176ad = 0x176ad,
+ BNXT_ULP_CLASS_HID_16d6d = 0x16d6d,
+ BNXT_ULP_CLASS_HID_10665 = 0x10665,
+ BNXT_ULP_CLASS_HID_11245 = 0x11245,
+ BNXT_ULP_CLASS_HID_14271 = 0x14271,
+ BNXT_ULP_CLASS_HID_15e51 = 0x15e51,
+ BNXT_ULP_CLASS_HID_12061 = 0x12061,
+ BNXT_ULP_CLASS_HID_13c41 = 0x13c41,
+ BNXT_ULP_CLASS_HID_16c05 = 0x16c05,
+ BNXT_ULP_CLASS_HID_17865 = 0x17865,
+ BNXT_ULP_CLASS_HID_10d21 = 0x10d21,
+ BNXT_ULP_CLASS_HID_11901 = 0x11901,
+ BNXT_ULP_CLASS_HID_149c1 = 0x149c1,
+ BNXT_ULP_CLASS_HID_14589 = 0x14589,
+ BNXT_ULP_CLASS_HID_12f31 = 0x12f31,
+ BNXT_ULP_CLASS_HID_13b11 = 0x13b11,
+ BNXT_ULP_CLASS_HID_16bd9 = 0x16bd9,
+ BNXT_ULP_CLASS_HID_16799 = 0x16799,
+ BNXT_ULP_CLASS_HID_11831 = 0x11831,
+ BNXT_ULP_CLASS_HID_114f1 = 0x114f1,
+ BNXT_ULP_CLASS_HID_144b1 = 0x144b1,
+ BNXT_ULP_CLASS_HID_15091 = 0x15091,
+ BNXT_ULP_CLASS_HID_13ac1 = 0x13ac1,
+ BNXT_ULP_CLASS_HID_13681 = 0x13681,
+ BNXT_ULP_CLASS_HID_166b1 = 0x166b1,
+ BNXT_ULP_CLASS_HID_17291 = 0x17291,
+ BNXT_ULP_CLASS_HID_4007d = 0x4007d,
+ BNXT_ULP_CLASS_HID_41041 = 0x41041,
+ BNXT_ULP_CLASS_HID_5100d = 0x5100d,
+ BNXT_ULP_CLASS_HID_50f77 = 0x50f77,
+ BNXT_ULP_CLASS_HID_48845 = 0x48845,
+ BNXT_ULP_CLASS_HID_487af = 0x487af,
+ BNXT_ULP_CLASS_HID_5877b = 0x5877b,
+ BNXT_ULP_CLASS_HID_5973f = 0x5973f,
+ BNXT_ULP_CLASS_HID_41c31 = 0x41c31,
+ BNXT_ULP_CLASS_HID_40b1b = 0x40b1b,
+ BNXT_ULP_CLASS_HID_50b67 = 0x50b67,
+ BNXT_ULP_CLASS_HID_51b2b = 0x51b2b,
+ BNXT_ULP_CLASS_HID_4831f = 0x4831f,
+ BNXT_ULP_CLASS_HID_49363 = 0x49363,
+ BNXT_ULP_CLASS_HID_5932f = 0x5932f,
+ BNXT_ULP_CLASS_HID_58211 = 0x58211,
+ BNXT_ULP_CLASS_HID_4161b = 0x4161b,
+ BNXT_ULP_CLASS_HID_405bd = 0x405bd,
+ BNXT_ULP_CLASS_HID_50589 = 0x50589,
+ BNXT_ULP_CLASS_HID_5150d = 0x5150d,
+ BNXT_ULP_CLASS_HID_49e23 = 0x49e23,
+ BNXT_ULP_CLASS_HID_48d85 = 0x48d85,
+ BNXT_ULP_CLASS_HID_58d11 = 0x58d11,
+ BNXT_ULP_CLASS_HID_59d15 = 0x59d15,
+ BNXT_ULP_CLASS_HID_4012d = 0x4012d,
+ BNXT_ULP_CLASS_HID_41131 = 0x41131,
+ BNXT_ULP_CLASS_HID_5113d = 0x5113d,
+ BNXT_ULP_CLASS_HID_50027 = 0x50027,
+ BNXT_ULP_CLASS_HID_48935 = 0x48935,
+ BNXT_ULP_CLASS_HID_49939 = 0x49939,
+ BNXT_ULP_CLASS_HID_59905 = 0x59905,
+ BNXT_ULP_CLASS_HID_5882f = 0x5882f,
+ BNXT_ULP_CLASS_HID_41b99 = 0x41b99,
+ BNXT_ULP_CLASS_HID_40b03 = 0x40b03,
+ BNXT_ULP_CLASS_HID_50acf = 0x50acf,
+ BNXT_ULP_CLASS_HID_51a93 = 0x51a93,
+ BNXT_ULP_CLASS_HID_48307 = 0x48307,
+ BNXT_ULP_CLASS_HID_492cb = 0x492cb,
+ BNXT_ULP_CLASS_HID_59297 = 0x59297,
+ BNXT_ULP_CLASS_HID_581d9 = 0x581d9,
+ BNXT_ULP_CLASS_HID_41653 = 0x41653,
+ BNXT_ULP_CLASS_HID_40655 = 0x40655,
+ BNXT_ULP_CLASS_HID_50601 = 0x50601,
+ BNXT_ULP_CLASS_HID_51545 = 0x51545,
+ BNXT_ULP_CLASS_HID_49e1b = 0x49e1b,
+ BNXT_ULP_CLASS_HID_48e1d = 0x48e1d,
+ BNXT_ULP_CLASS_HID_58d49 = 0x58d49,
+ BNXT_ULP_CLASS_HID_59d0d = 0x59d0d,
+ BNXT_ULP_CLASS_HID_40115 = 0x40115,
+ BNXT_ULP_CLASS_HID_41099 = 0x41099,
+ BNXT_ULP_CLASS_HID_51085 = 0x51085,
+ BNXT_ULP_CLASS_HID_5000f = 0x5000f,
+ BNXT_ULP_CLASS_HID_4889d = 0x4889d,
+ BNXT_ULP_CLASS_HID_49881 = 0x49881,
+ BNXT_ULP_CLASS_HID_5980d = 0x5980d,
+ BNXT_ULP_CLASS_HID_59797 = 0x59797,
+ BNXT_ULP_CLASS_HID_41c09 = 0x41c09,
+ BNXT_ULP_CLASS_HID_40c13 = 0x40c13,
+ BNXT_ULP_CLASS_HID_50b1f = 0x50b1f,
+ BNXT_ULP_CLASS_HID_51b03 = 0x51b03,
+ BNXT_ULP_CLASS_HID_48417 = 0x48417,
+ BNXT_ULP_CLASS_HID_4931b = 0x4931b,
+ BNXT_ULP_CLASS_HID_59307 = 0x59307,
+ BNXT_ULP_CLASS_HID_58309 = 0x58309,
+ BNXT_ULP_CLASS_HID_4160f = 0x4160f,
+ BNXT_ULP_CLASS_HID_40561 = 0x40561,
+ BNXT_ULP_CLASS_HID_5052d = 0x5052d,
+ BNXT_ULP_CLASS_HID_51501 = 0x51501,
+ BNXT_ULP_CLASS_HID_49dc7 = 0x49dc7,
+ BNXT_ULP_CLASS_HID_48d29 = 0x48d29,
+ BNXT_ULP_CLASS_HID_58d05 = 0x58d05,
+ BNXT_ULP_CLASS_HID_59cc9 = 0x59cc9,
+ BNXT_ULP_CLASS_HID_40161 = 0x40161,
+ BNXT_ULP_CLASS_HID_41125 = 0x41125,
+ BNXT_ULP_CLASS_HID_51061 = 0x51061,
+ BNXT_ULP_CLASS_HID_5004b = 0x5004b,
+ BNXT_ULP_CLASS_HID_48929 = 0x48929,
+ BNXT_ULP_CLASS_HID_4986d = 0x4986d,
+ BNXT_ULP_CLASS_HID_59829 = 0x59829,
+ BNXT_ULP_CLASS_HID_58823 = 0x58823,
+ BNXT_ULP_CLASS_HID_41ba5 = 0x41ba5,
+ BNXT_ULP_CLASS_HID_40b0f = 0x40b0f,
+ BNXT_ULP_CLASS_HID_50b0b = 0x50b0b,
+ BNXT_ULP_CLASS_HID_51a8f = 0x51a8f,
+ BNXT_ULP_CLASS_HID_48303 = 0x48303,
+ BNXT_ULP_CLASS_HID_49307 = 0x49307,
+ BNXT_ULP_CLASS_HID_592a3 = 0x592a3,
+ BNXT_ULP_CLASS_HID_58205 = 0x58205,
+ BNXT_ULP_CLASS_HID_4172f = 0x4172f,
+ BNXT_ULP_CLASS_HID_40621 = 0x40621,
+ BNXT_ULP_CLASS_HID_5062d = 0x5062d,
+ BNXT_ULP_CLASS_HID_51621 = 0x51621,
+ BNXT_ULP_CLASS_HID_49f07 = 0x49f07,
+ BNXT_ULP_CLASS_HID_48e29 = 0x48e29,
+ BNXT_ULP_CLASS_HID_58e25 = 0x58e25,
+ BNXT_ULP_CLASS_HID_59d29 = 0x59d29,
+ BNXT_ULP_CLASS_HID_400c9 = 0x400c9,
+ BNXT_ULP_CLASS_HID_4108d = 0x4108d,
+ BNXT_ULP_CLASS_HID_51049 = 0x51049,
+ BNXT_ULP_CLASS_HID_50fc3 = 0x50fc3,
+ BNXT_ULP_CLASS_HID_48881 = 0x48881,
+ BNXT_ULP_CLASS_HID_487cb = 0x487cb,
+ BNXT_ULP_CLASS_HID_587c7 = 0x587c7,
+ BNXT_ULP_CLASS_HID_5978b = 0x5978b,
+ BNXT_ULP_CLASS_HID_41c4d = 0x41c4d,
+ BNXT_ULP_CLASS_HID_40b47 = 0x40b47,
+ BNXT_ULP_CLASS_HID_50b03 = 0x50b03,
+ BNXT_ULP_CLASS_HID_51b47 = 0x51b47,
+ BNXT_ULP_CLASS_HID_4834b = 0x4834b,
+ BNXT_ULP_CLASS_HID_4930f = 0x4930f,
+ BNXT_ULP_CLASS_HID_5934b = 0x5934b,
+ BNXT_ULP_CLASS_HID_5824d = 0x5824d,
+ BNXT_ULP_CLASS_HID_41687 = 0x41687,
+ BNXT_ULP_CLASS_HID_40609 = 0x40609,
+ BNXT_ULP_CLASS_HID_50585 = 0x50585,
+ BNXT_ULP_CLASS_HID_51589 = 0x51589,
+ BNXT_ULP_CLASS_HID_49e0f = 0x49e0f,
+ BNXT_ULP_CLASS_HID_48d81 = 0x48d81,
+ BNXT_ULP_CLASS_HID_58d8d = 0x58d8d,
+ BNXT_ULP_CLASS_HID_59d01 = 0x59d01,
+ BNXT_ULP_CLASS_HID_40109 = 0x40109,
+ BNXT_ULP_CLASS_HID_4110d = 0x4110d,
+ BNXT_ULP_CLASS_HID_51109 = 0x51109,
+ BNXT_ULP_CLASS_HID_50003 = 0x50003,
+ BNXT_ULP_CLASS_HID_48901 = 0x48901,
+ BNXT_ULP_CLASS_HID_49905 = 0x49905,
+ BNXT_ULP_CLASS_HID_59901 = 0x59901,
+ BNXT_ULP_CLASS_HID_5880b = 0x5880b,
+ BNXT_ULP_CLASS_HID_10619 = 0x10619,
+ BNXT_ULP_CLASS_HID_11239 = 0x11239,
+ BNXT_ULP_CLASS_HID_14205 = 0x14205,
+ BNXT_ULP_CLASS_HID_15e25 = 0x15e25,
+ BNXT_ULP_CLASS_HID_12417 = 0x12417,
+ BNXT_ULP_CLASS_HID_13037 = 0x13037,
+ BNXT_ULP_CLASS_HID_16ff3 = 0x16ff3,
+ BNXT_ULP_CLASS_HID_17c13 = 0x17c13,
+ BNXT_ULP_CLASS_HID_1111d = 0x1111d,
+ BNXT_ULP_CLASS_HID_10cdb = 0x10cdb,
+ BNXT_ULP_CLASS_HID_15d19 = 0x15d19,
+ BNXT_ULP_CLASS_HID_148c7 = 0x148c7,
+ BNXT_ULP_CLASS_HID_13f0b = 0x13f0b,
+ BNXT_ULP_CLASS_HID_12ac9 = 0x12ac9,
+ BNXT_ULP_CLASS_HID_17b17 = 0x17b17,
+ BNXT_ULP_CLASS_HID_176d5 = 0x176d5,
+ BNXT_ULP_CLASS_HID_10bab = 0x10bab,
+ BNXT_ULP_CLASS_HID_10769 = 0x10769,
+ BNXT_ULP_CLASS_HID_15787 = 0x15787,
+ BNXT_ULP_CLASS_HID_14345 = 0x14345,
+ BNXT_ULP_CLASS_HID_12989 = 0x12989,
+ BNXT_ULP_CLASS_HID_12567 = 0x12567,
+ BNXT_ULP_CLASS_HID_17585 = 0x17585,
+ BNXT_ULP_CLASS_HID_16143 = 0x16143,
+ BNXT_ULP_CLASS_HID_1064d = 0x1064d,
+ BNXT_ULP_CLASS_HID_1128d = 0x1128d,
+ BNXT_ULP_CLASS_HID_14249 = 0x14249,
+ BNXT_ULP_CLASS_HID_15e49 = 0x15e49,
+ BNXT_ULP_CLASS_HID_1244b = 0x1244b,
+ BNXT_ULP_CLASS_HID_1304b = 0x1304b,
+ BNXT_ULP_CLASS_HID_16047 = 0x16047,
+ BNXT_ULP_CLASS_HID_17c47 = 0x17c47,
+ BNXT_ULP_CLASS_HID_11113 = 0x11113,
+ BNXT_ULP_CLASS_HID_10cd1 = 0x10cd1,
+ BNXT_ULP_CLASS_HID_15cf7 = 0x15cf7,
+ BNXT_ULP_CLASS_HID_148b5 = 0x148b5,
+ BNXT_ULP_CLASS_HID_13f01 = 0x13f01,
+ BNXT_ULP_CLASS_HID_12ac7 = 0x12ac7,
+ BNXT_ULP_CLASS_HID_17ae5 = 0x17ae5,
+ BNXT_ULP_CLASS_HID_176a3 = 0x176a3,
+ BNXT_ULP_CLASS_HID_10bd5 = 0x10bd5,
+ BNXT_ULP_CLASS_HID_10793 = 0x10793,
+ BNXT_ULP_CLASS_HID_15791 = 0x15791,
+ BNXT_ULP_CLASS_HID_14357 = 0x14357,
+ BNXT_ULP_CLASS_HID_129c3 = 0x129c3,
+ BNXT_ULP_CLASS_HID_12581 = 0x12581,
+ BNXT_ULP_CLASS_HID_17587 = 0x17587,
+ BNXT_ULP_CLASS_HID_16145 = 0x16145,
+ BNXT_ULP_CLASS_HID_10643 = 0x10643,
+ BNXT_ULP_CLASS_HID_11263 = 0x11263,
+ BNXT_ULP_CLASS_HID_14227 = 0x14227,
+ BNXT_ULP_CLASS_HID_15e47 = 0x15e47,
+ BNXT_ULP_CLASS_HID_12421 = 0x12421,
+ BNXT_ULP_CLASS_HID_13041 = 0x13041,
+ BNXT_ULP_CLASS_HID_16005 = 0x16005,
+ BNXT_ULP_CLASS_HID_17c25 = 0x17c25,
+ BNXT_ULP_CLASS_HID_11147 = 0x11147,
+ BNXT_ULP_CLASS_HID_10d05 = 0x10d05,
+ BNXT_ULP_CLASS_HID_15d43 = 0x15d43,
+ BNXT_ULP_CLASS_HID_14901 = 0x14901,
+ BNXT_ULP_CLASS_HID_13f45 = 0x13f45,
+ BNXT_ULP_CLASS_HID_12b03 = 0x12b03,
+ BNXT_ULP_CLASS_HID_17b01 = 0x17b01,
+ BNXT_ULP_CLASS_HID_176c7 = 0x176c7,
+ BNXT_ULP_CLASS_HID_11bcf = 0x11bcf,
+ BNXT_ULP_CLASS_HID_1178d = 0x1178d,
+ BNXT_ULP_CLASS_HID_1474d = 0x1474d,
+ BNXT_ULP_CLASS_HID_1536d = 0x1536d,
+ BNXT_ULP_CLASS_HID_139bd = 0x139bd,
+ BNXT_ULP_CLASS_HID_1357f = 0x1357f,
+ BNXT_ULP_CLASS_HID_16547 = 0x16547,
+ BNXT_ULP_CLASS_HID_17167 = 0x17167,
+ BNXT_ULP_CLASS_HID_11685 = 0x11685,
+ BNXT_ULP_CLASS_HID_1024f = 0x1024f,
+ BNXT_ULP_CLASS_HID_1524d = 0x1524d,
+ BNXT_ULP_CLASS_HID_14e0f = 0x14e0f,
+ BNXT_ULP_CLASS_HID_1345f = 0x1345f,
+ BNXT_ULP_CLASS_HID_1201d = 0x1201d,
+ BNXT_ULP_CLASS_HID_1705f = 0x1705f,
+ BNXT_ULP_CLASS_HID_16c1d = 0x16c1d,
+ BNXT_ULP_CLASS_HID_100ef = 0x100ef,
+ BNXT_ULP_CLASS_HID_11d0f = 0x11d0f,
+ BNXT_ULP_CLASS_HID_14ccf = 0x14ccf,
+ BNXT_ULP_CLASS_HID_158ef = 0x158ef,
+ BNXT_ULP_CLASS_HID_12eed = 0x12eed,
+ BNXT_ULP_CLASS_HID_13b0d = 0x13b0d,
+ BNXT_ULP_CLASS_HID_16acd = 0x16acd,
+ BNXT_ULP_CLASS_HID_16687 = 0x16687,
+ BNXT_ULP_CLASS_HID_11c07 = 0x11c07,
+ BNXT_ULP_CLASS_HID_117c5 = 0x117c5,
+ BNXT_ULP_CLASS_HID_1478d = 0x1478d,
+ BNXT_ULP_CLASS_HID_1538d = 0x1538d,
+ BNXT_ULP_CLASS_HID_13a05 = 0x13a05,
+ BNXT_ULP_CLASS_HID_135cf = 0x135cf,
+ BNXT_ULP_CLASS_HID_1658f = 0x1658f,
+ BNXT_ULP_CLASS_HID_1718f = 0x1718f,
+ BNXT_ULP_CLASS_HID_11667 = 0x11667,
+ BNXT_ULP_CLASS_HID_10225 = 0x10225,
+ BNXT_ULP_CLASS_HID_15247 = 0x15247,
+ BNXT_ULP_CLASS_HID_14e05 = 0x14e05,
+ BNXT_ULP_CLASS_HID_13455 = 0x13455,
+ BNXT_ULP_CLASS_HID_12017 = 0x12017,
+ BNXT_ULP_CLASS_HID_17035 = 0x17035,
+ BNXT_ULP_CLASS_HID_16bf7 = 0x16bf7,
+ BNXT_ULP_CLASS_HID_10115 = 0x10115,
+ BNXT_ULP_CLASS_HID_11d15 = 0x11d15,
+ BNXT_ULP_CLASS_HID_14d05 = 0x14d05,
+ BNXT_ULP_CLASS_HID_15905 = 0x15905,
+ BNXT_ULP_CLASS_HID_12f17 = 0x12f17,
+ BNXT_ULP_CLASS_HID_13b17 = 0x13b17,
+ BNXT_ULP_CLASS_HID_16ad7 = 0x16ad7,
+ BNXT_ULP_CLASS_HID_16695 = 0x16695,
+ BNXT_ULP_CLASS_HID_11be5 = 0x11be5,
+ BNXT_ULP_CLASS_HID_117a7 = 0x117a7,
+ BNXT_ULP_CLASS_HID_14767 = 0x14767,
+ BNXT_ULP_CLASS_HID_15387 = 0x15387,
+ BNXT_ULP_CLASS_HID_139e7 = 0x139e7,
+ BNXT_ULP_CLASS_HID_135a5 = 0x135a5,
+ BNXT_ULP_CLASS_HID_16565 = 0x16565,
+ BNXT_ULP_CLASS_HID_17185 = 0x17185,
+ BNXT_ULP_CLASS_HID_11687 = 0x11687,
+ BNXT_ULP_CLASS_HID_10245 = 0x10245,
+ BNXT_ULP_CLASS_HID_15287 = 0x15287,
+ BNXT_ULP_CLASS_HID_14e45 = 0x14e45,
+ BNXT_ULP_CLASS_HID_13485 = 0x13485,
+ BNXT_ULP_CLASS_HID_12047 = 0x12047,
+ BNXT_ULP_CLASS_HID_17085 = 0x17085,
+ BNXT_ULP_CLASS_HID_16c47 = 0x16c47,
+ BNXT_ULP_CLASS_HID_400f4 = 0x400f4,
+ BNXT_ULP_CLASS_HID_410c8 = 0x410c8,
+ BNXT_ULP_CLASS_HID_51084 = 0x51084,
+ BNXT_ULP_CLASS_HID_50ffe = 0x50ffe,
+ BNXT_ULP_CLASS_HID_488cc = 0x488cc,
+ BNXT_ULP_CLASS_HID_48726 = 0x48726,
+ BNXT_ULP_CLASS_HID_587f2 = 0x587f2,
+ BNXT_ULP_CLASS_HID_597b6 = 0x597b6,
+ BNXT_ULP_CLASS_HID_41b10 = 0x41b10,
+ BNXT_ULP_CLASS_HID_40b8a = 0x40b8a,
+ BNXT_ULP_CLASS_HID_50a46 = 0x50a46,
+ BNXT_ULP_CLASS_HID_51a1a = 0x51a1a,
+ BNXT_ULP_CLASS_HID_4838e = 0x4838e,
+ BNXT_ULP_CLASS_HID_49242 = 0x49242,
+ BNXT_ULP_CLASS_HID_5921e = 0x5921e,
+ BNXT_ULP_CLASS_HID_58150 = 0x58150,
+ BNXT_ULP_CLASS_HID_41686 = 0x41686,
+ BNXT_ULP_CLASS_HID_405e8 = 0x405e8,
+ BNXT_ULP_CLASS_HID_505a4 = 0x505a4,
+ BNXT_ULP_CLASS_HID_51588 = 0x51588,
+ BNXT_ULP_CLASS_HID_49d4e = 0x49d4e,
+ BNXT_ULP_CLASS_HID_48da0 = 0x48da0,
+ BNXT_ULP_CLASS_HID_58d8c = 0x58d8c,
+ BNXT_ULP_CLASS_HID_59c40 = 0x59c40,
+ BNXT_ULP_CLASS_HID_40040 = 0x40040,
+ BNXT_ULP_CLASS_HID_41004 = 0x41004,
+ BNXT_ULP_CLASS_HID_510c0 = 0x510c0,
+ BNXT_ULP_CLASS_HID_50f4a = 0x50f4a,
+ BNXT_ULP_CLASS_HID_48808 = 0x48808,
+ BNXT_ULP_CLASS_HID_48742 = 0x48742,
+ BNXT_ULP_CLASS_HID_5874e = 0x5874e,
+ BNXT_ULP_CLASS_HID_59702 = 0x59702,
+ BNXT_ULP_CLASS_HID_41bfe = 0x41bfe,
+ BNXT_ULP_CLASS_HID_40a58 = 0x40a58,
+ BNXT_ULP_CLASS_HID_50a2c = 0x50a2c,
+ BNXT_ULP_CLASS_HID_51ae8 = 0x51ae8,
+ BNXT_ULP_CLASS_HID_4825c = 0x4825c,
+ BNXT_ULP_CLASS_HID_49228 = 0x49228,
+ BNXT_ULP_CLASS_HID_592ec = 0x592ec,
+ BNXT_ULP_CLASS_HID_5815e = 0x5815e,
+ BNXT_ULP_CLASS_HID_41698 = 0x41698,
+ BNXT_ULP_CLASS_HID_4051a = 0x4051a,
+ BNXT_ULP_CLASS_HID_505ce = 0x505ce,
+ BNXT_ULP_CLASS_HID_5158a = 0x5158a,
+ BNXT_ULP_CLASS_HID_49d58 = 0x49d58,
+ BNXT_ULP_CLASS_HID_48dca = 0x48dca,
+ BNXT_ULP_CLASS_HID_58d8e = 0x58d8e,
+ BNXT_ULP_CLASS_HID_59c5a = 0x59c5a,
+ BNXT_ULP_CLASS_HID_4002e = 0x4002e,
+ BNXT_ULP_CLASS_HID_410ea = 0x410ea,
+ BNXT_ULP_CLASS_HID_510ae = 0x510ae,
+ BNXT_ULP_CLASS_HID_50f08 = 0x50f08,
+ BNXT_ULP_CLASS_HID_488ee = 0x488ee,
+ BNXT_ULP_CLASS_HID_48748 = 0x48748,
+ BNXT_ULP_CLASS_HID_5870c = 0x5870c,
+ BNXT_ULP_CLASS_HID_597e8 = 0x597e8,
+ BNXT_ULP_CLASS_HID_41b4a = 0x41b4a,
+ BNXT_ULP_CLASS_HID_40b8c = 0x40b8c,
+ BNXT_ULP_CLASS_HID_50a48 = 0x50a48,
+ BNXT_ULP_CLASS_HID_51a0c = 0x51a0c,
+ BNXT_ULP_CLASS_HID_48388 = 0x48388,
+ BNXT_ULP_CLASS_HID_4924c = 0x4924c,
+ BNXT_ULP_CLASS_HID_59208 = 0x59208,
+ BNXT_ULP_CLASS_HID_5828a = 0x5828a,
+ BNXT_ULP_CLASS_HID_40540 = 0x40540,
+ BNXT_ULP_CLASS_HID_41500 = 0x41500,
+ BNXT_ULP_CLASS_HID_515d0 = 0x515d0,
+ BNXT_ULP_CLASS_HID_5044a = 0x5044a,
+ BNXT_ULP_CLASS_HID_48d18 = 0x48d18,
+ BNXT_ULP_CLASS_HID_49dd8 = 0x49dd8,
+ BNXT_ULP_CLASS_HID_59da8 = 0x59da8,
+ BNXT_ULP_CLASS_HID_58c02 = 0x58c02,
+ BNXT_ULP_CLASS_HID_41048 = 0x41048,
+ BNXT_ULP_CLASS_HID_400c2 = 0x400c2,
+ BNXT_ULP_CLASS_HID_50092 = 0x50092,
+ BNXT_ULP_CLASS_HID_51f52 = 0x51f52,
+ BNXT_ULP_CLASS_HID_49800 = 0x49800,
+ BNXT_ULP_CLASS_HID_4889a = 0x4889a,
+ BNXT_ULP_CLASS_HID_5974a = 0x5974a,
+ BNXT_ULP_CLASS_HID_587c8 = 0x587c8,
+ BNXT_ULP_CLASS_HID_40bc2 = 0x40bc2,
+ BNXT_ULP_CLASS_HID_41b82 = 0x41b82,
+ BNXT_ULP_CLASS_HID_51a62 = 0x51a62,
+ BNXT_ULP_CLASS_HID_50ac0 = 0x50ac0,
+ BNXT_ULP_CLASS_HID_493aa = 0x493aa,
+ BNXT_ULP_CLASS_HID_48208 = 0x48208,
+ BNXT_ULP_CLASS_HID_582c8 = 0x582c8,
+ BNXT_ULP_CLASS_HID_59288 = 0x59288,
+ BNXT_ULP_CLASS_HID_40688 = 0x40688,
+ BNXT_ULP_CLASS_HID_41540 = 0x41540,
+ BNXT_ULP_CLASS_HID_51508 = 0x51508,
+ BNXT_ULP_CLASS_HID_50582 = 0x50582,
+ BNXT_ULP_CLASS_HID_48d40 = 0x48d40,
+ BNXT_ULP_CLASS_HID_49d08 = 0x49d08,
+ BNXT_ULP_CLASS_HID_59dc0 = 0x59dc0,
+ BNXT_ULP_CLASS_HID_58c4a = 0x58c4a,
+ BNXT_ULP_CLASS_HID_4104a = 0x4104a,
+ BNXT_ULP_CLASS_HID_400a8 = 0x400a8,
+ BNXT_ULP_CLASS_HID_50f78 = 0x50f78,
+ BNXT_ULP_CLASS_HID_51f38 = 0x51f38,
+ BNXT_ULP_CLASS_HID_4980a = 0x4980a,
+ BNXT_ULP_CLASS_HID_49768 = 0x49768,
+ BNXT_ULP_CLASS_HID_59738 = 0x59738,
+ BNXT_ULP_CLASS_HID_587aa = 0x587aa,
+ BNXT_ULP_CLASS_HID_40bd8 = 0x40bd8,
+ BNXT_ULP_CLASS_HID_41bc8 = 0x41bc8,
+ BNXT_ULP_CLASS_HID_51b88 = 0x51b88,
+ BNXT_ULP_CLASS_HID_50ada = 0x50ada,
+ BNXT_ULP_CLASS_HID_493c8 = 0x493c8,
+ BNXT_ULP_CLASS_HID_4820a = 0x4820a,
+ BNXT_ULP_CLASS_HID_582da = 0x582da,
+ BNXT_ULP_CLASS_HID_5929a = 0x5929a,
+ BNXT_ULP_CLASS_HID_4056a = 0x4056a,
+ BNXT_ULP_CLASS_HID_4152a = 0x4152a,
+ BNXT_ULP_CLASS_HID_5150a = 0x5150a,
+ BNXT_ULP_CLASS_HID_50468 = 0x50468,
+ BNXT_ULP_CLASS_HID_48d2a = 0x48d2a,
+ BNXT_ULP_CLASS_HID_49dea = 0x49dea,
+ BNXT_ULP_CLASS_HID_59dca = 0x59dca,
+ BNXT_ULP_CLASS_HID_58c28 = 0x58c28,
+ BNXT_ULP_CLASS_HID_4118a = 0x4118a,
+ BNXT_ULP_CLASS_HID_400c8 = 0x400c8,
+ BNXT_ULP_CLASS_HID_50088 = 0x50088,
+ BNXT_ULP_CLASS_HID_51088 = 0x51088,
+ BNXT_ULP_CLASS_HID_4984a = 0x4984a,
+ BNXT_ULP_CLASS_HID_48888 = 0x48888,
+ BNXT_ULP_CLASS_HID_58888 = 0x58888,
+ BNXT_ULP_CLASS_HID_587ca = 0x587ca,
+ BNXT_ULP_CLASS_HID_10690 = 0x10690,
+ BNXT_ULP_CLASS_HID_112b0 = 0x112b0,
+ BNXT_ULP_CLASS_HID_1428c = 0x1428c,
+ BNXT_ULP_CLASS_HID_15eac = 0x15eac,
+ BNXT_ULP_CLASS_HID_1249e = 0x1249e,
+ BNXT_ULP_CLASS_HID_130be = 0x130be,
+ BNXT_ULP_CLASS_HID_16f7a = 0x16f7a,
+ BNXT_ULP_CLASS_HID_17c9a = 0x17c9a,
+ BNXT_ULP_CLASS_HID_1119a = 0x1119a,
+ BNXT_ULP_CLASS_HID_10c58 = 0x10c58,
+ BNXT_ULP_CLASS_HID_15c7e = 0x15c7e,
+ BNXT_ULP_CLASS_HID_1483c = 0x1483c,
+ BNXT_ULP_CLASS_HID_13f88 = 0x13f88,
+ BNXT_ULP_CLASS_HID_12a4e = 0x12a4e,
+ BNXT_ULP_CLASS_HID_17a6c = 0x17a6c,
+ BNXT_ULP_CLASS_HID_1762a = 0x1762a,
+ BNXT_ULP_CLASS_HID_11b46 = 0x11b46,
+ BNXT_ULP_CLASS_HID_11704 = 0x11704,
+ BNXT_ULP_CLASS_HID_147c4 = 0x147c4,
+ BNXT_ULP_CLASS_HID_153e4 = 0x153e4,
+ BNXT_ULP_CLASS_HID_13934 = 0x13934,
+ BNXT_ULP_CLASS_HID_135f6 = 0x135f6,
+ BNXT_ULP_CLASS_HID_165ce = 0x165ce,
+ BNXT_ULP_CLASS_HID_171ee = 0x171ee,
+ BNXT_ULP_CLASS_HID_116ee = 0x116ee,
+ BNXT_ULP_CLASS_HID_102ac = 0x102ac,
+ BNXT_ULP_CLASS_HID_152ce = 0x152ce,
+ BNXT_ULP_CLASS_HID_14e8c = 0x14e8c,
+ BNXT_ULP_CLASS_HID_134dc = 0x134dc,
+ BNXT_ULP_CLASS_HID_1209e = 0x1209e,
+ BNXT_ULP_CLASS_HID_170bc = 0x170bc,
+ BNXT_ULP_CLASS_HID_16b7e = 0x16b7e,
+ BNXT_ULP_CLASS_HID_119ae = 0x119ae,
+ BNXT_ULP_CLASS_HID_1146a = 0x1146a,
+ BNXT_ULP_CLASS_HID_14426 = 0x14426,
+ BNXT_ULP_CLASS_HID_15046 = 0x15046,
+ BNXT_ULP_CLASS_HID_1263a = 0x1263a,
+ BNXT_ULP_CLASS_HID_1325a = 0x1325a,
+ BNXT_ULP_CLASS_HID_16216 = 0x16216,
+ BNXT_ULP_CLASS_HID_17e36 = 0x17e36,
+ BNXT_ULP_CLASS_HID_1133e = 0x1133e,
+ BNXT_ULP_CLASS_HID_10ffa = 0x10ffa,
+ BNXT_ULP_CLASS_HID_15f1a = 0x15f1a,
+ BNXT_ULP_CLASS_HID_14bee = 0x14bee,
+ BNXT_ULP_CLASS_HID_1312a = 0x1312a,
+ BNXT_ULP_CLASS_HID_12dea = 0x12dea,
+ BNXT_ULP_CLASS_HID_17d1e = 0x17d1e,
+ BNXT_ULP_CLASS_HID_169de = 0x169de,
+ BNXT_ULP_CLASS_HID_11ee6 = 0x11ee6,
+ BNXT_ULP_CLASS_HID_10abe = 0x10abe,
+ BNXT_ULP_CLASS_HID_15ade = 0x15ade,
+ BNXT_ULP_CLASS_HID_1569e = 0x1569e,
+ BNXT_ULP_CLASS_HID_13cee = 0x13cee,
+ BNXT_ULP_CLASS_HID_128ae = 0x128ae,
+ BNXT_ULP_CLASS_HID_1676e = 0x1676e,
+ BNXT_ULP_CLASS_HID_1748e = 0x1748e,
+ BNXT_ULP_CLASS_HID_1098e = 0x1098e,
+ BNXT_ULP_CLASS_HID_1044e = 0x1044e,
+ BNXT_ULP_CLASS_HID_1546e = 0x1546e,
+ BNXT_ULP_CLASS_HID_1402e = 0x1402e,
+ BNXT_ULP_CLASS_HID_1367e = 0x1367e,
+ BNXT_ULP_CLASS_HID_1223e = 0x1223e,
+ BNXT_ULP_CLASS_HID_1725e = 0x1725e,
+ BNXT_ULP_CLASS_HID_16e1e = 0x16e1e,
+ BNXT_ULP_CLASS_HID_1172f = 0x1172f,
+ BNXT_ULP_CLASS_HID_103ed = 0x103ed,
+ BNXT_ULP_CLASS_HID_1530b = 0x1530b,
+ BNXT_ULP_CLASS_HID_14fc9 = 0x14fc9,
+ BNXT_ULP_CLASS_HID_1351d = 0x1351d,
+ BNXT_ULP_CLASS_HID_121db = 0x121db,
+ BNXT_ULP_CLASS_HID_171f9 = 0x171f9,
+ BNXT_ULP_CLASS_HID_16db7 = 0x16db7,
+ BNXT_ULP_CLASS_HID_102bf = 0x102bf,
+ BNXT_ULP_CLASS_HID_11edf = 0x11edf,
+ BNXT_ULP_CLASS_HID_14e9b = 0x14e9b,
+ BNXT_ULP_CLASS_HID_15abb = 0x15abb,
+ BNXT_ULP_CLASS_HID_120ad = 0x120ad,
+ BNXT_ULP_CLASS_HID_13ccd = 0x13ccd,
+ BNXT_ULP_CLASS_HID_16c89 = 0x16c89,
+ BNXT_ULP_CLASS_HID_1675f = 0x1675f,
+ BNXT_ULP_CLASS_HID_10c67 = 0x10c67,
+ BNXT_ULP_CLASS_HID_11987 = 0x11987,
+ BNXT_ULP_CLASS_HID_1485f = 0x1485f,
+ BNXT_ULP_CLASS_HID_1441d = 0x1441d,
+ BNXT_ULP_CLASS_HID_12a55 = 0x12a55,
+ BNXT_ULP_CLASS_HID_1262f = 0x1262f,
+ BNXT_ULP_CLASS_HID_1764d = 0x1764d,
+ BNXT_ULP_CLASS_HID_1620f = 0x1620f,
+ BNXT_ULP_CLASS_HID_1070f = 0x1070f,
+ BNXT_ULP_CLASS_HID_1132f = 0x1132f,
+ BNXT_ULP_CLASS_HID_143ef = 0x143ef,
+ BNXT_ULP_CLASS_HID_15f0f = 0x15f0f,
+ BNXT_ULP_CLASS_HID_125fd = 0x125fd,
+ BNXT_ULP_CLASS_HID_1311d = 0x1311d,
+ BNXT_ULP_CLASS_HID_161dd = 0x161dd,
+ BNXT_ULP_CLASS_HID_17dfd = 0x17dfd,
+ BNXT_ULP_CLASS_HID_10acb = 0x10acb,
+ BNXT_ULP_CLASS_HID_10687 = 0x10687,
+ BNXT_ULP_CLASS_HID_156a7 = 0x156a7,
+ BNXT_ULP_CLASS_HID_14163 = 0x14163,
+ BNXT_ULP_CLASS_HID_128b7 = 0x128b7,
+ BNXT_ULP_CLASS_HID_12377 = 0x12377,
+ BNXT_ULP_CLASS_HID_17493 = 0x17493,
+ BNXT_ULP_CLASS_HID_16f53 = 0x16f53,
+ BNXT_ULP_CLASS_HID_1045b = 0x1045b,
+ BNXT_ULP_CLASS_HID_1107b = 0x1107b,
+ BNXT_ULP_CLASS_HID_1404f = 0x1404f,
+ BNXT_ULP_CLASS_HID_15c6f = 0x15c6f,
+ BNXT_ULP_CLASS_HID_1225f = 0x1225f,
+ BNXT_ULP_CLASS_HID_13e7f = 0x13e7f,
+ BNXT_ULP_CLASS_HID_16e3b = 0x16e3b,
+ BNXT_ULP_CLASS_HID_17a5b = 0x17a5b,
+ BNXT_ULP_CLASS_HID_10f1f = 0x10f1f,
+ BNXT_ULP_CLASS_HID_11b3f = 0x11b3f,
+ BNXT_ULP_CLASS_HID_14bff = 0x14bff,
+ BNXT_ULP_CLASS_HID_147b7 = 0x147b7,
+ BNXT_ULP_CLASS_HID_12d0f = 0x12d0f,
+ BNXT_ULP_CLASS_HID_1392f = 0x1392f,
+ BNXT_ULP_CLASS_HID_169e7 = 0x169e7,
+ BNXT_ULP_CLASS_HID_165a7 = 0x165a7,
+ BNXT_ULP_CLASS_HID_11a0f = 0x11a0f,
+ BNXT_ULP_CLASS_HID_116cf = 0x116cf,
+ BNXT_ULP_CLASS_HID_1468f = 0x1468f,
+ BNXT_ULP_CLASS_HID_152af = 0x152af,
+ BNXT_ULP_CLASS_HID_138ff = 0x138ff,
+ BNXT_ULP_CLASS_HID_134bf = 0x134bf,
+ BNXT_ULP_CLASS_HID_1648f = 0x1648f,
+ BNXT_ULP_CLASS_HID_170af = 0x170af,
+ BNXT_ULP_CLASS_HID_40c38 = 0x40c38,
+ BNXT_ULP_CLASS_HID_41c04 = 0x41c04,
+ BNXT_ULP_CLASS_HID_51c48 = 0x51c48,
+ BNXT_ULP_CLASS_HID_50332 = 0x50332,
+ BNXT_ULP_CLASS_HID_48400 = 0x48400,
+ BNXT_ULP_CLASS_HID_48bea = 0x48bea,
+ BNXT_ULP_CLASS_HID_58b3e = 0x58b3e,
+ BNXT_ULP_CLASS_HID_59b7a = 0x59b7a,
+ BNXT_ULP_CLASS_HID_417dc = 0x417dc,
+ BNXT_ULP_CLASS_HID_40746 = 0x40746,
+ BNXT_ULP_CLASS_HID_5068a = 0x5068a,
+ BNXT_ULP_CLASS_HID_516d6 = 0x516d6,
+ BNXT_ULP_CLASS_HID_48f42 = 0x48f42,
+ BNXT_ULP_CLASS_HID_49e8e = 0x49e8e,
+ BNXT_ULP_CLASS_HID_59ed2 = 0x59ed2,
+ BNXT_ULP_CLASS_HID_58d9c = 0x58d9c,
+ BNXT_ULP_CLASS_HID_41a4a = 0x41a4a,
+ BNXT_ULP_CLASS_HID_40924 = 0x40924,
+ BNXT_ULP_CLASS_HID_50968 = 0x50968,
+ BNXT_ULP_CLASS_HID_51944 = 0x51944,
+ BNXT_ULP_CLASS_HID_49182 = 0x49182,
+ BNXT_ULP_CLASS_HID_4816c = 0x4816c,
+ BNXT_ULP_CLASS_HID_58140 = 0x58140,
+ BNXT_ULP_CLASS_HID_5908c = 0x5908c,
+ BNXT_ULP_CLASS_HID_40c8c = 0x40c8c,
+ BNXT_ULP_CLASS_HID_41cc8 = 0x41cc8,
+ BNXT_ULP_CLASS_HID_51c0c = 0x51c0c,
+ BNXT_ULP_CLASS_HID_50386 = 0x50386,
+ BNXT_ULP_CLASS_HID_484c4 = 0x484c4,
+ BNXT_ULP_CLASS_HID_48b8e = 0x48b8e,
+ BNXT_ULP_CLASS_HID_58b82 = 0x58b82,
+ BNXT_ULP_CLASS_HID_59bce = 0x59bce,
+ BNXT_ULP_CLASS_HID_10a54 = 0x10a54,
+ BNXT_ULP_CLASS_HID_11e74 = 0x11e74,
+ BNXT_ULP_CLASS_HID_14e48 = 0x14e48,
+ BNXT_ULP_CLASS_HID_15268 = 0x15268,
+ BNXT_ULP_CLASS_HID_1285a = 0x1285a,
+ BNXT_ULP_CLASS_HID_13c7a = 0x13c7a,
+ BNXT_ULP_CLASS_HID_163be = 0x163be,
+ BNXT_ULP_CLASS_HID_1705e = 0x1705e,
+ BNXT_ULP_CLASS_HID_11d5e = 0x11d5e,
+ BNXT_ULP_CLASS_HID_1009c = 0x1009c,
+ BNXT_ULP_CLASS_HID_150ba = 0x150ba,
+ BNXT_ULP_CLASS_HID_144f8 = 0x144f8,
+ BNXT_ULP_CLASS_HID_1334c = 0x1334c,
+ BNXT_ULP_CLASS_HID_1268a = 0x1268a,
+ BNXT_ULP_CLASS_HID_176a8 = 0x176a8,
+ BNXT_ULP_CLASS_HID_17aee = 0x17aee,
+ BNXT_ULP_CLASS_HID_11782 = 0x11782,
+ BNXT_ULP_CLASS_HID_11bc0 = 0x11bc0,
+ BNXT_ULP_CLASS_HID_14b00 = 0x14b00,
+ BNXT_ULP_CLASS_HID_15f20 = 0x15f20,
+ BNXT_ULP_CLASS_HID_135f0 = 0x135f0,
+ BNXT_ULP_CLASS_HID_13932 = 0x13932,
+ BNXT_ULP_CLASS_HID_1690a = 0x1690a,
+ BNXT_ULP_CLASS_HID_17d2a = 0x17d2a,
+ BNXT_ULP_CLASS_HID_11a2a = 0x11a2a,
+ BNXT_ULP_CLASS_HID_10e68 = 0x10e68,
+ BNXT_ULP_CLASS_HID_15e0a = 0x15e0a,
+ BNXT_ULP_CLASS_HID_14248 = 0x14248,
+ BNXT_ULP_CLASS_HID_13818 = 0x13818,
+ BNXT_ULP_CLASS_HID_12c5a = 0x12c5a,
+ BNXT_ULP_CLASS_HID_17c78 = 0x17c78,
+ BNXT_ULP_CLASS_HID_167ba = 0x167ba,
+ BNXT_ULP_CLASS_HID_1f91 = 0x1f91,
+ BNXT_ULP_CLASS_HID_0763 = 0x0763,
+ BNXT_ULP_CLASS_HID_0f7b = 0x0f7b,
+ BNXT_ULP_CLASS_HID_16af = 0x16af,
+ BNXT_ULP_CLASS_HID_1daf = 0x1daf,
+ BNXT_ULP_CLASS_HID_0539 = 0x0539,
+ BNXT_ULP_CLASS_HID_01ed = 0x01ed,
+ BNXT_ULP_CLASS_HID_097f = 0x097f,
+ BNXT_ULP_CLASS_HID_81ab8 = 0x81ab8,
+ BNXT_ULP_CLASS_HID_8020e = 0x8020e,
+ BNXT_ULP_CLASS_HID_815d8 = 0x815d8,
+ BNXT_ULP_CLASS_HID_81cae = 0x81cae,
+ BNXT_ULP_CLASS_HID_810a8 = 0x810a8,
+ BNXT_ULP_CLASS_HID_8183e = 0x8183e,
+ BNXT_ULP_CLASS_HID_8036a = 0x8036a,
+ BNXT_ULP_CLASS_HID_80af8 = 0x80af8,
+ BNXT_ULP_CLASS_HID_206fe = 0x206fe,
+ BNXT_ULP_CLASS_HID_20e4c = 0x20e4c,
+ BNXT_ULP_CLASS_HID_2111e = 0x2111e,
+ BNXT_ULP_CLASS_HID_218ec = 0x218ec,
+ BNXT_ULP_CLASS_HID_60472 = 0x60472,
+ BNXT_ULP_CLASS_HID_603c0 = 0x603c0,
+ BNXT_ULP_CLASS_HID_61692 = 0x61692,
+ BNXT_ULP_CLASS_HID_61e60 = 0x61e60,
+ BNXT_ULP_CLASS_HID_1f81 = 0x1f81,
+ BNXT_ULP_CLASS_HID_0773 = 0x0773,
+ BNXT_ULP_CLASS_HID_0f6b = 0x0f6b,
+ BNXT_ULP_CLASS_HID_16bf = 0x16bf,
+ BNXT_ULP_CLASS_HID_03cf = 0x03cf,
+ BNXT_ULP_CLASS_HID_0ab1 = 0x0ab1,
+ BNXT_ULP_CLASS_HID_130b = 0x130b,
+ BNXT_ULP_CLASS_HID_1afd = 0x1afd,
+ BNXT_ULP_CLASS_HID_1591 = 0x1591,
+ BNXT_ULP_CLASS_HID_1d03 = 0x1d03,
+ BNXT_ULP_CLASS_HID_057b = 0x057b,
+ BNXT_ULP_CLASS_HID_0ced = 0x0ced,
+ BNXT_ULP_CLASS_HID_19df = 0x19df,
+ BNXT_ULP_CLASS_HID_0141 = 0x0141,
+ BNXT_ULP_CLASS_HID_08b9 = 0x08b9,
+ BNXT_ULP_CLASS_HID_108d = 0x108d,
+ BNXT_ULP_CLASS_HID_1dbf = 0x1dbf,
+ BNXT_ULP_CLASS_HID_0529 = 0x0529,
+ BNXT_ULP_CLASS_HID_01fd = 0x01fd,
+ BNXT_ULP_CLASS_HID_096f = 0x096f,
+ BNXT_ULP_CLASS_HID_810b7 = 0x810b7,
+ BNXT_ULP_CLASS_HID_81821 = 0x81821,
+ BNXT_ULP_CLASS_HID_804f5 = 0x804f5,
+ BNXT_ULP_CLASS_HID_80c67 = 0x80c67,
+ BNXT_ULP_CLASS_HID_41333 = 0x41333,
+ BNXT_ULP_CLASS_HID_41aad = 0x41aad,
+ BNXT_ULP_CLASS_HID_40771 = 0x40771,
+ BNXT_ULP_CLASS_HID_40ee3 = 0x40ee3,
+ BNXT_ULP_CLASS_HID_c16cb = 0xc16cb,
+ BNXT_ULP_CLASS_HID_c1da5 = 0xc1da5,
+ BNXT_ULP_CLASS_HID_c1a09 = 0xc1a09,
+ BNXT_ULP_CLASS_HID_c01fb = 0xc01fb,
+ BNXT_ULP_CLASS_HID_1ff1 = 0x1ff1,
+ BNXT_ULP_CLASS_HID_0703 = 0x0703,
+ BNXT_ULP_CLASS_HID_0f1b = 0x0f1b,
+ BNXT_ULP_CLASS_HID_16cf = 0x16cf,
+ BNXT_ULP_CLASS_HID_03bf = 0x03bf,
+ BNXT_ULP_CLASS_HID_0ac1 = 0x0ac1,
+ BNXT_ULP_CLASS_HID_137b = 0x137b,
+ BNXT_ULP_CLASS_HID_1a8d = 0x1a8d,
+ BNXT_ULP_CLASS_HID_15e1 = 0x15e1,
+ BNXT_ULP_CLASS_HID_1d73 = 0x1d73,
+ BNXT_ULP_CLASS_HID_050b = 0x050b,
+ BNXT_ULP_CLASS_HID_0c9d = 0x0c9d,
+ BNXT_ULP_CLASS_HID_19af = 0x19af,
+ BNXT_ULP_CLASS_HID_0131 = 0x0131,
+ BNXT_ULP_CLASS_HID_08c9 = 0x08c9,
+ BNXT_ULP_CLASS_HID_10fd = 0x10fd,
+ BNXT_ULP_CLASS_HID_1dcf = 0x1dcf,
+ BNXT_ULP_CLASS_HID_0559 = 0x0559,
+ BNXT_ULP_CLASS_HID_018d = 0x018d,
+ BNXT_ULP_CLASS_HID_091f = 0x091f,
+ BNXT_ULP_CLASS_HID_810c7 = 0x810c7,
+ BNXT_ULP_CLASS_HID_81851 = 0x81851,
+ BNXT_ULP_CLASS_HID_80485 = 0x80485,
+ BNXT_ULP_CLASS_HID_80c17 = 0x80c17,
+ BNXT_ULP_CLASS_HID_41343 = 0x41343,
+ BNXT_ULP_CLASS_HID_41add = 0x41add,
+ BNXT_ULP_CLASS_HID_40701 = 0x40701,
+ BNXT_ULP_CLASS_HID_40e93 = 0x40e93,
+ BNXT_ULP_CLASS_HID_c16bb = 0xc16bb,
+ BNXT_ULP_CLASS_HID_c1dd5 = 0xc1dd5,
+ BNXT_ULP_CLASS_HID_c1a79 = 0xc1a79,
+ BNXT_ULP_CLASS_HID_c018b = 0xc018b,
+ BNXT_ULP_CLASS_HID_81aa8 = 0x81aa8,
+ BNXT_ULP_CLASS_HID_8021e = 0x8021e,
+ BNXT_ULP_CLASS_HID_815c8 = 0x815c8,
+ BNXT_ULP_CLASS_HID_81cbe = 0x81cbe,
+ BNXT_ULP_CLASS_HID_810b8 = 0x810b8,
+ BNXT_ULP_CLASS_HID_8182e = 0x8182e,
+ BNXT_ULP_CLASS_HID_8037a = 0x8037a,
+ BNXT_ULP_CLASS_HID_80ae8 = 0x80ae8,
+ BNXT_ULP_CLASS_HID_c1834 = 0xc1834,
+ BNXT_ULP_CLASS_HID_c079a = 0xc079a,
+ BNXT_ULP_CLASS_HID_c0af6 = 0xc0af6,
+ BNXT_ULP_CLASS_HID_c123a = 0xc123a,
+ BNXT_ULP_CLASS_HID_c16c4 = 0xc16c4,
+ BNXT_ULP_CLASS_HID_c1daa = 0xc1daa,
+ BNXT_ULP_CLASS_HID_c0086 = 0xc0086,
+ BNXT_ULP_CLASS_HID_c0874 = 0xc0874,
+ BNXT_ULP_CLASS_HID_a19ea = 0xa19ea,
+ BNXT_ULP_CLASS_HID_a0158 = 0xa0158,
+ BNXT_ULP_CLASS_HID_a0bb4 = 0xa0bb4,
+ BNXT_ULP_CLASS_HID_a13f8 = 0xa13f8,
+ BNXT_ULP_CLASS_HID_a17fa = 0xa17fa,
+ BNXT_ULP_CLASS_HID_a1f68 = 0xa1f68,
+ BNXT_ULP_CLASS_HID_a0244 = 0xa0244,
+ BNXT_ULP_CLASS_HID_a092a = 0xa092a,
+ BNXT_ULP_CLASS_HID_e1f76 = 0xe1f76,
+ BNXT_ULP_CLASS_HID_e06e4 = 0xe06e4,
+ BNXT_ULP_CLASS_HID_e0930 = 0xe0930,
+ BNXT_ULP_CLASS_HID_e1104 = 0xe1104,
+ BNXT_ULP_CLASS_HID_e1506 = 0xe1506,
+ BNXT_ULP_CLASS_HID_e1cf4 = 0xe1cf4,
+ BNXT_ULP_CLASS_HID_e07c0 = 0xe07c0,
+ BNXT_ULP_CLASS_HID_e0eb6 = 0xe0eb6,
+ BNXT_ULP_CLASS_HID_206ee = 0x206ee,
+ BNXT_ULP_CLASS_HID_20e5c = 0x20e5c,
+ BNXT_ULP_CLASS_HID_2110e = 0x2110e,
+ BNXT_ULP_CLASS_HID_218fc = 0x218fc,
+ BNXT_ULP_CLASS_HID_60462 = 0x60462,
+ BNXT_ULP_CLASS_HID_603d0 = 0x603d0,
+ BNXT_ULP_CLASS_HID_61682 = 0x61682,
+ BNXT_ULP_CLASS_HID_61e70 = 0x61e70,
+ BNXT_ULP_CLASS_HID_3167e = 0x3167e,
+ BNXT_ULP_CLASS_HID_31dec = 0x31dec,
+ BNXT_ULP_CLASS_HID_30030 = 0x30030,
+ BNXT_ULP_CLASS_HID_30fae = 0x30fae,
+ BNXT_ULP_CLASS_HID_70b14 = 0x70b14,
+ BNXT_ULP_CLASS_HID_71360 = 0x71360,
+ BNXT_ULP_CLASS_HID_705b4 = 0x705b4,
+ BNXT_ULP_CLASS_HID_70d22 = 0x70d22,
+ BNXT_ULP_CLASS_HID_29e26 = 0x29e26,
+ BNXT_ULP_CLASS_HID_28594 = 0x28594,
+ BNXT_ULP_CLASS_HID_288f8 = 0x288f8,
+ BNXT_ULP_CLASS_HID_29034 = 0x29034,
+ BNXT_ULP_CLASS_HID_693ba = 0x693ba,
+ BNXT_ULP_CLASS_HID_69b28 = 0x69b28,
+ BNXT_ULP_CLASS_HID_68e7c = 0x68e7c,
+ BNXT_ULP_CLASS_HID_69648 = 0x69648,
+ BNXT_ULP_CLASS_HID_38de8 = 0x38de8,
+ BNXT_ULP_CLASS_HID_39524 = 0x39524,
+ BNXT_ULP_CLASS_HID_39808 = 0x39808,
+ BNXT_ULP_CLASS_HID_387e6 = 0x387e6,
+ BNXT_ULP_CLASS_HID_7836c = 0x7836c,
+ BNXT_ULP_CLASS_HID_78ada = 0x78ada,
+ BNXT_ULP_CLASS_HID_79d8c = 0x79d8c,
+ BNXT_ULP_CLASS_HID_7857a = 0x7857a,
+ BNXT_ULP_CLASS_HID_81ad8 = 0x81ad8,
+ BNXT_ULP_CLASS_HID_8026e = 0x8026e,
+ BNXT_ULP_CLASS_HID_815b8 = 0x815b8,
+ BNXT_ULP_CLASS_HID_81cce = 0x81cce,
+ BNXT_ULP_CLASS_HID_810c8 = 0x810c8,
+ BNXT_ULP_CLASS_HID_8185e = 0x8185e,
+ BNXT_ULP_CLASS_HID_8030a = 0x8030a,
+ BNXT_ULP_CLASS_HID_80a98 = 0x80a98,
+ BNXT_ULP_CLASS_HID_c1844 = 0xc1844,
+ BNXT_ULP_CLASS_HID_c07ea = 0xc07ea,
+ BNXT_ULP_CLASS_HID_c0a86 = 0xc0a86,
+ BNXT_ULP_CLASS_HID_c124a = 0xc124a,
+ BNXT_ULP_CLASS_HID_c16b4 = 0xc16b4,
+ BNXT_ULP_CLASS_HID_c1dda = 0xc1dda,
+ BNXT_ULP_CLASS_HID_c00f6 = 0xc00f6,
+ BNXT_ULP_CLASS_HID_c0804 = 0xc0804,
+ BNXT_ULP_CLASS_HID_a199a = 0xa199a,
+ BNXT_ULP_CLASS_HID_a0128 = 0xa0128,
+ BNXT_ULP_CLASS_HID_a0bc4 = 0xa0bc4,
+ BNXT_ULP_CLASS_HID_a1388 = 0xa1388,
+ BNXT_ULP_CLASS_HID_a178a = 0xa178a,
+ BNXT_ULP_CLASS_HID_a1f18 = 0xa1f18,
+ BNXT_ULP_CLASS_HID_a0234 = 0xa0234,
+ BNXT_ULP_CLASS_HID_a095a = 0xa095a,
+ BNXT_ULP_CLASS_HID_e1f06 = 0xe1f06,
+ BNXT_ULP_CLASS_HID_e0694 = 0xe0694,
+ BNXT_ULP_CLASS_HID_e0940 = 0xe0940,
+ BNXT_ULP_CLASS_HID_e1174 = 0xe1174,
+ BNXT_ULP_CLASS_HID_e1576 = 0xe1576,
+ BNXT_ULP_CLASS_HID_e1c84 = 0xe1c84,
+ BNXT_ULP_CLASS_HID_e07b0 = 0xe07b0,
+ BNXT_ULP_CLASS_HID_e0ec6 = 0xe0ec6,
+ BNXT_ULP_CLASS_HID_2069e = 0x2069e,
+ BNXT_ULP_CLASS_HID_20e2c = 0x20e2c,
+ BNXT_ULP_CLASS_HID_2117e = 0x2117e,
+ BNXT_ULP_CLASS_HID_2188c = 0x2188c,
+ BNXT_ULP_CLASS_HID_60412 = 0x60412,
+ BNXT_ULP_CLASS_HID_603a0 = 0x603a0,
+ BNXT_ULP_CLASS_HID_616f2 = 0x616f2,
+ BNXT_ULP_CLASS_HID_61e00 = 0x61e00,
+ BNXT_ULP_CLASS_HID_3160e = 0x3160e,
+ BNXT_ULP_CLASS_HID_31d9c = 0x31d9c,
+ BNXT_ULP_CLASS_HID_30040 = 0x30040,
+ BNXT_ULP_CLASS_HID_30fde = 0x30fde,
+ BNXT_ULP_CLASS_HID_70b64 = 0x70b64,
+ BNXT_ULP_CLASS_HID_71310 = 0x71310,
+ BNXT_ULP_CLASS_HID_705c4 = 0x705c4,
+ BNXT_ULP_CLASS_HID_70d52 = 0x70d52,
+ BNXT_ULP_CLASS_HID_29e56 = 0x29e56,
+ BNXT_ULP_CLASS_HID_285e4 = 0x285e4,
+ BNXT_ULP_CLASS_HID_28888 = 0x28888,
+ BNXT_ULP_CLASS_HID_29044 = 0x29044,
+ BNXT_ULP_CLASS_HID_693ca = 0x693ca,
+ BNXT_ULP_CLASS_HID_69b58 = 0x69b58,
+ BNXT_ULP_CLASS_HID_68e0c = 0x68e0c,
+ BNXT_ULP_CLASS_HID_69638 = 0x69638,
+ BNXT_ULP_CLASS_HID_38d98 = 0x38d98,
+ BNXT_ULP_CLASS_HID_39554 = 0x39554,
+ BNXT_ULP_CLASS_HID_39878 = 0x39878,
+ BNXT_ULP_CLASS_HID_38796 = 0x38796,
+ BNXT_ULP_CLASS_HID_7831c = 0x7831c,
+ BNXT_ULP_CLASS_HID_78aaa = 0x78aaa,
+ BNXT_ULP_CLASS_HID_79dfc = 0x79dfc,
+ BNXT_ULP_CLASS_HID_7850a = 0x7850a,
+ BNXT_ULP_CLASS_HID_03b7 = 0x03b7,
+ BNXT_ULP_CLASS_HID_13f3 = 0x13f3,
+ BNXT_ULP_CLASS_HID_0255 = 0x0255,
+ BNXT_ULP_CLASS_HID_1675 = 0x1675,
+ BNXT_ULP_CLASS_HID_80f52 = 0x80f52,
+ BNXT_ULP_CLASS_HID_819f2 = 0x819f2,
+ BNXT_ULP_CLASS_HID_80542 = 0x80542,
+ BNXT_ULP_CLASS_HID_817e2 = 0x817e2,
+ BNXT_ULP_CLASS_HID_20a98 = 0x20a98,
+ BNXT_ULP_CLASS_HID_20538 = 0x20538,
+ BNXT_ULP_CLASS_HID_6081c = 0x6081c,
+ BNXT_ULP_CLASS_HID_61abc = 0x61abc,
+ BNXT_ULP_CLASS_HID_03a7 = 0x03a7,
+ BNXT_ULP_CLASS_HID_13e3 = 0x13e3,
+ BNXT_ULP_CLASS_HID_1047 = 0x1047,
+ BNXT_ULP_CLASS_HID_0721 = 0x0721,
+ BNXT_ULP_CLASS_HID_19b7 = 0x19b7,
+ BNXT_ULP_CLASS_HID_0911 = 0x0911,
+ BNXT_ULP_CLASS_HID_0df5 = 0x0df5,
+ BNXT_ULP_CLASS_HID_1d31 = 0x1d31,
+ BNXT_ULP_CLASS_HID_0245 = 0x0245,
+ BNXT_ULP_CLASS_HID_1665 = 0x1665,
+ BNXT_ULP_CLASS_HID_8055d = 0x8055d,
+ BNXT_ULP_CLASS_HID_80893 = 0x80893,
+ BNXT_ULP_CLASS_HID_407d9 = 0x407d9,
+ BNXT_ULP_CLASS_HID_40b1f = 0x40b1f,
+ BNXT_ULP_CLASS_HID_c1ad1 = 0xc1ad1,
+ BNXT_ULP_CLASS_HID_c0e17 = 0xc0e17,
+ BNXT_ULP_CLASS_HID_03d7 = 0x03d7,
+ BNXT_ULP_CLASS_HID_1393 = 0x1393,
+ BNXT_ULP_CLASS_HID_1037 = 0x1037,
+ BNXT_ULP_CLASS_HID_0751 = 0x0751,
+ BNXT_ULP_CLASS_HID_19c7 = 0x19c7,
+ BNXT_ULP_CLASS_HID_0961 = 0x0961,
+ BNXT_ULP_CLASS_HID_0d85 = 0x0d85,
+ BNXT_ULP_CLASS_HID_1d41 = 0x1d41,
+ BNXT_ULP_CLASS_HID_0235 = 0x0235,
+ BNXT_ULP_CLASS_HID_1615 = 0x1615,
+ BNXT_ULP_CLASS_HID_8052d = 0x8052d,
+ BNXT_ULP_CLASS_HID_808e3 = 0x808e3,
+ BNXT_ULP_CLASS_HID_407a9 = 0x407a9,
+ BNXT_ULP_CLASS_HID_40b6f = 0x40b6f,
+ BNXT_ULP_CLASS_HID_c1aa1 = 0xc1aa1,
+ BNXT_ULP_CLASS_HID_c0e67 = 0xc0e67,
+ BNXT_ULP_CLASS_HID_80f42 = 0x80f42,
+ BNXT_ULP_CLASS_HID_819e2 = 0x819e2,
+ BNXT_ULP_CLASS_HID_80552 = 0x80552,
+ BNXT_ULP_CLASS_HID_817f2 = 0x817f2,
+ BNXT_ULP_CLASS_HID_c0cce = 0xc0cce,
+ BNXT_ULP_CLASS_HID_c1f6e = 0xc1f6e,
+ BNXT_ULP_CLASS_HID_c1ade = 0xc1ade,
+ BNXT_ULP_CLASS_HID_c157e = 0xc157e,
+ BNXT_ULP_CLASS_HID_a0d8c = 0xa0d8c,
+ BNXT_ULP_CLASS_HID_a182c = 0xa182c,
+ BNXT_ULP_CLASS_HID_a1b9c = 0xa1b9c,
+ BNXT_ULP_CLASS_HID_a163c = 0xa163c,
+ BNXT_ULP_CLASS_HID_e0308 = 0xe0308,
+ BNXT_ULP_CLASS_HID_e1da8 = 0xe1da8,
+ BNXT_ULP_CLASS_HID_e1918 = 0xe1918,
+ BNXT_ULP_CLASS_HID_e0bda = 0xe0bda,
+ BNXT_ULP_CLASS_HID_20a88 = 0x20a88,
+ BNXT_ULP_CLASS_HID_20528 = 0x20528,
+ BNXT_ULP_CLASS_HID_6080c = 0x6080c,
+ BNXT_ULP_CLASS_HID_61aac = 0x61aac,
+ BNXT_ULP_CLASS_HID_31a18 = 0x31a18,
+ BNXT_ULP_CLASS_HID_314b8 = 0x314b8,
+ BNXT_ULP_CLASS_HID_71f9c = 0x71f9c,
+ BNXT_ULP_CLASS_HID_70a5e = 0x70a5e,
+ BNXT_ULP_CLASS_HID_282c0 = 0x282c0,
+ BNXT_ULP_CLASS_HID_29d60 = 0x29d60,
+ BNXT_ULP_CLASS_HID_68044 = 0x68044,
+ BNXT_ULP_CLASS_HID_692e4 = 0x692e4,
+ BNXT_ULP_CLASS_HID_39250 = 0x39250,
+ BNXT_ULP_CLASS_HID_38c12 = 0x38c12,
+ BNXT_ULP_CLASS_HID_797d4 = 0x797d4,
+ BNXT_ULP_CLASS_HID_78196 = 0x78196,
+ BNXT_ULP_CLASS_HID_80f32 = 0x80f32,
+ BNXT_ULP_CLASS_HID_81992 = 0x81992,
+ BNXT_ULP_CLASS_HID_80522 = 0x80522,
+ BNXT_ULP_CLASS_HID_81782 = 0x81782,
+ BNXT_ULP_CLASS_HID_c0cbe = 0xc0cbe,
+ BNXT_ULP_CLASS_HID_c1f1e = 0xc1f1e,
+ BNXT_ULP_CLASS_HID_c1aae = 0xc1aae,
+ BNXT_ULP_CLASS_HID_c150e = 0xc150e,
+ BNXT_ULP_CLASS_HID_a0dfc = 0xa0dfc,
+ BNXT_ULP_CLASS_HID_a185c = 0xa185c,
+ BNXT_ULP_CLASS_HID_a1bec = 0xa1bec,
+ BNXT_ULP_CLASS_HID_a164c = 0xa164c,
+ BNXT_ULP_CLASS_HID_e0378 = 0xe0378,
+ BNXT_ULP_CLASS_HID_e1dd8 = 0xe1dd8,
+ BNXT_ULP_CLASS_HID_e1968 = 0xe1968,
+ BNXT_ULP_CLASS_HID_e0baa = 0xe0baa,
+ BNXT_ULP_CLASS_HID_20af8 = 0x20af8,
+ BNXT_ULP_CLASS_HID_20558 = 0x20558,
+ BNXT_ULP_CLASS_HID_6087c = 0x6087c,
+ BNXT_ULP_CLASS_HID_61adc = 0x61adc,
+ BNXT_ULP_CLASS_HID_31a68 = 0x31a68,
+ BNXT_ULP_CLASS_HID_314c8 = 0x314c8,
+ BNXT_ULP_CLASS_HID_71fec = 0x71fec,
+ BNXT_ULP_CLASS_HID_70a2e = 0x70a2e,
+ BNXT_ULP_CLASS_HID_282b0 = 0x282b0,
+ BNXT_ULP_CLASS_HID_29d10 = 0x29d10,
+ BNXT_ULP_CLASS_HID_68034 = 0x68034,
+ BNXT_ULP_CLASS_HID_69294 = 0x69294,
+ BNXT_ULP_CLASS_HID_39220 = 0x39220,
+ BNXT_ULP_CLASS_HID_38c62 = 0x38c62,
+ BNXT_ULP_CLASS_HID_797a4 = 0x797a4,
+ BNXT_ULP_CLASS_HID_781e6 = 0x781e6,
+ BNXT_ULP_CLASS_HID_0f05 = 0x0f05,
+ BNXT_ULP_CLASS_HID_0f09 = 0x0f09,
+ BNXT_ULP_CLASS_HID_0f06 = 0x0f06,
+ BNXT_ULP_CLASS_HID_19a6 = 0x19a6,
+ BNXT_ULP_CLASS_HID_0f0a = 0x0f0a,
+ BNXT_ULP_CLASS_HID_19aa = 0x19aa,
+ BNXT_ULP_CLASS_HID_0f15 = 0x0f15,
+ BNXT_ULP_CLASS_HID_0f19 = 0x0f19,
+ BNXT_ULP_CLASS_HID_0f65 = 0x0f65,
+ BNXT_ULP_CLASS_HID_0f69 = 0x0f69,
+ BNXT_ULP_CLASS_HID_0f16 = 0x0f16,
+ BNXT_ULP_CLASS_HID_19b6 = 0x19b6,
+ BNXT_ULP_CLASS_HID_0f1a = 0x0f1a,
+ BNXT_ULP_CLASS_HID_19ba = 0x19ba,
+ BNXT_ULP_CLASS_HID_0f66 = 0x0f66,
+ BNXT_ULP_CLASS_HID_19c6 = 0x19c6,
+ BNXT_ULP_CLASS_HID_0f6a = 0x0f6a,
+ BNXT_ULP_CLASS_HID_19ca = 0x19ca
};
enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_0000 = 0x0000,
- BNXT_ULP_ACT_HID_0001 = 0x0001,
- BNXT_ULP_ACT_HID_0400 = 0x0400,
- BNXT_ULP_ACT_HID_01ab = 0x01ab,
+ BNXT_ULP_ACT_HID_0008 = 0x0008,
+ BNXT_ULP_ACT_HID_2000 = 0x2000,
+ BNXT_ULP_ACT_HID_1988 = 0x1988,
+ BNXT_ULP_ACT_HID_0080 = 0x0080,
+ BNXT_ULP_ACT_HID_3988 = 0x3988,
+ BNXT_ULP_ACT_HID_1a08 = 0x1a08,
BNXT_ULP_ACT_HID_0010 = 0x0010,
- BNXT_ULP_ACT_HID_05ab = 0x05ab,
- BNXT_ULP_ACT_HID_01bb = 0x01bb,
- BNXT_ULP_ACT_HID_0002 = 0x0002,
- BNXT_ULP_ACT_HID_0003 = 0x0003,
- BNXT_ULP_ACT_HID_0402 = 0x0402,
- BNXT_ULP_ACT_HID_01ad = 0x01ad,
- BNXT_ULP_ACT_HID_0012 = 0x0012,
- BNXT_ULP_ACT_HID_05ad = 0x05ad,
- BNXT_ULP_ACT_HID_01bd = 0x01bd,
- BNXT_ULP_ACT_HID_0613 = 0x0613,
- BNXT_ULP_ACT_HID_02a9 = 0x02a9,
- BNXT_ULP_ACT_HID_0054 = 0x0054,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
+ BNXT_ULP_ACT_HID_0050 = 0x0050,
+ BNXT_ULP_ACT_HID_0018 = 0x0018,
+ BNXT_ULP_ACT_HID_2010 = 0x2010,
+ BNXT_ULP_ACT_HID_1998 = 0x1998,
+ BNXT_ULP_ACT_HID_0090 = 0x0090,
+ BNXT_ULP_ACT_HID_3998 = 0x3998,
+ BNXT_ULP_ACT_HID_1a18 = 0x1a18,
+ BNXT_ULP_ACT_HID_32ea = 0x32ea,
+ BNXT_ULP_ACT_HID_32f2 = 0x32f2,
+ BNXT_ULP_ACT_HID_52ea = 0x52ea,
+ BNXT_ULP_ACT_HID_4c72 = 0x4c72,
+ BNXT_ULP_ACT_HID_336a = 0x336a,
+ BNXT_ULP_ACT_HID_6c72 = 0x6c72,
+ BNXT_ULP_ACT_HID_4cf2 = 0x4cf2,
+ BNXT_ULP_ACT_HID_32fa = 0x32fa,
+ BNXT_ULP_ACT_HID_3302 = 0x3302,
+ BNXT_ULP_ACT_HID_52fa = 0x52fa,
+ BNXT_ULP_ACT_HID_4c82 = 0x4c82,
+ BNXT_ULP_ACT_HID_337a = 0x337a,
+ BNXT_ULP_ACT_HID_6c82 = 0x6c82,
+ BNXT_ULP_ACT_HID_4d02 = 0x4d02,
+ BNXT_ULP_ACT_HID_0808 = 0x0808,
+ BNXT_ULP_ACT_HID_1008 = 0x1008,
+ BNXT_ULP_ACT_HID_1808 = 0x1808,
+ BNXT_ULP_ACT_HID_0818 = 0x0818,
+ BNXT_ULP_ACT_HID_1018 = 0x1018,
+ BNXT_ULP_ACT_HID_1818 = 0x1818,
+ BNXT_ULP_ACT_HID_0880 = 0x0880,
+ BNXT_ULP_ACT_HID_1080 = 0x1080,
+ BNXT_ULP_ACT_HID_1880 = 0x1880,
+ BNXT_ULP_ACT_HID_0890 = 0x0890,
+ BNXT_ULP_ACT_HID_1090 = 0x1090,
+ BNXT_ULP_ACT_HID_1890 = 0x1890,
+ BNXT_ULP_ACT_HID_3af2 = 0x3af2,
+ BNXT_ULP_ACT_HID_42f2 = 0x42f2,
+ BNXT_ULP_ACT_HID_4af2 = 0x4af2,
+ BNXT_ULP_ACT_HID_3b02 = 0x3b02,
+ BNXT_ULP_ACT_HID_4302 = 0x4302,
+ BNXT_ULP_ACT_HID_4b02 = 0x4b02,
+ BNXT_ULP_ACT_HID_3b6a = 0x3b6a,
+ BNXT_ULP_ACT_HID_436a = 0x436a,
+ BNXT_ULP_ACT_HID_4b6a = 0x4b6a,
+ BNXT_ULP_ACT_HID_3b7a = 0x3b7a,
+ BNXT_ULP_ACT_HID_437a = 0x437a,
+ BNXT_ULP_ACT_HID_4b7a = 0x4b7a,
+ BNXT_ULP_ACT_HID_640d = 0x640d,
+ BNXT_ULP_ACT_HID_641d = 0x641d,
+ BNXT_ULP_ACT_HID_071a = 0x071a,
+ BNXT_ULP_ACT_HID_0800 = 0x0800,
+ BNXT_ULP_ACT_HID_1000 = 0x1000,
+ BNXT_ULP_ACT_HID_1800 = 0x1800,
+ BNXT_ULP_ACT_HID_0810 = 0x0810,
+ BNXT_ULP_ACT_HID_1010 = 0x1010,
+ BNXT_ULP_ACT_HID_1810 = 0x1810,
+ BNXT_ULP_ACT_HID_1110 = 0x1110,
+ BNXT_ULP_ACT_HID_4420 = 0x4420,
+ BNXT_ULP_ACT_HID_2220 = 0x2220,
+ BNXT_ULP_ACT_HID_0c84 = 0x0c84,
+ BNXT_ULP_ACT_HID_3f94 = 0x3f94,
+ BNXT_ULP_ACT_HID_3330 = 0x3330,
+ BNXT_ULP_ACT_HID_50a4 = 0x50a4,
+ BNXT_ULP_ACT_HID_1910 = 0x1910,
+ BNXT_ULP_ACT_HID_4c20 = 0x4c20,
+ BNXT_ULP_ACT_HID_2a20 = 0x2a20,
+ BNXT_ULP_ACT_HID_1484 = 0x1484,
+ BNXT_ULP_ACT_HID_4794 = 0x4794,
+ BNXT_ULP_ACT_HID_3b30 = 0x3b30,
+ BNXT_ULP_ACT_HID_58a4 = 0x58a4,
+ BNXT_ULP_ACT_HID_2110 = 0x2110,
+ BNXT_ULP_ACT_HID_5420 = 0x5420,
+ BNXT_ULP_ACT_HID_3220 = 0x3220,
+ BNXT_ULP_ACT_HID_1c84 = 0x1c84,
+ BNXT_ULP_ACT_HID_4f94 = 0x4f94,
+ BNXT_ULP_ACT_HID_4330 = 0x4330,
+ BNXT_ULP_ACT_HID_60a4 = 0x60a4,
+ BNXT_ULP_ACT_HID_2910 = 0x2910,
+ BNXT_ULP_ACT_HID_5c20 = 0x5c20,
+ BNXT_ULP_ACT_HID_3a20 = 0x3a20,
+ BNXT_ULP_ACT_HID_2484 = 0x2484,
+ BNXT_ULP_ACT_HID_5794 = 0x5794,
+ BNXT_ULP_ACT_HID_4b30 = 0x4b30,
+ BNXT_ULP_ACT_HID_68a4 = 0x68a4,
+ BNXT_ULP_ACT_HID_1120 = 0x1120,
+ BNXT_ULP_ACT_HID_4430 = 0x4430,
+ BNXT_ULP_ACT_HID_2230 = 0x2230,
+ BNXT_ULP_ACT_HID_0c94 = 0x0c94,
+ BNXT_ULP_ACT_HID_3fa4 = 0x3fa4,
+ BNXT_ULP_ACT_HID_3340 = 0x3340,
+ BNXT_ULP_ACT_HID_50b4 = 0x50b4,
+ BNXT_ULP_ACT_HID_1920 = 0x1920,
+ BNXT_ULP_ACT_HID_4c30 = 0x4c30,
+ BNXT_ULP_ACT_HID_2a30 = 0x2a30,
+ BNXT_ULP_ACT_HID_1494 = 0x1494,
+ BNXT_ULP_ACT_HID_47a4 = 0x47a4,
+ BNXT_ULP_ACT_HID_3b40 = 0x3b40,
+ BNXT_ULP_ACT_HID_58b4 = 0x58b4,
+ BNXT_ULP_ACT_HID_2120 = 0x2120,
+ BNXT_ULP_ACT_HID_5430 = 0x5430,
+ BNXT_ULP_ACT_HID_3230 = 0x3230,
+ BNXT_ULP_ACT_HID_1c94 = 0x1c94,
+ BNXT_ULP_ACT_HID_4fa4 = 0x4fa4,
+ BNXT_ULP_ACT_HID_4340 = 0x4340,
+ BNXT_ULP_ACT_HID_60b4 = 0x60b4,
+ BNXT_ULP_ACT_HID_2920 = 0x2920,
+ BNXT_ULP_ACT_HID_5c30 = 0x5c30,
+ BNXT_ULP_ACT_HID_3a30 = 0x3a30,
+ BNXT_ULP_ACT_HID_2494 = 0x2494,
+ BNXT_ULP_ACT_HID_57a4 = 0x57a4,
+ BNXT_ULP_ACT_HID_4b40 = 0x4b40,
+ BNXT_ULP_ACT_HID_68b4 = 0x68b4,
+ BNXT_ULP_ACT_HID_2a98 = 0x2a98,
+ BNXT_ULP_ACT_HID_5da8 = 0x5da8,
+ BNXT_ULP_ACT_HID_3ba8 = 0x3ba8,
+ BNXT_ULP_ACT_HID_260c = 0x260c,
+ BNXT_ULP_ACT_HID_591c = 0x591c,
+ BNXT_ULP_ACT_HID_6a2c = 0x6a2c,
+ BNXT_ULP_ACT_HID_2aa8 = 0x2aa8,
+ BNXT_ULP_ACT_HID_5db8 = 0x5db8,
+ BNXT_ULP_ACT_HID_3bb8 = 0x3bb8,
+ BNXT_ULP_ACT_HID_261c = 0x261c,
+ BNXT_ULP_ACT_HID_592c = 0x592c,
+ BNXT_ULP_ACT_HID_6a3c = 0x6a3c,
+ BNXT_ULP_ACT_HID_3298 = 0x3298,
+ BNXT_ULP_ACT_HID_65a8 = 0x65a8,
+ BNXT_ULP_ACT_HID_43a8 = 0x43a8,
+ BNXT_ULP_ACT_HID_2e0c = 0x2e0c,
+ BNXT_ULP_ACT_HID_611c = 0x611c,
+ BNXT_ULP_ACT_HID_722c = 0x722c,
+ BNXT_ULP_ACT_HID_32a8 = 0x32a8,
+ BNXT_ULP_ACT_HID_65b8 = 0x65b8,
+ BNXT_ULP_ACT_HID_43b8 = 0x43b8,
+ BNXT_ULP_ACT_HID_2e1c = 0x2e1c,
+ BNXT_ULP_ACT_HID_612c = 0x612c,
+ BNXT_ULP_ACT_HID_723c = 0x723c,
+ BNXT_ULP_ACT_HID_3a98 = 0x3a98,
+ BNXT_ULP_ACT_HID_6da8 = 0x6da8,
+ BNXT_ULP_ACT_HID_4ba8 = 0x4ba8,
+ BNXT_ULP_ACT_HID_360c = 0x360c,
+ BNXT_ULP_ACT_HID_691c = 0x691c,
+ BNXT_ULP_ACT_HID_7a2c = 0x7a2c,
+ BNXT_ULP_ACT_HID_3aa8 = 0x3aa8,
+ BNXT_ULP_ACT_HID_6db8 = 0x6db8,
+ BNXT_ULP_ACT_HID_4bb8 = 0x4bb8,
+ BNXT_ULP_ACT_HID_361c = 0x361c,
+ BNXT_ULP_ACT_HID_692c = 0x692c,
+ BNXT_ULP_ACT_HID_7a3c = 0x7a3c,
+ BNXT_ULP_ACT_HID_4298 = 0x4298,
+ BNXT_ULP_ACT_HID_75a8 = 0x75a8,
+ BNXT_ULP_ACT_HID_53a8 = 0x53a8,
+ BNXT_ULP_ACT_HID_3e0c = 0x3e0c,
+ BNXT_ULP_ACT_HID_711c = 0x711c,
+ BNXT_ULP_ACT_HID_0670 = 0x0670,
+ BNXT_ULP_ACT_HID_42a8 = 0x42a8,
+ BNXT_ULP_ACT_HID_75b8 = 0x75b8,
+ BNXT_ULP_ACT_HID_53b8 = 0x53b8,
+ BNXT_ULP_ACT_HID_3e1c = 0x3e1c,
+ BNXT_ULP_ACT_HID_712c = 0x712c,
+ BNXT_ULP_ACT_HID_0680 = 0x0680,
+ BNXT_ULP_ACT_HID_3aea = 0x3aea,
+ BNXT_ULP_ACT_HID_42ea = 0x42ea,
+ BNXT_ULP_ACT_HID_4aea = 0x4aea,
+ BNXT_ULP_ACT_HID_3afa = 0x3afa,
+ BNXT_ULP_ACT_HID_42fa = 0x42fa,
+ BNXT_ULP_ACT_HID_4afa = 0x4afa,
+ BNXT_ULP_ACT_HID_43fa = 0x43fa,
+ BNXT_ULP_ACT_HID_770a = 0x770a,
+ BNXT_ULP_ACT_HID_550a = 0x550a,
+ BNXT_ULP_ACT_HID_3f6e = 0x3f6e,
+ BNXT_ULP_ACT_HID_727e = 0x727e,
+ BNXT_ULP_ACT_HID_661a = 0x661a,
+ BNXT_ULP_ACT_HID_07d2 = 0x07d2,
+ BNXT_ULP_ACT_HID_4bfa = 0x4bfa,
+ BNXT_ULP_ACT_HID_034e = 0x034e,
+ BNXT_ULP_ACT_HID_5d0a = 0x5d0a,
+ BNXT_ULP_ACT_HID_476e = 0x476e,
+ BNXT_ULP_ACT_HID_7a7e = 0x7a7e,
+ BNXT_ULP_ACT_HID_6e1a = 0x6e1a,
+ BNXT_ULP_ACT_HID_0fd2 = 0x0fd2,
+ BNXT_ULP_ACT_HID_53fa = 0x53fa,
+ BNXT_ULP_ACT_HID_0b4e = 0x0b4e,
+ BNXT_ULP_ACT_HID_650a = 0x650a,
+ BNXT_ULP_ACT_HID_4f6e = 0x4f6e,
+ BNXT_ULP_ACT_HID_06c2 = 0x06c2,
+ BNXT_ULP_ACT_HID_761a = 0x761a,
+ BNXT_ULP_ACT_HID_17d2 = 0x17d2,
+ BNXT_ULP_ACT_HID_5bfa = 0x5bfa,
+ BNXT_ULP_ACT_HID_134e = 0x134e,
+ BNXT_ULP_ACT_HID_6d0a = 0x6d0a,
+ BNXT_ULP_ACT_HID_576e = 0x576e,
+ BNXT_ULP_ACT_HID_0ec2 = 0x0ec2,
+ BNXT_ULP_ACT_HID_025e = 0x025e,
+ BNXT_ULP_ACT_HID_1fd2 = 0x1fd2,
+ BNXT_ULP_ACT_HID_440a = 0x440a,
+ BNXT_ULP_ACT_HID_771a = 0x771a,
+ BNXT_ULP_ACT_HID_551a = 0x551a,
+ BNXT_ULP_ACT_HID_3f7e = 0x3f7e,
+ BNXT_ULP_ACT_HID_728e = 0x728e,
+ BNXT_ULP_ACT_HID_662a = 0x662a,
+ BNXT_ULP_ACT_HID_07e2 = 0x07e2,
+ BNXT_ULP_ACT_HID_4c0a = 0x4c0a,
+ BNXT_ULP_ACT_HID_035e = 0x035e,
+ BNXT_ULP_ACT_HID_5d1a = 0x5d1a,
+ BNXT_ULP_ACT_HID_477e = 0x477e,
+ BNXT_ULP_ACT_HID_7a8e = 0x7a8e,
+ BNXT_ULP_ACT_HID_6e2a = 0x6e2a,
+ BNXT_ULP_ACT_HID_0fe2 = 0x0fe2,
+ BNXT_ULP_ACT_HID_540a = 0x540a,
+ BNXT_ULP_ACT_HID_0b5e = 0x0b5e,
+ BNXT_ULP_ACT_HID_651a = 0x651a,
+ BNXT_ULP_ACT_HID_4f7e = 0x4f7e,
+ BNXT_ULP_ACT_HID_06d2 = 0x06d2,
+ BNXT_ULP_ACT_HID_762a = 0x762a,
+ BNXT_ULP_ACT_HID_17e2 = 0x17e2,
+ BNXT_ULP_ACT_HID_5c0a = 0x5c0a,
+ BNXT_ULP_ACT_HID_135e = 0x135e,
+ BNXT_ULP_ACT_HID_6d1a = 0x6d1a,
+ BNXT_ULP_ACT_HID_577e = 0x577e,
+ BNXT_ULP_ACT_HID_0ed2 = 0x0ed2,
+ BNXT_ULP_ACT_HID_026e = 0x026e,
+ BNXT_ULP_ACT_HID_1fe2 = 0x1fe2,
+ BNXT_ULP_ACT_HID_5d82 = 0x5d82,
+ BNXT_ULP_ACT_HID_14d6 = 0x14d6,
+ BNXT_ULP_ACT_HID_6e92 = 0x6e92,
+ BNXT_ULP_ACT_HID_58f6 = 0x58f6,
+ BNXT_ULP_ACT_HID_104a = 0x104a,
+ BNXT_ULP_ACT_HID_215a = 0x215a,
+ BNXT_ULP_ACT_HID_5d92 = 0x5d92,
+ BNXT_ULP_ACT_HID_14e6 = 0x14e6,
+ BNXT_ULP_ACT_HID_6ea2 = 0x6ea2,
+ BNXT_ULP_ACT_HID_5906 = 0x5906,
+ BNXT_ULP_ACT_HID_105a = 0x105a,
+ BNXT_ULP_ACT_HID_216a = 0x216a,
+ BNXT_ULP_ACT_HID_6582 = 0x6582,
+ BNXT_ULP_ACT_HID_1cd6 = 0x1cd6,
+ BNXT_ULP_ACT_HID_7692 = 0x7692,
+ BNXT_ULP_ACT_HID_60f6 = 0x60f6,
+ BNXT_ULP_ACT_HID_184a = 0x184a,
+ BNXT_ULP_ACT_HID_295a = 0x295a,
+ BNXT_ULP_ACT_HID_6592 = 0x6592,
+ BNXT_ULP_ACT_HID_1ce6 = 0x1ce6,
+ BNXT_ULP_ACT_HID_76a2 = 0x76a2,
+ BNXT_ULP_ACT_HID_6106 = 0x6106,
+ BNXT_ULP_ACT_HID_185a = 0x185a,
+ BNXT_ULP_ACT_HID_296a = 0x296a,
+ BNXT_ULP_ACT_HID_6d82 = 0x6d82,
+ BNXT_ULP_ACT_HID_24d6 = 0x24d6,
+ BNXT_ULP_ACT_HID_02d6 = 0x02d6,
+ BNXT_ULP_ACT_HID_68f6 = 0x68f6,
+ BNXT_ULP_ACT_HID_204a = 0x204a,
+ BNXT_ULP_ACT_HID_315a = 0x315a,
+ BNXT_ULP_ACT_HID_6d92 = 0x6d92,
+ BNXT_ULP_ACT_HID_24e6 = 0x24e6,
+ BNXT_ULP_ACT_HID_02e6 = 0x02e6,
+ BNXT_ULP_ACT_HID_6906 = 0x6906,
+ BNXT_ULP_ACT_HID_205a = 0x205a,
+ BNXT_ULP_ACT_HID_316a = 0x316a,
+ BNXT_ULP_ACT_HID_7582 = 0x7582,
+ BNXT_ULP_ACT_HID_2cd6 = 0x2cd6,
+ BNXT_ULP_ACT_HID_0ad6 = 0x0ad6,
+ BNXT_ULP_ACT_HID_70f6 = 0x70f6,
+ BNXT_ULP_ACT_HID_284a = 0x284a,
+ BNXT_ULP_ACT_HID_395a = 0x395a,
+ BNXT_ULP_ACT_HID_7592 = 0x7592,
+ BNXT_ULP_ACT_HID_2ce6 = 0x2ce6,
+ BNXT_ULP_ACT_HID_0ae6 = 0x0ae6,
+ BNXT_ULP_ACT_HID_7106 = 0x7106,
+ BNXT_ULP_ACT_HID_285a = 0x285a,
+ BNXT_ULP_ACT_HID_396a = 0x396a,
+ BNXT_ULP_ACT_HID_0020 = 0x0020,
+ BNXT_ULP_ACT_HID_0030 = 0x0030,
+ BNXT_ULP_ACT_HID_65d4 = 0x65d4,
+ BNXT_ULP_ACT_HID_65e4 = 0x65e4,
+ BNXT_ULP_ACT_HID_330a = 0x330a,
+ BNXT_ULP_ACT_HID_331a = 0x331a,
+ BNXT_ULP_ACT_HID_1cfe = 0x1cfe,
+ BNXT_ULP_ACT_HID_1d0e = 0x1d0e,
+ BNXT_ULP_ACT_HID_1474 = 0x1474,
+ BNXT_ULP_ACT_HID_4838 = 0x4838,
+ BNXT_ULP_ACT_HID_6458 = 0x6458,
+ BNXT_ULP_ACT_HID_1c68 = 0x1c68,
+ BNXT_ULP_ACT_HID_6c34 = 0x6c34,
+ BNXT_ULP_ACT_HID_5d08 = 0x5d08,
+ BNXT_ULP_ACT_HID_5d10 = 0x5d10,
+ BNXT_ULP_ACT_HID_5d20 = 0x5d20,
+ BNXT_ULP_ACT_HID_2e18 = 0x2e18,
+ BNXT_ULP_ACT_HID_29d4 = 0x29d4,
+ BNXT_ULP_ACT_HID_7690 = 0x7690,
+ BNXT_ULP_ACT_HID_47a0 = 0x47a0,
+ BNXT_ULP_ACT_HID_435c = 0x435c,
+ BNXT_ULP_ACT_HID_5d18 = 0x5d18,
+ BNXT_ULP_ACT_HID_2e28 = 0x2e28,
+ BNXT_ULP_ACT_HID_29e4 = 0x29e4,
+ BNXT_ULP_ACT_HID_76a0 = 0x76a0,
+ BNXT_ULP_ACT_HID_47b0 = 0x47b0,
+ BNXT_ULP_ACT_HID_436c = 0x436c,
+ BNXT_ULP_ACT_HID_1436 = 0x1436,
+ BNXT_ULP_ACT_HID_143e = 0x143e,
+ BNXT_ULP_ACT_HID_144e = 0x144e,
+ BNXT_ULP_ACT_HID_6102 = 0x6102,
+ BNXT_ULP_ACT_HID_5cbe = 0x5cbe,
+ BNXT_ULP_ACT_HID_2dbe = 0x2dbe,
+ BNXT_ULP_ACT_HID_7a8a = 0x7a8a,
+ BNXT_ULP_ACT_HID_7646 = 0x7646,
+ BNXT_ULP_ACT_HID_1446 = 0x1446,
+ BNXT_ULP_ACT_HID_6112 = 0x6112,
+ BNXT_ULP_ACT_HID_5cce = 0x5cce,
+ BNXT_ULP_ACT_HID_2dce = 0x2dce,
+ BNXT_ULP_ACT_HID_7a9a = 0x7a9a,
+ BNXT_ULP_ACT_HID_7656 = 0x7656,
+ BNXT_ULP_ACT_HID_6508 = 0x6508,
+ BNXT_ULP_ACT_HID_6d08 = 0x6d08,
+ BNXT_ULP_ACT_HID_7508 = 0x7508,
+ BNXT_ULP_ACT_HID_6518 = 0x6518,
+ BNXT_ULP_ACT_HID_6d18 = 0x6d18,
+ BNXT_ULP_ACT_HID_7518 = 0x7518,
+ BNXT_ULP_ACT_HID_6e18 = 0x6e18,
+ BNXT_ULP_ACT_HID_256c = 0x256c,
+ BNXT_ULP_ACT_HID_036c = 0x036c,
+ BNXT_ULP_ACT_HID_698c = 0x698c,
+ BNXT_ULP_ACT_HID_20e0 = 0x20e0,
+ BNXT_ULP_ACT_HID_31f0 = 0x31f0,
+ BNXT_ULP_ACT_HID_7618 = 0x7618,
+ BNXT_ULP_ACT_HID_2d6c = 0x2d6c,
+ BNXT_ULP_ACT_HID_0b6c = 0x0b6c,
+ BNXT_ULP_ACT_HID_718c = 0x718c,
+ BNXT_ULP_ACT_HID_28e0 = 0x28e0,
+ BNXT_ULP_ACT_HID_39f0 = 0x39f0,
+ BNXT_ULP_ACT_HID_025c = 0x025c,
+ BNXT_ULP_ACT_HID_356c = 0x356c,
+ BNXT_ULP_ACT_HID_136c = 0x136c,
+ BNXT_ULP_ACT_HID_798c = 0x798c,
+ BNXT_ULP_ACT_HID_30e0 = 0x30e0,
+ BNXT_ULP_ACT_HID_41f0 = 0x41f0,
+ BNXT_ULP_ACT_HID_0a5c = 0x0a5c,
+ BNXT_ULP_ACT_HID_3d6c = 0x3d6c,
+ BNXT_ULP_ACT_HID_1b6c = 0x1b6c,
+ BNXT_ULP_ACT_HID_05d0 = 0x05d0,
+ BNXT_ULP_ACT_HID_38e0 = 0x38e0,
+ BNXT_ULP_ACT_HID_49f0 = 0x49f0,
+ BNXT_ULP_ACT_HID_6e28 = 0x6e28,
+ BNXT_ULP_ACT_HID_257c = 0x257c,
+ BNXT_ULP_ACT_HID_037c = 0x037c,
+ BNXT_ULP_ACT_HID_699c = 0x699c,
+ BNXT_ULP_ACT_HID_20f0 = 0x20f0,
+ BNXT_ULP_ACT_HID_3200 = 0x3200,
+ BNXT_ULP_ACT_HID_7628 = 0x7628,
+ BNXT_ULP_ACT_HID_2d7c = 0x2d7c,
+ BNXT_ULP_ACT_HID_0b7c = 0x0b7c,
+ BNXT_ULP_ACT_HID_719c = 0x719c,
+ BNXT_ULP_ACT_HID_28f0 = 0x28f0,
+ BNXT_ULP_ACT_HID_3a00 = 0x3a00,
+ BNXT_ULP_ACT_HID_026c = 0x026c,
+ BNXT_ULP_ACT_HID_357c = 0x357c,
+ BNXT_ULP_ACT_HID_137c = 0x137c,
+ BNXT_ULP_ACT_HID_799c = 0x799c,
+ BNXT_ULP_ACT_HID_30f0 = 0x30f0,
+ BNXT_ULP_ACT_HID_4200 = 0x4200,
+ BNXT_ULP_ACT_HID_0a6c = 0x0a6c,
+ BNXT_ULP_ACT_HID_3d7c = 0x3d7c,
+ BNXT_ULP_ACT_HID_1b7c = 0x1b7c,
+ BNXT_ULP_ACT_HID_05e0 = 0x05e0,
+ BNXT_ULP_ACT_HID_38f0 = 0x38f0,
+ BNXT_ULP_ACT_HID_4a00 = 0x4a00,
+ BNXT_ULP_ACT_HID_0be4 = 0x0be4,
+ BNXT_ULP_ACT_HID_3ef4 = 0x3ef4,
+ BNXT_ULP_ACT_HID_1cf4 = 0x1cf4,
+ BNXT_ULP_ACT_HID_0758 = 0x0758,
+ BNXT_ULP_ACT_HID_3a68 = 0x3a68,
+ BNXT_ULP_ACT_HID_4b78 = 0x4b78,
+ BNXT_ULP_ACT_HID_0bf4 = 0x0bf4,
+ BNXT_ULP_ACT_HID_3f04 = 0x3f04,
+ BNXT_ULP_ACT_HID_1d04 = 0x1d04,
+ BNXT_ULP_ACT_HID_0768 = 0x0768,
+ BNXT_ULP_ACT_HID_3a78 = 0x3a78,
+ BNXT_ULP_ACT_HID_4b88 = 0x4b88,
+ BNXT_ULP_ACT_HID_46f4 = 0x46f4,
+ BNXT_ULP_ACT_HID_24f4 = 0x24f4,
+ BNXT_ULP_ACT_HID_0f58 = 0x0f58,
+ BNXT_ULP_ACT_HID_13e4 = 0x13e4,
+ BNXT_ULP_ACT_HID_4268 = 0x4268,
+ BNXT_ULP_ACT_HID_5378 = 0x5378,
+ BNXT_ULP_ACT_HID_13f4 = 0x13f4,
+ BNXT_ULP_ACT_HID_4704 = 0x4704,
+ BNXT_ULP_ACT_HID_2504 = 0x2504,
+ BNXT_ULP_ACT_HID_0f68 = 0x0f68,
+ BNXT_ULP_ACT_HID_4278 = 0x4278,
+ BNXT_ULP_ACT_HID_5388 = 0x5388,
+ BNXT_ULP_ACT_HID_1be4 = 0x1be4,
+ BNXT_ULP_ACT_HID_4ef4 = 0x4ef4,
+ BNXT_ULP_ACT_HID_2cf4 = 0x2cf4,
+ BNXT_ULP_ACT_HID_1758 = 0x1758,
+ BNXT_ULP_ACT_HID_4a68 = 0x4a68,
+ BNXT_ULP_ACT_HID_5b78 = 0x5b78,
+ BNXT_ULP_ACT_HID_1bf4 = 0x1bf4,
+ BNXT_ULP_ACT_HID_4f04 = 0x4f04,
+ BNXT_ULP_ACT_HID_2d04 = 0x2d04,
+ BNXT_ULP_ACT_HID_1768 = 0x1768,
+ BNXT_ULP_ACT_HID_4a78 = 0x4a78,
+ BNXT_ULP_ACT_HID_5b88 = 0x5b88,
+ BNXT_ULP_ACT_HID_23e4 = 0x23e4,
+ BNXT_ULP_ACT_HID_56f4 = 0x56f4,
+ BNXT_ULP_ACT_HID_34f4 = 0x34f4,
+ BNXT_ULP_ACT_HID_1f58 = 0x1f58,
+ BNXT_ULP_ACT_HID_5268 = 0x5268,
+ BNXT_ULP_ACT_HID_6378 = 0x6378,
+ BNXT_ULP_ACT_HID_23f4 = 0x23f4,
+ BNXT_ULP_ACT_HID_5704 = 0x5704,
+ BNXT_ULP_ACT_HID_3504 = 0x3504,
+ BNXT_ULP_ACT_HID_1f68 = 0x1f68,
+ BNXT_ULP_ACT_HID_5278 = 0x5278,
+ BNXT_ULP_ACT_HID_6388 = 0x6388,
+ BNXT_ULP_ACT_HID_1c36 = 0x1c36,
+ BNXT_ULP_ACT_HID_2436 = 0x2436,
+ BNXT_ULP_ACT_HID_2c36 = 0x2c36,
+ BNXT_ULP_ACT_HID_1c46 = 0x1c46,
+ BNXT_ULP_ACT_HID_2446 = 0x2446,
+ BNXT_ULP_ACT_HID_2c46 = 0x2c46,
+ BNXT_ULP_ACT_HID_2546 = 0x2546,
+ BNXT_ULP_ACT_HID_5856 = 0x5856,
+ BNXT_ULP_ACT_HID_3656 = 0x3656,
+ BNXT_ULP_ACT_HID_20ba = 0x20ba,
+ BNXT_ULP_ACT_HID_53ca = 0x53ca,
+ BNXT_ULP_ACT_HID_64da = 0x64da,
+ BNXT_ULP_ACT_HID_2d46 = 0x2d46,
+ BNXT_ULP_ACT_HID_6056 = 0x6056,
+ BNXT_ULP_ACT_HID_3e56 = 0x3e56,
+ BNXT_ULP_ACT_HID_28ba = 0x28ba,
+ BNXT_ULP_ACT_HID_5bca = 0x5bca,
+ BNXT_ULP_ACT_HID_6cda = 0x6cda,
+ BNXT_ULP_ACT_HID_3546 = 0x3546,
+ BNXT_ULP_ACT_HID_6856 = 0x6856,
+ BNXT_ULP_ACT_HID_4656 = 0x4656,
+ BNXT_ULP_ACT_HID_30ba = 0x30ba,
+ BNXT_ULP_ACT_HID_63ca = 0x63ca,
+ BNXT_ULP_ACT_HID_74da = 0x74da,
+ BNXT_ULP_ACT_HID_3d46 = 0x3d46,
+ BNXT_ULP_ACT_HID_7056 = 0x7056,
+ BNXT_ULP_ACT_HID_4e56 = 0x4e56,
+ BNXT_ULP_ACT_HID_38ba = 0x38ba,
+ BNXT_ULP_ACT_HID_6bca = 0x6bca,
+ BNXT_ULP_ACT_HID_011e = 0x011e,
+ BNXT_ULP_ACT_HID_2556 = 0x2556,
+ BNXT_ULP_ACT_HID_5866 = 0x5866,
+ BNXT_ULP_ACT_HID_3666 = 0x3666,
+ BNXT_ULP_ACT_HID_20ca = 0x20ca,
+ BNXT_ULP_ACT_HID_53da = 0x53da,
+ BNXT_ULP_ACT_HID_64ea = 0x64ea,
+ BNXT_ULP_ACT_HID_2d56 = 0x2d56,
+ BNXT_ULP_ACT_HID_6066 = 0x6066,
+ BNXT_ULP_ACT_HID_3e66 = 0x3e66,
+ BNXT_ULP_ACT_HID_28ca = 0x28ca,
+ BNXT_ULP_ACT_HID_5bda = 0x5bda,
+ BNXT_ULP_ACT_HID_6cea = 0x6cea,
+ BNXT_ULP_ACT_HID_3556 = 0x3556,
+ BNXT_ULP_ACT_HID_6866 = 0x6866,
+ BNXT_ULP_ACT_HID_4666 = 0x4666,
+ BNXT_ULP_ACT_HID_30ca = 0x30ca,
+ BNXT_ULP_ACT_HID_63da = 0x63da,
+ BNXT_ULP_ACT_HID_74ea = 0x74ea,
+ BNXT_ULP_ACT_HID_3d56 = 0x3d56,
+ BNXT_ULP_ACT_HID_7066 = 0x7066,
+ BNXT_ULP_ACT_HID_4e66 = 0x4e66,
+ BNXT_ULP_ACT_HID_38ca = 0x38ca,
+ BNXT_ULP_ACT_HID_6bda = 0x6bda,
+ BNXT_ULP_ACT_HID_012e = 0x012e,
+ BNXT_ULP_ACT_HID_3ece = 0x3ece,
+ BNXT_ULP_ACT_HID_71de = 0x71de,
+ BNXT_ULP_ACT_HID_4fde = 0x4fde,
+ BNXT_ULP_ACT_HID_3a42 = 0x3a42,
+ BNXT_ULP_ACT_HID_6d52 = 0x6d52,
+ BNXT_ULP_ACT_HID_02a6 = 0x02a6,
+ BNXT_ULP_ACT_HID_3ede = 0x3ede,
+ BNXT_ULP_ACT_HID_71ee = 0x71ee,
+ BNXT_ULP_ACT_HID_4fee = 0x4fee,
+ BNXT_ULP_ACT_HID_3a52 = 0x3a52,
+ BNXT_ULP_ACT_HID_6d62 = 0x6d62,
+ BNXT_ULP_ACT_HID_02b6 = 0x02b6,
+ BNXT_ULP_ACT_HID_79de = 0x79de,
+ BNXT_ULP_ACT_HID_57de = 0x57de,
+ BNXT_ULP_ACT_HID_4242 = 0x4242,
+ BNXT_ULP_ACT_HID_46ce = 0x46ce,
+ BNXT_ULP_ACT_HID_7552 = 0x7552,
+ BNXT_ULP_ACT_HID_0aa6 = 0x0aa6,
+ BNXT_ULP_ACT_HID_46de = 0x46de,
+ BNXT_ULP_ACT_HID_79ee = 0x79ee,
+ BNXT_ULP_ACT_HID_57ee = 0x57ee,
+ BNXT_ULP_ACT_HID_4252 = 0x4252,
+ BNXT_ULP_ACT_HID_7562 = 0x7562,
+ BNXT_ULP_ACT_HID_0ab6 = 0x0ab6,
+ BNXT_ULP_ACT_HID_4ece = 0x4ece,
BNXT_ULP_ACT_HID_0622 = 0x0622,
- BNXT_ULP_ACT_HID_0454 = 0x0454,
- BNXT_ULP_ACT_HID_0064 = 0x0064,
- BNXT_ULP_ACT_HID_0614 = 0x0614,
- BNXT_ULP_ACT_HID_0615 = 0x0615,
- BNXT_ULP_ACT_HID_02ab = 0x02ab,
- BNXT_ULP_ACT_HID_0056 = 0x0056,
- BNXT_ULP_ACT_HID_0624 = 0x0624,
- BNXT_ULP_ACT_HID_0456 = 0x0456,
- BNXT_ULP_ACT_HID_0066 = 0x0066,
- BNXT_ULP_ACT_HID_048d = 0x048d,
- BNXT_ULP_ACT_HID_048f = 0x048f,
- BNXT_ULP_ACT_HID_04bc = 0x04bc,
- BNXT_ULP_ACT_HID_00a9 = 0x00a9,
- BNXT_ULP_ACT_HID_020f = 0x020f,
- BNXT_ULP_ACT_HID_0153 = 0x0153,
- BNXT_ULP_ACT_HID_04a9 = 0x04a9,
- BNXT_ULP_ACT_HID_01fc = 0x01fc,
- BNXT_ULP_ACT_HID_04be = 0x04be,
- BNXT_ULP_ACT_HID_00ab = 0x00ab,
- BNXT_ULP_ACT_HID_0211 = 0x0211,
- BNXT_ULP_ACT_HID_0155 = 0x0155,
- BNXT_ULP_ACT_HID_04ab = 0x04ab,
- BNXT_ULP_ACT_HID_01fe = 0x01fe,
- BNXT_ULP_ACT_HID_0667 = 0x0667,
- BNXT_ULP_ACT_HID_0254 = 0x0254,
- BNXT_ULP_ACT_HID_03ba = 0x03ba,
- BNXT_ULP_ACT_HID_02fe = 0x02fe,
- BNXT_ULP_ACT_HID_0654 = 0x0654,
- BNXT_ULP_ACT_HID_03a7 = 0x03a7,
- BNXT_ULP_ACT_HID_0669 = 0x0669,
- BNXT_ULP_ACT_HID_0256 = 0x0256,
- BNXT_ULP_ACT_HID_03bc = 0x03bc,
- BNXT_ULP_ACT_HID_0300 = 0x0300,
- BNXT_ULP_ACT_HID_0656 = 0x0656,
- BNXT_ULP_ACT_HID_03a9 = 0x03a9,
- BNXT_ULP_ACT_HID_021b = 0x021b,
- BNXT_ULP_ACT_HID_021c = 0x021c,
- BNXT_ULP_ACT_HID_021e = 0x021e,
- BNXT_ULP_ACT_HID_063f = 0x063f,
- BNXT_ULP_ACT_HID_0510 = 0x0510,
- BNXT_ULP_ACT_HID_03c6 = 0x03c6,
- BNXT_ULP_ACT_HID_0082 = 0x0082,
- BNXT_ULP_ACT_HID_06bb = 0x06bb,
- BNXT_ULP_ACT_HID_021d = 0x021d,
- BNXT_ULP_ACT_HID_0641 = 0x0641,
- BNXT_ULP_ACT_HID_0512 = 0x0512,
- BNXT_ULP_ACT_HID_03c8 = 0x03c8,
- BNXT_ULP_ACT_HID_0084 = 0x0084,
- BNXT_ULP_ACT_HID_06bd = 0x06bd,
- BNXT_ULP_ACT_HID_06d7 = 0x06d7,
- BNXT_ULP_ACT_HID_02c4 = 0x02c4,
- BNXT_ULP_ACT_HID_042a = 0x042a,
- BNXT_ULP_ACT_HID_036e = 0x036e,
- BNXT_ULP_ACT_HID_06c4 = 0x06c4,
- BNXT_ULP_ACT_HID_0417 = 0x0417,
- BNXT_ULP_ACT_HID_06d9 = 0x06d9,
- BNXT_ULP_ACT_HID_02c6 = 0x02c6,
- BNXT_ULP_ACT_HID_042c = 0x042c,
- BNXT_ULP_ACT_HID_0370 = 0x0370,
- BNXT_ULP_ACT_HID_06c6 = 0x06c6,
- BNXT_ULP_ACT_HID_0419 = 0x0419,
- BNXT_ULP_ACT_HID_0119 = 0x0119,
- BNXT_ULP_ACT_HID_046f = 0x046f,
- BNXT_ULP_ACT_HID_05d5 = 0x05d5,
- BNXT_ULP_ACT_HID_0519 = 0x0519,
- BNXT_ULP_ACT_HID_0106 = 0x0106,
- BNXT_ULP_ACT_HID_05c2 = 0x05c2,
- BNXT_ULP_ACT_HID_011b = 0x011b,
- BNXT_ULP_ACT_HID_0471 = 0x0471,
- BNXT_ULP_ACT_HID_05d7 = 0x05d7,
- BNXT_ULP_ACT_HID_051b = 0x051b,
- BNXT_ULP_ACT_HID_0108 = 0x0108,
- BNXT_ULP_ACT_HID_05c4 = 0x05c4,
- BNXT_ULP_ACT_HID_00a2 = 0x00a2,
- BNXT_ULP_ACT_HID_00a4 = 0x00a4
+ BNXT_ULP_ACT_HID_5fde = 0x5fde,
+ BNXT_ULP_ACT_HID_4a42 = 0x4a42,
+ BNXT_ULP_ACT_HID_0196 = 0x0196,
+ BNXT_ULP_ACT_HID_12a6 = 0x12a6,
+ BNXT_ULP_ACT_HID_4ede = 0x4ede,
+ BNXT_ULP_ACT_HID_0632 = 0x0632,
+ BNXT_ULP_ACT_HID_5fee = 0x5fee,
+ BNXT_ULP_ACT_HID_4a52 = 0x4a52,
+ BNXT_ULP_ACT_HID_01a6 = 0x01a6,
+ BNXT_ULP_ACT_HID_12b6 = 0x12b6,
+ BNXT_ULP_ACT_HID_56ce = 0x56ce,
+ BNXT_ULP_ACT_HID_0e22 = 0x0e22,
+ BNXT_ULP_ACT_HID_67de = 0x67de,
+ BNXT_ULP_ACT_HID_5242 = 0x5242,
+ BNXT_ULP_ACT_HID_0996 = 0x0996,
+ BNXT_ULP_ACT_HID_1aa6 = 0x1aa6,
+ BNXT_ULP_ACT_HID_56de = 0x56de,
+ BNXT_ULP_ACT_HID_0e32 = 0x0e32,
+ BNXT_ULP_ACT_HID_67ee = 0x67ee,
+ BNXT_ULP_ACT_HID_5252 = 0x5252,
+ BNXT_ULP_ACT_HID_09a6 = 0x09a6,
+ BNXT_ULP_ACT_HID_1ab6 = 0x1ab6,
+ BNXT_ULP_ACT_HID_31d0 = 0x31d0,
+ BNXT_ULP_ACT_HID_31e0 = 0x31e0,
+ BNXT_ULP_ACT_HID_39d0 = 0x39d0,
+ BNXT_ULP_ACT_HID_39e0 = 0x39e0,
+ BNXT_ULP_ACT_HID_41d0 = 0x41d0,
+ BNXT_ULP_ACT_HID_41e0 = 0x41e0,
+ BNXT_ULP_ACT_HID_49d0 = 0x49d0,
+ BNXT_ULP_ACT_HID_49e0 = 0x49e0,
+ BNXT_ULP_ACT_HID_64ba = 0x64ba,
+ BNXT_ULP_ACT_HID_64ca = 0x64ca,
+ BNXT_ULP_ACT_HID_6cba = 0x6cba,
+ BNXT_ULP_ACT_HID_6cca = 0x6cca,
+ BNXT_ULP_ACT_HID_74ba = 0x74ba,
+ BNXT_ULP_ACT_HID_74ca = 0x74ca,
+ BNXT_ULP_ACT_HID_00fe = 0x00fe,
+ BNXT_ULP_ACT_HID_010e = 0x010e,
+ BNXT_ULP_ACT_HID_331c = 0x331c,
+ BNXT_ULP_ACT_HID_332c = 0x332c,
+ BNXT_ULP_ACT_HID_6706 = 0x6706,
+ BNXT_ULP_ACT_HID_6716 = 0x6716,
+ BNXT_ULP_ACT_HID_1b6d = 0x1b6d,
+ BNXT_ULP_ACT_HID_1b7d = 0x1b7d,
+ BNXT_ULP_ACT_HID_641a = 0x641a
};
enum bnxt_ulp_df_tpl {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
index 0a5c7e3d6e..73cd7762e5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h
@@ -1,16 +1,18 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Aug 6 11:15:47 2021 */
-
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_WM,
BNXT_ULP_GLB_HF_ID_SVIF_INDEX,
+ BNXT_ULP_GLB_HF_ID_O_ECPRI_TYPE,
+ BNXT_ULP_GLB_HF_ID_I_ECPRI_TYPE,
+ BNXT_ULP_GLB_HF_ID_O_ECPRI_ID,
+ BNXT_ULP_GLB_HF_ID_I_ECPRI_ID,
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC,
BNXT_ULP_GLB_HF_ID_I_ETH_DMAC,
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC,
@@ -65,6 +67,20 @@ enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR,
BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR,
BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_NEXT_HDR,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_NEXT_HDR,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_HDR_LEN,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_HDR_LEN,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_ROUTING_TYPE,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_ROUTING_TYPE,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_SEG_LEFT,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_SEG_LEFT,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_LAST_ENTRY,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_LAST_ENTRY,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_FLAGS,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_FLAGS,
+ BNXT_ULP_GLB_HF_ID_O_SRV6_TAG,
+ BNXT_ULP_GLB_HF_ID_I_SRV6_TAG,
BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT,
@@ -415,94 +431,80 @@ enum bnxt_ulp_hf_0_2_0_bitmask {
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
- BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000080000000000
};
enum bnxt_ulp_hf_0_2_1_bitmask {
BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TC = 0x0000008000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_1_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf_0_2_2_bitmask {
BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_2_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000
};
enum bnxt_ulp_hf_0_2_3_bitmask {
@@ -536,61 +538,41 @@ enum bnxt_ulp_hf_0_2_3_bitmask {
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_TTL = 0x0000000800000000,
BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_CSUM = 0x0000000002000000,
- BNXT_ULP_HF_0_2_3_BITMASK_I_TCP_URP = 0x0000000001000000
+ BNXT_ULP_HF_0_2_3_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_4_bitmask {
BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_CSUM = 0x0000000000800000,
- BNXT_ULP_HF_0_2_4_BITMASK_I_TCP_URP = 0x0000000000400000
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000
};
enum bnxt_ulp_hf_0_2_5_bitmask {
@@ -617,58 +599,57 @@ enum bnxt_ulp_hf_0_2_5_bitmask {
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_5_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TC = 0x0000008000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
- BNXT_ULP_HF_0_2_5_BITMASK_I_UDP_CSUM = 0x0000000020000000
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_5_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000
};
enum bnxt_ulp_hf_0_2_6_bitmask {
BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_VER = 0x2000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TOS = 0x1000000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_LEN = 0x0800000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_TTL = 0x0100000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0001000000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000080000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000040000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
- BNXT_ULP_HF_0_2_6_BITMASK_I_UDP_CSUM = 0x0000000008000000
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SRC_PORT = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DST_PORT = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_SENT_SEQ = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_RECV_ACK = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_DATA_OFF = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_TCP_FLAGS = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_RX_WIN = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_CSUM = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_6_BITMASK_I_TCP_URP = 0x0000000004000000
};
enum bnxt_ulp_hf_0_2_7_bitmask {
@@ -695,21 +676,343 @@ enum bnxt_ulp_hf_0_2_7_bitmask {
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_DMAC = 0x0000080000000000,
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_SMAC = 0x0000040000000000,
BNXT_ULP_HF_0_2_7_BITMASK_I_ETH_TYPE = 0x0000020000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_VER = 0x0000010000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TOS = 0x0000008000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_LEN = 0x0000004000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_TTL = 0x0000000800000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CODE = 0x0000000020000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
- BNXT_ULP_HF_0_2_7_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_7_BITMASK_I_TCP_URP = 0x0000000001000000
+};
+
+enum bnxt_ulp_hf_0_2_8_bitmask {
+ BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_SENT_SEQ = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_RECV_ACK = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_DATA_OFF = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_TCP_FLAGS = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_RX_WIN = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_CSUM = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_8_BITMASK_I_TCP_URP = 0x0000000001000000
+};
+
+enum bnxt_ulp_hf_0_2_9_bitmask {
+ BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_RX_WIN = 0x0000000001000000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_CSUM = 0x0000000000800000,
+ BNXT_ULP_HF_0_2_9_BITMASK_I_TCP_URP = 0x0000000000400000
+};
+
+enum bnxt_ulp_hf_0_2_10_bitmask {
+ BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_TC = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_FLOW_LABEL = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_PROTO_ID = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_SRC_ADDR = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_IPV6_DST_ADDR = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_SRC_PORT = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_DST_PORT = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_LENGTH = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_10_BITMASK_I_UDP_CSUM = 0x0000000080000000
+};
+
+enum bnxt_ulp_hf_0_2_11_bitmask {
+ BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_TC = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_FLOW_LABEL = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_PAYLOAD_LEN = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_IPV6_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_11_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_12_bitmask {
+ BNXT_ULP_HF_0_2_12_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_SRC_PORT = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_DST_PORT = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_LENGTH = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_12_BITMASK_I_UDP_CSUM = 0x0000000020000000
+};
+
+enum bnxt_ulp_hf_0_2_13_bitmask {
+ BNXT_ULP_HF_0_2_13_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_DST_PORT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_LENGTH = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_13_BITMASK_I_UDP_CSUM = 0x0000000008000000
+};
+
+enum bnxt_ulp_hf_0_2_14_bitmask {
+ BNXT_ULP_HF_0_2_14_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_TC = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_FLOW_LABEL = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_PROTO_ID = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_SRC_ADDR = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_IPV6_DST_ADDR = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_SRC_PORT = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_DST_PORT = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_LENGTH = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_O_UDP_CSUM = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_FLAGS = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD0 = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_VNI = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_T_VXLAN_RSVD1 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_DMAC = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_SMAC = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ETH_TYPE = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_VER = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_TOS = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_LEN = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_FRAG_ID = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_FRAG_OFF = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_TTL = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_PROTO_ID = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_CSUM = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_SRC_ADDR = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_IPV4_DST_ADDR = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_TYPE = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_CODE = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_CSUM = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_IDENT = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_14_BITMASK_I_ICMP_SEQ_NUM = 0x0000000010000000
+};
+
+enum bnxt_ulp_hf_0_2_15_bitmask {
+ BNXT_ULP_HF_0_2_15_BITMASK_WM = 0x8000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_SVIF_INDEX = 0x4000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_VER = 0x2000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_TOS = 0x1000000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_LEN = 0x0800000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_TTL = 0x0100000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_CSUM = 0x0040000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_DST_PORT = 0x0004000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_LENGTH = 0x0002000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_O_UDP_CSUM = 0x0001000000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_VNI = 0x0000200000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_DMAC = 0x0000080000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_SMAC = 0x0000040000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ETH_TYPE = 0x0000020000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_VER = 0x0000010000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_TOS = 0x0000008000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_LEN = 0x0000004000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_TTL = 0x0000000800000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_CSUM = 0x0000000200000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_CODE = 0x0000000020000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_CSUM = 0x0000000010000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_IDENT = 0x0000000008000000,
+ BNXT_ULP_HF_0_2_15_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000
};
enum bnxt_ulp_hf_0_3_0_bitmask {
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 305e516a7f..4d325928e5 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Nov 12 19:33:52 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -77,7 +75,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.name = "INGRESS GENERIC_TABLE_MAC_ADDR_CACHE",
.result_num_entries = 512,
.result_num_bytes = 8,
- .key_num_bytes = 10,
+ .key_num_bytes = 12,
.num_buckets = 8,
.hash_tbl_entries = 2048,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
@@ -87,7 +85,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.name = "EGRESS GENERIC_TABLE_MAC_ADDR_CACHE",
.result_num_entries = 512,
.result_num_bytes = 8,
- .key_num_bytes = 10,
+ .key_num_bytes = 12,
.num_buckets = 8,
.hash_tbl_entries = 2048,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
@@ -96,7 +94,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
- .result_num_bytes = 19,
+ .result_num_bytes = 21,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
@@ -106,7 +104,7 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
BNXT_ULP_DIRECTION_EGRESS] = {
.name = "EGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
- .result_num_bytes = 19,
+ .result_num_bytes = 21,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
@@ -135,16 +133,16 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
- .result_num_entries = 0,
+ .result_num_entries = 4096,
.result_num_bytes = 6,
.key_num_bytes = 10,
.num_buckets = 4,
- .hash_tbl_entries = 0,
+ .hash_tbl_entries = 8192,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE << 1 |
BNXT_ULP_DIRECTION_EGRESS] = {
- .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
+ .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_CACHE",
.result_num_entries = 128,
.result_num_bytes = 6,
.key_num_bytes = 10,
@@ -152,6 +150,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.hash_tbl_entries = 512,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_L2_ENCAP_REC_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 6,
+ .key_num_bytes = 14,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_L2_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 14,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GEN_TABLE_VXLAN_ENCAP_REC_CACHE",
@@ -191,6 +209,166 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 22,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_IPV6_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_SOURCE_PROPERTY_IPV6_CACHE",
+ .result_num_entries = 2048,
+ .result_num_bytes = 6,
+ .key_num_bytes = 22,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_VXLAN_ENCAP_IPV6_REC_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 16384,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 6,
+ .key_num_bytes = 29,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SRV6_ENCAP_REC_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_SRV6_ENCAP_REC_CACHE",
+ .result_num_entries = 2048,
+ .result_num_bytes = 6,
+ .key_num_bytes = 86,
+ .num_buckets = 4,
+ .hash_tbl_entries = 8192,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_OUTER_TUNNEL_CACHE",
+ .result_num_entries = 4096,
+ .result_num_bytes = 4,
+ .key_num_bytes = 32,
+ .num_buckets = 4,
+ .hash_tbl_entries = 16384,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_OUTER_TUNNEL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_OUTER_TUNNEL_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 4,
+ .key_num_bytes = 32,
+ .num_buckets = 8,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE",
+ .result_num_entries = 512,
+ .result_num_bytes = 8,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_METER_PROFILE_TBL_CACHE",
+ .result_num_entries = 512,
+ .result_num_bytes = 8,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE",
+ .result_num_entries = 1024,
+ .result_num_bytes = 10,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_SHARED_METER_TBL_CACHE",
+ .result_num_entries = 1024,
+ .result_num_bytes = 10,
+ .key_num_bytes = 4,
+ .num_buckets = 8,
+ .hash_tbl_entries = 2048,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL",
+ .result_num_entries = 256,
+ .result_num_bytes = 8,
+ .key_num_bytes = 3,
+ .num_buckets = 4,
+ .hash_tbl_entries = 1024,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_GLOBAL_REGISTER_TBL << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GENERIC_TABLE_GLOBAL_REGISTER_TBL",
+ .result_num_entries = 0,
+ .result_num_bytes = 8,
+ .key_num_bytes = 3,
+ .num_buckets = 0,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 |
+ BNXT_ULP_DIRECTION_INGRESS] = {
+ .name = "INGRESS GEN_TABLE_CHAIN_ID_CACHE",
+ .result_num_entries = 0,
+ .result_num_bytes = 4,
+ .key_num_bytes = 4,
+ .num_buckets = 4,
+ .hash_tbl_entries = 0,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_CHAIN_ID_CACHE << 1 |
+ BNXT_ULP_DIRECTION_EGRESS] = {
+ .name = "EGRESS GEN_TABLE_CHAIN_ID_CACHE",
+ .result_num_entries = 64,
+ .result_num_bytes = 4,
+ .key_num_bytes = 4,
+ .num_buckets = 4,
+ .hash_tbl_entries = 256,
+ .result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@@ -281,8 +459,15 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xfffffff000000000,
.byte_count_shift = 0,
.packet_count_shift = 36,
- .dynamic_pad_en = 0,
+ .wc_dynamic_pad_en = 1,
+ .em_dynamic_pad_en = 0,
.dynamic_sram_en = 0,
+ .wc_slice_width = 80,
+ .wc_max_slices = 4,
+ .wc_mode_list = {0x00000000, 0x00000002,
+ 0x00000003, 0x00000003},
+ .wc_mod_list_max_size = 4,
+ .wc_ctl_size_bits = 16,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_THOR] = {
@@ -306,13 +491,15 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xfffffff800000000,
.byte_count_shift = 0,
.packet_count_shift = 35,
- .dynamic_pad_en = 1,
+ .wc_dynamic_pad_en = 1,
+ .em_dynamic_pad_en = 1,
.dynamic_sram_en = 1,
- .dyn_encap_list_size = 4,
+ .dyn_encap_list_size = 5,
.dyn_encap_sizes = {{64, TF_TBL_TYPE_ACT_ENCAP_8B},
{128, TF_TBL_TYPE_ACT_ENCAP_16B},
{256, TF_TBL_TYPE_ACT_ENCAP_32B},
- {512, TF_TBL_TYPE_ACT_ENCAP_64B}},
+ {512, TF_TBL_TYPE_ACT_ENCAP_64B},
+ {1024, TF_TBL_TYPE_ACT_ENCAP_128B}},
.dyn_modify_list_size = 4,
.dyn_modify_sizes = {{64, TF_TBL_TYPE_ACT_MODIFY_8B},
{128, TF_TBL_TYPE_ACT_MODIFY_16B},
@@ -348,55 +535,75 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = 0
+ .flags = 0,
+ .vxlan_port = 4789,
+ .vxlan_ip_port = 0
},
{
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .flags = 0
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_SRV6,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = 0,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_SRV6,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 3,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 3,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
.app_id = 4,
@@ -404,576 +611,617 @@ struct bnxt_ulp_app_capabilities_info ulp_app_cap_info_list[] = {
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY |
- BNXT_ULP_APP_CAP_SOCKET_DIRECT
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 3,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
- BNXT_ULP_APP_CAP_UNICAST_ONLY
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
+ BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_HA_DYNAMIC,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 1,
+ .ha_pool_id = 4,
+ .ha_reg_cnt = 9,
+ .ha_reg_state = 10
},
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.flags = BNXT_ULP_APP_CAP_SHARED_EN |
BNXT_ULP_APP_CAP_UNICAST_ONLY |
- BNXT_ULP_APP_CAP_SOCKET_DIRECT
- }
-};
-
-/* List of unnamed app tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = {
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN |
+ BNXT_ULP_APP_CAP_SOCKET_DIRECT |
+ BNXT_ULP_APP_CAP_HA_DYNAMIC,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 1,
+ .ha_pool_id = 4,
+ .ha_reg_cnt = 9,
+ .ha_reg_state = 10
+ },
{
- .app_id = 1,
+ .app_id = 6,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT |
+ BNXT_ULP_APP_CAP_BC_MC_SUPPORT,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 1,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ },
+ {
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 1024
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 250
},
{
- .app_id = 2,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 1024
+ .flags = BNXT_ULP_APP_CAP_BC_MC_SUPPORT |
+ BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN |
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 5,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY |
+ BNXT_ULP_APP_CAP_SHARED_EN |
+ BNXT_ULP_APP_CAP_HOT_UPGRADE_EN,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0,
+ .upgrade_fw_update = 0,
+ .ha_pool_id = 5,
+ .ha_reg_cnt = 7,
+ .ha_reg_state = 8
},
{
- .app_id = 4,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .flags = BNXT_ULP_APP_CAP_UNICAST_ONLY,
+ .vxlan_port = 0,
+ .vxlan_ip_port = 0
+ }
+};
+
+/* List of unnamed app tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_app_resource_resv_list[] = {
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 4,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 6648
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 1792
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 896
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 128
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 5,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 2
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
},
{
- .app_id = 5,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 6648
- }
-};
-
-/* List of global app tf resources required to be reserved per app/device */
-struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
+ .count = 6860
+ },
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
.app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .count = 1792
},
{
.app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 896
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
},
{
.app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
},
{
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 1,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1792
},
{
- .app_id = 1,
+ .app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4096
},
{
.app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
},
{
- .app_id = 2,
+ .app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 64
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
+ .app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 256
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6520
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 392
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 1024
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
- .direction = TF_DIR_RX
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 1024
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 2,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 6860
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 2
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_WC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 704
},
{
- .app_id = 2,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED_OWC,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 704
+ }
+};
+
+/* List of global app tf resources required to be reserved per app/device */
+struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
- .app_id = 2,
+ .app_id = 1,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_RX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
- .direction = TF_DIR_RX
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 2,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
- .direction = TF_DIR_RX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -982,6 +1230,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -990,6 +1239,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -998,6 +1248,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1006,6 +1257,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1014,6 +1266,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1022,6 +1275,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1030,6 +1284,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1038,6 +1293,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1046,6 +1302,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1054,6 +1311,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1062,6 +1320,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1070,6 +1329,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1078,6 +1338,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1086,6 +1347,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1094,6 +1356,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1102,6 +1365,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1110,6 +1374,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1118,6 +1383,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1126,6 +1392,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1134,6 +1401,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1142,6 +1410,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1150,6 +1419,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1158,6 +1428,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1166,6 +1437,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1174,6 +1446,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1182,6 +1455,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1190,6 +1464,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1198,6 +1473,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1206,6 +1482,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1214,6 +1491,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1222,6 +1500,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1230,6 +1509,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1238,6 +1518,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1246,6 +1527,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1254,6 +1536,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1262,6 +1545,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1270,6 +1554,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1278,6 +1563,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
@@ -1286,6 +1572,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
@@ -1294,6 +1581,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
@@ -1302,6 +1590,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
@@ -1310,6 +1599,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3,
@@ -1318,6 +1608,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4,
@@ -1326,6 +1617,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1334,6 +1626,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 4,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1342,6 +1635,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1350,6 +1644,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1358,6 +1653,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1366,6 +1662,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1374,6 +1671,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1382,6 +1680,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1390,6 +1689,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1398,6 +1698,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1406,6 +1707,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1414,6 +1716,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1422,6 +1725,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1430,6 +1734,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1438,6 +1743,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1446,6 +1752,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1454,6 +1761,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1462,6 +1770,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1470,6 +1779,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1478,6 +1788,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1486,6 +1797,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1494,6 +1806,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
@@ -1502,6 +1815,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
@@ -1510,6 +1824,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
@@ -1518,6 +1833,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
@@ -1526,6 +1842,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
@@ -1534,6 +1851,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
@@ -1542,6 +1860,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
@@ -1550,6 +1869,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
@@ -1558,6 +1878,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
@@ -1566,6 +1887,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
@@ -1574,6 +1896,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
@@ -1582,6 +1905,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
@@ -1590,6 +1914,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_4,
@@ -1598,6 +1923,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_5,
@@ -1606,6 +1932,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_6,
@@ -1614,6 +1941,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_7,
@@ -1622,6 +1950,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_8,
@@ -1630,6 +1959,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_9,
@@ -1638,6 +1968,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_10,
@@ -1646,6 +1977,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
@@ -1654,6 +1986,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
@@ -1662,6 +1995,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
@@ -1670,6 +2004,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
@@ -1678,6 +2013,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_3,
@@ -1686,6 +2022,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_4,
@@ -1694,6 +2031,7 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
@@ -1702,4346 +2040,14401 @@ struct bnxt_ulp_glb_resource_info ulp_app_glb_resource_tbl[] = {
{
.app_id = 5,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
- }
-};
-
-/* List of global tf resources required to be reserved per app/device */
-struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ },
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 2,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_EM_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_2,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 12,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
.direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_PROF_FUNC_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_L2_CNTXT_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
- .direction = TF_DIR_TX
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
},
{
- .app_id = 3,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_SHARED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_APP_GLB_AREC_PTR_1,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of global tf resources required to be reserved per app/device */
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
.direction = TF_DIR_TX
},
{
- .app_id = 3,
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_WC_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
.direction = TF_DIR_TX
},
{
- .app_id = 3,
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_8B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_9,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_8,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_9,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 11,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GRE_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_3,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
+ .direction = TF_DIR_TX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ }
+};
+
+/* List of tf resources required to be reserved per app/device */
+struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
+ .count = 256
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .count = 1023
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 0,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 256
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 24
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 256
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 1,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 256
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 4
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 256
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 4
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 24
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 48
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 128
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 16
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 2,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 11264
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 26624
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4096
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 2048
+ },
+ {
+ .app_id = 3,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 6144
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 48
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 12
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 3576
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 3576
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 4,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 64
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 28
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 12
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 192
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 192
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 512
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 256
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 16
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 1
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 2
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 5,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 2
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 7168
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 26624
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 4096
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 1024
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 2048
+ },
+ {
+ .app_id = 6,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 6144
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 422
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 88
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 13168
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 148
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 191
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 63
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 488
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 292
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 144
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 960
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 928
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 15232
+ },
+ {
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_0,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 272
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 6
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_2,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_3,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_4,
- .direction = TF_DIR_RX
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_5,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_6,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_EM_PROF,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_PROFILE_ID_7,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_0,
- .direction = TF_DIR_RX
+ .count = 32
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_1,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_2,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 3,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_EM_KEY_ID_3,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 272
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_RX
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
+ .count = 272
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_WC_PROF,
+ .count = 32
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .count = 63
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_type = TF_IDENT_TYPE_EM_PROF,
+ .count = 32
},
{
- .app_id = 4,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_RX
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
- .direction = TF_DIR_TX
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 7,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_EM_RECORD,
+ .count = 16384
+ },
+ {
+ .app_id = 7,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .glb_regfile_index = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .direction = TF_DIR_TX
- }
-};
-
-/* List of tf resources required to be reserved per app/device */
-struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 15
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 255
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 422
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 88
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 13168
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 148
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 191
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 192
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 6912
+ .count = 128
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 1023
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 511
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 223
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 255
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 488
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 511
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 1
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 292
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 144
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 960
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 928
+ .count = 16
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 15232
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 272
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 32
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 8192
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 31
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 2048
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 64
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 272
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 6
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4096
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 16384
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+ .count = 32
+ },
+ {
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 272
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 63
+ .count = 8
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 8192
+ .count = 1024
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 8192
+ .count = 256
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
- .count = 5
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 4
+ },
+ {
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 2048
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 4
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 100
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 272
+ .count = 2
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 128
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4096
+ .count = 32
},
{
- .app_id = 0,
+ .app_id = 8,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 16384
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .count = 1
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 588
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 128
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 256
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 6144
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 4096
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 8
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 1,
+ .app_id = 9,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 32
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 1024
},
{
- .app_id = 1,
+ .app_id = 9,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 6912
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 15
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
+ .count = 88
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 6912
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1023
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .count = 223
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .count = 255
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
+ .count = 511
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 2,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
+ },
+ {
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .count = 31
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 64
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 2,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 16384
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 32
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 2048
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 100
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 2,
+ .app_id = 10,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 16384
},
{
- .app_id = 3,
+ .app_id = 10,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 422
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 191
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.count = 1023
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.count = 15
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
.count = 255
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 422
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 960
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 88
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 13168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 292
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 148
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 191
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.count = 1023
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.count = 223
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
.count = 255
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 488
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
.count = 511
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 292
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 144
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 960
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 928
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 15232
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 8192
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 7168
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 26624
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
.count = 63
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.count = 4096
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
.count = 1
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EM_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
.count = 1024
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 6
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 128
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
.count = 2048
},
{
- .app_id = 3,
+ .app_id = 11,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
.count = 6144
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 62
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4080
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 4080
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
+ },
+ {
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 128
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .count = 1024
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
- },
- {
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .count = 512
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 64
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 1024
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 12,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 4096
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 32
+ .count = 191
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 63
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 32
+ .count = 192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .count = 8192
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 3340
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .count = 6912
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 3340
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 511
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 15
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
+ .count = 255
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 422
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 88
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 13168
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 148
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 191
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 6912
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
+ .count = 1023
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 511
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ .count = 223
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
+ .count = 255
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .count = 488
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .count = 511
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 292
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 144
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 960
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 928
},
{
- .app_id = 4,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 15232
},
{
- .app_id = 5,
+ .app_id = 13,
.device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_EM_TBL_TYPE_TBL_SCOPE,
+ .count = 1
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
.count = 2
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 1024
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 1024
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1000
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .count = 64
+ },
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 64
},
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ {
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 2
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_RX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 64
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 8192
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 16
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 128
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 128
+ .count = 2048
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 8
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .count = 1000
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 100
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 64
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.count = 32
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 2032
},
{
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 13,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
+ },
+ {
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 16
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 528
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_METER_PROF,
+ .count = 256
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .count = 1023
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
+ .count = 31
+ },
+ {
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
- .count = 32
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 6
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 512
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_RX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
- .count = 32
+ .count = 16384
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_L2_CTXT_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_WC_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .count = 4
+ .count = 63
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.resource_type = TF_IDENT_TYPE_EM_PROF,
- .count = 4
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .count = 512
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
- .count = 256
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EM_FKB,
- .count = 4
+ .count = 8192
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_WC_FKB,
- .count = 4
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .count = 5
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 4
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
- .count = 4
- },
- {
- .app_id = 5,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .resource_type = TF_TBL_TYPE_WC_FKB,
.count = 32
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
- .count = 2
+ .count = 272
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .count = 32
+ .count = 128
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
- .count = 4
+ .count = 4096
},
{
- .app_id = 5,
+ .app_id = 14,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_EM_TBL_TYPE_EM_RECORD,
- .count = 1024
+ .count = 16384
+ },
+ {
+ .app_id = 14,
+ .device_id = BNXT_ULP_DEVICE_ID_THOR,
+ .direction = TF_DIR_TX,
+ .session_type = BNXT_ULP_SESSION_TYPE_DEFAULT,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METADATA,
+ .count = 1
}
};
@@ -6138,787 +16531,1094 @@ uint32_t ulp_act_prop_map_table[] = {
BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN,
[BNXT_ULP_ACT_PROP_IDX_RSS_KEY] =
BNXT_ULP_ACT_PROP_SZ_RSS_KEY,
+ [BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE] =
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE,
+ [BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX] =
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBND,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBND,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBSM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBSM,
+ [BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF] =
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CF,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ID] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ECN_RMP_EN,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL_UPDATE,
+ [BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL] =
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL,
+ [BNXT_ULP_ACT_PROP_IDX_GOTO_CHAINID] =
+ BNXT_ULP_ACT_PROP_SZ_GOTO_CHAINID,
[BNXT_ULP_ACT_PROP_IDX_LAST] =
BNXT_ULP_ACT_PROP_SZ_LAST
};
uint8_t ulp_glb_field_tbl[] = {
- [2048] = 0,
- [2049] = 1,
- [2050] = 2,
- [2052] = 3,
- [2054] = 4,
- [2088] = 5,
- [2090] = 6,
- [2092] = 7,
- [2094] = 8,
- [2096] = 9,
- [2098] = 10,
- [2100] = 11,
- [2102] = 12,
- [2176] = 0,
- [2177] = 1,
- [2178] = 2,
- [2180] = 3,
- [2182] = 4,
- [2196] = 5,
- [2198] = 6,
- [2200] = 7,
- [2202] = 8,
- [2204] = 9,
- [2206] = 10,
- [2208] = 11,
- [2210] = 12,
- [2212] = 13,
- [2214] = 14,
- [2304] = 0,
- [2305] = 1,
- [2306] = 2,
- [2308] = 3,
- [2310] = 4,
- [2344] = 8,
- [2346] = 9,
- [2348] = 10,
- [2350] = 11,
- [2352] = 12,
- [2354] = 13,
- [2356] = 14,
- [2358] = 15,
- [2386] = 5,
- [2390] = 6,
- [2394] = 7,
- [2432] = 0,
- [2433] = 1,
- [2434] = 2,
- [2436] = 3,
- [2438] = 4,
- [2452] = 8,
- [2454] = 9,
- [2456] = 10,
- [2458] = 11,
- [2460] = 12,
- [2462] = 13,
- [2464] = 14,
- [2466] = 15,
- [2468] = 16,
- [2470] = 17,
- [2514] = 5,
- [2518] = 6,
- [2522] = 7,
- [2560] = 0,
- [2561] = 1,
- [2562] = 2,
- [2564] = 3,
- [2566] = 4,
- [2600] = 5,
- [2602] = 6,
- [2604] = 7,
- [2606] = 8,
- [2608] = 9,
- [2610] = 10,
- [2612] = 11,
- [2614] = 12,
- [2616] = 13,
- [2618] = 14,
- [2620] = 15,
- [2622] = 16,
- [2624] = 17,
- [2626] = 18,
- [2628] = 19,
- [2630] = 20,
- [2632] = 21,
- [2688] = 0,
- [2689] = 1,
- [2690] = 2,
- [2692] = 3,
- [2694] = 4,
- [2708] = 5,
- [2710] = 6,
- [2712] = 7,
- [2714] = 8,
- [2716] = 9,
- [2718] = 10,
- [2720] = 11,
- [2722] = 12,
- [2724] = 13,
- [2726] = 14,
- [2744] = 15,
- [2746] = 16,
- [2748] = 17,
- [2750] = 18,
- [2752] = 19,
- [2754] = 20,
- [2756] = 21,
- [2758] = 22,
- [2760] = 23,
- [2816] = 0,
- [2817] = 1,
- [2818] = 2,
- [2820] = 3,
- [2822] = 4,
- [2856] = 5,
- [2858] = 6,
- [2860] = 7,
- [2862] = 8,
- [2864] = 9,
- [2866] = 10,
- [2868] = 11,
- [2870] = 12,
- [2890] = 13,
- [2892] = 14,
- [2894] = 15,
- [2896] = 16,
- [2944] = 0,
- [2945] = 1,
- [2946] = 2,
- [2948] = 3,
- [2950] = 4,
- [2964] = 5,
- [2966] = 6,
- [2968] = 7,
- [2970] = 8,
- [2972] = 9,
- [2974] = 10,
- [2976] = 11,
- [2978] = 12,
- [2980] = 13,
- [2982] = 14,
- [3018] = 15,
- [3020] = 16,
- [3022] = 17,
- [3024] = 18,
- [3072] = 0,
- [3073] = 1,
- [3074] = 2,
- [3076] = 3,
- [3078] = 4,
- [3112] = 8,
- [3114] = 9,
- [3116] = 10,
- [3118] = 11,
- [3120] = 12,
- [3122] = 13,
- [3124] = 14,
- [3126] = 15,
- [3128] = 16,
- [3130] = 17,
- [3132] = 18,
- [3134] = 19,
- [3136] = 20,
- [3138] = 21,
- [3140] = 22,
- [3142] = 23,
- [3144] = 24,
- [3154] = 5,
- [3158] = 6,
- [3162] = 7,
- [3200] = 0,
- [3201] = 1,
- [3202] = 2,
- [3204] = 3,
- [3206] = 4,
- [3220] = 8,
- [3222] = 9,
- [3224] = 10,
- [3226] = 11,
- [3228] = 12,
- [3230] = 13,
- [3232] = 14,
- [3234] = 15,
- [3236] = 16,
- [3238] = 17,
- [3256] = 18,
- [3258] = 19,
- [3260] = 20,
- [3262] = 21,
- [3264] = 22,
- [3266] = 23,
- [3268] = 24,
- [3270] = 25,
- [3272] = 26,
- [3282] = 5,
- [3286] = 6,
- [3290] = 7,
- [3328] = 0,
- [3329] = 1,
- [3330] = 2,
- [3332] = 3,
- [3334] = 4,
- [3368] = 8,
- [3370] = 9,
- [3372] = 10,
- [3374] = 11,
- [3376] = 12,
- [3378] = 13,
- [3380] = 14,
- [3382] = 15,
- [3402] = 16,
- [3404] = 17,
- [3406] = 18,
- [3408] = 19,
- [3410] = 5,
- [3414] = 6,
- [3418] = 7,
- [3456] = 0,
- [3457] = 1,
- [3458] = 2,
- [3460] = 3,
- [3462] = 4,
- [3476] = 8,
- [3478] = 9,
- [3480] = 10,
- [3482] = 11,
- [3484] = 12,
- [3486] = 13,
- [3488] = 14,
- [3490] = 15,
- [3492] = 16,
- [3494] = 17,
- [3530] = 18,
- [3532] = 19,
- [3534] = 20,
- [3536] = 21,
- [3538] = 5,
- [3542] = 6,
- [3546] = 7,
- [3584] = 0,
- [3585] = 1,
- [3586] = 2,
- [3588] = 3,
- [3590] = 4,
- [3604] = 5,
- [3606] = 6,
- [3608] = 7,
- [3610] = 8,
- [3612] = 9,
- [3614] = 10,
- [3616] = 11,
- [3618] = 12,
- [3620] = 13,
- [3622] = 14,
- [3658] = 15,
- [3660] = 16,
- [3662] = 17,
- [3664] = 18,
- [3678] = 19,
- [3679] = 20,
- [3680] = 21,
- [3681] = 22,
[4096] = 0,
[4097] = 1,
- [4098] = 2,
- [4100] = 3,
- [4102] = 4,
- [4116] = 5,
- [4118] = 6,
- [4120] = 7,
- [4122] = 8,
- [4124] = 9,
- [4126] = 10,
- [4128] = 11,
- [4130] = 12,
- [4132] = 13,
- [4134] = 14,
- [4170] = 15,
- [4172] = 16,
- [4174] = 17,
- [4176] = 18,
- [4190] = 19,
- [4191] = 20,
- [4192] = 21,
- [4193] = 22,
+ [4102] = 2,
+ [4104] = 3,
+ [4106] = 4,
+ [4140] = 5,
+ [4142] = 6,
+ [4144] = 7,
+ [4146] = 8,
+ [4148] = 9,
+ [4150] = 10,
+ [4152] = 11,
+ [4154] = 12,
[4224] = 0,
[4225] = 1,
- [4227] = 20,
- [4229] = 21,
- [4231] = 22,
- [4244] = 2,
- [4246] = 3,
- [4248] = 4,
- [4250] = 5,
- [4252] = 6,
- [4254] = 7,
- [4256] = 8,
- [4258] = 9,
- [4260] = 10,
- [4262] = 11,
- [4265] = 23,
- [4267] = 24,
- [4269] = 25,
- [4271] = 26,
- [4273] = 27,
- [4275] = 28,
- [4277] = 29,
- [4279] = 30,
- [4298] = 12,
- [4300] = 13,
- [4302] = 14,
- [4304] = 15,
- [4318] = 16,
- [4319] = 17,
- [4320] = 18,
- [4321] = 19,
+ [4230] = 2,
+ [4232] = 3,
+ [4234] = 4,
+ [4248] = 5,
+ [4250] = 6,
+ [4252] = 7,
+ [4254] = 8,
+ [4256] = 9,
+ [4258] = 10,
+ [4260] = 11,
+ [4262] = 12,
+ [4264] = 13,
+ [4266] = 14,
[4352] = 0,
[4353] = 1,
- [4355] = 20,
- [4357] = 21,
- [4359] = 22,
- [4372] = 2,
- [4373] = 23,
- [4374] = 3,
- [4375] = 24,
- [4376] = 4,
- [4377] = 25,
- [4378] = 5,
- [4379] = 26,
- [4380] = 6,
- [4381] = 27,
- [4382] = 7,
- [4383] = 28,
- [4384] = 8,
- [4385] = 29,
- [4386] = 9,
- [4387] = 30,
- [4388] = 10,
- [4389] = 31,
- [4390] = 11,
- [4391] = 32,
- [4426] = 12,
- [4428] = 13,
- [4430] = 14,
- [4432] = 15,
- [4446] = 16,
- [4447] = 17,
- [4448] = 18,
- [4449] = 19,
+ [4358] = 2,
+ [4360] = 3,
+ [4362] = 4,
+ [4396] = 8,
+ [4398] = 9,
+ [4400] = 10,
+ [4402] = 11,
+ [4404] = 12,
+ [4406] = 13,
+ [4408] = 14,
+ [4410] = 15,
+ [4452] = 5,
+ [4456] = 6,
+ [4460] = 7,
[4480] = 0,
[4481] = 1,
- [4483] = 20,
- [4485] = 21,
- [4487] = 22,
- [4500] = 2,
- [4502] = 3,
- [4504] = 4,
- [4506] = 5,
- [4508] = 6,
- [4510] = 7,
- [4512] = 8,
- [4514] = 9,
- [4516] = 10,
- [4518] = 11,
- [4521] = 23,
- [4523] = 24,
- [4525] = 25,
- [4527] = 26,
- [4529] = 27,
- [4531] = 28,
- [4533] = 29,
- [4535] = 30,
- [4537] = 31,
- [4539] = 32,
- [4541] = 33,
- [4543] = 34,
- [4545] = 35,
- [4547] = 36,
- [4549] = 37,
- [4551] = 38,
- [4553] = 39,
- [4554] = 12,
- [4556] = 13,
- [4558] = 14,
- [4560] = 15,
- [4574] = 16,
- [4575] = 17,
- [4576] = 18,
- [4577] = 19,
+ [4486] = 2,
+ [4488] = 3,
+ [4490] = 4,
+ [4504] = 8,
+ [4506] = 9,
+ [4508] = 10,
+ [4510] = 11,
+ [4512] = 12,
+ [4514] = 13,
+ [4516] = 14,
+ [4518] = 15,
+ [4520] = 16,
+ [4522] = 17,
+ [4580] = 5,
+ [4584] = 6,
+ [4588] = 7,
[4608] = 0,
[4609] = 1,
- [4611] = 20,
- [4613] = 21,
- [4615] = 22,
- [4628] = 2,
- [4629] = 23,
- [4630] = 3,
- [4631] = 24,
- [4632] = 4,
- [4633] = 25,
- [4634] = 5,
- [4635] = 26,
- [4636] = 6,
- [4637] = 27,
- [4638] = 7,
- [4639] = 28,
- [4640] = 8,
- [4641] = 29,
- [4642] = 9,
- [4643] = 30,
- [4644] = 10,
- [4645] = 31,
- [4646] = 11,
- [4647] = 32,
- [4665] = 33,
- [4667] = 34,
- [4669] = 35,
- [4671] = 36,
- [4673] = 37,
- [4675] = 38,
- [4677] = 39,
- [4679] = 40,
- [4681] = 41,
- [4682] = 12,
- [4684] = 13,
- [4686] = 14,
- [4688] = 15,
- [4702] = 16,
- [4703] = 17,
- [4704] = 18,
- [4705] = 19,
+ [4614] = 2,
+ [4616] = 3,
+ [4618] = 4,
+ [4652] = 5,
+ [4654] = 6,
+ [4656] = 7,
+ [4658] = 8,
+ [4660] = 9,
+ [4662] = 10,
+ [4664] = 11,
+ [4666] = 12,
+ [4682] = 13,
+ [4684] = 14,
+ [4686] = 15,
+ [4688] = 16,
+ [4690] = 17,
+ [4692] = 18,
+ [4694] = 19,
+ [4696] = 20,
+ [4698] = 21,
[4736] = 0,
[4737] = 1,
- [4739] = 20,
- [4741] = 21,
- [4743] = 22,
- [4756] = 2,
- [4758] = 3,
- [4760] = 4,
- [4762] = 5,
- [4764] = 6,
- [4766] = 7,
- [4768] = 8,
- [4770] = 9,
- [4772] = 10,
- [4774] = 11,
- [4777] = 23,
- [4779] = 24,
- [4781] = 25,
- [4783] = 26,
- [4785] = 27,
- [4787] = 28,
- [4789] = 29,
- [4791] = 30,
- [4810] = 12,
- [4811] = 31,
- [4812] = 13,
- [4813] = 32,
- [4814] = 14,
- [4815] = 33,
- [4816] = 15,
- [4817] = 34,
- [4830] = 16,
- [4831] = 17,
- [4832] = 18,
- [4833] = 19,
+ [4742] = 2,
+ [4744] = 3,
+ [4746] = 4,
+ [4760] = 5,
+ [4762] = 6,
+ [4764] = 7,
+ [4766] = 8,
+ [4768] = 9,
+ [4770] = 10,
+ [4772] = 11,
+ [4774] = 12,
+ [4776] = 13,
+ [4778] = 14,
+ [4810] = 15,
+ [4812] = 16,
+ [4814] = 17,
+ [4816] = 18,
+ [4818] = 19,
+ [4820] = 20,
+ [4822] = 21,
+ [4824] = 22,
+ [4826] = 23,
[4864] = 0,
[4865] = 1,
- [4867] = 20,
- [4869] = 21,
- [4871] = 22,
- [4884] = 2,
- [4885] = 23,
- [4886] = 3,
- [4887] = 24,
- [4888] = 4,
- [4889] = 25,
- [4890] = 5,
- [4891] = 26,
- [4892] = 6,
- [4893] = 27,
- [4894] = 7,
- [4895] = 28,
- [4896] = 8,
- [4897] = 29,
- [4898] = 9,
- [4899] = 30,
- [4900] = 10,
- [4901] = 31,
- [4902] = 11,
- [4903] = 32,
- [4938] = 12,
- [4939] = 33,
- [4940] = 13,
- [4941] = 34,
- [4942] = 14,
- [4943] = 35,
- [4944] = 15,
- [4945] = 36,
- [4958] = 16,
- [4959] = 17,
- [4960] = 18,
- [4961] = 19,
+ [4870] = 2,
+ [4872] = 3,
+ [4874] = 4,
+ [4908] = 5,
+ [4910] = 6,
+ [4912] = 7,
+ [4914] = 8,
+ [4916] = 9,
+ [4918] = 10,
+ [4920] = 11,
+ [4922] = 12,
+ [4956] = 13,
+ [4958] = 14,
+ [4960] = 15,
+ [4962] = 16,
[4992] = 0,
[4993] = 1,
- [4995] = 20,
- [4997] = 21,
- [4999] = 22,
- [5003] = 33,
- [5005] = 34,
- [5007] = 35,
- [5009] = 36,
- [5011] = 37,
- [5012] = 2,
- [5013] = 23,
- [5014] = 3,
- [5015] = 24,
- [5016] = 4,
- [5017] = 25,
- [5018] = 5,
- [5019] = 26,
- [5020] = 6,
- [5021] = 27,
- [5022] = 7,
- [5023] = 28,
- [5024] = 8,
- [5025] = 29,
- [5026] = 9,
- [5027] = 30,
- [5028] = 10,
- [5029] = 31,
- [5030] = 11,
- [5031] = 32,
- [5066] = 12,
- [5068] = 13,
- [5070] = 14,
- [5072] = 15,
+ [4998] = 2,
+ [5000] = 3,
+ [5002] = 4,
+ [5016] = 5,
+ [5018] = 6,
+ [5020] = 7,
+ [5022] = 8,
+ [5024] = 9,
+ [5026] = 10,
+ [5028] = 11,
+ [5030] = 12,
+ [5032] = 13,
+ [5034] = 14,
+ [5084] = 15,
[5086] = 16,
- [5087] = 17,
- [5088] = 18,
- [5089] = 19,
- [6144] = 0,
- [6145] = 1,
- [6146] = 2,
- [6148] = 3,
- [6150] = 4,
- [6184] = 5,
- [6186] = 6,
- [6188] = 7,
- [6190] = 8,
- [6192] = 9,
- [6194] = 10,
- [6196] = 11,
- [6198] = 12,
- [6272] = 0,
- [6273] = 1,
- [6274] = 2,
- [6276] = 3,
- [6278] = 4,
- [6292] = 5,
- [6294] = 6,
- [6296] = 7,
- [6298] = 8,
- [6300] = 9,
- [6302] = 10,
- [6304] = 11,
- [6306] = 12,
- [6308] = 13,
- [6310] = 14,
- [6400] = 0,
- [6401] = 1,
- [6402] = 2,
- [6404] = 3,
- [6406] = 4,
- [6440] = 8,
- [6442] = 9,
- [6444] = 10,
- [6446] = 11,
- [6448] = 12,
- [6450] = 13,
- [6452] = 14,
- [6454] = 15,
- [6482] = 5,
- [6486] = 6,
- [6490] = 7,
- [6528] = 0,
- [6529] = 1,
- [6530] = 2,
- [6532] = 3,
- [6534] = 4,
- [6548] = 8,
- [6550] = 9,
- [6552] = 10,
- [6554] = 11,
- [6556] = 12,
- [6558] = 13,
- [6560] = 14,
- [6562] = 15,
- [6564] = 16,
- [6566] = 17,
- [6610] = 5,
- [6614] = 6,
- [6618] = 7,
- [6656] = 0,
- [6657] = 1,
- [6658] = 2,
- [6660] = 3,
- [6662] = 4,
- [6696] = 5,
- [6698] = 6,
- [6700] = 7,
- [6702] = 8,
- [6704] = 9,
- [6706] = 10,
- [6708] = 11,
- [6710] = 12,
- [6712] = 13,
- [6714] = 14,
- [6716] = 15,
- [6718] = 16,
- [6720] = 17,
- [6722] = 18,
- [6724] = 19,
- [6726] = 20,
- [6728] = 21,
- [6784] = 0,
- [6785] = 1,
- [6786] = 2,
- [6788] = 3,
- [6790] = 4,
- [6804] = 5,
- [6806] = 6,
- [6808] = 7,
- [6810] = 8,
- [6812] = 9,
- [6814] = 10,
- [6816] = 11,
- [6818] = 12,
- [6820] = 13,
- [6822] = 14,
- [6840] = 15,
- [6842] = 16,
- [6844] = 17,
- [6846] = 18,
- [6848] = 19,
- [6850] = 20,
- [6852] = 21,
- [6854] = 22,
- [6856] = 23,
- [6912] = 0,
- [6913] = 1,
- [6914] = 2,
- [6916] = 3,
- [6918] = 4,
- [6952] = 5,
- [6954] = 6,
- [6956] = 7,
- [6958] = 8,
- [6960] = 9,
- [6962] = 10,
- [6964] = 11,
- [6966] = 12,
- [6986] = 13,
- [6988] = 14,
- [6990] = 15,
- [6992] = 16,
- [7040] = 0,
- [7041] = 1,
- [7042] = 2,
- [7044] = 3,
- [7046] = 4,
- [7060] = 5,
- [7062] = 6,
- [7064] = 7,
- [7066] = 8,
- [7068] = 9,
- [7070] = 10,
- [7072] = 11,
- [7074] = 12,
- [7076] = 13,
- [7078] = 14,
- [7114] = 15,
- [7116] = 16,
- [7118] = 17,
- [7120] = 18,
- [7168] = 0,
- [7169] = 1,
- [7170] = 2,
- [7172] = 3,
- [7174] = 4,
- [7208] = 8,
- [7210] = 9,
- [7212] = 10,
- [7214] = 11,
- [7216] = 12,
- [7218] = 13,
- [7220] = 14,
- [7222] = 15,
- [7224] = 16,
- [7226] = 17,
- [7228] = 18,
- [7230] = 19,
- [7232] = 20,
- [7234] = 21,
- [7236] = 22,
- [7238] = 23,
- [7240] = 24,
- [7250] = 5,
- [7254] = 6,
- [7258] = 7,
- [7296] = 0,
- [7297] = 1,
- [7298] = 2,
- [7300] = 3,
- [7302] = 4,
- [7316] = 8,
- [7318] = 9,
- [7320] = 10,
- [7322] = 11,
- [7324] = 12,
- [7326] = 13,
- [7328] = 14,
- [7330] = 15,
- [7332] = 16,
- [7334] = 17,
- [7352] = 18,
- [7354] = 19,
- [7356] = 20,
- [7358] = 21,
- [7360] = 22,
- [7362] = 23,
- [7364] = 24,
- [7366] = 25,
- [7368] = 26,
- [7378] = 5,
- [7382] = 6,
- [7386] = 7,
- [7424] = 0,
- [7425] = 1,
- [7426] = 2,
- [7428] = 3,
- [7430] = 4,
- [7464] = 8,
- [7466] = 9,
- [7468] = 10,
- [7470] = 11,
- [7472] = 12,
- [7474] = 13,
- [7476] = 14,
- [7478] = 15,
- [7498] = 16,
- [7500] = 17,
- [7502] = 18,
- [7504] = 19,
- [7506] = 5,
- [7510] = 6,
- [7514] = 7,
- [7552] = 0,
- [7553] = 1,
- [7554] = 2,
- [7556] = 3,
- [7558] = 4,
- [7572] = 8,
- [7574] = 9,
- [7576] = 10,
- [7578] = 11,
- [7580] = 12,
- [7582] = 13,
- [7584] = 14,
- [7586] = 15,
- [7588] = 16,
- [7590] = 17,
- [7626] = 18,
- [7628] = 19,
- [7630] = 20,
- [7632] = 21,
- [7634] = 5,
- [7638] = 6,
- [7642] = 7
+ [5088] = 17,
+ [5090] = 18,
+ [5120] = 0,
+ [5121] = 1,
+ [5126] = 2,
+ [5128] = 3,
+ [5130] = 4,
+ [5164] = 8,
+ [5166] = 9,
+ [5168] = 10,
+ [5170] = 11,
+ [5172] = 12,
+ [5174] = 13,
+ [5176] = 14,
+ [5178] = 15,
+ [5194] = 16,
+ [5196] = 17,
+ [5198] = 18,
+ [5200] = 19,
+ [5202] = 20,
+ [5204] = 21,
+ [5206] = 22,
+ [5208] = 23,
+ [5210] = 24,
+ [5220] = 5,
+ [5224] = 6,
+ [5228] = 7,
+ [5248] = 0,
+ [5249] = 1,
+ [5254] = 2,
+ [5256] = 3,
+ [5258] = 4,
+ [5272] = 8,
+ [5274] = 9,
+ [5276] = 10,
+ [5278] = 11,
+ [5280] = 12,
+ [5282] = 13,
+ [5284] = 14,
+ [5286] = 15,
+ [5288] = 16,
+ [5290] = 17,
+ [5322] = 18,
+ [5324] = 19,
+ [5326] = 20,
+ [5328] = 21,
+ [5330] = 22,
+ [5332] = 23,
+ [5334] = 24,
+ [5336] = 25,
+ [5338] = 26,
+ [5348] = 5,
+ [5352] = 6,
+ [5356] = 7,
+ [5376] = 0,
+ [5377] = 1,
+ [5382] = 2,
+ [5384] = 3,
+ [5386] = 4,
+ [5420] = 8,
+ [5422] = 9,
+ [5424] = 10,
+ [5426] = 11,
+ [5428] = 12,
+ [5430] = 13,
+ [5432] = 14,
+ [5434] = 15,
+ [5468] = 16,
+ [5470] = 17,
+ [5472] = 18,
+ [5474] = 19,
+ [5476] = 5,
+ [5480] = 6,
+ [5484] = 7,
+ [5504] = 0,
+ [5505] = 1,
+ [5510] = 2,
+ [5512] = 3,
+ [5514] = 4,
+ [5528] = 8,
+ [5530] = 9,
+ [5532] = 10,
+ [5534] = 11,
+ [5536] = 12,
+ [5538] = 13,
+ [5540] = 14,
+ [5542] = 15,
+ [5544] = 16,
+ [5546] = 17,
+ [5596] = 18,
+ [5598] = 19,
+ [5600] = 20,
+ [5602] = 21,
+ [5604] = 5,
+ [5608] = 6,
+ [5612] = 7,
+ [5632] = 0,
+ [5633] = 1,
+ [5638] = 2,
+ [5640] = 3,
+ [5642] = 4,
+ [5656] = 5,
+ [5658] = 6,
+ [5660] = 7,
+ [5662] = 8,
+ [5664] = 9,
+ [5666] = 10,
+ [5668] = 11,
+ [5670] = 12,
+ [5672] = 13,
+ [5674] = 14,
+ [5724] = 15,
+ [5726] = 16,
+ [5728] = 17,
+ [5730] = 18,
+ [5744] = 19,
+ [5745] = 20,
+ [5746] = 21,
+ [5747] = 22,
+ [8192] = 0,
+ [8193] = 1,
+ [8198] = 2,
+ [8200] = 3,
+ [8202] = 4,
+ [8236] = 5,
+ [8238] = 6,
+ [8240] = 7,
+ [8242] = 8,
+ [8244] = 9,
+ [8246] = 10,
+ [8248] = 11,
+ [8250] = 12,
+ [8284] = 13,
+ [8286] = 14,
+ [8288] = 15,
+ [8290] = 16,
+ [8304] = 17,
+ [8305] = 18,
+ [8306] = 19,
+ [8307] = 20,
+ [8320] = 0,
+ [8321] = 1,
+ [8326] = 2,
+ [8328] = 3,
+ [8330] = 4,
+ [8344] = 5,
+ [8346] = 6,
+ [8348] = 7,
+ [8350] = 8,
+ [8352] = 9,
+ [8354] = 10,
+ [8356] = 11,
+ [8358] = 12,
+ [8360] = 13,
+ [8362] = 14,
+ [8412] = 15,
+ [8414] = 16,
+ [8416] = 17,
+ [8418] = 18,
+ [8432] = 19,
+ [8433] = 20,
+ [8434] = 21,
+ [8435] = 22,
+ [8448] = 0,
+ [8449] = 1,
+ [8455] = 18,
+ [8457] = 19,
+ [8459] = 20,
+ [8492] = 2,
+ [8493] = 21,
+ [8494] = 3,
+ [8495] = 22,
+ [8496] = 4,
+ [8497] = 23,
+ [8498] = 5,
+ [8499] = 24,
+ [8500] = 6,
+ [8501] = 25,
+ [8502] = 7,
+ [8503] = 26,
+ [8504] = 8,
+ [8505] = 27,
+ [8506] = 9,
+ [8507] = 28,
+ [8540] = 10,
+ [8542] = 11,
+ [8544] = 12,
+ [8546] = 13,
+ [8560] = 14,
+ [8561] = 15,
+ [8562] = 16,
+ [8563] = 17,
+ [8576] = 0,
+ [8577] = 1,
+ [8583] = 20,
+ [8585] = 21,
+ [8587] = 22,
+ [8600] = 2,
+ [8602] = 3,
+ [8604] = 4,
+ [8606] = 5,
+ [8608] = 6,
+ [8610] = 7,
+ [8612] = 8,
+ [8614] = 9,
+ [8616] = 10,
+ [8618] = 11,
+ [8621] = 23,
+ [8623] = 24,
+ [8625] = 25,
+ [8627] = 26,
+ [8629] = 27,
+ [8631] = 28,
+ [8633] = 29,
+ [8635] = 30,
+ [8668] = 12,
+ [8670] = 13,
+ [8672] = 14,
+ [8674] = 15,
+ [8688] = 16,
+ [8689] = 17,
+ [8690] = 18,
+ [8691] = 19,
+ [8704] = 0,
+ [8705] = 1,
+ [8711] = 18,
+ [8713] = 19,
+ [8715] = 20,
+ [8729] = 21,
+ [8731] = 22,
+ [8733] = 23,
+ [8735] = 24,
+ [8737] = 25,
+ [8739] = 26,
+ [8741] = 27,
+ [8743] = 28,
+ [8745] = 29,
+ [8747] = 30,
+ [8748] = 2,
+ [8750] = 3,
+ [8752] = 4,
+ [8754] = 5,
+ [8756] = 6,
+ [8758] = 7,
+ [8760] = 8,
+ [8762] = 9,
+ [8796] = 10,
+ [8798] = 11,
+ [8800] = 12,
+ [8802] = 13,
+ [8816] = 14,
+ [8817] = 15,
+ [8818] = 16,
+ [8819] = 17,
+ [8832] = 0,
+ [8833] = 1,
+ [8839] = 20,
+ [8841] = 21,
+ [8843] = 22,
+ [8856] = 2,
+ [8857] = 23,
+ [8858] = 3,
+ [8859] = 24,
+ [8860] = 4,
+ [8861] = 25,
+ [8862] = 5,
+ [8863] = 26,
+ [8864] = 6,
+ [8865] = 27,
+ [8866] = 7,
+ [8867] = 28,
+ [8868] = 8,
+ [8869] = 29,
+ [8870] = 9,
+ [8871] = 30,
+ [8872] = 10,
+ [8873] = 31,
+ [8874] = 11,
+ [8875] = 32,
+ [8924] = 12,
+ [8926] = 13,
+ [8928] = 14,
+ [8930] = 15,
+ [8944] = 16,
+ [8945] = 17,
+ [8946] = 18,
+ [8947] = 19,
+ [8960] = 0,
+ [8961] = 1,
+ [8967] = 18,
+ [8969] = 19,
+ [8971] = 20,
+ [9004] = 2,
+ [9005] = 21,
+ [9006] = 3,
+ [9007] = 22,
+ [9008] = 4,
+ [9009] = 23,
+ [9010] = 5,
+ [9011] = 24,
+ [9012] = 6,
+ [9013] = 25,
+ [9014] = 7,
+ [9015] = 26,
+ [9016] = 8,
+ [9017] = 27,
+ [9018] = 9,
+ [9019] = 28,
+ [9035] = 29,
+ [9037] = 30,
+ [9039] = 31,
+ [9041] = 32,
+ [9043] = 33,
+ [9045] = 34,
+ [9047] = 35,
+ [9049] = 36,
+ [9051] = 37,
+ [9052] = 10,
+ [9054] = 11,
+ [9056] = 12,
+ [9058] = 13,
+ [9072] = 14,
+ [9073] = 15,
+ [9074] = 16,
+ [9075] = 17,
+ [9088] = 0,
+ [9089] = 1,
+ [9095] = 20,
+ [9097] = 21,
+ [9099] = 22,
+ [9112] = 2,
+ [9114] = 3,
+ [9116] = 4,
+ [9118] = 5,
+ [9120] = 6,
+ [9122] = 7,
+ [9124] = 8,
+ [9126] = 9,
+ [9128] = 10,
+ [9130] = 11,
+ [9133] = 23,
+ [9135] = 24,
+ [9137] = 25,
+ [9139] = 26,
+ [9141] = 27,
+ [9143] = 28,
+ [9145] = 29,
+ [9147] = 30,
+ [9163] = 31,
+ [9165] = 32,
+ [9167] = 33,
+ [9169] = 34,
+ [9171] = 35,
+ [9173] = 36,
+ [9175] = 37,
+ [9177] = 38,
+ [9179] = 39,
+ [9180] = 12,
+ [9182] = 13,
+ [9184] = 14,
+ [9186] = 15,
+ [9200] = 16,
+ [9201] = 17,
+ [9202] = 18,
+ [9203] = 19,
+ [9216] = 0,
+ [9217] = 1,
+ [9223] = 18,
+ [9225] = 19,
+ [9227] = 20,
+ [9241] = 21,
+ [9243] = 22,
+ [9245] = 23,
+ [9247] = 24,
+ [9249] = 25,
+ [9251] = 26,
+ [9253] = 27,
+ [9255] = 28,
+ [9257] = 29,
+ [9259] = 30,
+ [9260] = 2,
+ [9262] = 3,
+ [9264] = 4,
+ [9266] = 5,
+ [9268] = 6,
+ [9270] = 7,
+ [9272] = 8,
+ [9274] = 9,
+ [9291] = 31,
+ [9293] = 32,
+ [9295] = 33,
+ [9297] = 34,
+ [9299] = 35,
+ [9301] = 36,
+ [9303] = 37,
+ [9305] = 38,
+ [9307] = 39,
+ [9308] = 10,
+ [9310] = 11,
+ [9312] = 12,
+ [9314] = 13,
+ [9328] = 14,
+ [9329] = 15,
+ [9330] = 16,
+ [9331] = 17,
+ [9344] = 0,
+ [9345] = 1,
+ [9351] = 20,
+ [9353] = 21,
+ [9355] = 22,
+ [9368] = 2,
+ [9369] = 23,
+ [9370] = 3,
+ [9371] = 24,
+ [9372] = 4,
+ [9373] = 25,
+ [9374] = 5,
+ [9375] = 26,
+ [9376] = 6,
+ [9377] = 27,
+ [9378] = 7,
+ [9379] = 28,
+ [9380] = 8,
+ [9381] = 29,
+ [9382] = 9,
+ [9383] = 30,
+ [9384] = 10,
+ [9385] = 31,
+ [9386] = 11,
+ [9387] = 32,
+ [9419] = 33,
+ [9421] = 34,
+ [9423] = 35,
+ [9425] = 36,
+ [9427] = 37,
+ [9429] = 38,
+ [9431] = 39,
+ [9433] = 40,
+ [9435] = 41,
+ [9436] = 12,
+ [9438] = 13,
+ [9440] = 14,
+ [9442] = 15,
+ [9456] = 16,
+ [9457] = 17,
+ [9458] = 18,
+ [9459] = 19,
+ [9472] = 0,
+ [9473] = 1,
+ [9479] = 18,
+ [9481] = 19,
+ [9483] = 20,
+ [9516] = 2,
+ [9517] = 21,
+ [9518] = 3,
+ [9519] = 22,
+ [9520] = 4,
+ [9521] = 23,
+ [9522] = 5,
+ [9523] = 24,
+ [9524] = 6,
+ [9525] = 25,
+ [9526] = 7,
+ [9527] = 26,
+ [9528] = 8,
+ [9529] = 27,
+ [9530] = 9,
+ [9531] = 28,
+ [9564] = 10,
+ [9565] = 29,
+ [9566] = 11,
+ [9567] = 30,
+ [9568] = 12,
+ [9569] = 31,
+ [9570] = 13,
+ [9571] = 32,
+ [9584] = 14,
+ [9585] = 15,
+ [9586] = 16,
+ [9587] = 17,
+ [9600] = 0,
+ [9601] = 1,
+ [9607] = 20,
+ [9609] = 21,
+ [9611] = 22,
+ [9624] = 2,
+ [9626] = 3,
+ [9628] = 4,
+ [9630] = 5,
+ [9632] = 6,
+ [9634] = 7,
+ [9636] = 8,
+ [9638] = 9,
+ [9640] = 10,
+ [9642] = 11,
+ [9645] = 23,
+ [9647] = 24,
+ [9649] = 25,
+ [9651] = 26,
+ [9653] = 27,
+ [9655] = 28,
+ [9657] = 29,
+ [9659] = 30,
+ [9692] = 12,
+ [9693] = 31,
+ [9694] = 13,
+ [9695] = 32,
+ [9696] = 14,
+ [9697] = 33,
+ [9698] = 15,
+ [9699] = 34,
+ [9712] = 16,
+ [9713] = 17,
+ [9714] = 18,
+ [9715] = 19,
+ [9728] = 0,
+ [9729] = 1,
+ [9735] = 18,
+ [9737] = 19,
+ [9739] = 20,
+ [9753] = 21,
+ [9755] = 22,
+ [9757] = 23,
+ [9759] = 24,
+ [9761] = 25,
+ [9763] = 26,
+ [9765] = 27,
+ [9767] = 28,
+ [9769] = 29,
+ [9771] = 30,
+ [9772] = 2,
+ [9774] = 3,
+ [9776] = 4,
+ [9778] = 5,
+ [9780] = 6,
+ [9782] = 7,
+ [9784] = 8,
+ [9786] = 9,
+ [9820] = 10,
+ [9821] = 31,
+ [9822] = 11,
+ [9823] = 32,
+ [9824] = 12,
+ [9825] = 33,
+ [9826] = 13,
+ [9827] = 34,
+ [9840] = 14,
+ [9841] = 15,
+ [9842] = 16,
+ [9843] = 17,
+ [9856] = 0,
+ [9857] = 1,
+ [9863] = 20,
+ [9865] = 21,
+ [9867] = 22,
+ [9880] = 2,
+ [9881] = 23,
+ [9882] = 3,
+ [9883] = 24,
+ [9884] = 4,
+ [9885] = 25,
+ [9886] = 5,
+ [9887] = 26,
+ [9888] = 6,
+ [9889] = 27,
+ [9890] = 7,
+ [9891] = 28,
+ [9892] = 8,
+ [9893] = 29,
+ [9894] = 9,
+ [9895] = 30,
+ [9896] = 10,
+ [9897] = 31,
+ [9898] = 11,
+ [9899] = 32,
+ [9948] = 12,
+ [9949] = 33,
+ [9950] = 13,
+ [9951] = 34,
+ [9952] = 14,
+ [9953] = 35,
+ [9954] = 15,
+ [9955] = 36,
+ [9968] = 16,
+ [9969] = 17,
+ [9970] = 18,
+ [9971] = 19,
+ [9984] = 0,
+ [9985] = 1,
+ [9991] = 18,
+ [9993] = 19,
+ [9995] = 20,
+ [9999] = 31,
+ [10001] = 32,
+ [10003] = 33,
+ [10005] = 34,
+ [10007] = 35,
+ [10009] = 21,
+ [10011] = 22,
+ [10013] = 23,
+ [10015] = 24,
+ [10017] = 25,
+ [10019] = 26,
+ [10021] = 27,
+ [10023] = 28,
+ [10025] = 29,
+ [10027] = 30,
+ [10028] = 2,
+ [10030] = 3,
+ [10032] = 4,
+ [10034] = 5,
+ [10036] = 6,
+ [10038] = 7,
+ [10040] = 8,
+ [10042] = 9,
+ [10076] = 10,
+ [10078] = 11,
+ [10080] = 12,
+ [10082] = 13,
+ [10096] = 14,
+ [10097] = 15,
+ [10098] = 16,
+ [10099] = 17,
+ [10112] = 0,
+ [10113] = 1,
+ [10119] = 20,
+ [10121] = 21,
+ [10123] = 22,
+ [10127] = 33,
+ [10129] = 34,
+ [10131] = 35,
+ [10133] = 36,
+ [10135] = 37,
+ [10136] = 2,
+ [10137] = 23,
+ [10138] = 3,
+ [10139] = 24,
+ [10140] = 4,
+ [10141] = 25,
+ [10142] = 5,
+ [10143] = 26,
+ [10144] = 6,
+ [10145] = 27,
+ [10146] = 7,
+ [10147] = 28,
+ [10148] = 8,
+ [10149] = 29,
+ [10150] = 9,
+ [10151] = 30,
+ [10152] = 10,
+ [10153] = 31,
+ [10154] = 11,
+ [10155] = 32,
+ [10204] = 12,
+ [10206] = 13,
+ [10208] = 14,
+ [10210] = 15,
+ [10224] = 16,
+ [10225] = 17,
+ [10226] = 18,
+ [10227] = 19,
+ [12288] = 0,
+ [12289] = 1,
+ [12294] = 2,
+ [12296] = 3,
+ [12298] = 4,
+ [12332] = 5,
+ [12334] = 6,
+ [12336] = 7,
+ [12338] = 8,
+ [12340] = 9,
+ [12342] = 10,
+ [12344] = 11,
+ [12346] = 12,
+ [12416] = 0,
+ [12417] = 1,
+ [12422] = 2,
+ [12424] = 3,
+ [12426] = 4,
+ [12440] = 5,
+ [12442] = 6,
+ [12444] = 7,
+ [12446] = 8,
+ [12448] = 9,
+ [12450] = 10,
+ [12452] = 11,
+ [12454] = 12,
+ [12456] = 13,
+ [12458] = 14,
+ [12544] = 0,
+ [12545] = 1,
+ [12550] = 2,
+ [12552] = 3,
+ [12554] = 4,
+ [12588] = 8,
+ [12590] = 9,
+ [12592] = 10,
+ [12594] = 11,
+ [12596] = 12,
+ [12598] = 13,
+ [12600] = 14,
+ [12602] = 15,
+ [12644] = 5,
+ [12648] = 6,
+ [12652] = 7,
+ [12672] = 0,
+ [12673] = 1,
+ [12678] = 2,
+ [12680] = 3,
+ [12682] = 4,
+ [12696] = 8,
+ [12698] = 9,
+ [12700] = 10,
+ [12702] = 11,
+ [12704] = 12,
+ [12706] = 13,
+ [12708] = 14,
+ [12710] = 15,
+ [12712] = 16,
+ [12714] = 17,
+ [12772] = 5,
+ [12776] = 6,
+ [12780] = 7,
+ [12800] = 0,
+ [12801] = 1,
+ [12806] = 2,
+ [12808] = 3,
+ [12810] = 4,
+ [12844] = 5,
+ [12846] = 6,
+ [12848] = 7,
+ [12850] = 8,
+ [12852] = 9,
+ [12854] = 10,
+ [12856] = 11,
+ [12858] = 12,
+ [12874] = 13,
+ [12876] = 14,
+ [12878] = 15,
+ [12880] = 16,
+ [12882] = 17,
+ [12884] = 18,
+ [12886] = 19,
+ [12888] = 20,
+ [12890] = 21,
+ [12928] = 0,
+ [12929] = 1,
+ [12934] = 2,
+ [12936] = 3,
+ [12938] = 4,
+ [12952] = 5,
+ [12954] = 6,
+ [12956] = 7,
+ [12958] = 8,
+ [12960] = 9,
+ [12962] = 10,
+ [12964] = 11,
+ [12966] = 12,
+ [12968] = 13,
+ [12970] = 14,
+ [13002] = 15,
+ [13004] = 16,
+ [13006] = 17,
+ [13008] = 18,
+ [13010] = 19,
+ [13012] = 20,
+ [13014] = 21,
+ [13016] = 22,
+ [13018] = 23,
+ [13056] = 0,
+ [13057] = 1,
+ [13062] = 2,
+ [13064] = 3,
+ [13066] = 4,
+ [13100] = 5,
+ [13102] = 6,
+ [13104] = 7,
+ [13106] = 8,
+ [13108] = 9,
+ [13110] = 10,
+ [13112] = 11,
+ [13114] = 12,
+ [13148] = 13,
+ [13150] = 14,
+ [13152] = 15,
+ [13154] = 16,
+ [13184] = 0,
+ [13185] = 1,
+ [13190] = 2,
+ [13192] = 3,
+ [13194] = 4,
+ [13208] = 5,
+ [13210] = 6,
+ [13212] = 7,
+ [13214] = 8,
+ [13216] = 9,
+ [13218] = 10,
+ [13220] = 11,
+ [13222] = 12,
+ [13224] = 13,
+ [13226] = 14,
+ [13276] = 15,
+ [13278] = 16,
+ [13280] = 17,
+ [13282] = 18,
+ [13312] = 0,
+ [13313] = 1,
+ [13318] = 2,
+ [13320] = 3,
+ [13322] = 4,
+ [13356] = 8,
+ [13358] = 9,
+ [13360] = 10,
+ [13362] = 11,
+ [13364] = 12,
+ [13366] = 13,
+ [13368] = 14,
+ [13370] = 15,
+ [13386] = 16,
+ [13388] = 17,
+ [13390] = 18,
+ [13392] = 19,
+ [13394] = 20,
+ [13396] = 21,
+ [13398] = 22,
+ [13400] = 23,
+ [13402] = 24,
+ [13412] = 5,
+ [13416] = 6,
+ [13420] = 7,
+ [13440] = 0,
+ [13441] = 1,
+ [13446] = 2,
+ [13448] = 3,
+ [13450] = 4,
+ [13464] = 8,
+ [13466] = 9,
+ [13468] = 10,
+ [13470] = 11,
+ [13472] = 12,
+ [13474] = 13,
+ [13476] = 14,
+ [13478] = 15,
+ [13480] = 16,
+ [13482] = 17,
+ [13514] = 18,
+ [13516] = 19,
+ [13518] = 20,
+ [13520] = 21,
+ [13522] = 22,
+ [13524] = 23,
+ [13526] = 24,
+ [13528] = 25,
+ [13530] = 26,
+ [13540] = 5,
+ [13544] = 6,
+ [13548] = 7,
+ [13568] = 0,
+ [13569] = 1,
+ [13574] = 2,
+ [13576] = 3,
+ [13578] = 4,
+ [13612] = 8,
+ [13614] = 9,
+ [13616] = 10,
+ [13618] = 11,
+ [13620] = 12,
+ [13622] = 13,
+ [13624] = 14,
+ [13626] = 15,
+ [13660] = 16,
+ [13662] = 17,
+ [13664] = 18,
+ [13666] = 19,
+ [13668] = 5,
+ [13672] = 6,
+ [13676] = 7,
+ [13696] = 0,
+ [13697] = 1,
+ [13702] = 2,
+ [13704] = 3,
+ [13706] = 4,
+ [13720] = 8,
+ [13722] = 9,
+ [13724] = 10,
+ [13726] = 11,
+ [13728] = 12,
+ [13730] = 13,
+ [13732] = 14,
+ [13734] = 15,
+ [13736] = 16,
+ [13738] = 17,
+ [13788] = 18,
+ [13790] = 19,
+ [13792] = 20,
+ [13794] = 21,
+ [13796] = 5,
+ [13800] = 6,
+ [13804] = 7
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
index 8869ab1c33..9d4ea8b422 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -15,7 +13,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 5,
+ .num_tbls = 9,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -25,56 +23,128 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 2, ingress */
[2] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 6,
- .start_tbl_idx = 5,
+ .num_tbls = 10,
+ .start_tbl_idx = 9,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 }
},
/* act_tid: 3, ingress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 11,
+ .num_tbls = 6,
+ .start_tbl_idx = 19,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 }
},
- /* act_tid: 4, egress */
+ /* act_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 5,
- .start_tbl_idx = 15,
+ .num_tbls = 7,
+ .start_tbl_idx = 25,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 7,
+ .cond_start_idx = 18,
.cond_nums = 0 }
},
- /* act_tid: 5, egress */
+ /* act_tid: 5, ingress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 4,
- .start_tbl_idx = 20,
+ .num_tbls = 20,
+ .start_tbl_idx = 32,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 12,
+ .cond_start_idx = 25,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 12,
- .start_tbl_idx = 24,
+ .num_tbls = 7,
+ .start_tbl_idx = 52,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 15,
+ .cond_start_idx = 40,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 7, egress */
+ [7] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 6,
+ .start_tbl_idx = 59,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 8, egress */
+ [8] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 15,
+ .start_tbl_idx = 65,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 9, egress */
+ [9] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 5,
+ .start_tbl_idx = 80,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 68,
+ .cond_nums = 0 }
+ },
+ /* act_tid: 10, egress */
+ [10] = {
+ .device_name = BNXT_ULP_DEVICE_ID_THOR,
+ .num_tbls = 11,
+ .start_tbl_idx = 85,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 71,
.cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
+ { /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 0,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
+ { /* act_tid: 1, , table: control.meter_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 1,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 1, , table: shared_mirror_record.rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
@@ -83,20 +153,31 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 0,
+ .cond_start_idx = 2,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 0,
- .blob_key_bit_size = 1,
- .key_bit_size = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 1,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
.key_num_fields = 1,
- .ident_start_idx = 0,
+ .ident_start_idx = 1,
.ident_nums = 1
},
+ { /* act_tid: 1, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 3,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -107,7 +188,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 1,
+ .cond_start_idx = 4,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -124,10 +205,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 2,
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 2,
+ .cond_start_idx = 5,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
@@ -137,6 +218,26 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.result_num_fields = 0,
.encap_num_fields = 47
},
+ { /* act_tid: 1, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 6,
+ .cond_nums = 3 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 48,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
{ /* act_tid: 1, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
@@ -147,13 +248,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 48,
+ .result_start_idx = 95,
.result_bit_size = 128,
.result_num_fields = 17
},
@@ -167,24 +268,88 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 9,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 65,
+ .result_start_idx = 112,
.result_bit_size = 64,
.result_num_fields = 13
},
- { /* act_tid: 2, , table: control.0 */
+ { /* act_tid: 2, , table: control.delete_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 9,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 10,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ { /* act_tid: 2, , table: control.mirror_del_exist_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 10,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 2, , table: control.mirror_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 11,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 2, , table: control.create */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 12,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -199,14 +364,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 3,
+ .cond_start_idx = 12,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 78,
+ .result_start_idx = 125,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -220,14 +385,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 3,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 83,
+ .result_start_idx = 130,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -241,14 +406,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 84,
+ .result_start_idx = 131,
.result_bit_size = 64,
.result_num_fields = 13,
.encap_num_fields = 0
@@ -263,13 +428,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 97,
+ .result_start_idx = 144,
.result_bit_size = 32,
.result_num_fields = 5
},
@@ -283,19 +448,54 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 4,
+ .cond_start_idx = 13,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1,
- .blob_key_bit_size = 1,
- .key_bit_size = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC,
+ .key_start_idx = 3,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
.key_num_fields = 1,
- .result_start_idx = 102,
+ .result_start_idx = 149,
.result_bit_size = 36,
.result_num_fields = 2
},
+ { /* act_tid: 3, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 13,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 4,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 3,
+ .ident_nums = 1
+ },
+ { /* act_tid: 3, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 14,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -306,12 +506,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 4,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 104,
+ .result_start_idx = 151,
.result_bit_size = 64,
.result_num_fields = 1
},
@@ -325,12 +525,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 2,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 5,
+ .cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 105,
+ .result_start_idx = 152,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -345,12 +545,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 6,
+ .cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 152,
+ .result_start_idx = 199,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 47
@@ -365,386 +565,564 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 7,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 199,
+ .result_start_idx = 246,
.result_bit_size = 128,
.result_num_fields = 17
},
+ { /* act_tid: 4, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 18,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 5,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 4,
+ .ident_nums = 1
+ },
+ { /* act_tid: 4, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 19,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 7,
+ .cond_start_idx = 20,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 216,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 263,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 4, , table: int_vtag_encap_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
+ { /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 8,
+ .cond_start_idx = 21,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 217,
+ .result_start_idx = 264,
.result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 11
+ .result_num_fields = 0
},
- { /* act_tid: 4, , table: mod_record.dec_ttl_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ { /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 22,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 228,
+ .result_start_idx = 264,
.result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .result_num_fields = 0
},
- { /* act_tid: 4, , table: int_full_act_record.0 */
+ { /* act_tid: 4, , table: int_compact_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
- .cond_start_idx = 10,
+ .cond_start_idx = 23,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 275,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 264,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0
},
- { /* act_tid: 4, , table: int_compact_act_record.0 */
+ { /* act_tid: 4, , table: int_compact_act_record.1 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 12,
+ .cond_start_idx = 25,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 292,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 277,
.result_bit_size = 64,
- .result_num_fields = 13
+ .result_num_fields = 13,
+ .encap_num_fields = 0
},
- { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ { /* act_tid: 5, , table: control.create_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 11,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 25,
+ .cond_nums = 2 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 4,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 27,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 305,
- .result_bit_size = 64,
- .result_num_fields = 1
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 6,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
+ .ident_nums = 0
},
- { /* act_tid: 5, , table: mod_record.ing_ttl */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ { /* act_tid: 5, , table: control.shared_meter_profile_0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 2,
- .cond_false_goto = 1,
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 28,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 306,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ { /* act_tid: 5, , table: meter_profile_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 29,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 353,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 290,
+ .result_bit_size = 65,
+ .result_num_fields = 11
},
- { /* act_tid: 5, , table: int_full_act_record.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_PROF,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 29,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 400,
- .result_bit_size = 128,
- .result_num_fields = 17
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 7,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .result_start_idx = 301,
+ .result_bit_size = 42,
+ .result_num_fields = 2
},
- { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 29,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 417,
- .result_bit_size = 64,
- .result_num_fields = 1
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 8,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
+ .ident_nums = 0
+ },
+ { /* act_tid: 5, , table: control.meter_created_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 30,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* act_tid: 6, , table: source_property_cache.rd */
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 31,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2,
- .blob_key_bit_size = 80,
- .key_bit_size = 80,
- .key_num_fields = 2,
- .ident_start_idx = 1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 9,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 5,
.ident_nums = 1
},
- { /* act_tid: 6, , table: control.0 */
+ { /* act_tid: 5, , table: control.shared_meter_profile_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 17,
+ .cond_start_idx = 31,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ { /* act_tid: 5, , table: meter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_type = TF_TBL_TYPE_METER_INST,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
- .cond_nums = 1 },
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 32,
+ .cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .record_size = 16,
- .result_start_idx = 418,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 3
+ .result_start_idx = 303,
+ .result_bit_size = 64,
+ .result_num_fields = 5
},
- { /* act_tid: 6, , table: source_property_cache.wr */
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
+ .cond_true_goto = 0,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 19,
+ .cond_start_idx = 32,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 4,
- .blob_key_bit_size = 80,
- .key_bit_size = 80,
- .key_num_fields = 2,
- .result_start_idx = 421,
- .result_bit_size = 48,
- .result_num_fields = 2
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .key_start_idx = 10,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .result_start_idx = 308,
+ .result_bit_size = 74,
+ .result_num_fields = 3
},
- { /* act_tid: 6, , table: sp_smac_ipv6.0 */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
+ { /* act_tid: 5, , table: control.delete_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 5,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 19,
+ .cond_start_idx = 32,
.cond_nums = 1 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .record_size = 32,
- .result_start_idx = 423,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 3
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ { /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_METER_PROFILE_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
+ .cond_false_goto = 2,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 20,
- .cond_nums = 2 },
+ .cond_start_idx = 33,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 6,
- .blob_key_bit_size = 136,
- .key_bit_size = 136,
- .key_num_fields = 5,
- .ident_start_idx = 2,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 11,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 6,
.ident_nums = 1
},
- { /* act_tid: 6, , table: control.0 */
+ { /* act_tid: 5, , table: control.mtr_prof_ref_cnt_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 22,
+ .cond_start_idx = 34,
.cond_nums = 1 },
- .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID
- },
- { /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 23,
- .cond_nums = 2 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 426,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 30
- },
- { /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 25,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 11,
- .blob_key_bit_size = 136,
- .key_bit_size = 136,
- .key_num_fields = 5,
- .result_start_idx = 456,
- .result_bit_size = 48,
- .result_num_fields = 2
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 12,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 7,
+ .ident_nums = 1
+ },
+ { /* act_tid: 5, , table: control.shared_mtr_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 36,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 5, , table: control.update_check */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 37,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_METER_TBL_CACHE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 37,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 13,
+ .blob_key_bit_size = 32,
+ .key_bit_size = 32,
+ .key_num_fields = 1,
+ .ident_start_idx = 8,
+ .ident_nums = 1
},
- { /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
+ { /* act_tid: 5, , table: meter_tbl.update_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 38,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_RD_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ident_start_idx = 9,
+ .ident_nums = 3,
+ .result_bit_size = 64
+ },
+ { /* act_tid: 5, , table: meter_tbl.update_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_METER_INST,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 40,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 311,
+ .result_bit_size = 64,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 6, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 40,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 14,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 12,
+ .ident_nums = 1
+ },
+ { /* act_tid: 6, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 41,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 42,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 316,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: int_vtag_encap_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
@@ -752,15 +1130,35 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 25,
- .cond_nums = 2 },
+ .cond_start_idx = 43,
+ .cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 458,
+ .result_start_idx = 317,
.result_bit_size = 0,
.result_num_fields = 0,
- .encap_num_fields = 30
+ .encap_num_fields = 11
+ },
+ { /* act_tid: 6, , table: mod_record.dec_ttl_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 44,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 328,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
{ /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -770,516 +1168,4512 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 0,
- .cond_false_goto = 0,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 27,
- .cond_nums = 0 },
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 45,
+ .cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 488,
+ .result_start_idx = 375,
.result_bit_size = 128,
.result_num_fields = 17
- }
-};
-
-struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
- /* cond_execute: act_tid: 1, shared_mirror_record.rd */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
- },
- /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
- },
- /* cond_execute: act_tid: 1, mod_record.ing_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
},
- /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 6, , table: int_compact_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_COMPACT_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 47,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 392,
+ .result_bit_size = 64,
+ .result_num_fields = 13
},
- /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 7, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 47,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 15,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 13,
+ .ident_nums = 1
},
- /* cond_execute: act_tid: 3, mod_record.ing_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ { /* act_tid: 7, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 48,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ { /* act_tid: 7, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 49,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 405,
+ .result_bit_size = 64,
+ .result_num_fields = 1
},
- /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ { /* act_tid: 7, , table: mod_record.ing_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 2,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 50,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 406,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
- /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
- {
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ { /* act_tid: 7, , table: mod_record.ing_no_ttl */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 51,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 453,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 7, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 52,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 500,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 8, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 52,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 16,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 14,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 53,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 8, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 517,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 8, , table: source_property_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 55,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 17,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .ident_start_idx = 15,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 56,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 8, , table: sp_smac_ipv4.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 57,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .record_size = 16,
+ .result_start_idx = 518,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 8, , table: source_property_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SOURCE_PROPERTY_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 58,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 19,
+ .blob_key_bit_size = 80,
+ .key_bit_size = 80,
+ .key_num_fields = 2,
+ .result_start_idx = 521,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 8, , table: sp_smac_ipv6.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 58,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .record_size = 32,
+ .result_start_idx = 523,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3
+ },
+ { /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 59,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 21,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .ident_start_idx = 16,
+ .ident_nums = 1
+ },
+ { /* act_tid: 8, , table: mod_record.ing_l2write */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 61,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 526,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 8, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 3,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 63,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 64,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 573,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_VXLAN_ENCAP_REC_CACHE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 66,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 26,
+ .blob_key_bit_size = 136,
+ .key_bit_size = 136,
+ .key_num_fields = 5,
+ .result_start_idx = 603,
+ .result_bit_size = 48,
+ .result_num_fields = 2
+ },
+ { /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 66,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 605,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 30
+ },
+ { /* act_tid: 8, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 68,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 635,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 9, , table: shared_mirror_record.rd */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 2,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 68,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 31,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 17,
+ .ident_nums = 1
+ },
+ { /* act_tid: 9, , table: control.mirror */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 69,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 70,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 652,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 9, , table: mod_record.vf_2_vf */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 71,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 653,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 9, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 71,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 700,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 10, , table: control.delete_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 71,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 72,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_NOP,
+ .key_start_idx = 32,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .ident_start_idx = 18,
+ .ident_nums = 1
+ },
+ { /* act_tid: 10, , table: control.mirror_del_exist_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 72,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 10, , table: control.mirror_ref_cnt_chk */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 73,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .func_info = {
+ .func_opc = BNXT_ULP_FUNC_OPC_EQ,
+ .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE,
+ .func_opr1 = BNXT_ULP_RF_IDX_REF_CNT,
+ .func_src2 = BNXT_ULP_FUNC_SRC_CONST,
+ .func_opr2 = 1,
+ .func_dst_opr = BNXT_ULP_RF_IDX_CC }
+ },
+ { /* act_tid: 10, , table: control.create */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 74,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* act_tid: 10, , table: mirror_tbl.alloc */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 74,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 717,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 10, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 74,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 722,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 10, , table: mod_record.vf_2_vf */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 723,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* act_tid: 10, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 770,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* act_tid: 10, , table: mirror_tbl.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 787,
+ .result_bit_size = 32,
+ .result_num_fields = 5
+ },
+ { /* act_tid: 10, , table: shared_mirror_record.wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TBL_TYPE_MIRROR_CONFIG,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 75,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .ref_cnt_opcode = BNXT_ULP_REF_CNT_OPC_INC,
+ .key_start_idx = 33,
+ .blob_key_bit_size = 4,
+ .key_bit_size = 4,
+ .key_num_fields = 1,
+ .result_start_idx = 792,
+ .result_bit_size = 36,
+ .result_num_fields = 2
+ }
+};
+
+struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
+ /* cond_execute: act_tid: 1, shared_meter_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER
+ },
+ /* cond_execute: act_tid: 1, control.meter_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 1, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 1, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 1, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ /* cond_execute: act_tid: 2, control.delete_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 2, control.mirror_del_exist_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 2, control.mirror_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 2, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 3, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 3, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 4, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 4, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_rss_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_queue_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ /* cond_execute: act_tid: 4, int_compact_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 5, control.create_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_UPDATE
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 5, meter_profile_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE
+ },
+ /* cond_execute: act_tid: 5, control.shared_meter_profile_0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, control.meter_created_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, control.shared_meter_profile_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 5, control.delete_check */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 5, meter_profile_tbl_cache.del_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER_PROFILE
+ },
+ /* cond_execute: act_tid: 5, control.mtr_prof_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.del_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, control.shared_mtr_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 5, shared_meter_tbl_cache.rd_update */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_METER
+ },
+ /* cond_execute: act_tid: 5, meter_tbl.update_rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID_UPDATE
+ },
+ /* cond_execute: act_tid: 6, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 6, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 6, mod_record.dec_ttl_egr */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 6, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ },
+ /* cond_execute: act_tid: 7, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 7, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 7, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 7, mod_record.ing_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 7, mod_record.ing_no_ttl */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ },
+ /* cond_execute: act_tid: 8, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 8, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 8, source_property_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 8, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, sp_smac_ipv4.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ },
+ /* cond_execute: act_tid: 8, sp_smac_ipv6.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ },
+ /* cond_execute: act_tid: 8, vxlan_encap_rec_cache.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 8, mod_record.ing_l2write */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ /* cond_execute: act_tid: 8, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 8, int_tun_encap_record.ipv4_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 8, int_tun_encap_record.ipv6_vxlan */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ },
+ /* cond_execute: act_tid: 9, shared_mirror_record.rd */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 9, control.mirror */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 9, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 10, control.delete_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_DELETE
+ },
+ /* cond_execute: act_tid: 10, control.mirror_del_exist_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: act_tid: 10, control.mirror_ref_cnt_chk */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_CC
+ },
+ /* cond_execute: act_tid: 10, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ }
+};
+
+struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
+ /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER & 0xff}
+ }
+ },
+ /* act_tid: 1, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ },
+ /* act_tid: 3, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 4, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ {
+ .field_info_mask = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "sw_meter_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ID & 0xff}
+ }
+ },
+ /* act_tid: 6, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 7, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: source_property_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: source_property_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
+ {
+ .field_info_mask = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "ipv4_dst_addr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "udp_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ }
+ },
+ /* act_tid: 9, , table: shared_mirror_record.rd */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
+ }
+ },
+ /* act_tid: 10, , table: shared_mirror_record.wr */
+ {
+ .field_info_mask = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "shared_index",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
+ /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 1, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_METER & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 1, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_DECAP_FUNC_NONE}
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_METER >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_METER & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: mirror_tbl.alloc */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 2, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 2, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ },
+ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 3, , table: mod_record.ing_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ {
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ttl_update",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tun_md_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "reserved_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip_ipv4_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_dport_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "metadata_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_op",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "metadata_prof",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 3, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ },
+ {
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
+ },
+ {
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ /* act_tid: 4, , table: int_compact_act_record.0 */
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RSS_VNIC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RSS_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
- /* cond_execute: act_tid: 4, mod_record.dec_ttl_egr */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 4, int_full_act_record.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, mod_record.ing_ttl */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 5, mod_record.ing_no_ttl */
+ /* act_tid: 4, , table: int_compact_act_record.1 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_DEC_TTL
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, source_property_cache.rd */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
- /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
- .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
- /* cond_execute: act_tid: 6, vxlan_encap_rec_cache.rd */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .description = "use_default",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
- /* cond_execute: act_tid: 6, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.ipv4_vxlan */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.ipv6_vxlan */
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV6
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .cond_opcode = BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_T_VXLAN
- }
-};
-
-struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
- /* act_tid: 1, , table: shared_mirror_record.rd */
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 5, , table: meter_profile_tbl.0 */
{
- .field_info_mask = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE & 0xff}
- }
+ .description = "cf",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CF & 0xff}
+ },
+ {
+ .description = "pm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM & 0xff}
+ },
+ {
+ .description = "rfc2698",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698 & 0xff}
+ },
+ {
+ .description = "cbsm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBSM & 0xff}
+ },
+ {
+ .description = "ebsm",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBSM & 0xff}
+ },
+ {
+ .description = "cbnd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBND & 0xff}
+ },
+ {
+ .description = "ebnd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBND & 0xff}
+ },
+ {
+ .description = "cbs",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS & 0xff}
+ },
+ {
+ .description = "ebs",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS & 0xff}
+ },
+ {
+ .description = "cir",
+ .field_bit_size = 17,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR & 0xff}
+ },
+ {
+ .description = "eir",
+ .field_bit_size = 17,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR & 0xff}
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "meter_profile_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
+ },
+ /* act_tid: 5, , table: meter_tbl.0 */
+ {
+ .description = "bkt_c",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
+ },
+ {
+ .description = "bkt_e",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
+ },
+ {
+ .description = "mtr_val",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL & 0xff}
+ },
+ {
+ .description = "ecn_rmp_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN & 0xff}
+ },
+ {
+ .description = "meter_profile",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "meter_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PTR_0 & 0xff}
},
- /* act_tid: 2, , table: shared_mirror_record.wr */
{
- .field_info_mask = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
- },
- .field_info_spec = {
- .description = "shared_index",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
- }
+ .description = "sw_meter_profile_id",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID & 0xff}
},
- /* act_tid: 6, , table: source_property_cache.rd */
+ /* act_tid: 5, , table: meter_tbl.update_wr */
{
- .field_info_mask = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- }
+ .description = "bkt_c",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
},
{
- .field_info_mask = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- }
+ .description = "bkt_e",
+ .field_bit_size = 27,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (134217727 >> 24) & 0xff,
+ (134217727 >> 16) & 0xff,
+ (134217727 >> 8) & 0xff,
+ 134217727 & 0xff}
},
- /* act_tid: 6, , table: source_property_cache.wr */
{
- .field_info_mask = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- }
+ .description = "mtr_val",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr3 = {
+ (BNXT_ULP_RF_IDX_RF_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RF_0 & 0xff}
},
{
- .field_info_mask = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- }
+ .description = "ecn_rmp_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN_UPDATE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_METER_INST_ECN_RMP_EN & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr3 = {
+ (BNXT_ULP_RF_IDX_RF_1 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RF_1 & 0xff}
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
{
- .field_info_mask = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
- }
+ .description = "meter_profile",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0 & 0xff}
},
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
{
- .field_info_mask = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
- }
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 6, , table: int_vtag_encap_record.0 */
{
- .field_info_mask = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
- }
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .field_info_mask = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- }
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- }
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
{
- .field_info_mask = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
- }
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "ipv4_dst_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
- }
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
- }
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "udp_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- }
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
- .field_info_mask = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
- /* act_tid: 1, , table: int_flow_counter_tbl.0 */
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ },
{
- .description = "count",
- .field_bit_size = 64,
+ .description = "vtag_de",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 1, , table: mod_record.ing_ttl */
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ },
+ /* act_tid: 6, , table: mod_record.dec_ttl_egr */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -1462,8 +5856,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
},
{
.description = "ttl_il3_dec",
@@ -1471,8 +5865,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
},
{
.description = "ttl_tl3_rdir",
@@ -1521,211 +5915,63 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- {
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- /* act_tid: 1, , table: int_full_act_record.0 */
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "encap_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DEC_TTL & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr2 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd1",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "decap_func",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_DECAP_FUNC_NONE}
- },
- {
- .description = "meter",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "stats_op",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "use_default",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "mirror",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr2 = {
- (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* act_tid: 6, , table: int_full_act_record.0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
- .description = "drop",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
- .description = "hit",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* act_tid: 1, , table: int_compact_act_record.0 */
- {
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
@@ -1734,23 +5980,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "decap_func",
.field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_DECAP_FUNC_THRU_TUN},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_DECAP_FUNC_NONE}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "meter",
@@ -1781,8 +6012,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -1819,21 +6050,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "vlan_del_rpt",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_VLAN_DEL_RPT_STRIP_OUTER},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "drop",
@@ -1860,49 +6078,11 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: mirror_tbl.alloc */
- {
- .description = "act_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "reserved",
- .field_bit_size = 13,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ignore_drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "copy_ing_or_egr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "enable",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* act_tid: 2, , table: int_flow_counter_tbl.0 */
- {
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: int_compact_act_record.0 */
+ /* act_tid: 6, , table: int_compact_act_record.0 */
{
.description = "rsvd0",
.field_bit_size = 8,
@@ -1944,8 +6124,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -1956,109 +6136,70 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "mirror",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr2 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "cond_copy",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 2, , table: mirror_tbl.wr */
- {
- .description = "act_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 13,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ignore_drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "copy_ing_or_egr",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enable",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- 1}
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
- /* act_tid: 2, , table: shared_mirror_record.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror_id",
- .field_bit_size = 4,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 3, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 7, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 3, , table: mod_record.ing_ttl */
+ /* act_tid: 7, , table: mod_record.ing_ttl */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -2112,14 +6253,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -2340,12 +6507,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -2437,7 +6634,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 3, , table: mod_record.ing_no_ttl */
+ /* act_tid: 7, , table: mod_record.ing_no_ttl */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -2489,14 +6686,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -2704,12 +6927,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -2801,7 +7054,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 3, , table: int_full_act_record.0 */
+ /* act_tid: 7, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -2851,9 +7104,16 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- 1}
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
},
{
.description = "stats_ptr",
@@ -2870,8 +7130,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
.description = "use_default",
@@ -2883,7 +7143,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "mirror",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
{
.description = "cond_copy",
@@ -2917,94 +7180,83 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_opr1 = {
1}
},
- /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 8, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ /* act_tid: 8, , table: sp_smac_ipv4.0 */
{
- .description = "ecv_valid",
- .field_bit_size = 1,
+ .description = "smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
- },
- {
- .description = "ecv_custom_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "ipv4_src_addr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ULP_THOR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
- },
- {
- .description = "ecv_l2_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ecv_l3_type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "reserved",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 8, , table: source_property_cache.wr */
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "vtag_tpid",
+ .description = "sp_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
},
+ /* act_tid: 8, , table: sp_smac_ipv6.0 */
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
+ (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
},
{
- .description = "vtag_de",
- .field_bit_size = 1,
+ .description = "ipv6_src_addr",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "reserved",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: mod_record.dec_ttl_egr */
+ /* act_tid: 8, , table: mod_record.ing_l2write */
{
.description = "metadata_en",
.field_bit_size = 1,
@@ -3039,9 +7291,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tun_md_en",
@@ -3058,14 +7308,40 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_smac_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ 1},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_ipv6_en",
@@ -3166,50 +7442,37 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "alt_pfid",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "alt_vid",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_rsvd",
.field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ttl_tl3_dec",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "ttl_il3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "tun_new_prot",
@@ -3234,12 +7497,42 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l2_dmac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_DST & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l2_smac",
.field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SET_MAC_SRC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr2 = {
+ (BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
.description = "l3_sip_ipv6",
@@ -3271,622 +7564,730 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 4, , table: int_full_act_record.0 */
+ /* act_tid: 8, , table: int_tun_encap_record.ipv4_vxlan */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L2_EN_YES}
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ },
+ {
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ },
+ {
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_i_vlan_type",
.field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ {
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
},
{
- .description = "mod_rec_ptr",
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
+ },
+ {
+ .description = "enc_ipv4_pkt_id",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
},
{
- .description = "rsvd1",
+ .description = "enc_ipv4_frag",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
},
{
- .description = "rsvd0",
+ .description = "enc_ipv4_ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "stats_op",
- .field_bit_size = 1,
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
},
{
- .description = "stats_ptr",
+ .description = "enc_udp_dport",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
},
{
- .description = "use_default",
- .field_bit_size = 1,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.wr */
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "drop",
- .field_bit_size = 1,
+ .description = "enc_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
+ /* act_tid: 8, , table: int_tun_encap_record.ipv6_vxlan */
{
- .description = "hit",
+ .description = "ecv_valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- /* act_tid: 4, , table: int_compact_act_record.0 */
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ ULP_THOR_SYM_ECV_VALID_YES}
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
},
{
- .description = "stats_op",
+ .description = "ecv_l2_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ ULP_THOR_SYM_ECV_L2_EN_YES}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
},
{
- .description = "use_default",
- .field_bit_size = 1,
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
},
{
- .description = "cond_copy",
- .field_bit_size = 1,
+ .description = "enc_eth_dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_o_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_o_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_i_vlan_tag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
{
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_i_vlan_type",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr2 = {
+ (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 5, , table: int_flow_counter_tbl.0 */
{
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_ihl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 5, , table: mod_record.ing_ttl */
{
- .description = "metadata_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_tos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rem_ovlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_pkt_id",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rem_ivlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_frag",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rep_add_ivlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "rep_add_ovlan",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "enc_ipv4_proto",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "ttl_update",
- .field_bit_size = 1,
+ .description = "enc_ipv4_daddr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "enc_ipv6_vtc",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- 1}
+ (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
},
{
- .description = "tun_md_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_zero",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_proto",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
},
{
- .description = "l2_dmac_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_ttl",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
},
{
- .description = "l2_smac_en",
- .field_bit_size = 1,
+ .description = "enc_ipv6_daddr",
+ .field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
},
{
- .description = "l3_sip_ipv6_en",
- .field_bit_size = 1,
+ .description = "enc_udp_sport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
},
{
- .description = "l3_dip_ipv6_en",
- .field_bit_size = 1,
+ .description = "enc_udp_dport",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_opr1 = {
+ (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
},
{
- .description = "l3_sip_ipv4_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_flags",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
},
{
- .description = "l3_dip_ipv4_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_rsvd0",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
},
{
- .description = "l4_sport_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_vni",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
},
{
- .description = "l4_dport_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "enc_vxlan_rsvd1",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
+ BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
},
+ /* act_tid: 8, , table: int_full_act_record.0 */
{
- .description = "metadata_data",
+ .description = "sp_rec_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_rsvd",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_op",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "metadata_prof",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
},
{
- .description = "ivlan_tpid",
+ .description = "encap_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_de",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
- .description = "ovlan_tpid",
+ .description = "mod_rec_ptr",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_de",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
- .description = "alt_pfid",
- .field_bit_size = 4,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_vid",
- .field_bit_size = 12,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_rsvd",
- .field_bit_size = 12,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_dec",
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
+ 1}
},
{
- .description = "ttl_il3_dec",
- .field_bit_size = 1,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
- BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
- .description = "ttl_tl3_rdir",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
},
{
- .description = "ttl_il3_rdir",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_new_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "tun_ex_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "tun_mv",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "reserved",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "mirror",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff}
},
{
- .description = "l3_sip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ 1}
},
+ /* act_tid: 9, , table: int_flow_counter_tbl.0 */
{
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: mod_record.ing_no_ttl */
+ /* act_tid: 9, , table: mod_record.vf_2_vf */
{
.description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "rem_ovlan",
@@ -3957,98 +8358,55 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l3_sip_ipv4_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_ipv4_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_sport_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dport_en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- 1},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_data",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
.description = "metadata_rsvd",
.field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_op",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "metadata_prof",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ivlan_tpid",
@@ -4168,84 +8526,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "l3_sip_ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l3_dip_ipv4",
.field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_IPV4_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l4_sport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
.description = "l4_dport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr2 = {
- (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 5, , table: int_full_act_record.0 */
+ /* act_tid: 9, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -4270,788 +8568,435 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
{
.description = "rsvd1",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "rsvd0",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "decap_func",
- .field_bit_size = 5,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meter",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "stats_op",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
- },
- {
- .description = "stats_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
- },
- {
- .description = "vnic_or_vport",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
- },
- {
- .description = "use_default",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "mirror",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "cond_copy",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "drop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "hit",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "type",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- /* act_tid: 6, , table: int_flow_counter_tbl.0 */
- {
- .description = "count",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: sp_smac_ipv4.0 */
- {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- },
- {
- .description = "ipv4_src_addr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: source_property_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
- },
- /* act_tid: 6, , table: sp_smac_ipv6.0 */
- {
- .description = "smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_SMAC & 0xff}
- },
- {
- .description = "ipv6_src_addr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
- },
- {
- .description = "reserved",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* act_tid: 6, , table: int_tun_encap_record.ipv4_vxlan */
- {
- .description = "ecv_valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VALID_YES}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ 1}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "enc_eth_dmac",
- .field_bit_size = 48,
+ .description = "use_default",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_tag",
- .field_bit_size = 16,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_SHARED_SAMPLE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_RF,
.field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ (BNXT_ULP_RF_IDX_MIRROR_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_ID_0 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "cond_copy",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_i_vlan_tag",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_i_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_ihl",
- .field_bit_size = 8,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_IHL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_IHL & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_tos",
- .field_bit_size = 8,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_TOS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_TOS & 0xff}
+ 1}
},
+ /* act_tid: 10, , table: mirror_tbl.alloc */
{
- .description = "enc_ipv4_pkt_id",
+ .description = "act_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_PKT_ID >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_PKT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_frag",
- .field_bit_size = 16,
+ .description = "reserved",
+ .field_bit_size = 13,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_FRAG >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_FRAG & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_ttl",
- .field_bit_size = 8,
+ .description = "ignore_drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_TTL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_TTL & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_proto",
- .field_bit_size = 8,
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_PROTO >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_PROTO & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv4_daddr",
- .field_bit_size = 32,
+ .description = "enable",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV4_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV4_DADDR & 0xff}
+ 1}
},
+ /* act_tid: 10, , table: int_flow_counter_tbl.0 */
{
- .description = "enc_ipv6_vtc",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* act_tid: 10, , table: mod_record.vf_2_vf */
{
- .description = "enc_ipv6_zero",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "enc_ipv6_proto",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rem_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv6_ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rem_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_ipv6_daddr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "rep_add_ivlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_udp_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ .description = "rep_add_ovlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_udp_dport",
- .field_bit_size = 16,
+ .description = "ttl_update",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_flags",
- .field_bit_size = 8,
+ .description = "tun_md_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_rsvd0",
- .field_bit_size = 24,
+ .description = "reserved_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_vni",
- .field_bit_size = 24,
+ .description = "l2_dmac_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_vxlan_rsvd1",
- .field_bit_size = 8,
+ .description = "l2_smac_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l3_sip_ipv6_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip_ipv6_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: int_tun_encap_record.ipv6_vxlan */
{
- .description = "ecv_valid",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "l4_sport_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L2_EN_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff}
+ (BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_L4_TYPE_UDP_CSUM}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_ECV_TUN_TYPE_VXLAN}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_eth_dmac",
- .field_bit_size = 48,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_ETH_DMAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "enc_o_vlan_tag",
+ .description = "ivlan_tpid",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_o_vlan_type",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_O_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_O_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_i_vlan_tag",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TCI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TCI & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .description = "ivlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_i_vlan_type",
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_tpid",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OI_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr2 = {
- (BNXT_ULP_ENC_FIELD_I_VLAN_TYPE >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_I_VLAN_TYPE & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_ihl",
- .field_bit_size = 8,
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_il3_rdir",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_tos",
- .field_bit_size = 8,
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_pkt_id",
+ .description = "tun_ex_prot",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_frag",
+ .description = "tun_mv",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_ttl",
- .field_bit_size = 8,
+ .description = "reserved",
+ .field_bit_size = 0,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_proto",
- .field_bit_size = 8,
+ .description = "l2_dmac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv4_daddr",
- .field_bit_size = 32,
+ .description = "l2_smac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_vtc",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_VTC_FLOW & 0xff}
- },
- {
- .description = "enc_ipv6_zero",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_proto",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_PROTO >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_PROTO & 0xff}
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_TTL >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_TTL & 0xff}
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_ipv6_daddr",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_IPV6_DADDR >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_IPV6_DADDR & 0xff}
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_udp_sport",
+ .description = "l4_sport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_SPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_SPORT & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "enc_udp_dport",
+ .description = "l4_dport",
.field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_UDP_DPORT >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_UDP_DPORT & 0xff}
- },
- {
- .description = "enc_vxlan_flags",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_FLAGS >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_FLAGS & 0xff}
- },
- {
- .description = "enc_vxlan_rsvd0",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD0 & 0xff}
- },
- {
- .description = "enc_vxlan_vni",
- .field_bit_size = 24,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_VNI & 0xff}
- },
- {
- .description = "enc_vxlan_rsvd1",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ENC_FIELD,
- .field_opr1 = {
- (BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
- BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
- /* act_tid: 6, , table: int_full_act_record.0 */
+ /* act_tid: 10, , table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_SP_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_SP_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
{
.description = "rsvd1",
@@ -5098,10 +9043,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
.description = "use_default",
@@ -5146,10 +9091,74 @@ struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
+ },
+ /* act_tid: 10, , table: mirror_tbl.wr */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 13,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ignore_drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "copy_ing_or_egr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* act_tid: 10, , table: shared_mirror_record.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "mirror_id",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MIRROR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MIRROR_PTR_0 & 0xff}
}
};
struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
+ /* act_tid: 1, , table: shared_meter_tbl_cache.rd */
+ {
+ .description = "meter_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
/* act_tid: 1, , table: shared_mirror_record.rd */
{
.description = "mirror_id",
@@ -5157,18 +9166,121 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
.ident_bit_size = 4,
.ident_bit_pos = 32
},
- /* act_tid: 6, , table: source_property_cache.rd */
+ /* act_tid: 2, , table: shared_mirror_record.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 3, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 4, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.rd2 */
+ {
+ .description = "meter_profile_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_profile_tbl_cache.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
+ },
+ /* act_tid: 5, , table: shared_meter_tbl_cache.rd_update */
+ {
+ .description = "meter_ptr",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PTR_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 5, , table: meter_tbl.update_rd */
+ {
+ .description = "ecn_rmp_en",
+ .regfile_idx = BNXT_ULP_RF_IDX_RF_1,
+ .ident_bit_size = 1,
+ .ident_bit_pos = 55
+ },
+ {
+ .description = "meter_profile",
+ .regfile_idx = BNXT_ULP_RF_IDX_METER_PROFILE_PTR_0,
+ .ident_bit_size = 8,
+ .ident_bit_pos = 56
+ },
+ {
+ .description = "mtr_val",
+ .regfile_idx = BNXT_ULP_RF_IDX_RF_0,
+ .ident_bit_size = 1,
+ .ident_bit_pos = 54
+ },
+ /* act_tid: 6, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 7, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 8, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 8, , table: source_property_cache.rd */
{
.description = "sp_rec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.ident_bit_size = 16,
.ident_bit_pos = 32
},
- /* act_tid: 6, , table: vxlan_encap_rec_cache.rd */
+ /* act_tid: 8, , table: vxlan_encap_rec_cache.rd */
{
.description = "enc_rec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.ident_bit_size = 16,
.ident_bit_pos = 32
+ },
+ /* act_tid: 9, , table: shared_mirror_record.rd */
+ {
+ .description = "mirror_id",
+ .regfile_idx = BNXT_ULP_RF_IDX_MIRROR_ID_0,
+ .ident_bit_size = 4,
+ .ident_bit_pos = 32
+ },
+ /* act_tid: 10, , table: shared_mirror_record.del_chk */
+ {
+ .description = "rid",
+ .regfile_idx = BNXT_ULP_RF_IDX_RID,
+ .ident_bit_size = 32,
+ .ident_bit_pos = 0
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 46c0d624dc..1a6c94f187 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Wed Nov 24 17:15:38 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -55,7 +53,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = {
/* class_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
- .num_tbls = 25,
+ .num_tbls = 33,
.start_tbl_idx = 91,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -123,9 +121,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.key_start_idx = 2,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.ident_start_idx = 4,
.ident_nums = 1
},
@@ -157,7 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 7,
+ .key_start_idx = 8,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -181,10 +179,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 28,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 29,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.result_start_idx = 6,
.result_bit_size = 62,
.result_num_fields = 4
@@ -214,7 +212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 33,
+ .key_start_idx = 35,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -287,7 +285,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 36,
+ .key_start_idx = 38,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -312,7 +310,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 79,
+ .key_start_idx = 81,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -332,7 +330,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 82,
+ .key_start_idx = 84,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -354,7 +352,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 196,
+ .key_start_idx = 198,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -425,7 +423,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 199,
+ .key_start_idx = 201,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -453,7 +451,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 242,
+ .key_start_idx = 244,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -478,7 +476,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 285,
+ .key_start_idx = 287,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -503,7 +501,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 288,
+ .key_start_idx = 290,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -528,7 +526,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 402,
+ .key_start_idx = 404,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -553,7 +551,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 516,
+ .key_start_idx = 518,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -578,7 +576,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 630,
+ .key_start_idx = 632,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -603,7 +601,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 744,
+ .key_start_idx = 746,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -628,7 +626,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 858,
+ .key_start_idx = 860,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -653,7 +651,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 972,
+ .key_start_idx = 974,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -675,7 +673,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .key_start_idx = 1086,
+ .key_start_idx = 1088,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
@@ -696,7 +694,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1087,
+ .key_start_idx = 1089,
.blob_key_bit_size = 19,
.key_bit_size = 19,
.key_num_fields = 2,
@@ -731,7 +729,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 1089,
+ .key_start_idx = 1091,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -755,7 +753,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1110,
+ .key_start_idx = 1112,
.blob_key_bit_size = 19,
.key_bit_size = 19,
.key_num_fields = 2,
@@ -788,10 +786,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1112,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 1114,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.ident_start_idx = 18,
.ident_nums = 1
},
@@ -823,7 +821,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 1117,
+ .key_start_idx = 1120,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
@@ -847,10 +845,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1138,
- .blob_key_bit_size = 76,
- .key_bit_size = 76,
- .key_num_fields = 5,
+ .key_start_idx = 1141,
+ .blob_key_bit_size = 92,
+ .key_bit_size = 92,
+ .key_num_fields = 6,
.result_start_idx = 422,
.result_bit_size = 62,
.result_num_fields = 4
@@ -880,7 +878,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1143,
+ .key_start_idx = 1147,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -953,7 +951,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1146,
+ .key_start_idx = 1150,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -978,7 +976,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1189,
+ .key_start_idx = 1193,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -998,7 +996,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1192,
+ .key_start_idx = 1196,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1021,7 +1019,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1306,
+ .key_start_idx = 1310,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1075,7 +1073,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1309,
+ .key_start_idx = 1313,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1098,7 +1096,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1352,
+ .key_start_idx = 1356,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1123,7 +1121,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1355,
+ .key_start_idx = 1359,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1145,7 +1143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1469,
+ .key_start_idx = 1473,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1177,7 +1175,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1470,
+ .key_start_idx = 1474,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1250,7 +1248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1473,
+ .key_start_idx = 1477,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1275,7 +1273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1516,
+ .key_start_idx = 1520,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1295,7 +1293,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1519,
+ .key_start_idx = 1523,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1317,7 +1315,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1633,
+ .key_start_idx = 1637,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1371,7 +1369,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1636,
+ .key_start_idx = 1640,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1399,7 +1397,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 1679,
+ .key_start_idx = 1683,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
@@ -1424,7 +1422,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 1722,
+ .key_start_idx = 1726,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -1449,7 +1447,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1725,
+ .key_start_idx = 1729,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1474,7 +1472,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1839,
+ .key_start_idx = 1843,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1499,7 +1497,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 1953,
+ .key_start_idx = 1957,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
@@ -1541,13 +1539,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2067,
+ .key_start_idx = 2071,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
.result_start_idx = 967,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .result_bit_size = 153,
+ .result_num_fields = 6
},
{ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
@@ -1563,7 +1561,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2068,
+ .key_start_idx = 2072,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1600,11 +1598,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2069,
+ .key_start_idx = 2073,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 972,
+ .result_start_idx = 973,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 35,
@@ -1624,11 +1622,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2090,
+ .key_start_idx = 2094,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 978,
+ .result_start_idx = 979,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1645,7 +1643,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 982,
+ .result_start_idx = 983,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1662,7 +1660,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 983,
+ .result_start_idx = 984,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1682,7 +1680,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 984,
+ .result_start_idx = 985,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
@@ -1701,13 +1699,13 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2091,
+ .key_start_idx = 2095,
.blob_key_bit_size = 10,
.key_bit_size = 10,
.key_num_fields = 1,
- .result_start_idx = 1001,
- .result_bit_size = 152,
- .result_num_fields = 5
+ .result_start_idx = 1002,
+ .result_bit_size = 153,
+ .result_num_fields = 6
},
{ /* class_tid: 4, , table: control.egr_0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
@@ -1734,7 +1732,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2092,
+ .key_start_idx = 2096,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1767,7 +1765,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 1006,
+ .result_start_idx = 1008,
.result_bit_size = 64,
.result_num_fields = 8
},
@@ -1785,11 +1783,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2093,
+ .key_start_idx = 2097,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1014,
+ .result_start_idx = 1016,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1807,7 +1805,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2094,
+ .key_start_idx = 2098,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
@@ -1842,11 +1840,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2095,
+ .key_start_idx = 2099,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1018,
+ .result_start_idx = 1020,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 36,
@@ -1866,11 +1864,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2116,
+ .key_start_idx = 2120,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1024,
+ .result_start_idx = 1026,
.result_bit_size = 62,
.result_num_fields = 4
},
@@ -1887,7 +1885,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1028,
+ .result_start_idx = 1030,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -1904,57 +1902,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1029,
+ .result_start_idx = 1031,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 5, , table: int_full_act_record.loopback */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 51,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1030,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
- },
- { /* class_tid: 5, , table: port_table.egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 51,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2117,
- .blob_key_bit_size = 10,
- .key_bit_size = 10,
- .key_num_fields = 1,
- .result_start_idx = 1047,
- .result_bit_size = 152,
- .result_num_fields = 5
- },
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -1965,28 +1921,30 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2118,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
+ .key_start_idx = 2121,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
.ident_start_idx = 37,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.vf_0 */
+ { /* class_tid: 5, , table: control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 3,
+ .cond_false_goto = 6,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 51,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ { /* class_tid: 5, , table: mod_record.vf_2_vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -1994,26 +1952,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
- .fdb_operand = BNXT_ULP_RF_IDX_RID,
- .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
- .pri_operand = 0,
- .key_start_idx = 2119,
- .blob_key_bit_size = 213,
- .key_bit_size = 213,
- .key_num_fields = 21,
- .result_start_idx = 1052,
- .result_bit_size = 43,
- .result_num_fields = 6,
- .ident_start_idx = 37,
- .ident_nums = 1
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1032,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_loopback */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -2021,16 +1972,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
- .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2140,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
- .result_start_idx = 1058,
- .result_bit_size = 62,
- .result_num_fields = 4
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1079,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
},
{ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
@@ -2044,8 +1993,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1062,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1096,
.result_bit_size = 32,
.result_num_fields = 1
},
@@ -2061,52 +2011,37 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST,
.tbl_operand = ULP_THOR_SYM_LOOPBACK_PARIF,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1063,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1097,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* class_tid: 5, , table: int_full_act_record.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_RX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 52,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
- .result_start_idx = 1064,
- .result_bit_size = 128,
- .result_num_fields = 17,
- .encap_num_fields = 0
- },
- { /* class_tid: 5, , table: ilt_tbl.vf_ing */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_ILT,
- .direction = TF_DIR_RX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 52,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1081,
- .result_bit_size = 64,
- .result_num_fields = 8
+ .key_start_idx = 2124,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 1098,
+ .result_bit_size = 138,
+ .result_num_fields = 7
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
.direction = TF_DIR_TX,
@@ -2119,14 +2054,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2141,
+ .key_start_idx = 2127,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .ident_start_idx = 38,
+ .ident_start_idx = 37,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.0 */
+ { /* class_tid: 5, , table: control.vf_2_vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
@@ -2138,9 +2073,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
- .resource_type = TF_IF_TBL_TYPE_ILT,
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
@@ -2148,15 +2083,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 53,
.cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
- .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
- .result_start_idx = 1089,
- .result_bit_size = 64,
- .result_num_fields = 8
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .key_start_idx = 2128,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1105,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 37,
+ .ident_nums = 1
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
@@ -2170,59 +2113,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2142,
+ .key_start_idx = 2149,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1097,
+ .result_start_idx = 1111,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 5, , table: metadata_record.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_METADATA,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 53,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
- .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0,
- .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1101,
- .result_bit_size = 16,
- .result_num_fields = 1
- },
- { /* class_tid: 5, , table: mod_record.vfr_egr */
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
- .direction = TF_DIR_TX,
- .execute_info = {
- .cond_true_goto = 1,
- .cond_false_goto = 1,
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 53,
- .cond_nums = 0 },
- .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
- .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
- .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 1102,
- .result_bit_size = 0,
- .result_num_fields = 0,
- .encap_num_fields = 47
- },
- { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ { /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_ing */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
- .direction = TF_DIR_TX,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
@@ -2232,15 +2136,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1149,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
+ .result_start_idx = 1115,
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_rd */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -2251,26 +2156,75 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2143,
- .blob_key_bit_size = 11,
- .key_bit_size = 11,
- .key_num_fields = 1,
+ .key_start_idx = 2150,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
.ident_start_idx = 38,
.ident_nums = 0
},
- { /* class_tid: 5, , table: control.ing_rd_vfr */
+ { /* class_tid: 5, , table: control.prof_tcam_cache.vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1,
- .cond_false_goto = 5,
+ .cond_false_goto = 10,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 53,
.cond_nums = 1 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
},
- { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ { /* class_tid: 5, , table: int_full_act_record.drop_action */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1132,
+ .result_bit_size = 128,
+ .result_num_fields = 17,
+ .encap_num_fields = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2153,
+ .blob_key_bit_size = 213,
+ .key_bit_size = 213,
+ .key_num_fields = 21,
+ .result_start_idx = 1149,
+ .result_bit_size = 43,
+ .result_num_fields = 6,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
@@ -2288,11 +2242,11 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2144,
+ .key_start_idx = 2174,
.blob_key_bit_size = 213,
.key_bit_size = 213,
.key_num_fields = 21,
- .result_start_idx = 1166,
+ .result_start_idx = 1155,
.result_bit_size = 43,
.result_num_fields = 6,
.ident_start_idx = 38,
@@ -2311,11 +2265,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
- .result_start_idx = 1172,
+ .result_start_idx = 1161,
+ .result_bit_size = 106,
+ .result_num_fields = 106
+ },
+ { /* class_tid: 5, , table: fkb_select.vf_em */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EM_FKB,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
+ .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
+ .result_start_idx = 1267,
.result_bit_size = 106,
.result_num_fields = 106
},
- { /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ { /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.direction = TF_DIR_RX,
@@ -2333,18 +2304,45 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 2165,
+ .key_start_idx = 2195,
.blob_key_bit_size = 94,
.key_bit_size = 94,
.key_num_fields = 43,
- .result_start_idx = 1278,
+ .result_start_idx = 1373,
.result_bit_size = 33,
.result_num_fields = 8
},
- { /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ { /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .pri_opcode = BNXT_ULP_PRI_OPC_CONST,
+ .pri_operand = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2238,
+ .blob_key_bit_size = 94,
+ .key_bit_size = 94,
+ .key_num_fields = 43,
+ .result_start_idx = 1381,
+ .result_bit_size = 33,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
@@ -2355,15 +2353,183 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 2208,
+ .key_start_idx = 2281,
+ .blob_key_bit_size = 14,
+ .key_bit_size = 14,
+ .key_num_fields = 3,
+ .result_start_idx = 1389,
+ .result_bit_size = 138,
+ .result_num_fields = 7
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_ing */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1396,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: em.vf_2_vfr.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_INTERNAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .key_start_idx = 2284,
+ .blob_key_bit_size = 0,
+ .key_bit_size = 0,
+ .key_num_fields = 114,
+ .result_start_idx = 1404,
+ .result_bit_size = 0,
+ .result_num_fields = 6
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 54,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2398,
.blob_key_bit_size = 11,
.key_bit_size = 11,
.key_num_fields = 1,
- .result_start_idx = 1286,
+ .ident_start_idx = 38,
+ .ident_nums = 0
+ },
+ { /* class_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 4,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 54,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID
+ },
+ { /* class_tid: 5, , table: ilt_tbl.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
+ .fdb_operand = BNXT_ULP_RF_IDX_RID,
+ .result_start_idx = 1410,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
+ .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .key_start_idx = 2399,
+ .blob_key_bit_size = 11,
+ .key_bit_size = 11,
+ .key_num_fields = 1,
+ .result_start_idx = 1418,
.result_bit_size = 62,
.result_num_fields = 4
},
- { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ { /* class_tid: 5, , table: ilt_tbl.vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_ILT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD,
+ .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_SVIF,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1422,
+ .result_bit_size = 64,
+ .result_num_fields = 8
+ },
+ { /* class_tid: 5, , table: mod_record.vfr_2_vf_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MODIFY_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 1430,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 47
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 55,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 1477,
+ .result_bit_size = 128,
+ .result_num_fields = 17
+ },
+ { /* class_tid: 5, , table: int_full_act_record.vfr_2_vf.ing0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -2373,17 +2539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 54,
+ .cond_start_idx = 55,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
- .result_start_idx = 1290,
+ .result_start_idx = 1494,
.result_bit_size = 128,
.result_num_fields = 17
},
- { /* class_tid: 5, , table: em.vfr.0 */
+ { /* class_tid: 5, , table: em.vfr_2_vf.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
@@ -2391,15 +2557,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 54,
+ .cond_start_idx = 55,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 2209,
+ .key_start_idx = 2400,
.blob_key_bit_size = 0,
.key_bit_size = 0,
.key_num_fields = 114,
- .result_start_idx = 1307,
+ .result_start_idx = 1511,
.result_bit_size = 0,
.result_num_fields = 6
}
@@ -2585,7 +2751,7 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
/* cond_execute: class_tid: 2, wm.l3_l4.ipv4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
- .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
+ .cond_operand = BNXT_ULP_HDR_BIT_I_IPV4
},
/* cond_execute: class_tid: 3, control.ipv6_check */
{
@@ -2651,17 +2817,22 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.vf_0 */
+ /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr_glb_act_rec_rd.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.0 */
+ /* cond_execute: class_tid: 5, control.vf_2_vfr.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
},
- /* cond_execute: class_tid: 5, control.ing_rd_vfr */
+ /* cond_execute: class_tid: 5, control.prof_tcam_cache.vfr.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
+ /* cond_execute: class_tid: 5, control.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
@@ -2798,6 +2969,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -3198,6 +3383,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: profile_tcam_cache.ipv6_rd */
{
.field_info_mask = {
@@ -3472,30 +3671,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -5809,25 +5991,22 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_mask = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 0xff}
+ (BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_ZERO,
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ (BNXT_ULP_CF_IDX_O_HAS_VTAG >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_HAS_VTAG & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
@@ -6795,30 +6974,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "tl2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "tl2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_TL2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_TL2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -17936,6 +18098,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -18336,6 +18512,20 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: profile_tcam_cache.f2_ipv6_rd */
{
.field_info_mask = {
@@ -18863,8 +19053,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -21143,8 +21348,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_THOR_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -21432,9 +21652,23 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_info_spec = {
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
(BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
}
@@ -23231,30 +23465,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -25548,30 +25765,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -26210,30 +26410,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "l2_vtag_present",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr2 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_YES},
- .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr3 = {
- ULP_THOR_SYM_L2_VTAG_PRESENT_NO}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -31940,25 +32123,108 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: port_table.egr_wr */
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_rd */
{
.field_info_mask = {
- .description = "dev.port_id",
- .field_bit_size = 10,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "dev.port_id",
- .field_bit_size = 10,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
/* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */
@@ -32308,70 +32574,57 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_rd */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ONES,
.field_opr1 = {
- 0xff,
0xff}
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_rd_vfr */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
{
.field_info_mask = {
.description = "etype",
@@ -32559,13 +32812,19 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "metadata",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_MASK >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK & 0xff}
},
.field_info_spec = {
.description = "metadata",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
}
},
{
@@ -32573,19 +32832,13 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.description = "svif",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
.description = "svif",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
@@ -32680,7 +32933,316 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_tpid_sel",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "l2_ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac1_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mac0_addr",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tunnel_id",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "llc",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "roce",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_MASK >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_MASK & 0xff}
+ },
+ .field_info_spec = {
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VF_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VF_META_VAL & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "mpass_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ .field_info_spec = {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ }
+ },
+ /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
{
.field_info_mask = {
.description = "l4_hdr_is_udp_tcp",
@@ -33214,8 +33776,8 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
{
@@ -33292,1474 +33854,4308 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = {
1}
}
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
+ /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
- },
- .field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
- }
- },
- /* class_tid: 5, , table: em.vfr.0 */
- {
- .field_info_mask = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
- }
- },
- {
- .field_info_mask = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "parif",
+ .description = "l4_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "spif",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "svif",
- .field_bit_size = 11,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "lcos",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "ieh",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "meta",
- .field_bit_size = 16,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "meta",
- .field_bit_size = 16,
+ .description = "l3_ipv6_cmp_dst",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "rcyc_cnt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "loopback",
+ .description = "l3_hdr_isIP",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_l2type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_dt",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_sa",
+ .description = "l2_vtag_present",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_nvt",
+ .description = "l2_uc_mc_bc",
.field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovd",
+ .description = "l2_hdr_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ovt",
+ .description = "tun_hdr_flags",
.field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivp",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivd",
+ .description = "tun_hdr_err",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivv",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tun_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_ivt",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_is_udp_tcp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl2_etype",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.l3type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl4_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_dst",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.sip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_ipv6_cmp_src",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_isIP",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip.ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.dip_selcmp.ipv6",
- .field_bit_size = 72,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_error",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ttl",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl3_hdr_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.prot",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_two_vtags",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.fid.ipv4",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_vtag_present",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.fid.ipv6",
- .field_bit_size = 20,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_uc_mc_bc",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.qos",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "tl2_hdr_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_nonext",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_nonext",
+ .description = "tl2_hdr_valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.ieh_esp",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.ieh_auth",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_auth",
+ .description = "hrec_next",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_frag",
+ .description = "agg_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_frag",
+ .description = "agg_error",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "metadata",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_0",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "pkt_type_1",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl3.df",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
.field_info_spec = {
- .description = "tl3.df",
+ .description = "valid",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl3.l3err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tl4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
}
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
{
.field_info_mask = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "recycle_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
{
.field_info_mask = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
.field_info_spec = {
- .description = "tl4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "hdr_sig_id",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
},
+ /* class_tid: 5, , table: em.vf_2_vfr.0 */
{
.field_info_mask = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
},
.field_info_spec = {
- .description = "tl4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
}
},
{
.field_info_mask = {
- .description = "tl4.err",
- .field_bit_size = 4,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tl4.err",
- .field_bit_size = 4,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tuntype",
+ .description = "parif",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "tflags",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- },
- {
- .field_info_mask = {
- .description = "tids",
- .field_bit_size = 24,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tids",
- .field_bit_size = 24,
+ .description = "spif",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
}
},
{
.field_info_mask = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tctxts",
- .field_bit_size = 24,
+ .description = "lcos",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
},
.field_info_spec = {
- .description = "tctxt",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
}
},
{
.field_info_mask = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "tqos",
- .field_bit_size = 3,
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "terr",
- .field_bit_size = 4,
+ .description = "loopback",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_l2type",
+ .description = "tl2_l2type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dmac",
+ .description = "tl2_dmac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_smac",
+ .description = "tl2_smac",
.field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_dt",
+ .description = "tl2_dt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_sa",
+ .description = "tl2_sa",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_nvt",
+ .description = "tl2_nvt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovp",
+ .description = "tl2_ovp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovd",
+ .description = "tl2_ovd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovv",
+ .description = "tl2_ovv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ovt",
+ .description = "tl2_ovt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivp",
+ .description = "tl2_ivp",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivd",
+ .description = "tl2_ivd",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivv",
+ .description = "tl2_ivv",
.field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_ivt",
+ .description = "tl2_ivt",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l2_etype",
+ .description = "tl2_etype",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.l3type",
+ .description = "tl3.l3type",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv4",
+ .description = "tl3.sip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip.ipv6",
+ .description = "tl3.sip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.sip_selcmp.ipv6",
+ .description = "tl3.sip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv4",
+ .description = "tl3.dip.ipv4",
.field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip.ipv6",
+ .description = "tl3.dip.ipv6",
.field_bit_size = 128,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.dip_selcmp.ipv6",
+ .description = "tl3.dip_selcmp.ipv6",
.field_bit_size = 72,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ttl",
+ .description = "tl3.ttl",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.prot",
+ .description = "tl3.prot",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv4",
+ .description = "tl3.fid.ipv4",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.fid.ipv6",
+ .description = "tl3.fid.ipv6",
.field_bit_size = 20,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.qos",
+ .description = "tl3.qos",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_nonext",
+ .description = "tl3.ieh_nonext",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
.field_info_mask = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
.field_info_spec = {
- .description = "l3.ieh_esp",
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SKIP
}
},
{
- .field_info_mask = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_auth",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.rd_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
+ }
+ },
+ /* class_tid: 5, , table: em.vfr_2_vf.0 */
+ {
+ .field_info_mask = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "spif",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "svif",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "lcos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
+ .field_opr1 = {
+ 0xff,
+ 0xff}
+ },
+ .field_info_spec = {
+ .description = "meta",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_VF_META_FID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_META_FID & 0xff}
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "rcyc_cnt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "loopback",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl3.l3err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tl4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tuntype",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tflags",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tids",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxts",
+ .field_bit_size = 24,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tctxt",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "tqos",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "terr",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_l2type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_dt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_sa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_nvt",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ovt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivd",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivv",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_ivt",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l2_etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.sip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip.ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.dip_selcmp.ipv6",
+ .field_bit_size = 72,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ttl",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.prot",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv4",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.fid.ipv6",
+ .field_bit_size = 20,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.qos",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_nonext",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_esp",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_auth",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_dest",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_rthdr",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_hop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.ieh_1frag",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.df",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv4",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l3.l3err.ipv6",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.l4type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.src",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.dst",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.flags",
+ .field_bit_size = 9,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.seq",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.ack",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.win",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.pa",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.opt",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tcpts",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.tsval",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.txecr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ },
+ {
+ .field_info_mask = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ .field_info_spec = {
+ .description = "l4.err",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ }
+ }
+};
+
+struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
+ /* class_tid: 1, , table: l2_cntxt_tcam.0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 1, , table: mac_addr_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "parif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "spif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "lcos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "loopback.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tuntype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tflags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tids.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tctxt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tqos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "terr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ },
+ {
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ },
+ {
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ },
+ {
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ },
+ {
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_dest",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_rthdr",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_hop",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_df.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.ieh_1frag",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.df",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv4",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_src.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l3.l3err.ipv6",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
- .field_info_mask = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.l4type",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.src",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.dst",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.flags",
- .field_bit_size = 9,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_win.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.seq",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.ack",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.win",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.pa",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.opt",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tcpts",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
{
- .field_info_mask = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.tsval",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.txecr",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .field_info_mask = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- .field_info_spec = {
- .description = "l4.err",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- }
- }
-};
-
-struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
- /* class_tid: 1, , table: l2_cntxt_tcam.0 */
- {
- .description = "prof_func_id",
- .field_bit_size = 7,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: mac_addr_cache.wr */
+ /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -34770,27 +38166,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ },
+ /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
+ {
+ .description = "valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35163,10 +38630,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -35225,22 +38691,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -35264,10 +38718,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -35279,10 +38732,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -35300,10 +38752,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -35387,19 +38838,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -35461,166 +38910,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l2_l3_l4_v6_em */
- {
- .description = "wc_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_type",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "em_key_id",
- .field_bit_size = 6,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_search_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
- {
- .description = "em_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
- },
- {
- .description = "em_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "wc_key_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: em.l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
- },
- {
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "opcode",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "meta_prof",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
- /* class_tid: 1, , table: fkb_select.l3_l4_wm */
+ /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -35747,7 +39037,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl2_ivt.en",
@@ -35771,7 +39063,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_sip_selcmp.en",
@@ -35783,7 +39077,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_dip_selcmp.en",
@@ -35801,7 +39097,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl3_fid.en",
@@ -35885,13 +39183,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "tl4_flags.en",
@@ -36055,9 +39357,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -36081,9 +39381,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_sip_selcmp.en",
@@ -36095,9 +39393,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_dip_selcmp.en",
@@ -36115,9 +39411,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_fid.en",
@@ -36201,17 +39495,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l4_flags.en",
@@ -36256,1160 +39546,1334 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l4_err.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 1, , table: profile_tcam_cache.wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: fkb_select.l3_l4_wm_vxlan */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv4 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "tl2_dt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l2 */
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.1 */
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_df.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: tunnel_cache.wr */
{
- .description = "tl3_l3err.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_l4type.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
+ /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
},
+ /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
{
- .description = "tid.en",
+ .description = "l2_cntxt_id.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tctxts.en",
+ .description = "parif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxt.en",
+ .description = "spif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tqos.en",
+ .description = "svif.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "terr.en",
+ .description = "lcos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
+ .description = "rcyc_cnt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
+ .description = "loopback.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dt.en",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "tl2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "tl2_dt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "tl2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "tl2_ovv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "tl2_ovt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "tl2_ivp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "tl2_ivd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
+ .description = "tl3_l3type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_selcmp.en",
+ .description = "tl3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
+ .description = "tl3_sip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
+ .description = "tl3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
+ .description = "tl3_dip_selcmp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_qos.en",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_esp.en",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_auth.en",
+ .description = "tl3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_dest.en",
+ .description = "tl3_ieh_nonext.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_frag.en",
+ .description = "tl3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_hop.en",
+ .description = "tl3_ieh_dest.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_df.en",
+ .description = "tl3_ieh_rthdr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3err.en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dst.en",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
+ .description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "tl4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
+ .description = "tl4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "tl4_opt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
+ .description = "tl4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_0 & 0xff}
- },
- {
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
+ .description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "tid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "tqos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "terr.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam.l3_l4.vxlan */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_2 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_3 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_2 & 0xff}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
},
{
- .description = "wc_search_en",
+ .description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
+ .description = "l2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
+ .description = "l2_ovd.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: profile_tcam_cache.wr */
- {
- .description = "rid",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
- },
- {
- .description = "profile_tcam_index",
- .field_bit_size = 10,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
- },
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
- },
- /* class_tid: 1, , table: wm.l3_l4.ipv4 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
},
- /* class_tid: 1, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 1, , table: wm.l3_l4.vxlan.ipv6 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: l2_cntxt_tcam.1 */
+ /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_search_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: tunnel_cache.wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -37420,103 +40884,98 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
+ .description = "profile_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
- /* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
+ /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ 3}
},
- /* class_tid: 2, , table: mac_addr_cache.wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: fkb_select.f2_l2_l3_l4_v6_em */
+ /* class_tid: 2, , table: fkb_select.f2_wm */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -37841,10 +41300,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff}
+ 1}
},
{
.description = "tid.en",
@@ -37886,19 +41344,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff}
+ 1}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -37982,10 +41438,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -37997,10 +41452,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -38018,10 +41472,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -38105,19 +41558,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -38179,24 +41630,46 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.f2_l2_l3_l4_v6_em */
+ /* class_tid: 2, , table: profile_tcam.f2 */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr3 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "em_key_type",
@@ -38208,27 +41681,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "pl_byp_lkup_en",
@@ -38236,7 +41701,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_l2_l3_l4_v6_wr */
+ /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -38259,19 +41724,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
@@ -38294,31 +41753,18 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: em.f2_l2_l3_l4_v6.0 */
- {
- .description = "valid",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
- },
+ /* class_tid: 2, , table: wm.l3_l4.ipv4 */
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 3}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "opcode",
@@ -38327,18 +41773,23 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
- /* class_tid: 2, , table: fkb_select.f2_wm */
+ /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -38663,9 +42114,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tid.en",
@@ -38707,17 +42156,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
},
{
.description = "l2_dt.en",
@@ -38776,8 +42227,22 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_opr2 = {
+ (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
+ .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l2_ivt.en",
@@ -38801,9 +42266,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
},
{
.description = "l3_sip_selcmp.en",
@@ -38815,9 +42281,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
},
{
.description = "l3_dip_selcmp.en",
@@ -38835,9 +42302,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
},
{
.description = "l3_fid.en",
@@ -38921,17 +42389,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
},
{
.description = "l4_flags.en",
@@ -38993,46 +42463,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam.f2 */
+ /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_4 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
- .field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV6 & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr2 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_5 & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr3 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_4 & 0xff}
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_type",
@@ -39044,19 +42492,27 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "pl_byp_lkup_en",
@@ -39064,7 +42520,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 2, , table: profile_tcam_cache.f2_wr */
+ /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -39087,13 +42543,19 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
},
{
.description = "wc_profile_id",
@@ -39116,24 +42578,22 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 2, , table: wm.l3_l4.ipv4 */
- {
- .description = "ctxt_data",
- .field_bit_size = 14,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
- },
+ /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "valid",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
.description = "data",
@@ -39145,14 +42605,24 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: fkb_select.l2_l3_l4_v6_em */
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
.description = "l2_cntxt_id.en",
.field_bit_size = 1,
@@ -39519,19 +42989,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l2_dmac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
+ 1}
},
{
.description = "l2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
+ 1}
},
{
.description = "l2_dt.en",
@@ -39590,22 +43058,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
{
.description = "l2_ivv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
- .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff},
- .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
- .field_opr2 = {
- (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff},
- .field_src3 = BNXT_ULP_FIELD_SRC_ZERO
+ 1}
},
{
.description = "l2_ivt.en",
@@ -39629,10 +43085,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_sip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff}
+ 1}
},
{
.description = "l3_sip_selcmp.en",
@@ -39644,10 +43099,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff}
+ 1}
},
{
.description = "l3_dip_selcmp.en",
@@ -39665,10 +43119,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID & 0xff}
+ 1}
},
{
.description = "l3_fid.en",
@@ -39752,19 +43205,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT & 0xff}
+ 1}
},
{
.description = "l4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_L4_FB_DST_PORT & 0xff}
+ 1}
},
{
.description = "l4_flags.en",
@@ -39826,24 +43277,32 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l2_l3_l4_v6_em */
+ /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
.description = "wc_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
},
{
.description = "wc_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
},
{
.description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "em_key_type",
@@ -39855,35 +43314,84 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_key_id",
.field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "pl_byp_lkup_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
+ {
+ .description = "wc_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ },
+ {
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ },
+ {
+ .description = "wc_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
{
+ .description = "em_key_type",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_key_id",
+ .field_bit_size = 6,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_profile_id",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "em_search_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
.description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam_cache.l2_l3_l4_v6_wr */
+ /* class_tid: 3, , table: profile_tcam_cache.wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -39906,19 +43414,13 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "em_profile_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "em_key_id",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_EM_KEY_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "wc_profile_id",
@@ -39941,14 +43443,33 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
},
- /* class_tid: 3, , table: em.l2_l3_l4_v6.0 */
+ /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .description = "valid",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
.description = "strength",
@@ -39956,7 +43477,26 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 3}
+ 1}
+ },
+ /* class_tid: 3, , table: wm.l3.ipv4 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meta_prof",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "data",
@@ -39968,8 +43508,17 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "strength",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 3, , table: wm.l2 */
+ {
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -39980,384 +43529,625 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: fkb_select.l3_l4_wc */
{
- .description = "l2_cntxt_id.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ },
+ {
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
+ /* class_tid: 4, , table: int_full_act_record.0 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "loopback.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_l2type.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dmac.en",
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ },
+ {
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovp.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovd.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 4, , table: port_table.ing_wr_0 */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovv.en",
- .field_bit_size = 1,
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "phy_port",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
+ .description = "port_is_pf",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .description = "prof_func_id",
+ .field_bit_size = 7,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ },
+ {
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ {
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ },
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ {
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ },
+ {
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ },
+ {
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
+ {
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ },
+ /* class_tid: 4, , table: int_full_act_record.egr_0 */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rsvd0",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 5,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "stats_op",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
},
{
- .description = "tl3_sip.en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_prot.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
+ /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .description = "tl3_qos.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "drv_func.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "drv_func.parent.mac",
+ .field_bit_size = 48,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "phy_port",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_dest.en",
+ .description = "port_is_pf",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "default_arec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tl3_df.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl4_l4type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tflags.en",
- .field_bit_size = 1,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "tids.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "tid.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
+ /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "tqos.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "terr.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "l2_l2type.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "l2_dmac.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
+ /* class_tid: 5, , table: mod_record.vf_2_vfr_egr */
{
- .description = "l2_smac.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -40365,317 +44155,403 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "l2_dt.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_l3type.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ (ULP_THOR_SYM_VF_2_VFR_META_VAL >> 8) & 0xff,
+ ULP_THOR_SYM_VF_2_VFR_META_VAL & 0xff}
},
{
- .description = "l3_dip_selcmp.en",
- .field_bit_size = 1,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_ttl.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_prot.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_fid.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_qos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_esp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_auth.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_dest.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_frag.en",
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_rthdr.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_hop.en",
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_df.en",
+ .description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_l3err.en",
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ {
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_loopback */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_MODIFY_PTR & 0xff}
},
{
- .description = "l4_dst.en",
- .field_bit_size = 1,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_flags.en",
- .field_bit_size = 1,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_seq.en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_ack.en",
- .field_bit_size = 1,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_win.en",
+ .description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ {
+ .description = "stats_ptr",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_pa.en",
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ },
+ {
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tcpts.en",
+ .description = "cond_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
+ .description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l3_l4.ip */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ 1}
},
+ /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_glb_act_rec_wr */
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
@@ -40686,75 +44562,80 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: profile_tcam.l3_l4.nonip */
{
.description = "wc_key_id",
- .field_bit_size = 6,
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_KEY_ID_1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_WC_PROFILE_ID_1 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "pl_byp_lkup_en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
- /* class_tid: 3, , table: profile_tcam_cache.wr */
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
.description = "rid",
.field_bit_size = 32,
@@ -40765,156 +44646,140 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "profile_tcam_index",
+ .description = "l2_cntxt_tcam_index",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
{
- .description = "em_key_id",
- .field_bit_size = 8,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: int_full_act_record.vf_2_vfr_ing */
{
- .description = "wc_profile_id",
- .field_bit_size = 8,
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_key_id",
- .field_bit_size = 8,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "flow_sig_id",
- .field_bit_size = 64,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: wm.l3_l4.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "rsvd0",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 3, , table: wm.l3.ipv4 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "use_default",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
- },
- {
- .description = "strength",
- .field_bit_size = 2,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 3, , table: wm.l2 */
{
- .description = "ctxt_data",
- .field_bit_size = 14,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta_prof",
- .field_bit_size = 3,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "opcode",
- .field_bit_size = 3,
+ .description = "drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "data",
- .field_bit_size = 16,
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "strength",
- .field_bit_size = 2,
+ .description = "type",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: int_full_act_record.0 */
+ /* class_tid: 5, , table: int_full_act_record.drop_action */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -40975,10 +44840,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "use_default",
@@ -41008,7 +44870,9 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
.description = "hit",
@@ -41024,49 +44888,66 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 4, , table: port_table.ing_wr_0 */
+ /* class_tid: 5, , table: l2_cntxt_tcam.vf_2_vfr_ing.0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "prof_func_id",
+ .field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_VF_2_VFR_PROF_FUNC_ID & 0xff}
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "ctxt_meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "def_ctxt_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "ctxt_opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */
+ {
+ .description = "parif",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ },
+ /* class_tid: 5, , table: l2_cntxt_tcam.vfr_2_vf_ing.0 */
{
.description = "prof_func_id",
.field_bit_size = 7,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_ANY_2_VF_PROF_FUNC_ID & 0xff}
},
{
.description = "ctxt_meta_prof",
@@ -41078,10 +44959,10 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.description = "def_ctxt_data",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
.description = "ctxt_opcode",
@@ -41097,8 +44978,8 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ (BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_L2_CNTXT_ID_1 & 0xff}
},
{
.description = "parif",
@@ -41106,692 +44987,683 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */
+ /* class_tid: 5, , table: fkb_select.vfr_em */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "svif.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ 1}
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "meta.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ 1}
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: int_full_act_record.egr_0 */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "tl2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "tl2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "tl2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "tl2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "tl2_ovp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
- BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl3_ieh_frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: port_table.egr_wr_0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "tl4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "tl4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "tl4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: ilt_tbl.egr_vfr */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tl4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tl4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tflags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tids.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "terr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l2_smac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "l2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l2_ivp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.loopback */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_dip.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l3_qos.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_ieh_esp.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l3_ieh_auth.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: port_table.egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.mac",
- .field_bit_size = 48,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drv_func.parent.mac",
- .field_bit_size = 48,
+ .description = "l3_ieh_hop.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC >> 8) & 0xff,
- BNXT_ULP_RF_IDX_DRV_FUNC_PARENT_MAC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "phy_port",
- .field_bit_size = 8,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "default_arec_ptr",
- .field_bit_size = 16,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l3_l3err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l4_src.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_flags.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l4_seq.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_LOOPBACK_PARIF}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */
{
- .description = "act_rec_ptr",
- .field_bit_size = 32,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vf_ing */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l4_err.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: fkb_select.vf_em */
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l2_cntxt_id.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "parif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "spif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "svif.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "lcos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "meta.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
@@ -41799,1359 +45671,1380 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
1}
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "rcyc_cnt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "loopback.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "tl2_l2type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "tl2_dmac.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "tl2_smac.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "tl2_dt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "tl2_sa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "tl2_nvt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "tl2_ovp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: ilt_tbl.vf_ing */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl2_ovd.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl2_ovv.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tl2_ovt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tl2_ivp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl2_ivv.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tl2_ivt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tl2_etype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_l3type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tl3_sip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "ilt_destination",
- .field_bit_size = 16,
+ .description = "tl3_sip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "act_rec_ptr",
- .field_bit_size = 16,
+ .description = "tl3_dip.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "fwd_op",
- .field_bit_size = 2,
+ .description = "tl3_dip_selcmp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_ilt_dest",
+ .description = "tl3_ttl.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_action",
+ .description = "tl3_prot.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "en_bd_meta",
+ .description = "tl3_fid.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "tl3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 23,
+ .description = "tl3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "tl3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "tl3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "tl3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "tl3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: metadata_record.vfr_egr */
{
- .description = "prof_meta_mask",
- .field_bit_size = 16,
+ .description = "tl3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ONES,
- .field_opr1 = {
- 0xff,
- 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: mod_record.vfr_egr */
{
- .description = "metadata_en",
+ .description = "tl3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rem_ovlan",
+ .description = "tl3_ieh_1frag.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rem_ivlan",
+ .description = "tl3_df.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rep_add_ivlan",
+ .description = "tl3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rep_add_ovlan",
+ .description = "tl4_l4type.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_update",
+ .description = "tl4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_md_en",
+ .description = "tl4_dst.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved_en",
+ .description = "tl4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac_en",
+ .description = "tl4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac_en",
+ .description = "tl4_pa.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv6_en",
+ .description = "tl4_opt.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6_en",
+ .description = "tl4_tcpts.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4_en",
+ .description = "tl4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4_en",
+ .description = "tuntype.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport_en",
+ .description = "tflags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dport_en",
+ .description = "tids.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_data",
- .field_bit_size = 16,
+ .description = "tid.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_rsvd",
- .field_bit_size = 10,
+ .description = "tctxts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_op",
- .field_bit_size = 2,
+ .description = "tctxt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "metadata_prof",
- .field_bit_size = 4,
+ .description = "tqos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_METADATA_PROF_0 & 0xff}
- },
- {
- .description = "ivlan_tpid",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ivlan_de",
+ .description = "terr.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
- },
- {
- .description = "ivlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_tpid",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_l2type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_pri",
- .field_bit_size = 3,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_dmac.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_de",
+ .description = "l2_smac.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ovlan_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_dt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_pfid",
- .field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_sa.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "alt_vid",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_nvt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_rsvd",
- .field_bit_size = 12,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ovp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_dec",
+ .description = "l2_ovd.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_il3_dec",
+ .description = "l2_ovv.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_tl3_rdir",
+ .description = "l2_ovt.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ttl_il3_rdir",
+ .description = "l2_ivp.en",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_new_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivd.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_ex_prot",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivv.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tun_mv",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_ivt.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "reserved",
- .field_bit_size = 0,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l2_etype.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_l3type.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac",
- .field_bit_size = 48,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_sip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_sip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv6",
- .field_bit_size = 128,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_dip.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_dip_selcmp.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip_ipv4",
- .field_bit_size = 32,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_ttl.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_sport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_prot.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_dport",
- .field_bit_size = 16,
- .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ .description = "l3_fid.en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vfr_egr */
{
- .description = "sp_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_qos.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "encap_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_nonext.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mod_rec_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_esp.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
- BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd1",
- .field_bit_size = 16,
+ .description = "l3_ieh_auth.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "rsvd0",
- .field_bit_size = 8,
+ .description = "l3_ieh_dest.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "decap_func",
- .field_bit_size = 5,
+ .description = "l3_ieh_frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 10,
+ .description = "l3_ieh_rthdr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_op",
+ .description = "l3_ieh_hop.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "stats_ptr",
- .field_bit_size = 16,
+ .description = "l3_ieh_1frag.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 11,
+ .description = "l3_df.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
- ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "use_default",
+ .description = "l3_l3err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 4,
+ .description = "l4_l4type.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "cond_copy",
+ .description = "l4_src.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vlan_del_rpt",
- .field_bit_size = 2,
+ .description = "l4_dst.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l4_flags.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "hit",
+ .description = "l4_seq.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "type",
- .field_bit_size = 3,
+ .description = "l4_ack.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- 1}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam.vfr_ing0 */
{
- .description = "prof_func_id",
- .field_bit_size = 7,
+ .description = "l4_win.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_PROF_FUNC_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_meta_prof",
- .field_bit_size = 3,
+ .description = "l4_pa.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "def_ctxt_data",
- .field_bit_size = 16,
+ .description = "l4_opt.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ctxt_opcode",
- .field_bit_size = 3,
+ .description = "l4_tcpts.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_THOR_SYM_CTXT_OPCODE_NORMAL_FLOW}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "l4_tsval.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "parif",
- .field_bit_size = 4,
+ .description = "l4_txecr.en",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CF,
- .field_opr1 = {
- (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
- BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: fkb_select.vfr_em */
{
- .description = "l2_cntxt_id.en",
+ .description = "l4_err.en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vf_2_vfr.0 */
{
- .description = "parif.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "spif.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "svif.en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "lcos.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meta.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
.field_opr1 = {
- 1}
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
},
{
- .description = "rcyc_cnt.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
},
{
- .description = "loopback.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl2_l2type.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam.vfr_2_vf.0 */
{
- .description = "tl2_dmac.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_smac.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_dt.en",
+ .description = "wc_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_sa.en",
- .field_bit_size = 1,
+ .description = "em_key_type",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_nvt.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 6,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_1 & 0xff}
},
{
- .description = "tl2_ovp.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_1 & 0xff}
},
{
- .description = "tl2_ovd.en",
+ .description = "em_search_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl2_ovv.en",
+ .description = "pl_byp_lkup_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: profile_tcam_cache.vfr_wr */
{
- .description = "tl2_ovt.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
+ },
+ {
+ .description = "profile_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivp.en",
- .field_bit_size = 1,
+ .description = "em_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivd.en",
- .field_bit_size = 1,
+ .description = "em_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivv.en",
- .field_bit_size = 1,
+ .description = "wc_profile_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_ivt.en",
- .field_bit_size = 1,
+ .description = "wc_key_id",
+ .field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl2_etype.en",
- .field_bit_size = 1,
+ .description = "flow_sig_id",
+ .field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_ing */
{
- .description = "tl3_l3type.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_sip.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_DROP_AREC_PTR & 0xff}
},
{
- .description = "tl3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW}
},
{
- .description = "tl3_dip.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_dip_selcmp.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ttl.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_prot.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_fid.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: em.vf_2_vfr.0 */
{
- .description = "tl3_qos.en",
+ .description = "valid",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl3_ieh_nonext.en",
- .field_bit_size = 1,
+ .description = "strength",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 3}
},
{
- .description = "tl3_ieh_esp.en",
- .field_bit_size = 1,
+ .description = "data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
},
{
- .description = "tl3_ieh_auth.en",
- .field_bit_size = 1,
+ .description = "opcode",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_dest.en",
- .field_bit_size = 1,
+ .description = "meta_prof",
+ .field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_frag.en",
- .field_bit_size = 1,
+ .description = "ctxt_data",
+ .field_bit_size = 14,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vfr_egr */
{
- .description = "tl3_ieh_rthdr.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_hop.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_ieh_1frag.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_BYPASS_LKUP}
},
{
- .description = "tl3_df.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl3_l3err.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "tl4_l4type.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_src.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
},
{
- .description = "tl4_dst.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */
{
- .description = "tl4_flags.en",
- .field_bit_size = 1,
+ .description = "rid",
+ .field_bit_size = 32,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RID & 0xff}
},
{
- .description = "tl4_seq.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_tcam_index",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_pa.en",
- .field_bit_size = 1,
+ .description = "l2_cntxt_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_opt.en",
- .field_bit_size = 1,
+ .description = "src_property_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: ilt_tbl.vf_egr */
{
- .description = "tl4_tcpts.en",
- .field_bit_size = 1,
+ .description = "ilt_destination",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tl4_err.en",
- .field_bit_size = 1,
+ .description = "act_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_opr1 = {
+ (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
},
{
- .description = "tuntype.en",
- .field_bit_size = 1,
+ .description = "fwd_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_FWD_OP_NORMAL_FLOW}
},
{
- .description = "tflags.en",
+ .description = "en_ilt_dest",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tids.en",
+ .description = "en_bd_action",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tid.en",
+ .description = "en_bd_meta",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "tctxts.en",
- .field_bit_size = 1,
+ .description = "parif",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_THOR_SYM_LOOPBACK_PARIF}
},
{
- .description = "tctxt.en",
- .field_bit_size = 1,
+ .description = "reserved",
+ .field_bit_size = 23,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
+ /* class_tid: 5, , table: mod_record.vfr_2_vf_egr */
{
- .description = "tqos.en",
+ .description = "metadata_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
},
{
- .description = "terr.en",
+ .description = "rem_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_l2type.en",
+ .description = "rem_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dmac.en",
+ .description = "rep_add_ivlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_smac.en",
+ .description = "rep_add_ovlan",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_dt.en",
+ .description = "ttl_update",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_sa.en",
+ .description = "tun_md_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_nvt.en",
+ .description = "reserved_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovp.en",
+ .description = "l2_dmac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovd.en",
+ .description = "l2_smac_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovv.en",
+ .description = "l3_sip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ovt.en",
+ .description = "l3_dip_ipv6_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivp.en",
+ .description = "l3_sip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivd.en",
+ .description = "l3_dip_ipv4_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivv.en",
+ .description = "l4_sport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_ivt.en",
+ .description = "l4_dport_en",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_etype.en",
- .field_bit_size = 1,
+ .description = "metadata_data",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_PORT_TABLE,
+ .field_opr1 = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
+ (BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA >> 8) & 0xff,
+ BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA & 0xff}
},
{
- .description = "l3_l3type.en",
- .field_bit_size = 1,
+ .description = "metadata_rsvd",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip.en",
- .field_bit_size = 1,
+ .description = "metadata_op",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_sip_selcmp.en",
- .field_bit_size = 1,
+ .description = "metadata_prof",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l3_dip.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_dip_selcmp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ttl.en",
+ .description = "ivlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_prot.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ivlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_fid.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_qos.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_pri",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_nonext.en",
+ .description = "ovlan_de",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_esp.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ovlan_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_auth.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "alt_pfid",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_dest.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "alt_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_frag.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "ttl_rsvd",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_rthdr.en",
+ .description = "ttl_tl3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_hop.en",
+ .description = "ttl_il3_dec",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_ieh_1frag.en",
+ .description = "ttl_tl3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_df.en",
+ .description = "ttl_il3_rdir",
.field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l3_l3err.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_new_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_l4type.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_ex_prot",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_src.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "tun_mv",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_dst.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "reserved",
+ .field_bit_size = 0,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_flags.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_dmac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_seq.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l2_smac",
+ .field_bit_size = 48,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_ack.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_win.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv6",
+ .field_bit_size = 128,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_pa.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_sip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_opt.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l3_dip_ipv4",
+ .field_bit_size = 32,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_tcpts.en",
- .field_bit_size = 1,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .description = "l4_sport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
},
{
- .description = "l4_tsval.en",
- .field_bit_size = 1,
+ .description = "l4_dport",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SKIP
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_egr */
+ {
+ .description = "sp_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_txecr.en",
- .field_bit_size = 1,
+ .description = "encap_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l4_err.en",
- .field_bit_size = 1,
+ .description = "mod_rec_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_MODIFY_PTR >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_MODIFY_PTR & 0xff}
},
- /* class_tid: 5, , table: profile_tcam.vfr_ing0 */
{
- .description = "wc_key_id",
- .field_bit_size = 6,
+ .description = "rsvd1",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_profile_id",
+ .description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "wc_search_en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_type",
- .field_bit_size = 2,
+ .description = "meter",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_key_id",
- .field_bit_size = 6,
+ .description = "stats_op",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_KEY_ID_0 & 0xff}
+ 1}
},
{
- .description = "em_profile_id",
- .field_bit_size = 8,
+ .description = "stats_ptr",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
- .field_opr1 = {
- (BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 >> 8) & 0xff,
- BNXT_ULP_GLB_RF_IDX_GLB_VFR_EM_PROF_ID_0 & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "em_search_en",
- .field_bit_size = 1,
+ .description = "vnic_or_vport",
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
- 1}
+ (ULP_THOR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+ ULP_THOR_SYM_LOOPBACK_PORT & 0xff}
},
{
- .description = "pl_byp_lkup_en",
+ .description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: l2_cntxt_tcam_cache.ing_wr_vfr */
{
- .description = "rid",
- .field_bit_size = 32,
+ .description = "mirror",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_RF,
- .field_opr1 = {
- (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
- BNXT_ULP_RF_IDX_RID & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_tcam_index",
- .field_bit_size = 10,
+ .description = "cond_copy",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "l2_cntxt_id",
- .field_bit_size = 10,
+ .description = "vlan_del_rpt",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "src_property_ptr",
- .field_bit_size = 10,
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */
+ {
+ .description = "type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 1}
+ },
+ /* class_tid: 5, , table: int_full_act_record.vfr_2_vf.ing0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
@@ -43261,7 +47154,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = {
.field_opr1 = {
1}
},
- /* class_tid: 5, , table: em.vfr.0 */
+ /* class_tid: 5, , table: em.vfr_2_vf.0 */
{
.description = "valid",
.field_bit_size = 1,
@@ -43313,7 +47206,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.description = "default_arec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.ident_bit_size = 16,
- .ident_bit_pos = 136
+ .ident_bit_pos = 137
},
{
.description = "drv_func.parent.mac",
@@ -43402,7 +47295,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
.description = "default_arec_ptr",
.regfile_idx = BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR,
.ident_bit_size = 16,
- .ident_bit_pos = 136
+ .ident_bit_pos = 137
},
{
.description = "drv_func.parent.mac",
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index 16a921e6c8..2a499c0ba2 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -20,7 +18,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 0,
- .cond_nums = 9 }
+ .cond_nums = 12 }
},
/* act_tid: 2, ingress */
[2] = {
@@ -29,7 +27,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.start_tbl_idx = 5,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 }
},
/* act_tid: 3, ingress */
@@ -38,39 +36,69 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
.num_tbls = 7,
.start_tbl_idx = 12,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 15,
- .cond_nums = 0 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 18,
+ .cond_nums = 3 }
},
- /* act_tid: 4, egress */
+ /* act_tid: 4, ingress */
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
.start_tbl_idx = 19,
.reject_info = {
- .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 21,
- .cond_nums = 0 }
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 29,
+ .cond_nums = 1 }
},
- /* act_tid: 5, egress */
+ /* act_tid: 5, ingress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 7,
+ .num_tbls = 1,
.start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 29,
+ .cond_start_idx = 35,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 6,
- .start_tbl_idx = 31,
+ .num_tbls = 5,
+ .start_tbl_idx = 25,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 35,
.cond_nums = 0 }
+ },
+ /* act_tid: 7, egress */
+ [7] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 7,
+ .start_tbl_idx = 30,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 43,
+ .cond_nums = 3 }
+ },
+ /* act_tid: 8, egress */
+ [8] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 6,
+ .start_tbl_idx = 37,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 54,
+ .cond_nums = 3 }
+ },
+ /* act_tid: 9, egress */
+ [9] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 3,
+ .start_tbl_idx = 43,
+ .reject_info = {
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
+ .cond_start_idx = 63,
+ .cond_nums = 0 }
}
};
@@ -85,7 +113,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 9,
+ .cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -107,7 +135,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 10,
+ .cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -127,7 +155,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 11,
+ .cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@@ -149,7 +177,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 12,
+ .cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -170,7 +198,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 13,
+ .cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -188,7 +216,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 },
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
@@ -203,7 +231,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
@@ -224,7 +252,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 14,
+ .cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -245,7 +273,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -267,7 +295,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -289,7 +317,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MIRROR_PTR_0,
@@ -309,7 +337,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 15,
+ .cond_start_idx = 18,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
@@ -329,8 +357,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
- .cond_nums = 1 },
+ .cond_start_idx = 21,
+ .cond_nums = 3 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
@@ -343,7 +371,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 24,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -362,7 +390,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 17,
+ .cond_start_idx = 25,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@@ -381,7 +409,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 26,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@@ -390,7 +418,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 3, , table: int_encap_mac_record.0 */
+ { /* act_tid: 3, , table: int_encap_vlan_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -400,7 +428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 19,
+ .cond_start_idx = 27,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -421,7 +449,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 19,
+ .cond_start_idx = 27,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -440,7 +468,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 20,
+ .cond_start_idx = 28,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -455,21 +483,130 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 21,
+ .cond_start_idx = 30,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 230,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ { /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 31,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 231,
+ .result_bit_size = 0,
+ .result_num_fields = 0
+ },
+ { /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 32,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_RSS_VNIC,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 231,
+ .result_bit_size = 0,
+ .result_num_fields = 0
+ },
+ { /* act_tid: 4, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+ .cond_start_idx = 33,
+ .cond_nums = 2 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 231,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 4, , table: int_full_act_record.1 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 35,
+ .cond_nums = 0 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
+ .result_start_idx = 257,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0
+ },
+ { /* act_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 35,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 35,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 283,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 6, , table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -479,18 +616,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 22,
+ .cond_start_idx = 36,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 8,
- .result_start_idx = 231,
+ .result_start_idx = 284,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* act_tid: 4, , table: int_full_act_record.0 */
+ { /* act_tid: 6, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -500,16 +637,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 24,
+ .cond_start_idx = 38,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 242,
+ .result_start_idx = 295,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 4, , table: ext_full_act_record.no_tag */
+ { /* act_tid: 6, , table: ext_full_act_record.no_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -519,17 +656,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 25,
+ .cond_start_idx = 39,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 268,
+ .result_start_idx = 321,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 4, , table: ext_full_act_record.one_tag */
+ { /* act_tid: 6, , table: ext_full_act_record.one_tag */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -539,28 +676,28 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 27,
+ .cond_start_idx = 41,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 305,
+ .result_start_idx = 358,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 5, , table: control.0 */
+ { /* act_tid: 7, , table: control.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
.direction = TF_DIR_TX,
.execute_info = {
.cond_true_goto = 1023,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
- .cond_nums = 1 },
+ .cond_start_idx = 46,
+ .cond_nums = 3 },
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP
},
- { /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ { /* act_tid: 7, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
@@ -570,16 +707,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
+ .cond_start_idx = 49,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 342,
+ .result_start_idx = 395,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: act_modify_ipv4_src.0 */
+ { /* act_tid: 7, , table: act_modify_ipv4_src.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.resource_sub_type =
@@ -589,16 +726,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 31,
+ .cond_start_idx = 50,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 343,
+ .result_start_idx = 396,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: act_modify_ipv4_dst.0 */
+ { /* act_tid: 7, , table: act_modify_ipv4_dst.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4,
.resource_sub_type =
@@ -608,16 +745,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 51,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 344,
+ .result_start_idx = 397,
.result_bit_size = 32,
.result_num_fields = 1
},
- { /* act_tid: 5, , table: int_encap_mac_record.dummy */
+ { /* act_tid: 7, , table: int_encap_vlan_record.dummy */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
@@ -627,18 +764,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 33,
+ .cond_start_idx = 52,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.record_size = 16,
- .result_start_idx = 345,
+ .result_start_idx = 398,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 11
},
- { /* act_tid: 5, , table: int_full_act_record.0 */
+ { /* act_tid: 7, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -648,16 +785,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 52,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 356,
+ .result_start_idx = 409,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 5, , table: ext_full_act_record.0 */
+ { /* act_tid: 7, , table: ext_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -667,17 +804,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 53,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 382,
+ .result_start_idx = 435,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 11
},
- { /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ { /* act_tid: 8, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
@@ -687,16 +824,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 57,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 419,
+ .result_start_idx = 472,
.result_bit_size = 64,
.result_num_fields = 1
},
- { /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ { /* act_tid: 8, , table: sp_smac_ipv4.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
.resource_sub_type =
@@ -706,18 +843,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 58,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 16,
- .result_start_idx = 420,
+ .result_start_idx = 473,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 2
},
- { /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ { /* act_tid: 8, , table: sp_smac_ipv6.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
.resource_sub_type =
@@ -727,18 +864,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 59,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 24,
- .result_start_idx = 422,
+ .result_start_idx = 475,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 2
},
- { /* act_tid: 6, , table: int_tun_encap_record.0 */
+ { /* act_tid: 8, , table: int_tun_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
.resource_sub_type =
@@ -748,18 +885,18 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 60,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.record_size = 64,
- .result_start_idx = 424,
+ .result_start_idx = 477,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 30
},
- { /* act_tid: 6, , table: int_full_act_record.0 */
+ { /* act_tid: 8, , table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
@@ -769,16 +906,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 39,
+ .cond_start_idx = 61,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 454,
+ .result_start_idx = 507,
.result_bit_size = 128,
.result_num_fields = 26
},
- { /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */
+ { /* act_tid: 8, , table: ext_full_act_record_vxlan.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
@@ -788,15 +925,64 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 40,
+ .cond_start_idx = 62,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .result_start_idx = 480,
+ .result_start_idx = 533,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 30
+ },
+ { /* act_tid: 9, , table: control.reject */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1023,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+ .cond_start_idx = 63,
+ .cond_nums = 0 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
+ { /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 63,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 589,
+ .result_bit_size = 64,
+ .result_num_fields = 1
+ },
+ { /* act_tid: 9, , table: int_full_act_record.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 0,
+ .cond_false_goto = 0,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 64,
+ .cond_nums = 1 },
+ .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
+ .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
+ .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
+ .result_start_idx = 590,
+ .result_bit_size = 128,
+ .result_num_fields = 26
}
};
@@ -838,6 +1024,18 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_VLAN_PCP
},
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_METER
+ },
/* cond_execute: act_tid: 1, shared_mirror_record.rd */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -866,10 +1064,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_reject: wh_plus, act_tid: 3 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
/* cond_execute: act_tid: 3, control.0 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
},
/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
{
@@ -894,12 +1113,41 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
- /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ /* cond_reject: wh_plus, act_tid: 4 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
- .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 4, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_rss_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 4, vnic_interface_queue_config.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
+ },
+ /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_QUEUE
},
- /* cond_execute: act_tid: 4, int_vtag_encap_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_RSS
+ },
+ /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 6, int_vtag_encap_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
@@ -907,11 +1155,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 4, int_full_act_record.0 */
+ /* cond_execute: act_tid: 6, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 4, ext_full_act_record.no_tag */
+ /* cond_execute: act_tid: 6, ext_full_act_record.no_tag */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -919,7 +1167,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 4, ext_full_act_record.one_tag */
+ /* cond_execute: act_tid: 6, ext_full_act_record.one_tag */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
@@ -927,60 +1175,103 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
- /* cond_execute: act_tid: 5, control.0 */
+ /* cond_reject: wh_plus, act_tid: 7 */
{
- .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
- .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 7, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_TP_SRC
},
- /* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
+ /* cond_execute: act_tid: 7, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
- /* cond_execute: act_tid: 5, act_modify_ipv4_src.0 */
+ /* cond_execute: act_tid: 7, act_modify_ipv4_src.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_SRC
},
- /* cond_execute: act_tid: 5, act_modify_ipv4_dst.0 */
+ /* cond_execute: act_tid: 7, act_modify_ipv4_dst.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_SET_IPV4_DST
},
- /* cond_execute: act_tid: 5, int_full_act_record.0 */
+ /* cond_execute: act_tid: 7, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 5, ext_full_act_record.0 */
+ /* cond_execute: act_tid: 7, ext_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
},
- /* cond_execute: act_tid: 6, int_flow_counter_tbl.0 */
+ /* cond_reject: wh_plus, act_tid: 8 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_DST
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SET_MAC_SRC
+ },
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
+ },
+ /* cond_execute: act_tid: 8, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
- /* cond_execute: act_tid: 6, sp_smac_ipv4.0 */
+ /* cond_execute: act_tid: 8, sp_smac_ipv4.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG
},
- /* cond_execute: act_tid: 6, sp_smac_ipv6.0 */
+ /* cond_execute: act_tid: 8, sp_smac_ipv6.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
.cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG
},
- /* cond_execute: act_tid: 6, int_tun_encap_record.0 */
+ /* cond_execute: act_tid: 8, int_tun_encap_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 6, int_full_act_record.0 */
+ /* cond_execute: act_tid: 8, int_full_act_record.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
},
- /* cond_execute: act_tid: 6, ext_full_act_record_vxlan.0 */
+ /* cond_execute: act_tid: 8, ext_full_act_record_vxlan.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET,
+ },
+ /* cond_execute: act_tid: 9, int_flow_counter_tbl.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+ .cond_operand = BNXT_ULP_ACT_BIT_COUNT
+ },
+ /* cond_execute: act_tid: 9, int_full_act_record.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET,
}
};
@@ -2252,7 +2543,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
},
- /* act_tid: 3, , table: int_encap_mac_record.0 */
+ /* act_tid: 3, , table: int_encap_vlan_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -2753,114 +3044,467 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
ULP_WP_SYM_DECAP_FUNC_THRU_L2}
},
{
- .description = "vnic_or_vport",
- .field_bit_size = 12,
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_valid",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ ULP_WP_SYM_ECV_VALID_YES}
+ },
+ {
+ .description = "ecv_custom_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_vtag_type",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l2_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l3_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_l4_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "ecv_tun_type",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_tpid",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_pcp",
+ .field_bit_size = 3,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_de",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vtag_vid",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: vnic_interface_rss_config.0 */
+ /* act_tid: 4, , table: vnic_interface_queue_config.0 */
+ /* act_tid: 4, , table: int_full_act_record.0 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_RSS_VNIC >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_RSS_VNIC & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 4, , table: int_full_act_record.1 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
- .field_opr1 = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "pop_vlan",
- .field_bit_size = 1,
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "meter",
- .field_bit_size = 1,
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "mirror",
- .field_bit_size = 2,
+ .description = "meter_id",
+ .field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "drop",
+ .description = "l3_rdir",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_valid",
+ .description = "tl3_rdir",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
- .field_opr1 = {
- ULP_WP_SYM_ECV_VALID_YES}
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_custom_en",
+ .description = "l3_ttl_dec",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_vtag_type",
- .field_bit_size = 4,
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l2_en",
- .field_bit_size = 1,
+ .description = "decap_func",
+ .field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_l3_type",
- .field_bit_size = 3,
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
{
- .description = "ecv_l4_type",
- .field_bit_size = 3,
+ .description = "pop_vlan",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "ecv_tun_type",
- .field_bit_size = 3,
+ .description = "meter",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_tpid",
- .field_bit_size = 16,
+ .description = "mirror",
+ .field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_pcp",
- .field_bit_size = 3,
+ .description = "drop",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_de",
+ .description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
- .description = "vtag_vid",
- .field_bit_size = 12,
+ .description = "type",
+ .field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 6, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: int_vtag_encap_record.0 */
+ /* act_tid: 6, , table: int_vtag_encap_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -2940,7 +3584,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
- /* act_tid: 4, , table: int_full_act_record.0 */
+ /* act_tid: 6, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3130,7 +3774,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: ext_full_act_record.no_tag */
+ /* act_tid: 6, , table: ext_full_act_record.no_tag */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3385,7 +4029,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 4, , table: ext_full_act_record.one_tag */
+ /* act_tid: 6, , table: ext_full_act_record.one_tag */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3660,14 +4304,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
- /* act_tid: 5, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 7, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: act_modify_ipv4_src.0 */
+ /* act_tid: 7, , table: act_modify_ipv4_src.0 */
{
.description = "ipv4_addr",
.field_bit_size = 32,
@@ -3677,7 +4321,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff}
},
- /* act_tid: 5, , table: act_modify_ipv4_dst.0 */
+ /* act_tid: 7, , table: act_modify_ipv4_dst.0 */
{
.description = "ipv4_addr",
.field_bit_size = 32,
@@ -3687,7 +4331,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff}
},
- /* act_tid: 5, , table: int_encap_mac_record.dummy */
+ /* act_tid: 7, , table: int_encap_vlan_record.dummy */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -3758,7 +4402,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: int_full_act_record.0 */
+ /* act_tid: 7, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -3988,7 +4632,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 5, , table: ext_full_act_record.0 */
+ /* act_tid: 7, , table: ext_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -4288,14 +4932,14 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: int_flow_counter_tbl.0 */
+ /* act_tid: 8, , table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: sp_smac_ipv4.0 */
+ /* act_tid: 8, , table: sp_smac_ipv4.0 */
{
.description = "smac",
.field_bit_size = 48,
@@ -4314,7 +4958,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_IPV4_SADDR >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_IPV4_SADDR & 0xff}
},
- /* act_tid: 6, , table: sp_smac_ipv6.0 */
+ /* act_tid: 8, , table: sp_smac_ipv6.0 */
{
.description = "smac",
.field_bit_size = 48,
@@ -4333,7 +4977,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_IPV6_SADDR >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_IPV6_SADDR & 0xff}
},
- /* act_tid: 6, , table: int_tun_encap_record.0 */
+ /* act_tid: 8, , table: int_tun_encap_record.0 */
{
.description = "ecv_valid",
.field_bit_size = 1,
@@ -4836,7 +5480,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
},
- /* act_tid: 6, , table: int_full_act_record.0 */
+ /* act_tid: 8, , table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -5011,7 +5655,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
- /* act_tid: 6, , table: ext_full_act_record_vxlan.0 */
+ /* act_tid: 8, , table: ext_full_act_record_vxlan.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
@@ -5684,6 +6328,185 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
(BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 >> 8) & 0xff,
BNXT_ULP_ENC_FIELD_VXLAN_RSVD1 & 0xff},
.field_src3 = BNXT_ULP_FIELD_SRC_SKIP
+ },
+ /* act_tid: 9, , table: int_flow_counter_tbl.0 */
+ {
+ .description = "count",
+ .field_bit_size = 64,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ /* act_tid: 9, , table: int_full_act_record.0 */
+ {
+ .description = "flow_cntr_ptr",
+ .field_bit_size = 14,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+ .field_opr1 = {
+ (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
+ },
+ {
+ .description = "age_enable",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "agg_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "rate_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "flow_cntr_en",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
+ },
+ {
+ .description = "tcpflags_key",
+ .field_bit_size = 8,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_mir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcpflags_match",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "encap_ptr",
+ .field_bit_size = 11,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "dst_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_dst_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "src_ip_ptr",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tcp_src_port",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter_id",
+ .field_bit_size = 10,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_rdir",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "l3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "tl3_ttl_dec",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "decap_func",
+ .field_bit_size = 4,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "vnic_or_vport",
+ .field_bit_size = 12,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+ .field_opr1 = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff}
+ },
+ {
+ .description = "pop_vlan",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "meter",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "mirror",
+ .field_bit_size = 2,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "drop",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "hit",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ {
+ .description = "type",
+ .field_bit_size = 1,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
}
};
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
index d1c3ebe065..9dd9821419 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c
@@ -1,10 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
-/* date: Fri Oct 8 11:41:10 2021 */
-
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
@@ -102,9 +100,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.key_start_idx = 1,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 1,
.ident_nums = 1
},
@@ -136,7 +134,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 6,
+ .key_start_idx = 7,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -160,10 +158,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 19,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 20,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 13,
.result_bit_size = 62,
.result_num_fields = 4
@@ -183,7 +181,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 24,
+ .key_start_idx = 26,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -236,7 +234,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 27,
+ .key_start_idx = 29,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -262,7 +260,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 70,
+ .key_start_idx = 72,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -288,7 +286,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 113,
+ .key_start_idx = 115,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -313,7 +311,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 156,
+ .key_start_idx = 158,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -334,7 +332,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 159,
+ .key_start_idx = 161,
.blob_key_bit_size = 176,
.key_bit_size = 176,
.key_num_fields = 10,
@@ -355,7 +353,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 169,
+ .key_start_idx = 171,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 10,
@@ -376,7 +374,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 179,
+ .key_start_idx = 181,
.blob_key_bit_size = 416,
.key_bit_size = 416,
.key_num_fields = 11,
@@ -397,7 +395,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 190,
+ .key_start_idx = 192,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -418,7 +416,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 201,
+ .key_start_idx = 203,
.blob_key_bit_size = 200,
.key_bit_size = 200,
.key_num_fields = 11,
@@ -439,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 212,
+ .key_start_idx = 214,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -461,9 +459,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 223,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
+ .key_start_idx = 225,
+ .blob_key_bit_size = 19,
+ .key_bit_size = 19,
.key_num_fields = 2,
.ident_start_idx = 9,
.ident_nums = 1
@@ -496,7 +494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 225,
+ .key_start_idx = 227,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -520,9 +518,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 238,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
+ .key_start_idx = 240,
+ .blob_key_bit_size = 19,
+ .key_bit_size = 19,
.key_num_fields = 2,
.result_start_idx = 140,
.result_bit_size = 52,
@@ -553,10 +551,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 240,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 242,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 11,
.ident_nums = 1
},
@@ -588,7 +586,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 245,
+ .key_start_idx = 248,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -612,10 +610,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 258,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 261,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 156,
.result_bit_size = 62,
.result_num_fields = 4
@@ -635,7 +633,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 263,
+ .key_start_idx = 267,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -672,7 +670,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 266,
+ .key_start_idx = 270,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -695,7 +693,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 309,
+ .key_start_idx = 313,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -716,7 +714,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 312,
+ .key_start_idx = 316,
.blob_key_bit_size = 112,
.key_bit_size = 112,
.key_num_fields = 8,
@@ -737,7 +735,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 320,
+ .key_start_idx = 324,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 8,
@@ -759,7 +757,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 328,
+ .key_start_idx = 332,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -780,10 +778,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 329,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 333,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.ident_start_idx = 16,
.ident_nums = 1
},
@@ -815,7 +813,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 334,
+ .key_start_idx = 339,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -839,10 +837,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 347,
- .blob_key_bit_size = 73,
- .key_bit_size = 73,
- .key_num_fields = 5,
+ .key_start_idx = 352,
+ .blob_key_bit_size = 89,
+ .key_bit_size = 89,
+ .key_num_fields = 6,
.result_start_idx = 213,
.result_bit_size = 62,
.result_num_fields = 4
@@ -861,7 +859,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 352,
+ .key_start_idx = 358,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -914,7 +912,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 355,
+ .key_start_idx = 361,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -940,7 +938,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 398,
+ .key_start_idx = 404,
.blob_key_bit_size = 81,
.key_bit_size = 81,
.key_num_fields = 43,
@@ -964,7 +962,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 441,
+ .key_start_idx = 447,
.blob_key_bit_size = 14,
.key_bit_size = 14,
.key_num_fields = 3,
@@ -985,7 +983,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 444,
+ .key_start_idx = 450,
.blob_key_bit_size = 176,
.key_bit_size = 176,
.key_num_fields = 10,
@@ -1006,7 +1004,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 454,
+ .key_start_idx = 460,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 10,
@@ -1027,7 +1025,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 464,
+ .key_start_idx = 470,
.blob_key_bit_size = 416,
.key_bit_size = 416,
.key_num_fields = 11,
@@ -1048,7 +1046,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .key_start_idx = 475,
+ .key_start_idx = 481,
.blob_key_bit_size = 448,
.key_bit_size = 448,
.key_num_fields = 11,
@@ -1090,7 +1088,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 486,
+ .key_start_idx = 492,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1127,7 +1125,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 487,
+ .key_start_idx = 493,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1151,7 +1149,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 500,
+ .key_start_idx = 506,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1256,7 +1254,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 501,
+ .key_start_idx = 507,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1291,7 +1289,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 502,
+ .key_start_idx = 508,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1315,7 +1313,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 515,
+ .key_start_idx = 521,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1337,7 +1335,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 516,
+ .key_start_idx = 522,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1372,7 +1370,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 517,
+ .key_start_idx = 523,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1396,7 +1394,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 530,
+ .key_start_idx = 536,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1511,7 +1509,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 531,
+ .key_start_idx = 537,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1546,7 +1544,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 532,
+ .key_start_idx = 538,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1570,7 +1568,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 545,
+ .key_start_idx = 551,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1667,7 +1665,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 546,
+ .key_start_idx = 552,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1691,7 +1689,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 559,
+ .key_start_idx = 565,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1726,7 +1724,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.pri_opcode = BNXT_ULP_PRI_OPC_CONST,
.pri_operand = 0,
- .key_start_idx = 560,
+ .key_start_idx = 566,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1750,7 +1748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
- .key_start_idx = 573,
+ .key_start_idx = 579,
.blob_key_bit_size = 8,
.key_bit_size = 8,
.key_num_fields = 1,
@@ -1837,7 +1835,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 574,
+ .key_start_idx = 580,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -1864,7 +1862,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
.pri_operand = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .key_start_idx = 587,
+ .key_start_idx = 593,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
@@ -2243,6 +2241,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -2595,6 +2607,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 1, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
@@ -5933,7 +5959,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
{
.field_info_mask = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -5942,7 +5968,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
.field_info_spec = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6160,7 +6186,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
{
.field_info_mask = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6169,7 +6195,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
},
.field_info_spec = {
.description = "svif",
- .field_bit_size = 8,
+ .field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
.field_src1 = BNXT_ULP_FIELD_SRC_HF,
.field_opr1 = {
@@ -6281,6 +6307,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -6455,7 +6495,9 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.description = "key_type",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr1 = {
+ 2}
},
.field_info_spec = {
.description = "key_type",
@@ -6567,6 +6609,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 2, , table: profile_tcam_cache.f2_rd */
{
.field_info_mask = {
@@ -6736,14 +6792,14 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
.field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
.field_opr1 = {
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
- (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_I_IPV4 & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_WP_SYM_L3_HDR_TYPE_IPV4},
@@ -7052,8 +7108,23 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
.field_info_spec = {
.description = "tl3_hdr_type",
.field_bit_size = 4,
- .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
- .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3,
+ .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT,
+ .field_opr1 = {
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+ .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr2 = {
+ ULP_WP_SYM_TL3_HDR_TYPE_IPV4},
+ .field_src3 = BNXT_ULP_FIELD_SRC_CONST,
+ .field_opr3 = {
+ ULP_WP_SYM_TL3_HDR_TYPE_IPV6}
}
},
{
@@ -7759,6 +7830,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 3, , table: l2_cntxt_tcam.0 */
{
.field_info_mask = {
@@ -8111,6 +8196,20 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}
}
},
+ {
+ .field_info_mask = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ },
+ .field_info_spec = {
+ .description = "etype",
+ .field_bit_size = 16,
+ .field_opc = BNXT_ULP_FIELD_OPC_SRC1,
+ .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
+ }
+ },
/* class_tid: 3, , table: profile_tcam_cache.rd */
{
.field_info_mask = {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 8790d7ac0d..fe1f65deb9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -296,6 +296,7 @@ int32_t
ulp_default_flow_create(struct rte_eth_dev *eth_dev,
struct ulp_tlv_param *param_list,
uint32_t ulp_class_tid,
+ uint16_t port_id,
uint32_t *flow_id)
{
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
@@ -355,12 +356,16 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
/* Get the function id */
if (ulp_port_db_port_func_id_get(ulp_ctx,
- eth_dev->data->port_id,
+ port_id,
&mapper_params.func_id)) {
BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
goto err1;
}
+ /* update the VF meta function id */
+ ULP_COMP_FLD_IDX_WR(&mapper_params, BNXT_ULP_CF_IDX_VF_META_FID,
+ BNXT_ULP_META_VF_FLAG | mapper_params.func_id);
+
BNXT_TF_DBG(DEBUG, "Creating default flow with template id: %u\n",
ulp_class_tid);
@@ -498,7 +503,7 @@ bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
return 0;
}
return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
- flow_id);
+ port_id, flow_id);
}
int32_t
@@ -526,8 +531,10 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
info->def_port_flow_id,
&bp->tx_cfa_action);
- if (rc)
+
+ if (rc || BNXT_TESTPMD_EN(bp))
bp->tx_cfa_action = 0;
+
info->valid = true;
return 0;
}
@@ -551,6 +558,7 @@ bnxt_create_port_vfr_default_rule(struct bnxt *bp,
}
};
return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
+ vfr_port_id,
flow_id);
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 85c9cbb7f2..dee2c04b24 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -311,7 +311,8 @@ ulp_fc_tf_flow_stat_get(struct bnxt_ulp_context *ctxt,
uint32_t dev_id = 0;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_flow_db_shared_session_get(res));
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
return -EINVAL;
@@ -437,8 +438,8 @@ void
ulp_fc_mgr_alarm_cb(void *arg)
{
int rc = 0;
- unsigned int j;
- enum tf_dir i;
+ unsigned int j = 0;
+ enum tf_dir i = 0;
struct bnxt_ulp_context *ctxt;
struct bnxt_ulp_fc_info *ulp_fc_info;
struct bnxt_ulp_device_params *dparms;
@@ -472,7 +473,8 @@ ulp_fc_mgr_alarm_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_fc_info->sw_acc_tbl[i][j].session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
bnxt_ulp_cntxt_entry_release();
@@ -512,6 +514,15 @@ ulp_fc_mgr_alarm_cb(void *arg)
if (!ulp_fc_info->sw_acc_tbl[i][j].valid)
continue;
hw_cntr_id = ulp_fc_info->sw_acc_tbl[i][j].hw_cntr_id;
+ tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
+ ulp_fc_info->sw_acc_tbl[i][j].session_type);
+ if (!tfp) {
+ BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
+ pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+ bnxt_ulp_cntxt_entry_release();
+ return;
+ }
+
rc = ulp_get_single_flow_stat(ctxt, tfp, ulp_fc_info, i,
hw_cntr_id, dparms);
if (rc)
@@ -603,7 +614,8 @@ int32_t ulp_fc_mgr_start_idx_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
*
*/
int32_t ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
- uint32_t hw_cntr_id)
+ uint32_t hw_cntr_id,
+ enum bnxt_ulp_session_type session_type)
{
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t sw_cntr_idx;
@@ -619,6 +631,7 @@ int32_t ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = true;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = hw_cntr_id;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].session_type = session_type;
ulp_fc_info->num_entries++;
pthread_mutex_unlock(&ulp_fc_info->fc_lock);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 9df5ae51a3..14836e0dd2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -29,6 +29,7 @@ struct sw_acc_counter {
bool valid;
uint32_t hw_cntr_id;
uint32_t pc_flow_idx;
+ enum bnxt_ulp_session_type session_type;
};
struct hw_fc_mem_info {
@@ -118,7 +119,9 @@ int ulp_fc_mgr_start_idx_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
*
*/
int ulp_fc_mgr_cntr_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
- uint32_t hw_cntr_id);
+ uint32_t hw_cntr_id,
+ enum bnxt_ulp_session_type session_type);
+
/*
* Reset the corresponding SW accumulator table entry based on
* the difference between this counter ID and the starting
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 9968311c44..2e6ea43ac1 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -653,7 +653,8 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
params->resource_hndl);
ulp_fc_mgr_cntr_set(ulp_ctxt, params->direction,
- params->resource_hndl);
+ params->resource_hndl,
+ ulp_flow_db_shared_session_get(params));
if (!ulp_fc_mgr_thread_isstarted(ulp_ctxt))
ulp_fc_mgr_thread_start(ulp_ctxt);
@@ -1824,8 +1825,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
* returns none
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
- enum bnxt_ulp_shared_session shared)
+ enum bnxt_ulp_session_type s_type)
{
- if (res && (shared & BNXT_ULP_SHARED_SESSION_YES))
+ if (res && (s_type & BNXT_ULP_SESSION_TYPE_SHARED))
res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION;
+ else if (res && (s_type & BNXT_ULP_SESSION_TYPE_SHARED_WC))
+ res->fdb_flags |= ULP_FDB_FLAG_SHARED_WC_SESSION;
+}
+
+/*
+ * Get the shared bit for the flow db entry
+ *
+ * res [out] shared session type
+ */
+enum bnxt_ulp_session_type
+ulp_flow_db_shared_session_get(struct ulp_flow_db_res_params *res)
+{
+ enum bnxt_ulp_session_type stype = BNXT_ULP_SESSION_TYPE_DEFAULT;
+
+ if (res && (res->fdb_flags & ULP_FDB_FLAG_SHARED_SESSION))
+ stype = BNXT_ULP_SESSION_TYPE_SHARED;
+ else if (res && (res->fdb_flags & ULP_FDB_FLAG_SHARED_WC_SESSION))
+ stype = BNXT_ULP_SESSION_TYPE_SHARED_WC;
+
+ return stype;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index ada34c0e6c..13a957fcff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -15,6 +15,7 @@
/* Defines for the fdb flag */
#define ULP_FDB_FLAG_SHARED_SESSION 0x1
+#define ULP_FDB_FLAG_SHARED_WC_SESSION 0x2
/*
* Structure for the flow database resource information
@@ -404,10 +405,18 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
* Set the shared bit for the flow db entry
*
* res [in] Ptr to fdb entry
- * shared [in] shared flag
+ * s_type [in] session flag
*
* returns none
*/
void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res,
- enum bnxt_ulp_shared_session shared);
+ enum bnxt_ulp_session_type s_type);
+
+/*
+ * Get the shared bit for the flow db entry
+ *
+ * res [out] Shared session type
+ */
+enum bnxt_ulp_session_type
+ulp_flow_db_shared_session_get(struct ulp_flow_db_res_params *res);
#endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 0030a487f5..42482b596f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
+ * Copyright(c) 2019-2023 Broadcom
* All rights reserved.
*/
@@ -54,7 +54,7 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
@@ -88,7 +88,7 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in client num get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
@@ -176,7 +176,7 @@ ulp_ha_mgr_timer_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_YES);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
goto cb_restart;
@@ -399,7 +399,7 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (tfp == NULL) {
BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
return -EINVAL;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7774a5537a..1f459c52a4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -115,7 +115,8 @@ ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data,
static int32_t
ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data,
- struct bnxt_ulp_glb_resource_info *glb_res)
+ struct bnxt_ulp_glb_resource_info *glb_res,
+ bool shared)
{
struct tf_alloc_identifier_parms iparms = { 0 };
struct tf_free_identifier_parms fparms;
@@ -123,7 +124,9 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
struct tf *tfp;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, shared ?
+ BNXT_ULP_SESSION_TYPE_SHARED :
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -167,7 +170,8 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
static int32_t
ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data,
- struct bnxt_ulp_glb_resource_info *glb_res)
+ struct bnxt_ulp_glb_resource_info *glb_res,
+ bool shared)
{
struct tf_alloc_tbl_entry_parms aparms = { 0 };
struct tf_free_tbl_entry_parms free_parms = { 0 };
@@ -176,7 +180,9 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_scope_id;
int32_t rc = 0;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, shared ?
+ BNXT_ULP_SESSION_TYPE_SHARED :
+ BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -728,6 +734,12 @@ ulp_mapper_priority_opc_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_PRI_OPC_APP_PRI:
*priority = parms->app_priority;
break;
+ case BNXT_ULP_PRI_OPC_APP_PRI_OR_CONST:
+ if (parms->app_priority)
+ *priority = parms->app_priority;
+ else
+ *priority = tbl->pri_operand;
+ break;
default:
BNXT_TF_DBG(ERR, "Priority opcode not supported %d\n",
tbl->pri_opcode);
@@ -815,7 +827,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
struct tf *tfp;
int rc;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get tf pointer\n");
return -EINVAL;
@@ -853,7 +865,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = ident->ident_type;
fid_parms.resource_hndl = iparms.id;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -900,7 +912,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
int rc;
/* Get the tfp from ulp context */
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get tf pointer\n");
return -EINVAL;
@@ -950,7 +962,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = ident->ident_type;
fid_parms.resource_hndl = sparms.search_id;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -1682,7 +1694,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = gfid;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1730,7 +1742,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = act_idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1778,7 +1790,7 @@ ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = act_idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -1846,7 +1858,7 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
uint16_t tmplen;
int32_t rc;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n");
return -EINVAL;
@@ -2026,7 +2038,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return 0;
}
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n");
return -EINVAL;
@@ -2088,7 +2100,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* For wild card tcam perform the post process to swap the blob */
if (ulp_mapper_tcam_is_wc_tcam(tbl)) {
- if (dparms->dynamic_pad_en) {
+ if (dparms->wc_dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
key, mask,
@@ -2204,7 +2216,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_type = tbl->resource_type;
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_hndl = idx;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -2245,7 +2257,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
int32_t pad = 0;
enum bnxt_ulp_byte_order key_order, res_order;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to get the mem type for EM\n");
@@ -2281,7 +2293,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* if dynamic padding is enabled then add padding to result data */
- if (dparms->dynamic_pad_en) {
+ if (dparms->em_dynamic_pad_en) {
/* add padding to make sure key is at byte boundary */
ulp_blob_pad_align(&key, ULP_BUFFER_ALIGN_8_BITS);
@@ -2300,7 +2312,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
- if (dparms->dynamic_pad_en) {
+ if (dparms->em_dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
/* when dynamic padding is enabled merge result + key */
@@ -2423,7 +2435,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bool shared = false;
enum tf_tbl_type tbl_type = tbl->resource_type;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
/* compute the blob size */
bit_size = ulp_mapper_dyn_blob_size_get(parms, tbl);
@@ -2637,7 +2649,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx = index;
sparms.tbl_scope_id = tbl_scope_id;
if (shared)
- tfp = bnxt_ulp_cntxt_shared_tfp_get(parms->ulp_ctx);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx,
+ tbl->session_type);
+
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR,
@@ -2671,7 +2685,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = index;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc) {
@@ -2721,7 +2735,7 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
enum bnxt_ulp_if_tbl_opc if_opc = tbl->tbl_opcode;
uint32_t res_size;
- tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->shared_session);
+ tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx, tbl->session_type);
/* Initialize the blob data */
if (!ulp_blob_init(&data, tbl->result_bit_size,
parms->device_params->result_byte_order)) {
@@ -3013,7 +3027,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_sub_type = tbl->resource_sub_type;
fid_parms.resource_hndl = key_index;
fid_parms.critical_resource = tbl->critical_resource;
- ulp_flow_db_shared_session_set(&fid_parms, tbl->shared_session);
+ ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
if (rc)
@@ -3077,12 +3091,14 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER:
rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
mapper_data,
- &glb_res[idx]);
+ &glb_res[idx],
+ false);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
mapper_data,
- &glb_res[idx]);
+ &glb_res[idx],
+ false);
break;
default:
BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
@@ -3104,108 +3120,57 @@ static int32_t
ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_data *mapper_data)
{
- struct tf_get_shared_tbl_increment_parms iparms;
struct bnxt_ulp_glb_resource_info *glb_res;
- struct tf_get_session_info_parms sparms;
- uint32_t num_entries, i, dev_id, res;
- struct tf_resource_info *res_info;
- uint32_t addend;
- uint64_t regval;
- enum tf_dir dir;
- int32_t rc = 0;
- struct tf *tfp;
+ uint32_t num_glb_res_ids, idx, dev_id;
uint8_t app_id;
+ uint32_t rc = 0;
- memset(&sparms, 0, sizeof(sparms));
- glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_entries);
- if (!glb_res || !num_entries) {
+ glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_glb_res_ids);
+ if (!glb_res || !num_glb_res_ids) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return -EINVAL;
}
- tfp = bnxt_ulp_cntxt_shared_tfp_get(ulp_ctx);
- if (!tfp) {
- BNXT_TF_DBG(ERR, "Failed to get tfp for app global init");
- return -EINVAL;
- }
- /*
- * Retrieve the resources that were assigned during the shared session
- * creation.
- */
- rc = tf_get_session_info(tfp, &sparms);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get session info (%d)\n", rc);
- return rc;
- }
-
- rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
+ rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get the app id in glb init (%d).\n",
+ BNXT_TF_DBG(ERR, "Failed to get device_id for glb init (%d)\n",
rc);
- return rc;
+ return -EINVAL;
}
- rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
+ rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get dev id for app glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get app_id for glb init (%d)\n",
rc);
- return rc;
+ return -EINVAL;
}
- /* Store all the app global resources */
- for (i = 0; i < num_entries; i++) {
- if (dev_id != glb_res[i].device_id ||
- app_id != glb_res[i].app_id)
+ /* Iterate the global resources and process each one */
+ for (idx = 0; idx < num_glb_res_ids; idx++) {
+ if (dev_id != glb_res[idx].device_id ||
+ glb_res[idx].app_id != app_id)
continue;
- dir = glb_res[i].direction;
- res = glb_res[i].resource_type;
- addend = 1;
-
- switch (glb_res[i].resource_func) {
+ switch (glb_res[idx].resource_func) {
case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER:
- res_info = &sparms.session_info.ident[dir].info[res];
+ rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
+ mapper_data,
+ &glb_res[idx],
+ false);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
- /*
- * Tables may have various strides for the allocations.
- * Need to account.
- */
- memset(&iparms, 0, sizeof(iparms));
- iparms.dir = dir;
- iparms.type = res;
- rc = tf_get_shared_tbl_increment(tfp, &iparms);
- if (rc) {
- BNXT_TF_DBG(ERR,
- "Failed to get addend for %s[%s] rc=(%d)\n",
- tf_tbl_type_2_str(res),
- tf_dir_2_str(dir), rc);
- return rc;
- }
- addend = iparms.increment_cnt;
- res_info = &sparms.session_info.tbl[dir].info[res];
- break;
- case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE:
- res_info = &sparms.session_info.tcam[dir].info[res];
- break;
- case BNXT_ULP_RESOURCE_FUNC_EM_TABLE:
- res_info = &sparms.session_info.em[dir].info[res];
+ rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
+ mapper_data,
+ &glb_res[idx],
+ false);
break;
default:
- BNXT_TF_DBG(ERR, "Unknown resource func (0x%x)\n",
- glb_res[i].resource_func);
- continue;
+ BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
+ glb_res[idx].resource_func);
+ rc = -EINVAL;
+ break;
}
- regval = tfp_cpu_to_be_64((uint64_t)res_info->start);
- res_info->start += addend;
- /*
- * All resources written to the global regfile are shared for
- * this function.
- */
- rc = ulp_mapper_glb_resource_write(mapper_data, &glb_res[i],
- regval, true);
if (rc)
return rc;
}
-
return rc;
}
@@ -3216,69 +3181,76 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
static int32_t
ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
enum bnxt_ulp_cond_opc opc,
- uint32_t operand,
+ uint64_t operand,
int32_t *res)
{
enum bnxt_ulp_flow_mem_type mtype = BNXT_ULP_FLOW_MEM_TYPE_INT;
+ uint32_t field_size = 0;
int32_t rc = 0;
- uint8_t bit;
- uint64_t regval;
+ uint8_t bit, tmp;
+ uint64_t regval, result = 0;
switch (opc) {
case BNXT_ULP_COND_OPC_CF_IS_SET:
if (operand < BNXT_ULP_CF_IDX_LAST) {
- *res = ULP_COMP_FLD_IDX_RD(parms, operand);
+ result = ULP_COMP_FLD_IDX_RD(parms, operand);
} else {
- BNXT_TF_DBG(ERR, "comp field out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "comp field out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_CF_NOT_SET:
if (operand < BNXT_ULP_CF_IDX_LAST) {
- *res = !ULP_COMP_FLD_IDX_RD(parms, operand);
+ result = !ULP_COMP_FLD_IDX_RD(parms, operand);
} else {
- BNXT_TF_DBG(ERR, "comp field out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "comp field out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ACT_BIT_IS_SET:
if (operand < BNXT_ULP_ACT_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->act_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "action bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "action bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET:
if (operand < BNXT_ULP_ACT_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "action bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "action bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_HDR_BIT_IS_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
@@ -3286,80 +3258,110 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
case BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET:
rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit);
if (rc) {
- BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+ BNXT_TF_DBG(ERR,
+ "invalid ulp_glb_field_tbl idx %" PRIu64 "\n",
operand);
return -EINVAL;
}
- *res = ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
+ result = ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
break;
case BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET:
rc = ulp_mapper_glb_field_tbl_get(parms, operand, &bit);
if (rc) {
- BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+ BNXT_TF_DBG(ERR,
+ "invalid ulp_glb_field_tbl idx %" PRIu64 "\n",
operand);
return -EINVAL;
}
- *res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
+ result = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
break;
case BNXT_ULP_COND_OPC_RF_IS_SET:
if (!ulp_regfile_read(parms->regfile, operand, ®val)) {
- BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
+ BNXT_TF_DBG(ERR,
+ "regfile[%" PRIu64 "] read oob\n",
+ operand);
return -EINVAL;
}
- *res = regval != 0;
+ result = regval != 0;
break;
case BNXT_ULP_COND_OPC_RF_NOT_SET:
if (!ulp_regfile_read(parms->regfile, operand, ®val)) {
- BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
+ BNXT_TF_DBG(ERR,
+ "regfile[%" PRIu64 "] read oob\n", operand);
return -EINVAL;
}
- *res = regval == 0;
+ result = regval == 0;
break;
case BNXT_ULP_COND_OPC_FLOW_PAT_MATCH:
- *res = parms->flow_pattern_id == operand;
+ result = parms->flow_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_ACT_PAT_MATCH:
- *res = parms->act_pattern_id == operand;
+ result = parms->act_pattern_id == operand;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_IS_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
BNXT_TF_DBG(ERR, "Failed to get the mem type\n");
return -EINVAL;
}
- *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 0 : 1;
+ result = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 0 : 1;
break;
case BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET:
if (bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype)) {
BNXT_TF_DBG(ERR, "Failed to get the mem type\n");
return -EINVAL;
}
- *res = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
+ result = (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT) ? 1 : 0;
break;
case BNXT_ULP_COND_OPC_ENC_HDR_BIT_IS_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ result = ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
case BNXT_ULP_COND_OPC_ENC_HDR_BIT_NOT_SET:
if (operand < BNXT_ULP_HDR_BIT_LAST) {
- *res = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
+ result = !ULP_BITMAP_ISSET(parms->enc_hdr_bitmap->bits,
operand);
} else {
- BNXT_TF_DBG(ERR, "header bit out of bounds %d\n",
+ BNXT_TF_DBG(ERR,
+ "header bit out of bounds %" PRIu64 "\n",
operand);
rc = -EINVAL;
}
break;
+ case BNXT_ULP_COND_OPC_ACT_PROP_IS_SET:
+ case BNXT_ULP_COND_OPC_ACT_PROP_NOT_SET:
+ /* only supporting 1-byte action properties for now */
+ if (operand >= BNXT_ULP_ACT_PROP_IDX_LAST) {
+ BNXT_TF_DBG(ERR,
+ "act_prop[%" PRIu64 "] oob\n", operand);
+ return -EINVAL;
+ }
+ field_size = ulp_mapper_act_prop_size_get(operand);
+ if (sizeof(tmp) != field_size) {
+ BNXT_TF_DBG(ERR,
+ "act_prop[%" PRIu64 "] field mismatch %u\n",
+ operand, field_size);
+ return -EINVAL;
+ }
+ tmp = parms->act_prop->act_details[operand];
+ if (opc == BNXT_ULP_COND_OPC_ACT_PROP_IS_SET)
+ result = (int32_t)(tmp);
+ else
+ result = (int32_t)(!tmp);
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid conditional opcode %d\n", opc);
rc = -EINVAL;
break;
}
+
+ *res = !!result;
return (rc);
}
@@ -3797,10 +3799,7 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp,
BNXT_TF_DBG(ERR, "Unable to free resource\n ");
return -EINVAL;
}
- if (res->fdb_flags & ULP_FDB_FLAG_SHARED_SESSION)
- tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_YES);
- else
- tfp = bnxt_ulp_cntxt_tfp_get(ulp, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp, ulp_flow_db_shared_session_get(res));
if (!tfp) {
BNXT_TF_DBG(ERR, "Unable to free resource failed to get tfp\n");
return -EINVAL;
@@ -4065,7 +4064,7 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
if (!ulp_ctx)
return -EINVAL;
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp)
return -EINVAL;
@@ -4136,7 +4135,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SHARED_SESSION_NO);
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT);
if (!tfp) {
BNXT_TF_DBG(ERR, "Failed to acquire tfp.\n");
/* Free the mapper data regardless of errors. */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index f8ffb567b5..57c9e7d175 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -118,8 +118,8 @@ int32_t ulp_port_db_deinit(struct bnxt_ulp_context *ulp_ctxt)
*
* Returns 0 on success or negative number on failure.
*/
-int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
- struct rte_eth_dev *eth_dev)
+int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
+ struct rte_eth_dev *eth_dev)
{
uint32_t port_id = eth_dev->data->port_id;
struct ulp_phy_port_info *port_data;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index f575a3c2e2..784b93f8b3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -11,6 +11,7 @@
#define BNXT_PORT_DB_MAX_INTF_LIST 256
#define BNXT_PORT_DB_MAX_FUNC 2048
#define BNXT_ULP_FREE_PARIF_BASE 11
+#define BNXT_ULP_META_VF_FLAG 0x1000
enum bnxt_ulp_svif_type {
BNXT_ULP_DRV_FUNC_SVIF = 0,
@@ -51,6 +52,7 @@ struct ulp_func_if_info {
uint8_t func_parent_mac[RTE_ETHER_ADDR_LEN];
uint16_t phy_port_id;
uint16_t ifindex;
+ uint16_t vf_meta_data;
};
/* Structure for the Port database resource information. */
@@ -58,6 +60,7 @@ struct ulp_interface_info {
enum bnxt_ulp_intf_type type;
uint16_t drv_func_id;
uint16_t vf_func_id;
+ uint8_t type_is_pf;
};
struct ulp_phy_port_info {
@@ -109,8 +112,8 @@ int32_t ulp_port_db_deinit(struct bnxt_ulp_context *ulp_ctxt);
*
* Returns 0 on success or negative number on failure.
*/
-int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
- struct rte_eth_dev *eth_dev);
+int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
+ struct rte_eth_dev *eth_dev);
/*
* Api to get the ulp ifindex for a given device port.
@@ -167,7 +170,6 @@ int32_t
ulp_port_db_spif_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t ifindex, uint32_t dir, uint16_t *spif);
-
/*
* Api to get the parif for a given ulp ifindex.
*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 80869b79c3..3566f3000b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -131,10 +131,6 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
params->field_idx = BNXT_ULP_PROTO_HDR_SVIF_NUM;
- /* Set the computed flags for no vlan tags before parsing */
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 1);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 1);
-
/* Parse all the items in the pattern */
while (item && item->type != RTE_FLOW_ITEM_TYPE_END) {
if (item->type >= (typeof(item->type))
@@ -515,8 +511,8 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
enum bnxt_ulp_direction_type item_dir;
uint16_t ethdev_id;
uint16_t mask = 0;
- int32_t rc = BNXT_TF_RC_PARSE_ERR;
uint32_t ifindex;
+ int32_t rc = BNXT_TF_RC_PARSE_ERR;
if (!item->spec) {
BNXT_TF_DBG(ERR, "ParseErr:Port spec is not valid\n");
@@ -535,6 +531,11 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
item_dir = BNXT_ULP_DIR_INVALID;
ethdev_id = port_spec->id;
mask = port_mask->id;
+
+ if (!port_mask->id) {
+ ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF_IGNORE);
+ mask = 0xff;
+ }
break;
}
case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: {
@@ -778,7 +779,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
outer_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_NO_VTAG, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_HAS_VTAG, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_OO_VLAN);
@@ -808,7 +809,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
inner_vtag_num++;
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_NO_VTAG, 0);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_HAS_VTAG, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1);
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_IO_VLAN);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 3dcc6dbc0c..fb6fb3553b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -171,7 +171,7 @@ extern struct bnxt_ulp_act_match_info ulp_act_match_list[];
/* Device Specific Tables for mapper */
struct bnxt_ulp_mapper_cond_info {
enum bnxt_ulp_cond_opc cond_opcode;
- uint32_t cond_operand;
+ uint64_t cond_operand;
};
struct bnxt_ulp_mapper_cond_list_info {
@@ -233,10 +233,11 @@ struct bnxt_ulp_device_params {
uint64_t packet_count_mask;
uint32_t byte_count_shift;
uint32_t packet_count_shift;
- uint32_t dynamic_pad_en;
+ uint32_t wc_dynamic_pad_en;
+ uint32_t em_dynamic_pad_en;
uint32_t dynamic_sram_en;
uint32_t dyn_encap_list_size;
- struct bnxt_ulp_dyn_size_map dyn_encap_sizes[4];
+ struct bnxt_ulp_dyn_size_map dyn_encap_sizes[5];
uint32_t dyn_modify_list_size;
struct bnxt_ulp_dyn_size_map dyn_modify_sizes[4];
uint16_t em_blk_size_bits;
@@ -305,8 +306,11 @@ struct bnxt_ulp_mapper_tbl_info {
enum bnxt_ulp_fdb_opc fdb_opcode;
uint32_t fdb_operand;
+ /* Manage ref_cnt via opcode for generic tables */
+ enum bnxt_ulp_ref_cnt_opc ref_cnt_opcode;
+
/* Shared session */
- enum bnxt_ulp_shared_session shared_session;
+ enum bnxt_ulp_session_type session_type;
};
struct bnxt_ulp_mapper_field_info {
@@ -340,6 +344,7 @@ struct bnxt_ulp_glb_resource_info {
uint8_t app_id;
enum bnxt_ulp_device_id device_id;
enum tf_dir direction;
+ enum bnxt_ulp_session_type session_type;
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
enum bnxt_ulp_glb_rf_idx glb_regfile_index;
@@ -349,6 +354,7 @@ struct bnxt_ulp_resource_resv_info {
uint8_t app_id;
enum bnxt_ulp_device_id device_id;
enum tf_dir direction;
+ enum bnxt_ulp_session_type session_type;
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
uint32_t count;
@@ -356,7 +362,13 @@ struct bnxt_ulp_resource_resv_info {
struct bnxt_ulp_app_capabilities_info {
uint8_t app_id;
+ uint32_t vxlan_port;
+ uint32_t vxlan_ip_port;
enum bnxt_ulp_device_id device_id;
+ uint32_t upgrade_fw_update;
+ uint8_t ha_pool_id;
+ uint8_t ha_reg_state;
+ uint8_t ha_reg_cnt;
uint32_t flags;
};
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 06/11] net/bnxt: add RSS and Queue action in TruFLow
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (4 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 07/11] net/bnxt: add support for rte meter Ajit Khaparde
` (4 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev
Cc: ferruh.yigit, thomas, Randy Schacher, Kishore Padmanabha,
Mike Baucom, Shuanglin Wang
[-- Attachment #1: Type: text/plain, Size: 187167 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
- Update ULP layer to support RSS/Queue action
- Modify VNIC handling driver to support RSS action
- Modify VNIC handling driver to support Queue action
This should allow to enable TruFlow path for all RTE_FLOW
by default in future.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/nics/features/bnxt.ini | 3 +
drivers/net/bnxt/bnxt.h | 39 +-
drivers/net/bnxt/bnxt_ethdev.c | 154 +--
drivers/net/bnxt/bnxt_filter.h | 6 +-
drivers/net/bnxt/bnxt_flow.c | 75 +-
drivers/net/bnxt/bnxt_hwrm.c | 187 +++-
drivers/net/bnxt/bnxt_hwrm.h | 30 +-
drivers/net/bnxt/bnxt_ring.c | 4 +-
drivers/net/bnxt/bnxt_rxq.c | 159 +--
drivers/net/bnxt/bnxt_rxr.c | 9 +-
drivers/net/bnxt/bnxt_txq.c | 2 +-
drivers/net/bnxt/bnxt_txr.c | 2 +-
drivers/net/bnxt/bnxt_txr.h | 2 +-
drivers/net/bnxt/bnxt_vnic.c | 969 +++++++++++++++++-
drivers/net/bnxt/bnxt_vnic.h | 80 +-
drivers/net/bnxt/meson.build | 3 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 248 ++++-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 35 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 258 ++++-
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 280 ++++-
drivers/net/bnxt/tf_ulp/meson.build | 25 +-
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 13 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 37 +-
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 4 +-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 121 ++-
drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 5 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 449 +++++++-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 14 +-
drivers/net/bnxt/tf_ulp/ulp_port_db.c | 58 ++
drivers/net/bnxt/tf_ulp/ulp_port_db.h | 26 +
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 22 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 338 +++++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 37 +-
35 files changed, 3281 insertions(+), 417 deletions(-)
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index 50a0b5bfa6..b225878a78 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -84,11 +84,14 @@ of_set_vlan_vid = Y
pf = Y
port_id = Y
port_representor = Y
+queue = Y
represented_port = Y
rss = Y
sample = Y
set_ipv4_dst = Y
set_ipv4_src = Y
+set_mac_dst = Y
+set_mac_src = Y
set_tp_dst = Y
set_tp_src = Y
vf = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index bb2e7fe003..6dd3c8b87c 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -24,6 +24,7 @@
#include "tf_core.h"
#include "bnxt_ulp.h"
#include "bnxt_tf_common.h"
+#include "bnxt_vnic.h"
/* Vendor ID */
#define PCI_VENDOR_ID_BROADCOM 0x14E4
@@ -163,6 +164,8 @@
#define BNXT_HWRM_CMD_TO_FORWARD(cmd) \
(bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32)))
+#define BNXT_NTOHS rte_be_to_cpu_16
+
struct bnxt_led_info {
uint8_t num_leds;
uint8_t led_id;
@@ -238,11 +241,11 @@ struct bnxt_parent_info {
struct bnxt_pf_info {
#define BNXT_FIRST_PF_FID 1
#define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs)
-#define BNXT_MAX_VF_REPS_WH 64
-#define BNXT_MAX_VF_REPS_TH 256
+#define BNXT_MAX_VF_REPS_P4 64
+#define BNXT_MAX_VF_REPS_P5 256
#define BNXT_MAX_VF_REPS(bp) \
- (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \
- BNXT_MAX_VF_REPS_WH)
+ (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_P5 : \
+ BNXT_MAX_VF_REPS_P4)
#define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs)
#define BNXT_FIRST_VF_FID 128
#define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
@@ -366,7 +369,7 @@ struct bnxt_ptp_cfg {
uint32_t tx_regs[BNXT_PTP_TX_REGS];
uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
- /* On Thor, the Rx timestamp is present in the Rx completion record */
+ /* On P5, the Rx timestamp is present in the Rx completion record */
uint64_t rx_timestamp;
uint64_t current_time;
};
@@ -679,8 +682,8 @@ struct bnxt {
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
-#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
-#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
+#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
+#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
#define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
#define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
#define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
@@ -689,7 +692,7 @@ struct bnxt {
#define BNXT_HAS_NQ(bp) BNXT_CHIP_P5(bp)
#define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_P5(bp))
#define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
-#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
+#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
uint32_t flags2;
@@ -697,8 +700,8 @@ struct bnxt {
#define BNXT_FLAGS2_PTP_ALARM_SCHEDULED BIT(1)
#define BNXT_P5_PTP_TIMESYNC_ENABLED(bp) \
((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
-#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
-#define BNXT_TESTPMD_EN(bp) \
+#define BNXT_FLAGS2_TESTPMD_EN BIT(3)
+#define BNXT_TESTPMD_EN(bp) \
((bp)->flags2 & BNXT_FLAGS2_TESTPMD_EN)
uint16_t chip_num;
@@ -719,7 +722,8 @@ struct bnxt {
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
-#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
+#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\
+ (bp)->app_id != 0xFF)
pthread_mutex_t flow_lock;
@@ -729,6 +733,7 @@ struct bnxt {
#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2)
#define BNXT_VNIC_CAP_VLAN_RX_STRIP BIT(3)
#define BNXT_RX_VLAN_STRIP_EN(bp) ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
+#define BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF BIT(4)
unsigned int rx_nr_rings;
unsigned int rx_cp_nr_rings;
unsigned int rx_num_qs_per_vnic;
@@ -758,7 +763,6 @@ struct bnxt {
uint16_t nr_vnics;
-#define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
struct bnxt_vnic_info *vnic_info;
STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
@@ -873,6 +877,7 @@ struct bnxt {
uint16_t tx_cfa_action;
struct bnxt_ring_stats *prev_rx_ring_stats;
struct bnxt_ring_stats *prev_tx_ring_stats;
+ struct bnxt_vnic_queue_db vnic_queue_db;
#define BNXT_MAX_MC_ADDRS ((bp)->max_mcast_addr)
struct rte_ether_addr *mcast_addr_list;
@@ -905,7 +910,7 @@ inline uint16_t bnxt_max_rings(struct bnxt *bp)
}
/*
- * RSS table size in Thor is 512.
+ * RSS table size in P5 is 512.
* Cap max Rx rings to the same value for RSS.
*/
if (BNXT_CHIP_P5(bp))
@@ -997,9 +1002,16 @@ void bnxt_schedule_fw_health_check(struct bnxt *bp);
bool is_bnxt_supported(struct rte_eth_dev *dev);
bool bnxt_stratus_device(struct bnxt *bp);
void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
+uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
int wait_to_complete);
+int
+bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
+int
+bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
extern const struct rte_flow_ops bnxt_flow_ops;
@@ -1053,5 +1065,6 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp);
struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bcde44bb14..4d84aaee0c 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -202,7 +202,7 @@ int is_bnxt_in_error(struct bnxt *bp)
* High level utility functions
*/
-static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
+uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
{
unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
BNXT_RSS_TBL_SIZE_P5);
@@ -421,6 +421,10 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
vnic_id, vnic, vnic->fw_grp_ids);
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc)
goto err_out;
@@ -429,7 +433,7 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
int j, nr_ctxs = bnxt_rss_ctxts(bp);
- /* RSS table size in Thor is 512.
+ /* RSS table size in P5 is 512.
* Cap max Rx rings to same value
*/
if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
@@ -479,9 +483,7 @@ static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
j, rxq->vnic, rxq->vnic->fw_grp_ids);
if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
- rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
- else
- vnic->rx_queue_cnt++;
+ vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
}
PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
@@ -755,12 +757,18 @@ static int bnxt_start_nic(struct bnxt *bp)
else
bp->flags &= ~BNXT_FLAG_JUMBO;
- /* THOR does not support ring groups.
+ /* P5 does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
if (BNXT_CHIP_P5(bp))
bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
+ rc = bnxt_vnic_queue_db_init(bp);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "could not allocate vnic db\n");
+ goto err_out;
+ }
+
rc = bnxt_alloc_hwrm_rings(bp);
if (rc) {
PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
@@ -808,6 +816,9 @@ static int bnxt_start_nic(struct bnxt *bp)
}
}
+ /* setup the default vnic details*/
+ bnxt_vnic_queue_db_update_dlft_vnic(bp);
+
/* VNIC configuration */
for (i = 0; i < bp->nr_vnics; i++) {
rc = bnxt_setup_one_vnic(bp, i);
@@ -901,6 +912,7 @@ static int bnxt_shutdown_nic(struct bnxt *bp)
bnxt_free_all_hwrm_resources(bp);
bnxt_free_all_filters(bp);
bnxt_free_all_vnics(bp);
+ bnxt_vnic_queue_db_deinit(bp);
return 0;
}
@@ -1431,7 +1443,6 @@ static void bnxt_ptp_get_current_time(void *arg)
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
-
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
if (rc != 0) {
PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
@@ -1450,6 +1461,7 @@ static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
return rc;
}
@@ -1891,7 +1903,7 @@ static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_PROMISC;
@@ -1920,7 +1932,7 @@ static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
@@ -1949,7 +1961,7 @@ static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
@@ -1978,7 +1990,7 @@ static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
@@ -2026,7 +2038,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
uint16_t idx, sft;
int i, rc;
@@ -2048,6 +2060,10 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
return -EINVAL;
}
+ if (bnxt_vnic_reta_config_update(bp, vnic, reta_conf, reta_size)) {
+ PMD_DRV_LOG(ERR, "Error in setting the reta config\n");
+ return -EINVAL;
+ }
for (i = 0; i < reta_size; i++) {
struct bnxt_rx_queue *rxq;
@@ -2058,11 +2074,6 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
continue;
rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
- if (!rxq) {
- PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
- return -EINVAL;
- }
-
if (BNXT_CHIP_P5(bp)) {
vnic->rss_table[i * 2] =
rxq->rx_ring->rx_ring_struct->fw_ring_id;
@@ -2073,7 +2084,6 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
}
-
rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return rc;
}
@@ -2083,7 +2093,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
uint16_t reta_size)
{
struct bnxt *bp = eth_dev->data->dev_private;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
uint16_t idx, sft, i;
int rc;
@@ -2153,7 +2163,7 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
}
/* Update the default RSS VNIC(s) */
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
vnic->hash_mode =
bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
@@ -2189,7 +2199,7 @@ static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_conf *rss_conf)
{
struct bnxt *bp = eth_dev->data->dev_private;
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int len, rc;
uint32_t hash_types;
@@ -2348,7 +2358,7 @@ static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
}
/* Add UDP tunneling port */
-static int
+int
bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel)
{
@@ -2410,7 +2420,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
return rc;
}
-static int
+int
bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel)
{
@@ -2474,7 +2484,7 @@ static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
int rc = 0;
uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
filter = STAILQ_FIRST(&vnic->filter);
while (filter) {
/* Search for this matching MAC+VLAN filter */
@@ -2513,7 +2523,7 @@ static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
* then the HWRM shall only create an l2 context id.
*/
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
filter = STAILQ_FIRST(&vnic->filter);
/* Check if the VLAN has already been added */
while (filter) {
@@ -2618,7 +2628,7 @@ bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
unsigned int i;
int rc;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
/* Remove any VLAN filters programmed */
for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
@@ -2677,16 +2687,18 @@ static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
static int
bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
{
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int rc;
/* Destroy, recreate and reconfigure the default vnic */
- rc = bnxt_free_one_vnic(bp, 0);
+ rc = bnxt_free_one_vnic(bp, bp->vnic_queue_db.dflt_vnic_id);
if (rc)
return rc;
- /* default vnic 0 */
- rc = bnxt_setup_one_vnic(bp, 0);
+ /* setup the default vnic details*/
+ bnxt_vnic_queue_db_update_dlft_vnic(bp);
+
+ rc = bnxt_setup_one_vnic(bp, bp->vnic_queue_db.dflt_vnic_id);
if (rc)
return rc;
@@ -2817,7 +2829,7 @@ bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
{
struct bnxt *bp = dev->data->dev_private;
/* Default Filter is tied to VNIC 0 */
- struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ struct bnxt_vnic_info *vnic = bnxt_get_default_vnic(bp);
int rc;
rc = is_bnxt_in_error(bp);
@@ -2867,7 +2879,7 @@ bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
if (rc)
return rc;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
bp->nb_mc_addr = nb_mc_addr;
@@ -3029,8 +3041,7 @@ bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
- uint32_t rc;
- uint32_t i;
+ uint32_t rc = 0;
rc = is_bnxt_in_error(bp);
if (rc)
@@ -3048,30 +3059,17 @@ int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
/* Is there a change in mtu setting? */
if (eth_dev->data->mtu == new_mtu)
- return 0;
+ return rc;
if (new_mtu > RTE_ETHER_MTU)
bp->flags |= BNXT_FLAG_JUMBO;
else
bp->flags &= ~BNXT_FLAG_JUMBO;
- for (i = 0; i < bp->nr_vnics; i++) {
- struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
- uint16_t size = 0;
-
- vnic->mru = BNXT_VNIC_MRU(new_mtu);
- rc = bnxt_hwrm_vnic_cfg(bp, vnic);
- if (rc)
- break;
-
- size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
- size -= RTE_PKTMBUF_HEADROOM;
-
- if (size < new_mtu) {
- rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
- if (rc)
- return rc;
- }
+ rc = bnxt_vnic_mru_config(bp, new_mtu);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "failed to update mtu in vnic context\n");
+ return rc;
}
if (bnxt_hwrm_config_host_mtu(bp))
@@ -5312,9 +5310,11 @@ static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
{
int rc = 0;
- rc = bnxt_get_config(bp);
- if (rc)
- return rc;
+ if (reconfig_dev) {
+ rc = bnxt_get_config(bp);
+ if (rc)
+ return rc;
+ }
rc = bnxt_alloc_switch_domain(bp);
if (rc)
@@ -5756,7 +5756,7 @@ static int
bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
{
struct rte_kvargs *kvlist;
- int ret;
+ int ret = 0;
if (devargs == NULL)
return 0;
@@ -5825,22 +5825,6 @@ static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
bp->flags |= BNXT_FLAG_STINGRAY;
- if (BNXT_TRUFLOW_EN(bp)) {
- /* extra mbuf field is required to store CFA code from mark */
- static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
- .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
- .size = sizeof(bnxt_cfa_code_dynfield_t),
- .align = __alignof__(bnxt_cfa_code_dynfield_t),
- };
- bnxt_cfa_code_dynfield_offset =
- rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
- if (bnxt_cfa_code_dynfield_offset < 0) {
- PMD_DRV_LOG(ERR,
- "Failed to register mbuf field for TruFlow mark\n");
- return -rte_errno;
- }
- }
-
rc = bnxt_map_pci_bars(eth_dev);
if (rc) {
PMD_DRV_LOG(ERR,
@@ -5878,6 +5862,26 @@ static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
if (rc)
return rc;
+ rc = bnxt_get_config(bp);
+ if (rc)
+ return rc;
+
+ if (BNXT_TRUFLOW_EN(bp)) {
+ /* extra mbuf field is required to store CFA code from mark */
+ static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
+ .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
+ .size = sizeof(bnxt_cfa_code_dynfield_t),
+ .align = __alignof__(bnxt_cfa_code_dynfield_t),
+ };
+ bnxt_cfa_code_dynfield_offset =
+ rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
+ if (bnxt_cfa_code_dynfield_offset < 0) {
+ PMD_DRV_LOG(ERR,
+ "Failed to register mbuf field for TruFlow mark\n");
+ return -rte_errno;
+ }
+ }
+
return rc;
}
@@ -5912,6 +5916,9 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
bp = eth_dev->data->dev_private;
+ /* set the default app id */
+ bp->app_id = bnxt_ulp_default_app_id_get();
+
/* Parse dev arguments passed on when starting the DPDK application. */
rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
if (rc)
@@ -5948,7 +5955,8 @@ static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
if (!ctx)
return;
- rte_free(ctx->va);
+ if (ctx->va)
+ rte_free(ctx->va);
ctx->va = NULL;
ctx->dma = RTE_BAD_IOVA;
diff --git a/drivers/net/bnxt/bnxt_filter.h b/drivers/net/bnxt/bnxt_filter.h
index 587932c96f..57d704d90b 100644
--- a/drivers/net/bnxt/bnxt_filter.h
+++ b/drivers/net/bnxt/bnxt_filter.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -173,4 +173,8 @@ struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS
#define L2_FILTER_ALLOC_INPUT_EN_NUM_VLANS \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS
+#define CFA_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
+#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE
#endif
diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 4a107e81e9..28dd5ae6cb 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -677,7 +677,6 @@ bnxt_validate_and_parse_flow_type(const struct rte_flow_attr *attr,
break;
}
break;
-
default:
break;
}
@@ -728,7 +727,7 @@ bnxt_find_matching_l2_filter(struct bnxt *bp, struct bnxt_filter_info *nf)
struct bnxt_vnic_info *vnic0;
int i;
- vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic0 = bnxt_get_default_vnic(bp);
f0 = STAILQ_FIRST(&vnic0->filter);
/* This flow has same DST MAC as the port/l2 filter. */
@@ -905,6 +904,10 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct bnxt_vnic_info *vnic,
act,
"Failed to alloc VNIC group");
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc) {
rte_flow_error_set(error, -rc,
@@ -1345,7 +1348,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
* The user specified redirect queue will be set while creating
* the ntuple filter in hardware.
*/
- vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic0 = bnxt_get_default_vnic(bp);
if (use_ntuple)
filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
else
@@ -1964,7 +1967,37 @@ bnxt_flow_create(struct rte_eth_dev *dev,
* in such a case.
*/
if (filter->filter_type == HWRM_CFA_TUNNEL_REDIRECT_FILTER &&
- filter->enables == filter->tunnel_type) {
+ (filter->enables == filter->tunnel_type ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE)) {
+ if (filter->enables & NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT) {
+ struct rte_eth_udp_tunnel tunnel = {0};
+
+ /* hwrm_tunnel_dst_port_alloc converts to Big Endian */
+ tunnel.udp_port = BNXT_NTOHS(filter->dst_port);
+ if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_VXLAN;
+ } else if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_GENEVE;
+ } else {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Invalid tunnel type");
+ ret = -EINVAL;
+ goto free_filter;
+ }
+ ret = bnxt_udp_tunnel_port_add_op(bp->eth_dev, &tunnel);
+ if (ret != 0) {
+ rte_flow_error_set(error, -ret,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Fail to add tunnel port");
+ goto free_filter;
+ }
+ }
ret = bnxt_hwrm_tunnel_redirect_query(bp, &tun_type);
if (ret) {
rte_flow_error_set(error, -ret,
@@ -2147,8 +2180,38 @@ _bnxt_flow_destroy(struct bnxt *bp,
filter = flow->filter;
vnic = flow->vnic;
+ /* If tunnel redirection to a VF/PF is specified then only tunnel_type
+ * is set and enable is set to the tunnel type. Issue hwrm cmd directly
+ * in such a case.
+ */
if (filter->filter_type == HWRM_CFA_TUNNEL_REDIRECT_FILTER &&
- filter->enables == filter->tunnel_type) {
+ (filter->enables == filter->tunnel_type ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN ||
+ filter->tunnel_type == CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE)) {
+ if (filter->enables & NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT) {
+ struct rte_eth_udp_tunnel tunnel = {0};
+
+ /* hwrm_tunnel_dst_port_free converts to Big Endian */
+ tunnel.udp_port = BNXT_NTOHS(filter->dst_port);
+ if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_VXLAN;
+ } else if (filter->tunnel_type ==
+ CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE) {
+ tunnel.prot_type = RTE_ETH_TUNNEL_TYPE_GENEVE;
+ } else {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL,
+ "Invalid tunnel type");
+ return ret;
+ }
+
+ ret = bnxt_udp_tunnel_port_del_op(bp->eth_dev,
+ &tunnel);
+ if (ret)
+ return ret;
+ }
ret = bnxt_handle_tunnel_redirect_destroy(bp, filter, error);
if (!ret)
goto done;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 3f273df6f3..77588bdf49 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -668,6 +668,7 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
else
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
+
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
@@ -858,9 +859,11 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
- if (BNXT_PF(bp)) {
+ if (BNXT_PF(bp))
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
- if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
+
+ if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
+ if (BNXT_CHIP_P5(bp) || BNXT_PF(bp)) {
bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
HWRM_UNLOCK();
@@ -894,6 +897,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
if (bp->tunnel_disable_flag)
PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
bp->tunnel_disable_flag);
+
unlock:
HWRM_UNLOCK();
@@ -951,6 +955,11 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
+ if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP) {
+ bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF;
+ PMD_DRV_LOG(DEBUG, "Trusted VF's outer RSS capability is enabled\n");
+ }
+
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
@@ -1097,7 +1106,16 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
bp->tx_nr_rings +
BNXT_NUM_ASYNC_CPR(bp));
- req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
+ if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
+ req.num_vnics = rte_cpu_to_le_16(RTE_MIN(BNXT_VNIC_MAX_SUPPORTED_ID,
+ bp->max_vnics));
+ enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
+ req.num_rsscos_ctxs = rte_cpu_to_le_16(RTE_MIN(BNXT_VNIC_MAX_SUPPORTED_ID,
+ bp->max_rsscos_ctx));
+ } else {
+ req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
+ }
+
if (bp->vf_resv_strategy ==
HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
@@ -1936,25 +1954,10 @@ static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cp
int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
- int rc = 0, i, j;
+ int rc = 0;
struct hwrm_vnic_alloc_input req = { 0 };
struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
- if (!BNXT_HAS_RING_GRPS(bp))
- goto skip_ring_grps;
-
- /* map ring groups to this vnic */
- PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
- vnic->start_grp_id, vnic->end_grp_id);
- for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
- vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
-
- vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
- vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
- vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
- vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
-
-skip_ring_grps:
vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
@@ -2068,7 +2071,8 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
*/
for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
rxq = bp->eth_dev->data->rx_queues[i];
- if (rxq->rx_started) {
+ if (rxq->rx_started &&
+ bnxt_vnic_queue_id_is_valid(vnic, i)) {
dflt_rxq = i;
break;
}
@@ -2298,14 +2302,22 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
- req.hash_mode_flags = vnic->hash_mode;
+ /* When the vnic_id in the request field is a valid
+ * one, the hash_mode_flags in the request field must
+ * be set to DEFAULT. And any request to change the
+ * default behavior must be done in a separate call
+ * to HWRM_VNIC_RSS_CFG by exclusively setting hash
+ * mode and vnic_id, rss_ctx_idx to INVALID.
+ */
+ req.hash_mode_flags = BNXT_HASH_MODE_DEFAULT;
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.ring_grp_tbl_addr =
rte_cpu_to_le_64(vnic->rss_table_dma_addr +
- i * HW_HASH_INDEX_SIZE);
+ i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
+ 2 * sizeof(uint16_t));
req.ring_table_pair_index = i;
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
@@ -2314,23 +2326,74 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
+ PMD_DRV_LOG(DEBUG, "RSS CFG: Hash level %d\n", req.hash_mode_flags);
}
return rc;
}
-int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
- struct bnxt_vnic_info *vnic)
+static int
+bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
- int rc = 0;
- struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
+ int rc = 0;
- if (!vnic->rss_table)
+ /* The reason we are returning success here is that this
+ * call is in the context of user/stack RSS configuration.
+ * Even though OUTER RSS is not supported, the normal RSS
+ * configuration should continue to work.
+ */
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)))
return 0;
- if (BNXT_CHIP_P5(bp))
- return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
+ /* Don't call RSS hash level configuration if the current
+ * hash level is the same as the hash level that is requested.
+ */
+ if (vnic->prev_hash_mode == vnic->hash_mode)
+ return 0;
+
+ HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
+
+ /* For FW, hash_mode == DEFAULT means that
+ * the FW is capable of doing INNER & OUTER RSS as well.
+ * DEFAULT doesn't mean that the FW is
+ * going to change the hash_mode to INNER. However, for
+ * the USER, DEFAULT means, change the hash mode to the
+ * NIC's DEFAULT hash mode which is INNER.
+ *
+ * Hence, driver should make the translation of hash_mode
+ * to INNERMOST when hash_mode from the dpdk stack is
+ * DEFAULT.
+ */
+ if (vnic->hash_mode == BNXT_HASH_MODE_DEFAULT)
+ req.hash_mode_flags = BNXT_HASH_MODE_INNERMOST;
+ else
+ req.hash_mode_flags = vnic->hash_mode;
+ req.vnic_id = rte_cpu_to_le_16(BNXT_DFLT_VNIC_ID_INVALID);
+ req.rss_ctx_idx = rte_cpu_to_le_16(BNXT_RSS_CTX_IDX_INVALID);
+
+ PMD_DRV_LOG(DEBUG, "RSS CFG: Hash level %d\n", req.hash_mode_flags);
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
+ BNXT_USE_CHIMP_MB);
+
+ HWRM_CHECK_RESULT();
+ /* Store the programmed hash_mode in prev_hash_mode so that
+ * it can checked against the next user requested hash mode.
+ */
+ if (!rc)
+ vnic->prev_hash_mode = vnic->hash_mode;
+ HWRM_UNLOCK();
+ return rc;
+}
+
+static int
+bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
+ struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc = 0;
HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
@@ -2352,6 +2415,39 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
return rc;
}
+int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ int rc = 0;
+
+ if (!vnic->rss_table)
+ return 0;
+
+ if (BNXT_CHIP_P5(bp)) {
+ rc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
+ if (rc)
+ return rc;
+ /* Configuring the hash mode has to be done in a
+ * different VNIC_RSS_CFG HWRM command by setting
+ * vnic_id & rss_ctx_id to INVALID. The only
+ * exception to this is if the USER doesn't want
+ * to change the default behavior. So, ideally
+ * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 should be
+ * called when user is explicitly changing the hash
+ * mode. However, this logic will unconditionally
+ * call bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 to
+ * simplify the logic as there is no harm in calling
+ * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 even when
+ * user is not setting it explicitly. Because, this
+ * routine will convert the default value to inner
+ * which is our adapter's default behavior.
+ */
+ return bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(bp, vnic);
+ }
+
+ return bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic);
+}
+
int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
struct bnxt_vnic_info *vnic)
{
@@ -2893,6 +2989,7 @@ void bnxt_free_all_hwrm_resources(struct bnxt *bp)
bnxt_hwrm_vnic_free(bp, vnic);
rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
}
/* Ring resources */
bnxt_free_all_hwrm_rings(bp);
@@ -3977,6 +4074,36 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
return rc;
}
+int bnxt_hwrm_tunnel_upar_id_get(struct bnxt *bp, uint8_t *upar_id,
+ uint8_t tunnel_type)
+{
+ struct hwrm_tunnel_dst_port_query_input req = {0};
+ struct hwrm_tunnel_dst_port_query_output *resp = bp->hwrm_cmd_resp_addr;
+ int rc = 0;
+
+ HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_QUERY, BNXT_USE_CHIMP_MB);
+ req.tunnel_type = tunnel_type;
+ rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+ HWRM_CHECK_RESULT();
+
+ switch (tunnel_type) {
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI:
+ *upar_id = resp->upar_in_use;
+ break;
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6:
+ *upar_id = resp->upar_in_use;
+ break;
+ default:
+ /* INVALID UPAR Id if another tunnel type tries to retrieve */
+ *upar_id = 0xff;
+ break;
+ }
+
+ HWRM_UNLOCK();
+
+ return rc;
+}
+
int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type)
{
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index f9d9fe0ef2..68384bc757 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -109,7 +109,31 @@ struct bnxt_pf_resource_info {
uint32_t num_hw_ring_grps;
};
-#define BNXT_CTX_VAL_INVAL 0xFFFF
+#define BNXT_CTX_VAL_INVAL 0xFFFF
+#define BNXT_RSS_CTX_IDX_INVALID 0xFFFF
+
+#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
+#define BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP))
+
+/*
+ * If the device supports VXLAN, GRE, IPIP and GENEVE tunnel parsing, then report
+ * RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM and
+ * RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM in the Rx/Tx offload capabilities of the device.
+ */
+#define BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp) \
+ (BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+
+#define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ
+#define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) \
(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
@@ -227,6 +251,8 @@ int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf);
int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type);
+int bnxt_hwrm_tunnel_upar_id_get(struct bnxt *bp, uint8_t *upar_id,
+ uint8_t tunnel_type);
int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
uint8_t tunnel_type);
int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf);
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 4cdbb177d9..686c3af4da 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -54,7 +54,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp)
return -EBUSY;
}
- /* THOR does not support ring groups.
+ /* P5 does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
if (BNXT_CHIP_P5(bp)) {
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index 99758dd304..0d0b5e28e4 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -400,7 +400,7 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
rxq->rx_deferred_start = rx_conf->rx_deferred_start;
rxq->rx_started = rxq->rx_deferred_start ? false : true;
- rxq->vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ rxq->vnic = bnxt_get_default_vnic(bp);
return 0;
err:
@@ -460,6 +460,8 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_rx_queue *rxq = bp->rx_queues[rx_queue_id];
struct bnxt_vnic_info *vnic = NULL;
+ uint16_t vnic_idx = 0;
+ uint16_t fw_grp_id = 0;
int rc = 0;
rc = is_bnxt_in_error(bp);
@@ -471,6 +473,13 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return -EINVAL;
}
+ vnic = bnxt_vnic_queue_id_get_next(bp, rx_queue_id, &vnic_idx);
+ if (vnic == NULL) {
+ PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n",
+ rx_queue_id);
+ return -EINVAL;
+ }
+
/* reset the previous stats for the rx_queue since the counters
* will be cleared when the queue is started.
*/
@@ -490,29 +499,37 @@ int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return rc;
if (BNXT_HAS_RING_GRPS(bp))
- rxq->vnic->dflt_ring_grp = bp->grp_info[rx_queue_id].fw_grp_id;
- /* Reconfigure default receive ring and MRU. */
- bnxt_hwrm_vnic_cfg(bp, rxq->vnic);
-
- PMD_DRV_LOG(INFO, "Rx queue started %d\n", rx_queue_id);
+ fw_grp_id = bp->grp_info[rx_queue_id].fw_grp_id;
- if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
- vnic = rxq->vnic;
+ do {
+ if (BNXT_HAS_RING_GRPS(bp))
+ vnic->dflt_ring_grp = fw_grp_id;
+ /* Reconfigure default receive ring and MRU. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+
+ PMD_DRV_LOG(INFO, "Rx queue started %d\n", rx_queue_id);
+
+ if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
+ if (BNXT_HAS_RING_GRPS(bp)) {
+ if (vnic->fw_grp_ids[rx_queue_id] !=
+ INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "invalid ring id %d\n",
+ rx_queue_id);
+ return 0;
+ }
- if (BNXT_HAS_RING_GRPS(bp)) {
- if (vnic->fw_grp_ids[rx_queue_id] != INVALID_HW_RING_ID)
- return 0;
+ vnic->fw_grp_ids[rx_queue_id] = fw_grp_id;
+ PMD_DRV_LOG(DEBUG, "vnic = %p fw_grp_id = %d\n",
+ vnic, fw_grp_id);
+ }
- vnic->fw_grp_ids[rx_queue_id] =
- bp->grp_info[rx_queue_id].fw_grp_id;
- PMD_DRV_LOG(DEBUG,
- "vnic = %p fw_grp_id = %d\n",
- vnic, bp->grp_info[rx_queue_id].fw_grp_id);
+ PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n",
+ vnic->rx_queue_cnt);
+ rc += bnxt_vnic_rss_queue_status_update(bp, vnic);
}
-
- PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
- rc = bnxt_vnic_rss_configure(bp, vnic);
- }
+ vnic_idx++;
+ } while ((vnic = bnxt_vnic_queue_id_get_next(bp, rx_queue_id,
+ &vnic_idx)) != NULL);
if (rc != 0) {
dev->data->rx_queue_state[rx_queue_id] =
@@ -535,6 +552,7 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
struct bnxt_vnic_info *vnic = NULL;
struct bnxt_rx_queue *rxq = NULL;
int active_queue_cnt = 0;
+ uint16_t vnic_idx = 0, q_id = rx_queue_id;
int i, rc = 0;
rc = is_bnxt_in_error(bp);
@@ -556,61 +574,64 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
return -EINVAL;
}
- vnic = rxq->vnic;
+ vnic = bnxt_vnic_queue_id_get_next(bp, q_id, &vnic_idx);
if (!vnic) {
- PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n",
- rx_queue_id);
+ PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n", q_id);
return -EINVAL;
}
- dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
+ dev->data->rx_queue_state[q_id] = RTE_ETH_QUEUE_STATE_STOPPED;
rxq->rx_started = false;
PMD_DRV_LOG(DEBUG, "Rx queue stopped\n");
- if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
- if (BNXT_HAS_RING_GRPS(bp))
- vnic->fw_grp_ids[rx_queue_id] = INVALID_HW_RING_ID;
-
- PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
- rc = bnxt_vnic_rss_configure(bp, vnic);
- }
-
- /* Compute current number of active receive queues. */
- for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
- if (bp->rx_queues[i]->rx_started)
- active_queue_cnt++;
+ do {
+ active_queue_cnt = 0;
+ if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
+ if (BNXT_HAS_RING_GRPS(bp))
+ vnic->fw_grp_ids[q_id] = INVALID_HW_RING_ID;
- if (BNXT_CHIP_P5(bp)) {
- /*
- * For Thor, we need to ensure that the VNIC default receive
- * ring corresponds to an active receive queue. When no queue
- * is active, we need to temporarily set the MRU to zero so
- * that packets are dropped early in the receive pipeline in
- * order to prevent the VNIC default receive ring from being
- * accessed.
- */
- if (active_queue_cnt == 0) {
- uint16_t saved_mru = vnic->mru;
-
- /* clear RSS setting on vnic. */
- bnxt_vnic_rss_clear_p5(bp, vnic);
-
- vnic->mru = 0;
- /* Reconfigure default receive ring and MRU. */
- bnxt_hwrm_vnic_cfg(bp, vnic);
- vnic->mru = saved_mru;
- } else {
- /* Reconfigure default receive ring. */
- bnxt_hwrm_vnic_cfg(bp, vnic);
+ PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n",
+ vnic->rx_queue_cnt);
+ rc = bnxt_vnic_rss_queue_status_update(bp, vnic);
}
- } else if (active_queue_cnt) {
- /*
- * If the queue being stopped is the current default queue and
- * there are other active queues, pick one of them as the
- * default and reconfigure the vnic.
- */
- if (vnic->dflt_ring_grp == bp->grp_info[rx_queue_id].fw_grp_id) {
- for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
+
+ /* Compute current number of active receive queues. */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
+ if (bp->rx_queues[i]->rx_started)
+ active_queue_cnt++;
+
+ if (BNXT_CHIP_P5(bp)) {
+ /*
+ * For P5, we need to ensure that the VNIC default
+ * receive ring corresponds to an active receive queue.
+ * When no queue is active, we need to temporarily set
+ * the MRU to zero so that packets are dropped early in
+ * the receive pipeline in order to prevent the VNIC
+ * default receive ring from being accessed.
+ */
+ if (active_queue_cnt == 0) {
+ uint16_t saved_mru = vnic->mru;
+
+ /* clear RSS setting on vnic. */
+ bnxt_vnic_rss_clear_p5(bp, vnic);
+
+ vnic->mru = 0;
+ /* Reconfigure default receive ring and MRU. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+ vnic->mru = saved_mru;
+ } else {
+ /* Reconfigure default receive ring. */
+ bnxt_hwrm_vnic_cfg(bp, vnic);
+ }
+ } else if (active_queue_cnt && vnic->dflt_ring_grp ==
+ bp->grp_info[q_id].fw_grp_id) {
+ /*
+ * If the queue being stopped is the current default
+ * queue and there are other active queues, pick one of
+ * them as the default and reconfigure the vnic.
+ */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id;
+ i++) {
if (bp->rx_queues[i]->rx_started) {
vnic->dflt_ring_grp =
bp->grp_info[i].fw_grp_id;
@@ -619,7 +640,9 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
}
}
}
- }
+ vnic_idx++;
+ } while ((vnic = bnxt_vnic_queue_id_get_next(bp, q_id,
+ &vnic_idx)) != NULL);
if (rc == 0)
bnxt_rx_queue_release_mbufs(rxq);
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index a067278dca..1ab0ef2f5d 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -691,7 +691,7 @@ static void
bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
{
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
- uint64_t last_hwrm_time;
+ uint64_t last_hwrm_time = 0;
uint64_t pkt_time = 0;
if (!BNXT_CHIP_P5(bp) || !ptp)
@@ -705,7 +705,6 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
* from the HWRM response with the lower 32 bits in the
* Rx completion to produce the 48 bit timestamp for the Rx packet
*/
- last_hwrm_time = ptp->current_time;
pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
/* timer has rolled over */
@@ -923,7 +922,7 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
- RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
+ RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
@@ -1089,6 +1088,7 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
break;
}
+ cpr->cp_raw_cons = raw_cons;
if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) {
/*
* For PMD, there is no need to keep on pushing to REARM
@@ -1097,7 +1097,6 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
goto done;
}
- cpr->cp_raw_cons = raw_cons;
/* Ring the completion queue doorbell. */
bnxt_db_cq(cpr);
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index c8745add5e..d1d1fe8f1f 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 21c2217092..10b716a00b 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 75456df5bd..b9b8a9b1a2 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c
index b3c03a2af5..be9c127b64 100644
--- a/drivers/net/bnxt/bnxt_vnic.c
+++ b/drivers/net/bnxt/bnxt_vnic.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -9,8 +9,26 @@
#include <rte_malloc.h>
#include "bnxt.h"
+#include "bnxt_rxq.h"
+#include "bnxt_rxr.h"
+#include "bnxt_ring.h"
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
+#include "bnxt_hwrm.h"
+
+/* Macros to manipulate vnic bitmaps*/
+#define BNXT_VNIC_BITMAP_SIZE 64
+#define BNXT_VNIC_BITMAP_SET(b, i) ((b[(i) / BNXT_VNIC_BITMAP_SIZE]) |= \
+ (1UL << ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE))))
+
+#define BNXT_VNIC_BITMAP_RESET(b, i) ((b[(i) / BNXT_VNIC_BITMAP_SIZE]) &= \
+ (~(1UL << ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE)))))
+
+#define BNXT_VNIC_BITMAP_GET(b, i) (((b[(i) / BNXT_VNIC_BITMAP_SIZE]) >> \
+ ((BNXT_VNIC_BITMAP_SIZE - 1) - \
+ ((i) % BNXT_VNIC_BITMAP_SIZE))) & 1)
/*
* VNIC Functions
@@ -51,6 +69,8 @@ static void bnxt_init_vnics(struct bnxt *bp)
vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
vnic->hash_mode =
HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
+ vnic->prev_hash_mode =
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
vnic->rx_queue_cnt = 0;
STAILQ_INIT(&vnic->filter);
@@ -84,6 +104,11 @@ void bnxt_free_all_vnics(struct bnxt *bp)
for (i = 0; i < bp->max_vnics; i++) {
vnic = &bp->vnic_info[i];
STAILQ_INSERT_TAIL(&bp->free_vnic_list, vnic, next);
+ if (vnic->ref_cnt) {
+ /* clean up the default vnic details */
+ bnxt_vnic_rss_action_free(bp, i);
+ }
+
vnic->rx_queue_cnt = 0;
}
}
@@ -212,6 +237,7 @@ int bnxt_alloc_vnic_mem(struct bnxt *bp)
int bnxt_vnic_grp_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
+ uint32_t i;
vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
if (!vnic->fw_grp_ids) {
@@ -220,7 +246,10 @@ int bnxt_vnic_grp_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
size);
return -ENOMEM;
}
- memset(vnic->fw_grp_ids, -1, size);
+
+ /* Initialize to invalid ring id */
+ for (i = 0; i < bp->max_ring_grps; i++)
+ vnic->fw_grp_ids[i] = INVALID_HW_RING_ID;
return 0;
}
@@ -259,30 +288,27 @@ int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl)
/* If FW has not advertised capability to configure outer/inner
* RSS hashing , just log a message. HW will work in default RSS mode.
*/
- if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)) {
- PMD_DRV_LOG(ERR, "RSS hash level cannot be configured\n");
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS))) {
+ if (lvl)
+ PMD_DRV_LOG(INFO,
+ "Given RSS level is unsupported, using default RSS level\n");
return mode;
}
switch (lvl) {
case BNXT_RSS_LEVEL_INNERMOST:
- if (l3_and_l4 || l4)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4;
- else if (l3_only)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2;
+ /* Irrespective of what RTE says, FW always does 4 tuple */
+ if (l3_and_l4 || l4 || l3_only)
+ mode = BNXT_HASH_MODE_INNERMOST;
break;
case BNXT_RSS_LEVEL_OUTERMOST:
- if (l3_and_l4 || l4)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4;
- else if (l3_only)
- mode =
- HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2;
+ /* Irrespective of what RTE says, FW always does 4 tuple */
+ if (l3_and_l4 || l4 || l3_only)
+ mode = BNXT_HASH_MODE_OUTERMOST;
break;
default:
- mode = HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
+ mode = BNXT_HASH_MODE_DEFAULT;
break;
}
@@ -296,7 +322,8 @@ uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode)
/* If FW has not advertised capability to configure inner/outer RSS
* return default hash mode.
*/
- if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS))
+ if ((BNXT_CHIP_P5(bp) && BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp)) ||
+ (!BNXT_CHIP_P5(bp) && !(bp->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)))
return RTE_ETH_RSS_LEVEL_PMD_DEFAULT;
if (mode == HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 ||
@@ -310,3 +337,909 @@ uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode)
return rss_level;
}
+
+static
+int32_t bnxt_vnic_populate_rss_table_p5(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ uint32_t ctx_idx = 0, rss_idx = 0, cnt = 0;
+ uint32_t q_id = -1;
+ struct bnxt_rx_queue *rxq;
+ uint16_t *ring_tbl = vnic->rss_table;
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ uint16_t ring_id;
+
+ /* For P5 platform */
+ for (ctx_idx = 0; ctx_idx < vnic->num_lb_ctxts; ctx_idx++) {
+ for (rss_idx = 0; rss_idx < BNXT_RSS_ENTRIES_PER_CTX_P5;
+ rss_idx++) {
+ /* Find next active ring. */
+ for (cnt = 0; cnt < BNXT_VNIC_MAX_QUEUE_SIZE; cnt++) {
+ if (++q_id == bp->rx_nr_rings)
+ q_id = 0; /* reset the q_id */
+ if (BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ q_id) &&
+ rx_queue_state[q_id] !=
+ RTE_ETH_QUEUE_STATE_STOPPED)
+ break;
+ }
+
+ /* no active queues exit */
+ if (cnt == BNXT_VNIC_MAX_QUEUE_SIZE)
+ return 0;
+
+ rxq = bp->rx_queues[q_id];
+ ring_id = rxq->rx_ring->rx_ring_struct->fw_ring_id;
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ ring_id = rxq->cp_ring->cp_ring_struct->fw_ring_id;
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ }
+ }
+ return 0;
+}
+
+static
+int32_t bnxt_vnic_populate_rss_table_p4(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ uint32_t rss_idx = 0, cnt = 0;
+ uint32_t q_id = -1;
+ uint16_t *ring_tbl = vnic->rss_table;
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ uint16_t ring_id;
+
+ /* For Wh+ platform */
+ for (rss_idx = 0; rss_idx < bnxt_rss_hash_tbl_size(bp); rss_idx++) {
+ /* Find next active ring. */
+ for (cnt = 0; cnt < BNXT_VNIC_MAX_QUEUE_SIZE; cnt++) {
+ if (++q_id == bp->rx_nr_rings)
+ q_id = 0; /* reset the q_id */
+ if (BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ q_id) &&
+ rx_queue_state[q_id] !=
+ RTE_ETH_QUEUE_STATE_STOPPED)
+ break;
+ }
+
+ /* no active queues exit */
+ if (cnt == BNXT_VNIC_MAX_QUEUE_SIZE)
+ return 0;
+
+ ring_id = vnic->fw_grp_ids[q_id];
+ *ring_tbl++ = rte_cpu_to_le_16(ring_id);
+ }
+ return 0;
+}
+
+static
+int32_t bnxt_vnic_populate_rss_table(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ /* RSS table population is different for p4 and p5 platforms */
+ if (BNXT_CHIP_P5(bp))
+ return bnxt_vnic_populate_rss_table_p5(bp, vnic);
+
+ return bnxt_vnic_populate_rss_table_p4(bp, vnic);
+}
+
+static void
+bnxt_vnic_queue_delete(struct bnxt *bp, uint16_t vnic_idx)
+{
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_idx];
+
+ if (bnxt_hwrm_vnic_free(bp, vnic))
+ PMD_DRV_LOG(ERR, "Failed to delete queue\n");
+
+ if (vnic->fw_grp_ids) {
+ rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
+ }
+
+ vnic->rx_queue_cnt = 0;
+ if (bp->nr_vnics)
+ bp->nr_vnics--;
+
+ /* reset the queue_bitmap */
+ memset(vnic->queue_bitmap, 0, sizeof(vnic->queue_bitmap));
+}
+
+static struct bnxt_vnic_info*
+bnxt_vnic_queue_create(struct bnxt *bp, int32_t vnic_id, uint16_t q_index)
+{
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ struct bnxt_vnic_info *vnic;
+ struct bnxt_rx_queue *rxq = NULL;
+ int32_t rc = -EINVAL;
+ uint16_t saved_mru = 0;
+
+ vnic = &bp->vnic_info[vnic_id];
+ if (vnic->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "invalid queue configuration %d\n", vnic_id);
+ return NULL;
+ }
+
+ /* set the queue_bitmap */
+ BNXT_VNIC_BITMAP_SET(vnic->queue_bitmap, q_index);
+
+ rxq = bp->rx_queues[q_index];
+ if (rx_queue_state[q_index] == RTE_ETH_QUEUE_STATE_STOPPED)
+ rxq->rx_started = 0;
+ else
+ rxq->rx_started = 1;
+
+ vnic->rx_queue_cnt++;
+ vnic->start_grp_id = q_index;
+ vnic->end_grp_id = q_index + 1;
+ vnic->func_default = 0; /* This is not a default VNIC. */
+ bp->nr_vnics++;
+
+ /* Allocate vnic group for p4 platform */
+ rc = bnxt_vnic_grp_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to allocate vnic groups\n");
+ goto cleanup;
+ }
+
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
+ rc = bnxt_hwrm_vnic_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to allocate vnic %d\n", q_index);
+ goto cleanup;
+ }
+
+ /* store the mru so we can set it to zero in hw */
+ if (rxq->rx_started == 0) {
+ saved_mru = vnic->mru;
+ vnic->mru = 0;
+ }
+
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ if (rxq->rx_started == 0)
+ vnic->mru = saved_mru;
+
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to configure vnic %d\n", q_index);
+ goto cleanup;
+ }
+
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(DEBUG, "Failed to configure vnic plcmode %d\n",
+ q_index);
+ goto cleanup;
+ }
+
+ vnic->ref_cnt++;
+ return vnic;
+
+cleanup:
+ bnxt_vnic_queue_delete(bp, vnic_id);
+ return NULL;
+}
+
+static inline int32_t
+bnxt_vnic_queue_db_lookup(struct bnxt *bp, uint64_t *q_list)
+{
+ /* lookup in the database to check if it is in use */
+ return rte_hash_lookup(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+}
+
+static inline int32_t
+bnxt_vnic_queue_db_del(struct bnxt *bp, uint64_t *q_list)
+{
+ return rte_hash_del_key(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+}
+
+static int32_t
+bnxt_vnic_queue_db_add(struct bnxt *bp, uint64_t *q_list)
+{
+ struct bnxt_vnic_info *vnic_info;
+ int32_t vnic_id, rc = -1;
+
+ vnic_id = rte_hash_add_key(bp->vnic_queue_db.rss_q_db,
+ (const void *)q_list);
+
+ if (vnic_id < 0 || vnic_id >= bp->max_vnics) {
+ PMD_DRV_LOG(DEBUG, "unable to assign vnic index %d\n",
+ vnic_id);
+ return rc;
+ }
+
+ vnic_info = &bp->vnic_info[vnic_id];
+ if (vnic_info->fw_vnic_id != INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(DEBUG, "Invalid ring id for %d.\n", vnic_id);
+ return rc;
+ }
+ return vnic_id;
+}
+
+/* Function to validate the incoming rss configuration */
+static
+int32_t bnxt_vnic_queue_db_rss_validate(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ int32_t *vnic_idx)
+{
+ struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
+ int32_t rc = -EINVAL;
+ uint32_t idx = 0;
+ int32_t out_idx;
+
+ if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS)) {
+ PMD_DRV_LOG(ERR, "Error Rss is not supported on this port\n");
+ return rc;
+ }
+
+ /* rss queue is zero then use the default vnic */
+ if (rss_info->queue_num == 0) {
+ *vnic_idx = 0;
+ return 0;
+ }
+
+ /* Check to see if the queues id are in supported range */
+ if (rss_info->queue_num > bp->rx_nr_rings) {
+ PMD_DRV_LOG(ERR, "Error unsupported queue num.\n");
+ return rc;
+ }
+
+ /* validate the queue ids are in correct range */
+ for (idx = 0; idx < BNXT_VNIC_MAX_QUEUE_SIZE; idx++) {
+ if (BNXT_VNIC_BITMAP_GET(rss_info->queue_list, idx)) {
+ if (idx >= bp->rx_nr_rings) {
+ PMD_DRV_LOG(ERR,
+ "Error %d beyond support size %u\n",
+ idx, bp->rx_nr_rings);
+ return rc;
+ }
+ }
+ }
+
+ /* check if the vnic already exist */
+ out_idx = bnxt_vnic_queue_db_lookup(bp, rss_info->queue_list);
+ if (out_idx < 0 || out_idx >= bp->max_vnics)
+ return -ENOENT; /* entry not found */
+
+ /* found an entry */
+ *vnic_idx = out_idx;
+ return 0;
+}
+
+static void
+bnxt_vnic_rss_delete(struct bnxt *bp, uint16_t q_index)
+{
+ struct bnxt_vnic_info *vnic;
+
+ vnic = &bp->vnic_info[q_index];
+ if (vnic->rx_queue_cnt >= 1)
+ bnxt_hwrm_vnic_ctx_free(bp, vnic);
+
+ if (vnic->fw_vnic_id != INVALID_HW_RING_ID)
+ bnxt_hwrm_vnic_free(bp, vnic);
+
+ if (vnic->fw_grp_ids) {
+ rte_free(vnic->fw_grp_ids);
+ vnic->fw_grp_ids = NULL;
+ }
+
+ /* Update the vnic details for all the rx queues */
+ vnic->rx_queue_cnt = 0;
+ memset(vnic->queue_bitmap, 0, sizeof(vnic->queue_bitmap));
+
+ if (bp->nr_vnics)
+ bp->nr_vnics--;
+}
+
+/* The validation of the rss_info should be done before calling this function*/
+
+static struct bnxt_vnic_info *
+bnxt_vnic_rss_create(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t vnic_id)
+{
+ uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
+ struct bnxt_vnic_info *vnic;
+ struct bnxt_rx_queue *rxq = NULL;
+ uint32_t idx, nr_ctxs, config_rss = 0;
+ uint16_t saved_mru = 0;
+ uint16_t active_q_cnt = 0;
+ int16_t first_q = -1;
+ int16_t end_q = -1;
+ int32_t rc = 0;
+
+ /* Assign the vnic to be used for this rss configuration */
+ vnic = &bp->vnic_info[vnic_id];
+
+ /* Update the vnic details for all the rx queues */
+ for (idx = 0; idx < BNXT_VNIC_MAX_QUEUE_SIZE; idx++) {
+ if (BNXT_VNIC_BITMAP_GET(rss_info->queue_list, idx)) {
+ rxq = bp->rx_queues[idx];
+ if (rx_queue_state[idx] ==
+ RTE_ETH_QUEUE_STATE_STOPPED) {
+ rxq->rx_started = 0;
+ } else {
+ rxq->rx_started = 1;
+ active_q_cnt++;
+ }
+ vnic->rx_queue_cnt++;
+
+ /* Update the queue list */
+ BNXT_VNIC_BITMAP_SET(vnic->queue_bitmap, idx);
+ if (first_q == -1)
+ first_q = idx;
+ end_q = idx;
+ }
+ }
+ vnic->start_grp_id = first_q;
+ vnic->end_grp_id = end_q + 1;
+ vnic->func_default = 0; /* This is not a default VNIC. */
+ bp->nr_vnics++;
+
+ /* Allocate vnic group for p4 platform */
+ rc = bnxt_vnic_grp_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to allocate vnic groups\n");
+ goto fail_cleanup;
+ }
+
+ /* populate the fw group table */
+ bnxt_vnic_ring_grp_populate(bp, vnic);
+ bnxt_vnic_rules_init(vnic);
+
+ /* Allocate the vnic in the firmware */
+ rc = bnxt_hwrm_vnic_alloc(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to allocate vnic %d\n", idx);
+ goto fail_cleanup;
+ }
+
+ /* Allocate the vnic rss context */
+ /* RSS table size in P5 is 512. Cap max Rx rings to same value */
+ nr_ctxs = bnxt_rss_ctxts(bp);
+ for (idx = 0; idx < nr_ctxs; idx++) {
+ rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, idx);
+ if (rc)
+ break;
+ }
+ if (rc) {
+ PMD_DRV_LOG(ERR,
+ "HWRM ctx %d alloc failure rc: %x\n", idx, rc);
+ goto fail_cleanup;
+ }
+ vnic->num_lb_ctxts = nr_ctxs;
+
+ saved_mru = vnic->mru;
+ if (!active_q_cnt)
+ vnic->mru = 0;
+
+ /* configure the vnic details in firmware */
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ vnic->mru = saved_mru;
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to configure vnic %d\n", idx);
+ goto fail_cleanup;
+ }
+
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to configure vnic plcmode %d\n",
+ idx);
+ goto fail_cleanup;
+ }
+
+ /* hwrm_type conversion */
+ vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_info->rss_types);
+ vnic->hash_mode = bnxt_rte_to_hwrm_hash_level(bp, rss_info->rss_types,
+ rss_info->rss_level);
+
+ /* configure the key */
+ if (!rss_info->key_len)
+ /* If hash key has not been specified, use random hash key.*/
+ bnxt_prandom_bytes(vnic->rss_hash_key, HW_HASH_KEY_SIZE);
+ else
+ memcpy(vnic->rss_hash_key, rss_info->key, rss_info->key_len);
+
+ /* Prepare the indirection table */
+ bnxt_vnic_populate_rss_table(bp, vnic);
+
+ /* check to see if there is at least one queue that is active */
+ for (idx = vnic->start_grp_id; idx < vnic->end_grp_id; idx++) {
+ if (bnxt_vnic_queue_id_is_valid(vnic, idx) &&
+ bp->rx_queues[idx]->rx_started) {
+ config_rss = 1;
+ break;
+ }
+ }
+
+ /* configure the rss table */
+ if (config_rss) {
+ rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+ if (rc) {
+ memset(vnic->rss_hash_key, 0, HW_HASH_KEY_SIZE);
+ PMD_DRV_LOG(ERR,
+ "Failed to configure vnic rss details %d\n",
+ idx);
+ goto fail_cleanup;
+ }
+ }
+
+ vnic->ref_cnt++;
+ return vnic;
+
+fail_cleanup:
+ bnxt_vnic_rss_delete(bp, idx);
+ return NULL;
+}
+
+int32_t
+bnxt_vnic_rss_queue_status_update(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
+ return 0;
+
+ if (!(vnic->rss_table && vnic->hash_type))
+ return 0;
+
+ /* Prepare the indirection table */
+ bnxt_vnic_populate_rss_table(bp, vnic);
+
+ /* configure the rss table */
+ if (bnxt_hwrm_vnic_rss_cfg(bp, vnic)) {
+ PMD_DRV_LOG(DEBUG, "Failed to update vnic rss details\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int32_t
+bnxt_vnic_rss_hash_algo_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic,
+ struct bnxt_vnic_rss_info *rss_info)
+{
+ uint8_t old_rss_hash_key[HW_HASH_KEY_SIZE] = { 0 };
+ uint16_t hash_type;
+ uint8_t hash_mode;
+ uint32_t apply = 0;
+
+ /* validate key length */
+ if (rss_info->key_len != 0 && rss_info->key_len != HW_HASH_KEY_SIZE) {
+ PMD_DRV_LOG(ERR,
+ "Invalid hashkey length, should be %d bytes\n",
+ HW_HASH_KEY_SIZE);
+ return -EINVAL;
+ }
+
+ /* hwrm_type conversion */
+ hash_type = bnxt_rte_to_hwrm_hash_types(rss_info->rss_types);
+ hash_mode = bnxt_rte_to_hwrm_hash_level(bp, rss_info->rss_types,
+ rss_info->rss_level);
+ if (vnic->hash_mode != hash_mode ||
+ vnic->hash_type != hash_type) {
+ apply = 1;
+ vnic->hash_mode = hash_mode;
+ vnic->hash_type = hash_type;
+ }
+ /* Store the old hash key before programming the new one. It will
+ * be used to restore the old hash key when HWRM_VNIC_RSS_CFG
+ * fails.
+ */
+ memcpy(old_rss_hash_key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
+ if (rss_info->key_len != 0 && memcmp(rss_info->key, vnic->rss_hash_key,
+ HW_HASH_KEY_SIZE)) {
+ apply = 1;
+ memcpy(vnic->rss_hash_key, rss_info->key, HW_HASH_KEY_SIZE);
+ }
+
+ if (apply) {
+ if (bnxt_hwrm_vnic_rss_cfg(bp, vnic)) {
+ memcpy(vnic->rss_hash_key, old_rss_hash_key, HW_HASH_KEY_SIZE);
+ BNXT_TF_DBG(ERR, "Error configuring vnic RSS config\n");
+ return -EINVAL;
+ }
+ BNXT_TF_DBG(INFO, "Rss config successfully applied\n");
+ }
+ return 0;
+}
+
+int32_t bnxt_vnic_queue_db_deinit(struct bnxt *bp)
+{
+ if (bp->vnic_queue_db.rss_q_db != NULL)
+ rte_hash_free(bp->vnic_queue_db.rss_q_db);
+ return 0;
+}
+
+int32_t bnxt_vnic_queue_db_init(struct bnxt *bp)
+{
+ struct rte_hash_parameters hash_tbl_params = {0};
+ char hash_tbl_name[64] = {0};
+
+ /* choose the least supported value */
+ if (bp->rx_nr_rings > BNXT_VNIC_MAX_QUEUE_SIZE)
+ bp->vnic_queue_db.num_queues = BNXT_VNIC_MAX_QUEUE_SIZE;
+ else
+ bp->vnic_queue_db.num_queues = bp->rx_nr_rings;
+
+ /* create the hash table for the rss hash entries */
+ snprintf(hash_tbl_name, sizeof(hash_tbl_name),
+ "bnxt_rss_hash_%d", bp->eth_dev->data->port_id);
+ hash_tbl_params.name = hash_tbl_name;
+ hash_tbl_params.entries = (bp->max_vnics > BNXT_VNIC_MAX_SUPPORTED_ID) ?
+ BNXT_VNIC_MAX_SUPPORTED_ID : bp->max_vnics;
+ hash_tbl_params.key_len = BNXT_VNIC_MAX_QUEUE_SZ_IN_8BITS;
+ hash_tbl_params.socket_id = rte_socket_id();
+ bp->vnic_queue_db.rss_q_db = rte_hash_create(&hash_tbl_params);
+ if (bp->vnic_queue_db.rss_q_db == NULL) {
+ PMD_DRV_LOG(ERR, "Failed to create rss hash tbl\n");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+void bnxt_vnic_queue_db_update_dlft_vnic(struct bnxt *bp)
+{
+ struct bnxt_vnic_info *dflt_vnic;
+ uint64_t bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+ uint32_t idx;
+ int32_t vnic_id;
+
+ /* populate all the queue ids in the default vnic */
+ memset(bitmap, 0, sizeof(bitmap));
+ for (idx = 0; idx < bp->vnic_queue_db.num_queues; idx++)
+ BNXT_VNIC_BITMAP_SET(bitmap, idx);
+
+ vnic_id = bnxt_vnic_queue_db_add(bp, bitmap);
+ if (vnic_id < 0) {
+ PMD_DRV_LOG(ERR, "Unable to alloc vnic for default rss\n");
+ return;
+ }
+
+ dflt_vnic = bnxt_vnic_queue_db_get_vnic(bp, vnic_id);
+ if (dflt_vnic == NULL) {
+ PMD_DRV_LOG(ERR, "Invalid vnic for default rss %d\n", vnic_id);
+ return;
+ }
+ /* Update the default vnic structure */
+ bp->vnic_queue_db.dflt_vnic_id = vnic_id;
+ memcpy(dflt_vnic->queue_bitmap, bitmap, sizeof(bitmap));
+ dflt_vnic->rx_queue_cnt = bp->vnic_queue_db.num_queues;
+ dflt_vnic->ref_cnt++;
+}
+
+int32_t bnxt_vnic_queue_action_alloc(struct bnxt *bp,
+ uint16_t q_index,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid)
+{
+ uint64_t queue_list[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS] = {0};
+ struct bnxt_vnic_info *vnic_info;
+ int32_t idx;
+ int32_t rc = -EINVAL;
+
+ /* validate the given queue id */
+ if (q_index >= bp->rx_nr_rings || q_index >= BNXT_VNIC_MAX_QUEUE_SIZE) {
+ PMD_DRV_LOG(ERR, "invalid queue id should be less than %d\n",
+ bp->rx_nr_rings);
+ return rc;
+ }
+
+ /* Populate the queue list */
+ BNXT_VNIC_BITMAP_SET(queue_list, q_index);
+
+ /* check to see if the q_index is already in use */
+ idx = bnxt_vnic_queue_db_lookup(bp, queue_list);
+ if (idx < 0) {
+ /* Assign the vnic slot */
+ idx = bnxt_vnic_queue_db_add(bp, queue_list);
+ if (idx < 0) {
+ PMD_DRV_LOG(DEBUG, "Unable to alloc vnic for queue\n");
+ return rc;
+ }
+
+ /* Allocate a new one */
+ vnic_info = bnxt_vnic_queue_create(bp, idx, q_index);
+ if (!vnic_info) {
+ PMD_DRV_LOG(ERR, "failed to create vnic - %d\n",
+ q_index);
+ bnxt_vnic_queue_db_del(bp, queue_list);
+ return rc; /* failed */
+ }
+ } else {
+ vnic_info = bnxt_vnic_queue_db_get_vnic(bp, idx);
+ if (vnic_info == NULL) {
+ PMD_DRV_LOG(ERR, "Unable to lookup vnic for queue %d\n",
+ q_index);
+ return rc;
+ }
+ /* increment the reference count and return the vnic id */
+ vnic_info->ref_cnt++;
+ }
+ *vnic_idx = (uint16_t)idx;
+ *vnicid = vnic_info->fw_vnic_id;
+ return 0;
+}
+
+int32_t
+bnxt_vnic_queue_action_free(struct bnxt *bp, uint16_t vnic_id)
+{
+ struct bnxt_vnic_info *vnic_info;
+ int32_t rc = -EINVAL;
+ int32_t vnic_idx = vnic_id, idx;
+
+ /* validate the given vnic idx */
+ if (vnic_idx >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic idx %d\n", vnic_idx);
+ return rc;
+ }
+
+ /* validate the vnic info */
+ vnic_info = &bp->vnic_info[vnic_idx];
+ if (!vnic_info->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "Invalid vnic idx, no queues being used\n");
+ return rc;
+ }
+ if (vnic_info->ref_cnt) {
+ vnic_info->ref_cnt--;
+ if (!vnic_info->ref_cnt) {
+ idx = bnxt_vnic_queue_db_del(bp,
+ vnic_info->queue_bitmap);
+ /* Check to ensure there is no corruption */
+ if (idx != vnic_idx)
+ PMD_DRV_LOG(ERR, "bad vnic idx %d\n", vnic_idx);
+
+ bnxt_vnic_queue_delete(bp, vnic_idx);
+ }
+ }
+ return 0;
+}
+
+int32_t
+bnxt_vnic_rss_action_alloc(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid)
+{
+ struct bnxt_vnic_info *vnic_info = NULL;
+ int32_t rc = -EINVAL;
+ int32_t idx;
+
+ /* validate the given parameters */
+ rc = bnxt_vnic_queue_db_rss_validate(bp, rss_info, &idx);
+ if (rc == -EINVAL) {
+ PMD_DRV_LOG(ERR, "Failed to apply the rss action.\n");
+ return rc;
+ } else if (rc == -ENOENT) {
+ /* Allocate a new entry */
+ idx = bnxt_vnic_queue_db_add(bp, rss_info->queue_list);
+ if (idx < 0) {
+ PMD_DRV_LOG(DEBUG, "Unable to alloc vnic for rss\n");
+ return rc;
+ }
+ /* create the rss vnic */
+ vnic_info = bnxt_vnic_rss_create(bp, rss_info, idx);
+ if (!vnic_info) {
+ PMD_DRV_LOG(ERR, "Failed to create rss action.\n");
+ bnxt_vnic_queue_db_del(bp, rss_info->queue_list);
+ return rc;
+ }
+ } else {
+ vnic_info = bnxt_vnic_queue_db_get_vnic(bp, idx);
+ if (vnic_info == NULL) {
+ PMD_DRV_LOG(ERR, "Unable to lookup vnic for idx %d\n",
+ idx);
+ return rc;
+ }
+ /* increment the reference count and return the vnic id */
+ vnic_info->ref_cnt++;
+
+ /* check configuration has changed then update hash details */
+ rc = bnxt_vnic_rss_hash_algo_update(bp, vnic_info, rss_info);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Failed to update the rss action.\n");
+ return rc;
+ }
+ }
+ *vnic_idx = idx;
+ *vnicid = vnic_info->fw_vnic_id;
+ return 0;
+}
+
+/* Delete the vnic associated with the given rss action index */
+int32_t
+bnxt_vnic_rss_action_free(struct bnxt *bp, uint16_t vnic_id)
+{
+ uint64_t bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+ struct bnxt_vnic_info *vnic_info;
+ int32_t rc = -EINVAL;
+ uint64_t *q_list;
+ int32_t idx = 0;
+
+ /* validate the given vnic id */
+ if (vnic_id >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic id %d\n", vnic_id);
+ return rc;
+ }
+
+ /* validate vnic info */
+ vnic_info = &bp->vnic_info[vnic_id];
+ if (!vnic_info->rx_queue_cnt) {
+ PMD_DRV_LOG(ERR, "Invalid vnic id, not using any queues\n");
+ return rc;
+ }
+
+ if (vnic_info->ref_cnt) {
+ vnic_info->ref_cnt--;
+ if (!vnic_info->ref_cnt) {
+ if (bp->vnic_queue_db.dflt_vnic_id == vnic_id) {
+ /* in case of default queue, list can be
+ * changed by reta config so need a list
+ * with all queues populated.
+ */
+ memset(bitmap, 0, sizeof(bitmap));
+ for (idx = 0;
+ idx < bp->vnic_queue_db.num_queues;
+ idx++)
+ BNXT_VNIC_BITMAP_SET(bitmap, idx);
+ q_list = bitmap;
+ } else {
+ q_list = vnic_info->queue_bitmap;
+ }
+ idx = bnxt_vnic_queue_db_del(bp, q_list);
+
+ /* check to ensure there is no corruption */
+ if (idx != vnic_id)
+ PMD_DRV_LOG(ERR, "bad vnic idx %d\n", vnic_id);
+ bnxt_vnic_rss_delete(bp, vnic_id);
+ }
+ }
+ return 0;
+}
+
+int32_t
+bnxt_vnic_reta_config_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic_info,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ uint64_t l_bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS] = {0};
+ uint16_t i, sft, idx;
+ uint16_t q_id;
+
+ for (i = 0; i < reta_size; i++) {
+ idx = i / RTE_ETH_RETA_GROUP_SIZE;
+ sft = i % RTE_ETH_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ q_id = reta_conf[idx].reta[sft];
+ if (q_id >= bp->vnic_queue_db.num_queues ||
+ !bp->eth_dev->data->rx_queues[q_id]) {
+ PMD_DRV_LOG(ERR, "Queue id %d is invalid\n", q_id);
+ return -EINVAL;
+ }
+ BNXT_VNIC_BITMAP_SET(l_bitmap, q_id);
+ }
+ /* update the queue bitmap after the validation */
+ memcpy(vnic_info->queue_bitmap, l_bitmap, sizeof(l_bitmap));
+ return 0;
+}
+
+int32_t
+bnxt_vnic_queue_id_is_valid(struct bnxt_vnic_info *vnic_info,
+ uint16_t queue_id)
+{
+ if (BNXT_VNIC_BITMAP_GET(vnic_info->queue_bitmap, queue_id))
+ return 1;
+ return 0;
+}
+
+void
+bnxt_vnic_ring_grp_populate(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+ uint32_t i;
+
+ /* check if ring group is supported */
+ if (!BNXT_HAS_RING_GRPS(bp))
+ return;
+
+ /* map ring groups to this vnic */
+ for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
+ if (bnxt_vnic_queue_id_is_valid(vnic, i) &&
+ bp->rx_queues[i]->rx_started)
+ vnic->fw_grp_ids[i] = bp->grp_info[i].fw_grp_id;
+
+ vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
+}
+
+void
+bnxt_vnic_rules_init(struct bnxt_vnic_info *vnic)
+{
+ vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
+ vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
+ vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
+}
+
+int32_t
+bnxt_vnic_mru_config(struct bnxt *bp, uint16_t new_mtu)
+{
+ struct bnxt_vnic_info *vnic;
+ uint16_t size = 0;
+ int32_t rc = 0;
+ uint32_t i;
+
+ for (i = 0; i < bp->max_vnics; i++) {
+ vnic = &bp->vnic_info[i];
+ if (vnic->fw_vnic_id == INVALID_VNIC_ID)
+ continue;
+
+ vnic->mru = BNXT_VNIC_MRU(new_mtu);
+ rc = bnxt_hwrm_vnic_cfg(bp, vnic);
+ if (rc)
+ break;
+
+ size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
+ size -= RTE_PKTMBUF_HEADROOM;
+
+ if (size < new_mtu) {
+ rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+ if (rc)
+ break;
+ }
+ }
+ return rc;
+}
+
+struct bnxt_vnic_info *
+bnxt_vnic_queue_db_get_vnic(struct bnxt *bp, uint16_t vnic_idx)
+{
+ struct bnxt_vnic_info *vnic_info;
+
+ if (vnic_idx >= bp->max_vnics) {
+ PMD_DRV_LOG(ERR, "invalid vnic index %u\n", vnic_idx);
+ return NULL;
+ }
+ vnic_info = &bp->vnic_info[vnic_idx];
+ return vnic_info;
+}
+
+struct bnxt_vnic_info *
+bnxt_vnic_queue_id_get_next(struct bnxt *bp, uint16_t queue_id,
+ uint16_t *vnic_idx)
+{
+ struct bnxt_vnic_info *vnic = NULL;
+ uint16_t i = *vnic_idx;
+
+ while (i < bp->max_vnics) {
+ vnic = &bp->vnic_info[i];
+ if (vnic->ref_cnt && BNXT_VNIC_BITMAP_GET(vnic->queue_bitmap,
+ queue_id)) {
+ /* found a vnic that has the queue id */
+ *vnic_idx = i;
+ return vnic;
+ }
+ i++;
+ }
+ return NULL;
+}
+
+void
+bnxt_vnic_tpa_cfg(struct bnxt *bp, uint16_t queue_id, bool flag)
+{
+ struct bnxt_vnic_info *vnic = NULL;
+ uint16_t vnic_idx = 0;
+
+ while ((vnic = bnxt_vnic_queue_id_get_next(bp, queue_id,
+ &vnic_idx)) != NULL) {
+ bnxt_hwrm_vnic_tpa_cfg(bp, vnic, flag);
+ vnic_idx++;
+ }
+}
+
+inline struct bnxt_vnic_info *
+bnxt_get_default_vnic(struct bnxt *bp)
+{
+ return &bp->vnic_info[bp->vnic_queue_db.dflt_vnic_id];
+}
diff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h
index 9055b93c4b..4396d95bda 100644
--- a/drivers/net/bnxt/bnxt_vnic.h
+++ b/drivers/net/bnxt/bnxt_vnic.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -8,11 +8,29 @@
#include <sys/queue.h>
#include <stdbool.h>
+#include <rte_hash.h>
-#define INVALID_VNIC_ID ((uint16_t)-1)
+#define INVALID_VNIC_ID ((uint16_t)-1)
+#define BNXT_RSS_LEVEL_INNERMOST 0x2
+#define BNXT_RSS_LEVEL_OUTERMOST 0x1
+#define BNXT_VNIC_MAX_QUEUE_SIZE 256
+#define BNXT_VNIC_MAX_QUEUE_SZ_IN_8BITS (BNXT_VNIC_MAX_QUEUE_SIZE / 8)
+#define BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS (BNXT_VNIC_MAX_QUEUE_SIZE / 64)
+/* Limit the number of vnic creations*/
+#define BNXT_VNIC_MAX_SUPPORTED_ID 64
-#define BNXT_RSS_LEVEL_INNERMOST 0x2
-#define BNXT_RSS_LEVEL_OUTERMOST 0x1
+#define BNXT_HASH_MODE_DEFAULT HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT
+#define BNXT_HASH_MODE_INNERMOST \
+ (HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 | \
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2)
+#define BNXT_HASH_MODE_OUTERMOST \
+ (HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 | \
+ HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2)
+#define BNXT_VNIC_OUTER_RSS_UNSUPPORTED(bp) \
+ ((BNXT_PF(bp) && !((bp)->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS)) || \
+ (BNXT_VF(bp) && BNXT_VF_IS_TRUSTED(bp) && \
+ !((bp)->vnic_cap_flags & BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF)) || \
+ (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)))
struct bnxt_vnic_info {
STAILQ_ENTRY(bnxt_vnic_info) next;
@@ -28,6 +46,7 @@ struct bnxt_vnic_info {
uint16_t mru;
uint16_t hash_type;
uint8_t hash_mode;
+ uint8_t prev_hash_mode;
const struct rte_memzone *rss_mz;
rte_iova_t rss_table_dma_addr;
uint16_t *rss_table;
@@ -50,11 +69,29 @@ struct bnxt_vnic_info {
bool func_default;
bool bd_stall;
bool rss_dflt_cr;
+ uint16_t ref_cnt;
+ uint64_t queue_bitmap[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
STAILQ_HEAD(, bnxt_filter_info) filter;
STAILQ_HEAD(, rte_flow) flow_list;
};
+struct bnxt_vnic_queue_db {
+ uint16_t num_queues;
+ uint16_t dflt_vnic_id;
+ struct rte_hash *rss_q_db;
+};
+
+/* RSS structure to pass values as an structure argument*/
+struct bnxt_vnic_rss_info {
+ uint32_t rss_level;
+ uint64_t rss_types;
+ uint32_t key_len; /**< Hash key length in bytes. */
+ const uint8_t *key; /**< Hash key. */
+ uint32_t queue_num; /**< Number of entries in @p queue. */
+ uint64_t queue_list[BNXT_VNIC_MAX_QUEUE_SZ_IN_64BITS];
+};
+
struct bnxt;
int bnxt_free_vnic(struct bnxt *bp, struct bnxt_vnic_info *vnic,
int pool);
@@ -69,4 +106,39 @@ void bnxt_prandom_bytes(void *dest_ptr, size_t len);
uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type);
int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl);
uint64_t bnxt_hwrm_to_rte_rss_level(struct bnxt *bp, uint32_t mode);
+
+int32_t bnxt_vnic_queue_db_init(struct bnxt *bp);
+int32_t bnxt_vnic_queue_db_deinit(struct bnxt *bp);
+
+void bnxt_vnic_queue_db_update_dlft_vnic(struct bnxt *bp);
+int32_t
+bnxt_vnic_rss_queue_status_update(struct bnxt *bp, struct bnxt_vnic_info *vnic);
+
+int32_t bnxt_vnic_queue_action_alloc(struct bnxt *bp, uint16_t q_index,
+ uint16_t *vnic_idx,
+ uint16_t *vnicid);
+int32_t bnxt_vnic_queue_action_free(struct bnxt *bp, uint16_t q_index);
+
+int32_t bnxt_vnic_rss_action_alloc(struct bnxt *bp,
+ struct bnxt_vnic_rss_info *rss_info,
+ uint16_t *queue_id,
+ uint16_t *vnicid);
+int32_t bnxt_vnic_rss_action_free(struct bnxt *bp, uint16_t q_index);
+
+int32_t bnxt_vnic_reta_config_update(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic_info,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+int32_t bnxt_vnic_queue_id_is_valid(struct bnxt_vnic_info *vnic_info,
+ uint16_t queue_id);
+void bnxt_vnic_ring_grp_populate(struct bnxt *bp, struct bnxt_vnic_info *vnic);
+void bnxt_vnic_rules_init(struct bnxt_vnic_info *vnic);
+int32_t bnxt_vnic_mru_config(struct bnxt *bp, uint16_t new_mtu);
+struct bnxt_vnic_info *bnxt_vnic_queue_db_get_vnic(struct bnxt *bp,
+ uint16_t vnic_idx);
+struct bnxt_vnic_info *
+bnxt_vnic_queue_id_get_next(struct bnxt *bp, uint16_t queue_id,
+ uint16_t *vnic_idx);
+void bnxt_vnic_tpa_cfg(struct bnxt *bp, uint16_t queue_id, bool flag);
+
#endif
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index ead03a5ea3..c7a0d5f6c9 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -25,6 +25,8 @@ endforeach
headers = files('rte_pmd_bnxt.h')
+deps += ['hash']
+
sources = files(
'bnxt_cpr.c',
'bnxt_ethdev.c',
@@ -41,7 +43,6 @@ sources = files(
'bnxt_util.c',
'bnxt_vnic.c',
'bnxt_reps.c',
-
'rte_pmd_bnxt.c',
)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
index b09cccedf5..474854d59b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2021-2021 Broadcom
+ * Copyright(c) 2021-2023 Broadcom
* All rights reserved.
*/
@@ -17,6 +17,36 @@
#include "bnxt_tf_common.h"
#include "bnxt_tf_pmd_shim.h"
+int
+bnxt_tunnel_dst_port_free(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type)
+{
+ return bnxt_hwrm_tunnel_dst_port_free(bp,
+ port,
+ type);
+}
+
+int
+bnxt_tunnel_dst_port_alloc(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type)
+{
+ return bnxt_hwrm_tunnel_dst_port_alloc(bp,
+ port,
+ type);
+}
+
+int
+bnxt_tunnel_upar_id_get(struct bnxt *bp,
+ uint8_t type,
+ uint8_t *upar_id)
+{
+ return bnxt_hwrm_tunnel_upar_id_get(bp,
+ upar_id,
+ type);
+}
+
struct bnxt *
bnxt_pmd_get_bp(uint16_t port)
{
@@ -59,7 +89,7 @@ int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms)
BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
return rc;
}
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
if (vnic == NULL) {
BNXT_TF_DBG(ERR, "default vnic not available for %u\n",
parms->port_id);
@@ -108,7 +138,6 @@ static int32_t glob_error_fn(const char *epath, int32_t eerrno)
return 0;
}
-
static int32_t ulp_pmd_get_mac_by_pci(const char *pci_name, uint8_t *mac)
{
char path[ULP_FILE_PATH_SIZE], dev_str[ULP_FILE_PATH_SIZE];
@@ -244,7 +273,7 @@ bnxt_pmd_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
bp = eth_dev->data->dev_private;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
return vnic->fw_vnic_id;
}
@@ -343,7 +372,6 @@ bnxt_pmd_get_vport(uint16_t port_id)
return (1 << bnxt_pmd_get_phy_port_id(port_id));
}
-
int32_t
bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
{
@@ -363,7 +391,7 @@ bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
if (bp->vnic_info == NULL)
return 0;
- vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ vnic = bnxt_get_default_vnic(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_UCAST;
@@ -376,3 +404,211 @@ bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev)
return rc;
}
+
+int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id)
+{
+ struct bnxt *bp = NULL;
+ uint16_t q_index;
+ struct ulp_rte_act_prop *ap = parms->act_prop;
+
+ bp = bnxt_pmd_get_bp(parms->port_id);
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
+ return -EINVAL;
+ }
+
+ memcpy(&q_index, &ap->act_details[BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX],
+ BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX);
+
+ return bnxt_vnic_queue_action_alloc(bp, q_index, vnic_idx, vnic_id);
+}
+
+int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx)
+{
+ struct bnxt *bp = NULL;
+
+ bp = tfp->bp;
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp\n");
+ return -EINVAL;
+ }
+ return bnxt_vnic_queue_action_free(bp, vnic_idx);
+}
+
+int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id)
+{
+ struct bnxt *bp = NULL;
+ struct bnxt_vnic_rss_info rss_info = {0};
+ struct ulp_rte_act_prop *ap = parms->act_prop;
+
+ bp = bnxt_pmd_get_bp(parms->port_id);
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp for port_id %u\n", parms->port_id);
+ return -EINVAL;
+ }
+
+ /* get the details */
+ memset(&rss_info, 0, sizeof(rss_info));
+ memcpy(&rss_info.rss_types,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_TYPES],
+ BNXT_ULP_ACT_PROP_SZ_RSS_TYPES);
+ memcpy(&rss_info.rss_level,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_LEVEL],
+ BNXT_ULP_ACT_PROP_SZ_RSS_LEVEL);
+ memcpy(&rss_info.key_len,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN],
+ BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN);
+ if (rss_info.key_len)
+ rss_info.key = &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY];
+ memcpy(&rss_info.queue_num,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM],
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM);
+
+ /* Validate the size of the queue list */
+ if (sizeof(rss_info.queue_list) < BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE) {
+ BNXT_TF_DBG(ERR, "Mismatch of RSS queue size in template\n");
+ return -EINVAL;
+ }
+ memcpy(rss_info.queue_list,
+ &ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE],
+ BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE);
+
+ return bnxt_vnic_rss_action_alloc(bp, &rss_info, vnic_idx, vnic_id);
+}
+
+int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx)
+{
+ struct bnxt *bp = tfp->bp;
+
+ if (bp == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid bp\n");
+ return -EINVAL;
+ }
+ return bnxt_vnic_rss_action_free(bp, vnic_idx);
+}
+
+#define ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT 16
+#define ULP_GLOBAL_TUNNEL_PORT_ID_MASK ((uint16_t)0xffff)
+#define ULP_GLOBAL_TUNNEL_UPARID_SHIFT 8
+#define ULP_GLOBAL_TUNNEL_UPARID_MASK ((uint16_t)0xff)
+#define ULP_GLOBAL_TUNNEL_TYPE_SHIFT 0
+#define ULP_GLOBAL_TUNNEL_TYPE_MASK ((uint16_t)0xffff)
+
+/* Extracts the dpdk port id and tunnel type from the handle */
+static void
+bnxt_pmd_global_reg_hndl_to_data(uint32_t handle, uint16_t *port,
+ uint8_t *upar_id, uint8_t *type)
+{
+ *type = (handle >> ULP_GLOBAL_TUNNEL_TYPE_SHIFT) &
+ ULP_GLOBAL_TUNNEL_TYPE_MASK;
+ *upar_id = (handle >> ULP_GLOBAL_TUNNEL_UPARID_SHIFT) &
+ ULP_GLOBAL_TUNNEL_UPARID_MASK;
+ *port = (handle >> ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT) &
+ ULP_GLOBAL_TUNNEL_PORT_ID_MASK;
+}
+
+/* Packs the dpdk port id and tunnel type in the handle */
+static void
+bnxt_pmd_global_reg_data_to_hndl(uint16_t port_id, uint8_t upar_id,
+ uint8_t type, uint32_t *handle)
+{
+ *handle = (port_id & ULP_GLOBAL_TUNNEL_PORT_ID_MASK) <<
+ ULP_GLOBAL_TUNNEL_PORT_ID_SHIFT;
+ *handle |= (upar_id & ULP_GLOBAL_TUNNEL_UPARID_MASK) <<
+ ULP_GLOBAL_TUNNEL_UPARID_SHIFT;
+ *handle |= (type & ULP_GLOBAL_TUNNEL_TYPE_MASK) <<
+ ULP_GLOBAL_TUNNEL_TYPE_SHIFT;
+}
+
+static struct bnxt_global_tunnel_info
+ ulp_global_tunnel_db[BNXT_GLOBAL_REGISTER_TUNNEL_MAX] = {{0}};
+/* Sets or resets the tunnel ports.
+ * If dport == 0, then the port_id and type are retrieved from the handle.
+ * otherwise, the incoming port_id, type, and dport are used.
+ * The type is enum ulp_mapper_ulp_global_tunnel_type
+ */
+int32_t
+bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
+ uint16_t udp_port, uint32_t *handle)
+{
+ uint16_t lport_id, ldport;
+ uint8_t hwtype, ltype, lupar_id;
+ struct bnxt *bp;
+ int32_t rc = 0;
+
+ /* convert to HWRM type */
+ switch (type) {
+ case BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN:
+ hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Tunnel Type (%d) invalid\n", type);
+ return -EINVAL;
+ }
+
+ if (!udp_port) {
+ /* Free based on the handle */
+ if (!handle) {
+ BNXT_TF_DBG(ERR, "Free with invalid handle\n");
+ return -EINVAL;
+ }
+ bnxt_pmd_global_reg_hndl_to_data(*handle, &lport_id,
+ &lupar_id, <ype);
+
+ bp = bnxt_pmd_get_bp(lport_id);
+ if (!bp) {
+ BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n",
+ lport_id);
+ return -EINVAL;
+ }
+
+ if (!ulp_global_tunnel_db[ltype].ref_cnt)
+ return 0;
+ ldport = ulp_global_tunnel_db[ltype].dport;
+ rc = bnxt_hwrm_tunnel_dst_port_free(bp, ldport, hwtype);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Unable to free tunnel dst port (%d)\n",
+ ldport);
+ return rc;
+ }
+ ulp_global_tunnel_db[ltype].ref_cnt--;
+ if (ulp_global_tunnel_db[ltype].ref_cnt == 0)
+ ulp_global_tunnel_db[ltype].dport = 0;
+ } else {
+ bp = bnxt_pmd_get_bp(port_id);
+ if (!bp) {
+ BNXT_TF_DBG(ERR, "Unable to get dev by port %d\n",
+ port_id);
+ return -EINVAL;
+ }
+
+ rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_port, hwtype);
+ if (!rc) {
+ ulp_global_tunnel_db[type].ref_cnt++;
+ ulp_global_tunnel_db[type].dport = udp_port;
+ bnxt_pmd_global_reg_data_to_hndl(port_id, 0,
+ type, handle);
+ }
+ }
+ return rc;
+}
+
+#define BNXT_ULP_HOT_UP_DYNAMIC_ENV_VAR "BNXT_ULP_T_HA_SUPPORT"
+/* This function queries the linux shell variable to determine
+ * whether Hot upgrade should be disabled or not.
+ * If BNXT_ULP_T_HA_SUPPORT is set to zero explicitly then
+ * hotupgrade is disabled.
+ */
+int32_t bnxt_pmd_get_hot_upgrade_env(void)
+{
+ char *env;
+ int32_t hot_up = 1;
+
+ env = getenv(BNXT_ULP_HOT_UP_DYNAMIC_ENV_VAR);
+ if (env && strcmp(env, "0") == 0)
+ hot_up = 0;
+ return hot_up;
+}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index d6d7a1f0af..b76e4b849d 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2021-2021 Broadcom
+ * Copyright(c) 2021-2023 Broadcom
* All rights reserved.
*/
@@ -9,6 +9,19 @@
#include "bnxt_tf_common.h"
#include "ulp_mapper.h"
+/* Simple structure to manage the custom global tunnel */
+struct bnxt_global_tunnel_info {
+ uint16_t dport;
+ uint16_t ref_cnt;
+};
+
+/* Internal Tunnel type, */
+enum bnxt_global_register_tunnel_type {
+ BNXT_GLOBAL_REGISTER_TUNNEL_UNUSED = 0,
+ BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN,
+ BNXT_GLOBAL_REGISTER_TUNNEL_MAX
+};
+
int32_t bnxt_rss_config_action_apply(struct bnxt_ulp_mapper_parms *parms);
int32_t bnxt_pmd_get_parent_mac_addr(struct bnxt_ulp_mapper_parms *parms,
uint8_t *mac);
@@ -25,4 +38,24 @@ uint16_t bnxt_pmd_get_phy_port_id(uint16_t port);
uint16_t bnxt_pmd_get_vport(uint16_t port);
enum bnxt_ulp_intf_type bnxt_pmd_get_interface_type(uint16_t port);
int32_t bnxt_pmd_set_unicast_rxmask(struct rte_eth_dev *eth_dev);
+int32_t bnxt_pmd_queue_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id);
+int32_t bnxt_pmd_queue_action_delete(struct tf *tfp, uint16_t vnic_idx);
+int32_t bnxt_pmd_rss_action_create(struct bnxt_ulp_mapper_parms *parms,
+ uint16_t *vnic_idx, uint16_t *vnic_id);
+int32_t bnxt_pmd_rss_action_delete(struct tf *tfp, uint16_t vnic_idx);
+int32_t bnxt_tunnel_dst_port_free(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type);
+int32_t bnxt_tunnel_dst_port_alloc(struct bnxt *bp,
+ uint16_t port,
+ uint8_t type);
+int32_t
+bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
+ uint16_t udp_port, uint32_t *handle);
+int32_t
+bnxt_tunnel_upar_id_get(struct bnxt *bp,
+ uint8_t type,
+ uint8_t *upar_id);
+int32_t bnxt_pmd_get_hot_upgrade_env(void);
#endif /* _BNXT_TF_PMD_ABSTRACT_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 109bd0652a..08eb0c6063 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -78,7 +78,7 @@ bnxt_ulp_devid_get(struct bnxt *bp,
if (BNXT_STINGRAY(bp))
*ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY;
else
- /* Assuming Whitney */
+ /* Assuming P4 */
*ulp_dev_id = BNXT_ULP_DEVICE_ID_WH_PLUS;
return 0;
@@ -340,12 +340,62 @@ bnxt_ulp_tf_shared_session_resources_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+/* Function to set the hot upgrade support into the context */
+static int
+bnxt_ulp_multi_shared_session_support_set(struct bnxt *bp,
+ enum bnxt_ulp_device_id devid,
+ uint32_t fw_hu_update)
+{
+ struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
+ struct tf_get_version_parms v_params = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+ int32_t new_fw = 0;
+
+ v_params.device_type = bnxt_ulp_cntxt_convert_dev_id(devid);
+ v_params.bp = bp;
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_version(tfp, &v_params);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get tf version.\n");
+ return rc;
+ }
+
+ if (v_params.major == 1 && v_params.minor == 0 &&
+ v_params.update == 1) {
+ new_fw = 1;
+ }
+ /* if the version update is greater than 0 then set support for
+ * multiple version
+ */
+ if (new_fw) {
+ ulp_ctx->cfg_data->ulp_flags |= BNXT_ULP_MULTI_SHARED_SUPPORT;
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED;
+ }
+ if (!new_fw && fw_hu_update) {
+ ulp_ctx->cfg_data->ulp_flags &= ~BNXT_ULP_HIGH_AVAIL_ENABLED;
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED |
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC;
+ }
+
+ if (!new_fw && !fw_hu_update) {
+ ulp_ctx->cfg_data->hu_session_type =
+ BNXT_ULP_SESSION_TYPE_SHARED |
+ BNXT_ULP_SESSION_TYPE_SHARED_OWC;
+ }
+
+ return rc;
+}
+
int32_t
bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
uint8_t app_id, uint32_t dev_id)
{
struct bnxt_ulp_app_capabilities_info *info;
- uint32_t num = 0;
+ uint32_t num = 0, fw = 0;
uint16_t i;
bool found = false;
struct bnxt_ulp_context *ulp_ctx = bp->ulp_ctx;
@@ -375,15 +425,49 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
if (info[i].flags & BNXT_ULP_APP_CAP_UNICAST_ONLY)
ulp_ctx->cfg_data->ulp_flags |=
BNXT_ULP_APP_UNICAST_ONLY;
+ if (info[i].flags & BNXT_ULP_APP_CAP_IP_TOS_PROTO_SUPPORT)
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_TOS_PROTO_SUPPORT;
+ if (info[i].flags & BNXT_ULP_APP_CAP_BC_MC_SUPPORT)
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_BC_MC_SUPPORT;
if (info[i].flags & BNXT_ULP_APP_CAP_SOCKET_DIRECT) {
/* Enable socket direction only if MR is enabled in fw*/
if (BNXT_MULTIROOT_EN(bp)) {
ulp_ctx->cfg_data->ulp_flags |=
BNXT_ULP_APP_SOCKET_DIRECT;
- BNXT_TF_DBG(DEBUG,
- "Socket Direct feature is enabled");
+ BNXT_TF_DBG(INFO,
+ "Socket Direct feature is enabled\n");
}
}
+ if (info[i].flags & BNXT_ULP_APP_CAP_HA_DYNAMIC) {
+ /* Read the environment variable to determine hot up */
+ if (!bnxt_pmd_get_hot_upgrade_env()) {
+ ulp_ctx->cfg_data->ulp_flags |=
+ BNXT_ULP_APP_HA_DYNAMIC;
+ /* reset Hot upgrade, dynamically disabled */
+ ulp_ctx->cfg_data->ulp_flags &=
+ ~BNXT_ULP_HIGH_AVAIL_ENABLED;
+ ulp_ctx->cfg_data->def_session_type =
+ BNXT_ULP_SESSION_TYPE_DEFAULT_NON_HA;
+ BNXT_TF_DBG(INFO, "Hot upgrade disabled.\n");
+ }
+ }
+
+ bnxt_ulp_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port);
+ bnxt_ulp_vxlan_port_set(ulp_ctx, info[i].vxlan_port);
+
+ /* set the shared session support from firmware */
+ fw = info[i].upgrade_fw_update;
+ if (ULP_HIGH_AVAIL_IS_ENABLED(ulp_ctx->cfg_data->ulp_flags) &&
+ bnxt_ulp_multi_shared_session_support_set(bp, dev_id, fw)) {
+ BNXT_TF_DBG(ERR,
+ "Unable to get shared session support\n");
+ return -EINVAL;
+ }
+ bnxt_ulp_ha_reg_set(ulp_ctx, info[i].ha_reg_state,
+ info[i].ha_reg_cnt);
+ ulp_ctx->cfg_data->ha_pool_id = info[i].ha_pool_id;
}
if (!found) {
BNXT_TF_DBG(ERR, "APP ID %d, Device ID: 0x%x not supported.\n",
@@ -1027,6 +1111,11 @@ ulp_ctx_init(struct bnxt *bp,
goto error_deinit;
}
+ if (BNXT_TESTPMD_EN(bp)) {
+ ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED;
+ BNXT_TF_DBG(ERR, "Enabled Testpmd forward mode\n");
+ }
+
/*
* Shared session must be created before first regular session but after
* the ulp_ctx is valid.
@@ -1055,7 +1144,6 @@ ulp_ctx_init(struct bnxt *bp,
}
bnxt_ulp_cntxt_num_shared_clients_set(bp->ulp_ctx, true);
-
/* Open the ulp session. */
rc = ulp_ctx_session_open(bp, session);
if (rc)
@@ -1181,7 +1269,7 @@ ulp_ctx_attach(struct bnxt *bp,
tfp->session = NULL;
return rc;
}
-
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, BNXT_ULP_SESSION_TYPE_DEFAULT, tfp);
return rc;
}
@@ -1427,7 +1515,8 @@ bnxt_ulp_deinit(struct bnxt *bp,
return;
ha_enabled = bnxt_ulp_cntxt_ha_enabled(bp->ulp_ctx);
- if (ha_enabled && session->session_opened) {
+ if (ha_enabled &&
+ bnxt_ulp_session_is_open(session, BNXT_ULP_SESSION_TYPE_DEFAULT)) {
int32_t rc = ulp_ha_mgr_close(bp->ulp_ctx);
if (rc)
BNXT_TF_DBG(ERR, "Failed to close HA (%d)\n", rc);
@@ -1490,6 +1579,7 @@ bnxt_ulp_init(struct bnxt *bp,
struct bnxt_ulp_session_state *session)
{
int rc;
+ uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
/* Allocate and Initialize the ulp context. */
rc = ulp_ctx_init(bp, session);
@@ -1584,6 +1674,13 @@ bnxt_ulp_init(struct bnxt *bp,
goto jump_to_error;
}
}
+
+ rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n");
+ return rc;
+ }
+
BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
return rc;
@@ -1592,6 +1689,30 @@ bnxt_ulp_init(struct bnxt *bp,
return rc;
}
+static int
+ulp_cust_vxlan_alloc(struct bnxt *bp)
+{
+ int rc = 0;
+
+ if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_alloc(bp,
+ bp->ulp_ctx->cfg_data->vxlan_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to set global vxlan port\n");
+ }
+
+ if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_alloc(bp,
+ bp->ulp_ctx->cfg_data->vxlan_ip_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to set global custom vxlan_ip port\n");
+ }
+
+ return rc;
+}
+
/*
* When a port is initialized by dpdk. This functions sets up
* the port specific details.
@@ -1686,6 +1807,7 @@ bnxt_ulp_port_init(struct bnxt *bp)
BNXT_TF_DBG(ERR, "Failed to update port database\n");
goto jump_to_error;
}
+
/* create the default rules */
rc = bnxt_ulp_create_df_rules(bp);
if (rc) {
@@ -1711,6 +1833,10 @@ bnxt_ulp_port_init(struct bnxt *bp)
}
}
+ rc = ulp_cust_vxlan_alloc(bp);
+ if (rc)
+ goto jump_to_error;
+
return rc;
jump_to_error:
@@ -1718,6 +1844,28 @@ bnxt_ulp_port_init(struct bnxt *bp)
return rc;
}
+static void
+ulp_cust_vxlan_free(struct bnxt *bp)
+{
+ int rc;
+
+ if (ULP_APP_CUST_VXLAN_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_free(bp,
+ bp->ulp_ctx->cfg_data->vxlan_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to clear global vxlan port\n");
+ }
+
+ if (ULP_APP_CUST_VXLAN_IP_SUPPORT(bp->ulp_ctx)) {
+ rc = bnxt_tunnel_dst_port_free(bp,
+ bp->ulp_ctx->cfg_data->vxlan_ip_port,
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to clear global custom vxlan port\n");
+ }
+}
+
/*
* When a port is de-initialized by dpdk. This functions clears up
* the port specific details.
@@ -1770,6 +1918,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp)
if (bp->ulp_ctx->cfg_data && bp->ulp_ctx->cfg_data->ref_cnt) {
bp->ulp_ctx->cfg_data->ref_cnt--;
if (bp->ulp_ctx->cfg_data->ref_cnt) {
+ /* Free tunnel configurations */
+ ulp_cust_vxlan_free(bp);
+
/* free the port details */
/* Free the default flow rule associated to this port */
bnxt_ulp_destroy_df_rules(bp, false);
@@ -2201,6 +2352,45 @@ bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx)
pthread_mutex_unlock(&ulp_ctx->cfg_data->flow_db_lock);
}
+/* Function to extract the action type from the shared action handle. */
+int32_t
+bnxt_get_action_handle_type(const struct rte_flow_action_handle *handle,
+ uint32_t *action_handle_type)
+{
+ if (!action_handle_type)
+ return -EINVAL;
+
+ *action_handle_type = (uint32_t)(((uint64_t)handle >> 32) & 0xffffffff);
+ if (*action_handle_type >= BNXT_ULP_GEN_TBL_MAX_SZ)
+ return -EINVAL;
+
+ return 0;
+}
+
+/* Function to extract the direction from the shared action handle. */
+int32_t
+bnxt_get_action_handle_direction(const struct rte_flow_action_handle *handle,
+ uint32_t *dir)
+{
+ uint32_t shared_type;
+ int32_t ret = 0;
+
+ ret = bnxt_get_action_handle_type(handle, &shared_type);
+ if (ret)
+ return ret;
+
+ *dir = shared_type & 0x1 ? BNXT_ULP_DIR_EGRESS : BNXT_ULP_DIR_INGRESS;
+
+ return ret;
+}
+
+/* Function to extract the action index from the shared action handle. */
+uint32_t
+bnxt_get_action_handle_index(const struct rte_flow_action_handle *handle)
+{
+ return (uint32_t)((uint64_t)handle & 0xffffffff);
+}
+
/* Function to set the ha info into the context */
int32_t
bnxt_ulp_cntxt_ptr2_ha_info_set(struct bnxt_ulp_context *ulp_ctx,
@@ -2306,6 +2496,13 @@ bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp)
return ulp->cfg_data->app_tun;
}
+/* Function to get the truflow app id. This defined in the build file */
+uint32_t
+bnxt_ulp_default_app_id_get(void)
+{
+ return BNXT_TF_APP_ID;
+}
+
/* Function to convert ulp dev id to regular dev id. */
uint32_t
bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
@@ -2329,6 +2526,53 @@ bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id)
return type;
}
+/* This function sets the IF table index for the
+ * Application to poll to get the hot upgrade state and count details from
+ * the firmware.
+ */
+int32_t
+bnxt_ulp_ha_reg_set(struct bnxt_ulp_context *ulp_ctx,
+ uint8_t state, uint8_t cnt)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ if (ULP_MULTI_SHARED_IS_SUPPORTED(ulp_ctx)) {
+ ulp_ctx->cfg_data->hu_reg_state = state;
+ ulp_ctx->cfg_data->hu_reg_cnt = cnt;
+ } else {
+ ulp_ctx->cfg_data->hu_reg_state = ULP_HA_IF_TBL_IDX;
+ ulp_ctx->cfg_data->hu_reg_cnt = ULP_HA_CLIENT_CNT_IF_TBL_IDX;
+ }
+ return 0;
+}
+
+/* This function gets the IF table index for the
+ * application to poll to get the application hot upgrade state from
+ * the firmware.
+ */
+uint32_t
+bnxt_ulp_ha_reg_state_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (uint32_t)ulp_ctx->cfg_data->hu_reg_state;
+}
+
+/* This function gets the IF table index for the
+ * Application to poll to get the application count from
+ * the firmware.
+ */
+uint32_t
+bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (uint32_t)ulp_ctx->cfg_data->hu_reg_cnt;
+}
+
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type)
{
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 9b30851b13..53d76e1465 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -386,4 +386,5 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
+
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 55885d1b8c..ad04644db4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -14,6 +14,8 @@
#include "ulp_ha_mgr.h"
#include "ulp_tun.h"
#include <rte_malloc.h>
+#include "ulp_template_db_tbl.h"
+#include "tfp.h"
static int32_t
bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr,
@@ -78,6 +80,17 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
#endif
}
+static inline void
+bnxt_ulp_init_parser_cf_defaults(struct ulp_rte_parser_params *params,
+ uint16_t port_id)
+{
+ /* Set up defaults for Comp field */
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_INCOMING_IF, port_id);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_DEV_PORT_ID, port_id);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG,
+ BNXT_ULP_INVALID_SVIF_VAL);
+}
+
void
bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
struct ulp_rte_parser_params *params,
@@ -130,6 +143,10 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG,
1);
+ } else {
+ ULP_COMP_FLD_IDX_WR(params,
+ BNXT_ULP_CF_IDX_HA_SUPPORT_DISABLED,
+ 1);
}
/* Update the socket direct flag */
@@ -197,13 +214,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
/* Set the flow attributes */
bnxt_ulp_set_dir_attributes(¶ms, attr);
- /* copy the device port id and direction for further processing */
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_INCOMING_IF,
- dev->data->port_id);
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DEV_PORT_ID,
- dev->data->port_id);
- ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_SVIF_FLAG,
- BNXT_ULP_INVALID_SVIF_VAL);
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
/* Get the function id */
if (ulp_port_db_port_func_id_get(ulp_ctx,
@@ -320,6 +331,7 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
/* Set the flow attributes */
bnxt_ulp_set_dir_attributes(¶ms, attr);
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
/* Parse the rte flow pattern */
ret = bnxt_ulp_rte_parser_hdr_parse(pattern, ¶ms);
@@ -494,6 +506,256 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev,
return rc;
}
+static int32_t
+bnxt_ulp_action_handle_chk_args(const struct rte_flow_action *action,
+ const struct rte_flow_indir_action_conf *conf)
+{
+ if (!action || !conf)
+ return BNXT_TF_RC_ERROR;
+ /* shared action only allowed to have one direction */
+ if (conf->ingress == 1 && conf->egress == 1)
+ return BNXT_TF_RC_ERROR;
+ /* shared action must have at least one direction */
+ if (conf->ingress == 0 && conf->egress == 0)
+ return BNXT_TF_RC_ERROR;
+ return BNXT_TF_RC_SUCCESS;
+}
+
+static inline void
+bnxt_ulp_set_action_handle_dir_attr(struct ulp_rte_parser_params *params,
+ const struct rte_flow_indir_action_conf *conf)
+{
+ if (conf->ingress == 1)
+ params->dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+ else if (conf->egress == 1)
+ params->dir_attr |= BNXT_ULP_FLOW_ATTR_EGRESS;
+}
+
+static struct rte_flow_action_handle *
+bnxt_ulp_action_handle_create(struct rte_eth_dev *dev,
+ const struct rte_flow_indir_action_conf *conf,
+ const struct rte_flow_action *action,
+ struct rte_flow_error *error)
+{
+ enum bnxt_ulp_intf_type port_type = BNXT_ULP_INTF_TYPE_INVALID;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ struct ulp_rte_parser_params params;
+ struct bnxt_ulp_context *ulp_ctx;
+ uint32_t act_tid;
+ uint16_t func_id;
+ uint32_t ifindex;
+ int ret = BNXT_TF_RC_ERROR;
+ const struct rte_flow_action actions[2] = {
+ {
+ .type = action->type,
+ .conf = action->conf
+ },
+ {
+ .type = RTE_FLOW_ACTION_TYPE_END
+ }
+ };
+
+ if (bnxt_ulp_action_handle_chk_args(action, conf) != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ goto parse_error;
+ }
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+
+ ULP_BITMAP_SET(params.act_bitmap.bits, BNXT_ULP_ACT_BIT_SHARED);
+
+ /* Set the shared action direction attribute */
+ bnxt_ulp_set_action_handle_dir_attr(¶ms, conf);
+
+ /* perform the conversion from dpdk port to bnxt ifindex */
+ if (ulp_port_db_dev_port_to_ulp_index(ulp_ctx,
+ dev->data->port_id,
+ &ifindex)) {
+ BNXT_TF_DBG(ERR, "Port id is not valid\n");
+ goto parse_error;
+ }
+ port_type = ulp_port_db_port_type_get(ulp_ctx, ifindex);
+ if (port_type == BNXT_ULP_INTF_TYPE_INVALID) {
+ BNXT_TF_DBG(ERR, "Port type is not valid\n");
+ goto parse_error;
+ }
+
+ bnxt_ulp_init_parser_cf_defaults(¶ms, dev->data->port_id);
+
+ /* Emulating the match port for direction processing */
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_MATCH_PORT_TYPE,
+ port_type);
+
+ if ((params.dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS) &&
+ port_type == BNXT_ULP_INTF_TYPE_VF_REP) {
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ } else {
+ /* Assign the input direction */
+ if (params.dir_attr & BNXT_ULP_FLOW_ATTR_INGRESS)
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_INGRESS);
+ else
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION,
+ BNXT_ULP_DIR_EGRESS);
+ }
+
+ /* Parse the shared action */
+ ret = bnxt_ulp_rte_parser_act_parse(actions, ¶ms);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ /* Perform the rte flow post process */
+ bnxt_ulp_rte_parser_post_process(¶ms);
+
+ /* do the tunnel offload process if any */
+ ret = ulp_tunnel_offload_process(¶ms);
+ if (ret == BNXT_TF_RC_ERROR)
+ goto parse_error;
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ return (struct rte_flow_action_handle *)((uintptr_t)mparms.shared_hndl);
+
+parse_error:
+ rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "Failed to create shared action.");
+ return NULL;
+}
+
+static int
+bnxt_ulp_action_handle_destroy(struct rte_eth_dev *dev,
+ struct rte_flow_action_handle *shared_hndl,
+ struct rte_flow_error *error)
+{
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ struct bnxt_ulp_shared_act_info *act_info;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop;
+ struct bnxt_ulp_context *ulp_ctx;
+ enum bnxt_ulp_direction_type dir;
+ uint32_t act_tid, act_info_entries;
+ int ret = BNXT_TF_RC_ERROR;
+ uint32_t shared_action_type;
+ uint64_t tmp64;
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx) {
+ BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
+ goto parse_error;
+ }
+
+ if (!shared_hndl) {
+ BNXT_TF_DBG(ERR, "Invalid argument of shared handle\n");
+ goto parse_error;
+ }
+
+ act_prop = ¶ms.act_prop;
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+
+ if (bnxt_ulp_cntxt_app_id_get(ulp_ctx, ¶ms.app_id)) {
+ BNXT_TF_DBG(ERR, "failed to get the app id\n");
+ goto parse_error;
+ }
+ /* The template will delete the entry if there are no references */
+ if (bnxt_get_action_handle_type(shared_hndl, &shared_action_type)) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ goto parse_error;
+ }
+
+ act_info_entries = 0;
+ act_info = bnxt_ulp_shared_act_info_get(&act_info_entries);
+ if (shared_action_type >= act_info_entries || !act_info) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ goto parse_error;
+ }
+
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ act_info[shared_action_type].act_bitmask);
+ ULP_BITMAP_SET(params.act_bitmap.bits, BNXT_ULP_ACT_BIT_DELETE);
+
+ ret = bnxt_get_action_handle_direction(shared_hndl, &dir);
+ if (ret) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle dir\n");
+ goto parse_error;
+ }
+
+ if (dir == BNXT_ULP_DIR_EGRESS) {
+ params.dir_attr = BNXT_ULP_FLOW_ATTR_EGRESS;
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+ } else {
+ params.dir_attr = BNXT_ULP_FLOW_ATTR_INGRESS;
+ ULP_BITMAP_SET(params.act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_ING);
+ }
+
+ tmp64 = tfp_cpu_to_be_64((uint64_t)
+ bnxt_get_action_handle_index(shared_hndl));
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE],
+ &tmp64, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE);
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+ if (ret)
+ goto parse_error;
+
+ return 0;
+
+parse_error:
+ rte_flow_error_set(error, BNXT_TF_RC_ERROR,
+ RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+ "Failed to destroy shared action.");
+ return -EINVAL;
+}
+
/* Tunnel offload Apis */
#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1
@@ -685,6 +947,8 @@ const struct rte_flow_ops bnxt_ulp_rte_flow_ops = {
.flush = bnxt_ulp_flow_flush,
.query = bnxt_ulp_flow_query,
.isolate = NULL,
+ .action_handle_create = bnxt_ulp_action_handle_create,
+ .action_handle_destroy = bnxt_ulp_action_handle_destroy,
/* Tunnel offload callbacks */
.tunnel_decap_set = bnxt_ulp_tunnel_decap_set,
.tunnel_match = bnxt_ulp_tunnel_match,
diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build
index 71094b9974..c7df7e42f1 100644
--- a/drivers/net/bnxt/tf_ulp/meson.build
+++ b/drivers/net/bnxt/tf_ulp/meson.build
@@ -1,28 +1,29 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-# Copyright(c) 2021 Broadcom
+# Copyright(c) 2023 Broadcom
#Include the folder for headers
includes += include_directories('.')
+cflags += '-DBNXT_TF_APP_ID=0'
#Add the source files
sources += files(
+ 'bnxt_tf_pmd_shim.c',
'bnxt_ulp.c',
- 'ulp_mark_mgr.c',
- 'ulp_flow_db.c',
- 'ulp_utils.c',
- 'ulp_mapper.c',
- 'ulp_matcher.c',
- 'ulp_rte_parser.c',
'bnxt_ulp_flow.c',
- 'ulp_port_db.c',
'ulp_def_rules.c',
'ulp_fc_mgr.c',
- 'ulp_tun.c',
- 'bnxt_tf_pmd_shim.c',
- 'ulp_gen_tbl.c',
+ 'ulp_flow_db.c',
'ulp_gen_hash.c',
+ 'ulp_gen_tbl.c',
'ulp_ha_mgr.c',
- 'ulp_rte_handler_tbl.c')
+ 'ulp_mapper.c',
+ 'ulp_mark_mgr.c',
+ 'ulp_matcher.c',
+ 'ulp_port_db.c',
+ 'ulp_rte_handler_tbl.c',
+ 'ulp_rte_parser.c',
+ 'ulp_tun.c',
+ 'ulp_utils.c')
subdir('generic_templates')
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index dee2c04b24..c39cde39aa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -438,8 +438,8 @@ void
ulp_fc_mgr_alarm_cb(void *arg)
{
int rc = 0;
- unsigned int j = 0;
- enum tf_dir i = 0;
+ unsigned int j;
+ enum tf_dir i;
struct bnxt_ulp_context *ctxt;
struct bnxt_ulp_fc_info *ulp_fc_info;
struct bnxt_ulp_device_params *dparms;
@@ -473,14 +473,6 @@ ulp_fc_mgr_alarm_cb(void *arg)
return;
}
- tfp = bnxt_ulp_cntxt_tfp_get(ctxt,
- ulp_fc_info->sw_acc_tbl[i][j].session_type);
- if (!tfp) {
- BNXT_TF_DBG(ERR, "Failed to get the truflow pointer\n");
- bnxt_ulp_cntxt_entry_release();
- return;
- }
-
/*
* Take the fc_lock to ensure no flow is destroyed
* during the bulk get
@@ -667,6 +659,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir,
sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid = false;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0;
+ ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].session_type = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0;
ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
index 5279beb764..ebf32d6702 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -259,23 +259,26 @@ ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_idx, uint32_t ckey)
{
struct ulp_flow_db_res_params res;
+ uint32_t fid = 0; /* not using for this case */
res.direction = tbl_idx & 0x1;
res.resource_sub_type = tbl_idx >> 1;
res.resource_hndl = ckey;
- return ulp_mapper_gen_tbl_res_free(ulp_ctx, &res);
+ return ulp_mapper_gen_tbl_res_free(ulp_ctx, fid, &res);
}
/* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
+ * fid [in] - The fid the generic table is associated with
* res [in] - Pointer to flow db resource entry
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t fid,
struct ulp_flow_db_res_params *res)
{
struct bnxt_ulp_mapper_data *mapper_data;
@@ -283,7 +286,7 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
struct ulp_mapper_gen_tbl_entry entry;
struct ulp_gen_hash_entry_params hash_entry;
int32_t tbl_idx;
- uint32_t fid = 0;
+ uint32_t rid = 0;
uint32_t key_idx;
/* Extract the resource sub type and direction */
@@ -326,9 +329,10 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
/* Decrement the reference count */
if (!ULP_GEN_TBL_REF_CNT(&entry)) {
- BNXT_TF_DBG(ERR, "generic table corrupt %x:%" PRIX64 "\n",
+ BNXT_TF_DBG(DEBUG,
+ "generic table entry already free %x:%" PRIX64 "\n",
tbl_idx, res->resource_hndl);
- return -EINVAL;
+ return 0;
}
ULP_GEN_TBL_REF_CNT_DEC(&entry);
@@ -336,24 +340,27 @@ ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
if (ULP_GEN_TBL_REF_CNT(&entry))
return 0;
- /* Delete the generic table entry. First extract the fid */
+ /* Delete the generic table entry. First extract the rid */
if (ulp_mapper_gen_tbl_entry_data_get(&entry, ULP_GEN_TBL_FID_OFFSET,
ULP_GEN_TBL_FID_SIZE_BITS,
- (uint8_t *)&fid,
- sizeof(fid))) {
- BNXT_TF_DBG(ERR, "Unable to get fid %x:%" PRIX64 "\n",
+ (uint8_t *)&rid,
+ sizeof(rid))) {
+ BNXT_TF_DBG(ERR, "Unable to get rid %x:%" PRIX64 "\n",
tbl_idx, res->resource_hndl);
return -EINVAL;
}
- fid = tfp_be_to_cpu_32(fid);
- /* no need to del if fid is 0 since there is no associated resource */
- if (fid) {
+ rid = tfp_be_to_cpu_32(rid);
+ /* no need to del if rid is 0 since there is no associated resource
+ * if rid from the entry is equal to the incoming fid, then we have a
+ * recursive delete, so don't follow the rid.
+ */
+ if (rid && rid != fid) {
/* Destroy the flow associated with the shared flow id */
if (ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID,
- fid))
+ rid))
BNXT_TF_DBG(ERR,
- "Error in deleting shared flow id %x\n",
- fid);
+ "Error in deleting shared resource id %x\n",
+ rid);
}
/* Delete the entry from the hash table */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
index 3060072967..4c5a6e176f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -134,12 +134,14 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry,
* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
+ * fid [in] - The fid the generic table is associated with
* res [in] - Pointer to flow db resource entry
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t fid,
struct ulp_flow_db_res_params *res);
/* Free the generic table list entry
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
index 42482b596f..f3f5bda890 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c
@@ -23,8 +23,6 @@
#define ULP_HA_IF_TBL_DIR TF_DIR_RX
#define ULP_HA_IF_TBL_TYPE TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR
-#define ULP_HA_IF_TBL_IDX 10
-#define ULP_HA_CLIENT_CNT_IF_TBL_IDX 9
static void ulp_ha_mgr_timer_cancel(struct bnxt_ulp_context *ulp_ctx);
static int32_t ulp_ha_mgr_timer_start(void *arg);
@@ -42,8 +40,8 @@ static int32_t
ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx, uint32_t *cnt);
static int32_t
-ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
- enum ulp_ha_mgr_state state)
+ulp_ha_mgr_state_set_v1(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
{
struct tf_set_if_tbl_entry_parms set_parms = { 0 };
struct tf *tfp;
@@ -66,7 +64,7 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
set_parms.type = ULP_HA_IF_TBL_TYPE;
set_parms.data = (uint8_t *)&val;
set_parms.data_sz_in_bytes = sizeof(val);
- set_parms.idx = ULP_HA_IF_TBL_IDX;
+ set_parms.idx = bnxt_ulp_ha_reg_state_get(ulp_ctx);
rc = tf_set_if_tbl_entry(tfp, &set_parms);
if (rc)
@@ -76,8 +74,82 @@ ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
}
static int32_t
-ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
- uint32_t *cnt)
+ulp_ha_mgr_state_set_v2(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
+{
+ struct tf_set_session_hotup_state_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid parms in state get.\n");
+ return -EINVAL;
+ }
+
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp == NULL) {
+ BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
+ return -EINVAL;
+ }
+
+ parms.state = (uint16_t)state;
+ rc = tf_set_session_hotup_state(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to write the HA state\n");
+ return rc;
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_ha_mgr_state_set(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state state)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_state_set_v2(ulp_ctx, state);
+ else
+ return ulp_ha_mgr_state_set_v1(ulp_ctx, state);
+}
+
+static int32_t
+ulp_ha_mgr_tf_state_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *state,
+ uint32_t *cnt)
+{
+ struct tf_get_session_hotup_state_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (ulp_ctx == NULL) {
+ BNXT_TF_DBG(ERR, "Invalid parms in client num get.\n");
+ return -EINVAL;
+ }
+
+ tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx, BNXT_ULP_SESSION_TYPE_SHARED_WC);
+ if (tfp == NULL) {
+ BNXT_TF_DBG(ERR, "Unable to get the TFP.\n");
+ return -EINVAL;
+ }
+
+ rc = tf_get_session_hotup_state(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to read the HA state\n");
+ return rc;
+ }
+
+ if (state)
+ *state = parms.state;
+
+ if (cnt)
+ *cnt = parms.ref_cnt;
+
+ return rc;
+}
+
+static int32_t
+ulp_ha_mgr_tf_client_num_get_v1(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *cnt)
{
struct tf_get_if_tbl_entry_parms get_parms = { 0 };
struct tf *tfp;
@@ -96,7 +168,7 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
get_parms.dir = ULP_HA_IF_TBL_DIR;
get_parms.type = ULP_HA_IF_TBL_TYPE;
- get_parms.idx = ULP_HA_CLIENT_CNT_IF_TBL_IDX;
+ get_parms.idx = bnxt_ulp_ha_reg_cnt_get(ulp_ctx);
get_parms.data = (uint8_t *)&val;
get_parms.data_sz_in_bytes = sizeof(val);
@@ -108,6 +180,16 @@ ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+static int32_t
+ulp_ha_mgr_tf_client_num_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t *cnt)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_tf_state_get(ulp_ctx, NULL, cnt);
+ else
+ return ulp_ha_mgr_tf_client_num_get_v1(ulp_ctx, cnt);
+}
+
static int32_t
ulp_ha_mgr_region_set(struct bnxt_ulp_context *ulp_ctx,
enum ulp_ha_mgr_region region)
@@ -386,9 +468,9 @@ ulp_ha_mgr_app_type_get(struct bnxt_ulp_context *ulp_ctx,
return 0;
}
-int32_t
-ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
- enum ulp_ha_mgr_state *state)
+static int32_t
+ulp_ha_mgr_state_get_v1(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state *state)
{
struct tf_get_if_tbl_entry_parms get_parms = { 0 };
struct tf *tfp;
@@ -407,7 +489,7 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
get_parms.dir = ULP_HA_IF_TBL_DIR;
get_parms.type = ULP_HA_IF_TBL_TYPE;
- get_parms.idx = ULP_HA_IF_TBL_IDX;
+ get_parms.idx = bnxt_ulp_ha_reg_state_get(ulp_ctx);
get_parms.data = (uint8_t *)&val;
get_parms.data_sz_in_bytes = sizeof(val);
@@ -419,6 +501,16 @@ ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+int32_t
+ulp_ha_mgr_state_get(struct bnxt_ulp_context *ulp_ctx,
+ enum ulp_ha_mgr_state *state)
+{
+ if (bnxt_ulp_cntxt_multi_shared_session_enabled(ulp_ctx))
+ return ulp_ha_mgr_tf_state_get(ulp_ctx, state, NULL);
+ else
+ return ulp_ha_mgr_state_get_v1(ulp_ctx, state);
+}
+
int32_t
ulp_ha_mgr_open(struct bnxt_ulp_context *ulp_ctx)
{
@@ -607,10 +699,9 @@ ulp_ha_mgr_close(struct bnxt_ulp_context *ulp_ctx)
BNXT_TF_DBG(INFO,
"On Close: SEC[COPY] => [INIT] after %d ms\n",
ULP_HA_WAIT_TIMEOUT - timeout);
- } else {
- BNXT_TF_DBG(ERR, "On Close: Invalid type/state %d/%d\n",
- curr_state, app_type);
}
+ /* else do nothing just return*/
+
cleanup:
return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
index ded967a0af..c39a1371d9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -8,6 +8,9 @@
#include "bnxt_ulp.h"
+#define ULP_HA_IF_TBL_IDX 10
+#define ULP_HA_CLIENT_CNT_IF_TBL_IDX 9
+
enum ulp_ha_mgr_state {
ULP_HA_STATE_INIT,
ULP_HA_STATE_PRIM_RUN,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 1f459c52a4..e5f1d266d7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -149,7 +149,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
* Shared resources are never allocated through this method, so the
* shared flag is always false.
*/
- rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false);
+ rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, shared);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write to global resource id\n");
/* Free the identifier when update failed */
@@ -212,7 +212,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
* Shared resources are never allocated through this method, so the
* shared flag is always false.
*/
- rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, false);
+ rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval, shared);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write to global resource id\n");
/* Free the identifier when update failed */
@@ -442,6 +442,7 @@ ulp_mapper_dyn_tbl_type_get(struct bnxt_ulp_mapper_parms *mparms,
case TF_TBL_TYPE_ACT_ENCAP_16B:
case TF_TBL_TYPE_ACT_ENCAP_32B:
case TF_TBL_TYPE_ACT_ENCAP_64B:
+ case TF_TBL_TYPE_ACT_ENCAP_128B:
size_map = d_params->dyn_encap_sizes;
for (i = 0; i < d_params->dyn_encap_list_size; i++) {
if (blob_len <= size_map[i].slab_size) {
@@ -534,6 +535,41 @@ ulp_mapper_tcam_entry_free(struct bnxt_ulp_context *ulp,
return tf_free_tcam_entry(tfp, &fparms);
}
+static int32_t
+ulp_mapper_clear_full_action_record(struct tf *tfp,
+ struct bnxt_ulp_context *ulp_ctx,
+ struct tf_free_tbl_entry_parms *fparms)
+{
+ struct tf_set_tbl_entry_parms sparms = { 0 };
+ uint32_t dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ int32_t rc = 0;
+
+ rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to get the dev id from ulp.\n");
+ return rc;
+ }
+
+ if (dev_id == BNXT_ULP_DEVICE_ID_THOR) {
+ sparms.dir = fparms->dir;
+ sparms.data = mapper_fld_zeros;
+ sparms.type = fparms->type;
+ sparms.data_sz_in_bytes = 16; /* FULL ACT REC SIZE - THOR */
+ sparms.idx = fparms->idx;
+ sparms.tbl_scope_id = fparms->tbl_scope_id;
+ rc = tf_set_tbl_entry(tfp, &sparms);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Index table[%s][%s][%x] write fail rc=%d\n",
+ tf_tbl_type_2_str(sparms.type),
+ tf_dir_2_str(sparms.dir),
+ sparms.idx, rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
static inline int32_t
ulp_mapper_index_entry_free(struct bnxt_ulp_context *ulp,
struct tf *tfp,
@@ -551,6 +587,9 @@ ulp_mapper_index_entry_free(struct bnxt_ulp_context *ulp,
*/
(void)bnxt_ulp_cntxt_tbl_scope_id_get(ulp, &fparms.tbl_scope_id);
+ if (fparms.type == TF_TBL_TYPE_FULL_ACT_RECORD)
+ (void)ulp_mapper_clear_full_action_record(tfp, ulp, &fparms);
+
return tf_free_tbl_entry(tfp, &fparms);
}
@@ -665,6 +704,10 @@ ulp_mapper_fdb_opc_alloc_rid(struct bnxt_ulp_mapper_parms *parms,
BNXT_ULP_FDB_TYPE_RID, rid);
return -EINVAL;
}
+ /* save the rid into the parms in case a flow fails before pushing the
+ * rid into the fid
+ */
+ parms->rid = rid;
return 0;
}
@@ -845,7 +888,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
tf_ident_2_str(iparms.ident_type));
return rc;
}
- BNXT_TF_INF("Alloc ident %s:%s.success.\n",
+ BNXT_TF_DBG(DEBUG, "Alloc ident %s:%s.success.\n",
tf_dir_2_str(iparms.dir),
tf_ident_2_str(iparms.ident_type));
@@ -941,9 +984,9 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms,
sparms.search_id);
return rc;
}
- BNXT_TF_INF("Search ident %s:%s:%x.success.\n",
+ BNXT_TF_DBG(DEBUG, "Search ident %s:%s:%x.success.\n",
tf_dir_2_str(sparms.dir),
- tf_tbl_type_2_str(sparms.ident_type),
+ tf_ident_2_str(sparms.ident_type),
sparms.search_id);
/* Write it to the regfile */
@@ -1016,6 +1059,20 @@ ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
+ case BNXT_ULP_PORT_TABLE_PORT_IS_PF:
+ if (ulp_port_db_port_is_pf_get(parms->ulp_ctx, port_id,
+ val)) {
+ BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
+ return -EINVAL;
+ }
+ break;
+ case BNXT_ULP_PORT_TABLE_VF_FUNC_METADATA:
+ if (ulp_port_db_port_meta_data_get(parms->ulp_ctx, port_id,
+ val)) {
+ BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
+ return -EINVAL;
+ }
+ break;
default:
BNXT_TF_DBG(ERR, "Invalid port_data %d\n", port_data);
return -EINVAL;
@@ -1042,6 +1099,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
uint8_t *buffer;
uint64_t lregval;
bool shared;
+ uint8_t i = 0;
*val_len = bitlen;
*value = 0;
@@ -1111,6 +1169,11 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
*val = &buffer[field_size - bytelen];
+ if (sizeof(*value) >= field_size) {
+ *value = buffer[0];
+ for (i = 1; i < field_size; i++)
+ *value = (*value << 8) | buffer[i];
+ }
break;
case BNXT_ULP_FIELD_SRC_ACT_PROP_SZ:
if (!ulp_operand_read(field_opr,
@@ -1254,11 +1317,22 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms,
}
break;
case BNXT_ULP_FIELD_SRC_PORT_TABLE:
+ if (!ulp_operand_read(field_opr,
+ (uint8_t *)&idx, sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "CF operand read failed\n");
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) {
+ BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx,
+ bytelen);
+ return -EINVAL;
+ }
+
/* The port id is present in the comp field list */
- port_id = ULP_COMP_FLD_IDX_RD(parms,
- BNXT_ULP_CF_IDX_DEV_PORT_ID);
+ port_id = ULP_COMP_FLD_IDX_RD(parms, idx);
/* get the port table enum */
- if (!ulp_operand_read(field_opr,
+ if (!ulp_operand_read(field_opr + sizeof(uint16_t),
(uint8_t *)&idx, sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "Port table enum read failed\n");
return -EINVAL;
@@ -1557,9 +1631,8 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms,
break;
}
- if (!rc) {
+ if (!rc)
return rc;
- }
error:
BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name,
fld->description, (val) ? write_idx : 0, val_len);
@@ -1878,7 +1951,7 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
tf_dir_2_str(sparms.dir), sparms.idx);
return -EIO;
}
- BNXT_TF_INF("tcam[%s][%s][%x] write success.\n",
+ BNXT_TF_DBG(DEBUG, "tcam[%s][%s][%x] write success.\n",
tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
tf_dir_2_str(sparms.dir), sparms.idx);
@@ -2168,7 +2241,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
rc = tf_search_tcam_entry(tfp, &searchparms);
if (rc) {
- BNXT_TF_DBG(ERR, "tcam search failed rc=%d\n", rc);
+ BNXT_TF_DBG(ERR, "entry priority process failed\n");
return rc;
}
@@ -2546,7 +2619,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
gparms.dir = tbl->direction;
gparms.type = tbl->resource_type;
gparms.data = ulp_blob_data_get(&data, &tmplen);
- gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
+ gparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tbl->result_bit_size);
gparms.idx = index;
rc = tf_get_tbl_entry(tfp, &gparms);
if (rc) {
@@ -2651,7 +2724,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (shared)
tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx,
tbl->session_type);
-
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR,
@@ -2661,7 +2733,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
sparms.idx, rc);
goto error;
}
- BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n",
+ BNXT_TF_DBG(DEBUG, "Index table[%s][%s][%x] write successful\n",
tf_tbl_type_2_str(sparms.type),
tf_dir_2_str(sparms.dir), sparms.idx);
@@ -2832,6 +2904,61 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+static int32_t
+ulp_mapper_gen_tbl_ref_cnt_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ struct ulp_mapper_gen_tbl_entry *entry)
+{
+ int32_t rc = 0;
+ uint64_t val64;
+
+ /* Allow the template to manage the reference count */
+ switch (tbl->ref_cnt_opcode) {
+ case BNXT_ULP_REF_CNT_OPC_INC:
+ ULP_GEN_TBL_REF_CNT_INC(entry);
+ break;
+ case BNXT_ULP_REF_CNT_OPC_DEC:
+ /* writes never decrement the ref count */
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_WRITE)
+ return -EINVAL;
+
+ ULP_GEN_TBL_REF_CNT_DEC(entry);
+ break;
+ case BNXT_ULP_REF_CNT_OPC_NOP:
+ /* Nothing to be done, generally used when
+ * template gets the ref_cnt to make a decision
+ */
+ break;
+ case BNXT_ULP_REF_CNT_OPC_DEFAULT:
+ /* This is the default case and is backward
+ * compatible with older templates
+ */
+ if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP)
+ ULP_GEN_TBL_REF_CNT_INC(entry);
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid REF_CNT_OPC %d\n",
+ tbl->ref_cnt_opcode);
+ return -EINVAL;
+ }
+
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_READ) {
+ /* Add ref_cnt to the regfile for template to use. */
+ val64 = (uint32_t)ULP_GEN_TBL_REF_CNT(entry);
+ val64 = tfp_cpu_to_be_64(val64);
+ rc = ulp_regfile_write(parms->regfile,
+ BNXT_ULP_RF_IDX_REF_CNT,
+ val64);
+ if (rc) {
+ BNXT_TF_DBG(ERR,
+ "Failed to write regfile[ref_cnt]\n");
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
static int32_t
ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -2886,6 +3013,7 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* The_key is a byte array convert it to a search index */
cache_key = ulp_blob_data_get(&key, &tmplen);
+
/* get the generic table */
gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx];
@@ -2949,10 +3077,6 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
"Failed to scan ident list\n");
return -EINVAL;
}
- if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {
- /* increment the reference count */
- ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
- }
/* it is a hit */
gen_tbl_miss = 0;
@@ -2969,8 +3093,13 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* store the hash index in the fdb */
key_index = hash_entry.hash_index;
}
- /* check the reference count */
- if (ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) {
+
+ /* check the reference count and ignore ref_cnt if NOP.
+ * NOP allows a write as an update.
+ */
+
+ if (tbl->ref_cnt_opcode != BNXT_ULP_REF_CNT_OPC_NOP &&
+ ULP_GEN_TBL_REF_CNT(&gen_tbl_ent)) {
/* a hit then error */
BNXT_TF_DBG(ERR, "generic entry already present\n");
return -EINVAL; /* success */
@@ -2999,8 +3128,6 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- /* increment the reference count */
- ULP_GEN_TBL_REF_CNT_INC(&gen_tbl_ent);
fdb_write = 1;
parms->shared_hndl = (uint64_t)tbl_idx << 32 | key_index;
break;
@@ -3030,9 +3157,24 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms,
ulp_flow_db_shared_session_set(&fid_parms, tbl->session_type);
rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
- if (rc)
+ if (rc) {
BNXT_TF_DBG(ERR, "Fail to add gen ent flowdb %d\n", rc);
+ return rc;
+ }
+
+ /* Reset the in-flight RID when generic table is written and the
+ * rid has been pushed into a handle (rid or fid). Once it has
+ * been written, we have persistent accounting of the resources.
+ */
+ if (tbl->tbl_opcode == BNXT_ULP_GENERIC_TBL_OPC_WRITE &&
+ (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE ||
+ tbl->fdb_opcode == BNXT_ULP_FDB_OPC_PUSH_FID))
+ parms->rid = 0;
+
+ rc = ulp_mapper_gen_tbl_ref_cnt_process(parms, tbl,
+ &gen_tbl_ent);
}
+
return rc;
}
@@ -3041,6 +3183,8 @@ ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
{
int32_t rc = 0;
+ uint64_t val64 = 0;
+ uint32_t rid;
/* process the fdb opcode for alloc push */
if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE) {
@@ -3049,7 +3193,204 @@ ulp_mapper_ctrl_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to do fdb alloc\n");
return rc;
}
+ } else if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_DELETE_RID_REGFILE) {
+ rc = ulp_regfile_read(parms->regfile, tbl->fdb_operand, &val64);
+ if (!rc) {
+ BNXT_TF_DBG(ERR, "Failed to get RID from regfile\n");
+ return rc;
+ }
+ rid = (uint32_t)tfp_be_to_cpu_64(val64);
+ rc = ulp_mapper_resources_free(parms->ulp_ctx,
+ BNXT_ULP_FDB_TYPE_RID,
+ rid);
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_mapper_vnic_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms;
+ uint16_t vnic_idx = 0, vnic_id = 0;
+ int32_t rc = 0;
+
+ switch (tbl->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_RSS:
+ if (tbl->tbl_opcode != BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE) {
+ BNXT_TF_DBG(ERR, "Invalid vnic table opcode\n");
+ return -EINVAL;
+ }
+ rc = bnxt_pmd_rss_action_create(parms, &vnic_idx, &vnic_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed create rss action\n");
+ return rc;
+ }
+ break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE:
+ if (tbl->tbl_opcode != BNXT_ULP_VNIC_TBL_OPC_ALLOC_WR_REGFILE) {
+ BNXT_TF_DBG(ERR, "Invalid vnic table opcode\n");
+ return -EINVAL;
+ }
+ rc = bnxt_pmd_queue_action_create(parms, &vnic_idx, &vnic_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed create queue action\n");
+ return rc;
+ }
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid vnic table sub type\n");
+ return -EINVAL;
+ }
+
+ /* Link the created vnic to the flow in the flow db */
+ memset(&fid_parms, 0, sizeof(fid_parms));
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = tbl->resource_func;
+ fid_parms.resource_type = tbl->resource_type;
+ fid_parms.resource_sub_type = tbl->resource_sub_type;
+ fid_parms.resource_hndl = vnic_idx;
+ fid_parms.critical_resource = tbl->critical_resource;
+ rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
+ rc);
+ return rc;
+ }
+ rc = ulp_regfile_write(parms->regfile, tbl->tbl_operand,
+ (uint64_t)tfp_cpu_to_be_64(vnic_id));
+ if (rc)
+ BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n",
+ tbl->tbl_operand, rc);
+
+ return rc;
+}
+
+/* Free the vnic resource */
+static int32_t
+ulp_mapper_vnic_tbl_res_free(struct bnxt_ulp_context *ulp __rte_unused,
+ struct tf *tfp,
+ struct ulp_flow_db_res_params *res)
+{
+ uint16_t vnic_idx = res->resource_hndl;
+
+ if (res->resource_sub_type ==
+ BNXT_ULP_RESOURCE_SUB_TYPE_VNIC_TABLE_QUEUE)
+ return bnxt_pmd_queue_action_delete(tfp, vnic_idx);
+ else
+ return bnxt_pmd_rss_action_delete(tfp, vnic_idx);
+}
+
+static int32_t
+ulp_mapper_global_res_free(struct bnxt_ulp_context *ulp __rte_unused,
+ struct tf *tfp __rte_unused,
+ struct ulp_flow_db_res_params *res)
+{
+ uint16_t port_id = 0, dport = 0; /* Not needed for free */
+ int32_t rc = 0;
+ uint8_t ttype;
+ uint32_t handle = res->resource_hndl;
+
+ switch (res->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN:
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN;
+ rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
+ &handle);
+ break;
+ default:
+ rc = -EINVAL;
+ BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
+ res->resource_sub_type);
+ break;
+ }
+
+ return rc;
+}
+
+static int32_t
+ulp_mapper_global_register_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms = { 0 };
+ struct ulp_blob data;
+ uint16_t data_len = 0;
+ uint8_t *tmp_data;
+ uint16_t udp_port;
+ uint32_t handle;
+ int32_t rc = 0, write_reg = 0;
+ uint8_t ttype;
+
+ /* Initialize the blob data */
+ if (!ulp_blob_init(&data, tbl->result_bit_size,
+ BNXT_ULP_BYTE_ORDER_BE)) {
+ BNXT_TF_DBG(ERR, "Failed initial ulp_global table blob\n");
+ return -EINVAL;
+ }
+
+ /* read the arguments from the result table */
+ rc = ulp_mapper_tbl_result_build(parms, tbl, &data,
+ "ULP Global Result");
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
+ return rc;
+ }
+
+ switch (tbl->tbl_opcode) {
+ case BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_WR_REGFILE:
+ write_reg = 1;
+ break;
+ case BNXT_ULP_GLOBAL_REGISTER_TBL_OPC_NOT_USED:
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Invalid global table opcode %d\n",
+ tbl->tbl_opcode);
+ return -EINVAL;
+ }
+
+ switch (tbl->resource_sub_type) {
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_VXLAN:
+ tmp_data = ulp_blob_data_get(&data, &data_len);
+ udp_port = *((uint16_t *)tmp_data);
+ udp_port = tfp_be_to_cpu_16(udp_port);
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN;
+
+ rc = bnxt_pmd_global_tunnel_set(parms->port_id, ttype,
+ udp_port, &handle);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to set VXLAN UDP port\n");
+ return rc;
+ }
+ break;
+ default:
+ rc = -EINVAL;
+ BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
+ tbl->resource_sub_type);
+ return rc;
}
+
+ /* Set the common pieces of fid parms */
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = tbl->resource_func;
+ fid_parms.resource_sub_type = tbl->resource_sub_type;
+ fid_parms.critical_resource = tbl->critical_resource;
+ fid_parms.resource_hndl = handle;
+
+ rc = ulp_mapper_fdb_opc_process(parms, tbl, &fid_parms);
+
+ if (rc)
+ return rc;
+
+ /* write to the regfile if opcode is set */
+ if (write_reg) {
+ rc = ulp_regfile_write(parms->regfile,
+ tbl->tbl_operand,
+ (uint64_t)tfp_cpu_to_be_64(handle));
+ if (rc)
+ BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n",
+ tbl->tbl_operand);
+ }
+
return rc;
}
@@ -3112,36 +3453,33 @@ ulp_mapper_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
-/*
- * Iterate over the shared resources assigned during tf_open_session and store
- * them in the global regfile with the shared flag.
- */
static int32_t
ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
- struct bnxt_ulp_mapper_data *mapper_data)
+ struct bnxt_ulp_mapper_data *mapper_data)
{
struct bnxt_ulp_glb_resource_info *glb_res;
uint32_t num_glb_res_ids, idx, dev_id;
uint8_t app_id;
- uint32_t rc = 0;
+ int32_t rc = 0;
glb_res = bnxt_ulp_app_glb_resource_info_list_get(&num_glb_res_ids);
if (!glb_res || !num_glb_res_ids) {
BNXT_TF_DBG(ERR, "Invalid Arguments\n");
return -EINVAL;
}
+
rc = bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get device_id for glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get device id for glb init (%d)\n",
rc);
- return -EINVAL;
+ return rc;
}
rc = bnxt_ulp_cntxt_app_id_get(ulp_ctx, &app_id);
if (rc) {
- BNXT_TF_DBG(ERR, "Failed to get app_id for glb init (%d)\n",
+ BNXT_TF_DBG(ERR, "Failed to get app id for glb init (%d)\n",
rc);
- return -EINVAL;
+ return rc;
}
/* Iterate the global resources and process each one */
@@ -3154,13 +3492,13 @@ ulp_mapper_app_glb_resource_info_init(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_mapper_resource_ident_allocate(ulp_ctx,
mapper_data,
&glb_res[idx],
- false);
+ true);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
rc = ulp_mapper_resource_index_tbl_alloc(ulp_ctx,
mapper_data,
&glb_res[idx],
- false);
+ true);
break;
default:
BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
@@ -3726,6 +4064,12 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
case BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE:
rc = ulp_mapper_ctrl_tbl_process(parms, tbl);
break;
+ case BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE:
+ rc = ulp_mapper_vnic_tbl_process(parms, tbl);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE:
+ rc = ulp_mapper_global_register_tbl_process(parms, tbl);
+ break;
case BNXT_ULP_RESOURCE_FUNC_INVALID:
rc = 0;
break;
@@ -3781,7 +4125,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
return rc;
error:
- BNXT_TF_DBG(ERR, "%s tables failed creation for %d:%d\n",
+ BNXT_TF_DBG(ERR, "%s tables failed operation for %d:%d\n",
ulp_mapper_tmpl_name_str(parms->tmpl_type),
parms->dev_id, tid);
return rc;
@@ -3828,7 +4172,13 @@ ulp_mapper_resource_free(struct bnxt_ulp_context *ulp,
rc = ulp_mapper_child_flow_free(ulp, fid, res);
break;
case BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE:
- rc = ulp_mapper_gen_tbl_res_free(ulp, res);
+ rc = ulp_mapper_gen_tbl_res_free(ulp, fid, res);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_VNIC_TABLE:
+ rc = ulp_mapper_vnic_tbl_res_free(ulp, tfp, res);
+ break;
+ case BNXT_ULP_RESOURCE_FUNC_GLOBAL_REGISTER_TABLE:
+ rc = ulp_mapper_global_res_free(ulp, tfp, res);
break;
default:
break;
@@ -4045,11 +4395,26 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
return rc;
flow_error:
+ if (parms.rid) {
+ /* An RID was in-flight but not pushed, free the resources */
+ trc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_RID,
+ parms.rid);
+ if (trc)
+ BNXT_TF_DBG(ERR,
+ "Failed to free resources rid=0x%08x rc=%d\n",
+ parms.rid, trc);
+ parms.rid = 0;
+ }
+
/* Free all resources that were allocated during flow creation */
- trc = ulp_mapper_flow_destroy(ulp_ctx, parms.flow_type,
- parms.fid);
- if (trc)
- BNXT_TF_DBG(ERR, "Failed to free all resources rc=%d\n", trc);
+ if (parms.fid) {
+ trc = ulp_mapper_flow_destroy(ulp_ctx, parms.flow_type,
+ parms.fid);
+ if (trc)
+ BNXT_TF_DBG(ERR,
+ "Failed to free resources fid=0x%08x rc=%d\n",
+ parms.fid, trc);
+ }
return rc;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index b7e6f3ada2..225a14ccfa 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -52,6 +52,7 @@ struct bnxt_ulp_mapper_parms {
struct ulp_regfile *regfile;
struct bnxt_ulp_context *ulp_ctx;
uint32_t fid;
+ uint32_t rid;
enum bnxt_ulp_fdb_type flow_type;
struct bnxt_ulp_mapper_data *mapper_data;
struct bnxt_ulp_device_params *device_params;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index 67fa61fc7c..8c90998a7d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -29,8 +29,8 @@ ulp_matcher_action_hash_calculate(uint64_t hi_sig, uint64_t app_id)
hi_sig |= ((hi_sig % BNXT_ULP_ACT_HID_HIGH_PRIME) <<
BNXT_ULP_ACT_HID_SHFTL);
- app_id |= ((app_id % BNXT_ULP_CLASS_HID_LOW_PRIME) <<
- (BNXT_ULP_CLASS_HID_SHFTL + 2));
+ app_id |= ((app_id % BNXT_ULP_ACT_HID_LOW_PRIME) <<
+ (BNXT_ULP_ACT_HID_SHFTL + 2));
hash = hi_sig ^ app_id;
hash = (hash >> BNXT_ULP_ACT_HID_SHFTR) & BNXT_ULP_ACT_HID_MASK;
return (uint32_t)hash;
@@ -46,12 +46,8 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
{
struct bnxt_ulp_class_match_info *class_match;
uint32_t class_hid;
- uint8_t vf_to_vf;
uint16_t tmpl_id;
- /* Get vf to vf flow */
- vf_to_vf = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_VF_TO_VF);
-
/* calculate the hash of the given flow */
class_hid = ulp_matcher_class_hash_calculate((params->hdr_bitmap.bits ^
params->app_id),
@@ -81,10 +77,6 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
goto error;
}
- if (vf_to_vf != class_match->act_vnic) {
- BNXT_TF_DBG(DEBUG, "Vnic Match failed\n");
- goto error;
- }
BNXT_TF_DBG(DEBUG, "Found matching pattern template %d\n",
class_match->class_tid);
*class_id = class_match->class_tid;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
index 57c9e7d175..ba1f966ec3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c
@@ -150,6 +150,11 @@ int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
intf = &port_db->ulp_intf_list[ifindex];
intf->type = bnxt_pmd_get_interface_type(port_id);
+ if (intf->type == BNXT_ULP_INTF_TYPE_PF)
+ intf->type_is_pf = 1;
+ else
+ intf->type_is_pf = 0;
+
intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id,
BNXT_ULP_INTF_TYPE_INVALID);
@@ -182,6 +187,9 @@ int32_t ulp_port_db_port_update(struct bnxt_ulp_context *ulp_ctxt,
bnxt_pmd_get_vnic_id(port_id, BNXT_ULP_INTF_TYPE_VF_REP);
func->phy_port_id = bnxt_pmd_get_phy_port_id(port_id);
func->ifindex = ifindex;
+ func->func_valid = true;
+ func->vf_meta_data = tfp_cpu_to_be_16(BNXT_ULP_META_VF_FLAG |
+ intf->vf_func_id);
}
/* When there is no match, the default action is to send the packet to
@@ -702,3 +710,53 @@ ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
}
return -EINVAL;
}
+
+/*
+ * Api to get the port type for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * type [out] type if pf or not
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_is_pf_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint8_t **type)
+{
+ struct ulp_func_if_info *info;
+ struct bnxt_ulp_port_db *port_db;
+ uint16_t pid;
+
+ port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt);
+ info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
+ if (info) {
+ pid = info->ifindex;
+ *type = &port_db->ulp_intf_list[pid].type_is_pf;
+ return 0;
+ }
+ return -EINVAL;
+}
+
+/*
+ * Api to get the meta data for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * meta data [out] the meta data of the given port
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_meta_data_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint16_t port_id, uint8_t **meta_data)
+{
+ struct ulp_func_if_info *info;
+
+ info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
+ if (info) {
+ *meta_data = (uint8_t *)&info->vf_meta_data;
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.h b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
index 784b93f8b3..d4efe0a3d5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_port_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.h
@@ -328,4 +328,30 @@ ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
int32_t
ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint16_t *phy_port);
+
+/*
+ * Api to get the port type for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * type [out] type if pf or not
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_is_pf_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint8_t **type);
+
+/*
+ * Api to get the meta data for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] dpdk port id
+ * meta data [out] the meta data of the given port
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_port_meta_data_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint16_t port_id, uint8_t **meta_data);
#endif /* _ULP_PORT_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 9cf1ebfe1d..1fbfe18db3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -38,8 +38,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_QUEUE] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_queue_act_handler
},
[RTE_FLOW_ACTION_TYPE_DROP] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
@@ -162,12 +162,12 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_set_mac_src_act_handler
},
[RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_set_mac_dst_act_handler
},
[RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
@@ -197,6 +197,14 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_port_act_handler
},
+ [RTE_FLOW_ACTION_TYPE_INDIRECT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_action_hdlr_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_INDIRECT + 1] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
};
struct bnxt_ulp_rte_act_info ulp_vendor_act_info[] = {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 3566f3000b..d7450b92ff 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -24,6 +24,7 @@
#define ULP_VLAN_PRIORITY_MASK 0x700
#define ULP_VLAN_TAG_MASK 0xFFF /* Last 12 bits*/
#define ULP_UDP_PORT_VXLAN 4789
+#define ULP_UDP_PORT_VXLAN_MASK 0XFFFF
/* Utility function to skip the void items. */
static inline int32_t
@@ -190,7 +191,7 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
hdr_info = &ulp_vendor_act_info[action_item->type -
BNXT_RTE_FLOW_ACTION_TYPE_END];
} else {
- if (action_item->type > RTE_FLOW_ACTION_TYPE_SHARED)
+ if (action_item->type > RTE_FLOW_ACTION_TYPE_INDIRECT)
goto act_parser_error;
/* get the header information from the act info table */
hdr_info = &ulp_act_info[action_item->type];
@@ -227,7 +228,7 @@ static void
bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
{
uint32_t ifindex;
- uint16_t port_id, parif;
+ uint16_t port_id, parif, svif;
uint32_t mtype;
enum bnxt_ulp_direction_type dir;
@@ -252,6 +253,14 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
}
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
parif);
+ /* Set port SVIF */
+ if (ulp_port_db_svif_get(params->ulp_ctx, ifindex,
+ BNXT_ULP_PHY_PORT_SVIF, &svif)) {
+ BNXT_TF_DBG(ERR, "ParseErr:ifindex is not valid\n");
+ return;
+ }
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_PHY_PORT_SVIF,
+ svif);
} else {
/* Get the match port type */
mtype = ULP_COMP_FLD_IDX_RD(params,
@@ -317,10 +326,11 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
BNXT_ULP_FLOW_DIR_BITMASK_EGR);
}
- /* calculate the VF to VF flag */
+ /* Evaluate the VF to VF flag */
if (act_port_set && act_port_type == BNXT_ULP_INTF_TYPE_VF_REP &&
match_port_type == BNXT_ULP_INTF_TYPE_VF_REP)
- ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_VF_TO_VF, 1);
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_VF_TO_VF);
/* Update the decrement ttl computational fields */
if (ULP_BITMAP_ISSET(params->act_bitmap.bits,
@@ -438,8 +448,7 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
else
svif_type = BNXT_ULP_DRV_FUNC_SVIF;
}
- ulp_port_db_svif_get(params->ulp_ctx, ifindex, svif_type,
- &svif);
+ ulp_port_db_svif_get(params->ulp_ctx, ifindex, svif_type, &svif);
svif = rte_cpu_to_be_16(svif);
hdr_field = ¶ms->hdr_field[BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX];
memcpy(hdr_field->spec, &svif, sizeof(svif));
@@ -575,8 +584,11 @@ ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
/* Function to handle the update of proto header based on field values */
static void
ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
- uint16_t type, uint32_t in_flag)
+ uint16_t type, uint32_t in_flag,
+ uint32_t has_vlan, uint32_t has_vlan_mask)
{
+#define ULP_RTE_ETHER_TYPE_ROE 0xfc3d
+
if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV4)) {
if (in_flag) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
@@ -587,7 +599,7 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
BNXT_ULP_HDR_BIT_O_IPV4);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1);
}
- } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV6)) {
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV6)) {
if (in_flag) {
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_I_IPV6);
@@ -597,6 +609,29 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
BNXT_ULP_HDR_BIT_O_IPV6);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1);
}
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
+ has_vlan_mask = 1;
+ has_vlan = 1;
+ } else if (type == tfp_cpu_to_be_16(ULP_RTE_ETHER_TYPE_ROE)) {
+ /* Update the hdr_bitmap with RoE */
+ ULP_BITMAP_SET(param->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_O_ROE);
+ }
+
+ if (has_vlan_mask) {
+ if (in_flag) {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_HAS_VTAG,
+ has_vlan);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_VLAN_NO_IGNORE,
+ 1);
+ } else {
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_HAS_VTAG,
+ has_vlan);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_VLAN_NO_IGNORE,
+ 1);
+ }
}
}
@@ -624,17 +659,25 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint16_t eth_type = 0;
uint32_t inner_flag = 0;
+ uint32_t has_vlan = 0, has_vlan_mask = 0;
/* Perform validations */
if (eth_spec) {
- /* Todo: work around to avoid multicast and broadcast addr */
- if (ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.dst_addr))
+ /* Avoid multicast and broadcast addr */
+ if (!ULP_APP_BC_MC_SUPPORT(params->ulp_ctx) &&
+ ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.dst_addr))
return BNXT_TF_RC_PARSE_ERR;
- if (ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.src_addr))
+ if (!ULP_APP_BC_MC_SUPPORT(params->ulp_ctx) &&
+ ulp_rte_parser_is_bcmc_addr(ð_spec->hdr.src_addr))
return BNXT_TF_RC_PARSE_ERR;
eth_type = eth_spec->hdr.ether_type;
+ has_vlan = eth_spec->has_vlan;
+ }
+ if (eth_mask) {
+ eth_type &= eth_mask->hdr.ether_type;
+ has_vlan_mask = eth_mask->has_vlan;
}
if (ulp_rte_prsr_fld_size_validate(params, &idx,
@@ -663,7 +706,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(eth_spec, hdr.ether_type),
ulp_deference_struct(eth_mask, hdr.ether_type),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
/* Update the protocol hdr bitmap */
if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
@@ -684,7 +728,8 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
dmac_idx);
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
+ ulp_rte_l2_proto_type_update(params, eth_type, inner_flag,
+ has_vlan, has_vlan_mask);
return BNXT_TF_RC_SUCCESS;
}
@@ -837,7 +882,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_ERROR;
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l2_proto_type_update(params, eth_type, inner_flag);
+ ulp_rte_l2_proto_type_update(params, eth_type, inner_flag, 1, 1);
return BNXT_TF_RC_SUCCESS;
}
@@ -876,22 +921,21 @@ ulp_rte_l3_proto_type_update(struct ulp_rte_parser_params *param,
ULP_BITMAP_SET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_O_ICMP);
}
- if (proto) {
- if (in_flag) {
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
- proto);
- } else {
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
- 1);
- ULP_COMP_FLD_IDX_WR(param,
- BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
- proto);
- }
+
+ if (in_flag) {
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
+ proto);
+ } else {
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
+ 1);
+ ULP_COMP_FLD_IDX_WR(param,
+ BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
+ proto);
}
}
@@ -906,6 +950,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = 0, dip_idx = 0;
uint32_t size;
uint8_t proto = 0;
+ uint8_t proto_mask = 0;
uint32_t inner_flag = 0;
uint32_t cnt;
@@ -934,8 +979,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
/*
* The tos field is ignored since OVS is setting it as wild card
- * match and it is not supported. This is a work around and
- * shall be addressed in the future.
+ * match and it is not supported. An application can enable tos support.
*/
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.type_of_service);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -943,7 +987,8 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
hdr.type_of_service),
ulp_deference_struct(ipv4_mask,
hdr.type_of_service),
- ULP_PRSR_ACT_MASK_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MASK_IGNORE);
size = sizeof(((struct rte_flow_item_ipv4 *)NULL)->hdr.total_length);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -978,7 +1023,9 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
hdr.next_proto_id),
ulp_deference_struct(ipv4_mask,
hdr.next_proto_id),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
+
if (ipv4_spec)
proto = ipv4_spec->hdr.next_proto_id;
@@ -1020,11 +1067,14 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
* in the IPv4 spec but don't set the mask. So, consider
* the mask in the proto value calculation.
*/
- if (ipv4_mask)
+ if (ipv4_mask) {
proto &= ipv4_mask->hdr.next_proto_id;
+ proto_mask = ipv4_mask->hdr.next_proto_id;
+ }
/* Update the field protocol hdr bitmap */
- ulp_rte_l3_proto_type_update(params, proto, inner_flag);
+ if (proto_mask)
+ ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
}
@@ -1038,11 +1088,12 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_ipv6 *ipv6_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0, dip_idx = 0;
- uint32_t size;
+ uint32_t size, vtc_flow;
uint32_t ver_spec = 0, ver_mask = 0;
uint32_t tc_spec = 0, tc_mask = 0;
uint32_t lab_spec = 0, lab_mask = 0;
uint8_t proto = 0;
+ uint8_t proto_mask = 0;
uint32_t inner_flag = 0;
uint32_t cnt;
@@ -1064,22 +1115,25 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
* header fields
*/
if (ipv6_spec) {
- ver_spec = BNXT_ULP_GET_IPV6_VER(ipv6_spec->hdr.vtc_flow);
- tc_spec = BNXT_ULP_GET_IPV6_TC(ipv6_spec->hdr.vtc_flow);
- lab_spec = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_spec->hdr.vtc_flow);
+ vtc_flow = ntohl(ipv6_spec->hdr.vtc_flow);
+ ver_spec = htonl(BNXT_ULP_GET_IPV6_VER(vtc_flow));
+ tc_spec = htonl(BNXT_ULP_GET_IPV6_TC(vtc_flow));
+ lab_spec = htonl(BNXT_ULP_GET_IPV6_FLOWLABEL(vtc_flow));
proto = ipv6_spec->hdr.proto;
}
if (ipv6_mask) {
- ver_mask = BNXT_ULP_GET_IPV6_VER(ipv6_mask->hdr.vtc_flow);
- tc_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow);
- lab_mask = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow);
+ vtc_flow = ntohl(ipv6_mask->hdr.vtc_flow);
+ ver_mask = htonl(BNXT_ULP_GET_IPV6_VER(vtc_flow));
+ tc_mask = htonl(BNXT_ULP_GET_IPV6_TC(vtc_flow));
+ lab_mask = htonl(BNXT_ULP_GET_IPV6_FLOWLABEL(vtc_flow));
/* Some of the PMD applications may set the protocol field
* in the IPv6 spec but don't set the mask. So, consider
* the mask in proto value calculation.
*/
proto &= ipv6_mask->hdr.proto;
+ proto_mask = ipv6_mask->hdr.proto;
}
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.vtc_flow);
@@ -1092,7 +1146,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
* shall be addressed in the future.
*/
ulp_rte_prsr_fld_mask(params, &idx, size, &tc_spec, &tc_mask,
- ULP_PRSR_ACT_MASK_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MASK_IGNORE);
ulp_rte_prsr_fld_mask(params, &idx, size, &lab_spec, &lab_mask,
ULP_PRSR_ACT_MASK_IGNORE);
@@ -1107,7 +1162,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
ulp_rte_prsr_fld_mask(params, &idx, size,
ulp_deference_struct(ipv6_spec, hdr.proto),
ulp_deference_struct(ipv6_mask, hdr.proto),
- ULP_PRSR_ACT_MATCH_IGNORE);
+ (ULP_APP_TOS_PROTO_SUPPORT(params->ulp_ctx)) ?
+ ULP_PRSR_ACT_DEFAULT : ULP_PRSR_ACT_MATCH_IGNORE);
size = sizeof(((struct rte_flow_item_ipv6 *)NULL)->hdr.hop_limits);
ulp_rte_prsr_fld_mask(params, &idx, size,
@@ -1144,7 +1200,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
}
/* Update the field protocol hdr bitmap */
- ulp_rte_l3_proto_type_update(params, proto, inner_flag);
+ if (proto_mask)
+ ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
return BNXT_TF_RC_SUCCESS;
@@ -1280,7 +1337,8 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP) ||
+ ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN))
out_l4 = BNXT_ULP_HDR_BIT_I_UDP;
ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
@@ -1385,7 +1443,8 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
/* Set the udp header bitmap and computed l4 header bitmaps */
if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
- ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP))
+ ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP) ||
+ ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN))
out_l4 = BNXT_ULP_HDR_BIT_I_TCP;
ulp_rte_l4_proto_type_update(params, sport, sport_mask, dport,
@@ -1403,6 +1462,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
const struct rte_flow_item_vxlan *vxlan_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
uint32_t idx = 0;
+ uint16_t dport;
uint32_t size;
if (ulp_rte_prsr_fld_size_validate(params, &idx,
@@ -1442,6 +1502,15 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
+
+ dport = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT);
+ if (!dport) {
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
+ ULP_UDP_PORT_VXLAN);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT_MASK,
+ ULP_UDP_PORT_VXLAN_MASK);
+ }
+
return BNXT_TF_RC_SUCCESS;
}
@@ -1637,6 +1706,8 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
{
const struct rte_flow_action_rss *rss;
struct ulp_rte_act_prop *ap = ¶m->act_prop;
+ uint64_t queue_list[BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE / sizeof(uint64_t)];
+ uint32_t idx = 0, id;
if (action_item == NULL || action_item->conf == NULL) {
BNXT_TF_DBG(ERR, "Parse Err: invalid rss configuration\n");
@@ -1652,12 +1723,50 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY_LEN],
&rss->key_len, BNXT_ULP_ACT_PROP_SZ_RSS_KEY_LEN);
- if (rss->key_len > BNXT_ULP_ACT_PROP_SZ_RSS_KEY) {
- BNXT_TF_DBG(ERR, "Parse Err: RSS key too big\n");
+ if (rss->key_len != 0 && rss->key_len != BNXT_ULP_ACT_PROP_SZ_RSS_KEY) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS key length must be 40 bytes\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ /* User may specify only key length. In that case, rss->key will be NULL.
+ * So, reject the flow if key_length is valid but rss->key is NULL.
+ * Also, copy the RSS hash key only when rss->key is valid.
+ */
+ if (rss->key_len != 0 && rss->key == NULL) {
+ BNXT_TF_DBG(ERR,
+ "Parse Err: A valid RSS key must be provided with a valid key len.\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ if (rss->key)
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY], rss->key, rss->key_len);
+
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE_NUM],
+ &rss->queue_num, BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE_NUM);
+
+ if (rss->queue_num >= ULP_BYTE_2_BITS(BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE)) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS queue num too big\n");
return BNXT_TF_RC_ERROR;
}
- memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_KEY], rss->key,
- rss->key_len);
+
+ /* Queues converted into a bitmap format */
+ memset(queue_list, 0, sizeof(queue_list));
+ for (idx = 0; idx < rss->queue_num; idx++) {
+ id = rss->queue[idx];
+ if (id >= ULP_BYTE_2_BITS(BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE)) {
+ BNXT_TF_DBG(ERR, "Parse Err: RSS queue id too big\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ if ((queue_list[id / ULP_INDEX_BITMAP_SIZE] >>
+ ((ULP_INDEX_BITMAP_SIZE - 1) -
+ (id % ULP_INDEX_BITMAP_SIZE)) & 1)) {
+ BNXT_TF_DBG(ERR, "Parse Err: duplicate queue ids\n");
+ return BNXT_TF_RC_ERROR;
+ }
+ queue_list[id / ULP_INDEX_BITMAP_SIZE] |= (1UL <<
+ ((ULP_INDEX_BITMAP_SIZE - 1) - (id % ULP_INDEX_BITMAP_SIZE)));
+ }
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_RSS_QUEUE],
+ (uint8_t *)queue_list, BNXT_ULP_ACT_PROP_SZ_RSS_QUEUE);
/* set the RSS action header bit */
ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS);
@@ -2253,6 +2362,8 @@ ulp_rte_port_act_handler(const struct rte_flow_action *act_item,
/* Set the action port */
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_ACT_PORT_TYPE, intf_type);
+ ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_DEV_ACT_PORT_ID,
+ ethdev_id);
return ulp_rte_parser_act_port_set(param, ifindex, act_dir);
}
@@ -2484,6 +2595,63 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
return ret;
}
+int32_t
+ulp_rte_action_hdlr_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_handle *handle;
+ struct bnxt_ulp_shared_act_info *act_info;
+ uint64_t action_bitmask;
+ uint32_t shared_action_type;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+ uint64_t tmp64;
+ enum bnxt_ulp_direction_type dir, handle_dir;
+ uint32_t act_info_entries = 0;
+ int32_t ret;
+
+ handle = action_item->conf;
+
+ /* Have to use the computed direction since the params->dir_attr
+ * can be different (transfer, ingress, egress)
+ */
+ dir = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_DIRECTION);
+
+ /* direction of shared action must match direction of flow */
+ ret = bnxt_get_action_handle_direction(handle, &handle_dir);
+ if (ret || dir != handle_dir) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle or direction\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ if (bnxt_get_action_handle_type(handle, &shared_action_type)) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ act_info = bnxt_ulp_shared_act_info_get(&act_info_entries);
+ if (shared_action_type >= act_info_entries || !act_info) {
+ BNXT_TF_DBG(ERR, "Invalid shared handle\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ action_bitmask = act_info[shared_action_type].act_bitmask;
+
+ /* shared actions of the same type cannot be repeated */
+ if (params->act_bitmap.bits & action_bitmask) {
+ BNXT_TF_DBG(ERR, "indirect actions cannot be repeated\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ tmp64 = tfp_cpu_to_be_64((uint64_t)bnxt_get_action_handle_index(handle));
+
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SHARED_HANDLE],
+ &tmp64, BNXT_ULP_ACT_PROP_SZ_SHARED_HANDLE);
+
+ ULP_BITMAP_SET(params->act_bitmap.bits, action_bitmask);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of bnxt vendor Flow action vxlan Header. */
int32_t
ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
@@ -2504,3 +2672,69 @@ ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F2);
return ulp_rte_vxlan_decap_act_handler(NULL, params);
}
+
+/* Function to handle the parsing of RTE Flow action queue. */
+int32_t
+ulp_rte_queue_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *param)
+{
+ const struct rte_flow_action_queue *q_info;
+ struct ulp_rte_act_prop *ap = ¶m->act_prop;
+
+ if (action_item == NULL || action_item->conf == NULL) {
+ BNXT_TF_DBG(ERR, "Parse Err: invalid queue configuration\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ q_info = action_item->conf;
+ /* Copy the queue into the specific action properties */
+ memcpy(&ap->act_details[BNXT_ULP_ACT_PROP_IDX_QUEUE_INDEX],
+ &q_info->index, BNXT_ULP_ACT_PROP_SZ_QUEUE_INDEX);
+
+ /* set the queue action header bit */
+ ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_QUEUE);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_set_mac *set_mac;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+
+ set_mac = action_item->conf;
+ if (set_mac) {
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC],
+ set_mac->mac_addr, BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC);
+ /* Update the hdr_bitmap with set mac src */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_SET_MAC_SRC);
+ return BNXT_TF_RC_SUCCESS;
+ }
+ BNXT_TF_DBG(ERR, "Parse Error: set mac src arg is invalid\n");
+ return BNXT_TF_RC_ERROR;
+}
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_set_mac *set_mac;
+ struct ulp_rte_act_prop *act = ¶ms->act_prop;
+
+ set_mac = action_item->conf;
+ if (set_mac) {
+ memcpy(&act->act_details[BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST],
+ set_mac->mac_addr, BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST);
+ /* Update the hdr_bitmap with set ipv4 dst */
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_ACT_BIT_SET_MAC_DST);
+ return BNXT_TF_RC_SUCCESS;
+ }
+ BNXT_TF_DBG(ERR, "Parse Error: set mac dst arg is invalid\n");
+ return BNXT_TF_RC_ERROR;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index b0b2b4f33f..401ce4885d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2014-2021 Broadcom
+ * Copyright(c) 2014-2023 Broadcom
* All rights reserved.
*/
@@ -80,6 +80,16 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
void
bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow item PF Header. */
+int32_t
+ulp_rte_pf_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow item VF Header. */
+int32_t
+ulp_rte_vf_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
/* Parse items PORT_ID, PORT_REPRESENTOR and REPRESENTED_PORT. */
int32_t
ulp_rte_port_hdr_handler(const struct rte_flow_item *item,
@@ -238,6 +248,15 @@ ulp_rte_set_tp_dst_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow action JUMP .*/
int32_t
@@ -249,7 +268,7 @@ ulp_rte_sample_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
-ulp_rte_shared_act_handler(const struct rte_flow_action *action_item,
+ulp_rte_action_hdlr_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
int32_t
@@ -259,4 +278,18 @@ ulp_vendor_vxlan_decap_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_vendor_vxlan_decap_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
+
+int32_t
+ulp_rte_queue_act_handler(const struct rte_flow_action *act_item,
+ struct ulp_rte_parser_params *param);
+
+/* Function to handle the parsing of RTE Flow action set mac src.*/
+int32_t
+ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action set mac dst.*/
+int32_t
+ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
#endif /* _ULP_RTE_PARSER_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 07/11] net/bnxt: add support for rte meter
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (5 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
` (3 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Randy Schacher, Jay Ding
[-- Attachment #1: Type: text/plain, Size: 32690 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Add RTE meter support into the ULP layer.
Currently:
- Chaining of meters is not supported
- Meter can be shared by multiple flows
- srtcm_rfc2697 type is supported
- Stats are not supported in the implementation yet
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/nics/features/bnxt.ini | 1 +
drivers/net/bnxt/bnxt.h | 2 +
drivers/net/bnxt/bnxt_ethdev.c | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 8 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 3 +
drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 ++++++++++++++++++
drivers/net/bnxt/tf_ulp/meson.build | 1 +
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 29 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
10 files changed, 961 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index b225878a78..8b523e3bef 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -77,6 +77,7 @@ dec_ttl = Y
drop = Y
jump = Y
mark = Y
+meter = Y
of_pop_vlan = Y
of_push_vlan = Y
of_set_vlan_pcp = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 6dd3c8b87c..7d508c7c23 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1014,6 +1014,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel);
extern const struct rte_flow_ops bnxt_flow_ops;
+extern const struct rte_flow_ops bnxt_flow_meter_ops;
#define bnxt_acquire_flow_lock(bp) \
pthread_mutex_lock(&(bp)->flow_lock)
@@ -1065,6 +1066,7 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+int bnxt_flow_meter_ops_get(struct rte_eth_dev *eth_dev, void *arg);
struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp);
struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 4d84aaee0c..7bceb0524a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4091,6 +4091,7 @@ static const struct eth_dev_ops bnxt_dev_ops = {
.timesync_adjust_time = bnxt_timesync_adjust_time,
.timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
+ .mtr_ops_get = bnxt_flow_meter_ops_get,
};
static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 08eb0c6063..3459140f18 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1681,6 +1681,14 @@ bnxt_ulp_init(struct bnxt *bp,
return rc;
}
+ if (ulp_dev_id == BNXT_ULP_DEVICE_ID_THOR) {
+ rc = bnxt_flow_meter_init(bp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to config meter\n");
+ goto jump_to_error;
+ }
+ }
+
BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
return rc;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 53d76e1465..a6ad5c1eaa 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -371,6 +371,9 @@ bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
unsigned int
bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+int32_t
+bnxt_flow_meter_init(struct bnxt *bp);
+
uint32_t
bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
new file mode 100644
index 0000000000..2461c46f90
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
@@ -0,0 +1,909 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include <math.h>
+#include <sys/queue.h>
+
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_flow.h>
+#include <rte_flow_driver.h>
+#include <rte_tailq.h>
+#include <rte_alarm.h>
+#include <rte_cycles.h>
+#include <rte_mtr.h>
+#include <rte_mtr_driver.h>
+
+#include "bnxt.h"
+#include "bnxt_filter.h"
+#include "bnxt_hwrm.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxq.h"
+#include "bnxt_rxr.h"
+#include "bnxt_vnic.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "tfp.h"
+#include "bnxt_tf_common.h"
+#include "ulp_rte_parser.h"
+#include "ulp_matcher.h"
+#include "ulp_flow_db.h"
+#include "ulp_mapper.h"
+#include "ulp_fc_mgr.h"
+#include "ulp_port_db.h"
+#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
+#include <rte_malloc.h>
+
+/**
+ * Meter init status
+ */
+int bnxt_meter_initialized;
+
+/**
+ * Internal api to config global config.
+ * returns 0 on success.
+ */
+static int32_t
+bnxt_meter_global_cfg_update(struct bnxt *bp,
+ enum tf_dir dir,
+ enum tf_global_config_type type,
+ uint32_t offset,
+ uint32_t value,
+ uint32_t set_flag)
+{
+ uint32_t global_cfg = 0;
+ struct tf_global_cfg_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ parms.dir = dir,
+ parms.type = type,
+ parms.offset = offset,
+ parms.config = (uint8_t *)&global_cfg,
+ parms.config_sz_in_bytes = sizeof(global_cfg);
+
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_global_cfg(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to get global cfg 0x%x rc:%d\n",
+ type, rc);
+ return rc;
+ }
+
+ if (set_flag)
+ global_cfg |= value;
+ else
+ global_cfg &= ~value;
+
+ rc = tf_set_global_cfg(tfp, &parms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set global cfg 0x%x rc:%d\n",
+ type, rc);
+ return rc;
+ }
+ return rc;
+}
+
+/**
+ * When a port is initialized by dpdk. This functions is called
+ * to enable the meter and initializes the meter global configurations.
+ */
+#define BNXT_THOR_FMTCR_NUM_MET_MET_1K (0x7UL << 20)
+#define BNXT_THOR_FMTCR_CNTRS_ENABLE (0x1UL << 25)
+#define BNXT_THOR_FMTCR_INTERVAL_1K (1024)
+int32_t
+bnxt_flow_meter_init(struct bnxt *bp)
+{
+ int rc = 0;
+
+ /*
+ * Enable metering. Set the meter global configuration register.
+ * Set number of meter to 1K. Disable the drop counter for now.
+ */
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_RX, TF_METER_CFG,
+ 0,
+ BNXT_THOR_FMTCR_NUM_MET_MET_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set rx meter configuration\n");
+ goto jump_to_error;
+ }
+
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_TX, TF_METER_CFG,
+ 0,
+ BNXT_THOR_FMTCR_NUM_MET_MET_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set tx meter configuration\n");
+ goto jump_to_error;
+ }
+
+ /*
+ * Set meter refresh rate to 1024 clock cycle. This value works for
+ * most bit rates especially for high rates.
+ */
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_RX, TF_METER_INTERVAL_CFG,
+ 0,
+ BNXT_THOR_FMTCR_INTERVAL_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set rx meter interval\n");
+ goto jump_to_error;
+ }
+
+ rc = bnxt_meter_global_cfg_update(bp, TF_DIR_TX, TF_METER_INTERVAL_CFG,
+ 0,
+ BNXT_THOR_FMTCR_INTERVAL_1K,
+ 1);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to set tx meter interval\n");
+ goto jump_to_error;
+ }
+
+ bnxt_meter_initialized = 1;
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter has been initialized\n");
+ return rc;
+
+jump_to_error:
+ return rc;
+}
+
+/**
+ * Get meter capabilities.
+ */
+#define MAX_FLOW_PER_METER 1024
+#define MAX_METER_RATE_100GBPS ((1ULL << 30) * 100 / 8)
+static int
+bnxt_flow_mtr_cap_get(struct rte_eth_dev *dev,
+ struct rte_mtr_capabilities *cap,
+ struct rte_mtr_error *error)
+{
+ struct bnxt *bp = dev->data->dev_private;
+ uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST;
+ struct tf_get_session_info_parms iparms;
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id);
+ if (rc)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Unable to get device id from ulp");
+
+ /* Get number of meter reserved for this session */
+ memset(&iparms, 0, sizeof(iparms));
+ tfp = bnxt_ulp_bp_tfp_get(bp, BNXT_ULP_SESSION_TYPE_DEFAULT);
+ rc = tf_get_session_info(tfp, &iparms);
+ if (rc != 0)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to get session resource info");
+
+ memset(cap, 0, sizeof(struct rte_mtr_capabilities));
+
+ cap->n_max = iparms.session_info.tbl[TF_DIR_RX].info[TF_TBL_TYPE_METER_INST].stride;
+ if (!cap->n_max)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL,
+ "Meter is not supported");
+
+ cap->srtcm_rfc2697_byte_mode_supported = 1;
+ cap->n_shared_max = cap->n_max;
+ /* No meter is identical */
+ cap->identical = 1;
+ cap->shared_identical = 1;
+ cap->shared_n_flows_per_mtr_max = MAX_FLOW_PER_METER;
+ cap->chaining_n_mtrs_per_flow_max = 1; /* Chaining is not supported. */
+ cap->meter_srtcm_rfc2697_n_max = cap->n_max;
+ cap->meter_rate_max = MAX_METER_RATE_100GBPS;
+ /* No stats supported now */
+ cap->stats_mask = 0;
+
+ return 0;
+}
+
+/**
+ * Calculate mantissa and exponent for cir / eir reg.
+ */
+#define BNXT_CPU_CLOCK 800
+#define MEGA 1000000
+#define NUM_BIT_PER_BYTE 8
+static inline void
+bnxt_ulp_flow_meter_xir_calc(int64_t xir, uint32_t *reg)
+{
+ int64_t temp;
+ uint16_t m = 0;
+ uint16_t e = 0;
+ uint8_t *swap = 0;
+
+ /* Special case xir == 0 ? both exp and matissa are 0. */
+ if (xir == 0) {
+ *reg = 0;
+ return;
+ }
+
+ /*
+ * e = floor(log2(cir)) + 27
+ * a (MBps) = xir (bps) / MEGA
+ * b (MBpc) = a (MBps) / CPU_CLOCK (Mcps)
+ * e = floor(log2(b)) + 27
+ */
+ temp = xir * (1 << 24) / (BNXT_CPU_CLOCK >> 3) / MEGA;
+ e = log2(temp);
+
+ /*
+ * m = round(b/2^(e-27) - 1) * 2048
+ * = round(b*2^(27-e) - 1) * 2^11
+ * = round(b*2^(38-e) - 2^11)
+ *
+ */
+ m = xir * (1 << (38 - e)) / BNXT_CPU_CLOCK / MEGA - (1 << 11);
+ *reg = ((m & 0x7FF) << 6) | (e & 0x3F);
+ swap = (uint8_t *)reg;
+ *reg = swap[0] << 16 | swap[1] << 8 | swap[2];
+}
+
+/**
+ * Calculate mantissa and exponent for cbs / ebs reg.
+ */
+static inline void
+bnxt_ulp_flow_meter_xbs_calc(int64_t xbs, uint16_t *reg)
+{
+ uint16_t m = 0;
+ uint16_t e = 0;
+
+ if (xbs == 0) {
+ *reg = 0;
+ return;
+ }
+
+ /*
+ * e = floor(log2(xbs)) + 1
+ */
+ e = log2(xbs) + 1;
+
+ /*
+ * m = round(xbs/2^(e-1) - 1) * 128
+ * = round(xbs*2^(1-e) - 1) * 2^7
+ * = round(xbs*2^(8-e) - 2^7)
+ *
+ */
+ m = xbs / (1 << (e - 8)) - (1 << 7);
+ *reg = ((m & 0x7F) << 5) | (e & 0x1F);
+ *reg = rte_cpu_to_be_16(*reg);
+}
+
+/**
+ * Parse the meter profile.
+ */
+static inline int
+bnxt_ulp_meter_profile_parse(struct ulp_rte_act_prop *act_prop,
+ const struct rte_mtr_meter_profile *profile,
+ struct rte_mtr_error *error)
+{
+ uint64_t cir, cbs, eir, ebs;
+ uint32_t cir_reg, eir_reg;
+ uint16_t cbs_reg, ebs_reg;
+ bool alg_rfc2698 = false;
+ bool pm = false;
+
+ /* Profile must not be NULL. */
+ if (profile == NULL)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL, "Meter profile is null.");
+
+ if (profile->packet_mode)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "Metering packet_mode is not supported");
+
+ switch (profile->alg) {
+ case RTE_MTR_SRTCM_RFC2697:
+ cir = profile->srtcm_rfc2697.cir;
+ cbs = profile->srtcm_rfc2697.cbs;
+ eir = 0;
+ ebs = profile->srtcm_rfc2697.ebs;
+ break;
+ case RTE_MTR_TRTCM_RFC2698:
+ cir = profile->trtcm_rfc2698.cir;
+ cbs = profile->trtcm_rfc2698.cbs;
+ eir = profile->trtcm_rfc2698.pir;
+ ebs = profile->trtcm_rfc2698.pbs;
+ alg_rfc2698 = true;
+ break;
+ case RTE_MTR_TRTCM_RFC4115:
+ cir = profile->trtcm_rfc4115.cir;
+ cbs = profile->trtcm_rfc4115.cbs;
+ eir = profile->trtcm_rfc4115.eir;
+ ebs = profile->trtcm_rfc4115.ebs;
+ alg_rfc2698 = true;
+ break;
+ default:
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "Metering algorithm type is invalid");
+ }
+
+ /* The CBS and EBS must be configured so that at least one
+ * of them is larger than 0. It is recommended that when
+ * the value of the CBS or the EBS is larger than 0, it
+ * is larger than or equal to the size of the largest possible
+ * IP packet in the stream.
+ */
+ if (cbs == 0 && ebs == 0)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "CBS & EBS cannot both be 0. One of"
+ " them should be larger than the MTU");
+
+ if (alg_rfc2698 && eir < cir)
+ return -rte_mtr_error_set(error, EINVAL,
+ RTE_MTR_ERROR_TYPE_METER_PROFILE,
+ NULL,
+ "PIR must be equal to or greater than CIR");
+
+ bnxt_ulp_flow_meter_xir_calc(cir, &cir_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_CIR],
+ &cir_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CIR);
+
+ bnxt_ulp_flow_meter_xir_calc(eir, &eir_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_EIR],
+ &eir_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EIR);
+
+ bnxt_ulp_flow_meter_xbs_calc(cbs, &cbs_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_CBS],
+ &cbs_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_CBS);
+
+ bnxt_ulp_flow_meter_xbs_calc(ebs, &ebs_reg);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_EBS],
+ &ebs_reg,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_EBS);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_RFC2698],
+ &alg_rfc2698,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_RFC2698);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_PM],
+ &pm,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_PM);
+
+ return 0;
+}
+
+/**
+ * Add MTR profile.
+ */
+static int
+bnxt_flow_meter_profile_add(struct rte_eth_dev *dev,
+ uint32_t meter_profile_id,
+ struct rte_mtr_meter_profile *profile,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop = ¶ms.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+ params.act_bitmap.bits = BNXT_ULP_ACT_BIT_METER_PROFILE;
+ /* not direction from rte_mtr. Set ingress by default */
+ params.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_profile_id = tfp_cpu_to_be_32(meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ ret = bnxt_ulp_meter_profile_parse(act_prop, profile, error);
+ if (ret)
+ goto parse_error;
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto act_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto act_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto act_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto act_error;
+
+ return 0;
+parse_error:
+ return ret;
+act_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to add meter profile.");
+}
+
+/**
+ * Delete meter profile.
+ */
+static int
+bnxt_flow_meter_profile_delete(struct rte_eth_dev *dev,
+ uint32_t meter_profile_id,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params params;
+ struct ulp_rte_act_prop *act_prop = ¶ms.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(¶ms, 0, sizeof(struct ulp_rte_parser_params));
+ params.ulp_ctx = ulp_ctx;
+ params.act_bitmap.bits = BNXT_ULP_ACT_BIT_METER_PROFILE;
+ params.act_bitmap.bits |= BNXT_ULP_ACT_BIT_DELETE;
+ /* not direction from rte_mtr. Set ingress by default */
+ params.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_profile_id = tfp_cpu_to_be_32(meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ ret = ulp_matcher_action_match(¶ms, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, ¶ms,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(params.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter profile %d deleted\n",
+ meter_profile_id);
+
+ return 0;
+
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to delete meter profile.");
+}
+
+/**
+ * Create meter.
+ */
+static int
+bnxt_flow_meter_create(struct rte_eth_dev *dev, uint32_t meter_id,
+ struct rte_mtr_params *params, int shared __rte_unused,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ bool meter_en = params->meter_enable ? true : false;
+ int ret;
+ uint32_t tmp_meter_id, tmp_profile_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+
+ tmp_profile_id = tfp_cpu_to_be_32(params->meter_profile_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_PROF_ID],
+ &tmp_profile_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_PROF_ID);
+
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL],
+ &meter_en,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_MTR_VAL);
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is created\n", meter_id);
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to add meter.");
+}
+
+/**
+ * Destroy meter.
+ */
+static int
+bnxt_flow_meter_destroy(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_meter_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ pparams.act_bitmap.bits |= BNXT_ULP_ACT_BIT_DELETE;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is deleted\n", meter_id);
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to delete meter.");
+}
+
+/**
+ * Set meter valid/invalid.
+ */
+static int
+bnxt_flow_meter_enable_set(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ uint8_t val,
+ struct rte_mtr_error *error)
+{
+ struct bnxt_ulp_context *ulp_ctx;
+ struct ulp_rte_parser_params pparams;
+ struct ulp_rte_act_prop *act_prop = &pparams.act_prop;
+ struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+ uint32_t act_tid;
+ uint16_t func_id;
+ int ret;
+ uint32_t tmp_meter_id;
+
+ if (!bnxt_meter_initialized)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Bnxt meter is not initialized");
+
+ ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
+ if (!ulp_ctx)
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "ULP context is not initialized");
+
+ /* Initialize the parser params */
+ memset(&pparams, 0, sizeof(struct ulp_rte_parser_params));
+ pparams.ulp_ctx = ulp_ctx;
+ pparams.act_bitmap.bits = BNXT_ULP_ACT_BIT_SHARED_METER;
+ pparams.act_bitmap.bits |= BNXT_ULP_ACT_BIT_UPDATE;
+ /* not direction from rte_mtr. Set ingress by default */
+ pparams.dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
+
+ tmp_meter_id = tfp_cpu_to_be_32(meter_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_ID],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER_INST_ID);
+ act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL_UPDATE] = 1;
+ act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER_INST_MTR_VAL] = val;
+
+ ret = ulp_matcher_action_match(&pparams, &act_tid);
+ if (ret != BNXT_TF_RC_SUCCESS)
+ goto parse_error;
+
+ bnxt_ulp_init_mapper_params(&mparms, &pparams,
+ BNXT_ULP_FDB_TYPE_REGULAR);
+ mparms.act_tid = act_tid;
+
+ /* Get the function id */
+ if (ulp_port_db_port_func_id_get(ulp_ctx,
+ dev->data->port_id,
+ &func_id)) {
+ BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+ goto parse_error;
+ }
+
+ /* Protect flow creation */
+ if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+ BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+ goto parse_error;
+ }
+
+ ret = ulp_mapper_flow_create(pparams.ulp_ctx, &mparms);
+ bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+
+ if (ret)
+ goto parse_error;
+
+ BNXT_TF_DBG(DEBUG, "Bnxt flow meter %d is %s\n",
+ meter_id, val ? "enabled" : "disabled");
+
+ return 0;
+parse_error:
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Failed to enable/disable meter.");
+}
+
+/**
+ * Enable flow meter.
+ */
+static int
+bnxt_flow_meter_enable(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ return bnxt_flow_meter_enable_set(dev, meter_id, 1, error);
+}
+
+/**
+ * Disable flow meter.
+ */
+static int
+bnxt_flow_meter_disable(struct rte_eth_dev *dev,
+ uint32_t meter_id,
+ struct rte_mtr_error *error)
+{
+ return bnxt_flow_meter_enable_set(dev, meter_id, 0, error);
+}
+
+/**
+ * Update meter profile.
+ */
+static int
+bnxt_flow_meter_profile_update(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ uint32_t meter_profile_id __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_profile_update not supported");
+}
+
+/**
+ * Udate meter stats mask.
+ */
+static int
+bnxt_flow_meter_stats_update(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ uint64_t stats_mask __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_stats_update not supported");
+}
+
+/**
+ * Read meter statistics.
+ */
+static int
+bnxt_flow_meter_stats_read(struct rte_eth_dev *dev __rte_unused,
+ uint32_t meter_id __rte_unused,
+ struct rte_mtr_stats *stats __rte_unused,
+ uint64_t *stats_mask __rte_unused,
+ int clear __rte_unused,
+ struct rte_mtr_error *error)
+{
+ return -rte_mtr_error_set(error, ENOTSUP,
+ RTE_MTR_ERROR_TYPE_UNSPECIFIED,
+ NULL,
+ "Meter_stats_read not supported yet");
+}
+
+static const struct rte_mtr_ops bnxt_flow_mtr_ops = {
+ .capabilities_get = bnxt_flow_mtr_cap_get,
+ .meter_profile_add = bnxt_flow_meter_profile_add,
+ .meter_profile_delete = bnxt_flow_meter_profile_delete,
+ .meter_policy_validate = NULL,
+ .meter_policy_add = NULL,
+ .meter_policy_delete = NULL,
+ .create = bnxt_flow_meter_create,
+ .destroy = bnxt_flow_meter_destroy,
+ .meter_enable = bnxt_flow_meter_enable,
+ .meter_disable = bnxt_flow_meter_disable,
+ .meter_profile_update = bnxt_flow_meter_profile_update,
+ .meter_dscp_table_update = NULL,
+ .stats_update = bnxt_flow_meter_stats_update,
+ .stats_read = bnxt_flow_meter_stats_read,
+};
+
+/**
+ * Get meter operations.
+ */
+int
+bnxt_flow_meter_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg)
+{
+ *(const struct rte_mtr_ops **)arg = &bnxt_flow_mtr_ops;
+ return 0;
+}
diff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build
index c7df7e42f1..53a34b4413 100644
--- a/drivers/net/bnxt/tf_ulp/meson.build
+++ b/drivers/net/bnxt/tf_ulp/meson.build
@@ -11,6 +11,7 @@ sources += files(
'bnxt_tf_pmd_shim.c',
'bnxt_ulp.c',
'bnxt_ulp_flow.c',
+ 'bnxt_ulp_meter.c',
'ulp_def_rules.c',
'ulp_fc_mgr.c',
'ulp_flow_db.c',
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index 1fbfe18db3..af02f857d3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -66,8 +66,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
.proto_act_func = ulp_rte_port_act_handler
},
[RTE_FLOW_ACTION_TYPE_METER] = {
- .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
- .proto_act_func = NULL
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_meter_act_handler
},
[RTE_FLOW_ACTION_TYPE_SECURITY] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index d7450b92ff..d64c9e4968 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -2697,6 +2697,35 @@ ulp_rte_queue_act_handler(const struct rte_flow_action *action_item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow action meter. */
+int32_t
+ulp_rte_meter_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_action_meter *meter;
+ struct ulp_rte_act_prop *act_prop = ¶ms->act_prop;
+ uint32_t tmp_meter_id;
+
+ if (action_item == NULL || action_item->conf == NULL) {
+ BNXT_TF_DBG(ERR, "Parse Err: invalid meter configuration\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ meter = action_item->conf;
+ if (meter) {
+ /* validate the mtr_id and update the reference counter */
+ tmp_meter_id = tfp_cpu_to_be_32(meter->mtr_id);
+ memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_METER],
+ &tmp_meter_id,
+ BNXT_ULP_ACT_PROP_SZ_METER);
+ }
+
+ /* set the meter action header bit */
+ ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_METER);
+
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of RTE Flow action set mac src.*/
int32_t
ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 401ce4885d..74c7170a45 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -292,4 +292,9 @@ ulp_rte_set_mac_src_act_handler(const struct rte_flow_action *action_item,
int32_t
ulp_rte_set_mac_dst_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params);
+
+/* Function to handle the parsing of RTE Flow action meter. */
+int32_t
+ulp_rte_meter_act_handler(const struct rte_flow_action *action_item,
+ struct ulp_rte_parser_params *params);
#endif /* _ULP_RTE_PARSER_H_ */
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 08/11] net/bnxt: update PTP support on Thor
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (6 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 07/11] net/bnxt: add support for rte meter Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
` (2 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Somnath Kotur, Randy Schacher, Kalesh AP
[-- Attachment #1: Type: text/plain, Size: 10819 bytes --]
From: Somnath Kotur <somnath.kotur@broadcom.com>
add locking and time stamp checks to ptp feature
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 5 ++++
drivers/net/bnxt/bnxt_ethdev.c | 11 +++++++++
drivers/net/bnxt/bnxt_hwrm.c | 11 ++++++++-
drivers/net/bnxt/bnxt_ring.c | 3 +++
drivers/net/bnxt/bnxt_rxr.c | 8 ++++--
drivers/net/bnxt/bnxt_txq.c | 1 +
drivers/net/bnxt/bnxt_txr.c | 45 +++++++++++++++++++++++++++++++---
drivers/net/bnxt/bnxt_txr.h | 1 +
8 files changed, 79 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 7d508c7c23..dadd0bd95a 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -349,6 +349,7 @@ struct bnxt_ptp_cfg {
BNXT_PTP_MSG_PDELAY_RESP)
uint8_t tx_tstamp_en:1;
int rx_filter;
+ uint8_t filter_all;
#define BNXT_PTP_RX_TS_L 0
#define BNXT_PTP_RX_TS_H 1
@@ -372,6 +373,8 @@ struct bnxt_ptp_cfg {
/* On P5, the Rx timestamp is present in the Rx completion record */
uint64_t rx_timestamp;
uint64_t current_time;
+ uint64_t old_time;
+ rte_spinlock_t ptp_lock;
};
struct bnxt_coal {
@@ -722,6 +725,7 @@ struct bnxt {
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
+#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(10)
#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\
(bp)->app_id != 0xFF)
@@ -849,6 +853,7 @@ struct bnxt {
struct bnxt_led_info *leds;
uint8_t ieee_1588;
struct bnxt_ptp_cfg *ptp_cfg;
+ uint8_t ptp_all_rx_tstamp;
uint16_t vf_resv_strategy;
struct bnxt_ctx_mem_info *ctx;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 7bceb0524a..ea817e1fdd 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1441,8 +1441,11 @@ static void bnxt_ptp_get_current_time(void *arg)
if (!ptp)
return;
+ rte_spinlock_lock(&ptp->ptp_lock);
+ ptp->old_time = ptp->current_time;
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
if (rc != 0) {
PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
@@ -1458,8 +1461,11 @@ static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
return 0;
+ rte_spinlock_lock(&ptp->ptp_lock);
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ ptp->old_time = ptp->current_time;
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
@@ -3611,12 +3617,15 @@ bnxt_timesync_enable(struct rte_eth_dev *dev)
ptp->rx_filter = 1;
ptp->tx_tstamp_en = 1;
+ ptp->filter_all = 1;
ptp->rxctl = BNXT_PTP_MSG_EVENTS;
rc = bnxt_hwrm_ptp_cfg(bp);
if (rc)
return rc;
+ rte_spinlock_init(&ptp->ptp_lock);
+ bp->ptp_all_rx_tstamp = 1;
memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
@@ -3653,9 +3662,11 @@ bnxt_timesync_disable(struct rte_eth_dev *dev)
ptp->rx_filter = 0;
ptp->tx_tstamp_en = 0;
ptp->rxctl = 0;
+ ptp->filter_all = 0;
bnxt_hwrm_ptp_cfg(bp);
+ bp->ptp_all_rx_tstamp = 0;
if (!BNXT_CHIP_P5(bp))
bnxt_unmap_ptp_regs(bp);
else
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 77588bdf49..82679d1b32 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -669,6 +669,11 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
+ if (ptp->filter_all)
+ flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
+ else if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
+ flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
+
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
@@ -810,7 +815,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
struct hwrm_func_qcaps_input req = {.req_type = 0 };
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
uint16_t new_max_vfs;
- uint32_t flags;
+ uint32_t flags, flags_ext2;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
@@ -898,6 +903,10 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
bp->tunnel_disable_flag);
+ flags_ext2 = rte_le_to_cpu_32(resp->flags_ext2);
+ if (flags_ext2 & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
+ bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
+
unlock:
HWRM_UNLOCK();
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 686c3af4da..34b2510d54 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -227,6 +227,9 @@ int bnxt_alloc_rings(struct bnxt *bp, unsigned int socket_id, uint16_t qidx,
tx_ring->bd_dma = mz_phys_addr + tx_ring_start;
tx_ring_info->tx_desc_mapping = tx_ring->bd_dma;
tx_ring->mem_zone = (const void *)mz;
+ tx_ring_info->nr_bds = rte_zmalloc("bnxt_nr_bds",
+ sizeof(unsigned short) *
+ tx_ring->ring_size, 0);
if (!tx_ring->bd)
return -ENOMEM;
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 1ab0ef2f5d..0cabfb583c 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -697,7 +697,7 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
if (!BNXT_CHIP_P5(bp) || !ptp)
return;
- /* On Thor, Rx timestamps are provided directly in the
+ /* On P5, Rx timestamps are provided directly in the
* Rx completion records to the driver. Only 32 bits of
* the timestamp is present in the completion. Driver needs
* to read the current 48 bit free running timer using the
@@ -705,6 +705,9 @@ bnxt_get_rx_ts_p5(struct bnxt *bp, uint32_t rx_ts_cmpl)
* from the HWRM response with the lower 32 bits in the
* Rx completion to produce the 48 bit timestamp for the Rx packet
*/
+ rte_spinlock_lock(&ptp->ptp_lock);
+ last_hwrm_time = ptp->old_time;
+ rte_spinlock_unlock(&ptp->ptp_lock);
pkt_time = (last_hwrm_time & BNXT_PTP_CURRENT_TIME_MASK) | rx_ts_cmpl;
if (rx_ts_cmpl < (uint32_t)last_hwrm_time) {
/* timer has rolled over */
@@ -922,7 +925,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,
if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &
RX_PKT_CMPL_FLAGS_MASK) ==
- RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP))
+ RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP) ||
+ bp->ptp_all_rx_tstamp)
bnxt_get_rx_ts_p5(rxq->bp, rxcmp1->reorder);
if (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index d1d1fe8f1f..4df4604975 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -96,6 +96,7 @@ void bnxt_tx_queue_release_op(struct rte_eth_dev *dev, uint16_t queue_idx)
if (txq->tx_ring) {
bnxt_free_ring(txq->tx_ring->tx_ring_struct);
rte_free(txq->tx_ring->tx_ring_struct);
+ rte_free(txq->tx_ring->nr_bds);
rte_free(txq->tx_ring);
}
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 10b716a00b..6a11f5c8dc 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -143,6 +143,41 @@ bnxt_zero_data_len_tso_segsz(struct rte_mbuf *tx_pkt, uint8_t data_len_chk)
return false;
}
+static bool
+bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
+{
+ const struct rte_ether_hdr *eth_hdr;
+ struct rte_ether_hdr _eth_hdr;
+ uint16_t eth_type, proto;
+ uint32_t off = 0;
+
+ eth_hdr = rte_pktmbuf_read(m, off, sizeof(_eth_hdr), &_eth_hdr);
+ eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
+ off += sizeof(*eth_hdr);
+ /* Check for single tagged and double tagged VLANs */
+ if (eth_type == RTE_ETHER_TYPE_VLAN) {
+ const struct rte_vlan_hdr *vh;
+ struct rte_vlan_hdr vh_copy;
+
+ vh = rte_pktmbuf_read(m, off, sizeof(*vh), &vh_copy);
+ if (unlikely(vh == NULL))
+ return false;
+ off += sizeof(*vh);
+ proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_VLAN) {
+ const struct rte_vlan_hdr *vh;
+ struct rte_vlan_hdr vh_copy;
+
+ vh = rte_pktmbuf_read(m, off, sizeof(*vh), &vh_copy);
+ if (unlikely(vh == NULL))
+ return false;
+ off += sizeof(*vh);
+ proto = rte_be_to_cpu_16(vh->eth_proto);
+ }
+ }
+ return false;
+}
+
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
@@ -157,6 +192,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
bool long_bd = false;
unsigned short nr_bds;
uint16_t prod;
+ bool pkt_needs_ts = 0;
struct rte_mbuf *m_seg;
struct rte_mbuf **tx_buf;
static const uint32_t lhint_arr[4] = {
@@ -202,9 +238,13 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
if (unlikely(bnxt_zero_data_len_tso_segsz(tx_pkt, 1)))
return -EIO;
+ if (unlikely(txq->bp->ptp_cfg != NULL && txq->bp->ptp_all_rx_tstamp == 1))
+ pkt_needs_ts = bnxt_check_pkt_needs_ts(tx_pkt);
+
prod = RING_IDX(ring, txr->tx_raw_prod);
tx_buf = &txr->tx_buf_ring[prod];
*tx_buf = tx_pkt;
+ txr->nr_bds[prod] = nr_bds;
txbd = &txr->tx_desc_ring[prod];
txbd->opaque = *coal_pkts;
@@ -341,7 +381,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
/* IP CSO */
txbd1->lflags |= TX_BD_LONG_LFLAGS_T_IP_CHKSUM;
} else if ((tx_pkt->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) ==
- RTE_MBUF_F_TX_IEEE1588_TMST) {
+ RTE_MBUF_F_TX_IEEE1588_TMST || pkt_needs_ts) {
/* PTP */
txbd1->lflags |= TX_BD_LONG_LFLAGS_STAMP;
}
@@ -427,8 +467,7 @@ static void bnxt_tx_cmp(struct bnxt_tx_queue *txq, int nr_pkts)
unsigned short nr_bds;
tx_buf = &txr->tx_buf_ring[RING_IDX(ring, raw_cons)];
- nr_bds = (*tx_buf)->nb_segs +
- bnxt_xmit_need_long_bd(*tx_buf, txq);
+ nr_bds = txr->nr_bds[RING_IDX(ring, raw_cons)];
for (j = 0; j < nr_bds; j++) {
mbuf = *tx_buf;
*tx_buf = NULL;
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index b9b8a9b1a2..8e391ee58a 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -24,6 +24,7 @@ struct bnxt_tx_ring_info {
rte_iova_t tx_desc_mapping;
+ unsigned short *nr_bds;
struct bnxt_ring *tx_ring_struct;
};
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 09/11] net/bnxt: fix multi-root card support
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (7 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Kishore Padmanabha, stable, Shahaji Bhosle
[-- Attachment #1: Type: text/plain, Size: 4012 bytes --]
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Changed the logic to use device serial number to identify that
different ports belong to same physical card instead of the PCI
domain address.
Fixes: 34a7ff5a920e ("net/bnxt: support multi root capability")
Cc: stable@dpdk.org
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 3 +++
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 ++++++++---
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 ++
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index dadd0bd95a..08791b8a17 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -138,6 +138,7 @@
#define BNXT_NUM_CMPL_DMA_AGGR 36
#define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
#define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
+#define BNXT_DEVICE_SERIAL_NUM_SIZE 8
#define BNXT_DEFAULT_VNIC_STATE_MASK \
HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
@@ -863,6 +864,8 @@ struct bnxt {
uint16_t num_reps;
struct bnxt_rep_info *rep_info;
uint16_t *cfa_code_map;
+ /* Device Serial Number */
+ uint8_t dsn[BNXT_DEVICE_SERIAL_NUM_SIZE];
/* Struct to hold adapter error recovery related info */
struct bnxt_error_recovery_info *recovery_info;
#define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 82679d1b32..edad84c262 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -863,6 +863,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
+ memcpy(bp->dsn, resp->device_serial_number, sizeof(bp->dsn));
if (BNXT_PF(bp))
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 3459140f18..500c177039 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1318,9 +1318,13 @@ ulp_get_session(struct bnxt *bp, struct rte_pci_addr *pci_addr)
/* if multi root capability is enabled, then ignore the pci bus id */
STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) {
- if (session->pci_info.domain == pci_addr->domain &&
- (BNXT_MULTIROOT_EN(bp) ||
- session->pci_info.bus == pci_addr->bus)) {
+ if (BNXT_MULTIROOT_EN(bp)) {
+ if (!memcmp(bp->dsn, session->dsn,
+ sizeof(session->dsn))) {
+ return session;
+ }
+ } else if (session->pci_info.domain == pci_addr->domain &&
+ session->pci_info.bus == pci_addr->bus) {
return session;
}
}
@@ -1364,6 +1368,7 @@ ulp_session_init(struct bnxt *bp,
/* Add it to the queue */
session->pci_info.domain = pci_addr->domain;
session->pci_info.bus = pci_addr->bus;
+ memcpy(session->dsn, bp->dsn, sizeof(session->dsn));
rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
if (rc) {
BNXT_TF_DBG(ERR, "mutex create failed\n");
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index a6ad5c1eaa..92db7751fe 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -131,11 +131,13 @@ struct bnxt_ulp_pci_info {
uint8_t bus;
};
+#define BNXT_ULP_DEVICE_SERIAL_NUM_SIZE 8
struct bnxt_ulp_session_state {
STAILQ_ENTRY(bnxt_ulp_session_state) next;
bool bnxt_ulp_init;
pthread_mutex_t bnxt_ulp_mutex;
struct bnxt_ulp_pci_info pci_info;
+ uint8_t dsn[BNXT_ULP_DEVICE_SERIAL_NUM_SIZE];
struct bnxt_ulp_data *cfg_data;
struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
uint32_t session_opened[BNXT_ULP_SESSION_MAX];
--
2.39.2 (Apple Git-143)
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4218 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 10/11] net/bnxt: add support for eCPRI packet parsing
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (8 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Randy Schacher, Shahaji Bhosle, Manish Kurup
[-- Attachment #1: Type: text/plain, Size: 21024 bytes --]
From: Randy Schacher <stuart.schacher@broadcom.com>
Add eCPRI parsing and offload support in the TruFlow ULP layer.
Signed-off-by: Randy Schacher <stuart.schacher@broadcom.com>
Signed-off-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Manish Kurup <manish.kurup@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
.mailmap | 1 +
doc/guides/nics/features/bnxt.ini | 1 +
drivers/net/bnxt/bnxt.h | 4 +
drivers/net/bnxt/bnxt_ethdev.c | 35 +++++
drivers/net/bnxt/bnxt_hwrm.c | 17 +++
drivers/net/bnxt/bnxt_txr.c | 10 +-
drivers/net/bnxt/bnxt_vnic.c | 5 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c | 7 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 24 ++++
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 18 +++
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 120 +++++++++++++++++-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +
16 files changed, 256 insertions(+), 7 deletions(-)
diff --git a/.mailmap b/.mailmap
index 0062d08f41..6c600baa62 100644
--- a/.mailmap
+++ b/.mailmap
@@ -830,6 +830,7 @@ Malvika Gupta <malvika.gupta@arm.com>
Mandal Purna Chandra <purna.chandra.mandal@intel.com>
Mandeep Rohilla <mrohilla@brocade.com>
Manish Chopra <manishc@marvell.com>
+Manish Kurup <manish.kurup@broadcom.com>
Manish Tomar <manish.tomar@nxp.com>
Mao Jiang <maox.jiang@intel.com>
Mao YingMing <maoyingming@baidu.com>
diff --git a/doc/guides/nics/features/bnxt.ini b/doc/guides/nics/features/bnxt.ini
index 8b523e3bef..bd4e2295dc 100644
--- a/doc/guides/nics/features/bnxt.ini
+++ b/doc/guides/nics/features/bnxt.ini
@@ -57,6 +57,7 @@ Perf doc = Y
[rte_flow items]
any = Y
+ecpri = Y
eth = P
ipv4 = Y
ipv6 = Y
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 08791b8a17..ed21ba7f29 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -844,10 +844,14 @@ struct bnxt {
uint8_t port_cnt;
uint8_t vxlan_port_cnt;
uint8_t geneve_port_cnt;
+ uint8_t ecpri_port_cnt;
uint16_t vxlan_port;
uint16_t geneve_port;
+ uint16_t ecpri_port;
uint16_t vxlan_fw_dst_port_id;
uint16_t geneve_fw_dst_port_id;
+ uint16_t ecpri_fw_dst_port_id;
+ uint16_t ecpri_upar_in_use;
uint32_t fw_ver;
uint32_t hwrm_spec_code;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index ea817e1fdd..ee1552452a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -2405,6 +2405,20 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
tunnel_type =
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
+ udp_tunnel->udp_port);
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Only one port allowed\n");
+ return -ENOSPC;
+ }
+ bp->ecpri_port_cnt++;
+ return 0;
+ }
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
@@ -2423,6 +2437,10 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
bp->geneve_port_cnt++;
+ if (tunnel_type ==
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI)
+ bp->ecpri_port_cnt++;
+
return rc;
}
@@ -2474,6 +2492,23 @@ bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
port = bp->geneve_fw_dst_port_id;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (!bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
+ return -EINVAL;
+ }
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
+ udp_tunnel->udp_port, bp->ecpri_port);
+ return -EINVAL;
+ }
+ if (--bp->ecpri_port_cnt)
+ return 0;
+
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI;
+ port = bp->ecpri_fw_dst_port_id;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index edad84c262..b944547656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -2969,6 +2969,10 @@ bnxt_free_tunnel_ports(struct bnxt *bp)
if (bp->geneve_port_cnt)
bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
+
+ if (bp->ecpri_port_cnt)
+ bnxt_hwrm_tunnel_dst_port_free(bp, bp->ecpri_fw_dst_port_id,
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI);
}
void bnxt_free_all_hwrm_resources(struct bnxt *bp)
@@ -4075,6 +4079,12 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
rte_le_to_cpu_16(resp->tunnel_dst_port_id);
bp->geneve_port = port;
break;
+ case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI:
+ bp->ecpri_fw_dst_port_id =
+ rte_le_to_cpu_16(resp->tunnel_dst_port_id);
+ bp->ecpri_port = port;
+ bp->ecpri_upar_in_use = resp->upar_in_use;
+ break;
default:
break;
}
@@ -4142,6 +4152,13 @@ int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
bp->geneve_port_cnt = 0;
}
+ if (tunnel_type ==
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI) {
+ bp->ecpri_port = 0;
+ bp->ecpri_upar_in_use = 0;
+ bp->ecpri_port_cnt = 0;
+ }
+
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 6a11f5c8dc..899986764f 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -150,10 +150,14 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
struct rte_ether_hdr _eth_hdr;
uint16_t eth_type, proto;
uint32_t off = 0;
-
+ /*
+ * Check that the received packet is a eCPRI packet
+ */
eth_hdr = rte_pktmbuf_read(m, off, sizeof(_eth_hdr), &_eth_hdr);
eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
off += sizeof(*eth_hdr);
+ if (eth_type == RTE_ETHER_TYPE_ECPRI)
+ return true;
/* Check for single tagged and double tagged VLANs */
if (eth_type == RTE_ETHER_TYPE_VLAN) {
const struct rte_vlan_hdr *vh;
@@ -164,6 +168,8 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
return false;
off += sizeof(*vh);
proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_ECPRI)
+ return true;
if (proto == RTE_ETHER_TYPE_VLAN) {
const struct rte_vlan_hdr *vh;
struct rte_vlan_hdr vh_copy;
@@ -173,6 +179,8 @@ bnxt_check_pkt_needs_ts(struct rte_mbuf *m)
return false;
off += sizeof(*vh);
proto = rte_be_to_cpu_16(vh->eth_proto);
+ if (proto == RTE_ETHER_TYPE_ECPRI)
+ return true;
}
}
return false;
diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c
index be9c127b64..2be456956d 100644
--- a/drivers/net/bnxt/bnxt_vnic.c
+++ b/drivers/net/bnxt/bnxt_vnic.c
@@ -258,7 +258,8 @@ uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)
{
uint16_t hwrm_type = 0;
- if (rte_type & RTE_ETH_RSS_IPV4)
+ if ((rte_type & RTE_ETH_RSS_IPV4) ||
+ (rte_type & RTE_ETH_RSS_ECPRI))
hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
if (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
hwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
@@ -277,7 +278,7 @@ uint16_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)
int bnxt_rte_to_hwrm_hash_level(struct bnxt *bp, uint64_t hash_f, uint32_t lvl)
{
uint32_t mode = HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT;
- bool l3 = (hash_f & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6));
+ bool l3 = (hash_f & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_ECPRI));
bool l4 = (hash_f & (RTE_ETH_RSS_NONFRAG_IPV4_UDP |
RTE_ETH_RSS_NONFRAG_IPV6_UDP |
RTE_ETH_RSS_NONFRAG_IPV4_TCP |
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
index 474854d59b..239191e14e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c
@@ -543,12 +543,15 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
case BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN:
hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
break;
+ case BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI:
+ hwtype = HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI;
+ break;
default:
BNXT_TF_DBG(ERR, "Tunnel Type (%d) invalid\n", type);
return -EINVAL;
}
- if (!udp_port) {
+ if (!udp_port && type != BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI) {
/* Free based on the handle */
if (!handle) {
BNXT_TF_DBG(ERR, "Free with invalid handle\n");
@@ -589,7 +592,7 @@ bnxt_pmd_global_tunnel_set(uint16_t port_id, uint8_t type,
if (!rc) {
ulp_global_tunnel_db[type].ref_cnt++;
ulp_global_tunnel_db[type].dport = udp_port;
- bnxt_pmd_global_reg_data_to_hndl(port_id, 0,
+ bnxt_pmd_global_reg_data_to_hndl(port_id, bp->ecpri_upar_in_use,
type, handle);
}
}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
index b76e4b849d..18feab6cac 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h
@@ -19,6 +19,7 @@ struct bnxt_global_tunnel_info {
enum bnxt_global_register_tunnel_type {
BNXT_GLOBAL_REGISTER_TUNNEL_UNUSED = 0,
BNXT_GLOBAL_REGISTER_TUNNEL_VXLAN,
+ BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI,
BNXT_GLOBAL_REGISTER_TUNNEL_MAX
};
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 500c177039..b696b6dc3e 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -456,6 +456,7 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
bnxt_ulp_vxlan_ip_port_set(ulp_ctx, info[i].vxlan_ip_port);
bnxt_ulp_vxlan_port_set(ulp_ctx, info[i].vxlan_port);
+ bnxt_ulp_ecpri_udp_port_set(ulp_ctx, info[i].ecpri_udp_port);
/* set the shared session support from firmware */
fw = info[i].upgrade_fw_update;
@@ -479,6 +480,29 @@ bnxt_ulp_cntxt_app_caps_init(struct bnxt *bp,
return 0;
}
+/* Function to retrieve the vxlan_ip (ecpri) port from the context. */
+int
+bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t ecpri_udp_port)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return -EINVAL;
+
+ ulp_ctx->cfg_data->ecpri_udp_port = ecpri_udp_port;
+
+ return 0;
+}
+
+/* Function to retrieve the vxlan_ip (ecpri) port from the context. */
+unsigned int
+bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx)
+{
+ if (!ulp_ctx || !ulp_ctx->cfg_data)
+ return 0;
+
+ return (unsigned int)ulp_ctx->cfg_data->ecpri_udp_port;
+}
+
/* Function to set the number for vxlan_ip (custom vxlan) port into the context */
int
bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 92db7751fe..258801f633 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -113,6 +113,7 @@ struct bnxt_ulp_data {
struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
uint32_t vxlan_port;
uint32_t vxlan_ip_port;
+ uint32_t ecpri_udp_port;
uint8_t hu_reg_state;
uint8_t hu_reg_cnt;
uint32_t hu_session_type;
@@ -367,12 +368,19 @@ bnxt_ulp_vxlan_port_set(struct bnxt_ulp_context *ulp_ctx,
uint32_t vxlan_port);
unsigned int
bnxt_ulp_vxlan_port_get(struct bnxt_ulp_context *ulp_ctx);
+
int
bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
uint32_t vxlan_ip_port);
unsigned int
bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+int
+bnxt_ulp_ecpri_udp_port_set(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t ecpri_udp_port);
+unsigned int
+bnxt_ulp_ecpri_udp_port_get(struct bnxt_ulp_context *ulp_ctx);
+
int32_t
bnxt_flow_meter_init(struct bnxt *bp);
@@ -391,5 +399,4 @@ bnxt_ulp_ha_reg_cnt_get(struct bnxt_ulp_context *ulp_ctx);
struct tf*
bnxt_ulp_bp_tfp_get(struct bnxt *bp, enum bnxt_ulp_session_type type);
-
#endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index e5f1d266d7..6d345e12c7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -3298,6 +3298,11 @@ ulp_mapper_global_res_free(struct bnxt_ulp_context *ulp __rte_unused,
rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
&handle);
break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI:
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI;
+ rc = bnxt_pmd_global_tunnel_set(port_id, ttype, dport,
+ &handle);
+ break;
default:
rc = -EINVAL;
BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
@@ -3362,6 +3367,19 @@ ulp_mapper_global_register_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
break;
+ case BNXT_ULP_RESOURCE_SUB_TYPE_GLOBAL_REGISTER_CUST_ECPRI:
+ tmp_data = ulp_blob_data_get(&data, &data_len);
+ udp_port = *((uint16_t *)tmp_data);
+ udp_port = tfp_be_to_cpu_16(udp_port);
+ ttype = BNXT_GLOBAL_REGISTER_TUNNEL_ECPRI;
+
+ rc = bnxt_pmd_global_tunnel_set(parms->port_id, ttype,
+ udp_port, &handle);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Unable to set eCPRI UDP port\n");
+ return rc;
+ }
+ break;
default:
rc = -EINVAL;
BNXT_TF_DBG(ERR, "Invalid ulp global resource type %d\n",
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
index af02f857d3..51b2e98103 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
@@ -408,6 +408,10 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
},
+ [RTE_FLOW_ITEM_TYPE_ECPRI] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ecpri_hdr_handler
+ },
[RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_port_hdr_handler
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index d64c9e4968..0937d0dbe4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -143,7 +143,7 @@ bnxt_ulp_rte_parser_hdr_parse(const struct rte_flow_item pattern[],
hdr_info = &ulp_vendor_hdr_info[item->type -
BNXT_RTE_FLOW_ITEM_TYPE_END];
} else {
- if (item->type > RTE_FLOW_ITEM_TYPE_HIGIG2)
+ if (item->type > RTE_FLOW_ITEM_TYPE_ECPRI)
goto hdr_parser_error;
hdr_info = &ulp_hdr_info[item->type];
}
@@ -612,6 +612,10 @@ ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param,
} else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
has_vlan_mask = 1;
has_vlan = 1;
+ } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_ECPRI)) {
+ /* Update the hdr_bitmap with eCPRI */
+ ULP_BITMAP_SET(param->hdr_fp_bit.bits,
+ BNXT_ULP_HDR_BIT_O_ECPRI);
} else if (type == tfp_cpu_to_be_16(ULP_RTE_ETHER_TYPE_ROE)) {
/* Update the hdr_bitmap with RoE */
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
@@ -1660,6 +1664,120 @@ ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item,
return BNXT_TF_RC_SUCCESS;
}
+/* Function to handle the parsing of RTE Flow item ECPRI Header. */
+int32_t
+ulp_rte_ecpri_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params)
+{
+ const struct rte_flow_item_ecpri *ecpri_spec = item->spec;
+ const struct rte_flow_item_ecpri *ecpri_mask = item->mask;
+ struct rte_flow_item_ecpri l_ecpri_spec, l_ecpri_mask;
+ struct rte_flow_item_ecpri *p_ecpri_spec = &l_ecpri_spec;
+ struct rte_flow_item_ecpri *p_ecpri_mask = &l_ecpri_mask;
+ struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap;
+ uint32_t idx = 0, cnt;
+ uint32_t size;
+
+ if (ulp_rte_prsr_fld_size_validate(params, &idx,
+ BNXT_ULP_PROTO_HDR_ECPRI_NUM)) {
+ BNXT_TF_DBG(ERR, "Error parsing protocol header\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ /* Figure out if eCPRI is within L4(UDP), unsupported, for now */
+ cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
+ if (cnt >= 1) {
+ BNXT_TF_DBG(ERR, "Parse Err: L4 header stack >= 2 not supported\n");
+ return BNXT_TF_RC_ERROR;
+ }
+
+ if (!ecpri_spec || !ecpri_mask)
+ goto parser_set_ecpri_hdr_bit;
+
+ memcpy(p_ecpri_spec, ecpri_spec, sizeof(*ecpri_spec));
+ memcpy(p_ecpri_mask, ecpri_mask, sizeof(*ecpri_mask));
+
+ p_ecpri_spec->hdr.common.u32 = rte_be_to_cpu_32(p_ecpri_spec->hdr.common.u32);
+ p_ecpri_mask->hdr.common.u32 = rte_be_to_cpu_32(p_ecpri_mask->hdr.common.u32);
+
+ /*
+ * Init eCPRI spec+mask to correct defaults, also clear masks of fields
+ * we ignore in the TCAM.
+ */
+
+ l_ecpri_spec.hdr.common.size = 0;
+ l_ecpri_spec.hdr.common.c = 0;
+ l_ecpri_spec.hdr.common.res = 0;
+ l_ecpri_spec.hdr.common.revision = 1;
+ l_ecpri_mask.hdr.common.size = 0;
+ l_ecpri_mask.hdr.common.c = 1;
+ l_ecpri_mask.hdr.common.res = 0;
+ l_ecpri_mask.hdr.common.revision = 0xf;
+
+ switch (p_ecpri_spec->hdr.common.type) {
+ case RTE_ECPRI_MSG_TYPE_IQ_DATA:
+ l_ecpri_mask.hdr.type0.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_BIT_SEQ:
+ l_ecpri_mask.hdr.type1.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
+ l_ecpri_mask.hdr.type2.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_GEN_DATA:
+ l_ecpri_mask.hdr.type3.seq_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RM_ACC:
+ l_ecpri_mask.hdr.type4.rr = 0;
+ l_ecpri_mask.hdr.type4.rw = 0;
+ l_ecpri_mask.hdr.type4.rma_id = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_DLY_MSR:
+ l_ecpri_spec.hdr.type5.act_type = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_RMT_RST:
+ l_ecpri_spec.hdr.type6.rst_op = 0;
+ break;
+
+ case RTE_ECPRI_MSG_TYPE_EVT_IND:
+ l_ecpri_spec.hdr.type7.evt_type = 0;
+ l_ecpri_spec.hdr.type7.seq = 0;
+ l_ecpri_spec.hdr.type7.number = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ p_ecpri_spec->hdr.common.u32 = rte_cpu_to_be_32(p_ecpri_spec->hdr.common.u32);
+ p_ecpri_mask->hdr.common.u32 = rte_cpu_to_be_32(p_ecpri_mask->hdr.common.u32);
+
+ /* Type */
+ size = sizeof(((struct rte_flow_item_ecpri *)NULL)->hdr.common.u32);
+ ulp_rte_prsr_fld_mask(params, &idx, size,
+ ulp_deference_struct(p_ecpri_spec, hdr.common.u32),
+ ulp_deference_struct(p_ecpri_mask, hdr.common.u32),
+ ULP_PRSR_ACT_DEFAULT);
+
+ /* PC/RTC/MSR_ID */
+ size = sizeof(((struct rte_flow_item_ecpri *)NULL)->hdr.dummy[0]);
+ ulp_rte_prsr_fld_mask(params, &idx, size,
+ ulp_deference_struct(p_ecpri_spec, hdr.dummy),
+ ulp_deference_struct(p_ecpri_mask, hdr.dummy),
+ ULP_PRSR_ACT_DEFAULT);
+
+parser_set_ecpri_hdr_bit:
+ /* Update the hdr_bitmap with eCPRI */
+ ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ECPRI);
+ return BNXT_TF_RC_SUCCESS;
+}
+
/* Function to handle the parsing of RTE Flow item void Header */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 74c7170a45..9dd7ebcb76 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -149,6 +149,11 @@ int32_t
ulp_rte_icmp6_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
+/* Function to handle the parsing of RTE Flow item ECPRI Header. */
+int32_t
+ulp_rte_ecpri_hdr_handler(const struct rte_flow_item *item,
+ struct ulp_rte_parser_params *params);
+
/* Function to handle the parsing of RTE Flow item void Header. */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index fb6fb3553b..9e11b3e305 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -29,6 +29,7 @@
#define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4
#define BNXT_ULP_PROTO_HDR_GRE_NUM 2
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
+#define BNXT_ULP_PROTO_HDR_ECPRI_NUM 2
#define BNXT_ULP_PROTO_HDR_MAX 128
#define BNXT_ULP_PROTO_HDR_ENCAP_MAX 64
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
@@ -364,6 +365,7 @@ struct bnxt_ulp_app_capabilities_info {
uint8_t app_id;
uint32_t vxlan_port;
uint32_t vxlan_ip_port;
+ uint32_t ecpri_udp_port;
enum bnxt_ulp_device_id device_id;
uint32_t upgrade_fw_update;
uint8_t ha_pool_id;
--
2.39.2 (Apple Git-143)
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v4 11/11] net/bnxt: set RSS config based on RSS mode
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
` (9 preceding siblings ...)
2023-06-28 16:29 ` [PATCH v4 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
@ 2023-06-28 16:29 ` Ajit Khaparde
10 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:29 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, thomas, Shuanglin Wang, Kishore Padmanabha, Mike Baucom
[-- Attachment #1: Type: text/plain, Size: 1200 bytes --]
From: Shuanglin Wang <shuanglin.wang@broadcom.com>
Avoid submitting hwrm RSS request when rss mode disabled.
On WH+, if rss mode isn't enabled, then there is no rss context.
Submitting HWRM_VNIC_RSS_CFG request to firmware would hit a failure.
The fix is to check the rss context. If no rss context, then don't
submit the hwrm request.
Signed-off-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index b944547656..06f196760f 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -2405,6 +2405,9 @@ bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
int rc = 0;
+ if (vnic->num_lb_ctxts == 0)
+ return rc;
+
HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
--
2.39.2 (Apple Git-143)
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/11] net/bnxt: update Truflow core
2023-06-10 18:32 ` Thomas Monjalon
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
@ 2023-06-28 16:35 ` Ajit Khaparde
2023-06-28 19:07 ` Thomas Monjalon
1 sibling, 1 reply; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-28 16:35 UTC (permalink / raw)
To: Thomas Monjalon
Cc: Randy Schacher, Farah Smith, Shahaji Bhosle, dev, david.marchand
[-- Attachment #1: Type: text/plain, Size: 2054 bytes --]
On Sat, Jun 10, 2023 at 11:33 AM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 04/05/2023 19:36, Ajit Khaparde:
> > From: Randy Schacher <stuart.schacher@broadcom.com>
> >
> > Update TruFlow core code to:
> > - Add shared session management
> > - Add SRAM session management
> > - Add dynamic TCAM management
> > - Add shared TCAM session management
> > - Add Hot Upgrade support
> > - Update copyright year
>
> I suppose you can update the date in the previous patch
> for the whole driver.
To some extent the idea was to update the date in the patch when the
code change was happening, instead of a blanket date change.
>
> Also this patch is removing some blank lines out of Truflow.
> And I don't understand the need for removing the blank lines
> before the last #ifdef of the file.
The template files are auto generated using a bunch of scripts.
What we are seeing is probably because of that.
But we have cleaned up many of those in the v4 submission.
>
> More important, you are doing huge update of many different things
> in one patch.
> It looks like you don't want the community to follow what you are doing.
Actually, no.
As I mentioned above, most of the truflow files are auto generated.
The reason for bundling some of the changes together was to avoid
multiple patches hitting the mail server patch size limit.
We thought it might be better to take the patch size hit on one patch
instead of multiple patches.
We are working on some design changes to the auto generation scripts
which will avoid big churn in the template patches in the future.
>
> For info, there are other things to fix in this patchset:
> Error: Incorrect indent at drivers/net/bnxt/tf_ulp/generic_templates/meson.build
> rte_flow doc out of sync for bnxt
> action set_mac_dst
> action set_mac_src
> You can run the following script to catch these issues:
> devtools/check-meson.py
> devtools/check-doc-vs-code.sh
We have addressed these in the v4 version.
Thanks
>
>
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/11] net/bnxt: update Truflow core
2023-06-28 16:35 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
@ 2023-06-28 19:07 ` Thomas Monjalon
2023-06-29 4:30 ` Ajit Khaparde
0 siblings, 1 reply; 30+ messages in thread
From: Thomas Monjalon @ 2023-06-28 19:07 UTC (permalink / raw)
To: Ajit Khaparde
Cc: Randy Schacher, Farah Smith, Shahaji Bhosle, dev, david.marchand
28/06/2023 18:35, Ajit Khaparde:
> On Sat, Jun 10, 2023 at 11:33 AM Thomas Monjalon <thomas@monjalon.net> wrote:
> > More important, you are doing huge update of many different things
> > in one patch.
> > It looks like you don't want the community to follow what you are doing.
> Actually, no.
> As I mentioned above, most of the truflow files are auto generated.
> The reason for bundling some of the changes together was to avoid
> multiple patches hitting the mail server patch size limit.
> We thought it might be better to take the patch size hit on one patch
> instead of multiple patches.
I don't see how it is better to have one huge patch
than multiple big ones.
>
> We are working on some design changes to the auto generation scripts
> which will avoid big churn in the template patches in the future.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/11] net/bnxt: update Truflow core
2023-06-28 19:07 ` Thomas Monjalon
@ 2023-06-29 4:30 ` Ajit Khaparde
2023-06-30 12:16 ` Ajit Khaparde
0 siblings, 1 reply; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-29 4:30 UTC (permalink / raw)
To: Thomas Monjalon
Cc: Randy Schacher, Farah Smith, Shahaji Bhosle, dev, david.marchand
[-- Attachment #1: Type: text/plain, Size: 1450 bytes --]
On Wed, Jun 28, 2023 at 12:07 PM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 28/06/2023 18:35, Ajit Khaparde:
> > On Sat, Jun 10, 2023 at 11:33 AM Thomas Monjalon <thomas@monjalon.net> wrote:
> > > More important, you are doing huge update of many different things
> > > in one patch.
> > > It looks like you don't want the community to follow what you are doing.
> > Actually, no.
> > As I mentioned above, most of the truflow files are auto generated.
> > The reason for bundling some of the changes together was to avoid
> > multiple patches hitting the mail server patch size limit.
> > We thought it might be better to take the patch size hit on one patch
> > instead of multiple patches.
>
> I don't see how it is better to have one huge patch
> than multiple big ones.
Well, its debatable now, considering we are having this discussion.
But as I said, the current design of the truflow generator scripts tend to make
a lot of changes even for a small modification or adjustment to the code.
We had patches which were moving around the same lines of code because
of the script. That's why we decided to take this approach.
We could try to split the patch with the template changes, but that may take
time and we are closing in on rc3 date.
>
> >
> > We are working on some design changes to the auto generation scripts
> > which will avoid big churn in the template patches in the future.
>
>
>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/11] net/bnxt: update Truflow core
2023-06-29 4:30 ` Ajit Khaparde
@ 2023-06-30 12:16 ` Ajit Khaparde
0 siblings, 0 replies; 30+ messages in thread
From: Ajit Khaparde @ 2023-06-30 12:16 UTC (permalink / raw)
To: Thomas Monjalon
Cc: Randy Schacher, Farah Smith, Shahaji Bhosle, dev, david.marchand
[-- Attachment #1: Type: text/plain, Size: 1657 bytes --]
On Wed, Jun 28, 2023 at 9:30 PM Ajit Khaparde
<ajit.khaparde@broadcom.com> wrote:
>
> On Wed, Jun 28, 2023 at 12:07 PM Thomas Monjalon <thomas@monjalon.net> wrote:
> >
> > 28/06/2023 18:35, Ajit Khaparde:
> > > On Sat, Jun 10, 2023 at 11:33 AM Thomas Monjalon <thomas@monjalon.net> wrote:
> > > > More important, you are doing huge update of many different things
> > > > in one patch.
> > > > It looks like you don't want the community to follow what you are doing.
> > > Actually, no.
> > > As I mentioned above, most of the truflow files are auto generated.
> > > The reason for bundling some of the changes together was to avoid
> > > multiple patches hitting the mail server patch size limit.
> > > We thought it might be better to take the patch size hit on one patch
> > > instead of multiple patches.
> >
> > I don't see how it is better to have one huge patch
> > than multiple big ones.
> Well, its debatable now, considering we are having this discussion.
> But as I said, the current design of the truflow generator scripts tend to make
> a lot of changes even for a small modification or adjustment to the code.
> We had patches which were moving around the same lines of code because
> of the script. That's why we decided to take this approach.
> We could try to split the patch with the template changes, but that may take
> time and we are closing in on rc3 date.
Patches applied to dpdk-next-net-brcm. Thanks
>
>
>
>
>
> >
> > >
> > > We are working on some design changes to the auto generation scripts
> > > which will avoid big churn in the template patches in the future.
> >
> >
> >
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^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2023-06-30 12:17 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
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2023-05-04 17:36 [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 01/11] net/bnxt: remove deprecated features Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
2023-06-10 18:32 ` Thomas Monjalon
2023-06-28 16:29 ` [PATCH v4 00/11] sync Truflow support with latest release Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 01/11] net/bnxt: remove deprecated features Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 02/11] net/bnxt: update bnxt hsi structure Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 03/11] net/bnxt: update copyright date and cleanup whitespace Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 04/11] net/bnxt: update Truflow core Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 07/11] net/bnxt: add support for rte meter Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
2023-06-28 16:29 ` [PATCH v4 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
2023-06-28 16:35 ` [PATCH v3 04/11] net/bnxt: update Truflow core Ajit Khaparde
2023-06-28 19:07 ` Thomas Monjalon
2023-06-29 4:30 ` Ajit Khaparde
2023-06-30 12:16 ` Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 05/11] net/bnxt: update ULP shared session support Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 06/11] net/bnxt: add RSS and Queue action in TruFLow Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 07/11] net/bnxt: add support for rte meter Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 08/11] net/bnxt: update PTP support on Thor Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 09/11] net/bnxt: fix multi-root card support Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 10/11] net/bnxt: add support for eCPRI packet parsing Ajit Khaparde
2023-05-04 17:36 ` [PATCH v3 11/11] net/bnxt: set RSS config based on RSS mode Ajit Khaparde
2023-05-10 17:16 ` [PATCH v3 00/11] sync Truflow support with latest release Ajit Khaparde
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