[PATCH 0/2] net/mlx5: add random item support

[PATCH 0/2] net/mlx5: add random item support

[Michael Baum]

Add support for matching random value using the "rte_flow_item_random"
structure.

Depends-on: series-29307 ("ethdev: add random item support")

Erez Shitrit (1):
  net/mlx5/hws: add support for random number match

Michael Baum (1):
  net/mlx5: add random item support

 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               | 10 +++++++-
 doc/guides/rel_notes/release_23_11.rst |  4 +++
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 35 +++++++++++++++++++++++++-
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  8 +++++-
 drivers/net/mlx5/mlx5_flow.h           |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
 8 files changed, 68 insertions(+), 3 deletions(-)

-- 
2.25.1

[PATCH 1/2] net/mlx5/hws: add support for random number match

[Michael Baum]

From: Erez Shitrit <erezsh@nvidia.com>

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that filed we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 35 ++++++++++++++++++++++++++-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  8 +++++-
 drivers/net/mlx5/mlx5_flow.h          |  3 +++
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 33d0f2d18e..a20ea73605 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -177,7 +177,8 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_spi,              v->hdr.spi,             rte_flow_item_esp) \
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
-	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth)
+	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 
 /* Item set function format */
 #define X(set_type, func_name, value, item_type) \
@@ -1965,6 +1966,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2016,6 +2044,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2319,6 +2348,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_IB_BTH;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6b645f4cf0..1405c752b8 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -136,6 +136,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,
 	MLX5DR_DEFINER_FNAME_IB_L4_OPCODE,
 	MLX5DR_DEFINER_FNAME_IB_L4_QPN,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -392,6 +393,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -501,7 +507,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 3a97975d69..8a9bd71692 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -233,6 +233,9 @@ enum mlx5_feature_name {
 /* IB BTH ITEM. */
 #define MLX5_FLOW_ITEM_IB_BTH (1ull << 51)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 52)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
-- 
2.25.1

[PATCH 2/2] net/mlx5: add random item support

[Michael Baum]

Add support for random item in HWS mode.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               | 10 +++++++++-
 doc/guides/rel_notes/release_23_11.rst |  4 ++++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 +++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 +++++
 5 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index c0e0b779cf..5606f435f2 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -86,6 +86,7 @@ nvgre                = Y
 port_id              = Y
 port_representor     = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index eac67a7864..f754fab3e1 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -165,7 +165,7 @@ Features
 - Sub-Function.
 - Matching on represented port.
 - Matching on aggregated affinity.
-
+- Matching on random value.
 
 Limitations
 -----------
@@ -554,6 +554,7 @@ Limitations
   - Modification of the MPLS header is supported only in HWS and only to copy from,
     the encapsulation level is always 0.
   - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
+  - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
@@ -712,6 +713,13 @@ Limitations
 
 - The NIC egress flow rules on representor port are not supported.
 
+- Match on random value:
+
+  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
+  - Supported only in table with ``nb_flows=1``.
+  - NIC ingress flow in group 0 is not supported.
+  - Supports matching only 16 bits (LSB).
+
 - During live migration to a new process set its flow engine as standby mode,
   the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).
   Live migration is only supported under SWS (``dv_flow_en=1``).
diff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst
index 1e90bf83e7..8a4c04ed75 100644
--- a/doc/guides/rel_notes/release_23_11.rst
+++ b/doc/guides/rel_notes/release_23_11.rst
@@ -76,6 +76,10 @@ New Features
 
   Added ``RTE_FLOW_ITEM_RANDOM`` to match random value.
 
+* **Updated NVIDIA mlx5 net driver.**
+
+  * Added support for random value matching.
+
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index a8dd9920e6..1238d00073 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5385,6 +5385,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifications of the MPLS header "
 				"is not supported");
+	if (dst_data->field == RTE_FLOW_FIELD_RANDOM ||
+	    src_data->field == RTE_FLOW_FIELD_RANDOM)
+		return rte_flow_error_set(error, ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifications of random value is not supported");
 	if (dst_data->field == RTE_FLOW_FIELD_MARK ||
 	    src_data->field == RTE_FLOW_FIELD_MARK)
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 5395969eb0..6fe6103a37 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -3893,6 +3893,10 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifying Geneve VNI is not supported");
+	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifying random value is not supported");
 	/* Due to HW bug, tunnel MPLS header is read only. */
 	if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)
 		return rte_flow_error_set(error, EINVAL,
@@ -5375,6 +5379,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_ESP:
 		case RTE_FLOW_ITEM_TYPE_FLEX:
 		case RTE_FLOW_ITEM_TYPE_IB_BTH:
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
 			break;
 		case RTE_FLOW_ITEM_TYPE_INTEGRITY:
 			/*
-- 
2.25.1

RE: [PATCH 1/2] net/mlx5/hws: add support for random number match

[Ori Kam]

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Tuesday, August 22, 2023 1:36 PM
> From: Erez Shitrit <erezsh@nvidia.com>
> 
> The HW adds a random number per each hash, this value can be used for
> statistic calculation over the packets, for example by setting one bit in
> the mask of that filed we will get half of the traffic in the flow, and
> so on with the rest of the mask.
> 
> Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

RE: [PATCH 2/2] net/mlx5: add random item support

[Ori Kam]

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Tuesday, August 22, 2023 1:36 PM
> Add support for random item in HWS mode.
> 
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[PATCH v2 0/2] net/mlx5: add random item support

[Michael Baum]

Add support for matching random value using the "rte_flow_item_random"
structure.

Depends-on: series-29472 ("ethdev: add random item support")

v2:
 - Rebase.
 - Move release notes to the new release file.

Erez Shitrit (1):
  net/mlx5/hws: add support for random number match

Michael Baum (1):
  net/mlx5: add random item support

 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               | 10 +++++++-
 doc/guides/rel_notes/release_24_03.rst |  3 +++
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 33 ++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h           |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
 8 files changed, 66 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH v2 1/2] net/mlx5/hws: add support for random number match

[Michael Baum]

From: Erez Shitrit <erezsh@nvidia.com>

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that filed we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h          |  3 +++
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 0b60479406..005733372a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -182,6 +182,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
 	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
@@ -2173,6 +2174,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2224,6 +2252,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2537,6 +2566,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6f1c99e37a..18591ef853 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -150,6 +150,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -407,6 +408,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -516,7 +522,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 6dde9de688..14311eff10 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -277,6 +277,9 @@ enum mlx5_feature_name {
 /* NSH ITEM */
 #define MLX5_FLOW_ITEM_NSH (1ull << 53)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 53)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
-- 
2.25.1

[PATCH v2 2/2] net/mlx5: add random item support

[Michael Baum]

Add support for random item in HWS mode.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               | 10 +++++++++-
 doc/guides/rel_notes/release_24_03.rst |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 +++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 +++++
 5 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index 0739fe9d63..6261b7d657 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -88,6 +88,7 @@ port_id              = Y
 port_representor     = Y
 ptype                = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 6b52fb93c5..129f7d9d24 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -167,7 +167,7 @@ Features
 - Sub-Function.
 - Matching on represented port.
 - Matching on aggregated affinity.
-
+- Matching on random value.
 
 Limitations
 -----------
@@ -564,6 +564,7 @@ Limitations
   - Modification of the MPLS header is supported only in HWS and only to copy from,
     the encapsulation level is always 0.
   - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
+  - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
@@ -770,6 +771,13 @@ Limitations
   - In HW steering (``dv_flow_en`` = 2):
     - not supported on guest port.
 
+- Match on random value:
+
+  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
+  - Supported only in table with ``nb_flows=1``.
+  - NIC ingress flow in group 0 is not supported.
+  - Supports matching only 16 bits (LSB).
+
 - During live migration to a new process set its flow engine as standby mode,
   the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).
   Live migration is only supported under SWS (``dv_flow_en=1``).
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index ab91ce2b21..164cf74f5b 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -59,6 +59,9 @@ New Features
 
   Added ``RTE_FLOW_ITEM_RANDOM`` to match random value.
 
+* **Updated NVIDIA mlx5 net driver.**
+
+  * Added support for ``RTE_FLOW_ITEM_TYPE_RUNDOM`` flow item.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 115d730317..67a44095d7 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifications of the MPLS header "
 				"is not supported");
+	if (dst_data->field == RTE_FLOW_FIELD_RANDOM ||
+	    src_data->field == RTE_FLOW_FIELD_RANDOM)
+		return rte_flow_error_set(error, ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifications of random value is not supported");
 	if (dst_data->field == RTE_FLOW_FIELD_MARK ||
 	    src_data->field == RTE_FLOW_FIELD_MARK)
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index da873ae2e2..af4e9abd89 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifying vlan_type is not supported");
+	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifying random value is not supported");
 	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
@@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_FLEX:
 		case RTE_FLOW_ITEM_TYPE_IB_BTH:
 		case RTE_FLOW_ITEM_TYPE_PTYPE:
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
 			break;
 		case RTE_FLOW_ITEM_TYPE_INTEGRITY:
 			/*
-- 
2.25.1

RE: [PATCH v2 1/2] net/mlx5/hws: add support for random number match

[Dariusz Sosnowski]

> The HW adds a random number per each hash, this value can be used for
> statistic calculation over the packets, for example by setting one bit in the mask
> of that filed we will get half of the traffic in the flow, and so on with the rest of
> the mask.
Looks like there's a typo - s/filed/field

Other than that, LGTM.

Best regards,
Dariusz Sosnowski

RE: [PATCH v2 2/2] net/mlx5: add random item support

[Dariusz Sosnowski]

> +- Match on random value:
> +
> +  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
> +  - Supported only in table with ``nb_flows=1``.
> +  - NIC ingress flow in group 0 is not supported.
Shouldn't egress flow in group 0 be mentioned here as well?

> +* **Updated NVIDIA mlx5 net driver.**
> +
> +  * Added support for ``RTE_FLOW_ITEM_TYPE_RUNDOM`` flow item.
Typo - s/RUNDOM/RANDOM

Other than that, LGTM.

Best regards,
Dariusz Sosnowski

[PATCH v3 0/2] net/mlx5: add random item support

[Michael Baum]

Add support for matching random value using the "rte_flow_item_random"
structure.

Depends-on: series-30553 ("ethdev: add random item support")

v2:
 - Rebase.
 - Move release notes to the new release file.

v3:
 - Fix typos in commit message and release notes.
 - Update limitations.


Erez Shitrit (1):
  net/mlx5/hws: add support for random number match

Michael Baum (1):
  net/mlx5: add random item support

 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               |  9 +++++++
 doc/guides/rel_notes/release_24_03.rst |  3 +++
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 33 ++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h           |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
 8 files changed, 66 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v3 1/2] net/mlx5/hws: add support for random number match

[Michael Baum]

From: Erez Shitrit <erezsh@nvidia.com>

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that field we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h          |  3 +++
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 0b60479406..005733372a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -182,6 +182,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
 	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
@@ -2173,6 +2174,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2224,6 +2252,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2537,6 +2566,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6f1c99e37a..18591ef853 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -150,6 +150,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -407,6 +408,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -516,7 +522,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 6dde9de688..14311eff10 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -277,6 +277,9 @@ enum mlx5_feature_name {
 /* NSH ITEM */
 #define MLX5_FLOW_ITEM_NSH (1ull << 53)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 53)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
-- 
2.25.1

[PATCH v3 2/2] net/mlx5: add random item support

[Michael Baum]

Add support for random item in HWS mode.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 doc/guides/nics/features/mlx5.ini      | 1 +
 doc/guides/nics/mlx5.rst               | 9 +++++++++
 doc/guides/rel_notes/release_24_03.rst | 3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        | 5 +++++
 drivers/net/mlx5/mlx5_flow_hw.c        | 5 +++++
 5 files changed, 23 insertions(+)

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index 0739fe9d63..6261b7d657 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -88,6 +88,7 @@ port_id              = Y
 port_representor     = Y
 ptype                = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 6b52fb93c5..971c229850 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -167,6 +167,7 @@ Features
 - Sub-Function.
 - Matching on represented port.
 - Matching on aggregated affinity.
+- Matching on random value.
 
 
 Limitations
@@ -564,6 +565,7 @@ Limitations
   - Modification of the MPLS header is supported only in HWS and only to copy from,
     the encapsulation level is always 0.
   - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
+  - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
@@ -770,6 +772,13 @@ Limitations
   - In HW steering (``dv_flow_en`` = 2):
     - not supported on guest port.
 
+- Match on random value:
+
+  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
+  - Supported only in table with ``nb_flows=1``.
+  - NIC ingress/egress flow in group 0 is not supported.
+  - Supports matching only 16 bits (LSB).
+
 - During live migration to a new process set its flow engine as standby mode,
   the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).
   Live migration is only supported under SWS (``dv_flow_en=1``).
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 819cef7f20..93e58b55ca 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -60,6 +60,9 @@ New Features
   * Added ``RTE_FLOW_ITEM_TYPE_RANDOM`` to match random value.
   * Added ``RTE_FLOW_FIELD_RANDOM`` to represent it in field API.
 
+* **Updated NVIDIA mlx5 net driver.**
+
+  * Added support for ``RTE_FLOW_ITEM_TYPE_RANDOM`` flow item.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 115d730317..67a44095d7 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifications of the MPLS header "
 				"is not supported");
+	if (dst_data->field == RTE_FLOW_FIELD_RANDOM ||
+	    src_data->field == RTE_FLOW_FIELD_RANDOM)
+		return rte_flow_error_set(error, ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifications of random value is not supported");
 	if (dst_data->field == RTE_FLOW_FIELD_MARK ||
 	    src_data->field == RTE_FLOW_FIELD_MARK)
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index da873ae2e2..af4e9abd89 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifying vlan_type is not supported");
+	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifying random value is not supported");
 	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
@@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_FLEX:
 		case RTE_FLOW_ITEM_TYPE_IB_BTH:
 		case RTE_FLOW_ITEM_TYPE_PTYPE:
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
 			break;
 		case RTE_FLOW_ITEM_TYPE_INTEGRITY:
 			/*
-- 
2.25.1

RE: [PATCH v3 1/2] net/mlx5/hws: add support for random number match

[Dariusz Sosnowski]

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Thursday, December 14, 2023 16:13
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; Suanming
> Mou <suanmingm@nvidia.com>; Erez Shitrit <erezsh@nvidia.com>
> Subject: [PATCH v3 1/2] net/mlx5/hws: add support for random number match
> 
> From: Erez Shitrit <erezsh@nvidia.com>
> 
> The HW adds a random number per each hash, this value can be used for
> statistic calculation over the packets, for example by setting one bit in the mask
> of that field we will get half of the traffic in the flow, and so on with the rest of
> the mask.
> 
> Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Best regards,
Dariusz Sosnowski

RE: [PATCH v3 2/2] net/mlx5: add random item support

[Dariusz Sosnowski]

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Thursday, December 14, 2023 16:13
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; Suanming
> Mou <suanmingm@nvidia.com>
> Subject: [PATCH v3 2/2] net/mlx5: add random item support
> 
> Add support for random item in HWS mode.
> 
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Best regards,
Dariusz Sosnowski

[PATCH v4 0/2] net/mlx5: add random item support

[Michael Baum]

Add support for matching random value using the "rte_flow_item_random"
structure.

Depends-on: series-30553 ("ethdev: add random item support")

v2:
 - Rebase.
 - Move release notes to the new release file.

v3:
 - Fix typos in commit message and release notes.
 - Update limitations.

v4:
 - Fix using same value for both "MLX5_FLOW_ITEM_NSH" and
   "MLX5_FLOW_ITEM_RANDOM".
 - Add "Acked-by" from v3.

Erez Shitrit (1):
  net/mlx5/hws: add support for random number match

Michael Baum (1):
  net/mlx5: add random item support

 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               |  9 +++++++
 doc/guides/rel_notes/release_24_03.rst |  3 +++
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 33 ++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h           |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
 8 files changed, 66 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v4 1/2] net/mlx5/hws: add support for random number match

[Michael Baum]

From: Erez Shitrit <erezsh@nvidia.com>

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that field we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h          |  3 +++
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 0b60479406..005733372a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -182,6 +182,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
 	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
@@ -2173,6 +2174,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2224,6 +2252,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2537,6 +2566,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		default:
 			DR_LOG(ERR, "Unsupported item type %d", items->type);
 			rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6f1c99e37a..18591ef853 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -150,6 +150,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -407,6 +408,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -516,7 +522,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 6dde9de688..0a83c7f384 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -277,6 +277,9 @@ enum mlx5_feature_name {
 /* NSH ITEM */
 #define MLX5_FLOW_ITEM_NSH (1ull << 53)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 54)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
-- 
2.25.1

[PATCH v4 2/2] net/mlx5: add random item support

[Michael Baum]

Add support for random item in HWS mode.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/features/mlx5.ini      | 1 +
 doc/guides/nics/mlx5.rst               | 9 +++++++++
 doc/guides/rel_notes/release_24_03.rst | 3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        | 5 +++++
 drivers/net/mlx5/mlx5_flow_hw.c        | 5 +++++
 5 files changed, 23 insertions(+)

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index 0739fe9d63..6261b7d657 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -88,6 +88,7 @@ port_id              = Y
 port_representor     = Y
 ptype                = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 6b52fb93c5..971c229850 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -167,6 +167,7 @@ Features
 - Sub-Function.
 - Matching on represented port.
 - Matching on aggregated affinity.
+- Matching on random value.
 
 
 Limitations
@@ -564,6 +565,7 @@ Limitations
   - Modification of the MPLS header is supported only in HWS and only to copy from,
     the encapsulation level is always 0.
   - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
+  - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
@@ -770,6 +772,13 @@ Limitations
   - In HW steering (``dv_flow_en`` = 2):
     - not supported on guest port.
 
+- Match on random value:
+
+  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
+  - Supported only in table with ``nb_flows=1``.
+  - NIC ingress/egress flow in group 0 is not supported.
+  - Supports matching only 16 bits (LSB).
+
 - During live migration to a new process set its flow engine as standby mode,
   the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).
   Live migration is only supported under SWS (``dv_flow_en=1``).
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 819cef7f20..93e58b55ca 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -60,6 +60,9 @@ New Features
   * Added ``RTE_FLOW_ITEM_TYPE_RANDOM`` to match random value.
   * Added ``RTE_FLOW_FIELD_RANDOM`` to represent it in field API.
 
+* **Updated NVIDIA mlx5 net driver.**
+
+  * Added support for ``RTE_FLOW_ITEM_TYPE_RANDOM`` flow item.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 115d730317..67a44095d7 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifications of the MPLS header "
 				"is not supported");
+	if (dst_data->field == RTE_FLOW_FIELD_RANDOM ||
+	    src_data->field == RTE_FLOW_FIELD_RANDOM)
+		return rte_flow_error_set(error, ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifications of random value is not supported");
 	if (dst_data->field == RTE_FLOW_FIELD_MARK ||
 	    src_data->field == RTE_FLOW_FIELD_MARK)
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index da873ae2e2..af4e9abd89 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifying vlan_type is not supported");
+	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifying random value is not supported");
 	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
@@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_FLEX:
 		case RTE_FLOW_ITEM_TYPE_IB_BTH:
 		case RTE_FLOW_ITEM_TYPE_PTYPE:
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
 			break;
 		case RTE_FLOW_ITEM_TYPE_INTEGRITY:
 			/*
-- 
2.25.1

RE: [PATCH v4 1/2] net/mlx5/hws: add support for random number match

[Dariusz Sosnowski]

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Monday, December 25, 2023 11:25
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>;
> Suanming Mou <suanmingm@nvidia.com>; Erez Shitrit <erezsh@nvidia.com>
> Subject: [PATCH v4 1/2] net/mlx5/hws: add support for random number
> match
> 
> From: Erez Shitrit <erezsh@nvidia.com>
> 
> The HW adds a random number per each hash, this value can be used for
> statistic calculation over the packets, for example by setting one bit in the mask
> of that field we will get half of the traffic in the flow, and so on with the rest of
> the mask.
> 
> Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Best regards,
Dariusz Sosnowski

[PATCH v5 0/2] net/mlx5: add random item support

[Michael Baum]

Add support for matching random value using the "rte_flow_item_random"
structure.

v2:
 - Rebase.
 - Move release notes to the new release file.

v3:
 - Fix typos in commit message and release notes.
 - Update limitations.

v4:
 - Fix using same value for both "MLX5_FLOW_ITEM_NSH" and
   "MLX5_FLOW_ITEM_RANDOM".
 - Add "Acked-by" from v3.

v5:
 - Rebase.
 - Remove "Depends-on" label.


Erez Shitrit (1):
  net/mlx5/hws: add support for random number match

Michael Baum (1):
  net/mlx5: add random item support

 doc/guides/nics/features/mlx5.ini      |  1 +
 doc/guides/nics/mlx5.rst               |  9 +++++++
 doc/guides/rel_notes/release_24_03.rst |  1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c  | 33 ++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h  |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h           |  3 +++
 drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
 8 files changed, 64 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH v5 1/2] net/mlx5/hws: add support for random number match

[Michael Baum]

From: Erez Shitrit <erezsh@nvidia.com>

The HW adds a random number per each hash, this value can be used for
statistic calculation over the packets, for example by setting one bit in
the mask of that field we will get half of the traffic in the flow, and
so on with the rest of the mask.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_definer.h |  8 ++++++-
 drivers/net/mlx5/mlx5_flow.h          |  3 +++
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index af924b490c..750eb9c7c6 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -187,6 +187,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET_BE32,     ipsec_sequence_number,  v->hdr.seq,             rte_flow_item_esp) \
 	X(SET,		ib_l4_udp_port,		UDP_ROCEV2_PORT,	rte_flow_item_ib_bth) \
 	X(SET,		ib_l4_opcode,		v->hdr.opcode,		rte_flow_item_ib_bth) \
+	X(SET,		random_number,		v->value,		rte_flow_item_random) \
 	X(SET,		ib_l4_bth_a,		v->hdr.a,		rte_flow_item_ib_bth) \
 
 /* Item set function format */
@@ -2200,6 +2201,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,
 	return 0;
 }
 
+static int
+mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd,
+				struct rte_flow_item *item,
+				int item_idx)
+{
+	const struct rte_flow_item_random *m = item->mask;
+	const struct rte_flow_item_random *l = item->last;
+	struct mlx5dr_definer_fc *fc;
+
+	if (!m)
+		return 0;
+
+	if (m->value != (m->value & UINT16_MAX)) {
+		DR_LOG(ERR, "Random value is 16 bits only");
+		rte_errno = EINVAL;
+		return rte_errno;
+	}
+
+	fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM];
+	fc->item_idx = item_idx;
+	fc->tag_set = &mlx5dr_definer_random_number_set;
+	fc->is_range = l && l->value;
+	DR_CALC_SET_HDR(fc, random_number, random_number);
+
+	return 0;
+}
+
 static int
 mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,
 			 struct mlx5dr_definer_fc *fc,
@@ -2251,6 +2279,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
 	case RTE_FLOW_ITEM_TYPE_TAG:
 	case RTE_FLOW_ITEM_TYPE_META:
 	case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
+	case RTE_FLOW_ITEM_TYPE_RANDOM:
 		return 0;
 	default:
 		DR_LOG(ERR, "Range not supported over item type %d", item->type);
@@ -2645,6 +2674,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 			ret = mlx5dr_definer_conv_item_ptype(&cd, items, i);
 			item_flags |= MLX5_FLOW_ITEM_PTYPE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
+			ret = mlx5dr_definer_conv_item_random(&cd, items, i);
+			item_flags |= MLX5_FLOW_ITEM_RANDOM;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 			ret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i);
 			item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 3dc5f4438d..7b7463fc91 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -155,6 +155,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
+	MLX5DR_DEFINER_FNAME_RANDOM_NUM,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
@@ -412,6 +413,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits {
 	u8 destination_address[0x20];
 };
 
+struct mlx5_ifc_definer_hl_random_number_bits {
+	u8 random_number[0x10];
+	u8 reserved[0x10];
+};
+
 struct mlx5_ifc_definer_hl_ipv6_addr_bits {
 	u8 ipv6_address_127_96[0x20];
 	u8 ipv6_address_95_64[0x20];
@@ -521,7 +527,7 @@ struct mlx5_ifc_definer_hl_bits {
 	struct mlx5_ifc_definer_hl_mpls_bits mpls_inner;
 	u8 unsupported_config_headers_outer[0x80];
 	u8 unsupported_config_headers_inner[0x80];
-	u8 unsupported_random_number[0x20];
+	struct mlx5_ifc_definer_hl_random_number_bits random_number;
 	struct mlx5_ifc_definer_hl_ipsec_bits ipsec;
 	struct mlx5_ifc_definer_hl_metadata_bits metadata;
 	u8 unsupported_utc_timestamp[0x40];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index fe4f46724b..6f720de14d 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -277,6 +277,9 @@ enum mlx5_feature_name {
 /* NSH ITEM */
 #define MLX5_FLOW_ITEM_NSH (1ull << 53)
 
+/* Random ITEM */
+#define MLX5_FLOW_ITEM_RANDOM (1ull << 54)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
-- 
2.25.1

[PATCH v5 2/2] net/mlx5: add random item support

[Michael Baum]

Add support for random item in HWS mode.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/features/mlx5.ini      | 1 +
 doc/guides/nics/mlx5.rst               | 9 +++++++++
 doc/guides/rel_notes/release_24_03.rst | 1 +
 drivers/net/mlx5/mlx5_flow_dv.c        | 5 +++++
 drivers/net/mlx5/mlx5_flow_hw.c        | 5 +++++
 5 files changed, 21 insertions(+)

diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini
index 0739fe9d63..6261b7d657 100644
--- a/doc/guides/nics/features/mlx5.ini
+++ b/doc/guides/nics/features/mlx5.ini
@@ -88,6 +88,7 @@ port_id              = Y
 port_representor     = Y
 ptype                = Y
 quota                = Y
+random               = Y
 tag                  = Y
 tcp                  = Y
 udp                  = Y
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 27384d5a86..f8930cb902 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -167,6 +167,7 @@ Features
 - Sub-Function.
 - Matching on represented port.
 - Matching on aggregated affinity.
+- Matching on random value.
 
 
 Limitations
@@ -571,6 +572,7 @@ Limitations
   - Modification of the MPLS header is supported only in HWS and only to copy from,
     the encapsulation level is always 0.
   - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
+  - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets cannot skip past the boundary of a field.
   - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``
@@ -777,6 +779,13 @@ Limitations
   - In HW steering (``dv_flow_en`` = 2):
     - not supported on guest port.
 
+- Match on random value:
+
+  - Supported only with HW Steering enabled (``dv_flow_en`` = 2).
+  - Supported only in table with ``nb_flows=1``.
+  - NIC ingress/egress flow in group 0 is not supported.
+  - Supports matching only 16 bits (LSB).
+
 - During live migration to a new process set its flow engine as standby mode,
   the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).
   Live migration is only supported under SWS (``dv_flow_en=1``).
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index 5e545da867..a1dfea263c 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -75,6 +75,7 @@ New Features
   * Added support for VXLAN-GPE matching in HW Steering flow engine
     (``dv_flow_en`` = 2).
 
+  * Added support for ``RTE_FLOW_ITEM_TYPE_RANDOM`` flow item.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index bc0572a763..88b5c20758 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5496,6 +5496,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifications of the MPLS header "
 				"is not supported");
+	if (dst_data->field == RTE_FLOW_FIELD_RANDOM ||
+	    src_data->field == RTE_FLOW_FIELD_RANDOM)
+		return rte_flow_error_set(error, ENOTSUP,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifications of random value is not supported");
 	if (dst_data->field == RTE_FLOW_FIELD_MARK ||
 	    src_data->field == RTE_FLOW_FIELD_MARK)
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 48b70c0c29..f06d2ce273 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5085,6 +5085,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
 				"modifying vlan_type is not supported");
+	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION, action,
+				"modifying random value is not supported");
 	if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION, action,
@@ -6851,6 +6855,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_FLEX:
 		case RTE_FLOW_ITEM_TYPE_IB_BTH:
 		case RTE_FLOW_ITEM_TYPE_PTYPE:
+		case RTE_FLOW_ITEM_TYPE_RANDOM:
 			break;
 		case RTE_FLOW_ITEM_TYPE_INTEGRITY:
 			/*
-- 
2.25.1

RE: [PATCH v5 0/2] net/mlx5: add random item support

[Raslan Darawsheh]

Hi,

> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Thursday, January 25, 2024 2:37 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>;
> Suanming Mou <suanmingm@nvidia.com>
> Subject: [PATCH v5 0/2] net/mlx5: add random item support
> 
> Add support for matching random value using the "rte_flow_item_random"
> structure.
> 
> v2:
>  - Rebase.
>  - Move release notes to the new release file.
> 
> v3:
>  - Fix typos in commit message and release notes.
>  - Update limitations.
> 
> v4:
>  - Fix using same value for both "MLX5_FLOW_ITEM_NSH" and
>    "MLX5_FLOW_ITEM_RANDOM".
>  - Add "Acked-by" from v3.
> 
> v5:
>  - Rebase.
>  - Remove "Depends-on" label.
> 
> 
> Erez Shitrit (1):
>   net/mlx5/hws: add support for random number match
> 
> Michael Baum (1):
>   net/mlx5: add random item support
> 
>  doc/guides/nics/features/mlx5.ini      |  1 +
>  doc/guides/nics/mlx5.rst               |  9 +++++++
>  doc/guides/rel_notes/release_24_03.rst |  1 +
> drivers/net/mlx5/hws/mlx5dr_definer.c  | 33
> ++++++++++++++++++++++++++  drivers/net/mlx5/hws/mlx5dr_definer.h  |
> 8 ++++++-
>  drivers/net/mlx5/mlx5_flow.h           |  3 +++
>  drivers/net/mlx5/mlx5_flow_dv.c        |  5 ++++
>  drivers/net/mlx5/mlx5_flow_hw.c        |  5 ++++
>  8 files changed, 64 insertions(+), 1 deletion(-)
> 
> --
> 2.25.1

Sereis applied to next-net-mlx,
Kindest regards
Raslan Darawsheh