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From: Thomas Monjalon <thomas@monjalon.net>
To: Haiyue Wang <haiyue.wang@intel.com>
Cc: dev@dpdk.org, arybchenko@solarflare.com, ferruh.yigit@intel.com,
	jerinjacobk@gmail.com, xiaolong.ye@intel.com,
	ray.kinsella@intel.com, chenmin.sun@intel.com,
	Slava Ovsiienko <viacheslavo@mellanox.com>
Subject: Re: [dpdk-dev] [PATCH v1 3/3] ethdev: enhance the API for getting burst mode information
Date: Fri, 01 Nov 2019 23:46:23 +0100	[thread overview]
Message-ID: <20693558.VL3dRorq05@xps> (raw)
In-Reply-To: <20191031171139.105110-3-haiyue.wang@intel.com>

Thank you for trying to address comments done late.

31/10/2019 18:11, Haiyue Wang:
> --- a/lib/librte_ethdev/rte_ethdev.h
> +++ b/lib/librte_ethdev/rte_ethdev.h
> -enum rte_eth_burst_mode_option {
> -	RTE_ETH_BURST_SCALAR = (1 << 0),
> -	RTE_ETH_BURST_VECTOR = (1 << 1),
> -
> -	/**< bits[15:2] are reserved for each vector type */
> -	RTE_ETH_BURST_ALTIVEC = (1 << 2),
> -	RTE_ETH_BURST_NEON = (1 << 3),
> -	RTE_ETH_BURST_SSE = (1 << 4),
> -	RTE_ETH_BURST_AVX2 = (1 << 5),
> -	RTE_ETH_BURST_AVX512 = (1 << 6),
> -
> -	RTE_ETH_BURST_SCATTERED = (1 << 16), /**< Support scattered packets */
> -	RTE_ETH_BURST_BULK_ALLOC = (1 << 17), /**< Support mbuf bulk alloc */
> -	RTE_ETH_BURST_SIMPLE = (1 << 18),
> -
> -	RTE_ETH_BURST_PER_QUEUE = (1 << 19), /**< Support per queue burst */
> -};
> +#define RTE_ETH_BURST_SCALAR        (1ULL << 0)
> +#define RTE_ETH_BURST_VECTOR        (1ULL << 1)

Only one bit is needed: if it is not vector, it is scalar.
I think you can remove the scalar bit.

> +/**< bits[15:2] are reserved for each vector type */

Why 15:2 instead of 2:15?

> +#define RTE_ETH_BURST_ALTIVEC       (1ULL << 2)
> +#define RTE_ETH_BURST_NEON          (1ULL << 3)
> +#define RTE_ETH_BURST_SSE           (1ULL << 4)
> +#define RTE_ETH_BURST_AVX2          (1ULL << 5)
> +#define RTE_ETH_BURST_AVX512        (1ULL << 6)

Of course, I still believe that giving a special treatment
to vector instructions is wrong.
You did not justify why it needs to be defined in bits
instead of string. I am not asking again because anyway you
don't really reply. I think you are executing an order you received
and I don't want to blame you more.
I suspect a real hidden issue in Intel CPUs that you try to mitigate.
No need to reply to this comment.
Anyway I will propose to replace this API in the next release.

> +/**< Support per queue burst */
> +#define RTE_ETH_BURST_PER_QUEUE     (1ULL << 63)

This comment is meaningless.
If this bit has a usage, please explain how to use this bit
in the comment.



  reply	other threads:[~2019-11-01 22:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-31 17:11 [dpdk-dev] [PATCH v1 1/3] net/ice: remove the specific burst mode bit set Haiyue Wang
2019-10-31 17:11 ` [dpdk-dev] [PATCH v1 2/3] net/i40e: " Haiyue Wang
2019-10-31 17:11 ` [dpdk-dev] [PATCH v1 3/3] ethdev: enhance the API for getting burst mode information Haiyue Wang
2019-11-01 22:46   ` Thomas Monjalon [this message]
2019-11-02  5:29     ` Wang, Haiyue
2019-11-02  6:55       ` Liu, Yu Y
2019-11-02  8:38         ` Slava Ovsiienko
2019-11-02 19:21           ` Damjan Marion (damarion)
2019-11-03  7:50             ` Slava Ovsiienko
2019-11-05 15:12               ` Ferruh Yigit
2019-11-05 15:54                 ` Stephen Hemminger
2019-11-03 20:46             ` Ray Kinsella
2019-11-03  2:34           ` Wang, Haiyue
2019-11-03  3:03             ` Wang, Haiyue
2019-11-03  8:59             ` Slava Ovsiienko
2019-11-03 11:38               ` Wang, Haiyue
2019-11-03 19:31                 ` Slava Ovsiienko
2019-11-04  1:01                   ` Wang, Haiyue
2019-11-02 18:31         ` Thomas Monjalon
2019-11-03  3:52     ` Wang, Haiyue
2019-11-03 22:20       ` Thomas Monjalon
2019-11-04  0:51         ` Wang, Haiyue

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