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From: David Marchand <david.marchand@redhat.com>
To: "Stanisław Kardach" <kda@semihalf.com>
Cc: dev <dev@dpdk.org>, Frank Zhao <Frank.Zhao@starfivetech.com>,
	 Sam Grove <sam.grove@sifive.com>,
	Marcin Wojtas <mw@semihalf.com>,
	upstream@semihalf.com, Thomas Monjalon <thomas@monjalon.net>,
	Stephen Hemminger <stephen@networkplumber.org>
Subject: Re: [PATCH 00/11] Introduce support for RISC-V architecture
Date: Mon, 9 May 2022 16:30:49 +0200	[thread overview]
Message-ID: <CAJFAV8xb60trxT1JQs8q2pzAhiamXSxM_vh8J3noDWdDX+Nx2g@mail.gmail.com> (raw)
In-Reply-To: <CALVGJW+rDU2F+QYVOEAqE2C5EXeXobOPL7rkdb4LipBjjW10uw@mail.gmail.com>

On Mon, May 9, 2022 at 2:24 PM Stanisław Kardach <kda@semihalf.com> wrote:
>> Testing all riscv configs in test-meson-buils.sh seems too much to me.
>> Is there a real value to test both current targets?
>
> It's for sanity and compilation coverage testing. I.e. SiFive variant has a specific build config which does not require extra barriers when reading time and cycle registers for rte_rdtsc_precise(). I want to make sure that if anyone changes some code based on configuration flags, it gets at least compile-checked.
> I believe similar thing is done for Aarch64 builds.

As far as I experienced, building all those aarch64 combinations never
revealed any specific platform compilation issue.
It only consumes cpu, disk and our (maintainers) time.
I proposed to Thomas to shrink aarch64 builds list not so long ago :-).

The best would be for SiFive to provide a system for the CI to do
those checks on their variant.


>> About the new "Sponsored-by" tag, it should not raise warnings in the
>> CI if we agree on its addition.
>
> I'll modify it in V2 to be in form of:
>   Sponsored by: StarFive Technology
>   ...
>   Signed-off-by: ...
> This was suggested by Stephen Hemminger as having a precedent in Linux kernel. Interestingly enough first use of this tag in kernel source was this year in January.

I don't have an opinion on the spelling.

At the moment, the checks raise a warning:
http://mails.dpdk.org/archives/test-report/2022-May/278580.html

My point is that for this new tag, either checkpatch.pl in kernel
handles it (which I don't think it is the case) or we need to disable
the signature check in checkpatch.pl and something is added in dpdk
checkpatches.sh to accept all known tags.


>> In general, please avoid letting arch specific headers leak
>> internal/non rte_ prefixed helpers out of them.
>> For example, I noticed a RV64_CSRR macro that can be undefined after usage.
>
> Thanks for noticing. I'l fix this one in V2.
> There are 2 other symbols that leak but on purpose (out of a better idea): vect_load_128() and vect_and(). Both are used in l3fwd_em to simulate vector operations. Other platforms reference their intrinsics straight in the l3fwd_em.c. As I don't have support for vector ops and I wanted to indicate that xmm_t should be an isolated API, I've put both in rte_vect.h. That said I'm not happy with this solution and am open to suggestions on how to solve it neatly.

I'll try to have a look in the next revision.


>>
>>
>> Patch 3 is huge, not sure it is easy to split, did you consider doing so?
>
> It seems to me the nature of a new EAL implementation, I have to include all symbols, otherwise DPDK won't compile.
> Alternatively I could have a huge initial patch with empty stubs that would be filled in later commits. Downside of this approach is that it's hard to verify each commit separately as tests will fail until all implementation is there, so the division is only visual.

If you are sure there is nothing that can be separated, let's keep it whole.



-- 
David Marchand


  parent reply	other threads:[~2022-05-09 14:31 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 17:29 Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39   ` Stephen Hemminger
2022-05-05 17:49     ` Stanisław Kardach
2022-05-05 18:09       ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35   ` Stephen Hemminger
2022-05-05 17:43     ` Stanisław Kardach
2022-05-05 18:06       ` Stephen Hemminger
2022-05-10 23:28   ` Honnappa Nagarahalli
2022-05-11 10:07     ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06  9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24   ` Stanisław Kardach
2022-05-09 12:30     ` Thomas Monjalon
2022-05-11  8:09       ` Morten Brørup
2022-05-11 10:28         ` Stanisław Kardach
2022-05-11 11:06           ` Thomas Monjalon
2022-05-09 14:30     ` David Marchand [this message]
2022-05-10 11:21       ` Stanisław Kardach
2022-05-10 12:31         ` Thomas Monjalon
2022-05-10 14:00           ` Stanisław Kardach
2022-05-10 14:23             ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07   ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35     ` Stanisław Kardach
2022-05-10 15:07   ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48   ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13  6:50       ` Heinrich Schuchardt
2022-05-13  8:42         ` Stanisław Kardach
2022-05-13 10:51           ` Heinrich Schuchardt
2022-05-13 11:47             ` Stanisław Kardach
2022-05-13 15:37         ` Stephen Hemminger
2022-05-16  8:00           ` Stanisław Kardach
2022-05-10 15:48     ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48     ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47       ` Aaron Conole
2022-05-12 16:07         ` Stanisław Kardach
2022-05-13 14:33           ` Aaron Conole
2022-05-12  8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12  8:35   ` Stanisław Kardach
2022-05-12  9:46     ` Heinrich Schuchardt
2022-05-12 13:56       ` Stanisław Kardach
2022-05-12 21:06         ` Heinrich Schuchardt

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