From: Matan Azrad <matan@nvidia.com>
To: Itamar Gozlan <igozlan@nvidia.com>,
Alex Vesker <valex@nvidia.com>,
Slava Ovsiienko <viacheslavo@nvidia.com>,
"NBU-Contact-Thomas Monjalon (EXTERNAL)" <thomas@monjalon.net>,
Suanming Mou <suanmingm@nvidia.com>, Ori Kam <orika@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: RE: [PATCH 1/5] net/mlx5/hws: add support for matching on bth_a bit
Date: Mon, 9 Oct 2023 07:57:38 +0000 [thread overview]
Message-ID: <DM4PR12MB5389D972F1010F042D961111DFCEA@DM4PR12MB5389.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20230918120705.265025-1-igozlan@nvidia.com>
> RTE_FLOW_ITEM_TYPE_IB_BTH matches an InfiniBand base transport header.
> We extend the match on the acknowledgment bit (BTH_A).
>
> Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
Series-acked-by: Matan Azrad <matan@nvidia.com>
> ---
> drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++++++++++--
> drivers/net/mlx5/hws/mlx5dr_definer.h | 1 +
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c
> b/drivers/net/mlx5/hws/mlx5dr_definer.c
> index 33d0f2d18e..b82af9d102 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_definer.c
> +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
> @@ -177,7 +177,8 @@ struct mlx5dr_definer_conv_data {
> X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \
> X(SET_BE32, ipsec_sequence_number, v->hdr.seq,
> rte_flow_item_esp) \
> X(SET, ib_l4_udp_port, UDP_ROCEV2_PORT,
> rte_flow_item_ib_bth) \
> - X(SET, ib_l4_opcode, v->hdr.opcode,
> rte_flow_item_ib_bth)
> + X(SET, ib_l4_opcode, v->hdr.opcode,
> rte_flow_item_ib_bth) \
> + X(SET, ib_l4_bth_a, v->hdr.a,
> rte_flow_item_ib_bth) \
>
> /* Item set function format */
> #define X(set_type, func_name, value, item_type) \ @@ -2148,7 +2149,7 @@
> mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,
>
> if (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||
> m->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||
> - m->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
> + m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {
> rte_errno = ENOTSUP;
> return rte_errno;
> }
> @@ -2167,6 +2168,13 @@ mlx5dr_definer_conv_item_ib_l4(struct
> mlx5dr_definer_conv_data *cd,
> DR_CALC_SET_HDR(fc, ib_l4, qp);
> }
>
> + if (m->hdr.a) {
> + fc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_A];
> + fc->item_idx = item_idx;
> + fc->tag_set = &mlx5dr_definer_ib_l4_bth_a_set;
> + DR_CALC_SET_HDR(fc, ib_l4, ackreq);
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h
> b/drivers/net/mlx5/hws/mlx5dr_definer.h
> index 6b645f4cf0..bf026fa6bb 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_definer.h
> +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
> @@ -136,6 +136,7 @@ enum mlx5dr_definer_fname {
> MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,
> MLX5DR_DEFINER_FNAME_IB_L4_OPCODE,
> MLX5DR_DEFINER_FNAME_IB_L4_QPN,
> + MLX5DR_DEFINER_FNAME_IB_L4_A,
> MLX5DR_DEFINER_FNAME_MAX,
> };
>
> --
> 2.38.1
next prev parent reply other threads:[~2023-10-09 7:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-18 12:07 Itamar Gozlan
2023-09-18 12:07 ` [PATCH 2/5] net/mlx5/hws: support additional 4 C registers Itamar Gozlan
2023-09-18 12:07 ` [PATCH 3/5] net/mlx5/hws: supporting add_field action Itamar Gozlan
2023-09-18 12:07 ` [PATCH 4/5] net/mlx5/hws: supporting default miss table in HWS Itamar Gozlan
2023-10-29 16:02 ` Ori Kam
2023-09-18 12:07 ` [PATCH 5/5] net/mlx5/hws: fix field copy bind Itamar Gozlan
2023-10-09 7:57 ` Matan Azrad [this message]
2023-10-10 9:33 ` [PATCH 1/5] net/mlx5/hws: add support for matching on bth_a bit Raslan Darawsheh
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