From: dpdklab@iol.unh.edu
To: test-report@dpdk.org
Cc: dpdk-test-reports@iol.unh.edu
Subject: |WARNING| pw127534 [PATCH] [v4] crypto/qat: support to enable insecure algorithms
Date: Fri, 26 May 2023 00:40:32 -0700 (PDT) [thread overview]
Message-ID: <64706270.0c0a0220.4aabd.448dSMTPIN_ADDED_MISSING@mx.google.com> (raw)
Test-Label: iol-testing
Test-Status: WARNING
http://dpdk.org/patch/127534
_apply patch failure_
Submitter: Vikash Poddar <vikash.chandrax.poddar@intel.com>
Date: Friday, May 26 2023 06:48:32
Applied on: CommitID:c9df59bcc9bec67783de98486879594e52bdc418
Apply patch set 127534 failed:
Checking patch app/test/test_cryptodev_asym.c...
Checking patch doc/guides/cryptodevs/qat.rst...
error: while searching for:
To use this feature the user must set the devarg on process start as a device additional devarg::
-a 03:01.1,qat_sym_cipher_crc_enable=1
Running QAT PMD with Intel IPSEC MB library for symmetric precomputes function
error: patch failed: doc/guides/cryptodevs/qat.rst:314
Checking patch drivers/common/qat/qat_device.c...
Hunk #1 succeeded at 365 (offset -6 lines).
Checking patch drivers/common/qat/qat_device.h...
error: while searching for:
#define QAT_DEV_NAME_MAX_LEN 64
#define QAT_IPSEC_MB_LIB "qat_ipsec_mb_lib"
#define SYM_ENQ_THRESHOLD_NAME "qat_sym_enq_threshold"
#define ASYM_ENQ_THRESHOLD_NAME "qat_asym_enq_threshold"
#define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
#define SYM_CIPHER_CRC_ENABLE_NAME "qat_sym_cipher_crc_enable"
#define QAT_CMD_SLICE_MAP "qat_cmd_slice_disable"
#define QAT_CMD_SLICE_MAP_POS 5
#define MAX_QP_THRESHOLD_SIZE 32
/**
error: patch failed: drivers/common/qat/qat_device.h:17
Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c...
Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c...
Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c...
Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c...
Checking patch drivers/crypto/qat/qat_asym.c...
Checking patch drivers/crypto/qat/qat_crypto.h...
Checking patch drivers/crypto/qat/qat_sym.c...
Hunk #2 succeeded at 282 (offset -4 lines).
Applied patch app/test/test_cryptodev_asym.c cleanly.
Applying patch doc/guides/cryptodevs/qat.rst with 1 reject...
Rejected hunk #1.
Applied patch drivers/common/qat/qat_device.c cleanly.
Applying patch drivers/common/qat/qat_device.h with 1 reject...
Rejected hunk #1.
Applied patch drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c cleanly.
Applied patch drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c cleanly.
Applied patch drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c cleanly.
Applied patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c cleanly.
Applied patch drivers/crypto/qat/qat_asym.c cleanly.
Applied patch drivers/crypto/qat/qat_crypto.h cleanly.
Applied patch drivers/crypto/qat/qat_sym.c cleanly.
hint: Use 'git am --show-current-patch' to see the failed patch
diff a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst (rejected hunks)
@@ -314,7 +314,21 @@ If not supported, the CRC is calculated by the QAT PMD using the NET CRC API.
To use this feature the user must set the devarg on process start as a device additional devarg::
- -a 03:01.1,qat_sym_cipher_crc_enable=1
+ -a 03:01.1,qat_sym_cipher_crc_enable=1
+
+
+Running QAT PMD with insecure crypto algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A few insecure crypto algorithms are deprecated from QAT drivers. This needs to be reflected in DPDK QAT PMD.
+DPDK QAT PMD has by default disabled all the insecure crypto algorithms from Gen 1,2,3 and 4.
+A PMD parameter is used to enable the capability.
+
+- qat_legacy_capa
+
+To use this feature the user must set the parameter on process start as a device additional parameter::
+
+ -a b1:01.2,qat_legacy_capa=1
Running QAT PMD with Intel IPSEC MB library for symmetric precomputes function
diff a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h (rejected hunks)
@@ -17,13 +17,14 @@
#define QAT_DEV_NAME_MAX_LEN 64
+#define QAT_LEGACY_CAPA "qat_legacy_capa"
#define QAT_IPSEC_MB_LIB "qat_ipsec_mb_lib"
#define SYM_ENQ_THRESHOLD_NAME "qat_sym_enq_threshold"
#define ASYM_ENQ_THRESHOLD_NAME "qat_asym_enq_threshold"
#define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
#define SYM_CIPHER_CRC_ENABLE_NAME "qat_sym_cipher_crc_enable"
#define QAT_CMD_SLICE_MAP "qat_cmd_slice_disable"
-#define QAT_CMD_SLICE_MAP_POS 5
+#define QAT_CMD_SLICE_MAP_POS 6
#define MAX_QP_THRESHOLD_SIZE 32
/**
https://lab.dpdk.org/results/dashboard/patchsets/26406/
UNH-IOL DPDK Community Lab
reply other threads:[~2023-05-26 7:40 UTC|newest]
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