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From: Nicolas Chautru <nicolas.chautru@intel.com>
To: dev@dpdk.org, thomas@monjalon.net, gakhil@marvell.com,
	hemant.agrawal@nxp.com, trix@redhat.com
Cc: maxime.coquelin@redhat.com, mdr@ashroe.eu,
	bruce.richardson@intel.com, david.marchand@redhat.com,
	stephen@networkplumber.org,
	Nicolas Chautru <nicolas.chautru@intel.com>
Subject: [PATCH v1 08/10] baseband/acc200: support interrupt
Date: Thu,  7 Jul 2022 17:01:41 -0700	[thread overview]
Message-ID: <1657238503-143836-9-git-send-email-nicolas.chautru@intel.com> (raw)
In-Reply-To: <1657238503-143836-1-git-send-email-nicolas.chautru@intel.com>

Adding support for capability and functions for
MSI/MSI-X interript and underlying information ring.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/acc200/rte_acc200_pmd.c | 370 ++++++++++++++++++++++++++++++-
 1 file changed, 368 insertions(+), 2 deletions(-)

diff --git a/drivers/baseband/acc200/rte_acc200_pmd.c b/drivers/baseband/acc200/rte_acc200_pmd.c
index 36c5561..ecfbc7a 100644
--- a/drivers/baseband/acc200/rte_acc200_pmd.c
+++ b/drivers/baseband/acc200/rte_acc200_pmd.c
@@ -363,6 +363,217 @@
 	free_base_addresses(base_addrs, i);
 }
 
+/*
+ * Find queue_id of a device queue based on details from the Info Ring.
+ * If a queue isn't found UINT16_MAX is returned.
+ */
+static inline uint16_t
+get_queue_id_from_ring_info(struct rte_bbdev_data *data,
+		const union acc200_info_ring_data ring_data)
+{
+	uint16_t queue_id;
+
+	for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
+		struct acc200_queue *acc200_q =
+				data->queues[queue_id].queue_private;
+		if (acc200_q != NULL && acc200_q->aq_id == ring_data.aq_id &&
+				acc200_q->qgrp_id == ring_data.qg_id &&
+				acc200_q->vf_id == ring_data.vf_id)
+			return queue_id;
+	}
+
+	return UINT16_MAX;
+}
+
+/* Checks PF Info Ring to find the interrupt cause and handles it accordingly */
+static inline void
+acc200_check_ir(struct acc200_device *acc200_dev)
+{
+	volatile union acc200_info_ring_data *ring_data;
+	uint16_t info_ring_head = acc200_dev->info_ring_head;
+	if (acc200_dev->info_ring == NULL)
+		return;
+
+	ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head &
+			ACC200_INFO_RING_MASK);
+
+	while (ring_data->valid) {
+		if ((ring_data->int_nb < ACC200_PF_INT_DMA_DL_DESC_IRQ) || (
+				ring_data->int_nb >
+				ACC200_PF_INT_DMA_DL5G_DESC_IRQ)) {
+			rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x",
+				ring_data->int_nb, ring_data->detailed_info);
+			/* Initialize Info Ring entry and move forward */
+			ring_data->val = 0;
+		}
+		info_ring_head++;
+		ring_data = acc200_dev->info_ring +
+				(info_ring_head & ACC200_INFO_RING_MASK);
+	}
+}
+
+/* Checks PF Info Ring to find the interrupt cause and handles it accordingly */
+static inline void
+acc200_pf_interrupt_handler(struct rte_bbdev *dev)
+{
+	struct acc200_device *acc200_dev = dev->data->dev_private;
+	volatile union acc200_info_ring_data *ring_data;
+	struct acc200_deq_intr_details deq_intr_det;
+
+	ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head &
+			ACC200_INFO_RING_MASK);
+
+	while (ring_data->valid) {
+
+		rte_bbdev_log_debug(
+				"ACC200 PF Interrupt received, Info Ring data: 0x%x -> %d",
+				ring_data->val, ring_data->int_nb);
+
+		switch (ring_data->int_nb) {
+		case ACC200_PF_INT_DMA_DL_DESC_IRQ:
+		case ACC200_PF_INT_DMA_UL_DESC_IRQ:
+		case ACC200_PF_INT_DMA_FFT_DESC_IRQ:
+		case ACC200_PF_INT_DMA_UL5G_DESC_IRQ:
+		case ACC200_PF_INT_DMA_DL5G_DESC_IRQ:
+			deq_intr_det.queue_id = get_queue_id_from_ring_info(
+					dev->data, *ring_data);
+			if (deq_intr_det.queue_id == UINT16_MAX) {
+				rte_bbdev_log(ERR,
+						"Couldn't find queue: aq_id: %u, qg_id: %u, vf_id: %u",
+						ring_data->aq_id,
+						ring_data->qg_id,
+						ring_data->vf_id);
+				return;
+			}
+			rte_bbdev_pmd_callback_process(dev,
+					RTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);
+			break;
+		default:
+			rte_bbdev_pmd_callback_process(dev,
+					RTE_BBDEV_EVENT_ERROR, NULL);
+			break;
+		}
+
+		/* Initialize Info Ring entry and move forward */
+		ring_data->val = 0;
+		++acc200_dev->info_ring_head;
+		ring_data = acc200_dev->info_ring +
+				(acc200_dev->info_ring_head &
+				ACC200_INFO_RING_MASK);
+	}
+}
+
+/* Checks VF Info Ring to find the interrupt cause and handles it accordingly */
+static inline void
+acc200_vf_interrupt_handler(struct rte_bbdev *dev)
+{
+	struct acc200_device *acc200_dev = dev->data->dev_private;
+	volatile union acc200_info_ring_data *ring_data;
+	struct acc200_deq_intr_details deq_intr_det;
+
+	ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head &
+			ACC200_INFO_RING_MASK);
+
+	while (ring_data->valid) {
+
+		rte_bbdev_log_debug(
+				"ACC200 VF Interrupt received, Info Ring data: 0x%x\n",
+				ring_data->val);
+
+		switch (ring_data->int_nb) {
+		case ACC200_VF_INT_DMA_DL_DESC_IRQ:
+		case ACC200_VF_INT_DMA_UL_DESC_IRQ:
+		case ACC200_VF_INT_DMA_FFT_DESC_IRQ:
+		case ACC200_VF_INT_DMA_UL5G_DESC_IRQ:
+		case ACC200_VF_INT_DMA_DL5G_DESC_IRQ:
+			/* VFs are not aware of their vf_id - it's set to 0 in
+			 * queue structures.
+			 */
+			ring_data->vf_id = 0;
+			deq_intr_det.queue_id = get_queue_id_from_ring_info(
+					dev->data, *ring_data);
+			if (deq_intr_det.queue_id == UINT16_MAX) {
+				rte_bbdev_log(ERR,
+						"Couldn't find queue: aq_id: %u, qg_id: %u",
+						ring_data->aq_id,
+						ring_data->qg_id);
+				return;
+			}
+			rte_bbdev_pmd_callback_process(dev,
+					RTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);
+			break;
+		default:
+			rte_bbdev_pmd_callback_process(dev,
+					RTE_BBDEV_EVENT_ERROR, NULL);
+			break;
+		}
+
+		/* Initialize Info Ring entry and move forward */
+		ring_data->valid = 0;
+		++acc200_dev->info_ring_head;
+		ring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head
+				& ACC200_INFO_RING_MASK);
+	}
+}
+
+/* Interrupt handler triggered by ACC200 dev for handling specific interrupt */
+static void
+acc200_dev_interrupt_handler(void *cb_arg)
+{
+	struct rte_bbdev *dev = cb_arg;
+	struct acc200_device *acc200_dev = dev->data->dev_private;
+
+	/* Read info ring */
+	if (acc200_dev->pf_device)
+		acc200_pf_interrupt_handler(dev);
+	else
+		acc200_vf_interrupt_handler(dev);
+}
+
+/* Allocate and setup inforing */
+static int
+allocate_info_ring(struct rte_bbdev *dev)
+{
+	struct acc200_device *d = dev->data->dev_private;
+	const struct acc200_registry_addr *reg_addr;
+	rte_iova_t info_ring_iova;
+	uint32_t phys_low, phys_high;
+
+	if (d->info_ring != NULL)
+		return 0; /* Already configured */
+
+	/* Choose correct registry addresses for the device type */
+	if (d->pf_device)
+		reg_addr = &pf_reg_addr;
+	else
+		reg_addr = &vf_reg_addr;
+	/* Allocate InfoRing */
+	if (d->info_ring == NULL)
+		d->info_ring = rte_zmalloc_socket("Info Ring",
+				ACC200_INFO_RING_NUM_ENTRIES *
+				sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE,
+				dev->data->socket_id);
+	if (d->info_ring == NULL) {
+		rte_bbdev_log(ERR,
+				"Failed to allocate Info Ring for %s:%u",
+				dev->device->driver->name,
+				dev->data->dev_id);
+		return -ENOMEM;
+	}
+	info_ring_iova = rte_malloc_virt2iova(d->info_ring);
+
+	/* Setup Info Ring */
+	phys_high = (uint32_t)(info_ring_iova >> 32);
+	phys_low  = (uint32_t)(info_ring_iova);
+	acc200_reg_write(d, reg_addr->info_ring_hi, phys_high);
+	acc200_reg_write(d, reg_addr->info_ring_lo, phys_low);
+	acc200_reg_write(d, reg_addr->info_ring_en, ACC200_REG_IRQ_EN_ALL);
+	d->info_ring_head = (acc200_reg_read(d, reg_addr->info_ring_ptr) &
+			0xFFF) / sizeof(union acc200_info_ring_data);
+	return 0;
+}
+
+
 /* Allocate 64MB memory used for all software rings */
 static int
 acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
@@ -370,6 +581,7 @@
 	uint32_t phys_low, phys_high, value;
 	struct acc200_device *d = dev->data->dev_private;
 	const struct acc200_registry_addr *reg_addr;
+	int ret;
 
 	if (d->pf_device && !d->acc200_conf.pf_mode_en) {
 		rte_bbdev_log(NOTICE,
@@ -470,6 +682,14 @@
 	acc200_reg_write(d, reg_addr->tail_ptrs_fft_hi, phys_high);
 	acc200_reg_write(d, reg_addr->tail_ptrs_fft_lo, phys_low);
 
+	ret = allocate_info_ring(dev);
+	if (ret < 0) {
+		rte_bbdev_log(ERR, "Failed to allocate info_ring for %s:%u",
+				dev->device->driver->name,
+				dev->data->dev_id);
+		/* Continue */
+	}
+
 	if (d->harq_layout == NULL)
 		d->harq_layout = rte_zmalloc_socket("HARQ Layout",
 				ACC200_HARQ_LAYOUT * sizeof(*d->harq_layout),
@@ -492,17 +712,121 @@
 	return 0;
 }
 
+static int
+acc200_intr_enable(struct rte_bbdev *dev)
+{
+	int ret;
+	struct acc200_device *d = dev->data->dev_private;
+	/*
+	 * MSI/MSI-X are supported
+	 * Option controlled by vfio-intr through EAL parameter
+	 */
+	if (rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_VFIO_MSI) {
+
+		ret = allocate_info_ring(dev);
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't allocate info ring for device: %s",
+					dev->data->name);
+			return ret;
+		}
+		ret = rte_intr_enable(dev->intr_handle);
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't enable interrupts for device: %s",
+					dev->data->name);
+			rte_free(d->info_ring);
+			return ret;
+		}
+		ret = rte_intr_callback_register(dev->intr_handle,
+				acc200_dev_interrupt_handler, dev);
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't register interrupt callback for device: %s",
+					dev->data->name);
+			rte_free(d->info_ring);
+			return ret;
+		}
+
+		return 0;
+	} else if (rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_VFIO_MSIX) {
+
+		ret = allocate_info_ring(dev);
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't allocate info ring for device: %s",
+					dev->data->name);
+			return ret;
+		}
+
+		int i, max_queues;
+		struct acc200_device *acc200_dev = dev->data->dev_private;
+
+		if (acc200_dev->pf_device)
+			max_queues = ACC200_MAX_PF_MSIX;
+		else
+			max_queues = ACC200_MAX_VF_MSIX;
+
+		if (rte_intr_efd_enable(dev->intr_handle, max_queues)) {
+			rte_bbdev_log(ERR, "Failed to create fds for %u queues",
+					dev->data->num_queues);
+			return -1;
+		}
+
+		for (i = 0; i < max_queues; ++i) {
+			if (rte_intr_efds_index_set(dev->intr_handle, i,
+					rte_intr_fd_get(dev->intr_handle)))
+				return -rte_errno;
+		}
+
+		if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+				dev->data->num_queues)) {
+			rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+					dev->data->num_queues);
+			return -ENOMEM;
+		}
+
+		ret = rte_intr_enable(dev->intr_handle);
+
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't enable interrupts for device: %s",
+					dev->data->name);
+			rte_free(d->info_ring);
+			return ret;
+		}
+		ret = rte_intr_callback_register(dev->intr_handle,
+				acc200_dev_interrupt_handler, dev);
+		if (ret < 0) {
+			rte_bbdev_log(ERR,
+					"Couldn't register interrupt callback for device: %s",
+					dev->data->name);
+			rte_free(d->info_ring);
+			return ret;
+		}
+
+		return 0;
+	}
+
+	rte_bbdev_log(ERR, "ACC200 (%s) supports only VFIO MSI/MSI-X interrupts\n",
+			dev->data->name);
+	return -ENOTSUP;
+}
+
 /* Free memory used for software rings */
 static int
 acc200_dev_close(struct rte_bbdev *dev)
 {
 	struct acc200_device *d = dev->data->dev_private;
+	acc200_check_ir(d);
 	if (d->sw_rings_base != NULL) {
 		rte_free(d->tail_ptrs);
+		rte_free(d->info_ring);
 		rte_free(d->sw_rings_base);
 		rte_free(d->harq_layout);
 		d->sw_rings_base = NULL;
 		d->tail_ptrs = NULL;
+		d->info_ring = NULL;
 		d->harq_layout = NULL;
 	}
 	/* Ensure all in flight HW transactions are completed */
@@ -795,6 +1119,7 @@
 					RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH |
 					RTE_BBDEV_TURBO_SOFT_OUTPUT |
 					RTE_BBDEV_TURBO_EARLY_TERMINATION |
+					RTE_BBDEV_TURBO_DEC_INTERRUPTS |
 					RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |
 					RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT |
 					RTE_BBDEV_TURBO_MAP_DEC |
@@ -816,6 +1141,7 @@
 					RTE_BBDEV_TURBO_CRC_24B_ATTACH |
 					RTE_BBDEV_TURBO_RV_INDEX_BYPASS |
 					RTE_BBDEV_TURBO_RATE_MATCH |
+					RTE_BBDEV_TURBO_ENC_INTERRUPTS |
 					RTE_BBDEV_TURBO_ENC_SCATTER_GATHER,
 				.num_buffers_src =
 						RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
@@ -829,7 +1155,8 @@
 				.capability_flags =
 					RTE_BBDEV_LDPC_RATE_MATCH |
 					RTE_BBDEV_LDPC_CRC_24B_ATTACH |
-					RTE_BBDEV_LDPC_INTERLEAVER_BYPASS,
+					RTE_BBDEV_LDPC_INTERLEAVER_BYPASS |
+					RTE_BBDEV_LDPC_ENC_INTERRUPTS,
 				.num_buffers_src =
 						RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 				.num_buffers_dst =
@@ -850,7 +1177,8 @@
 				RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS |
 				RTE_BBDEV_LDPC_DEC_SCATTER_GATHER |
 				RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION |
-				RTE_BBDEV_LDPC_LLR_COMPRESSION,
+				RTE_BBDEV_LDPC_LLR_COMPRESSION |
+				RTE_BBDEV_LDPC_DEC_INTERRUPTS,
 			.llr_size = 8,
 			.llr_decimals = 1,
 			.num_buffers_src =
@@ -918,15 +1246,46 @@
 	dev_info->min_alignment = 1;
 	dev_info->capabilities = bbdev_capabilities;
 	dev_info->harq_buffer_size = 0;
+
+	acc200_check_ir(d);
+}
+
+static int
+acc200_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct acc200_queue *q = dev->data->queues[queue_id].queue_private;
+
+	if (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&
+			rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)
+		return -ENOTSUP;
+
+	q->irq_enable = 1;
+	return 0;
+}
+
+static int
+acc200_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct acc200_queue *q = dev->data->queues[queue_id].queue_private;
+
+	if (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&
+			rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)
+		return -ENOTSUP;
+
+	q->irq_enable = 0;
+	return 0;
 }
 
 static const struct rte_bbdev_ops acc200_bbdev_ops = {
 	.setup_queues = acc200_setup_queues,
+	.intr_enable = acc200_intr_enable,
 	.close = acc200_dev_close,
 	.info_get = acc200_dev_info_get,
 	.queue_setup = acc200_queue_setup,
 	.queue_release = acc200_queue_release,
 	.queue_stop = acc200_queue_stop,
+	.queue_intr_enable = acc200_queue_intr_enable,
+	.queue_intr_disable = acc200_queue_intr_disable
 };
 
 /* ACC200 PCI PF address map */
@@ -3821,6 +4180,7 @@ static inline uint32_t hq_index(uint32_t offset)
 	if (op->status != 0) {
 		/* These errors are not expected */
 		q_data->queue_stats.dequeue_err_count++;
+		acc200_check_ir(q->d);
 	}
 
 	/* CRC invalid if error exists */
@@ -3890,6 +4250,9 @@ static inline uint32_t hq_index(uint32_t offset)
 
 	op->ldpc_dec.iter_count = (uint8_t) rsp.iter_cnt;
 
+	if (op->status & (1 << RTE_BBDEV_DRV_ERROR))
+		acc200_check_ir(q->d);
+
 	/* Check if this is the last desc in batch (Atomic Queue) */
 	if (desc->req.last_desc_in_batch) {
 		(*aq_dequeued)++;
@@ -4365,6 +4728,9 @@ static inline uint32_t hq_index(uint32_t offset)
 	if (op->status != 0)
 		q_data->queue_stats.dequeue_err_count++;
 
+	if (op->status & (1 << RTE_BBDEV_DRV_ERROR))
+		acc200_check_ir(q->d);
+
 	/* Check if this is the last desc in batch (Atomic Queue) */
 	if (desc->req.last_desc_in_batch) {
 		(*aq_dequeued)++;
-- 
1.8.3.1


  parent reply	other threads:[~2022-07-08  0:17 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-08  0:01 [PATCH v1 00/10] baseband/acc200 Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 01/10] baseband/acc200: introduce PMD for ACC200 Nicolas Chautru
2022-09-12  1:08   ` [PATCH v2 00/11] baseband/acc200 Nic Chautru
2022-09-12  1:08     ` [PATCH v2 01/11] baseband/acc100: refactory to segregate common code Nic Chautru
2022-09-12 15:19       ` Bruce Richardson
2022-09-12  1:08     ` [PATCH v2 02/11] baseband/acc200: introduce PMD for ACC200 Nic Chautru
2022-09-12 15:41       ` Bruce Richardson
2022-09-12  1:08     ` [PATCH v2 03/11] baseband/acc200: add HW register definitions Nic Chautru
2022-09-12  1:08     ` [PATCH v2 04/11] baseband/acc200: add info get function Nic Chautru
2022-09-12  1:08     ` [PATCH v2 05/11] baseband/acc200: add queue configuration Nic Chautru
2022-09-12  1:08     ` [PATCH v2 06/11] baseband/acc200: add LDPC processing functions Nic Chautru
2022-09-12  1:08     ` [PATCH v2 07/11] baseband/acc200: add LTE " Nic Chautru
2022-09-12  1:08     ` [PATCH v2 08/11] baseband/acc200: add support for FFT operations Nic Chautru
2022-09-12  1:08     ` [PATCH v2 09/11] baseband/acc200: support interrupt Nic Chautru
2022-09-12  1:08     ` [PATCH v2 10/11] baseband/acc200: add device status and vf2pf comms Nic Chautru
2022-09-12  1:08     ` [PATCH v2 11/11] baseband/acc200: add PF configure companion function Nic Chautru
2022-07-08  0:01 ` [PATCH v1 02/10] baseband/acc200: add HW register definitions Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 03/10] baseband/acc200: add info get function Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 04/10] baseband/acc200: add queue configuration Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 05/10] baseband/acc200: add LDPC processing functions Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 06/10] baseband/acc200: add LTE " Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 07/10] baseband/acc200: add support for FFT operations Nicolas Chautru
2022-07-08  0:01 ` Nicolas Chautru [this message]
2022-07-08  0:01 ` [PATCH v1 09/10] baseband/acc200: add device status and vf2pf comms Nicolas Chautru
2022-07-08  0:01 ` [PATCH v1 10/10] baseband/acc200: add PF configure companion function Nicolas Chautru
2022-07-12 13:48 ` [PATCH v1 00/10] baseband/acc200 Maxime Coquelin
2022-07-14 18:49   ` Vargas, Hernan
2022-07-17 13:08     ` Tom Rix
2022-07-22 18:29       ` Vargas, Hernan
2022-07-22 20:19         ` Tom Rix
2022-08-15 17:52           ` Chautru, Nicolas
2022-08-30  7:44   ` Maxime Coquelin
2022-08-30 19:45     ` Chautru, Nicolas
2022-08-31 16:43       ` Maxime Coquelin
2022-08-31 19:20         ` Thomas Monjalon
2022-08-31 19:26       ` Tom Rix
2022-08-31 22:37         ` Chautru, Nicolas
2022-09-01  0:28           ` Tom Rix
2022-09-01  1:26             ` Chautru, Nicolas
2022-09-01 13:49               ` Tom Rix
2022-09-01 20:34                 ` Chautru, Nicolas
2022-09-06 12:51                   ` Tom Rix
2022-09-14 10:35                     ` Thomas Monjalon
2022-09-14 11:50                       ` Maxime Coquelin
2022-09-14 13:19                         ` Bruce Richardson
2022-09-14 13:27                           ` Maxime Coquelin
2022-09-14 13:44                           ` [EXT] " Akhil Goyal
2022-09-14 14:23                             ` Thomas Monjalon
2022-09-14 19:57                               ` Chautru, Nicolas
2022-09-14 20:08                                 ` Maxime Coquelin

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