* [dpdk-dev] [PATCH 1/3] common/mlx5: fix relaxed ordering support detection
2020-05-12 12:21 [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Shiri Kuzin
@ 2020-05-12 12:21 ` Shiri Kuzin
2020-05-12 12:21 ` [dpdk-dev] [PATCH 2/3] common/mlx5: fix relaxed ordering count object Shiri Kuzin
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Shiri Kuzin @ 2020-05-12 12:21 UTC (permalink / raw)
To: dev; +Cc: matan, viacheslavo
Relaxed ordering is a PCI optimization that allows reordering
of reads/writes in order to improve performance.
In order to enable this optimization only when relaxed ordering
is supported, it is checked if IBV_ACCESS_RELAXED_ORDERING is
defined in verbs.h.
Since IBV_ACCESS_RELAXED_ORDERING is an enum and not
defined relaxed ordering wasn't enabled even when supported.
This issue is fixed by using AUTOCONF to check if relaxed
ordering is supported and disabling only if it isn't.
Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
---
drivers/common/mlx5/Makefile | 5 +++++
drivers/common/mlx5/meson.build | 2 ++
drivers/common/mlx5/mlx5_glue.h | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/Makefile b/drivers/common/mlx5/Makefile
index 8b663ef..0d8cc1b 100644
--- a/drivers/common/mlx5/Makefile
+++ b/drivers/common/mlx5/Makefile
@@ -68,6 +68,11 @@ mlx5_autoconf.h.new: FORCE
mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh
$Q $(RM) -f -- '$@'
$Q sh -- '$<' '$@' \
+ HAVE_IBV_RELAXED_ORDERING \
+ infiniband/verbs.h \
+ enum IBV_ACCESS_RELAXED_ORDERING \
+ $(AUTOCONF_OUTPUT)
+ $Q sh -- '$<' '$@' \
HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT \
infiniband/mlx5dv.h \
enum MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX \
diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build
index 165aa25..5a802ba 100644
--- a/drivers/common/mlx5/meson.build
+++ b/drivers/common/mlx5/meson.build
@@ -94,6 +94,8 @@ has_member_args = [
# [ "MACRO to define if found", "header for the search",
# "symbol to search" ]
has_sym_args = [
+ [ 'HAVE_IBV_RELAXED_ORDERING', 'infiniband/verbs.h',
+ 'IBV_ACCESS_RELAXED_ORDERING ' ],
[ 'HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT', 'infiniband/mlx5dv.h',
'MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX' ],
[ 'HAVE_IBV_DEVICE_TUNNEL_SUPPORT', 'infiniband/mlx5dv.h',
diff --git a/drivers/common/mlx5/mlx5_glue.h b/drivers/common/mlx5/mlx5_glue.h
index 184c410..81d6a22 100644
--- a/drivers/common/mlx5/mlx5_glue.h
+++ b/drivers/common/mlx5/mlx5_glue.h
@@ -98,7 +98,7 @@
uint64_t comp_mask; };
#endif
-#ifndef IBV_ACCESS_RELAXED_ORDERING
+#ifndef HAVE_IBV_RELAXED_ORDERING
#define IBV_ACCESS_RELAXED_ORDERING 0
#endif
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-dev] [PATCH 2/3] common/mlx5: fix relaxed ordering count object
2020-05-12 12:21 [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Shiri Kuzin
2020-05-12 12:21 ` [dpdk-dev] [PATCH 1/3] common/mlx5: fix relaxed ordering support detection Shiri Kuzin
@ 2020-05-12 12:21 ` Shiri Kuzin
2020-05-12 12:21 ` [dpdk-dev] [PATCH 3/3] common/mlx5: disable relaxed ordering in unsuitable cpus Shiri Kuzin
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Shiri Kuzin @ 2020-05-12 12:21 UTC (permalink / raw)
To: dev; +Cc: matan, viacheslavo
In order to improve performance relaxed ordering was enabled
when creating count object using Devx.
Currently rte enables this optimization by default when using
Devx.
This causes an issue when using firmware that does not have this
capability causing a count object failure.
In order to fix this issue a check of firmware capabilities was
added before enabling relaxed ordering.
Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++++
drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/mlx5_flow_dv.c | 8 +++++---
4 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 230ac58..fba485e 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -451,6 +451,10 @@ struct mlx5_devx_obj *
attr->log_max_hairpin_num_packets = MLX5_GET
(cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
+ attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
+ relaxed_ordering_write);
+ attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
+ relaxed_ordering_read);
attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
eth_net_offloads);
attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index ac10687..49b174a 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -100,6 +100,8 @@ struct mlx5_hca_attr {
uint32_t log_max_hairpin_wq_data_sz:5;
uint32_t log_max_hairpin_num_packets:5;
uint32_t vhca_id:16;
+ uint32_t relaxed_ordering_write:1;
+ uint32_t relaxed_ordering_read:1;
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
};
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 4ab1c75..6212085 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -999,7 +999,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_d0[0xb];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
- u8 reserved_at_e8[0x2];
+ u8 relaxed_ordering_write[0x1];
+ u8 relaxed_ordering_read[0x1];
u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 4ebb7ce..c7702c5 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4100,8 +4100,8 @@ struct field_modify_info modify_tcp[] = {
static struct mlx5_counter_stats_mem_mng *
flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
{
- struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
- (dev->data->dev_private))->sh;
+ struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_ibv_shared *sh = priv->sh;
struct mlx5_devx_mkey_attr mkey_attr;
struct mlx5_counter_stats_mem_mng *mem_mng;
volatile struct flow_counter_stats *raw_data;
@@ -4133,7 +4133,9 @@ struct field_modify_info modify_tcp[] = {
mkey_attr.pg_access = 0;
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
- mkey_attr.relaxed_ordering = 1;
+ if (priv->config.hca_attr.relaxed_ordering_write &&
+ priv->config.hca_attr.relaxed_ordering_read)
+ mkey_attr.relaxed_ordering = 1;
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
mlx5_glue->devx_umem_dereg(mem_mng->umem);
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-dev] [PATCH 3/3] common/mlx5: disable relaxed ordering in unsuitable cpus
2020-05-12 12:21 [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Shiri Kuzin
2020-05-12 12:21 ` [dpdk-dev] [PATCH 1/3] common/mlx5: fix relaxed ordering support detection Shiri Kuzin
2020-05-12 12:21 ` [dpdk-dev] [PATCH 2/3] common/mlx5: fix relaxed ordering count object Shiri Kuzin
@ 2020-05-12 12:21 ` Shiri Kuzin
2020-05-12 12:30 ` [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Matan Azrad
2020-05-13 10:36 ` Raslan Darawsheh
4 siblings, 0 replies; 6+ messages in thread
From: Shiri Kuzin @ 2020-05-12 12:21 UTC (permalink / raw)
To: dev; +Cc: matan, viacheslavo
Relaxed ordering is a PCI optimization that enables reordering
reads/writes in order to improve performance.
Relaxed ordering was enabled for all processors causing
a degradation in performance in Haswell and Broadwell processors
that don't support this optimization.
In order to avoid that we check if the processor is Haswell
or Broadwell and if so we disable relaxed ordering.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
---
drivers/common/mlx5/mlx5_common.c | 82 ++++++++++++++++++++++++++++++++++++
drivers/common/mlx5/mlx5_common.h | 2 +
drivers/common/mlx5/mlx5_common_mr.c | 6 ++-
drivers/net/mlx5/mlx5_flow_dv.c | 3 +-
4 files changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c
index 4261045..1c77763 100644
--- a/drivers/common/mlx5/mlx5_common.c
+++ b/drivers/common/mlx5/mlx5_common.c
@@ -22,6 +22,8 @@
const struct mlx5_glue *mlx5_glue;
#endif
+uint8_t haswell_broadwell_cpu;
+
/**
* Get PCI information by sysfs device path.
*
@@ -292,6 +294,29 @@ enum mlx5_class
#endif
+/* In case this is an x86_64 intel processor to check if
+ * we should use relaxed ordering.
+ */
+#ifdef RTE_ARCH_X86_64
+/**
+ * This function returns processor identification and feature information
+ * into the registers.
+ *
+ * @param eax, ebx, ecx, edx
+ * Pointers to the registers that will hold cpu information.
+ * @param level
+ * The main category of information returned.
+ */
+static inline void mlx5_cpu_id(unsigned int level,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ __asm__("cpuid\n\t"
+ : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "0" (level));
+}
+#endif
+
RTE_INIT_PRIO(mlx5_log_init, LOG)
{
mlx5_common_logtype = rte_log_register("pmd.common.mlx5");
@@ -350,3 +375,60 @@ enum mlx5_class
mlx5_glue = NULL;
return;
}
+
+/**
+ * This function is responsible of initializing the variable
+ * haswell_broadwell_cpu by checking if the cpu is intel
+ * and reading the data returned from mlx5_cpu_id().
+ * since haswell and broadwell cpus don't have improved performance
+ * when using relaxed ordering we want to check the cpu type before
+ * before deciding whether to enable RO or not.
+ * if the cpu is haswell or broadwell the variable will be set to 1
+ * otherwise it will be 0.
+ */
+RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
+{
+#ifdef RTE_ARCH_X86_64
+ unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
+ unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
+ unsigned int i, model, family, brand_id, vendor;
+ unsigned int signature_intel_ebx = 0x756e6547;
+ unsigned int extended_model;
+ unsigned int eax = 0;
+ unsigned int ebx = 0;
+ unsigned int ecx = 0;
+ unsigned int edx = 0;
+ int max_level;
+
+ mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
+ vendor = ebx;
+ max_level = eax;
+ if (max_level < 1) {
+ haswell_broadwell_cpu = 0;
+ return;
+ }
+ mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
+ model = (eax >> 4) & 0x0f;
+ family = (eax >> 8) & 0x0f;
+ brand_id = ebx & 0xff;
+ extended_model = (eax >> 12) & 0xf0;
+ /* Check if the processor is Haswell or Broadwell */
+ if (vendor == signature_intel_ebx) {
+ if (family == 0x06)
+ model += extended_model;
+ if (brand_id == 0 && family == 0x6) {
+ for (i = 0; i < RTE_DIM(broadwell_models); i++)
+ if (model == broadwell_models[i]) {
+ haswell_broadwell_cpu = 1;
+ return;
+ }
+ for (i = 0; i < RTE_DIM(haswell_models); i++)
+ if (model == haswell_models[i]) {
+ haswell_broadwell_cpu = 1;
+ return;
+ }
+ }
+ }
+#endif
+ haswell_broadwell_cpu = 0;
+}
diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index b37b820..8cd3ea5 100644
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -213,4 +213,6 @@ enum mlx5_class {
void mlx5_translate_port_name(const char *port_name_in,
struct mlx5_switch_info *port_info_out);
+extern uint8_t haswell_broadwell_cpu;
+
#endif /* RTE_PMD_MLX5_COMMON_H_ */
diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c
index 9d4a06d..3b46446 100644
--- a/drivers/common/mlx5/mlx5_common_mr.c
+++ b/drivers/common/mlx5/mlx5_common_mr.c
@@ -770,7 +770,8 @@ struct mlx5_mr *
*/
mr->ibv_mr = mlx5_glue->reg_mr(pd, (void *)data.start, len,
IBV_ACCESS_LOCAL_WRITE |
- IBV_ACCESS_RELAXED_ORDERING);
+ (haswell_broadwell_cpu ? 0 :
+ IBV_ACCESS_RELAXED_ORDERING));
if (mr->ibv_mr == NULL) {
DEBUG("Fail to create a verbs MR for address (%p)",
(void *)addr);
@@ -1045,7 +1046,8 @@ struct mlx5_mr *
return NULL;
mr->ibv_mr = mlx5_glue->reg_mr(pd, (void *)addr, len,
IBV_ACCESS_LOCAL_WRITE |
- IBV_ACCESS_RELAXED_ORDERING);
+ (haswell_broadwell_cpu ? 0 :
+ IBV_ACCESS_RELAXED_ORDERING));
if (mr->ibv_mr == NULL) {
DRV_LOG(WARNING,
"Fail to create a verbs MR for address (%p)",
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index c7702c5..8b018fb 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4134,7 +4134,8 @@ struct field_modify_info modify_tcp[] = {
mkey_attr.klm_array = NULL;
mkey_attr.klm_num = 0;
if (priv->config.hca_attr.relaxed_ordering_write &&
- priv->config.hca_attr.relaxed_ordering_read)
+ priv->config.hca_attr.relaxed_ordering_read &&
+ !haswell_broadwell_cpu)
mkey_attr.relaxed_ordering = 1;
mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
if (!mem_mng->dm) {
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes
2020-05-12 12:21 [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Shiri Kuzin
` (2 preceding siblings ...)
2020-05-12 12:21 ` [dpdk-dev] [PATCH 3/3] common/mlx5: disable relaxed ordering in unsuitable cpus Shiri Kuzin
@ 2020-05-12 12:30 ` Matan Azrad
2020-05-13 10:36 ` Raslan Darawsheh
4 siblings, 0 replies; 6+ messages in thread
From: Matan Azrad @ 2020-05-12 12:30 UTC (permalink / raw)
To: Shiri Kuzin, dev; +Cc: Slava Ovsiienko
From: Shiri Kuzin
> Fixed some bugs regarding relaxed ordering in mlx5.
>
> Shiri Kuzin (3):
> common/mlx5: fix relaxed ordering support detection
> common/mlx5: fix relaxed ordering count object
> common/mlx5: disable relaxed ordering in unsuitable cpus
Series-acked-by: Matan Azrad <matan@mellanox.com>
> drivers/common/mlx5/Makefile | 5 +++
> drivers/common/mlx5/meson.build | 2 +
> drivers/common/mlx5/mlx5_common.c | 82
> ++++++++++++++++++++++++++++++++++++
> drivers/common/mlx5/mlx5_common.h | 2 +
> drivers/common/mlx5/mlx5_common_mr.c | 6 ++-
> drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 2 +
> drivers/common/mlx5/mlx5_glue.h | 2 +-
> drivers/common/mlx5/mlx5_prm.h | 3 +-
> drivers/net/mlx5/mlx5_flow_dv.c | 9 ++--
> 10 files changed, 110 insertions(+), 7 deletions(-)
>
> --
> 1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes
2020-05-12 12:21 [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Shiri Kuzin
` (3 preceding siblings ...)
2020-05-12 12:30 ` [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes Matan Azrad
@ 2020-05-13 10:36 ` Raslan Darawsheh
4 siblings, 0 replies; 6+ messages in thread
From: Raslan Darawsheh @ 2020-05-13 10:36 UTC (permalink / raw)
To: Shiri Kuzin, dev; +Cc: Matan Azrad, Slava Ovsiienko
Hi,
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Shiri Kuzin
> Sent: Tuesday, May 12, 2020 3:22 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@mellanox.com>; Slava Ovsiienko
> <viacheslavo@mellanox.com>
> Subject: [dpdk-dev] [PATCH 0/3] mlx5: relaxed ordering fixes
>
> Fixed some bugs regarding relaxed ordering in mlx5.
>
> Shiri Kuzin (3):
> common/mlx5: fix relaxed ordering support detection
> common/mlx5: fix relaxed ordering count object
> common/mlx5: disable relaxed ordering in unsuitable cpus
>
> drivers/common/mlx5/Makefile | 5 +++
> drivers/common/mlx5/meson.build | 2 +
> drivers/common/mlx5/mlx5_common.c | 82
> ++++++++++++++++++++++++++++++++++++
> drivers/common/mlx5/mlx5_common.h | 2 +
> drivers/common/mlx5/mlx5_common_mr.c | 6 ++-
> drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 2 +
> drivers/common/mlx5/mlx5_glue.h | 2 +-
> drivers/common/mlx5/mlx5_prm.h | 3 +-
> drivers/net/mlx5/mlx5_flow_dv.c | 9 ++--
> 10 files changed, 110 insertions(+), 7 deletions(-)
>
> --
> 1.8.3.1
Series applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
^ permalink raw reply [flat|nested] 6+ messages in thread