* [dpdk-dev] [PATCH v2 0/8] update base code batch 3
@ 2020-07-01 5:49 Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Qi Zhang
` (9 more replies)
0 siblings, 10 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang
The patchset include couple bug fixes and code clean
also update the version number.
v2:
- add missing part in ice_rem_rss_cfg_sync in PATCH 1/8
- remove unnessary change in PATCH 1/8
Qi Zhang (8):
net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
net/ice/base: cleanup some code style
net/ice/base: move lldp function to common module
net/ice/base: code clean in FDIR module
net/ice/base: add capability list AQ function
net/ice/base: split capability parse into separate functions
net/ice/base: clear and free XLT entries on reset
net/ice/base: update version
drivers/net/ice/base/README | 2 +-
drivers/net/ice/base/ice_adminq_cmd.h | 6 +-
drivers/net/ice/base/ice_common.c | 588 ++++++++++++++++++++++++----------
drivers/net/ice/base/ice_common.h | 3 +
drivers/net/ice/base/ice_dcb.c | 33 --
drivers/net/ice/base/ice_dcb.h | 3 -
drivers/net/ice/base/ice_fdir.c | 23 +-
drivers/net/ice/base/ice_fdir.h | 3 -
drivers/net/ice/base/ice_flex_pipe.c | 4 +-
drivers/net/ice/base/ice_flow.c | 24 +-
drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
drivers/net/ice/base/ice_sched.c | 3 +-
12 files changed, 446 insertions(+), 247 deletions(-)
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 2/8] net/ice/base: cleanup some code style Qi Zhang
` (8 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, stable, Junfeng Guo
An IP header combined with GTP-U header should be regarded as
inner layer for RSS, otherwise it mess the field vector between
an IPv4 rule and IPv6 rule e.g:
testpmd> flow create 0 ingress patterh eth / ipv4 / udp / gtpu / \
gtpu_psc / ipv4 / udp / end actions rss types ipv4-udp end key_len \
0 queues end / end
testpmd> flow create 0 ingress patterh eth / ipv4 / udp / gtpu / \
gtpu_psc / ipv6 / udp / end actions rss types ipv6-udp end key_len \
0 queues end / end
Fixes: b7d34ccc47b5 ("net/ice/base: packet encapsulation for RSS")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
drivers/net/ice/base/ice_flow.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 6adcda844..180fe4466 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -3557,6 +3557,13 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (status)
goto exit;
+ /* don't do RSS for GTPU outer */
+ if (segs_cnt == ICE_RSS_OUTER_HEADERS &&
+ (segs[segs_cnt - 1].hdrs & ICE_FLOW_SEG_HDR_GTPU)) {
+ printf("ignore gtpu\n");
+ return ICE_SUCCESS;
+ }
+
/* Search for a flow profile that has matching headers, hash fields
* and has the input VSI associated to it. If found, no further
* operations required and exit.
@@ -3673,6 +3680,7 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
ice_acquire_lock(&hw->rss_locks);
status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
ICE_RSS_OUTER_HEADERS, symm);
+
if (!status)
status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,
addl_hdrs, ICE_RSS_INNER_HEADERS,
@@ -3706,6 +3714,10 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (!segs)
return ICE_ERR_NO_MEMORY;
+ if (segs_cnt == ICE_RSS_OUTER_HEADERS &&
+ segs[segs_cnt - 1].hdrs & ICE_FLOW_SEG_HDR_GTPU)
+ return ICE_SUCCESS;
+
/* Construct the packet segment info from the hashed fields */
status = ice_flow_set_rss_seg_info(&segs[segs_cnt - 1], hashed_flds,
addl_hdrs);
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 2/8] net/ice/base: cleanup some code style
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 3/8] net/ice/base: move lldp function to common module Qi Zhang
` (7 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
Cleanup code style issue reported by kernel checkpatch.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 6 ++++--
drivers/net/ice/base/ice_common.c | 2 --
drivers/net/ice/base/ice_flow.c | 12 ++++++------
drivers/net/ice/base/ice_sched.c | 3 +--
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9ee5b4eb5..e17369f5e 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2794,8 +2794,10 @@ struct ice_aq_desc {
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;
- struct ice_aqc_set_health_status_config set_health_status_config;
- struct ice_aqc_get_supported_health_status_codes get_supported_health_status_codes;
+ struct ice_aqc_set_health_status_config
+ set_health_status_config;
+ struct ice_aqc_get_supported_health_status_codes
+ get_supported_health_status_codes;
struct ice_aqc_get_health_status get_health_status;
struct ice_aqc_clear_health_status clear_health_status;
} params;
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 1683daf28..21044b071 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -193,14 +193,12 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
pcaps->module_type[2]);
-
if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
sizeof(pi->phy.link_info.module_type),
ICE_NONDMA_TO_NONDMA);
-
}
return status;
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 180fe4466..d1b8a0534 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -805,16 +805,16 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
}
if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
(hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
- src = !i ?
- (const ice_bitmap_t *)ice_ptypes_ipv4_ofos_all :
- (const ice_bitmap_t *)ice_ptypes_ipv4_il;
+ src = i ?
+ (const ice_bitmap_t *)ice_ptypes_ipv4_il :
+ (const ice_bitmap_t *)ice_ptypes_ipv4_ofos_all;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
} else if ((hdrs & ICE_FLOW_SEG_HDR_IPV6) &&
(hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
- src = !i ?
- (const ice_bitmap_t *)ice_ptypes_ipv6_ofos_all :
- (const ice_bitmap_t *)ice_ptypes_ipv6_il;
+ src = i ?
+ (const ice_bitmap_t *)ice_ptypes_ipv6_il :
+ (const ice_bitmap_t *)ice_ptypes_ipv6_ofos_all;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
} else if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 91847110b..8ee4b708e 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -5334,7 +5334,7 @@ void ice_sched_replay_agg(struct ice_hw *hw)
ice_acquire_lock(&pi->sched_lock);
LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
- list_entry) {
+ list_entry)
/* replay aggregator (re-create aggregator node) */
if (!ice_cmp_bitmap(agg_info->tc_bitmap,
agg_info->replay_tc_bitmap,
@@ -5363,7 +5363,6 @@ void ice_sched_replay_agg(struct ice_hw *hw)
ice_info(hw, "Replay agg bw [id=%d] failed\n",
agg_info->agg_id);
}
- }
ice_release_lock(&pi->sched_lock);
}
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 3/8] net/ice/base: move lldp function to common module
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 2/8] net/ice/base: cleanup some code style Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module Qi Zhang
` (6 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, Dave Ertman, Paul M Stillwell Jr
To implement a FW workaround for LFC, a set_local_mib must be
performed after every link up event. For systems that do not
have DCB configured, we need to move the function
ice_aq_set_lldp_mib() from the DCB specific ice_dcb.c to
ice_common.c so that the driver always has access to this AQ
command.
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 33 +++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 +++
drivers/net/ice/base/ice_dcb.c | 33 ---------------------------------
drivers/net/ice/base/ice_dcb.h | 3 ---
4 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 21044b071..cab81e0fc 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4557,3 +4557,36 @@ bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
return false;
}
+
+/**
+ * ice_aq_set_lldp_mib - Set the LLDP MIB
+ * @hw: pointer to the HW struct
+ * @mib_type: Local, Remote or both Local and Remote MIBs
+ * @buf: pointer to the caller-supplied buffer to store the MIB block
+ * @buf_size: size of the buffer (in bytes)
+ * @cd: pointer to command details structure or NULL
+ *
+ * Set the LLDP MIB. (0x0A08)
+ */
+enum ice_status
+ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_lldp_set_local_mib *cmd;
+ struct ice_aq_desc desc;
+
+ cmd = &desc.params.lldp_set_mib;
+
+ if (buf_size == 0 || !buf)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
+
+ desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
+ desc.datalen = CPU_TO_LE16(buf_size);
+
+ cmd->type = mib_type;
+ cmd->length = CPU_TO_LE16(buf_size);
+
+ return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+}
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index cb41497bc..329d0b50f 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -220,4 +220,7 @@ void ice_print_rollback_msg(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
+enum ice_status
+ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 6bdec18c0..b9643b5ce 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -136,39 +136,6 @@ ice_aq_start_lldp(struct ice_hw *hw, bool persist, struct ice_sq_cd *cd)
}
/**
- * ice_aq_set_lldp_mib - Set the LLDP MIB
- * @hw: pointer to the HW struct
- * @mib_type: Local, Remote or both Local and Remote MIBs
- * @buf: pointer to the caller-supplied buffer to store the MIB block
- * @buf_size: size of the buffer (in bytes)
- * @cd: pointer to command details structure or NULL
- *
- * Set the LLDP MIB. (0x0A08)
- */
-enum ice_status
-ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
- struct ice_sq_cd *cd)
-{
- struct ice_aqc_lldp_set_local_mib *cmd;
- struct ice_aq_desc desc;
-
- cmd = &desc.params.lldp_set_mib;
-
- if (buf_size == 0 || !buf)
- return ICE_ERR_PARAM;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
-
- desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
- desc.datalen = CPU_TO_LE16(buf_size);
-
- cmd->type = mib_type;
- cmd->length = CPU_TO_LE16(buf_size);
-
- return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
-}
-
-/**
* ice_get_dcbx_status
* @hw: pointer to the HW struct
*
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 3ffeb864c..83b6e4d8f 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -183,9 +183,6 @@ ice_aq_get_lldp_mib(struct ice_hw *hw, u8 bridge_type, u8 mib_type, void *buf,
u16 buf_size, u16 *local_len, u16 *remote_len,
struct ice_sq_cd *cd);
enum ice_status
-ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
- struct ice_sq_cd *cd);
-enum ice_status
ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
struct ice_aqc_get_cee_dcb_cfg_resp *buff,
struct ice_sq_cd *cd);
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (2 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 3/8] net/ice/base: move lldp function to common module Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-02 4:20 ` Yang, Qiming
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 5/8] net/ice/base: add capability list AQ function Qi Zhang
` (5 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, Paul M Stillwell Jr
Remove unused macro and funciton.
Declare no external referenced function as static.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 23 +----------------------
drivers/net/ice/base/ice_fdir.h | 3 ---
2 files changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index c5a20632c..b1dc2afb7 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -597,7 +597,7 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
* ice_set_dflt_val_fd_desc
* @fd_fltr_ctx: pointer to fd filter descriptor
*/
-void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
+static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
{
fd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
fd_fltr_ctx->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;
@@ -1389,27 +1389,6 @@ bool ice_fdir_is_dup_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input)
}
/**
- * ice_clear_vsi_fd_table - admin command to clear FD table for a VSI
- * @hw: hardware data structure
- * @vsi_num: vsi_num (HW VSI num)
- *
- * Clears FD table entries by issuing admin command (direct, 0x0B06)
- * Must to pass valid vsi_num as returned by "AddVSI".
- */
-enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw, u16 vsi_num)
-{
- struct ice_aqc_clear_fd_table *cmd;
- struct ice_aq_desc desc;
-
- cmd = &desc.params.clear_fd_table;
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_fd_table);
- cmd->clear_type = CL_FD_VM_VF_TYPE_VSI_IDX;
-
- cmd->vsi_index = CPU_TO_LE16(vsi_num);
- return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
-}
-
-/**
* ice_clear_pf_fd_table - admin command to clear FD table for PF
* @hw: hardware data structure
*
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index 1f31debe6..ad3e11a5b 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -17,7 +17,6 @@
#define ICE_FDIR_TUN_PKT_OFF 50
#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF)
#define ICE_FDIR_BUF_FULL_MARGIN 10
-#define ICE_FDIR_BUF_HEAD_ROOM 32
/* macros for offsets into packets for flow director programming */
#define ICE_IPV4_SRC_ADDR_OFFSET 26
@@ -222,7 +221,6 @@ struct ice_fdir_base_pkt {
enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id);
enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id);
-void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx);
enum ice_status
ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
enum ice_status
@@ -231,7 +229,6 @@ enum ice_status
ice_alloc_fd_shrd_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
enum ice_status
ice_free_fd_shrd_item(struct ice_hw *hw, u16 cntr_id, u16 num_fltr);
-enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw, u16 vsi_num);
enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw);
void
ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 5/8] net/ice/base: add capability list AQ function
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (3 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 6/8] net/ice/base: split capability parse into separate functions Qi Zhang
` (4 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
The current implementation for reading device and function capabilities
from firmware, ice_aq_discover_caps, has potentially undesirable
side effects.
ice_aq_discover_caps calls ice_parse_caps, resulting in overwriting the
capabilities stored in the hw structure. This is ok during
initialization, but means that code which wants to read the capabilities
after initialization cannot use ice_aq_discover_caps without being
careful of the side effects.
Factor out the AQ command logic into a new ice_aq_list_caps function.
This will be used by the ice_aq_discover_caps function.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 62 +++++++++++++++++++++++++++++++--------
1 file changed, 50 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index cab81e0fc..33e29bc0e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2007,20 +2007,27 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
}
/**
- * ice_aq_discover_caps - query function/device capabilities
+ * ice_aq_list_caps - query function/device capabilities
* @hw: pointer to the HW struct
- * @buf: a virtual buffer to hold the capabilities
- * @buf_size: Size of the virtual buffer
- * @cap_count: cap count needed if AQ err==ENOMEM
- * @opc: capabilities type to discover - pass in the command opcode
+ * @buf: a buffer to hold the capabilities
+ * @buf_size: size of the buffer
+ * @cap_count: if not NULL, set to the number of capabilities reported
+ * @opc: capabilities type to discover, device or function
* @cd: pointer to command details structure or NULL
*
- * Get the function(0x000a)/device(0x000b) capabilities description from
- * the firmware.
+ * Get the function (0x000A) or device (0x000B) capabilities description from
+ * firmware and store it in the buffer.
+ *
+ * If the cap_count pointer is not NULL, then it is set to the number of
+ * capabilities firmware will report. Note that if the buffer size is too
+ * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
+ * cap_count will still be updated in this case. It is recommended that the
+ * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
+ * firmware could return) to avoid this.
*/
static enum ice_status
-ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
- enum ice_adminq_opc opc, struct ice_sq_cd *cd)
+ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
+ enum ice_adminq_opc opc, struct ice_sq_cd *cd)
{
struct ice_aqc_list_caps *cmd;
struct ice_aq_desc desc;
@@ -2033,12 +2040,43 @@ ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
return ICE_ERR_PARAM;
ice_fill_dflt_direct_cmd_desc(&desc, opc);
-
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (cap_count)
+ *cap_count = LE32_TO_CPU(cmd->count);
+
+ return status;
+}
+
+/**
+ * ice_aq_discover_caps - query function/device capabilities
+ * @hw: pointer to the HW struct
+ * @buf: a virtual buffer to hold the capabilities
+ * @buf_size: Size of the virtual buffer
+ * @cap_count: cap count needed if AQ err==ENOMEM
+ * @opc: capabilities type to discover - pass in the command opcode
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get the function(0x000a)/device(0x000b) capabilities description from
+ * the firmware.
+ *
+ * NOTE: this function has the side effect of updating the hw->dev_caps or
+ * hw->func_caps by way of calling ice_parse_caps.
+ */
+static enum ice_status
+ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
+ enum ice_adminq_opc opc, struct ice_sq_cd *cd)
+{
+ u32 local_cap_count = 0;
+ enum ice_status status;
+
+ status = ice_aq_list_caps(hw, buf, buf_size, &local_cap_count,
+ opc, cd);
if (!status)
- ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
+ ice_parse_caps(hw, buf, local_cap_count, opc);
else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
- *cap_count = LE32_TO_CPU(cmd->count);
+ *cap_count = local_cap_count;
+
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 6/8] net/ice/base: split capability parse into separate functions
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (4 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 5/8] net/ice/base: add capability list AQ function Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 7/8] net/ice/base: clear and free XLT entries on reset Qi Zhang
` (3 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
The ice_parse_caps function is used to convert the capability block data
coming from firmware into a structured format used by other parts of the
code.
The current implementation directly updates the hw->func_caps and
hw->dev_caps structures. It is directly called from within
ice_aq_discover_caps. This causes the discover_caps function to have the
side effect of modifying the hw capability structures, which is not
intuitive.
Split this function into ice_parse_dev_caps and ice_parse_func_caps.
These functions will take a pointer to the dev_caps and func_caps
respectively. Also create an ice_parse_common_caps for sharing the
capability logic that is common to device and function.
Doing so enables a future refactor to allow reading and parsing
capabilities into a local caps structure instead of modifying the
members of the hw structure directly.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 491 +++++++++++++++++++++++------------
drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
2 files changed, 332 insertions(+), 160 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 33e29bc0e..6168fb4f0 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1821,189 +1821,362 @@ static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
}
/**
- * ice_parse_caps - parse function/device capabilities
+ * ice_parse_common_caps - parse common device/function capabilities
* @hw: pointer to the HW struct
- * @buf: pointer to a buffer containing function/device capability records
- * @cap_count: number of capability records in the list
- * @opc: type of capabilities list to parse
+ * @caps: pointer to common capabilities structure
+ * @elem: the capability element to parse
+ * @prefix: message prefix for tracing capabilities
*
- * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
+ * Given a capability element, extract relevant details into the common
+ * capability structure.
+ *
+ * Returns: true if the capability matches one of the common capability ids,
+ * false otherwise.
+ */
+static bool
+ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
+ struct ice_aqc_list_caps_elem *elem, const char *prefix)
+{
+ u32 logical_id = LE32_TO_CPU(elem->logical_id);
+ u32 phys_id = LE32_TO_CPU(elem->phys_id);
+ u32 number = LE32_TO_CPU(elem->number);
+ u16 cap = LE16_TO_CPU(elem->cap);
+ bool found = true;
+
+ switch (cap) {
+ case ICE_AQC_CAPS_VALID_FUNCTIONS:
+ caps->valid_functions = number;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: valid_functions (bitmap) = %d\n", prefix,
+ caps->valid_functions);
+ break;
+ case ICE_AQC_CAPS_DCB:
+ caps->dcb = (number == 1);
+ caps->active_tc_bitmap = logical_id;
+ caps->maxtc = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: dcb = %d\n", prefix, caps->dcb);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: active_tc_bitmap = %d\n", prefix,
+ caps->active_tc_bitmap);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: maxtc = %d\n", prefix, caps->maxtc);
+ break;
+ case ICE_AQC_CAPS_RSS:
+ caps->rss_table_size = number;
+ caps->rss_table_entry_width = logical_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rss_table_size = %d\n", prefix,
+ caps->rss_table_size);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rss_table_entry_width = %d\n", prefix,
+ caps->rss_table_entry_width);
+ break;
+ case ICE_AQC_CAPS_RXQS:
+ caps->num_rxq = number;
+ caps->rxq_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_rxq = %d\n", prefix,
+ caps->num_rxq);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rxq_first_id = %d\n", prefix,
+ caps->rxq_first_id);
+ break;
+ case ICE_AQC_CAPS_TXQS:
+ caps->num_txq = number;
+ caps->txq_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_txq = %d\n", prefix,
+ caps->num_txq);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: txq_first_id = %d\n", prefix,
+ caps->txq_first_id);
+ break;
+ case ICE_AQC_CAPS_MSIX:
+ caps->num_msix_vectors = number;
+ caps->msix_vector_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_msix_vectors = %d\n", prefix,
+ caps->num_msix_vectors);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: msix_vector_first_id = %d\n", prefix,
+ caps->msix_vector_first_id);
+ break;
+ case ICE_AQC_CAPS_MAX_MTU:
+ caps->max_mtu = number;
+ ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
+ prefix, caps->max_mtu);
+ break;
+ default:
+ /* Not one of the recognized common capabilities */
+ found = false;
+ }
+
+ return found;
+}
+
+/**
+ * ice_recalc_port_limited_caps - Recalculate port limited capabilities
+ * @hw: pointer to the HW structure
+ * @caps: pointer to capabilities structure to fix
+ *
+ * Re-calculate the capabilities that are dependent on the number of physical
+ * ports; i.e. some features are not supported or function differently on
+ * devices with more than 4 ports.
*/
static void
-ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
- enum ice_adminq_opc opc)
+ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
{
- struct ice_aqc_list_caps_elem *cap_resp;
- struct ice_hw_func_caps *func_p = NULL;
- struct ice_hw_dev_caps *dev_p = NULL;
- struct ice_hw_common_caps *caps;
- char const *prefix;
- u32 i;
+ /* This assumes device capabilities are always scanned before function
+ * capabilities during the initialization flow.
+ */
+ if (hw->dev_caps.num_funcs > 4) {
+ /* Max 4 TCs per port */
+ caps->maxtc = 4;
+ ice_debug(hw, ICE_DBG_INIT,
+ "reducing maxtc to %d (based on #ports)\n",
+ caps->maxtc);
+ }
+}
- if (!buf)
- return;
+/**
+ * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_VSI.
+ */
+static void
+ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
+ LE32_TO_CPU(cap->number));
+ ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
+ func_p->guar_num_vsi);
+}
- cap_resp = (struct ice_aqc_list_caps_elem *)buf;
+/**
+ * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_FD.
+ */
+static void
+ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 reg_val, val;
- if (opc == ice_aqc_opc_list_dev_caps) {
- dev_p = &hw->dev_caps;
- caps = &dev_p->common_cap;
+ if (hw->dcf_enabled)
+ return;
+ reg_val = rd32(hw, GLQF_FD_SIZE);
+ val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
+ GLQF_FD_SIZE_FD_GSIZE_S;
+ func_p->fd_fltr_guar =
+ ice_get_num_per_func(hw, val);
+ val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
+ GLQF_FD_SIZE_FD_BSIZE_S;
+ func_p->fd_fltr_best_effort = val;
+
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: fd_fltr_guar = %d\n",
+ func_p->fd_fltr_guar);
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: fd_fltr_best_effort = %d\n",
+ func_p->fd_fltr_best_effort);
+}
- ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
+/**
+ * ice_parse_func_caps - Parse function capabilities
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @buf: buffer containing the function capability records
+ * @cap_count: the number of capabilities
+ *
+ * Helper function to parse function (0x000A) capabilities list. For
+ * capabilities shared between device and function, this relies on
+ * ice_parse_common_caps.
+ *
+ * Loop through the list of provided capabilities and extract the relevant
+ * data into the function capabilities structured.
+ */
+static void
+ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ void *buf, u32 cap_count)
+{
+ struct ice_aqc_list_caps_elem *cap_resp;
+ u32 i;
- prefix = "dev cap";
- } else if (opc == ice_aqc_opc_list_func_caps) {
- func_p = &hw->func_caps;
- caps = &func_p->common_cap;
+ cap_resp = (struct ice_aqc_list_caps_elem *)buf;
- ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
+ ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
- prefix = "func cap";
- } else {
- ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
- return;
- }
+ for (i = 0; i < cap_count; i++) {
+ u16 cap = LE16_TO_CPU(cap_resp[i].cap);
+ bool found;
- for (i = 0; caps && i < cap_count; i++, cap_resp++) {
- u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
- u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
- u32 number = LE32_TO_CPU(cap_resp->number);
- u16 cap = LE16_TO_CPU(cap_resp->cap);
+ found = ice_parse_common_caps(hw, &func_p->common_cap,
+ &cap_resp[i], "func caps");
switch (cap) {
- case ICE_AQC_CAPS_VALID_FUNCTIONS:
- caps->valid_functions = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: valid_functions (bitmap) = %d\n", prefix,
- caps->valid_functions);
-
- /* store func count for resource management purposes */
- if (dev_p)
- dev_p->num_funcs = ice_hweight32(number);
- break;
case ICE_AQC_CAPS_VSI:
- if (dev_p) {
- dev_p->num_vsi_allocd_to_host = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_vsi_allocd_to_host = %d\n",
- prefix,
- dev_p->num_vsi_allocd_to_host);
- } else if (func_p) {
- func_p->guar_num_vsi =
- ice_get_num_per_func(hw, ICE_MAX_VSI);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: guar_num_vsi (fw) = %d\n",
- prefix, number);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: guar_num_vsi = %d\n",
- prefix, func_p->guar_num_vsi);
- }
- break;
- case ICE_AQC_CAPS_DCB:
- caps->dcb = (number == 1);
- caps->active_tc_bitmap = logical_id;
- caps->maxtc = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: dcb = %d\n", prefix, caps->dcb);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: active_tc_bitmap = %d\n", prefix,
- caps->active_tc_bitmap);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: maxtc = %d\n", prefix, caps->maxtc);
- break;
- case ICE_AQC_CAPS_RSS:
- caps->rss_table_size = number;
- caps->rss_table_entry_width = logical_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rss_table_size = %d\n", prefix,
- caps->rss_table_size);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rss_table_entry_width = %d\n", prefix,
- caps->rss_table_entry_width);
+ ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_RXQS:
- caps->num_rxq = number;
- caps->rxq_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_rxq = %d\n", prefix,
- caps->num_rxq);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rxq_first_id = %d\n", prefix,
- caps->rxq_first_id);
+ case ICE_AQC_CAPS_FD:
+ ice_parse_fdir_func_caps(hw, func_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_TXQS:
- caps->num_txq = number;
- caps->txq_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_txq = %d\n", prefix,
- caps->num_txq);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: txq_first_id = %d\n", prefix,
- caps->txq_first_id);
+ default:
+ /* Don't list common capabilities as unknown */
+ if (!found)
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: unknown capability[%d]: 0x%x\n",
+ i, cap);
break;
- case ICE_AQC_CAPS_MSIX:
- caps->num_msix_vectors = number;
- caps->msix_vector_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_msix_vectors = %d\n", prefix,
- caps->num_msix_vectors);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: msix_vector_first_id = %d\n", prefix,
- caps->msix_vector_first_id);
+ }
+ }
+
+ ice_recalc_port_limited_caps(hw, &func_p->common_cap);
+}
+
+/**
+ * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
+ */
+static void
+ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_funcs = ice_hweight32(number);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
+ dev_p->num_funcs);
+}
+
+/**
+ * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_VSI for device capabilities.
+ */
+static void
+ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_vsi_allocd_to_host = number;
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
+ dev_p->num_vsi_allocd_to_host);
+}
+
+/**
+ * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_FD for device capabilities.
+ */
+static void
+ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_flow_director_fltr = number;
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
+ dev_p->num_flow_director_fltr);
+}
+
+/**
+ * ice_parse_dev_caps - Parse device capabilities
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @buf: buffer containing the device capability records
+ * @cap_count: the number of capabilities
+ *
+ * Helper device to parse device (0x000B) capabilities list. For
+ * capabilities shared between device and device, this relies on
+ * ice_parse_common_caps.
+ *
+ * Loop through the list of provided capabilities and extract the relevant
+ * data into the device capabilities structured.
+ */
+static void
+ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ void *buf, u32 cap_count)
+{
+ struct ice_aqc_list_caps_elem *cap_resp;
+ u32 i;
+
+ cap_resp = (struct ice_aqc_list_caps_elem *)buf;
+
+ ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
+
+ for (i = 0; i < cap_count; i++) {
+ u16 cap = LE16_TO_CPU(cap_resp[i].cap);
+ bool found;
+
+ found = ice_parse_common_caps(hw, &dev_p->common_cap,
+ &cap_resp[i], "dev caps");
+
+ switch (cap) {
+ case ICE_AQC_CAPS_VALID_FUNCTIONS:
+ ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_FD:
- if (dev_p) {
- dev_p->num_flow_director_fltr = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_flow_director_fltr = %d\n",
- prefix,
- dev_p->num_flow_director_fltr);
- }
- if (func_p) {
- u32 reg_val, val;
-
- if (hw->dcf_enabled)
- break;
- reg_val = rd32(hw, GLQF_FD_SIZE);
- val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
- GLQF_FD_SIZE_FD_GSIZE_S;
- func_p->fd_fltr_guar =
- ice_get_num_per_func(hw, val);
- val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
- GLQF_FD_SIZE_FD_BSIZE_S;
- func_p->fd_fltr_best_effort = val;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: fd_fltr_guar = %d\n",
- prefix, func_p->fd_fltr_guar);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: fd_fltr_best_effort = %d\n",
- prefix, func_p->fd_fltr_best_effort);
- }
+ case ICE_AQC_CAPS_VSI:
+ ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_MAX_MTU:
- caps->max_mtu = number;
- ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
- prefix, caps->max_mtu);
+ case ICE_AQC_CAPS_FD:
+ ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
break;
default:
- ice_debug(hw, ICE_DBG_INIT,
- "%s: unknown capability[%d]: 0x%x\n", prefix,
- i, cap);
+ /* Don't list common capabilities as unknown */
+ if (!found)
+ ice_debug(hw, ICE_DBG_INIT,
+ "dev caps: unknown capability[%d]: 0x%x\n",
+ i, cap);
break;
}
}
- /* Re-calculate capabilities that are dependent on the number of
- * physical ports; i.e. some features are not supported or function
- * differently on devices with more than 4 ports.
- */
- if (hw->dev_caps.num_funcs > 4) {
- /* Max 4 TCs per port */
- caps->maxtc = 4;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: maxtc = %d (based on #ports)\n", prefix,
- caps->maxtc);
- }
+ ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
+}
+
+/**
+ * ice_parse_caps - parse function/device capabilities
+ * @hw: pointer to the HW struct
+ * @buf: pointer to a buffer containing function/device capability records
+ * @cap_count: number of capability records in the list
+ * @opc: type of capabilities list to parse
+ *
+ * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
+ */
+static void
+ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
+ enum ice_adminq_opc opc)
+{
+ if (!buf)
+ return;
+
+ if (opc == ice_aqc_opc_list_dev_caps)
+ ice_parse_dev_caps(hw, &hw->dev_caps, buf, cap_count);
+ else if (opc == ice_aqc_opc_list_func_caps)
+ ice_parse_func_caps(hw, &hw->func_caps, buf, cap_count);
+ else
+ ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
}
/**
@@ -2850,9 +3023,9 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
* bits and OR request bits.
*/
cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
- ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
+ ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
- ICE_AQC_PHY_FEC_25G_KR_REQ;
+ ICE_AQC_PHY_FEC_25G_KR_REQ;
break;
case ICE_FEC_RS:
/* Clear BASE-R bits, and AND RS ability
@@ -2860,7 +3033,7 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
*/
cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
- ICE_AQC_PHY_FEC_25G_RS_544_REQ;
+ ICE_AQC_PHY_FEC_25G_RS_544_REQ;
break;
case ICE_FEC_NONE:
/* Clear all FEC option bits. */
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 012d129df..c47114d16 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1148,7 +1148,6 @@ struct ice_tx_cmpltnq {
};
#pragma pack()
-
/* LAN Tx Completion Queue Context */
#pragma pack(1)
struct ice_tx_cmpltnq_ctx {
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 7/8] net/ice/base: clear and free XLT entries on reset
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (5 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 6/8] net/ice/base: split capability parse into separate functions Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 8/8] net/ice/base: update version Qi Zhang
` (2 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang, stable, Vignesh Sridhar, Paul M Stillwell Jr
This fix has been added to address memory leak issues resulting from
triggering a sudden driver reset which does not allow us to follow our
normal removal flows for SW XLT entries for advanced features.
- Adding call to destroy flow profile locks when clearing SW XLT tables.
- Extraction sequence entries were not correctly cleared previously
which could cause ownership conflicts for repeated reset-replay calls.
Fixes: 969890d505b1 ("net/ice/base: enable clearing of HW tables")
Cc: stable@dpdk.org
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 016dc2b39..284569464 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3666,6 +3666,8 @@ static void ice_free_flow_profs(struct ice_hw *hw, u8 blk_idx)
LIST_DEL(&p->l_entry);
if (p->acts)
ice_free(hw, p->acts);
+
+ ice_destroy_lock(&p->entries_lock);
ice_free(hw, p);
}
ice_release_lock(&hw->fl_profs_locks[blk_idx]);
@@ -3794,7 +3796,7 @@ void ice_clear_hw_tbls(struct ice_hw *hw)
prof_redir->count * sizeof(*prof_redir->t),
ICE_NONDMA_MEM);
- ice_memset(es->t, 0, es->count * sizeof(*es->t),
+ ice_memset(es->t, 0, es->count * sizeof(*es->t) * es->fvw,
ICE_NONDMA_MEM);
ice_memset(es->ref_count, 0, es->count * sizeof(*es->ref_count),
ICE_NONDMA_MEM);
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v2 8/8] net/ice/base: update version
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (6 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 7/8] net/ice/base: clear and free XLT entries on reset Qi Zhang
@ 2020-07-01 5:49 ` Qi Zhang
2020-07-02 4:22 ` [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Yang, Qiming
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
9 siblings, 0 replies; 22+ messages in thread
From: Qi Zhang @ 2020-07-01 5:49 UTC (permalink / raw)
To: qiming.yang; +Cc: dev, Qi Zhang
Update base code version in readme.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README
index 726593971..1e9c854ae 100644
--- a/drivers/net/ice/base/README
+++ b/drivers/net/ice/base/README
@@ -6,7 +6,7 @@ Intel® ICE driver
==================
This directory contains source code of FreeBSD ice driver of version
-2020.03.26 released by the team which develops
+2020.06.17 released by the team which develops
basic drivers for any ice NIC. The directory of base/ contains the
original source package.
This driver is valid for the product(s) listed below
--
2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module Qi Zhang
@ 2020-07-02 4:20 ` Yang, Qiming
0 siblings, 0 replies; 22+ messages in thread
From: Yang, Qiming @ 2020-07-02 4:20 UTC (permalink / raw)
To: Zhang, Qi Z; +Cc: dev, Stillwell Jr, Paul M
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Wednesday, July 1, 2020 13:50
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: dev@dpdk.org; Zhang, Qi Z <qi.z.zhang@intel.com>; Stillwell Jr, Paul M
> <paul.m.stillwell.jr@intel.com>
> Subject: [PATCH v2 4/8] net/ice/base: code clean in FDIR module
>
> Remove unused macro and funciton.
This error spell still exist. Please fix it when you apply it
> Declare no external referenced function as static.
>
> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/ice/base/ice_fdir.c | 23 +----------------------
> drivers/net/ice/base/ice_fdir.h | 3 ---
> 2 files changed, 1 insertion(+), 25 deletions(-)
>
> diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
> index c5a20632c..b1dc2afb7 100644
> --- a/drivers/net/ice/base/ice_fdir.c
> +++ b/drivers/net/ice/base/ice_fdir.c
> @@ -597,7 +597,7 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
> * ice_set_dflt_val_fd_desc
> * @fd_fltr_ctx: pointer to fd filter descriptor
> */
> -void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
> +static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx
> +*fd_fltr_ctx)
> {
> fd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
> fd_fltr_ctx->comp_report =
> ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;
> @@ -1389,27 +1389,6 @@ bool ice_fdir_is_dup_fltr(struct ice_hw *hw,
> struct ice_fdir_fltr *input) }
>
> /**
> - * ice_clear_vsi_fd_table - admin command to clear FD table for a VSI
> - * @hw: hardware data structure
> - * @vsi_num: vsi_num (HW VSI num)
> - *
> - * Clears FD table entries by issuing admin command (direct, 0x0B06)
> - * Must to pass valid vsi_num as returned by "AddVSI".
> - */
> -enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw, u16 vsi_num) -{
> - struct ice_aqc_clear_fd_table *cmd;
> - struct ice_aq_desc desc;
> -
> - cmd = &desc.params.clear_fd_table;
> - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_fd_table);
> - cmd->clear_type = CL_FD_VM_VF_TYPE_VSI_IDX;
> -
> - cmd->vsi_index = CPU_TO_LE16(vsi_num);
> - return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
> -}
> -
> -/**
> * ice_clear_pf_fd_table - admin command to clear FD table for PF
> * @hw: hardware data structure
> *
> diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
> index 1f31debe6..ad3e11a5b 100644
> --- a/drivers/net/ice/base/ice_fdir.h
> +++ b/drivers/net/ice/base/ice_fdir.h
> @@ -17,7 +17,6 @@
> #define ICE_FDIR_TUN_PKT_OFF 50
> #define ICE_FDIR_MAX_RAW_PKT_SIZE (512 +
> ICE_FDIR_TUN_PKT_OFF)
> #define ICE_FDIR_BUF_FULL_MARGIN 10
> -#define ICE_FDIR_BUF_HEAD_ROOM 32
>
> /* macros for offsets into packets for flow director programming */
> #define ICE_IPV4_SRC_ADDR_OFFSET 26
> @@ -222,7 +221,6 @@ struct ice_fdir_base_pkt {
>
> enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id);
> enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id); -void
> ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx); enum
> ice_status ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16
> num_fltr); enum ice_status @@ -231,7 +229,6 @@ enum ice_status
> ice_alloc_fd_shrd_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
> enum ice_status ice_free_fd_shrd_item(struct ice_hw *hw, u16 cntr_id,
> u16 num_fltr); -enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw,
> u16 vsi_num); enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw);
> void ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,
> --
> 2.13.6
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [dpdk-dev] [PATCH v2 0/8] update base code batch 3
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (7 preceding siblings ...)
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 8/8] net/ice/base: update version Qi Zhang
@ 2020-07-02 4:22 ` Yang, Qiming
2020-07-02 13:06 ` Zhang, Qi Z
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
9 siblings, 1 reply; 22+ messages in thread
From: Yang, Qiming @ 2020-07-02 4:22 UTC (permalink / raw)
To: Zhang, Qi Z; +Cc: dev
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Wednesday, July 1, 2020 13:50
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: dev@dpdk.org; Zhang, Qi Z <qi.z.zhang@intel.com>
> Subject: [PATCH v2 0/8] update base code batch 3
>
> The patchset include couple bug fixes and code clean also update the version
> number.
>
> v2:
> - add missing part in ice_rem_rss_cfg_sync in PATCH 1/8
> - remove unnessary change in PATCH 1/8
>
> Qi Zhang (8):
> net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
> net/ice/base: cleanup some code style
> net/ice/base: move lldp function to common module
> net/ice/base: code clean in FDIR module
> net/ice/base: add capability list AQ function
> net/ice/base: split capability parse into separate functions
> net/ice/base: clear and free XLT entries on reset
> net/ice/base: update version
>
> drivers/net/ice/base/README | 2 +-
> drivers/net/ice/base/ice_adminq_cmd.h | 6 +-
> drivers/net/ice/base/ice_common.c | 588
> ++++++++++++++++++++++++----------
> drivers/net/ice/base/ice_common.h | 3 +
> drivers/net/ice/base/ice_dcb.c | 33 --
> drivers/net/ice/base/ice_dcb.h | 3 -
> drivers/net/ice/base/ice_fdir.c | 23 +-
> drivers/net/ice/base/ice_fdir.h | 3 -
> drivers/net/ice/base/ice_flex_pipe.c | 4 +-
> drivers/net/ice/base/ice_flow.c | 24 +-
> drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
> drivers/net/ice/base/ice_sched.c | 3 +-
> 12 files changed, 446 insertions(+), 247 deletions(-)
>
> --
> 2.13.6
Only with a small spell issue in patch 4/8, please fix it when you apply the patch set
Acked-by: Qiming Yang <qiming.yang@intel.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [dpdk-dev] [PATCH v2 0/8] update base code batch 3
2020-07-02 4:22 ` [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Yang, Qiming
@ 2020-07-02 13:06 ` Zhang, Qi Z
0 siblings, 0 replies; 22+ messages in thread
From: Zhang, Qi Z @ 2020-07-02 13:06 UTC (permalink / raw)
To: Yang, Qiming; +Cc: dev
> -----Original Message-----
> From: Yang, Qiming <qiming.yang@intel.com>
> Sent: Thursday, July 2, 2020 12:23 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH v2 0/8] update base code batch 3
>
>
>
> > -----Original Message-----
> > From: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Sent: Wednesday, July 1, 2020 13:50
> > To: Yang, Qiming <qiming.yang@intel.com>
> > Cc: dev@dpdk.org; Zhang, Qi Z <qi.z.zhang@intel.com>
> > Subject: [PATCH v2 0/8] update base code batch 3
> >
> > The patchset include couple bug fixes and code clean also update the
> > version number.
> >
> > v2:
> > - add missing part in ice_rem_rss_cfg_sync in PATCH 1/8
> > - remove unnessary change in PATCH 1/8
> >
> > Qi Zhang (8):
> > net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
> > net/ice/base: cleanup some code style
> > net/ice/base: move lldp function to common module
> > net/ice/base: code clean in FDIR module
> > net/ice/base: add capability list AQ function
> > net/ice/base: split capability parse into separate functions
> > net/ice/base: clear and free XLT entries on reset
> > net/ice/base: update version
> >
> > drivers/net/ice/base/README | 2 +-
> > drivers/net/ice/base/ice_adminq_cmd.h | 6 +-
> > drivers/net/ice/base/ice_common.c | 588
> > ++++++++++++++++++++++++----------
> > drivers/net/ice/base/ice_common.h | 3 +
> > drivers/net/ice/base/ice_dcb.c | 33 --
> > drivers/net/ice/base/ice_dcb.h | 3 -
> > drivers/net/ice/base/ice_fdir.c | 23 +-
> > drivers/net/ice/base/ice_fdir.h | 3 -
> > drivers/net/ice/base/ice_flex_pipe.c | 4 +-
> > drivers/net/ice/base/ice_flow.c | 24 +-
> > drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
> > drivers/net/ice/base/ice_sched.c | 3 +-
> > 12 files changed, 446 insertions(+), 247 deletions(-)
> >
> > --
> > 2.13.6
>
> Only with a small spell issue in patch 4/8, please fix it when you apply the
> patch set
>
> Acked-by: Qiming Yang <qiming.yang@intel.com>
Applied to dpdk-next-net-intel after fix the typo in patch 4/8.
Thanks
Qi
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 0/8] update base code batch 3
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
` (8 preceding siblings ...)
2020-07-02 4:22 ` [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Yang, Qiming
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Junfeng Guo
` (8 more replies)
9 siblings, 9 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang; +Cc: dev, stable, ferruh.yigit, junfeng.guo
The patchset include couple bug fixes and code clean
also update the version number.
v3:
- adjust code position in ice_rem_rss_cfg_sync in PATCH 1/8
- remove uncessary printf and cleanup code style in PATCH 1/8
v2:
- add missing part in ice_rem_rss_cfg_sync in PATCH 1/8
- remove unnessary change in PATCH 1/8
Qi Zhang (8):
net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
net/ice/base: cleanup some code style
net/ice/base: move LLDP function to common module
net/ice/base: clean code in flow director module
net/ice/base: add capability list AQ function
net/ice/base: split capability parse into separate functions
net/ice/base: clear and free XLT entries on reset
net/ice/base: update version
drivers/net/ice/base/README | 2 +-
drivers/net/ice/base/ice_adminq_cmd.h | 6 +-
drivers/net/ice/base/ice_common.c | 588 ++++++++++++++++++--------
drivers/net/ice/base/ice_common.h | 3 +
drivers/net/ice/base/ice_dcb.c | 33 --
drivers/net/ice/base/ice_dcb.h | 3 -
drivers/net/ice/base/ice_fdir.c | 23 +-
drivers/net/ice/base/ice_fdir.h | 3 -
drivers/net/ice/base/ice_flex_pipe.c | 4 +-
drivers/net/ice/base/ice_flow.c | 22 +-
drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
drivers/net/ice/base/ice_sched.c | 3 +-
12 files changed, 444 insertions(+), 247 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 2/8] net/ice/base: cleanup some code style Junfeng Guo
` (7 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang; +Cc: dev, stable, ferruh.yigit, junfeng.guo
From: Qi Zhang <qi.z.zhang@intel.com>
An IP header combined with GTP-U header should be regarded as
inner layer for RSS, otherwise it mess the field vector between
an IPv4 rule and IPv6 rule e.g:
testpmd> flow create 0 ingress pattern eth / ipv4 / udp / gtpu / \
gtp_psc / ipv4 / udp / end actions rss types ipv4-udp end key_len \
0 queues end / end
testpmd> flow create 0 ingress pattern eth / ipv4 / udp / gtpu / \
gtp_psc / ipv6 / udp / end actions rss types ipv6-udp end key_len \
0 queues end / end
Fixes: b7d34ccc47b5 ("net/ice/base: packet encapsulation for RSS")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 6adcda844..984fa90ce 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -3557,6 +3557,11 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (status)
goto exit;
+ /* don't do RSS for GTPU outer */
+ if (segs_cnt == ICE_RSS_OUTER_HEADERS &&
+ segs[segs_cnt - 1].hdrs & ICE_FLOW_SEG_HDR_GTPU)
+ return ICE_SUCCESS;
+
/* Search for a flow profile that has matching headers, hash fields
* and has the input VSI associated to it. If found, no further
* operations required and exit.
@@ -3673,6 +3678,7 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
ice_acquire_lock(&hw->rss_locks);
status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
ICE_RSS_OUTER_HEADERS, symm);
+
if (!status)
status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,
addl_hdrs, ICE_RSS_INNER_HEADERS,
@@ -3712,6 +3718,10 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (status)
goto out;
+ if (segs_cnt == ICE_RSS_OUTER_HEADERS &&
+ segs[segs_cnt - 1].hdrs & ICE_FLOW_SEG_HDR_GTPU)
+ return ICE_SUCCESS;
+
prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS);
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 2/8] net/ice/base: cleanup some code style
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 3/8] net/ice/base: move LLDP function to common module Junfeng Guo
` (6 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Bruce Allan, Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
Cleanup code style issue reported by kernel checkpatch.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 6 ++++--
drivers/net/ice/base/ice_common.c | 2 --
drivers/net/ice/base/ice_flow.c | 12 ++++++------
drivers/net/ice/base/ice_sched.c | 3 +--
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9ee5b4eb5..e17369f5e 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2794,8 +2794,10 @@ struct ice_aq_desc {
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;
- struct ice_aqc_set_health_status_config set_health_status_config;
- struct ice_aqc_get_supported_health_status_codes get_supported_health_status_codes;
+ struct ice_aqc_set_health_status_config
+ set_health_status_config;
+ struct ice_aqc_get_supported_health_status_codes
+ get_supported_health_status_codes;
struct ice_aqc_get_health_status get_health_status;
struct ice_aqc_clear_health_status clear_health_status;
} params;
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 1683daf28..21044b071 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -193,14 +193,12 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
pcaps->module_type[2]);
-
if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
sizeof(pi->phy.link_info.module_type),
ICE_NONDMA_TO_NONDMA);
-
}
return status;
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 984fa90ce..9a17d956b 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -805,16 +805,16 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
}
if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
(hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
- src = !i ?
- (const ice_bitmap_t *)ice_ptypes_ipv4_ofos_all :
- (const ice_bitmap_t *)ice_ptypes_ipv4_il;
+ src = i ?
+ (const ice_bitmap_t *)ice_ptypes_ipv4_il :
+ (const ice_bitmap_t *)ice_ptypes_ipv4_ofos_all;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
} else if ((hdrs & ICE_FLOW_SEG_HDR_IPV6) &&
(hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {
- src = !i ?
- (const ice_bitmap_t *)ice_ptypes_ipv6_ofos_all :
- (const ice_bitmap_t *)ice_ptypes_ipv6_il;
+ src = i ?
+ (const ice_bitmap_t *)ice_ptypes_ipv6_il :
+ (const ice_bitmap_t *)ice_ptypes_ipv6_ofos_all;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
} else if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 91847110b..8ee4b708e 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -5334,7 +5334,7 @@ void ice_sched_replay_agg(struct ice_hw *hw)
ice_acquire_lock(&pi->sched_lock);
LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
- list_entry) {
+ list_entry)
/* replay aggregator (re-create aggregator node) */
if (!ice_cmp_bitmap(agg_info->tc_bitmap,
agg_info->replay_tc_bitmap,
@@ -5363,7 +5363,6 @@ void ice_sched_replay_agg(struct ice_hw *hw)
ice_info(hw, "Replay agg bw [id=%d] failed\n",
agg_info->agg_id);
}
- }
ice_release_lock(&pi->sched_lock);
}
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 3/8] net/ice/base: move LLDP function to common module
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 2/8] net/ice/base: cleanup some code style Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 4/8] net/ice/base: clean code in flow director module Junfeng Guo
` (5 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Dave Ertman, Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
To implement a FW workaround for LFC, a set_local_mib must be
performed after every link up event. For systems that do not
have DCB configured, we need to move the function
ice_aq_set_lldp_mib() from the DCB specific ice_dcb.c to
ice_common.c so that the driver always has access to this AQ
command.
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_common.c | 33 +++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 +++
drivers/net/ice/base/ice_dcb.c | 33 -------------------------------
drivers/net/ice/base/ice_dcb.h | 3 ---
4 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 21044b071..cab81e0fc 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4557,3 +4557,36 @@ bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
return false;
}
+
+/**
+ * ice_aq_set_lldp_mib - Set the LLDP MIB
+ * @hw: pointer to the HW struct
+ * @mib_type: Local, Remote or both Local and Remote MIBs
+ * @buf: pointer to the caller-supplied buffer to store the MIB block
+ * @buf_size: size of the buffer (in bytes)
+ * @cd: pointer to command details structure or NULL
+ *
+ * Set the LLDP MIB. (0x0A08)
+ */
+enum ice_status
+ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_lldp_set_local_mib *cmd;
+ struct ice_aq_desc desc;
+
+ cmd = &desc.params.lldp_set_mib;
+
+ if (buf_size == 0 || !buf)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
+
+ desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
+ desc.datalen = CPU_TO_LE16(buf_size);
+
+ cmd->type = mib_type;
+ cmd->length = CPU_TO_LE16(buf_size);
+
+ return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+}
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index cb41497bc..329d0b50f 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -220,4 +220,7 @@ void ice_print_rollback_msg(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
+enum ice_status
+ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 6bdec18c0..b9643b5ce 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -135,39 +135,6 @@ ice_aq_start_lldp(struct ice_hw *hw, bool persist, struct ice_sq_cd *cd)
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
-/**
- * ice_aq_set_lldp_mib - Set the LLDP MIB
- * @hw: pointer to the HW struct
- * @mib_type: Local, Remote or both Local and Remote MIBs
- * @buf: pointer to the caller-supplied buffer to store the MIB block
- * @buf_size: size of the buffer (in bytes)
- * @cd: pointer to command details structure or NULL
- *
- * Set the LLDP MIB. (0x0A08)
- */
-enum ice_status
-ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
- struct ice_sq_cd *cd)
-{
- struct ice_aqc_lldp_set_local_mib *cmd;
- struct ice_aq_desc desc;
-
- cmd = &desc.params.lldp_set_mib;
-
- if (buf_size == 0 || !buf)
- return ICE_ERR_PARAM;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
-
- desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD);
- desc.datalen = CPU_TO_LE16(buf_size);
-
- cmd->type = mib_type;
- cmd->length = CPU_TO_LE16(buf_size);
-
- return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
-}
-
/**
* ice_get_dcbx_status
* @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 3ffeb864c..83b6e4d8f 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -183,9 +183,6 @@ ice_aq_get_lldp_mib(struct ice_hw *hw, u8 bridge_type, u8 mib_type, void *buf,
u16 buf_size, u16 *local_len, u16 *remote_len,
struct ice_sq_cd *cd);
enum ice_status
-ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
- struct ice_sq_cd *cd);
-enum ice_status
ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
struct ice_aqc_get_cee_dcb_cfg_resp *buff,
struct ice_sq_cd *cd);
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 4/8] net/ice/base: clean code in flow director module
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (2 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 3/8] net/ice/base: move LLDP function to common module Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 5/8] net/ice/base: add capability list AQ function Junfeng Guo
` (4 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
Remove unused macro and function.
Declare no external referenced function as static.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_fdir.c | 23 +----------------------
drivers/net/ice/base/ice_fdir.h | 3 ---
2 files changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index c5a20632c..b1dc2afb7 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -597,7 +597,7 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {
* ice_set_dflt_val_fd_desc
* @fd_fltr_ctx: pointer to fd filter descriptor
*/
-void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
+static void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)
{
fd_fltr_ctx->comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
fd_fltr_ctx->comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL;
@@ -1388,27 +1388,6 @@ bool ice_fdir_is_dup_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input)
return ret;
}
-/**
- * ice_clear_vsi_fd_table - admin command to clear FD table for a VSI
- * @hw: hardware data structure
- * @vsi_num: vsi_num (HW VSI num)
- *
- * Clears FD table entries by issuing admin command (direct, 0x0B06)
- * Must to pass valid vsi_num as returned by "AddVSI".
- */
-enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw, u16 vsi_num)
-{
- struct ice_aqc_clear_fd_table *cmd;
- struct ice_aq_desc desc;
-
- cmd = &desc.params.clear_fd_table;
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_fd_table);
- cmd->clear_type = CL_FD_VM_VF_TYPE_VSI_IDX;
-
- cmd->vsi_index = CPU_TO_LE16(vsi_num);
- return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
-}
-
/**
* ice_clear_pf_fd_table - admin command to clear FD table for PF
* @hw: hardware data structure
diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h
index 1f31debe6..ad3e11a5b 100644
--- a/drivers/net/ice/base/ice_fdir.h
+++ b/drivers/net/ice/base/ice_fdir.h
@@ -17,7 +17,6 @@
#define ICE_FDIR_TUN_PKT_OFF 50
#define ICE_FDIR_MAX_RAW_PKT_SIZE (512 + ICE_FDIR_TUN_PKT_OFF)
#define ICE_FDIR_BUF_FULL_MARGIN 10
-#define ICE_FDIR_BUF_HEAD_ROOM 32
/* macros for offsets into packets for flow director programming */
#define ICE_IPV4_SRC_ADDR_OFFSET 26
@@ -222,7 +221,6 @@ struct ice_fdir_base_pkt {
enum ice_status ice_alloc_fd_res_cntr(struct ice_hw *hw, u16 *cntr_id);
enum ice_status ice_free_fd_res_cntr(struct ice_hw *hw, u16 cntr_id);
-void ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx);
enum ice_status
ice_alloc_fd_guar_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
enum ice_status
@@ -231,7 +229,6 @@ enum ice_status
ice_alloc_fd_shrd_item(struct ice_hw *hw, u16 *cntr_id, u16 num_fltr);
enum ice_status
ice_free_fd_shrd_item(struct ice_hw *hw, u16 cntr_id, u16 num_fltr);
-enum ice_status ice_clear_vsi_fd_table(struct ice_hw *hw, u16 vsi_num);
enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw);
void
ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 5/8] net/ice/base: add capability list AQ function
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (3 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 4/8] net/ice/base: clean code in flow director module Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 6/8] net/ice/base: split capability parse into separate functions Junfeng Guo
` (3 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Jacob Keller,
Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
The current implementation for reading device and function capabilities
from firmware, ice_aq_discover_caps, has potentially undesirable
side effects.
ice_aq_discover_caps calls ice_parse_caps, resulting in overwriting the
capabilities stored in the hw structure. This is ok during
initialization, but means that code which wants to read the capabilities
after initialization cannot use ice_aq_discover_caps without being
careful of the side effects.
Factor out the AQ command logic into a new ice_aq_list_caps function.
This will be used by the ice_aq_discover_caps function.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_common.c | 62 +++++++++++++++++++++++++------
1 file changed, 50 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index cab81e0fc..33e29bc0e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2007,20 +2007,27 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
}
/**
- * ice_aq_discover_caps - query function/device capabilities
+ * ice_aq_list_caps - query function/device capabilities
* @hw: pointer to the HW struct
- * @buf: a virtual buffer to hold the capabilities
- * @buf_size: Size of the virtual buffer
- * @cap_count: cap count needed if AQ err==ENOMEM
- * @opc: capabilities type to discover - pass in the command opcode
+ * @buf: a buffer to hold the capabilities
+ * @buf_size: size of the buffer
+ * @cap_count: if not NULL, set to the number of capabilities reported
+ * @opc: capabilities type to discover, device or function
* @cd: pointer to command details structure or NULL
*
- * Get the function(0x000a)/device(0x000b) capabilities description from
- * the firmware.
+ * Get the function (0x000A) or device (0x000B) capabilities description from
+ * firmware and store it in the buffer.
+ *
+ * If the cap_count pointer is not NULL, then it is set to the number of
+ * capabilities firmware will report. Note that if the buffer size is too
+ * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
+ * cap_count will still be updated in this case. It is recommended that the
+ * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
+ * firmware could return) to avoid this.
*/
static enum ice_status
-ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
- enum ice_adminq_opc opc, struct ice_sq_cd *cd)
+ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
+ enum ice_adminq_opc opc, struct ice_sq_cd *cd)
{
struct ice_aqc_list_caps *cmd;
struct ice_aq_desc desc;
@@ -2033,12 +2040,43 @@ ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
return ICE_ERR_PARAM;
ice_fill_dflt_direct_cmd_desc(&desc, opc);
-
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (cap_count)
+ *cap_count = LE32_TO_CPU(cmd->count);
+
+ return status;
+}
+
+/**
+ * ice_aq_discover_caps - query function/device capabilities
+ * @hw: pointer to the HW struct
+ * @buf: a virtual buffer to hold the capabilities
+ * @buf_size: Size of the virtual buffer
+ * @cap_count: cap count needed if AQ err==ENOMEM
+ * @opc: capabilities type to discover - pass in the command opcode
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get the function(0x000a)/device(0x000b) capabilities description from
+ * the firmware.
+ *
+ * NOTE: this function has the side effect of updating the hw->dev_caps or
+ * hw->func_caps by way of calling ice_parse_caps.
+ */
+static enum ice_status
+ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
+ enum ice_adminq_opc opc, struct ice_sq_cd *cd)
+{
+ u32 local_cap_count = 0;
+ enum ice_status status;
+
+ status = ice_aq_list_caps(hw, buf, buf_size, &local_cap_count,
+ opc, cd);
if (!status)
- ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
+ ice_parse_caps(hw, buf, local_cap_count, opc);
else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
- *cap_count = LE32_TO_CPU(cmd->count);
+ *cap_count = local_cap_count;
+
return status;
}
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 6/8] net/ice/base: split capability parse into separate functions
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (4 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 5/8] net/ice/base: add capability list AQ function Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 7/8] net/ice/base: clear and free XLT entries on reset Junfeng Guo
` (2 subsequent siblings)
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Jacob Keller,
Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
The ice_parse_caps function is used to convert the capability block data
coming from firmware into a structured format used by other parts of the
code.
The current implementation directly updates the hw->func_caps and
hw->dev_caps structures. It is directly called from within
ice_aq_discover_caps. This causes the discover_caps function to have the
side effect of modifying the hw capability structures, which is not
intuitive.
Split this function into ice_parse_dev_caps and ice_parse_func_caps.
These functions will take a pointer to the dev_caps and func_caps
respectively. Also create an ice_parse_common_caps for sharing the
capability logic that is common to device and function.
Doing so enables a future refactor to allow reading and parsing
capabilities into a local caps structure instead of modifying the
members of the hw structure directly.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_common.c | 491 ++++++++++++++++++---------
drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
2 files changed, 332 insertions(+), 160 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 33e29bc0e..6168fb4f0 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1821,189 +1821,362 @@ static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
}
/**
- * ice_parse_caps - parse function/device capabilities
+ * ice_parse_common_caps - parse common device/function capabilities
* @hw: pointer to the HW struct
- * @buf: pointer to a buffer containing function/device capability records
- * @cap_count: number of capability records in the list
- * @opc: type of capabilities list to parse
+ * @caps: pointer to common capabilities structure
+ * @elem: the capability element to parse
+ * @prefix: message prefix for tracing capabilities
*
- * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
+ * Given a capability element, extract relevant details into the common
+ * capability structure.
+ *
+ * Returns: true if the capability matches one of the common capability ids,
+ * false otherwise.
+ */
+static bool
+ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
+ struct ice_aqc_list_caps_elem *elem, const char *prefix)
+{
+ u32 logical_id = LE32_TO_CPU(elem->logical_id);
+ u32 phys_id = LE32_TO_CPU(elem->phys_id);
+ u32 number = LE32_TO_CPU(elem->number);
+ u16 cap = LE16_TO_CPU(elem->cap);
+ bool found = true;
+
+ switch (cap) {
+ case ICE_AQC_CAPS_VALID_FUNCTIONS:
+ caps->valid_functions = number;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: valid_functions (bitmap) = %d\n", prefix,
+ caps->valid_functions);
+ break;
+ case ICE_AQC_CAPS_DCB:
+ caps->dcb = (number == 1);
+ caps->active_tc_bitmap = logical_id;
+ caps->maxtc = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: dcb = %d\n", prefix, caps->dcb);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: active_tc_bitmap = %d\n", prefix,
+ caps->active_tc_bitmap);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: maxtc = %d\n", prefix, caps->maxtc);
+ break;
+ case ICE_AQC_CAPS_RSS:
+ caps->rss_table_size = number;
+ caps->rss_table_entry_width = logical_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rss_table_size = %d\n", prefix,
+ caps->rss_table_size);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rss_table_entry_width = %d\n", prefix,
+ caps->rss_table_entry_width);
+ break;
+ case ICE_AQC_CAPS_RXQS:
+ caps->num_rxq = number;
+ caps->rxq_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_rxq = %d\n", prefix,
+ caps->num_rxq);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: rxq_first_id = %d\n", prefix,
+ caps->rxq_first_id);
+ break;
+ case ICE_AQC_CAPS_TXQS:
+ caps->num_txq = number;
+ caps->txq_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_txq = %d\n", prefix,
+ caps->num_txq);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: txq_first_id = %d\n", prefix,
+ caps->txq_first_id);
+ break;
+ case ICE_AQC_CAPS_MSIX:
+ caps->num_msix_vectors = number;
+ caps->msix_vector_first_id = phys_id;
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: num_msix_vectors = %d\n", prefix,
+ caps->num_msix_vectors);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: msix_vector_first_id = %d\n", prefix,
+ caps->msix_vector_first_id);
+ break;
+ case ICE_AQC_CAPS_MAX_MTU:
+ caps->max_mtu = number;
+ ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
+ prefix, caps->max_mtu);
+ break;
+ default:
+ /* Not one of the recognized common capabilities */
+ found = false;
+ }
+
+ return found;
+}
+
+/**
+ * ice_recalc_port_limited_caps - Recalculate port limited capabilities
+ * @hw: pointer to the HW structure
+ * @caps: pointer to capabilities structure to fix
+ *
+ * Re-calculate the capabilities that are dependent on the number of physical
+ * ports; i.e. some features are not supported or function differently on
+ * devices with more than 4 ports.
*/
static void
-ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
- enum ice_adminq_opc opc)
+ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
{
- struct ice_aqc_list_caps_elem *cap_resp;
- struct ice_hw_func_caps *func_p = NULL;
- struct ice_hw_dev_caps *dev_p = NULL;
- struct ice_hw_common_caps *caps;
- char const *prefix;
- u32 i;
+ /* This assumes device capabilities are always scanned before function
+ * capabilities during the initialization flow.
+ */
+ if (hw->dev_caps.num_funcs > 4) {
+ /* Max 4 TCs per port */
+ caps->maxtc = 4;
+ ice_debug(hw, ICE_DBG_INIT,
+ "reducing maxtc to %d (based on #ports)\n",
+ caps->maxtc);
+ }
+}
- if (!buf)
- return;
+/**
+ * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_VSI.
+ */
+static void
+ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
+ ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
+ LE32_TO_CPU(cap->number));
+ ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
+ func_p->guar_num_vsi);
+}
- cap_resp = (struct ice_aqc_list_caps_elem *)buf;
+/**
+ * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @cap: pointer to the capability element to parse
+ *
+ * Extract function capabilities for ICE_AQC_CAPS_FD.
+ */
+static void
+ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 reg_val, val;
- if (opc == ice_aqc_opc_list_dev_caps) {
- dev_p = &hw->dev_caps;
- caps = &dev_p->common_cap;
+ if (hw->dcf_enabled)
+ return;
+ reg_val = rd32(hw, GLQF_FD_SIZE);
+ val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
+ GLQF_FD_SIZE_FD_GSIZE_S;
+ func_p->fd_fltr_guar =
+ ice_get_num_per_func(hw, val);
+ val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
+ GLQF_FD_SIZE_FD_BSIZE_S;
+ func_p->fd_fltr_best_effort = val;
+
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: fd_fltr_guar = %d\n",
+ func_p->fd_fltr_guar);
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: fd_fltr_best_effort = %d\n",
+ func_p->fd_fltr_best_effort);
+}
- ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
+/**
+ * ice_parse_func_caps - Parse function capabilities
+ * @hw: pointer to the HW struct
+ * @func_p: pointer to function capabilities structure
+ * @buf: buffer containing the function capability records
+ * @cap_count: the number of capabilities
+ *
+ * Helper function to parse function (0x000A) capabilities list. For
+ * capabilities shared between device and function, this relies on
+ * ice_parse_common_caps.
+ *
+ * Loop through the list of provided capabilities and extract the relevant
+ * data into the function capabilities structured.
+ */
+static void
+ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
+ void *buf, u32 cap_count)
+{
+ struct ice_aqc_list_caps_elem *cap_resp;
+ u32 i;
- prefix = "dev cap";
- } else if (opc == ice_aqc_opc_list_func_caps) {
- func_p = &hw->func_caps;
- caps = &func_p->common_cap;
+ cap_resp = (struct ice_aqc_list_caps_elem *)buf;
- ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
+ ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);
- prefix = "func cap";
- } else {
- ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
- return;
- }
+ for (i = 0; i < cap_count; i++) {
+ u16 cap = LE16_TO_CPU(cap_resp[i].cap);
+ bool found;
- for (i = 0; caps && i < cap_count; i++, cap_resp++) {
- u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
- u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
- u32 number = LE32_TO_CPU(cap_resp->number);
- u16 cap = LE16_TO_CPU(cap_resp->cap);
+ found = ice_parse_common_caps(hw, &func_p->common_cap,
+ &cap_resp[i], "func caps");
switch (cap) {
- case ICE_AQC_CAPS_VALID_FUNCTIONS:
- caps->valid_functions = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: valid_functions (bitmap) = %d\n", prefix,
- caps->valid_functions);
-
- /* store func count for resource management purposes */
- if (dev_p)
- dev_p->num_funcs = ice_hweight32(number);
- break;
case ICE_AQC_CAPS_VSI:
- if (dev_p) {
- dev_p->num_vsi_allocd_to_host = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_vsi_allocd_to_host = %d\n",
- prefix,
- dev_p->num_vsi_allocd_to_host);
- } else if (func_p) {
- func_p->guar_num_vsi =
- ice_get_num_per_func(hw, ICE_MAX_VSI);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: guar_num_vsi (fw) = %d\n",
- prefix, number);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: guar_num_vsi = %d\n",
- prefix, func_p->guar_num_vsi);
- }
- break;
- case ICE_AQC_CAPS_DCB:
- caps->dcb = (number == 1);
- caps->active_tc_bitmap = logical_id;
- caps->maxtc = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: dcb = %d\n", prefix, caps->dcb);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: active_tc_bitmap = %d\n", prefix,
- caps->active_tc_bitmap);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: maxtc = %d\n", prefix, caps->maxtc);
- break;
- case ICE_AQC_CAPS_RSS:
- caps->rss_table_size = number;
- caps->rss_table_entry_width = logical_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rss_table_size = %d\n", prefix,
- caps->rss_table_size);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rss_table_entry_width = %d\n", prefix,
- caps->rss_table_entry_width);
+ ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_RXQS:
- caps->num_rxq = number;
- caps->rxq_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_rxq = %d\n", prefix,
- caps->num_rxq);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: rxq_first_id = %d\n", prefix,
- caps->rxq_first_id);
+ case ICE_AQC_CAPS_FD:
+ ice_parse_fdir_func_caps(hw, func_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_TXQS:
- caps->num_txq = number;
- caps->txq_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_txq = %d\n", prefix,
- caps->num_txq);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: txq_first_id = %d\n", prefix,
- caps->txq_first_id);
+ default:
+ /* Don't list common capabilities as unknown */
+ if (!found)
+ ice_debug(hw, ICE_DBG_INIT,
+ "func caps: unknown capability[%d]: 0x%x\n",
+ i, cap);
break;
- case ICE_AQC_CAPS_MSIX:
- caps->num_msix_vectors = number;
- caps->msix_vector_first_id = phys_id;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_msix_vectors = %d\n", prefix,
- caps->num_msix_vectors);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: msix_vector_first_id = %d\n", prefix,
- caps->msix_vector_first_id);
+ }
+ }
+
+ ice_recalc_port_limited_caps(hw, &func_p->common_cap);
+}
+
+/**
+ * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
+ */
+static void
+ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_funcs = ice_hweight32(number);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
+ dev_p->num_funcs);
+}
+
+/**
+ * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_VSI for device capabilities.
+ */
+static void
+ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_vsi_allocd_to_host = number;
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
+ dev_p->num_vsi_allocd_to_host);
+}
+
+/**
+ * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_FD for device capabilities.
+ */
+static void
+ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ u32 number = LE32_TO_CPU(cap->number);
+
+ dev_p->num_flow_director_fltr = number;
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
+ dev_p->num_flow_director_fltr);
+}
+
+/**
+ * ice_parse_dev_caps - Parse device capabilities
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @buf: buffer containing the device capability records
+ * @cap_count: the number of capabilities
+ *
+ * Helper device to parse device (0x000B) capabilities list. For
+ * capabilities shared between device and device, this relies on
+ * ice_parse_common_caps.
+ *
+ * Loop through the list of provided capabilities and extract the relevant
+ * data into the device capabilities structured.
+ */
+static void
+ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
+ void *buf, u32 cap_count)
+{
+ struct ice_aqc_list_caps_elem *cap_resp;
+ u32 i;
+
+ cap_resp = (struct ice_aqc_list_caps_elem *)buf;
+
+ ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);
+
+ for (i = 0; i < cap_count; i++) {
+ u16 cap = LE16_TO_CPU(cap_resp[i].cap);
+ bool found;
+
+ found = ice_parse_common_caps(hw, &dev_p->common_cap,
+ &cap_resp[i], "dev caps");
+
+ switch (cap) {
+ case ICE_AQC_CAPS_VALID_FUNCTIONS:
+ ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_FD:
- if (dev_p) {
- dev_p->num_flow_director_fltr = number;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: num_flow_director_fltr = %d\n",
- prefix,
- dev_p->num_flow_director_fltr);
- }
- if (func_p) {
- u32 reg_val, val;
-
- if (hw->dcf_enabled)
- break;
- reg_val = rd32(hw, GLQF_FD_SIZE);
- val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
- GLQF_FD_SIZE_FD_GSIZE_S;
- func_p->fd_fltr_guar =
- ice_get_num_per_func(hw, val);
- val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
- GLQF_FD_SIZE_FD_BSIZE_S;
- func_p->fd_fltr_best_effort = val;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: fd_fltr_guar = %d\n",
- prefix, func_p->fd_fltr_guar);
- ice_debug(hw, ICE_DBG_INIT,
- "%s: fd_fltr_best_effort = %d\n",
- prefix, func_p->fd_fltr_best_effort);
- }
+ case ICE_AQC_CAPS_VSI:
+ ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
break;
- case ICE_AQC_CAPS_MAX_MTU:
- caps->max_mtu = number;
- ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
- prefix, caps->max_mtu);
+ case ICE_AQC_CAPS_FD:
+ ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
break;
default:
- ice_debug(hw, ICE_DBG_INIT,
- "%s: unknown capability[%d]: 0x%x\n", prefix,
- i, cap);
+ /* Don't list common capabilities as unknown */
+ if (!found)
+ ice_debug(hw, ICE_DBG_INIT,
+ "dev caps: unknown capability[%d]: 0x%x\n",
+ i, cap);
break;
}
}
- /* Re-calculate capabilities that are dependent on the number of
- * physical ports; i.e. some features are not supported or function
- * differently on devices with more than 4 ports.
- */
- if (hw->dev_caps.num_funcs > 4) {
- /* Max 4 TCs per port */
- caps->maxtc = 4;
- ice_debug(hw, ICE_DBG_INIT,
- "%s: maxtc = %d (based on #ports)\n", prefix,
- caps->maxtc);
- }
+ ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
+}
+
+/**
+ * ice_parse_caps - parse function/device capabilities
+ * @hw: pointer to the HW struct
+ * @buf: pointer to a buffer containing function/device capability records
+ * @cap_count: number of capability records in the list
+ * @opc: type of capabilities list to parse
+ *
+ * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
+ */
+static void
+ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
+ enum ice_adminq_opc opc)
+{
+ if (!buf)
+ return;
+
+ if (opc == ice_aqc_opc_list_dev_caps)
+ ice_parse_dev_caps(hw, &hw->dev_caps, buf, cap_count);
+ else if (opc == ice_aqc_opc_list_func_caps)
+ ice_parse_func_caps(hw, &hw->func_caps, buf, cap_count);
+ else
+ ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
}
/**
@@ -2850,9 +3023,9 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
* bits and OR request bits.
*/
cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
- ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
+ ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
- ICE_AQC_PHY_FEC_25G_KR_REQ;
+ ICE_AQC_PHY_FEC_25G_KR_REQ;
break;
case ICE_FEC_RS:
/* Clear BASE-R bits, and AND RS ability
@@ -2860,7 +3033,7 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
*/
cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
- ICE_AQC_PHY_FEC_25G_RS_544_REQ;
+ ICE_AQC_PHY_FEC_25G_RS_544_REQ;
break;
case ICE_FEC_NONE:
/* Clear all FEC option bits. */
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 012d129df..c47114d16 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1148,7 +1148,6 @@ struct ice_tx_cmpltnq {
};
#pragma pack()
-
/* LAN Tx Completion Queue Context */
#pragma pack(1)
struct ice_tx_cmpltnq_ctx {
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 7/8] net/ice/base: clear and free XLT entries on reset
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (5 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 6/8] net/ice/base: split capability parse into separate functions Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 8/8] net/ice/base: update version Junfeng Guo
2020-07-10 4:05 ` [dpdk-dev] [PATCH v3 0/8] update base code batch 3 Zhang, Qi Z
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang
Cc: dev, stable, ferruh.yigit, junfeng.guo, Vignesh Sridhar,
Paul M Stillwell Jr
From: Qi Zhang <qi.z.zhang@intel.com>
This fix has been added to address memory leak issues resulting from
triggering a sudden driver reset which does not allow us to follow our
normal removal flows for SW XLT entries for advanced features.
- Adding call to destroy flow profile locks when clearing SW XLT tables.
- Extraction sequence entries were not correctly cleared previously
which could cause ownership conflicts for repeated reset-replay calls.
Fixes: 969890d505b1 ("net/ice/base: enable clearing of HW tables")
Cc: stable@dpdk.org
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 016dc2b39..284569464 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3666,6 +3666,8 @@ static void ice_free_flow_profs(struct ice_hw *hw, u8 blk_idx)
LIST_DEL(&p->l_entry);
if (p->acts)
ice_free(hw, p->acts);
+
+ ice_destroy_lock(&p->entries_lock);
ice_free(hw, p);
}
ice_release_lock(&hw->fl_profs_locks[blk_idx]);
@@ -3794,7 +3796,7 @@ void ice_clear_hw_tbls(struct ice_hw *hw)
prof_redir->count * sizeof(*prof_redir->t),
ICE_NONDMA_MEM);
- ice_memset(es->t, 0, es->count * sizeof(*es->t),
+ ice_memset(es->t, 0, es->count * sizeof(*es->t) * es->fvw,
ICE_NONDMA_MEM);
ice_memset(es->ref_count, 0, es->count * sizeof(*es->ref_count),
ICE_NONDMA_MEM);
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [dpdk-dev] [PATCH v3 8/8] net/ice/base: update version
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (6 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 7/8] net/ice/base: clear and free XLT entries on reset Junfeng Guo
@ 2020-07-10 2:14 ` Junfeng Guo
2020-07-10 4:05 ` [dpdk-dev] [PATCH v3 0/8] update base code batch 3 Zhang, Qi Z
8 siblings, 0 replies; 22+ messages in thread
From: Junfeng Guo @ 2020-07-10 2:14 UTC (permalink / raw)
To: qi.z.zhang, qiming.yang; +Cc: dev, stable, ferruh.yigit, junfeng.guo
From: Qi Zhang <qi.z.zhang@intel.com>
Update base code version in readme.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
drivers/net/ice/base/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README
index 726593971..1e9c854ae 100644
--- a/drivers/net/ice/base/README
+++ b/drivers/net/ice/base/README
@@ -6,7 +6,7 @@ Intel® ICE driver
==================
This directory contains source code of FreeBSD ice driver of version
-2020.03.26 released by the team which develops
+2020.06.17 released by the team which develops
basic drivers for any ice NIC. The directory of base/ contains the
original source package.
This driver is valid for the product(s) listed below
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [dpdk-dev] [PATCH v3 0/8] update base code batch 3
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
` (7 preceding siblings ...)
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 8/8] net/ice/base: update version Junfeng Guo
@ 2020-07-10 4:05 ` Zhang, Qi Z
8 siblings, 0 replies; 22+ messages in thread
From: Zhang, Qi Z @ 2020-07-10 4:05 UTC (permalink / raw)
To: Guo, Junfeng, Yang, Qiming; +Cc: dev, stable, Yigit, Ferruh
> -----Original Message-----
> From: Guo, Junfeng <junfeng.guo@intel.com>
> Sent: Friday, July 10, 2020 10:14 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming <qiming.yang@intel.com>
> Cc: dev@dpdk.org; stable@dpdk.org; Yigit, Ferruh <ferruh.yigit@intel.com>;
> Guo, Junfeng <junfeng.guo@intel.com>
> Subject: [PATCH v3 0/8] update base code batch 3
>
> The patchset include couple bug fixes and code clean also update the version
> number.
>
> v3:
> - adjust code position in ice_rem_rss_cfg_sync in PATCH 1/8
> - remove uncessary printf and cleanup code style in PATCH 1/8
>
> v2:
> - add missing part in ice_rem_rss_cfg_sync in PATCH 1/8
> - remove unnessary change in PATCH 1/8
>
> Qi Zhang (8):
> net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist
> net/ice/base: cleanup some code style
> net/ice/base: move LLDP function to common module
> net/ice/base: clean code in flow director module
> net/ice/base: add capability list AQ function
> net/ice/base: split capability parse into separate functions
> net/ice/base: clear and free XLT entries on reset
> net/ice/base: update version
>
> drivers/net/ice/base/README | 2 +-
> drivers/net/ice/base/ice_adminq_cmd.h | 6 +-
> drivers/net/ice/base/ice_common.c | 588 ++++++++++++++++++--------
> drivers/net/ice/base/ice_common.h | 3 +
> drivers/net/ice/base/ice_dcb.c | 33 --
> drivers/net/ice/base/ice_dcb.h | 3 -
> drivers/net/ice/base/ice_fdir.c | 23 +-
> drivers/net/ice/base/ice_fdir.h | 3 -
> drivers/net/ice/base/ice_flex_pipe.c | 4 +-
> drivers/net/ice/base/ice_flow.c | 22 +-
> drivers/net/ice/base/ice_lan_tx_rx.h | 1 -
> drivers/net/ice/base/ice_sched.c | 3 +-
> 12 files changed, 444 insertions(+), 247 deletions(-)
>
> --
> 2.25.1
Since the patch set already be merged,
overwrite v2 by v3 on the only modified PATCH 1/8 in dpdk-next-net-intel
Thanks
Qi
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-07-10 4:06 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-01 5:49 [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 2/8] net/ice/base: cleanup some code style Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 3/8] net/ice/base: move lldp function to common module Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 4/8] net/ice/base: code clean in FDIR module Qi Zhang
2020-07-02 4:20 ` Yang, Qiming
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 5/8] net/ice/base: add capability list AQ function Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 6/8] net/ice/base: split capability parse into separate functions Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 7/8] net/ice/base: clear and free XLT entries on reset Qi Zhang
2020-07-01 5:49 ` [dpdk-dev] [PATCH v2 8/8] net/ice/base: update version Qi Zhang
2020-07-02 4:22 ` [dpdk-dev] [PATCH v2 0/8] update base code batch 3 Yang, Qiming
2020-07-02 13:06 ` Zhang, Qi Z
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 " Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 1/8] net/ice/base: fix GTP-U inner RSS IPv4 IPv6 co-exist Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 2/8] net/ice/base: cleanup some code style Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 3/8] net/ice/base: move LLDP function to common module Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 4/8] net/ice/base: clean code in flow director module Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 5/8] net/ice/base: add capability list AQ function Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 6/8] net/ice/base: split capability parse into separate functions Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 7/8] net/ice/base: clear and free XLT entries on reset Junfeng Guo
2020-07-10 2:14 ` [dpdk-dev] [PATCH v3 8/8] net/ice/base: update version Junfeng Guo
2020-07-10 4:05 ` [dpdk-dev] [PATCH v3 0/8] update base code batch 3 Zhang, Qi Z
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