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From: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
To: "Van Haaren, Harry" <harry.van.haaren@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant
Date: Mon, 14 Sep 2020 10:39:02 +0000
Message-ID: <BN6PR18MB11400342EB595893F85732C4DE230@BN6PR18MB1140.namprd18.prod.outlook.com> (raw)
In-Reply-To: <BYAPR11MB3143B6143122A830F58345AFD7230@BYAPR11MB3143.namprd11.prod.outlook.com>

>> >This commit adds a new rte_prefetch0_write() variant, suggests to
>the
>> >compiler to use a prefetch instruction with intention to write. As a
>> >compiler builtin, the compiler can choose based on compilation
>target
>> >what the best implementation for this instruction is.
>>
>> Why not have the other variants too i.e. l2/l3/temporal store
>prefetches too?
>
>Hi Pavan,
>
Hi Harry,
(LTNS)

>Are there architectures that actually implement those? Usually for a WB
>mem store to complete,
>the data must be present in L1 cache (on x86 at least), and that's what
>the patch below with write0 achieves.

ARM64 does supports all modes of store prefetch
"
<type> is one of:
PLD Prefetch for load, encoded in the "Rt<4:3>" field as 0b00.
PLI Preload instructions, encoded in the "Rt<4:3>" field as 0b01.
PST Prefetch for store, encoded in the "Rt<4:3>" field as 0b10.
<target> is one of:
L1 Level 1 cache, encoded in the "Rt<2:1>" field as 0b00.
L2 Level 2 cache, encoded in the "Rt<2:1>" field as 0b01.
L3 Level 3 cache, encoded in the "Rt<2:1>" field as 0b10.
<policy> is one of:
KEEP Retained or temporal prefetch, allocated in the cache normally. Encoded in the "Rt<0>"
field as 0.
STRM Streaming or non-temporal prefetch, for data that is used only once. Encoded in the
"Rt<0>" field as 1.
For more information on these prefetch
"

>
>I'm against adding all the variants "just in case", it leads to API bloat,
>and increases
>cognitive load on the programmer. My expectation is that in 99% of
>usage the prefetch
>write instruction should target L1.
>

There is a use case when cache mode is write through and application is 
pipelining work across cores sharing same L2 cluster.

>Cheers, -Harry

Regards,
Pavan.

>
>> >Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
>> >
>> >---
>> >
>> >The integer constants passed to the builtin are not available as
>> >a #define value, and doing #defines just for this write variant
>> >does not seems a nice solution to me... particularly for those using
>> >IDEs where any #define value is auto-hinted for code-completion.
>> >
>> >---
>> > lib/librte_eal/include/generic/rte_prefetch.h | 16
>++++++++++++++++
>> > 1 file changed, 16 insertions(+)
>
><snip patch contents>


  reply	other threads:[~2020-09-14 10:39 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  9:19 Harry van Haaren
2020-09-13 20:11 ` Pavan Nikhilesh Bhagavatula
2020-09-14  8:12   ` Van Haaren, Harry
2020-09-14 10:39     ` Pavan Nikhilesh Bhagavatula [this message]
2020-09-14 15:10       ` Van Haaren, Harry
2020-09-14 15:10 ` [dpdk-dev] [PATCH v2] eal: add new prefetch write variants Harry van Haaren
2020-10-08  7:42   ` David Marchand
2020-10-08  8:34     ` Van Haaren, Harry
2020-10-08  8:39       ` Van Haaren, Harry
2020-10-08  8:54   ` Jerin Jacob
2020-10-10 10:21   ` Ruifeng Wang
2020-10-15  8:18   ` David Marchand
2020-10-15  8:44     ` Van Haaren, Harry
2020-10-15 10:32   ` [dpdk-dev] [PATCH v3] " Harry van Haaren
2020-10-15 20:27     ` David Marchand

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