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From: "Xueming(Steven) Li" <xuemingl@nvidia.com>
To: 谢华伟(此时此刻) <huawei.xhw@alibaba-inc.com>,
	Maxime Coquelin <maxime.coquelin@redhat.com>,
	"ferruh.yigit@intel.com" <ferruh.yigit@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	"anatoly.burakov@intel.com" <anatoly.burakov@intel.com>,
	"david.marchand@redhat.com" <david.marchand@redhat.com>,
	"zhihong.wang@intel.com" <zhihong.wang@intel.com>,
	"chenbo.xia@intel.com" <chenbo.xia@intel.com>,
	"grive@u256.net" <grive@u256.net>
Subject: Re: [dpdk-dev] [PATCH v5 1/3] PCI: use PCI standard sysfs entry to get PIO address
Date: Sun, 24 Jan 2021 15:10:45 +0000
Message-ID: <BY5PR12MB4324D97742461E9AE0738F98A1BE9@BY5PR12MB4324.namprd12.prod.outlook.com> (raw)
In-Reply-To: <c7abe265-d5e2-a507-97ce-00987e1305d4@alibaba-inc.com>

Hi Huawei,

>-----Original Message-----
>From: dev <dev-bounces@dpdk.org> On Behalf Of 谢华伟(此时此刻)
>Sent: Friday, January 15, 2021 2:24 AM
>To: Maxime Coquelin <maxime.coquelin@redhat.com>;
>ferruh.yigit@intel.com
>Cc: dev@dpdk.org; anatoly.burakov@intel.com;
>david.marchand@redhat.com; zhihong.wang@intel.com;
>chenbo.xia@intel.com; grive@u256.net
>Subject: Re: [dpdk-dev] [PATCH v5 1/3] PCI: use PCI standard sysfs entry to get
>PIO address
>
>
>On 2021/1/12 16:07, Maxime Coquelin wrote:
>> Hi Huawei,
>>
>> The title should be under the form:
>> "bus/pci: use PCI standard sysfs entry to get PIO address"
>>
>> On 10/22/20 5:51 PM, 谢华伟(此时此刻) wrote:
>>> From: "huawei.xhw" <huawei.xhw@alibaba-inc.com>
>>>
>>> Previously with igb_uio we get PIO address from igb_uio sysfs entry,
>>> with uio_pci_generic, we get PIO address from /proc/ioports.

It will be great to explain a little bit more what this patch is trying to do.

>>>
>>> Signed-off-by: huawei.xhw <huawei.xhw@alibaba-inc.com>
>> In order to comply with the contribution rules, your name must be
>> disaplyed under the form:
>>
>> Signed-off-by: Firstname Lastname <huawei.xhw@alibaba-inc.com>
>Would fix this.
>>> ---
>>>   drivers/bus/pci/linux/pci.c     | 77 -----------------------------------------
>>>   drivers/bus/pci/linux/pci_uio.c | 64 ++++++++++++++++++++++++----------
>>>   2 files changed, 46 insertions(+), 95 deletions(-)
>>>
>>> diff --git a/drivers/bus/pci/linux/pci.c
>>> b/drivers/bus/pci/linux/pci.c index 2e1808b..0f38abf 100644
>>> --- a/drivers/bus/pci/linux/pci.c
>>> +++ b/drivers/bus/pci/linux/pci.c
>>> @@ -677,71 +677,6 @@ int rte_pci_write_config(const struct
>rte_pci_device *device,
>>>   	}
>>>   }
>>>
>>> -#if defined(RTE_ARCH_X86)
>>> -static int
>>> -pci_ioport_map(struct rte_pci_device *dev, int bar __rte_unused,
>>> -		struct rte_pci_ioport *p)
>>> -{
>>> -	uint16_t start, end;
>>> -	FILE *fp;
>>> -	char *line = NULL;
>>> -	char pci_id[16];
>>> -	int found = 0;
>>> -	size_t linesz;
>>> -
>>> -	if (rte_eal_iopl_init() != 0) {
>>> -		RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for
>PCI device %s\n",
>>> -			__func__, dev->name);
>>> -		return -1;
>>> -	}
>>> -
>>> -	snprintf(pci_id, sizeof(pci_id), PCI_PRI_FMT,
>>> -		 dev->addr.domain, dev->addr.bus,
>>> -		 dev->addr.devid, dev->addr.function);
>>> -
>>> -	fp = fopen("/proc/ioports", "r");
>>> -	if (fp == NULL) {
>>> -		RTE_LOG(ERR, EAL, "%s(): can't open ioports\n", __func__);
>>> -		return -1;
>>> -	}
>>> -
>>> -	while (getdelim(&line, &linesz, '\n', fp) > 0) {
>>> -		char *ptr = line;
>>> -		char *left;
>>> -		int n;
>>> -
>>> -		n = strcspn(ptr, ":");
>>> -		ptr[n] = 0;
>>> -		left = &ptr[n + 1];
>>> -
>>> -		while (*left && isspace(*left))
>>> -			left++;
>>> -
>>> -		if (!strncmp(left, pci_id, strlen(pci_id))) {
>>> -			found = 1;
>>> -
>>> -			while (*ptr && isspace(*ptr))
>>> -				ptr++;
>>> -
>>> -			sscanf(ptr, "%04hx-%04hx", &start, &end);
>>> -
>>> -			break;
>>> -		}
>>> -	}
>>> -
>>> -	free(line);
>>> -	fclose(fp);
>>> -
>>> -	if (!found)
>>> -		return -1;
>>> -
>>> -	p->base = start;
>>> -	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%x\n", start);
>>> -
>>> -	return 0;
>>> -}
>>> -#endif
>>> -
>>>   int
>>>   rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
>>>   		struct rte_pci_ioport *p)
>>> @@ -756,14 +691,8 @@ int rte_pci_write_config(const struct
>rte_pci_device *device,
>>>   		break;
>>>   #endif
>>>   	case RTE_PCI_KDRV_IGB_UIO:
>>> -		ret = pci_uio_ioport_map(dev, bar, p);
>>> -		break;
>>>   	case RTE_PCI_KDRV_UIO_GENERIC:
>>> -#if defined(RTE_ARCH_X86)
>>> -		ret = pci_ioport_map(dev, bar, p);
>>> -#else
>>>   		ret = pci_uio_ioport_map(dev, bar, p); -#endif
>>>   		break;
>>>   	default:
>>>   		break;
>>> @@ -830,14 +759,8 @@ int rte_pci_write_config(const struct
>rte_pci_device *device,
>>>   		break;
>>>   #endif
>>>   	case RTE_PCI_KDRV_IGB_UIO:
>>> -		ret = pci_uio_ioport_unmap(p);
>>> -		break;
>>>   	case RTE_PCI_KDRV_UIO_GENERIC:
>>> -#if defined(RTE_ARCH_X86)
>>> -		ret = 0;
>>> -#else
>>>   		ret = pci_uio_ioport_unmap(p);
>>> -#endif
>>>   		break;
>>>   	default:
>>>   		break;
>>> diff --git a/drivers/bus/pci/linux/pci_uio.c
>>> b/drivers/bus/pci/linux/pci_uio.c index f3305a2..01f2a40 100644
>>> --- a/drivers/bus/pci/linux/pci_uio.c
>>> +++ b/drivers/bus/pci/linux/pci_uio.c
>>> @@ -373,10 +373,13 @@
>>>   pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
>>>   		   struct rte_pci_ioport *p)
>>>   {
>>> +	FILE *f = NULL;
>>>   	char dirname[PATH_MAX];
>>>   	char filename[PATH_MAX];
>>> -	int uio_num;
>>> -	unsigned long start;
>>> +	char buf[BUFSIZ];
>>> +	uint64_t phys_addr, end_addr, flags;
>>> +	unsigned long base;
>>> +	int i;
>>>
>>>   	if (rte_eal_iopl_init() != 0) {
>>>   		RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for
>PCI
>>> device %s\n", @@ -384,41 +387,66 @@
>>>   		return -1;
>>>   	}
>>>
>>> -	uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0);
>>> -	if (uio_num < 0)
>>> +	/* open and read addresses of the corresponding resource in sysfs */
>>> +	snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource",
>>> +		rte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus,
>>> +		dev->addr.devid, dev->addr.function);
>>> +	f = fopen(filename, "r");
>>> +	if (f == NULL) {
>>> +		RTE_LOG(ERR, EAL, "%s(): Cannot open sysfs resource: %s\n",
>>> +			__func__, strerror(errno));
>>>   		return -1;
>>> +	}
>>>
>>> -	/* get portio start */
>>> -	snprintf(filename, sizeof(filename),
>>> -		 "%s/portio/port%d/start", dirname, bar);
>>> -	if (eal_parse_sysfs_value(filename, &start) < 0) {
>>> -		RTE_LOG(ERR, EAL, "%s(): cannot parse portio start\n",
>>> -			__func__);
>>> -		return -1;
>>> +	for (i = 0; i < bar + 1; i++) {
>>> +		if (fgets(buf, sizeof(buf), f) == NULL) {
>>> +			RTE_LOG(ERR, EAL, "%s(): Cannot read sysfs
>resource\n", __func__);
>>> +			goto error;
>>> +		}
>>>   	}
>>> -	/* ensure we don't get anything funny here, read/write will cast to
>>> -	 * uin16_t */
>>> -	if (start > UINT16_MAX)
>>> -		return -1;
>>> +	if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr,
>>> +		&end_addr, &flags) < 0)
>>> +		goto error;
>>> +
>>> +	if (!(flags & IORESOURCE_IO)) {
>>> +		RTE_LOG(ERR, EAL, "%s(): bar resource other than IO is not
>supported\n", __func__);
>>> +		goto error;
>>> +	}
>>> +	base = (unsigned long)phys_addr;
>>> +	RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", __func__,
>>> +base);

Are you sure INFO level is required? BTW, there is a same log below.

>>> +
>>> +	if (base > UINT16_MAX)
>>> +		goto error;
>>>
>>>   	/* FIXME only for primary process ? */
>>>   	if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) {
>>> +		int uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname),
>0);
>>> +		if (uio_num < 0) {
>>> +			RTE_LOG(ERR, EAL, "cannot open %s: %s\n",
>>> +				dirname, strerror(errno));
>>> +			goto error;
>>> +		}
>>>
>>>   		snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num);
>>>   		dev->intr_handle.fd = open(filename, O_RDWR);
>>>   		if (dev->intr_handle.fd < 0) {
>>>   			RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
>>>   				filename, strerror(errno));
>>> -			return -1;
>>> +			goto error;
>>>   		}
>>>   		dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
>>>   	}
>>>
>>> -	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", start);
>>> +	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", base);
>>>
>>> -	p->base = start;
>>> +	p->base = base;
>>>   	p->len = 0;
>>> +	fclose(f);
>>>   	return 0;
>>> +error:
>>> +	if (f)
>>> +		fclose(f);
>>> +	return -1;
>>>   }
>>>   #else
>>>   int
>>>
>> I think it makes sense to have a common way for both igb_uio and
>> uio_pci_generic to get the PIO base address.
>>
>> With commit message and title fixed, feel free to add my:
>>
>> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
>Thanks Maxime.
>>
>> Thanks,
>> Maxime

Thanks,
Xueming

  reply	other threads:[~2021-01-24 15:10 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-30 14:59 [dpdk-dev] [PATCH v2] pci: support both PIO and MMIO BAR for legacy virtio on x86 谢华伟(此时此刻)
2020-10-01 10:22 ` Burakov, Anatoly
2020-10-02  5:44   ` 谢华伟(此时此刻)
2020-10-09  8:36 ` [dpdk-dev] [PATCH v3] " 谢华伟(此时此刻)
2020-10-13  8:41 ` [dpdk-dev] [PATCH v4] support both PIO and MMIO bar for virtio pci device 谢华伟(此时此刻)
2020-10-13  8:41   ` [dpdk-dev] [PATCH v4] pci: support both PIO and MMIO BAR for legacy virtio on x86 谢华伟(此时此刻)
2020-10-13 12:34     ` 谢华伟(此时此刻)
2020-10-21  8:46     ` 谢华伟(此时此刻)
2020-10-21 11:49     ` Ferruh Yigit
2020-10-21 12:32       ` 谢华伟(此时此刻)
2020-10-21 17:24         ` Ferruh Yigit
2020-10-22  9:15           ` 谢华伟(此时此刻)
2020-10-22  9:44             ` Ferruh Yigit
2020-10-22  9:57               ` 谢华伟(此时此刻)
2020-10-22 15:51 ` [dpdk-dev] [PATCH v5 0/3] support both PIO and MMIO BAR for virtio PMD 谢华伟(此时此刻)
2020-10-22 15:51   ` [dpdk-dev] [PATCH v5 1/3] PCI: use PCI standard sysfs entry to get PIO address 谢华伟(此时此刻)
2021-01-12  8:07     ` Maxime Coquelin
2021-01-14 18:23       ` 谢华伟(此时此刻)
2021-01-24 15:10         ` Xueming(Steven) Li [this message]
2020-10-22 15:51   ` [dpdk-dev] [PATCH v5 2/3] PCI: support MMIO in rte_pci_ioport_map/unap/read/write 谢华伟(此时此刻)
2021-01-12  8:23     ` Maxime Coquelin
2021-01-21  6:30       ` 谢华伟(此时此刻)
2021-01-24 15:22     ` Xueming(Steven) Li
2021-01-25  3:08       ` 谢华伟(此时此刻)
2021-01-27 10:40     ` Ferruh Yigit
2021-01-27 15:34       ` 谢华伟(此时此刻)
2021-01-27 16:45         ` Ferruh Yigit
2020-10-22 15:51   ` [dpdk-dev] [PATCH v5 3/3] PCI: don't use vfio ioctl call to access PIO resource 谢华伟(此时此刻)
2021-01-12  9:37     ` Maxime Coquelin
2021-01-12 16:58       ` Maxime Coquelin
2021-01-20 14:54         ` 谢华伟(此时此刻)
2021-01-21  8:29           ` Maxime Coquelin
2021-01-21 14:57             ` 谢华伟(此时此刻)
2021-01-21 15:00               ` 谢华伟(此时此刻)
2021-01-21 15:38               ` Maxime Coquelin
2021-01-22  7:25                 ` 谢华伟(此时此刻)
2021-01-26 10:44                   ` Maxime Coquelin
2021-01-27 10:32                     ` Ferruh Yigit
2021-01-27 12:17                       ` Maxime Coquelin
2021-01-27 14:43                       ` 谢华伟(此时此刻)
2021-01-27 16:45                         ` Ferruh Yigit
2021-01-28 13:43                           ` 谢华伟(此时此刻)
2021-01-26 12:30                   ` 谢华伟(此时此刻)
2021-01-26 12:35                     ` Maxime Coquelin
2021-01-26 14:24                       ` 谢华伟(此时此刻)
2020-10-27  8:50   ` [dpdk-dev] [PATCH v5 0/3] support both PIO and MMIO BAR for virtio PMD 谢华伟(此时此刻)
2020-10-28  3:48     ` 谢华伟(此时此刻)
2020-11-02 11:56   ` 谢华伟(此时此刻)
2020-11-10 12:35   ` 谢华伟(此时此刻)
2020-11-10 12:42     ` David Marchand
2020-11-12 13:35       ` 谢华伟(此时此刻)
2020-12-14 14:24       ` 谢华伟(此时此刻)
2020-12-16  7:54         ` Maxime Coquelin
2021-01-12 17:37   ` Maxime Coquelin
2021-01-14 18:19     ` 谢华伟(此时此刻)
2021-01-21  4:12     ` 谢华伟(此时此刻)
2021-01-21  8:47       ` Maxime Coquelin
2021-01-21 13:51         ` 谢华伟(此时此刻)

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